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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
*
* Author: Sebastian Hesselbarth <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
#define V(f6180, f6190, f6192, f6281, f6282, dx4122, dx1135) \
((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
(f6281 << 3) | (f6282 << 4) | (dx4122 << 5) | \
(dx1135 << 6))
enum kirkwood_variant {
VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
};
static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1, 1))),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1, 1))),
MPP_MODE(2,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1, 1))),
MPP_MODE(3,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1, 1))),
MPP_MODE(4,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0))),
MPP_MODE(5,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(6,
MPP_VAR_FUNCTION(0x1, "sysrst", "out", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0))),
MPP_MODE(7,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(8,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0, 0))),
MPP_MODE(9,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0, 0))),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0, 0))),
MPP_MODE(11,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0))),
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(14,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0, 0))),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(16,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0, 0))),
MPP_MODE(17,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(18,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(19,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1, 1))),
MPP_MODE(20,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 0, 0, 0, 0, 0, 0))),
MPP_MODE(21,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(22,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(23,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(24,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(25,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(26,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(27,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(28,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "nand", "ren", V(0, 0, 0, 0, 0, 0, 1))),
MPP_MODE(29,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "nand", "wen", V(0, 0, 0, 0, 0, 0, 1))),
MPP_MODE(30,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(31,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(32,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(33,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0, 1)),
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(34,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "nand", "ale", V(0, 0, 0, 0, 0, 0, 1))),
MPP_MODE(35,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 1, 1, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "nand", "cen", V(0, 0, 0, 0, 0, 0, 1))),
MPP_MODE(36,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(37,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(38,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(39,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(40,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(41,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(42,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(43,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(44,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(45,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(46,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(47,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(48,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0, 0))),
MPP_MODE(49,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1, 1)),
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0, 0)),
MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0, 0)),
MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0, 0))),
};
static const struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
MPP_FUNC_CTRL(0, 44, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 20),
MPP_GPIO_RANGE(1, 35, 35, 10),
};
static const struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
MPP_FUNC_CTRL(0, 35, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 4),
};
static const struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
MPP_FUNC_CTRL(0, 49, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 18),
};
static struct mvebu_pinctrl_soc_info mv88f6180_info = {
.variant = VARIANT_MV88F6180,
.controls = mv88f6180_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f6180_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f6190_info = {
.variant = VARIANT_MV88F6190,
.controls = mv88f619x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f619x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f6192_info = {
.variant = VARIANT_MV88F6192,
.controls = mv88f619x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f619x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f6281_info = {
.variant = VARIANT_MV88F6281,
.controls = mv88f628x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f628x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f6282_info = {
.variant = VARIANT_MV88F6282,
.controls = mv88f628x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f628x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv98dx4122_info = {
.variant = VARIANT_MV98DX4122,
.controls = mv88f628x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f628x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv98dx1135_info = {
.variant = VARIANT_MV98DX1135,
.controls = mv88f628x_mpp_controls,
.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
.modes = mv88f6xxx_mpp_modes,
.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
.gpioranges = mv88f628x_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
};
static const struct of_device_id kirkwood_pinctrl_of_match[] = {
{ .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
{ .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
{ .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
{ .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
{ .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
{ .compatible = "marvell,98dx4122-pinctrl", .data = &mv98dx4122_info },
{ .compatible = "marvell,98dx1135-pinctrl", .data = &mv98dx1135_info },
{ }
};
static int kirkwood_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
pdev->dev.platform_data = (void *)match->data;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver kirkwood_pinctrl_driver = {
.driver = {
.name = "kirkwood-pinctrl",
.of_match_table = kirkwood_pinctrl_of_match,
},
.probe = kirkwood_pinctrl_probe,
};
builtin_platform_driver(kirkwood_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-kirkwood.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada 380/385 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2013 Marvell
*
* Thomas Petazzoni <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
enum {
V_88F6810 = BIT(0),
V_88F6820 = BIT(1),
V_88F6828 = BIT(2),
V_88F6810_PLUS = (V_88F6810 | V_88F6820 | V_88F6828),
V_88F6820_PLUS = (V_88F6820 | V_88F6828),
};
static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6810_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6810_PLUS)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6810_PLUS)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6810_PLUS)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge", "mdc", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge", "mdio", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txclkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge0", "crs", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6810_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6810_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6810_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6810_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6810_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6810_PLUS)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "trig", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(20,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(21,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6810_PLUS)),
MPP_MODE(23,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6810_PLUS)),
MPP_MODE(24,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6810_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6810_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6810_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txclkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6810_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6810_PLUS)),
MPP_MODE(29,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6810_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6810_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6810_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6810_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6810_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "trig", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6810_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6810_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6810_PLUS)),
MPP_MODE(41,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6810_PLUS)),
MPP_MODE(43,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
MPP_MODE(50,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)),
MPP_MODE(52,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "clk", V_88F6810_PLUS)),
MPP_MODE(53,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "evreq", V_88F6810_PLUS)),
MPP_MODE(54,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
MPP_MODE(59,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)),
};
static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info;
static const struct of_device_id armada_38x_pinctrl_of_match[] = {
{
.compatible = "marvell,mv88f6810-pinctrl",
.data = (void *) V_88F6810,
},
{
.compatible = "marvell,mv88f6820-pinctrl",
.data = (void *) V_88F6820,
},
{
.compatible = "marvell,mv88f6828-pinctrl",
.data = (void *) V_88F6828,
},
{ },
};
static const struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {
MPP_FUNC_CTRL(0, 59, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 28),
};
static int armada_38x_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_38x_pinctrl_of_match, &pdev->dev);
if (!match)
return -ENODEV;
soc->variant = (unsigned) match->data & 0xff;
soc->controls = armada_38x_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls);
soc->gpioranges = armada_38x_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(armada_38x_mpp_gpio_ranges);
soc->modes = armada_38x_mpp_modes;
soc->nmodes = armada_38x_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver armada_38x_pinctrl_driver = {
.driver = {
.name = "armada-38x-pinctrl",
.of_match_table = of_match_ptr(armada_38x_pinctrl_of_match),
},
.probe = armada_38x_pinctrl_probe,
};
builtin_platform_driver(armada_38x_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-38x.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada 39x pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
enum {
V_88F6920 = BIT(0),
V_88F6925 = BIT(1),
V_88F6928 = BIT(2),
V_88F6920_PLUS = (V_88F6920 | V_88F6925 | V_88F6928),
V_88F6925_PLUS = (V_88F6925 | V_88F6928),
};
static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6920_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6920_PLUS)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6920_PLUS)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6920_PLUS)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "xsmi", "mdio", V_88F6920_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "xsmi", "mdc", V_88F6920_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ptp", "trig", V_88F6920_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ptp", "clk", V_88F6920_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ptp", "evreq", V_88F6920_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)),
MPP_MODE(20,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
MPP_MODE(21,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6920_PLUS)),
MPP_MODE(23,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6920_PLUS)),
MPP_MODE(24,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6920_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)),
MPP_MODE(29,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6920_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)),
MPP_MODE(41,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6920_PLUS)),
MPP_MODE(43,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6920_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6928),
MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
MPP_MODE(50,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928),
MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)),
MPP_MODE(52,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928),
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),
MPP_MODE(53,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6928),
MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928),
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)),
MPP_MODE(54,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6925_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS),
MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6920_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
MPP_MODE(59,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6920_PLUS)),
};
static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
static const struct of_device_id armada_39x_pinctrl_of_match[] = {
{
.compatible = "marvell,mv88f6920-pinctrl",
.data = (void *) V_88F6920,
},
{
.compatible = "marvell,mv88f6925-pinctrl",
.data = (void *) V_88F6925,
},
{
.compatible = "marvell,mv88f6928-pinctrl",
.data = (void *) V_88F6928,
},
{ },
};
static const struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {
MPP_FUNC_CTRL(0, 59, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 28),
};
static int armada_39x_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_39x_pinctrl_of_match, &pdev->dev);
if (!match)
return -ENODEV;
soc->variant = (unsigned) match->data & 0xff;
soc->controls = armada_39x_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls);
soc->gpioranges = armada_39x_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(armada_39x_mpp_gpio_ranges);
soc->modes = armada_39x_mpp_modes;
soc->nmodes = armada_39x_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver armada_39x_pinctrl_driver = {
.driver = {
.name = "armada-39x-pinctrl",
.of_match_table = of_match_ptr(armada_39x_pinctrl_of_match),
},
.probe = armada_39x_pinctrl_probe,
};
builtin_platform_driver(armada_39x_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-39x.c
|
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2016-2018 Nuvoton Technology corporation.
// Copyright (c) 2016, Dell Inc
// Copyright (c) 2021-2022 Jonathan Neuschäfer
//
// This driver uses the following registers:
// - Pin mux registers, in the GCR (general control registers) block
// - GPIO registers, specific to each GPIO bank
// - GPIO event (interrupt) registers, located centrally in the GPIO register
// block, shared between all GPIO banks
#include <linux/device.h>
#include <linux/fwnode.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
/* GCR registers */
#define WPCM450_GCR_MFSEL1 0x0c
#define WPCM450_GCR_MFSEL2 0x10
#define WPCM450_GCR_NONE 0
/* GPIO event (interrupt) registers */
#define WPCM450_GPEVTYPE 0x00
#define WPCM450_GPEVPOL 0x04
#define WPCM450_GPEVDBNC 0x08
#define WPCM450_GPEVEN 0x0c
#define WPCM450_GPEVST 0x10
#define WPCM450_NUM_BANKS 8
#define WPCM450_NUM_GPIOS 128
#define WPCM450_NUM_GPIO_IRQS 4
struct wpcm450_pinctrl;
struct wpcm450_bank;
struct wpcm450_gpio {
struct gpio_chip gc;
struct wpcm450_pinctrl *pctrl;
const struct wpcm450_bank *bank;
};
struct wpcm450_pinctrl {
struct pinctrl_dev *pctldev;
struct device *dev;
struct irq_domain *domain;
struct regmap *gcr_regmap;
void __iomem *gpio_base;
struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS];
unsigned long both_edges;
/*
* This spin lock protects registers and struct wpcm450_pinctrl fields
* against concurrent access.
*/
raw_spinlock_t lock;
};
struct wpcm450_bank {
/* Range of GPIOs in this port */
u8 base;
u8 length;
/* Register offsets (0 = register doesn't exist in this port) */
u8 cfg0, cfg1, cfg2;
u8 blink;
u8 dataout, datain;
/* Interrupt bit mapping */
u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */
u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */
u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */
};
static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = {
/* range cfg0 cfg1 cfg2 blink out in IRQ map */
{ 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 },
{ 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 },
{ 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 },
{ 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 },
{ 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 },
{ 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 },
{ 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 },
{ 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 },
};
static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d)
{
const struct wpcm450_bank *bank = gpio->bank;
int hwirq = irqd_to_hwirq(d);
if (hwirq < bank->first_irq_gpio)
return -EINVAL;
if (hwirq - bank->first_irq_gpio >= bank->num_irqs)
return -EINVAL;
return hwirq - bank->first_irq_gpio + bank->first_irq_bit;
}
static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum)
{
const struct wpcm450_bank *bank = gpio->bank;
if (bitnum < bank->first_irq_bit)
return -EINVAL;
if (bitnum - bank->first_irq_bit > bank->num_irqs)
return -EINVAL;
return bitnum - bank->first_irq_bit + bank->first_irq_gpio;
}
static void wpcm450_gpio_irq_ack(struct irq_data *d)
{
struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
unsigned long flags;
int bit;
bit = wpcm450_gpio_irq_bitnum(gpio, d);
if (bit < 0)
return;
raw_spin_lock_irqsave(&pctrl->lock, flags);
iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void wpcm450_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct wpcm450_gpio *gpio = gpiochip_get_data(gc);
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
unsigned long flags;
unsigned long even;
int bit;
bit = wpcm450_gpio_irq_bitnum(gpio, d);
if (bit < 0)
return;
raw_spin_lock_irqsave(&pctrl->lock, flags);
even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
__assign_bit(bit, &even, 0);
iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void wpcm450_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct wpcm450_gpio *gpio = gpiochip_get_data(gc);
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
unsigned long flags;
unsigned long even;
int bit;
bit = wpcm450_gpio_irq_bitnum(gpio, d);
if (bit < 0)
return;
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
raw_spin_lock_irqsave(&pctrl->lock, flags);
even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
__assign_bit(bit, &even, 1);
iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
/*
* This is an implementation of the gpio_chip->get() function, for use in
* wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided
* implementation there, because it would require taking gpio_chip->bgpio_lock,
* which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where
* a raw spin lock is held.
*/
static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset)
{
void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
unsigned long flags;
u32 level;
raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
level = !!(ioread32(reg) & BIT(offset));
raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
return level;
}
/*
* Since the GPIO controller does not support dual-edge triggered interrupts
* (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered
* interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the
* specified emulated dual-edge triggered interrupts, so that the next edge can
* be detected.
*/
static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all)
{
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
unsigned int bit;
for_each_set_bit(bit, &all, 32) {
int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
unsigned long evpol;
unsigned long flags;
int level;
do {
level = wpcm450_gpio_get(gpio, offset);
/* Switch event polarity to the opposite of the current level */
raw_spin_lock_irqsave(&pctrl->lock, flags);
evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
__assign_bit(bit, &evpol, !level);
iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
} while (wpcm450_gpio_get(gpio, offset) != level);
}
}
static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
unsigned long evtype, evpol;
unsigned long flags;
int ret = 0;
int bit;
bit = wpcm450_gpio_irq_bitnum(gpio, d);
if (bit < 0)
return bit;
irq_set_handler_locked(d, handle_level_irq);
raw_spin_lock_irqsave(&pctrl->lock, flags);
evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
__assign_bit(bit, &pctrl->both_edges, 0);
switch (flow_type) {
case IRQ_TYPE_LEVEL_LOW:
__assign_bit(bit, &evtype, 1);
__assign_bit(bit, &evpol, 0);
break;
case IRQ_TYPE_LEVEL_HIGH:
__assign_bit(bit, &evtype, 1);
__assign_bit(bit, &evpol, 1);
break;
case IRQ_TYPE_EDGE_FALLING:
__assign_bit(bit, &evtype, 0);
__assign_bit(bit, &evpol, 0);
break;
case IRQ_TYPE_EDGE_RISING:
__assign_bit(bit, &evtype, 0);
__assign_bit(bit, &evpol, 1);
break;
case IRQ_TYPE_EDGE_BOTH:
__assign_bit(bit, &evtype, 0);
__assign_bit(bit, &pctrl->both_edges, 1);
break;
default:
ret = -EINVAL;
}
iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
/* clear the event status for good measure */
iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
/* fix event polarity after clearing event status */
wpcm450_gpio_fix_evpol(gpio, BIT(bit));
return ret;
}
static const struct irq_chip wpcm450_gpio_irqchip = {
.name = "WPCM450-GPIO-IRQ",
.irq_ack = wpcm450_gpio_irq_ack,
.irq_unmask = wpcm450_gpio_irq_unmask,
.irq_mask = wpcm450_gpio_irq_mask,
.irq_set_type = wpcm450_gpio_set_irq_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
{
struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc));
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
unsigned long ours;
unsigned int bit;
ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;
raw_spin_lock_irqsave(&pctrl->lock, flags);
pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
pending &= ours;
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
if (pending & pctrl->both_edges)
wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
chained_irq_enter(chip, desc);
for_each_set_bit(bit, &pending, 32) {
int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
generic_handle_domain_irq(gpio->gc.irq.domain, offset);
}
chained_irq_exit(chip, desc);
}
static int smb0_pins[] = { 115, 114 };
static int smb1_pins[] = { 117, 116 };
static int smb2_pins[] = { 119, 118 };
static int smb3_pins[] = { 30, 31 };
static int smb4_pins[] = { 28, 29 };
static int smb5_pins[] = { 26, 27 };
static int scs1_pins[] = { 32 };
static int scs2_pins[] = { 33 };
static int scs3_pins[] = { 34 };
static int bsp_pins[] = { 41, 42 };
static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
static int r1err_pins[] = { 56 };
static int r1md_pins[] = { 57, 58 };
static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 };
static int r2err_pins[] = { 90 };
static int r2md_pins[] = { 91, 92 };
static int kbcc_pins[] = { 94, 93 };
static int clko_pins[] = { 96 };
static int smi_pins[] = { 97 };
static int uinc_pins[] = { 19 };
static int mben_pins[] = {};
static int gspi_pins[] = { 12, 13, 14, 15 };
static int sspi_pins[] = { 12, 13, 14, 15 };
static int xcs1_pins[] = { 35 };
static int xcs2_pins[] = { 36 };
static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 };
static int fi0_pins[] = { 64 };
static int fi1_pins[] = { 65 };
static int fi2_pins[] = { 66 };
static int fi3_pins[] = { 67 };
static int fi4_pins[] = { 68 };
static int fi5_pins[] = { 69 };
static int fi6_pins[] = { 70 };
static int fi7_pins[] = { 71 };
static int fi8_pins[] = { 72 };
static int fi9_pins[] = { 73 };
static int fi10_pins[] = { 74 };
static int fi11_pins[] = { 75 };
static int fi12_pins[] = { 76 };
static int fi13_pins[] = { 77 };
static int fi14_pins[] = { 78 };
static int fi15_pins[] = { 79 };
static int pwm0_pins[] = { 80 };
static int pwm1_pins[] = { 81 };
static int pwm2_pins[] = { 82 };
static int pwm3_pins[] = { 83 };
static int pwm4_pins[] = { 20 };
static int pwm5_pins[] = { 21 };
static int pwm6_pins[] = { 16 };
static int pwm7_pins[] = { 17 };
static int hg0_pins[] = { 20 };
static int hg1_pins[] = { 21 };
static int hg2_pins[] = { 22 };
static int hg3_pins[] = { 23 };
static int hg4_pins[] = { 24 };
static int hg5_pins[] = { 25 };
static int hg6_pins[] = { 59 };
static int hg7_pins[] = { 60 };
#define WPCM450_GRPS \
WPCM450_GRP(smb3), \
WPCM450_GRP(smb4), \
WPCM450_GRP(smb5), \
WPCM450_GRP(scs1), \
WPCM450_GRP(scs2), \
WPCM450_GRP(scs3), \
WPCM450_GRP(smb0), \
WPCM450_GRP(smb1), \
WPCM450_GRP(smb2), \
WPCM450_GRP(bsp), \
WPCM450_GRP(hsp1), \
WPCM450_GRP(hsp2), \
WPCM450_GRP(r1err), \
WPCM450_GRP(r1md), \
WPCM450_GRP(rmii2), \
WPCM450_GRP(r2err), \
WPCM450_GRP(r2md), \
WPCM450_GRP(kbcc), \
WPCM450_GRP(clko), \
WPCM450_GRP(smi), \
WPCM450_GRP(uinc), \
WPCM450_GRP(gspi), \
WPCM450_GRP(mben), \
WPCM450_GRP(xcs2), \
WPCM450_GRP(xcs1), \
WPCM450_GRP(sdio), \
WPCM450_GRP(sspi), \
WPCM450_GRP(fi0), \
WPCM450_GRP(fi1), \
WPCM450_GRP(fi2), \
WPCM450_GRP(fi3), \
WPCM450_GRP(fi4), \
WPCM450_GRP(fi5), \
WPCM450_GRP(fi6), \
WPCM450_GRP(fi7), \
WPCM450_GRP(fi8), \
WPCM450_GRP(fi9), \
WPCM450_GRP(fi10), \
WPCM450_GRP(fi11), \
WPCM450_GRP(fi12), \
WPCM450_GRP(fi13), \
WPCM450_GRP(fi14), \
WPCM450_GRP(fi15), \
WPCM450_GRP(pwm0), \
WPCM450_GRP(pwm1), \
WPCM450_GRP(pwm2), \
WPCM450_GRP(pwm3), \
WPCM450_GRP(pwm4), \
WPCM450_GRP(pwm5), \
WPCM450_GRP(pwm6), \
WPCM450_GRP(pwm7), \
WPCM450_GRP(hg0), \
WPCM450_GRP(hg1), \
WPCM450_GRP(hg2), \
WPCM450_GRP(hg3), \
WPCM450_GRP(hg4), \
WPCM450_GRP(hg5), \
WPCM450_GRP(hg6), \
WPCM450_GRP(hg7), \
enum {
#define WPCM450_GRP(x) fn_ ## x
WPCM450_GRPS
/* add placeholder for none/gpio */
WPCM450_GRP(gpio),
WPCM450_GRP(none),
#undef WPCM450_GRP
};
static struct group_desc wpcm450_groups[] = {
#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
.num_pins = ARRAY_SIZE(x ## _pins) }
WPCM450_GRPS
#undef WPCM450_GRP
};
#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a)
#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b }
#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
.groups = nm ## _grp }
struct wpcm450_func {
const char *name;
const unsigned int ngroups;
const char *const *groups;
};
WPCM450_SFUNC(smb3);
WPCM450_SFUNC(smb4);
WPCM450_SFUNC(smb5);
WPCM450_SFUNC(scs1);
WPCM450_SFUNC(scs2);
WPCM450_SFUNC(scs3);
WPCM450_SFUNC(smb0);
WPCM450_SFUNC(smb1);
WPCM450_SFUNC(smb2);
WPCM450_SFUNC(bsp);
WPCM450_SFUNC(hsp1);
WPCM450_SFUNC(hsp2);
WPCM450_SFUNC(r1err);
WPCM450_SFUNC(r1md);
WPCM450_SFUNC(rmii2);
WPCM450_SFUNC(r2err);
WPCM450_SFUNC(r2md);
WPCM450_SFUNC(kbcc);
WPCM450_SFUNC(clko);
WPCM450_SFUNC(smi);
WPCM450_SFUNC(uinc);
WPCM450_SFUNC(gspi);
WPCM450_SFUNC(mben);
WPCM450_SFUNC(xcs2);
WPCM450_SFUNC(xcs1);
WPCM450_SFUNC(sdio);
WPCM450_SFUNC(sspi);
WPCM450_SFUNC(fi0);
WPCM450_SFUNC(fi1);
WPCM450_SFUNC(fi2);
WPCM450_SFUNC(fi3);
WPCM450_SFUNC(fi4);
WPCM450_SFUNC(fi5);
WPCM450_SFUNC(fi6);
WPCM450_SFUNC(fi7);
WPCM450_SFUNC(fi8);
WPCM450_SFUNC(fi9);
WPCM450_SFUNC(fi10);
WPCM450_SFUNC(fi11);
WPCM450_SFUNC(fi12);
WPCM450_SFUNC(fi13);
WPCM450_SFUNC(fi14);
WPCM450_SFUNC(fi15);
WPCM450_SFUNC(pwm0);
WPCM450_SFUNC(pwm1);
WPCM450_SFUNC(pwm2);
WPCM450_SFUNC(pwm3);
WPCM450_SFUNC(pwm4);
WPCM450_SFUNC(pwm5);
WPCM450_SFUNC(pwm6);
WPCM450_SFUNC(pwm7);
WPCM450_SFUNC(hg0);
WPCM450_SFUNC(hg1);
WPCM450_SFUNC(hg2);
WPCM450_SFUNC(hg3);
WPCM450_SFUNC(hg4);
WPCM450_SFUNC(hg5);
WPCM450_SFUNC(hg6);
WPCM450_SFUNC(hg7);
#define WPCM450_GRP(x) #x
WPCM450_FUNC(gpio, WPCM450_GRPS);
#undef WPCM450_GRP
/* Function names */
static struct wpcm450_func wpcm450_funcs[] = {
WPCM450_MKFUNC(smb3),
WPCM450_MKFUNC(smb4),
WPCM450_MKFUNC(smb5),
WPCM450_MKFUNC(scs1),
WPCM450_MKFUNC(scs2),
WPCM450_MKFUNC(scs3),
WPCM450_MKFUNC(smb0),
WPCM450_MKFUNC(smb1),
WPCM450_MKFUNC(smb2),
WPCM450_MKFUNC(bsp),
WPCM450_MKFUNC(hsp1),
WPCM450_MKFUNC(hsp2),
WPCM450_MKFUNC(r1err),
WPCM450_MKFUNC(r1md),
WPCM450_MKFUNC(rmii2),
WPCM450_MKFUNC(r2err),
WPCM450_MKFUNC(r2md),
WPCM450_MKFUNC(kbcc),
WPCM450_MKFUNC(clko),
WPCM450_MKFUNC(smi),
WPCM450_MKFUNC(uinc),
WPCM450_MKFUNC(gspi),
WPCM450_MKFUNC(mben),
WPCM450_MKFUNC(xcs2),
WPCM450_MKFUNC(xcs1),
WPCM450_MKFUNC(sdio),
WPCM450_MKFUNC(sspi),
WPCM450_MKFUNC(fi0),
WPCM450_MKFUNC(fi1),
WPCM450_MKFUNC(fi2),
WPCM450_MKFUNC(fi3),
WPCM450_MKFUNC(fi4),
WPCM450_MKFUNC(fi5),
WPCM450_MKFUNC(fi6),
WPCM450_MKFUNC(fi7),
WPCM450_MKFUNC(fi8),
WPCM450_MKFUNC(fi9),
WPCM450_MKFUNC(fi10),
WPCM450_MKFUNC(fi11),
WPCM450_MKFUNC(fi12),
WPCM450_MKFUNC(fi13),
WPCM450_MKFUNC(fi14),
WPCM450_MKFUNC(fi15),
WPCM450_MKFUNC(pwm0),
WPCM450_MKFUNC(pwm1),
WPCM450_MKFUNC(pwm2),
WPCM450_MKFUNC(pwm3),
WPCM450_MKFUNC(pwm4),
WPCM450_MKFUNC(pwm5),
WPCM450_MKFUNC(pwm6),
WPCM450_MKFUNC(pwm7),
WPCM450_MKFUNC(hg0),
WPCM450_MKFUNC(hg1),
WPCM450_MKFUNC(hg2),
WPCM450_MKFUNC(hg3),
WPCM450_MKFUNC(hg4),
WPCM450_MKFUNC(hg5),
WPCM450_MKFUNC(hg6),
WPCM450_MKFUNC(hg7),
WPCM450_MKFUNC(gpio),
};
#define WPCM450_PINCFG(a, b, c, d, e, f, g) \
[a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \
.fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g }
struct wpcm450_pincfg {
int fn0, reg0, bit0;
int fn1, reg1, bit1;
};
/* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */
#define INV BIT(5)
static const struct wpcm450_pincfg pincfg[] = {
/* PIN FUNCTION 1 FUNCTION 2 */
WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30),
WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31),
WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22),
WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23),
WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0),
WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20),
WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21),
WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0),
WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0),
WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0),
WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0),
WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0),
WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0),
WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0),
WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0),
WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0),
WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0),
WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0),
WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0),
WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0),
WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0),
WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0),
WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0),
WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0),
WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30),
WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0),
WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0),
WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0),
WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0),
WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0),
WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30),
WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0),
WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0),
WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0),
WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0),
WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0),
WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0),
WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0),
WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0),
WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0),
WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0),
WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0),
WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0),
WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0),
WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0),
WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0),
WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0),
WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0),
WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0),
WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0),
WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0),
WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0),
WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0),
WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0),
WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0),
WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0),
WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0),
WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0),
WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0),
WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0),
WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0),
WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0),
WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0),
WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0),
WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0),
WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0),
WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0),
WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */
WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */
};
#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n)
static const struct pinctrl_pin_desc wpcm450_pins[] = {
WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3),
WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7),
WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11),
WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15),
WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19),
WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23),
WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27),
WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31),
WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35),
WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39),
WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43),
WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47),
WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51),
WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55),
WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59),
WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63),
WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67),
WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71),
WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75),
WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79),
WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83),
WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87),
WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91),
WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95),
WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99),
WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103),
WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107),
WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111),
WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115),
WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119),
WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123),
WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
};
/* Helper function to update MFSEL field according to the selected function */
static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected)
{
bool value = (fn == fn_selected);
if (bit & INV) {
value = !value;
bit &= ~INV;
}
regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0);
}
/* Enable mode in pin group */
static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
int npins, int func)
{
const struct wpcm450_pincfg *cfg;
int i;
for (i = 0; i < npins; i++) {
cfg = &pincfg[pin[i]];
if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) {
if (cfg->reg0)
wpcm450_update_mfsel(gcr_regmap, cfg->reg0,
cfg->bit0, cfg->fn0, func);
if (cfg->reg1)
wpcm450_update_mfsel(gcr_regmap, cfg->reg1,
cfg->bit1, cfg->fn1, func);
}
}
}
static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(wpcm450_groups);
}
static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return wpcm450_groups[selector].name;
}
static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
*npins = wpcm450_groups[selector].num_pins;
*pins = wpcm450_groups[selector].pins;
return 0;
}
static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
u32 *num_maps)
{
return pinconf_generic_dt_node_to_map(pctldev, np_config,
map, num_maps,
PIN_MAP_TYPE_INVALID);
}
static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, u32 num_maps)
{
kfree(map);
}
static const struct pinctrl_ops wpcm450_pinctrl_ops = {
.get_groups_count = wpcm450_get_groups_count,
.get_group_name = wpcm450_get_group_name,
.get_group_pins = wpcm450_get_group_pins,
.dt_node_to_map = wpcm450_dt_node_to_map,
.dt_free_map = wpcm450_dt_free_map,
};
static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(wpcm450_funcs);
}
static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return wpcm450_funcs[function].name;
}
static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const ngroups)
{
*ngroups = wpcm450_funcs[function].ngroups;
*groups = wpcm450_funcs[function].groups;
return 0;
}
static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
wpcm450_groups[group].num_pins, function);
return 0;
}
static const struct pinmux_ops wpcm450_pinmux_ops = {
.get_functions_count = wpcm450_get_functions_count,
.get_function_name = wpcm450_get_function_name,
.get_function_groups = wpcm450_get_function_groups,
.set_mux = wpcm450_pinmux_set_mux,
};
static int debounce_bitnum(int gpio)
{
if (gpio >= 0 && gpio < 16)
return gpio;
return -EINVAL;
}
static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
int bit;
u32 reg;
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
bit = debounce_bitnum(pin);
if (bit < 0)
return bit;
raw_spin_lock_irqsave(&pctrl->lock, flags);
reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
*config = pinconf_to_config_packed(param, !!(reg & BIT(bit)));
return 0;
default:
return -ENOTSUPP;
}
}
static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
unsigned int pin, unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
unsigned long flags;
unsigned long reg;
int bit;
int arg;
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
bit = debounce_bitnum(pin);
if (bit < 0)
return bit;
arg = pinconf_to_config_argument(config);
raw_spin_lock_irqsave(&pctrl->lock, flags);
reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
__assign_bit(bit, ®, arg);
iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
default:
return -ENOTSUPP;
}
}
static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
int ret;
while (num_configs--) {
ret = wpcm450_config_set_one(pctrl, pin, *configs++);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops wpcm450_pinconf_ops = {
.is_generic = true,
.pin_config_get = wpcm450_config_get,
.pin_config_set = wpcm450_config_set,
};
static struct pinctrl_desc wpcm450_pinctrl_desc = {
.name = "wpcm450-pinctrl",
.pins = wpcm450_pins,
.npins = ARRAY_SIZE(wpcm450_pins),
.pctlops = &wpcm450_pinctrl_ops,
.pmxops = &wpcm450_pinmux_ops,
.confops = &wpcm450_pinconf_ops,
.owner = THIS_MODULE,
};
static int wpcm450_gpio_set_config(struct gpio_chip *chip,
unsigned int offset, unsigned long config)
{
struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
return wpcm450_config_set_one(gpio->pctrl, offset, config);
}
static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
const struct wpcm450_bank *bank = gpio->bank;
return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
0, bank->base, bank->length);
}
static int wpcm450_gpio_register(struct platform_device *pdev,
struct wpcm450_pinctrl *pctrl)
{
struct device *dev = &pdev->dev;
struct fwnode_handle *child;
int ret;
pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->gpio_base))
return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
"Resource fail for GPIO controller\n");
device_for_each_child_node(dev, child) {
void __iomem *dat = NULL;
void __iomem *set = NULL;
void __iomem *dirout = NULL;
unsigned long flags = 0;
const struct wpcm450_bank *bank;
struct wpcm450_gpio *gpio;
struct gpio_irq_chip *girq;
u32 reg;
int i;
if (!fwnode_property_read_bool(child, "gpio-controller"))
continue;
ret = fwnode_property_read_u32(child, "reg", ®);
if (ret < 0)
return ret;
gpio = &pctrl->gpio_bank[reg];
gpio->pctrl = pctrl;
if (reg >= WPCM450_NUM_BANKS)
return dev_err_probe(dev, -EINVAL,
"GPIO index %d out of range!\n", reg);
bank = &wpcm450_banks[reg];
gpio->bank = bank;
dat = pctrl->gpio_base + bank->datain;
if (bank->dataout) {
set = pctrl->gpio_base + bank->dataout;
dirout = pctrl->gpio_base + bank->cfg0;
} else {
flags = BGPIOF_NO_OUTPUT;
}
ret = bgpio_init(&gpio->gc, dev, 4,
dat, set, NULL, dirout, NULL, flags);
if (ret < 0)
return dev_err_probe(dev, ret, "GPIO initialization failed\n");
gpio->gc.ngpio = bank->length;
gpio->gc.set_config = wpcm450_gpio_set_config;
gpio->gc.fwnode = child;
gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
girq = &gpio->gc.irq;
gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip);
girq->parent_handler = wpcm450_gpio_irqhandler;
girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->num_parents = 0;
for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
int irq;
irq = fwnode_irq_get(child, i);
if (irq < 0)
break;
if (!irq)
continue;
girq->parents[i] = irq;
girq->num_parents++;
}
ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
if (ret)
return dev_err_probe(dev, ret, "Failed to add GPIO chip\n");
}
return 0;
}
static int wpcm450_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct wpcm450_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
raw_spin_lock_init(&pctrl->lock);
dev_set_drvdata(dev, pctrl);
pctrl->gcr_regmap =
syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
if (IS_ERR(pctrl->gcr_regmap))
return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
"Failed to find nuvoton,wpcm450-gcr\n");
pctrl->pctldev = devm_pinctrl_register(dev,
&wpcm450_pinctrl_desc, pctrl);
if (IS_ERR(pctrl->pctldev))
return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
"Failed to register pinctrl device\n");
ret = wpcm450_gpio_register(pdev, pctrl);
if (ret < 0)
return ret;
return 0;
}
static const struct of_device_id wpcm450_pinctrl_match[] = {
{ .compatible = "nuvoton,wpcm450-pinctrl" },
{ }
};
MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match);
static struct platform_driver wpcm450_pinctrl_driver = {
.probe = wpcm450_pinctrl_probe,
.driver = {
.name = "wpcm450-pinctrl",
.of_match_table = wpcm450_pinctrl_match,
},
};
module_platform_driver(wpcm450_pinctrl_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Jonathan Neuschäfer <[email protected]>");
MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver");
|
linux-master
|
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
|
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2016-2018 Nuvoton Technology corporation.
// Copyright (c) 2016, Dell Inc
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
/* GCR registers */
#define NPCM7XX_GCR_PDID 0x00
#define NPCM7XX_GCR_MFSEL1 0x0C
#define NPCM7XX_GCR_MFSEL2 0x10
#define NPCM7XX_GCR_MFSEL3 0x64
#define NPCM7XX_GCR_MFSEL4 0xb0
#define NPCM7XX_GCR_CPCTL 0xD0
#define NPCM7XX_GCR_CP2BST 0xD4
#define NPCM7XX_GCR_B2CPNT 0xD8
#define NPCM7XX_GCR_I2CSEGSEL 0xE0
#define NPCM7XX_GCR_I2CSEGCTL 0xE4
#define NPCM7XX_GCR_SRCNT 0x68
#define NPCM7XX_GCR_FLOCKR1 0x74
#define NPCM7XX_GCR_DSCNT 0x78
#define SRCNT_ESPI BIT(3)
/* GPIO registers */
#define NPCM7XX_GP_N_TLOCK1 0x00
#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
#define NPCM7XX_GP_N_POL 0x08 /* Polarity */
#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
#define NPCM7XX_GP_N_OTYP 0x14
#define NPCM7XX_GP_N_MP 0x18
#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
#define NPCM7XX_GP_N_OBL0 0x30
#define NPCM7XX_GP_N_OBL1 0x34
#define NPCM7XX_GP_N_OBL2 0x38
#define NPCM7XX_GP_N_OBL3 0x3c
#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
#define NPCM7XX_GP_N_SPLCK 0x50
#define NPCM7XX_GP_N_MPLCK 0x54
#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
#define NPCM7XX_GP_N_OSRC 0x5c
#define NPCM7XX_GP_N_ODSC 0x60
#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
#define NPCM7XX_GP_N_TLOCK2 0x7c
#define NPCM7XX_GPIO_PER_BANK 32
#define NPCM7XX_GPIO_BANK_NUM 8
#define NPCM7XX_GCR_NONE 0
/* Structure for register banks */
struct npcm7xx_gpio {
void __iomem *base;
struct gpio_chip gc;
int irqbase;
int irq;
u32 pinctrl_id;
int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
int value);
int (*request)(struct gpio_chip *chip, unsigned int offset);
void (*free)(struct gpio_chip *chip, unsigned int offset);
};
struct npcm7xx_pinctrl {
struct pinctrl_dev *pctldev;
struct device *dev;
struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
struct irq_domain *domain;
struct regmap *gcr_regmap;
void __iomem *regs;
u32 bank_num;
};
/* GPIO handling in the pinctrl driver */
static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
unsigned int pinmask)
{
unsigned long flags;
unsigned long val;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = ioread32(reg) | pinmask;
iowrite32(val, reg);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
unsigned int pinmask)
{
unsigned long flags;
unsigned long val;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = ioread32(reg) & ~pinmask;
iowrite32(val, reg);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
seq_printf(s, "-- module %d [gpio%d - %d]\n",
bank->gc.base / bank->gc.ngpio,
bank->gc.base,
bank->gc.base + bank->gc.ngpio);
seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_DIN),
ioread32(bank->base + NPCM7XX_GP_N_DOUT),
ioread32(bank->base + NPCM7XX_GP_N_IEM),
ioread32(bank->base + NPCM7XX_GP_N_OE));
seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_PU),
ioread32(bank->base + NPCM7XX_GP_N_PD),
ioread32(bank->base + NPCM7XX_GP_N_DBNC),
ioread32(bank->base + NPCM7XX_GP_N_POL));
seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
ioread32(bank->base + NPCM7XX_GP_N_EVBE),
ioread32(bank->base + NPCM7XX_GP_N_EVEN),
ioread32(bank->base + NPCM7XX_GP_N_EVST));
seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_OTYP),
ioread32(bank->base + NPCM7XX_GP_N_OSRC),
ioread32(bank->base + NPCM7XX_GP_N_ODSC));
seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_OBL0),
ioread32(bank->base + NPCM7XX_GP_N_OBL1),
ioread32(bank->base + NPCM7XX_GP_N_OBL2),
ioread32(bank->base + NPCM7XX_GP_N_OBL3));
seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
}
static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
int ret;
ret = pinctrl_gpio_direction_input(offset + chip->base);
if (ret)
return ret;
return bank->direction_input(chip, offset);
}
/* Set GPIO to Output with initial value */
static int npcmgpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
int ret;
dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
value);
ret = pinctrl_gpio_direction_output(offset + chip->base);
if (ret)
return ret;
return bank->direction_output(chip, offset, value);
}
static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
int ret;
dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
ret = pinctrl_gpio_request(offset + chip->base);
if (ret)
return ret;
return bank->request(chip, offset);
}
static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
pinctrl_gpio_free(offset + chip->base);
}
static void npcmgpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc;
struct irq_chip *chip;
struct npcm7xx_gpio *bank;
unsigned long sts, en, bit;
gc = irq_desc_get_handler_data(desc);
bank = gpiochip_get_data(gc);
chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
en = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
en);
sts &= en;
for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
generic_handle_domain_irq(gc->irq.domain, bit);
chained_irq_exit(chip, desc);
}
static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
unsigned int gpio = BIT(irqd_to_hwirq(d));
dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
d->irq, type);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
dev_dbg(bank->gc.parent, "edge.rising\n");
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
break;
case IRQ_TYPE_EDGE_FALLING:
dev_dbg(bank->gc.parent, "edge.falling\n");
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
break;
case IRQ_TYPE_EDGE_BOTH:
dev_dbg(bank->gc.parent, "edge.both\n");
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
break;
case IRQ_TYPE_LEVEL_LOW:
dev_dbg(bank->gc.parent, "level.low\n");
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
break;
case IRQ_TYPE_LEVEL_HIGH:
dev_dbg(bank->gc.parent, "level.high\n");
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
break;
default:
dev_dbg(bank->gc.parent, "invalid irq type\n");
return -EINVAL;
}
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
irq_set_handler_locked(d, handle_level_irq);
} else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING)) {
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
irq_set_handler_locked(d, handle_edge_irq);
}
return 0;
}
static void npcmgpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
unsigned int gpio = irqd_to_hwirq(d);
dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
}
/* Disable GPIO interrupt */
static void npcmgpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
unsigned int gpio = irqd_to_hwirq(d);
/* Clear events */
dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
gpiochip_disable_irq(gc, gpio);
}
/* Enable GPIO interrupt */
static void npcmgpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct npcm7xx_gpio *bank = gpiochip_get_data(gc);
unsigned int gpio = irqd_to_hwirq(d);
/* Enable events */
gpiochip_enable_irq(gc, gpio);
dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
}
static unsigned int npcmgpio_irq_startup(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
unsigned int gpio = irqd_to_hwirq(d);
/* active-high, input, clear interrupt, enable interrupt */
dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
npcmgpio_direction_input(gc, gpio);
npcmgpio_irq_ack(d);
npcmgpio_irq_unmask(d);
return 0;
}
static const struct irq_chip npcmgpio_irqchip = {
.name = "NPCM7XX-GPIO-IRQ",
.irq_ack = npcmgpio_irq_ack,
.irq_unmask = npcmgpio_irq_unmask,
.irq_mask = npcmgpio_irq_mask,
.irq_set_type = npcmgpio_set_irq_type,
.irq_startup = npcmgpio_irq_startup,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/* pinmux handing in the pinctrl driver*/
static const int smb0_pins[] = { 115, 114 };
static const int smb0b_pins[] = { 195, 194 };
static const int smb0c_pins[] = { 202, 196 };
static const int smb0d_pins[] = { 198, 199 };
static const int smb0den_pins[] = { 197 };
static const int smb1_pins[] = { 117, 116 };
static const int smb1b_pins[] = { 126, 127 };
static const int smb1c_pins[] = { 124, 125 };
static const int smb1d_pins[] = { 4, 5 };
static const int smb2_pins[] = { 119, 118 };
static const int smb2b_pins[] = { 122, 123 };
static const int smb2c_pins[] = { 120, 121 };
static const int smb2d_pins[] = { 6, 7 };
static const int smb3_pins[] = { 30, 31 };
static const int smb3b_pins[] = { 39, 40 };
static const int smb3c_pins[] = { 37, 38 };
static const int smb3d_pins[] = { 59, 60 };
static const int smb4_pins[] = { 28, 29 };
static const int smb4b_pins[] = { 18, 19 };
static const int smb4c_pins[] = { 20, 21 };
static const int smb4d_pins[] = { 22, 23 };
static const int smb4den_pins[] = { 17 };
static const int smb5_pins[] = { 26, 27 };
static const int smb5b_pins[] = { 13, 12 };
static const int smb5c_pins[] = { 15, 14 };
static const int smb5d_pins[] = { 94, 93 };
static const int ga20kbc_pins[] = { 94, 93 };
static const int smb6_pins[] = { 172, 171 };
static const int smb7_pins[] = { 174, 173 };
static const int smb8_pins[] = { 129, 128 };
static const int smb9_pins[] = { 131, 130 };
static const int smb10_pins[] = { 133, 132 };
static const int smb11_pins[] = { 135, 134 };
static const int smb12_pins[] = { 221, 220 };
static const int smb13_pins[] = { 223, 222 };
static const int smb14_pins[] = { 22, 23 };
static const int smb15_pins[] = { 20, 21 };
static const int fanin0_pins[] = { 64 };
static const int fanin1_pins[] = { 65 };
static const int fanin2_pins[] = { 66 };
static const int fanin3_pins[] = { 67 };
static const int fanin4_pins[] = { 68 };
static const int fanin5_pins[] = { 69 };
static const int fanin6_pins[] = { 70 };
static const int fanin7_pins[] = { 71 };
static const int fanin8_pins[] = { 72 };
static const int fanin9_pins[] = { 73 };
static const int fanin10_pins[] = { 74 };
static const int fanin11_pins[] = { 75 };
static const int fanin12_pins[] = { 76 };
static const int fanin13_pins[] = { 77 };
static const int fanin14_pins[] = { 78 };
static const int fanin15_pins[] = { 79 };
static const int faninx_pins[] = { 175, 176, 177, 203 };
static const int pwm0_pins[] = { 80 };
static const int pwm1_pins[] = { 81 };
static const int pwm2_pins[] = { 82 };
static const int pwm3_pins[] = { 83 };
static const int pwm4_pins[] = { 144 };
static const int pwm5_pins[] = { 145 };
static const int pwm6_pins[] = { 146 };
static const int pwm7_pins[] = { 147 };
static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
/* RGMII 1 pin group */
static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
106, 107 };
/* RGMII 1 MD interface pin group */
static const int rg1mdio_pins[] = { 108, 109 };
/* RGMII 2 pin group */
static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
213, 214, 215 };
/* RGMII 2 MD interface pin group */
static const int rg2mdio_pins[] = { 216, 217 };
static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
213, 214, 215, 216, 217 };
/* Serial I/O Expander 1 */
static const int iox1_pins[] = { 0, 1, 2, 3 };
/* Serial I/O Expander 2 */
static const int iox2_pins[] = { 4, 5, 6, 7 };
/* Host Serial I/O Expander 2 */
static const int ioxh_pins[] = { 10, 11, 24, 25 };
static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
static const int mmcwp_pins[] = { 153 };
static const int mmccd_pins[] = { 155 };
static const int mmcrst_pins[] = { 155 };
static const int mmc8_pins[] = { 148, 149, 150, 151 };
/* RMII 1 pin groups */
static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
static const int r1err_pins[] = { 56 };
static const int r1md_pins[] = { 57, 58 };
/* RMII 2 pin groups */
static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
static const int r2err_pins[] = { 90 };
static const int r2md_pins[] = { 91, 92 };
static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
static const int sd1pwr_pins[] = { 143 };
static const int wdog1_pins[] = { 218 };
static const int wdog2_pins[] = { 219 };
/* BMC serial port 0 */
static const int bmcuart0a_pins[] = { 41, 42 };
static const int bmcuart0b_pins[] = { 48, 49 };
static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
/* System Control Interrupt and Power Management Event pin group */
static const int scipme_pins[] = { 169 };
/* System Management Interrupt pin group */
static const int sci_pins[] = { 170 };
/* Serial Interrupt Line pin group */
static const int serirq_pins[] = { 162 };
static const int clkout_pins[] = { 160 };
static const int clkreq_pins[] = { 231 };
static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
/* Graphics SPI Clock pin group */
static const int gspi_pins[] = { 12, 13, 14, 15 };
static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
static const int spixcs1_pins[] = { 228 };
static const int pspi1_pins[] = { 175, 176, 177 };
static const int pspi2_pins[] = { 17, 18, 19 };
static const int spi0cs1_pins[] = { 32 };
static const int spi3_pins[] = { 183, 184, 185, 186 };
static const int spi3cs1_pins[] = { 187 };
static const int spi3quad_pins[] = { 188, 189 };
static const int spi3cs2_pins[] = { 188 };
static const int spi3cs3_pins[] = { 189 };
static const int ddc_pins[] = { 204, 205, 206, 207 };
static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
static const int lpcclk_pins[] = { 168 };
static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
static const int lkgpo0_pins[] = { 16 };
static const int lkgpo1_pins[] = { 8 };
static const int lkgpo2_pins[] = { 9 };
static const int nprd_smi_pins[] = { 190 };
/*
* pin: name, number
* group: name, npins, pins
* function: name, ngroups, groups
*/
struct npcm7xx_group {
const char *name;
const unsigned int *pins;
int npins;
};
#define NPCM7XX_GRPS \
NPCM7XX_GRP(smb0), \
NPCM7XX_GRP(smb0b), \
NPCM7XX_GRP(smb0c), \
NPCM7XX_GRP(smb0d), \
NPCM7XX_GRP(smb0den), \
NPCM7XX_GRP(smb1), \
NPCM7XX_GRP(smb1b), \
NPCM7XX_GRP(smb1c), \
NPCM7XX_GRP(smb1d), \
NPCM7XX_GRP(smb2), \
NPCM7XX_GRP(smb2b), \
NPCM7XX_GRP(smb2c), \
NPCM7XX_GRP(smb2d), \
NPCM7XX_GRP(smb3), \
NPCM7XX_GRP(smb3b), \
NPCM7XX_GRP(smb3c), \
NPCM7XX_GRP(smb3d), \
NPCM7XX_GRP(smb4), \
NPCM7XX_GRP(smb4b), \
NPCM7XX_GRP(smb4c), \
NPCM7XX_GRP(smb4d), \
NPCM7XX_GRP(smb4den), \
NPCM7XX_GRP(smb5), \
NPCM7XX_GRP(smb5b), \
NPCM7XX_GRP(smb5c), \
NPCM7XX_GRP(smb5d), \
NPCM7XX_GRP(ga20kbc), \
NPCM7XX_GRP(smb6), \
NPCM7XX_GRP(smb7), \
NPCM7XX_GRP(smb8), \
NPCM7XX_GRP(smb9), \
NPCM7XX_GRP(smb10), \
NPCM7XX_GRP(smb11), \
NPCM7XX_GRP(smb12), \
NPCM7XX_GRP(smb13), \
NPCM7XX_GRP(smb14), \
NPCM7XX_GRP(smb15), \
NPCM7XX_GRP(fanin0), \
NPCM7XX_GRP(fanin1), \
NPCM7XX_GRP(fanin2), \
NPCM7XX_GRP(fanin3), \
NPCM7XX_GRP(fanin4), \
NPCM7XX_GRP(fanin5), \
NPCM7XX_GRP(fanin6), \
NPCM7XX_GRP(fanin7), \
NPCM7XX_GRP(fanin8), \
NPCM7XX_GRP(fanin9), \
NPCM7XX_GRP(fanin10), \
NPCM7XX_GRP(fanin11), \
NPCM7XX_GRP(fanin12), \
NPCM7XX_GRP(fanin13), \
NPCM7XX_GRP(fanin14), \
NPCM7XX_GRP(fanin15), \
NPCM7XX_GRP(faninx), \
NPCM7XX_GRP(pwm0), \
NPCM7XX_GRP(pwm1), \
NPCM7XX_GRP(pwm2), \
NPCM7XX_GRP(pwm3), \
NPCM7XX_GRP(pwm4), \
NPCM7XX_GRP(pwm5), \
NPCM7XX_GRP(pwm6), \
NPCM7XX_GRP(pwm7), \
NPCM7XX_GRP(rg1), \
NPCM7XX_GRP(rg1mdio), \
NPCM7XX_GRP(rg2), \
NPCM7XX_GRP(rg2mdio), \
NPCM7XX_GRP(ddr), \
NPCM7XX_GRP(uart1), \
NPCM7XX_GRP(uart2), \
NPCM7XX_GRP(bmcuart0a), \
NPCM7XX_GRP(bmcuart0b), \
NPCM7XX_GRP(bmcuart1), \
NPCM7XX_GRP(iox1), \
NPCM7XX_GRP(iox2), \
NPCM7XX_GRP(ioxh), \
NPCM7XX_GRP(gspi), \
NPCM7XX_GRP(mmc), \
NPCM7XX_GRP(mmcwp), \
NPCM7XX_GRP(mmccd), \
NPCM7XX_GRP(mmcrst), \
NPCM7XX_GRP(mmc8), \
NPCM7XX_GRP(r1), \
NPCM7XX_GRP(r1err), \
NPCM7XX_GRP(r1md), \
NPCM7XX_GRP(r2), \
NPCM7XX_GRP(r2err), \
NPCM7XX_GRP(r2md), \
NPCM7XX_GRP(sd1), \
NPCM7XX_GRP(sd1pwr), \
NPCM7XX_GRP(wdog1), \
NPCM7XX_GRP(wdog2), \
NPCM7XX_GRP(scipme), \
NPCM7XX_GRP(sci), \
NPCM7XX_GRP(serirq), \
NPCM7XX_GRP(jtag2), \
NPCM7XX_GRP(spix), \
NPCM7XX_GRP(spixcs1), \
NPCM7XX_GRP(pspi1), \
NPCM7XX_GRP(pspi2), \
NPCM7XX_GRP(ddc), \
NPCM7XX_GRP(clkreq), \
NPCM7XX_GRP(clkout), \
NPCM7XX_GRP(spi3), \
NPCM7XX_GRP(spi3cs1), \
NPCM7XX_GRP(spi3quad), \
NPCM7XX_GRP(spi3cs2), \
NPCM7XX_GRP(spi3cs3), \
NPCM7XX_GRP(spi0cs1), \
NPCM7XX_GRP(lpc), \
NPCM7XX_GRP(lpcclk), \
NPCM7XX_GRP(espi), \
NPCM7XX_GRP(lkgpo0), \
NPCM7XX_GRP(lkgpo1), \
NPCM7XX_GRP(lkgpo2), \
NPCM7XX_GRP(nprd_smi), \
\
enum {
#define NPCM7XX_GRP(x) fn_ ## x
NPCM7XX_GRPS
/* add placeholder for none/gpio */
NPCM7XX_GRP(none),
NPCM7XX_GRP(gpio),
#undef NPCM7XX_GRP
};
static struct npcm7xx_group npcm7xx_groups[] = {
#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
.npins = ARRAY_SIZE(x ## _pins) }
NPCM7XX_GRPS
#undef NPCM7XX_GRP
};
#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
.groups = nm ## _grp }
struct npcm7xx_func {
const char *name;
const unsigned int ngroups;
const char *const *groups;
};
NPCM7XX_SFUNC(smb0);
NPCM7XX_SFUNC(smb0b);
NPCM7XX_SFUNC(smb0c);
NPCM7XX_SFUNC(smb0d);
NPCM7XX_SFUNC(smb0den);
NPCM7XX_SFUNC(smb1);
NPCM7XX_SFUNC(smb1b);
NPCM7XX_SFUNC(smb1c);
NPCM7XX_SFUNC(smb1d);
NPCM7XX_SFUNC(smb2);
NPCM7XX_SFUNC(smb2b);
NPCM7XX_SFUNC(smb2c);
NPCM7XX_SFUNC(smb2d);
NPCM7XX_SFUNC(smb3);
NPCM7XX_SFUNC(smb3b);
NPCM7XX_SFUNC(smb3c);
NPCM7XX_SFUNC(smb3d);
NPCM7XX_SFUNC(smb4);
NPCM7XX_SFUNC(smb4b);
NPCM7XX_SFUNC(smb4c);
NPCM7XX_SFUNC(smb4d);
NPCM7XX_SFUNC(smb4den);
NPCM7XX_SFUNC(smb5);
NPCM7XX_SFUNC(smb5b);
NPCM7XX_SFUNC(smb5c);
NPCM7XX_SFUNC(smb5d);
NPCM7XX_SFUNC(ga20kbc);
NPCM7XX_SFUNC(smb6);
NPCM7XX_SFUNC(smb7);
NPCM7XX_SFUNC(smb8);
NPCM7XX_SFUNC(smb9);
NPCM7XX_SFUNC(smb10);
NPCM7XX_SFUNC(smb11);
NPCM7XX_SFUNC(smb12);
NPCM7XX_SFUNC(smb13);
NPCM7XX_SFUNC(smb14);
NPCM7XX_SFUNC(smb15);
NPCM7XX_SFUNC(fanin0);
NPCM7XX_SFUNC(fanin1);
NPCM7XX_SFUNC(fanin2);
NPCM7XX_SFUNC(fanin3);
NPCM7XX_SFUNC(fanin4);
NPCM7XX_SFUNC(fanin5);
NPCM7XX_SFUNC(fanin6);
NPCM7XX_SFUNC(fanin7);
NPCM7XX_SFUNC(fanin8);
NPCM7XX_SFUNC(fanin9);
NPCM7XX_SFUNC(fanin10);
NPCM7XX_SFUNC(fanin11);
NPCM7XX_SFUNC(fanin12);
NPCM7XX_SFUNC(fanin13);
NPCM7XX_SFUNC(fanin14);
NPCM7XX_SFUNC(fanin15);
NPCM7XX_SFUNC(faninx);
NPCM7XX_SFUNC(pwm0);
NPCM7XX_SFUNC(pwm1);
NPCM7XX_SFUNC(pwm2);
NPCM7XX_SFUNC(pwm3);
NPCM7XX_SFUNC(pwm4);
NPCM7XX_SFUNC(pwm5);
NPCM7XX_SFUNC(pwm6);
NPCM7XX_SFUNC(pwm7);
NPCM7XX_SFUNC(rg1);
NPCM7XX_SFUNC(rg1mdio);
NPCM7XX_SFUNC(rg2);
NPCM7XX_SFUNC(rg2mdio);
NPCM7XX_SFUNC(ddr);
NPCM7XX_SFUNC(uart1);
NPCM7XX_SFUNC(uart2);
NPCM7XX_SFUNC(bmcuart0a);
NPCM7XX_SFUNC(bmcuart0b);
NPCM7XX_SFUNC(bmcuart1);
NPCM7XX_SFUNC(iox1);
NPCM7XX_SFUNC(iox2);
NPCM7XX_SFUNC(ioxh);
NPCM7XX_SFUNC(gspi);
NPCM7XX_SFUNC(mmc);
NPCM7XX_SFUNC(mmcwp);
NPCM7XX_SFUNC(mmccd);
NPCM7XX_SFUNC(mmcrst);
NPCM7XX_SFUNC(mmc8);
NPCM7XX_SFUNC(r1);
NPCM7XX_SFUNC(r1err);
NPCM7XX_SFUNC(r1md);
NPCM7XX_SFUNC(r2);
NPCM7XX_SFUNC(r2err);
NPCM7XX_SFUNC(r2md);
NPCM7XX_SFUNC(sd1);
NPCM7XX_SFUNC(sd1pwr);
NPCM7XX_SFUNC(wdog1);
NPCM7XX_SFUNC(wdog2);
NPCM7XX_SFUNC(scipme);
NPCM7XX_SFUNC(sci);
NPCM7XX_SFUNC(serirq);
NPCM7XX_SFUNC(jtag2);
NPCM7XX_SFUNC(spix);
NPCM7XX_SFUNC(spixcs1);
NPCM7XX_SFUNC(pspi1);
NPCM7XX_SFUNC(pspi2);
NPCM7XX_SFUNC(ddc);
NPCM7XX_SFUNC(clkreq);
NPCM7XX_SFUNC(clkout);
NPCM7XX_SFUNC(spi3);
NPCM7XX_SFUNC(spi3cs1);
NPCM7XX_SFUNC(spi3quad);
NPCM7XX_SFUNC(spi3cs2);
NPCM7XX_SFUNC(spi3cs3);
NPCM7XX_SFUNC(spi0cs1);
NPCM7XX_SFUNC(lpc);
NPCM7XX_SFUNC(lpcclk);
NPCM7XX_SFUNC(espi);
NPCM7XX_SFUNC(lkgpo0);
NPCM7XX_SFUNC(lkgpo1);
NPCM7XX_SFUNC(lkgpo2);
NPCM7XX_SFUNC(nprd_smi);
/* Function names */
static struct npcm7xx_func npcm7xx_funcs[] = {
NPCM7XX_MKFUNC(smb0),
NPCM7XX_MKFUNC(smb0b),
NPCM7XX_MKFUNC(smb0c),
NPCM7XX_MKFUNC(smb0d),
NPCM7XX_MKFUNC(smb0den),
NPCM7XX_MKFUNC(smb1),
NPCM7XX_MKFUNC(smb1b),
NPCM7XX_MKFUNC(smb1c),
NPCM7XX_MKFUNC(smb1d),
NPCM7XX_MKFUNC(smb2),
NPCM7XX_MKFUNC(smb2b),
NPCM7XX_MKFUNC(smb2c),
NPCM7XX_MKFUNC(smb2d),
NPCM7XX_MKFUNC(smb3),
NPCM7XX_MKFUNC(smb3b),
NPCM7XX_MKFUNC(smb3c),
NPCM7XX_MKFUNC(smb3d),
NPCM7XX_MKFUNC(smb4),
NPCM7XX_MKFUNC(smb4b),
NPCM7XX_MKFUNC(smb4c),
NPCM7XX_MKFUNC(smb4d),
NPCM7XX_MKFUNC(smb4den),
NPCM7XX_MKFUNC(smb5),
NPCM7XX_MKFUNC(smb5b),
NPCM7XX_MKFUNC(smb5c),
NPCM7XX_MKFUNC(smb5d),
NPCM7XX_MKFUNC(ga20kbc),
NPCM7XX_MKFUNC(smb6),
NPCM7XX_MKFUNC(smb7),
NPCM7XX_MKFUNC(smb8),
NPCM7XX_MKFUNC(smb9),
NPCM7XX_MKFUNC(smb10),
NPCM7XX_MKFUNC(smb11),
NPCM7XX_MKFUNC(smb12),
NPCM7XX_MKFUNC(smb13),
NPCM7XX_MKFUNC(smb14),
NPCM7XX_MKFUNC(smb15),
NPCM7XX_MKFUNC(fanin0),
NPCM7XX_MKFUNC(fanin1),
NPCM7XX_MKFUNC(fanin2),
NPCM7XX_MKFUNC(fanin3),
NPCM7XX_MKFUNC(fanin4),
NPCM7XX_MKFUNC(fanin5),
NPCM7XX_MKFUNC(fanin6),
NPCM7XX_MKFUNC(fanin7),
NPCM7XX_MKFUNC(fanin8),
NPCM7XX_MKFUNC(fanin9),
NPCM7XX_MKFUNC(fanin10),
NPCM7XX_MKFUNC(fanin11),
NPCM7XX_MKFUNC(fanin12),
NPCM7XX_MKFUNC(fanin13),
NPCM7XX_MKFUNC(fanin14),
NPCM7XX_MKFUNC(fanin15),
NPCM7XX_MKFUNC(faninx),
NPCM7XX_MKFUNC(pwm0),
NPCM7XX_MKFUNC(pwm1),
NPCM7XX_MKFUNC(pwm2),
NPCM7XX_MKFUNC(pwm3),
NPCM7XX_MKFUNC(pwm4),
NPCM7XX_MKFUNC(pwm5),
NPCM7XX_MKFUNC(pwm6),
NPCM7XX_MKFUNC(pwm7),
NPCM7XX_MKFUNC(rg1),
NPCM7XX_MKFUNC(rg1mdio),
NPCM7XX_MKFUNC(rg2),
NPCM7XX_MKFUNC(rg2mdio),
NPCM7XX_MKFUNC(ddr),
NPCM7XX_MKFUNC(uart1),
NPCM7XX_MKFUNC(uart2),
NPCM7XX_MKFUNC(bmcuart0a),
NPCM7XX_MKFUNC(bmcuart0b),
NPCM7XX_MKFUNC(bmcuart1),
NPCM7XX_MKFUNC(iox1),
NPCM7XX_MKFUNC(iox2),
NPCM7XX_MKFUNC(ioxh),
NPCM7XX_MKFUNC(gspi),
NPCM7XX_MKFUNC(mmc),
NPCM7XX_MKFUNC(mmcwp),
NPCM7XX_MKFUNC(mmccd),
NPCM7XX_MKFUNC(mmcrst),
NPCM7XX_MKFUNC(mmc8),
NPCM7XX_MKFUNC(r1),
NPCM7XX_MKFUNC(r1err),
NPCM7XX_MKFUNC(r1md),
NPCM7XX_MKFUNC(r2),
NPCM7XX_MKFUNC(r2err),
NPCM7XX_MKFUNC(r2md),
NPCM7XX_MKFUNC(sd1),
NPCM7XX_MKFUNC(sd1pwr),
NPCM7XX_MKFUNC(wdog1),
NPCM7XX_MKFUNC(wdog2),
NPCM7XX_MKFUNC(scipme),
NPCM7XX_MKFUNC(sci),
NPCM7XX_MKFUNC(serirq),
NPCM7XX_MKFUNC(jtag2),
NPCM7XX_MKFUNC(spix),
NPCM7XX_MKFUNC(spixcs1),
NPCM7XX_MKFUNC(pspi1),
NPCM7XX_MKFUNC(pspi2),
NPCM7XX_MKFUNC(ddc),
NPCM7XX_MKFUNC(clkreq),
NPCM7XX_MKFUNC(clkout),
NPCM7XX_MKFUNC(spi3),
NPCM7XX_MKFUNC(spi3cs1),
NPCM7XX_MKFUNC(spi3quad),
NPCM7XX_MKFUNC(spi3cs2),
NPCM7XX_MKFUNC(spi3cs3),
NPCM7XX_MKFUNC(spi0cs1),
NPCM7XX_MKFUNC(lpc),
NPCM7XX_MKFUNC(lpcclk),
NPCM7XX_MKFUNC(espi),
NPCM7XX_MKFUNC(lkgpo0),
NPCM7XX_MKFUNC(lkgpo1),
NPCM7XX_MKFUNC(lkgpo2),
NPCM7XX_MKFUNC(nprd_smi),
};
#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
[a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
.fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
.fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
.flag = k }
/* Drive strength controlled by NPCM7XX_GP_N_ODSC */
#define DRIVE_STRENGTH_LO_SHIFT 8
#define DRIVE_STRENGTH_HI_SHIFT 12
#define DRIVE_STRENGTH_MASK 0x0000FF00
#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
((hi) << DRIVE_STRENGTH_HI_SHIFT))
#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
#define GPI 0x1 /* Not GPO */
#define GPO 0x2 /* Not GPI */
#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
struct npcm7xx_pincfg {
int flag;
int fn0, reg0, bit0;
int fn1, reg1, bit1;
int fn2, reg2, bit2;
};
static const struct npcm7xx_pincfg pincfg[] = {
/* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0),
NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0),
NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)),
NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)),
NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)),
NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */
NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)),
NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
};
/* number, name, drv_data */
static const struct pinctrl_pin_desc npcm7xx_pins[] = {
PINCTRL_PIN(0, "GPIO0/IOX1DI"),
PINCTRL_PIN(1, "GPIO1/IOX1LD"),
PINCTRL_PIN(2, "GPIO2/IOX1CK"),
PINCTRL_PIN(3, "GPIO3/IOX1D0"),
PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
PINCTRL_PIN(8, "GPIO8/LKGPO1"),
PINCTRL_PIN(9, "GPIO9/LKGPO2"),
PINCTRL_PIN(10, "GPIO10/IOXHLD"),
PINCTRL_PIN(11, "GPIO11/IOXHCK"),
PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
PINCTRL_PIN(16, "GPIO16/LKGPO0"),
PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
PINCTRL_PIN(24, "GPIO24/IOXHDO"),
PINCTRL_PIN(25, "GPIO25/IOXHDI"),
PINCTRL_PIN(26, "GPIO26/SMB5SDA"),
PINCTRL_PIN(27, "GPIO27/SMB5SCL"),
PINCTRL_PIN(28, "GPIO28/SMB4SDA"),
PINCTRL_PIN(29, "GPIO29/SMB4SCL"),
PINCTRL_PIN(30, "GPIO30/SMB3SDA"),
PINCTRL_PIN(31, "GPIO31/SMB3SCL"),
PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),
PINCTRL_PIN(33, "SPI0D2"),
PINCTRL_PIN(34, "SPI0D3"),
PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),
PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),
PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),
PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),
PINCTRL_PIN(41, "GPIO41/BSPRXD"),
PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),
PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),
PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),
PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),
PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),
PINCTRL_PIN(50, "GPIO50/nCTS2"),
PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),
PINCTRL_PIN(52, "GPIO52/nDCD2"),
PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
PINCTRL_PIN(54, "GPIO54/nDSR2"),
PINCTRL_PIN(55, "GPIO55/nRI2"),
PINCTRL_PIN(56, "GPIO56/R1RXERR"),
PINCTRL_PIN(57, "GPIO57/R1MDC"),
PINCTRL_PIN(58, "GPIO58/R1MDIO"),
PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),
PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),
PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),
PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),
PINCTRL_PIN(64, "GPIO64/FANIN0"),
PINCTRL_PIN(65, "GPIO65/FANIN1"),
PINCTRL_PIN(66, "GPIO66/FANIN2"),
PINCTRL_PIN(67, "GPIO67/FANIN3"),
PINCTRL_PIN(68, "GPIO68/FANIN4"),
PINCTRL_PIN(69, "GPIO69/FANIN5"),
PINCTRL_PIN(70, "GPIO70/FANIN6"),
PINCTRL_PIN(71, "GPIO71/FANIN7"),
PINCTRL_PIN(72, "GPIO72/FANIN8"),
PINCTRL_PIN(73, "GPIO73/FANIN9"),
PINCTRL_PIN(74, "GPIO74/FANIN10"),
PINCTRL_PIN(75, "GPIO75/FANIN11"),
PINCTRL_PIN(76, "GPIO76/FANIN12"),
PINCTRL_PIN(77, "GPIO77/FANIN13"),
PINCTRL_PIN(78, "GPIO78/FANIN14"),
PINCTRL_PIN(79, "GPIO79/FANIN15"),
PINCTRL_PIN(80, "GPIO80/PWM0"),
PINCTRL_PIN(81, "GPIO81/PWM1"),
PINCTRL_PIN(82, "GPIO82/PWM2"),
PINCTRL_PIN(83, "GPIO83/PWM3"),
PINCTRL_PIN(84, "GPIO84/R2TXD0"),
PINCTRL_PIN(85, "GPIO85/R2TXD1"),
PINCTRL_PIN(86, "GPIO86/R2TXEN"),
PINCTRL_PIN(87, "GPIO87/R2RXD0"),
PINCTRL_PIN(88, "GPIO88/R2RXD1"),
PINCTRL_PIN(89, "GPIO89/R2CRSDV"),
PINCTRL_PIN(90, "GPIO90/R2RXERR"),
PINCTRL_PIN(91, "GPIO91/R2MDC"),
PINCTRL_PIN(92, "GPIO92/R2MDIO"),
PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),
PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),
PINCTRL_PIN(96, "GPIO96/RG1TXD0"),
PINCTRL_PIN(97, "GPIO97/RG1TXD1"),
PINCTRL_PIN(98, "GPIO98/RG1TXD2"),
PINCTRL_PIN(99, "GPIO99/RG1TXD3"),
PINCTRL_PIN(100, "GPIO100/RG1TXC"),
PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),
PINCTRL_PIN(102, "GPIO102/RG1RXD0"),
PINCTRL_PIN(103, "GPIO103/RG1RXD1"),
PINCTRL_PIN(104, "GPIO104/RG1RXD2"),
PINCTRL_PIN(105, "GPIO105/RG1RXD3"),
PINCTRL_PIN(106, "GPIO106/RG1RXC"),
PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),
PINCTRL_PIN(108, "GPIO108/RG1MDC"),
PINCTRL_PIN(109, "GPIO109/RG1MDIO"),
PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
PINCTRL_PIN(114, "GPIO114/SMB0SCL"),
PINCTRL_PIN(115, "GPIO115/SMB0SDA"),
PINCTRL_PIN(116, "GPIO116/SMB1SCL"),
PINCTRL_PIN(117, "GPIO117/SMB1SDA"),
PINCTRL_PIN(118, "GPIO118/SMB2SCL"),
PINCTRL_PIN(119, "GPIO119/SMB2SDA"),
PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),
PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),
PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),
PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),
PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),
PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),
PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),
PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),
PINCTRL_PIN(128, "GPIO128/SMB8SCL"),
PINCTRL_PIN(129, "GPIO129/SMB8SDA"),
PINCTRL_PIN(130, "GPIO130/SMB9SCL"),
PINCTRL_PIN(131, "GPIO131/SMB9SDA"),
PINCTRL_PIN(132, "GPIO132/SMB10SCL"),
PINCTRL_PIN(133, "GPIO133/SMB10SDA"),
PINCTRL_PIN(134, "GPIO134/SMB11SCL"),
PINCTRL_PIN(135, "GPIO135/SMB11SDA"),
PINCTRL_PIN(136, "GPIO136/SD1DT0"),
PINCTRL_PIN(137, "GPIO137/SD1DT1"),
PINCTRL_PIN(138, "GPIO138/SD1DT2"),
PINCTRL_PIN(139, "GPIO139/SD1DT3"),
PINCTRL_PIN(140, "GPIO140/SD1CLK"),
PINCTRL_PIN(141, "GPIO141/SD1WP"),
PINCTRL_PIN(142, "GPIO142/SD1CMD"),
PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),
PINCTRL_PIN(144, "GPIO144/PWM4"),
PINCTRL_PIN(145, "GPIO145/PWM5"),
PINCTRL_PIN(146, "GPIO146/PWM6"),
PINCTRL_PIN(147, "GPIO147/PWM7"),
PINCTRL_PIN(148, "GPIO148/MMCDT4"),
PINCTRL_PIN(149, "GPIO149/MMCDT5"),
PINCTRL_PIN(150, "GPIO150/MMCDT6"),
PINCTRL_PIN(151, "GPIO151/MMCDT7"),
PINCTRL_PIN(152, "GPIO152/MMCCLK"),
PINCTRL_PIN(153, "GPIO153/MMCWP"),
PINCTRL_PIN(154, "GPIO154/MMCCMD"),
PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
PINCTRL_PIN(156, "GPIO156/MMCDT0"),
PINCTRL_PIN(157, "GPIO157/MMCDT1"),
PINCTRL_PIN(158, "GPIO158/MMCDT2"),
PINCTRL_PIN(159, "GPIO159/MMCDT3"),
PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),
PINCTRL_PIN(162, "GPIO162/SERIRQ"),
PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),
PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
PINCTRL_PIN(169, "GPIO169/nSCIPME"),
PINCTRL_PIN(170, "GPIO170/nSMI"),
PINCTRL_PIN(171, "GPIO171/SMB6SCL"),
PINCTRL_PIN(172, "GPIO172/SMB6SDA"),
PINCTRL_PIN(173, "GPIO173/SMB7SCL"),
PINCTRL_PIN(174, "GPIO174/SMB7SDA"),
PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
PINCTRL_PIN(178, "GPIO178/R1TXD0"),
PINCTRL_PIN(179, "GPIO179/R1TXD1"),
PINCTRL_PIN(180, "GPIO180/R1TXEN"),
PINCTRL_PIN(181, "GPIO181/R1RXD0"),
PINCTRL_PIN(182, "GPIO182/R1RXD1"),
PINCTRL_PIN(183, "GPIO183/SPI3CK"),
PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),
PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),
PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),
PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),
PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
PINCTRL_PIN(191, "GPIO191"),
PINCTRL_PIN(192, "GPIO192"),
PINCTRL_PIN(193, "GPIO193/R1CRSDV"),
PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),
PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),
PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),
PINCTRL_PIN(197, "GPIO197/SMB0DEN"),
PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),
PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),
PINCTRL_PIN(200, "GPIO200/R2CK"),
PINCTRL_PIN(201, "GPIO201/R1CK"),
PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),
PINCTRL_PIN(203, "GPIO203/FANIN16"),
PINCTRL_PIN(204, "GPIO204/DDC2SCL"),
PINCTRL_PIN(205, "GPIO205/DDC2SDA"),
PINCTRL_PIN(206, "GPIO206/HSYNC2"),
PINCTRL_PIN(207, "GPIO207/VSYNC2"),
PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),
PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),
PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),
PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
PINCTRL_PIN(218, "GPIO218/nWDO1"),
PINCTRL_PIN(219, "GPIO219/nWDO2"),
PINCTRL_PIN(220, "GPIO220/SMB12SCL"),
PINCTRL_PIN(221, "GPIO221/SMB12SDA"),
PINCTRL_PIN(222, "GPIO222/SMB13SCL"),
PINCTRL_PIN(223, "GPIO223/SMB13SDA"),
PINCTRL_PIN(224, "GPIO224/SPIXCK"),
PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),
PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),
PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),
PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),
PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),
PINCTRL_PIN(230, "GPIO230/SPIXD3"),
PINCTRL_PIN(231, "GPIO231/nCLKREQ"),
PINCTRL_PIN(255, "GPI255/DACOSEL"),
};
/* Enable mode in pin group */
static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
int pin_number, int mode)
{
const struct npcm7xx_pincfg *cfg;
int i;
for (i = 0 ; i < pin_number ; i++) {
cfg = &pincfg[pin[i]];
if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
if (cfg->reg0)
regmap_update_bits(gcr_regmap, cfg->reg0,
BIT(cfg->bit0),
!!(cfg->fn0 == mode) ?
BIT(cfg->bit0) : 0);
if (cfg->reg1)
regmap_update_bits(gcr_regmap, cfg->reg1,
BIT(cfg->bit1),
!!(cfg->fn1 == mode) ?
BIT(cfg->bit1) : 0);
if (cfg->reg2)
regmap_update_bits(gcr_regmap, cfg->reg2,
BIT(cfg->bit2),
!!(cfg->fn2 == mode) ?
BIT(cfg->bit2) : 0);
}
}
}
/* Get slew rate of pin (high/low) */
static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,
struct regmap *gcr_regmap, unsigned int pin)
{
u32 val;
int gpio = (pin % bank->gc.ngpio);
unsigned long pinmask = BIT(gpio);
if (pincfg[pin].flag & SLEW)
return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
& pinmask;
/* LPC Slew rate in SRCNT register */
if (pincfg[pin].flag & SLEWLPC) {
regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);
return !!(val & SRCNT_ESPI);
}
return -EINVAL;
}
/* Set slew rate of pin (high/low) */
static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,
struct regmap *gcr_regmap, unsigned int pin,
int arg)
{
int gpio = BIT(pin % bank->gc.ngpio);
if (pincfg[pin].flag & SLEW) {
switch (arg) {
case 0:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
gpio);
return 0;
case 1:
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
gpio);
return 0;
default:
return -EINVAL;
}
}
/* LPC Slew rate in SRCNT register */
if (pincfg[pin].flag & SLEWLPC) {
switch (arg) {
case 0:
regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
SRCNT_ESPI, 0);
return 0;
case 1:
regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
SRCNT_ESPI, SRCNT_ESPI);
return 0;
default:
return -EINVAL;
}
}
return -EINVAL;
}
/* Get drive strength for a pin, if supported */
static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,
unsigned int pin)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
struct npcm7xx_gpio *bank =
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
int gpio = (pin % bank->gc.ngpio);
unsigned long pinmask = BIT(gpio);
u32 ds = 0;
int flg, val;
flg = pincfg[pin].flag;
if (flg & DRIVE_STRENGTH_MASK) {
/* Get standard reading */
val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
& pinmask;
ds = val ? DSHI(flg) : DSLO(flg);
dev_dbg(bank->gc.parent,
"pin %d strength %d = %d\n", pin, val, ds);
return ds;
}
return -EINVAL;
}
/* Set drive strength for a pin, if supported */
static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,
unsigned int pin, int nval)
{
int v;
struct npcm7xx_gpio *bank =
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
int gpio = BIT(pin % bank->gc.ngpio);
v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
if (!nval || !v)
return -ENOTSUPP;
if (DSLO(v) == nval) {
dev_dbg(bank->gc.parent,
"setting pin %d to low strength [%d]\n", pin, nval);
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
return 0;
} else if (DSHI(v) == nval) {
dev_dbg(bank->gc.parent,
"setting pin %d to high strength [%d]\n", pin, nval);
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
return 0;
}
return -ENOTSUPP;
}
/* pinctrl_ops */
static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, "pinctrl_ops.dbg: %d", offset);
}
static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
return ARRAY_SIZE(npcm7xx_groups);
}
static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return npcm7xx_groups[selector].name;
}
static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
*npins = npcm7xx_groups[selector].npins;
*pins = npcm7xx_groups[selector].pins;
return 0;
}
static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
u32 *num_maps)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
return pinconf_generic_dt_node_to_map(pctldev, np_config,
map, num_maps,
PIN_MAP_TYPE_INVALID);
}
static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, u32 num_maps)
{
kfree(map);
}
static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
.get_groups_count = npcm7xx_get_groups_count,
.get_group_name = npcm7xx_get_group_name,
.get_group_pins = npcm7xx_get_group_pins,
.pin_dbg_show = npcm7xx_pin_dbg_show,
.dt_node_to_map = npcm7xx_dt_node_to_map,
.dt_free_map = npcm7xx_dt_free_map,
};
/* pinmux_ops */
static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(npcm7xx_funcs);
}
static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return npcm7xx_funcs[function].name;
}
static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const ngroups)
{
*ngroups = npcm7xx_funcs[function].ngroups;
*groups = npcm7xx_funcs[function].groups;
return 0;
}
static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,
npcm7xx_groups[group].name);
npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,
npcm7xx_groups[group].npins, group);
return 0;
}
static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
if (!range) {
dev_err(npcm->dev, "invalid range\n");
return -EINVAL;
}
if (!range->gc) {
dev_err(npcm->dev, "invalid gpiochip\n");
return -EINVAL;
}
npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);
return 0;
}
/* Release GPIO back to pinctrl mode */
static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
int virq;
virq = irq_find_mapping(npcm->domain, offset);
if (virq)
irq_dispose_mapping(virq);
}
/* Set GPIO direction */
static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
struct npcm7xx_gpio *bank =
&npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
int gpio = BIT(offset % bank->gc.ngpio);
dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,
input);
if (input)
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
else
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
return 0;
}
static const struct pinmux_ops npcm7xx_pinmux_ops = {
.get_functions_count = npcm7xx_get_functions_count,
.get_function_name = npcm7xx_get_function_name,
.get_function_groups = npcm7xx_get_function_groups,
.set_mux = npcm7xx_pinmux_set_mux,
.gpio_request_enable = npcm7xx_gpio_request_enable,
.gpio_disable_free = npcm7xx_gpio_request_free,
.gpio_set_direction = npcm_gpio_set_direction,
};
/* pinconf_ops */
static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
enum pin_config_param param = pinconf_to_config_param(*config);
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
struct npcm7xx_gpio *bank =
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
int gpio = (pin % bank->gc.ngpio);
unsigned long pinmask = BIT(gpio);
u32 ie, oe, pu, pd;
int rc = 0;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
if (param == PIN_CONFIG_BIAS_DISABLE)
rc = (!pu && !pd);
else if (param == PIN_CONFIG_BIAS_PULL_UP)
rc = (pu && !pd);
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
rc = (!pu && pd);
break;
case PIN_CONFIG_OUTPUT:
case PIN_CONFIG_INPUT_ENABLE:
ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
if (param == PIN_CONFIG_INPUT_ENABLE)
rc = (ie && !oe);
else if (param == PIN_CONFIG_OUTPUT)
rc = (!ie && oe);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
rc = npcm7xx_get_drive_strength(pctldev, pin);
if (rc)
*config = pinconf_to_config_packed(param, rc);
break;
case PIN_CONFIG_SLEW_RATE:
rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
if (rc >= 0)
*config = pinconf_to_config_packed(param, rc);
break;
default:
return -ENOTSUPP;
}
if (!rc)
return -EINVAL;
return 0;
}
static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
unsigned int pin, unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
u16 arg = pinconf_to_config_argument(config);
struct npcm7xx_gpio *bank =
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
int gpio = BIT(pin % bank->gc.ngpio);
dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
break;
case PIN_CONFIG_BIAS_PULL_UP:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
break;
case PIN_CONFIG_INPUT_ENABLE:
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
break;
case PIN_CONFIG_OUTPUT:
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
break;
case PIN_CONFIG_SLEW_RATE:
return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
case PIN_CONFIG_DRIVE_STRENGTH:
return npcm7xx_set_drive_strength(npcm, pin, arg);
default:
return -ENOTSUPP;
}
return 0;
}
/* Set multiple configuration settings for a pin */
static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
int rc;
while (num_configs--) {
rc = npcm7xx_config_set_one(npcm, pin, *configs++);
if (rc)
return rc;
}
return 0;
}
static const struct pinconf_ops npcm7xx_pinconf_ops = {
.is_generic = true,
.pin_config_get = npcm7xx_config_get,
.pin_config_set = npcm7xx_config_set,
};
/* pinctrl_desc */
static struct pinctrl_desc npcm7xx_pinctrl_desc = {
.name = "npcm7xx-pinctrl",
.pins = npcm7xx_pins,
.npins = ARRAY_SIZE(npcm7xx_pins),
.pctlops = &npcm7xx_pinctrl_ops,
.pmxops = &npcm7xx_pinmux_ops,
.confops = &npcm7xx_pinconf_ops,
.owner = THIS_MODULE,
};
static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
{
int ret = -ENXIO;
struct resource res;
struct device *dev = pctrl->dev;
struct fwnode_reference_args args;
struct fwnode_handle *child;
int id = 0;
for_each_gpiochip_node(dev, child) {
struct device_node *np = to_of_node(child);
ret = of_address_to_resource(np, 0, &res);
if (ret < 0) {
dev_err(dev, "Resource fail for GPIO bank %u\n", id);
return ret;
}
pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));
if (!pctrl->gpio_bank[id].base)
return -EINVAL;
ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,
NULL,
NULL,
pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,
BGPIOF_READ_OUTPUT_REG_SET);
if (ret) {
dev_err(dev, "bgpio_init() failed\n");
return ret;
}
ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
if (ret < 0) {
dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);
return ret;
}
ret = irq_of_parse_and_map(np, 0);
if (!ret) {
dev_err(dev, "No IRQ for GPIO bank %u\n", id);
return -EINVAL;
}
pctrl->gpio_bank[id].irq = ret;
pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;
pctrl->gpio_bank[id].pinctrl_id = args.args[0];
pctrl->gpio_bank[id].gc.base = args.args[1];
pctrl->gpio_bank[id].gc.ngpio = args.args[2];
pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
pctrl->gpio_bank[id].gc.parent = dev;
pctrl->gpio_bank[id].gc.fwnode = child;
pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
if (pctrl->gpio_bank[id].gc.label == NULL)
return -ENOMEM;
pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
id++;
}
pctrl->bank_num = id;
return ret;
}
static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)
{
int ret, id;
for (id = 0 ; id < pctrl->bank_num ; id++) {
struct gpio_irq_chip *girq;
girq = &pctrl->gpio_bank[id].gc.irq;
gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip);
girq->parent_handler = npcmgpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(pctrl->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
ret = -ENOMEM;
goto err_register;
}
girq->parents[0] = pctrl->gpio_bank[id].irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
ret = devm_gpiochip_add_data(pctrl->dev,
&pctrl->gpio_bank[id].gc,
&pctrl->gpio_bank[id]);
if (ret) {
dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);
goto err_register;
}
ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,
dev_name(pctrl->dev),
pctrl->gpio_bank[id].pinctrl_id,
pctrl->gpio_bank[id].gc.base,
pctrl->gpio_bank[id].gc.ngpio);
if (ret < 0) {
dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);
gpiochip_remove(&pctrl->gpio_bank[id].gc);
goto err_register;
}
}
return 0;
err_register:
for (; id > 0; id--)
gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);
return ret;
}
static int npcm7xx_pinctrl_probe(struct platform_device *pdev)
{
struct npcm7xx_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, pctrl);
pctrl->gcr_regmap =
syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
if (IS_ERR(pctrl->gcr_regmap)) {
dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");
return PTR_ERR(pctrl->gcr_regmap);
}
ret = npcm7xx_gpio_of(pctrl);
if (ret < 0) {
dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
return ret;
}
pctrl->pctldev = devm_pinctrl_register(&pdev->dev,
&npcm7xx_pinctrl_desc, pctrl);
if (IS_ERR(pctrl->pctldev)) {
dev_err(&pdev->dev, "Failed to register pinctrl device\n");
return PTR_ERR(pctrl->pctldev);
}
ret = npcm7xx_gpio_register(pctrl);
if (ret < 0) {
dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);
return ret;
}
pr_info("NPCM7xx Pinctrl driver probed\n");
return 0;
}
static const struct of_device_id npcm7xx_pinctrl_match[] = {
{ .compatible = "nuvoton,npcm750-pinctrl" },
{ },
};
MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);
static struct platform_driver npcm7xx_pinctrl_driver = {
.probe = npcm7xx_pinctrl_probe,
.driver = {
.name = "npcm7xx-pinctrl",
.of_match_table = npcm7xx_pinctrl_match,
.suppress_bind_attrs = true,
},
};
static int __init npcm7xx_pinctrl_register(void)
{
return platform_driver_register(&npcm7xx_pinctrl_driver);
}
arch_initcall(npcm7xx_pinctrl_register);
MODULE_AUTHOR("[email protected]");
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");
|
linux-master
|
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Freescale imx7d pinctrl driver
//
// Author: Anson Huang <[email protected]>
// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx7d_pads {
MX7D_PAD_RESERVE0 = 0,
MX7D_PAD_RESERVE1 = 1,
MX7D_PAD_RESERVE2 = 2,
MX7D_PAD_RESERVE3 = 3,
MX7D_PAD_RESERVE4 = 4,
MX7D_PAD_GPIO1_IO08 = 5,
MX7D_PAD_GPIO1_IO09 = 6,
MX7D_PAD_GPIO1_IO10 = 7,
MX7D_PAD_GPIO1_IO11 = 8,
MX7D_PAD_GPIO1_IO12 = 9,
MX7D_PAD_GPIO1_IO13 = 10,
MX7D_PAD_GPIO1_IO14 = 11,
MX7D_PAD_GPIO1_IO15 = 12,
MX7D_PAD_EPDC_DATA00 = 13,
MX7D_PAD_EPDC_DATA01 = 14,
MX7D_PAD_EPDC_DATA02 = 15,
MX7D_PAD_EPDC_DATA03 = 16,
MX7D_PAD_EPDC_DATA04 = 17,
MX7D_PAD_EPDC_DATA05 = 18,
MX7D_PAD_EPDC_DATA06 = 19,
MX7D_PAD_EPDC_DATA07 = 20,
MX7D_PAD_EPDC_DATA08 = 21,
MX7D_PAD_EPDC_DATA09 = 22,
MX7D_PAD_EPDC_DATA10 = 23,
MX7D_PAD_EPDC_DATA11 = 24,
MX7D_PAD_EPDC_DATA12 = 25,
MX7D_PAD_EPDC_DATA13 = 26,
MX7D_PAD_EPDC_DATA14 = 27,
MX7D_PAD_EPDC_DATA15 = 28,
MX7D_PAD_EPDC_SDCLK = 29,
MX7D_PAD_EPDC_SDLE = 30,
MX7D_PAD_EPDC_SDOE = 31,
MX7D_PAD_EPDC_SDSHR = 32,
MX7D_PAD_EPDC_SDCE0 = 33,
MX7D_PAD_EPDC_SDCE1 = 34,
MX7D_PAD_EPDC_SDCE2 = 35,
MX7D_PAD_EPDC_SDCE3 = 36,
MX7D_PAD_EPDC_GDCLK = 37,
MX7D_PAD_EPDC_GDOE = 38,
MX7D_PAD_EPDC_GDRL = 39,
MX7D_PAD_EPDC_GDSP = 40,
MX7D_PAD_EPDC_BDR0 = 41,
MX7D_PAD_EPDC_BDR1 = 42,
MX7D_PAD_EPDC_PWR_COM = 43,
MX7D_PAD_EPDC_PWR_STAT = 44,
MX7D_PAD_LCD_CLK = 45,
MX7D_PAD_LCD_ENABLE = 46,
MX7D_PAD_LCD_HSYNC = 47,
MX7D_PAD_LCD_VSYNC = 48,
MX7D_PAD_LCD_RESET = 49,
MX7D_PAD_LCD_DATA00 = 50,
MX7D_PAD_LCD_DATA01 = 51,
MX7D_PAD_LCD_DATA02 = 52,
MX7D_PAD_LCD_DATA03 = 53,
MX7D_PAD_LCD_DATA04 = 54,
MX7D_PAD_LCD_DATA05 = 55,
MX7D_PAD_LCD_DATA06 = 56,
MX7D_PAD_LCD_DATA07 = 57,
MX7D_PAD_LCD_DATA08 = 58,
MX7D_PAD_LCD_DATA09 = 59,
MX7D_PAD_LCD_DATA10 = 60,
MX7D_PAD_LCD_DATA11 = 61,
MX7D_PAD_LCD_DATA12 = 62,
MX7D_PAD_LCD_DATA13 = 63,
MX7D_PAD_LCD_DATA14 = 64,
MX7D_PAD_LCD_DATA15 = 65,
MX7D_PAD_LCD_DATA16 = 66,
MX7D_PAD_LCD_DATA17 = 67,
MX7D_PAD_LCD_DATA18 = 68,
MX7D_PAD_LCD_DATA19 = 69,
MX7D_PAD_LCD_DATA20 = 70,
MX7D_PAD_LCD_DATA21 = 71,
MX7D_PAD_LCD_DATA22 = 72,
MX7D_PAD_LCD_DATA23 = 73,
MX7D_PAD_UART1_RX_DATA = 74,
MX7D_PAD_UART1_TX_DATA = 75,
MX7D_PAD_UART2_RX_DATA = 76,
MX7D_PAD_UART2_TX_DATA = 77,
MX7D_PAD_UART3_RX_DATA = 78,
MX7D_PAD_UART3_TX_DATA = 79,
MX7D_PAD_UART3_RTS_B = 80,
MX7D_PAD_UART3_CTS_B = 81,
MX7D_PAD_I2C1_SCL = 82,
MX7D_PAD_I2C1_SDA = 83,
MX7D_PAD_I2C2_SCL = 84,
MX7D_PAD_I2C2_SDA = 85,
MX7D_PAD_I2C3_SCL = 86,
MX7D_PAD_I2C3_SDA = 87,
MX7D_PAD_I2C4_SCL = 88,
MX7D_PAD_I2C4_SDA = 89,
MX7D_PAD_ECSPI1_SCLK = 90,
MX7D_PAD_ECSPI1_MOSI = 91,
MX7D_PAD_ECSPI1_MISO = 92,
MX7D_PAD_ECSPI1_SS0 = 93,
MX7D_PAD_ECSPI2_SCLK = 94,
MX7D_PAD_ECSPI2_MOSI = 95,
MX7D_PAD_ECSPI2_MISO = 96,
MX7D_PAD_ECSPI2_SS0 = 97,
MX7D_PAD_SD1_CD_B = 98,
MX7D_PAD_SD1_WP = 99,
MX7D_PAD_SD1_RESET_B = 100,
MX7D_PAD_SD1_CLK = 101,
MX7D_PAD_SD1_CMD = 102,
MX7D_PAD_SD1_DATA0 = 103,
MX7D_PAD_SD1_DATA1 = 104,
MX7D_PAD_SD1_DATA2 = 105,
MX7D_PAD_SD1_DATA3 = 106,
MX7D_PAD_SD2_CD_B = 107,
MX7D_PAD_SD2_WP = 108,
MX7D_PAD_SD2_RESET_B = 109,
MX7D_PAD_SD2_CLK = 110,
MX7D_PAD_SD2_CMD = 111,
MX7D_PAD_SD2_DATA0 = 112,
MX7D_PAD_SD2_DATA1 = 113,
MX7D_PAD_SD2_DATA2 = 114,
MX7D_PAD_SD2_DATA3 = 115,
MX7D_PAD_SD3_CLK = 116,
MX7D_PAD_SD3_CMD = 117,
MX7D_PAD_SD3_DATA0 = 118,
MX7D_PAD_SD3_DATA1 = 119,
MX7D_PAD_SD3_DATA2 = 120,
MX7D_PAD_SD3_DATA3 = 121,
MX7D_PAD_SD3_DATA4 = 122,
MX7D_PAD_SD3_DATA5 = 123,
MX7D_PAD_SD3_DATA6 = 124,
MX7D_PAD_SD3_DATA7 = 125,
MX7D_PAD_SD3_STROBE = 126,
MX7D_PAD_SD3_RESET_B = 127,
MX7D_PAD_SAI1_RX_DATA = 128,
MX7D_PAD_SAI1_TX_BCLK = 129,
MX7D_PAD_SAI1_TX_SYNC = 130,
MX7D_PAD_SAI1_TX_DATA = 131,
MX7D_PAD_SAI1_RX_SYNC = 132,
MX7D_PAD_SAI1_RX_BCLK = 133,
MX7D_PAD_SAI1_MCLK = 134,
MX7D_PAD_SAI2_TX_SYNC = 135,
MX7D_PAD_SAI2_TX_BCLK = 136,
MX7D_PAD_SAI2_RX_DATA = 137,
MX7D_PAD_SAI2_TX_DATA = 138,
MX7D_PAD_ENET1_RGMII_RD0 = 139,
MX7D_PAD_ENET1_RGMII_RD1 = 140,
MX7D_PAD_ENET1_RGMII_RD2 = 141,
MX7D_PAD_ENET1_RGMII_RD3 = 142,
MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
MX7D_PAD_ENET1_RGMII_RXC = 144,
MX7D_PAD_ENET1_RGMII_TD0 = 145,
MX7D_PAD_ENET1_RGMII_TD1 = 146,
MX7D_PAD_ENET1_RGMII_TD2 = 147,
MX7D_PAD_ENET1_RGMII_TD3 = 148,
MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
MX7D_PAD_ENET1_RGMII_TXC = 150,
MX7D_PAD_ENET1_TX_CLK = 151,
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
};
enum imx7d_lpsr_pads {
MX7D_PAD_GPIO1_IO00 = 0,
MX7D_PAD_GPIO1_IO01 = 1,
MX7D_PAD_GPIO1_IO02 = 2,
MX7D_PAD_GPIO1_IO03 = 3,
MX7D_PAD_GPIO1_IO04 = 4,
MX7D_PAD_GPIO1_IO05 = 5,
MX7D_PAD_GPIO1_IO06 = 6,
MX7D_PAD_GPIO1_IO07 = 7,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};
static const struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
};
static const struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
.pins = imx7d_lpsr_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
.flags = ZERO_OFFSET_VALID,
};
static const struct of_device_id imx7d_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
{ /* sentinel */ }
};
static int imx7d_pinctrl_probe(struct platform_device *pdev)
{
const struct imx_pinctrl_soc_info *pinctrl_info;
pinctrl_info = of_device_get_match_data(&pdev->dev);
if (!pinctrl_info)
return -ENODEV;
return imx_pinctrl_probe(pdev, pinctrl_info);
}
static struct platform_driver imx7d_pinctrl_driver = {
.driver = {
.name = "imx7d-pinctrl",
.of_match_table = imx7d_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx7d_pinctrl_probe,
};
static int __init imx7d_pinctrl_init(void)
{
return platform_driver_register(&imx7d_pinctrl_driver);
}
arch_initcall(imx7d_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx7d.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx8ulp_pads {
IMX8ULP_PAD_PTD0 = 0,
IMX8ULP_PAD_PTD1,
IMX8ULP_PAD_PTD2,
IMX8ULP_PAD_PTD3,
IMX8ULP_PAD_PTD4,
IMX8ULP_PAD_PTD5,
IMX8ULP_PAD_PTD6,
IMX8ULP_PAD_PTD7,
IMX8ULP_PAD_PTD8,
IMX8ULP_PAD_PTD9,
IMX8ULP_PAD_PTD10,
IMX8ULP_PAD_PTD11,
IMX8ULP_PAD_PTD12,
IMX8ULP_PAD_PTD13,
IMX8ULP_PAD_PTD14,
IMX8ULP_PAD_PTD15,
IMX8ULP_PAD_PTD16,
IMX8ULP_PAD_PTD17,
IMX8ULP_PAD_PTD18,
IMX8ULP_PAD_PTD19,
IMX8ULP_PAD_PTD20,
IMX8ULP_PAD_PTD21,
IMX8ULP_PAD_PTD22,
IMX8ULP_PAD_PTD23,
IMX8ULP_PAD_RESERVE0,
IMX8ULP_PAD_RESERVE1,
IMX8ULP_PAD_RESERVE2,
IMX8ULP_PAD_RESERVE3,
IMX8ULP_PAD_RESERVE4,
IMX8ULP_PAD_RESERVE5,
IMX8ULP_PAD_RESERVE6,
IMX8ULP_PAD_RESERVE7,
IMX8ULP_PAD_PTE0,
IMX8ULP_PAD_PTE1,
IMX8ULP_PAD_PTE2,
IMX8ULP_PAD_PTE3,
IMX8ULP_PAD_PTE4,
IMX8ULP_PAD_PTE5,
IMX8ULP_PAD_PTE6,
IMX8ULP_PAD_PTE7,
IMX8ULP_PAD_PTE8,
IMX8ULP_PAD_PTE9,
IMX8ULP_PAD_PTE10,
IMX8ULP_PAD_PTE11,
IMX8ULP_PAD_PTE12,
IMX8ULP_PAD_PTE13,
IMX8ULP_PAD_PTE14,
IMX8ULP_PAD_PTE15,
IMX8ULP_PAD_PTE16,
IMX8ULP_PAD_PTE17,
IMX8ULP_PAD_PTE18,
IMX8ULP_PAD_PTE19,
IMX8ULP_PAD_PTE20,
IMX8ULP_PAD_PTE21,
IMX8ULP_PAD_PTE22,
IMX8ULP_PAD_PTE23,
IMX8ULP_PAD_RESERVE8,
IMX8ULP_PAD_RESERVE9,
IMX8ULP_PAD_RESERVE10,
IMX8ULP_PAD_RESERVE11,
IMX8ULP_PAD_RESERVE12,
IMX8ULP_PAD_RESERVE13,
IMX8ULP_PAD_RESERVE14,
IMX8ULP_PAD_RESERVE15,
IMX8ULP_PAD_PTF0,
IMX8ULP_PAD_PTF1,
IMX8ULP_PAD_PTF2,
IMX8ULP_PAD_PTF3,
IMX8ULP_PAD_PTF4,
IMX8ULP_PAD_PTF5,
IMX8ULP_PAD_PTF6,
IMX8ULP_PAD_PTF7,
IMX8ULP_PAD_PTF8,
IMX8ULP_PAD_PTF9,
IMX8ULP_PAD_PTF10,
IMX8ULP_PAD_PTF11,
IMX8ULP_PAD_PTF12,
IMX8ULP_PAD_PTF13,
IMX8ULP_PAD_PTF14,
IMX8ULP_PAD_PTF15,
IMX8ULP_PAD_PTF16,
IMX8ULP_PAD_PTF17,
IMX8ULP_PAD_PTF18,
IMX8ULP_PAD_PTF19,
IMX8ULP_PAD_PTF20,
IMX8ULP_PAD_PTF21,
IMX8ULP_PAD_PTF22,
IMX8ULP_PAD_PTF23,
IMX8ULP_PAD_PTF24,
IMX8ULP_PAD_PTF25,
IMX8ULP_PAD_PTF26,
IMX8ULP_PAD_PTF27,
IMX8ULP_PAD_PTF28,
IMX8ULP_PAD_PTF29,
IMX8ULP_PAD_PTF30,
IMX8ULP_PAD_PTF31,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
};
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
else
reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
.pins = imx8ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
};
static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8ulp-iomuxc1", },
{ /* sentinel */ }
};
static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
}
static struct platform_driver imx8ulp_pinctrl_driver = {
.driver = {
.name = "imx8ulp-pinctrl",
.of_match_table = imx8ulp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8ulp_pinctrl_probe,
};
static int __init imx8ulp_pinctrl_init(void)
{
return platform_driver_register(&imx8ulp_pinctrl_driver);
}
arch_initcall(imx8ulp_pinctrl_init);
MODULE_AUTHOR("Jacky Bai <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8ulp.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <[email protected]>
*/
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "../core.h"
#include "pinctrl-imx.h"
#define IMX_SC_PAD_FUNC_GET_WAKEUP 9
#define IMX_SC_PAD_FUNC_SET_WAKEUP 4
#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */
#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */
enum pad_func_e {
IMX_SC_PAD_FUNC_SET = 15,
IMX_SC_PAD_FUNC_GET = 16,
};
struct imx_sc_msg_req_pad_set {
struct imx_sc_rpc_msg hdr;
u32 val;
u16 pad;
} __packed __aligned(4);
struct imx_sc_msg_req_pad_get {
struct imx_sc_rpc_msg hdr;
u16 pad;
} __packed __aligned(4);
struct imx_sc_msg_resp_pad_get {
struct imx_sc_rpc_msg hdr;
u32 val;
} __packed;
struct imx_sc_msg_gpio_set_pad_wakeup {
struct imx_sc_rpc_msg hdr;
u16 pad;
u8 wakeup;
} __packed __aligned(4);
static struct imx_sc_ipc *pinctrl_ipc_handle;
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
{
imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE,
IMX_SC_IRQ_PAD, true);
return imx_scu_get_handle(&pinctrl_ipc_handle);
}
EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init);
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
{
struct imx_sc_msg_req_pad_get msg;
struct imx_sc_msg_resp_pad_get *resp;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_GET;
hdr->size = 2;
msg.pad = pin_id;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
if (ret)
return ret;
resp = (struct imx_sc_msg_resp_pad_get *)&msg;
*config = resp->val;
return 0;
}
EXPORT_SYMBOL_GPL(imx_pinconf_get_scu);
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_sc_msg_req_pad_set msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
unsigned int mux = configs[0];
unsigned int conf;
unsigned int val;
int ret;
if (num_configs == 1) {
struct imx_sc_msg_gpio_set_pad_wakeup wmsg;
hdr = &wmsg.hdr;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP;
hdr->size = 2;
wmsg.pad = pin_id;
wmsg.wakeup = *configs;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true);
dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %ld\n",
pin_id, *configs);
return ret;
}
/*
* Set mux and conf together in one IPC call
*/
WARN_ON(num_configs != 2);
conf = configs[1];
val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
val |= mux << BP_PAD_CTL_IFMUX;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_SET;
hdr->size = 3;
msg.pad = pin_id;
msg.val = val;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
pin_id, conf, val);
return ret;
}
EXPORT_SYMBOL_GPL(imx_pinconf_set_scu);
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_scu *pin_scu = &pin->conf.scu;
const __be32 *list = *list_p;
pin->pin = be32_to_cpu(*list++);
*pin_id = pin->pin;
pin_scu->mux_mode = be32_to_cpu(*list++);
pin_scu->config = be32_to_cpu(*list++);
*list_p = list;
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
pin_scu->mux_mode, pin_scu->config);
}
EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
MODULE_AUTHOR("Dong Aisheng <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-scu.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2018-2019 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx8mn_pads {
MX8MN_PAD_RESERVE0 = 0,
MX8MN_PAD_RESERVE1 = 1,
MX8MN_PAD_RESERVE2 = 2,
MX8MN_PAD_RESERVE3 = 3,
MX8MN_PAD_RESERVE4 = 4,
MX8MN_PAD_RESERVE5 = 5,
MX8MN_PAD_RESERVE6 = 6,
MX8MN_PAD_RESERVE7 = 7,
MX8MN_IOMUXC_BOOT_MODE2 = 8,
MX8MN_IOMUXC_BOOT_MODE3 = 9,
MX8MN_IOMUXC_GPIO1_IO00 = 10,
MX8MN_IOMUXC_GPIO1_IO01 = 11,
MX8MN_IOMUXC_GPIO1_IO02 = 12,
MX8MN_IOMUXC_GPIO1_IO03 = 13,
MX8MN_IOMUXC_GPIO1_IO04 = 14,
MX8MN_IOMUXC_GPIO1_IO05 = 15,
MX8MN_IOMUXC_GPIO1_IO06 = 16,
MX8MN_IOMUXC_GPIO1_IO07 = 17,
MX8MN_IOMUXC_GPIO1_IO08 = 18,
MX8MN_IOMUXC_GPIO1_IO09 = 19,
MX8MN_IOMUXC_GPIO1_IO10 = 20,
MX8MN_IOMUXC_GPIO1_IO11 = 21,
MX8MN_IOMUXC_GPIO1_IO12 = 22,
MX8MN_IOMUXC_GPIO1_IO13 = 23,
MX8MN_IOMUXC_GPIO1_IO14 = 24,
MX8MN_IOMUXC_GPIO1_IO15 = 25,
MX8MN_IOMUXC_ENET_MDC = 26,
MX8MN_IOMUXC_ENET_MDIO = 27,
MX8MN_IOMUXC_ENET_TD3 = 28,
MX8MN_IOMUXC_ENET_TD2 = 29,
MX8MN_IOMUXC_ENET_TD1 = 30,
MX8MN_IOMUXC_ENET_TD0 = 31,
MX8MN_IOMUXC_ENET_TX_CTL = 32,
MX8MN_IOMUXC_ENET_TXC = 33,
MX8MN_IOMUXC_ENET_RX_CTL = 34,
MX8MN_IOMUXC_ENET_RXC = 35,
MX8MN_IOMUXC_ENET_RD0 = 36,
MX8MN_IOMUXC_ENET_RD1 = 37,
MX8MN_IOMUXC_ENET_RD2 = 38,
MX8MN_IOMUXC_ENET_RD3 = 39,
MX8MN_IOMUXC_SD1_CLK = 40,
MX8MN_IOMUXC_SD1_CMD = 41,
MX8MN_IOMUXC_SD1_DATA0 = 42,
MX8MN_IOMUXC_SD1_DATA1 = 43,
MX8MN_IOMUXC_SD1_DATA2 = 44,
MX8MN_IOMUXC_SD1_DATA3 = 45,
MX8MN_IOMUXC_SD1_DATA4 = 46,
MX8MN_IOMUXC_SD1_DATA5 = 47,
MX8MN_IOMUXC_SD1_DATA6 = 48,
MX8MN_IOMUXC_SD1_DATA7 = 49,
MX8MN_IOMUXC_SD1_RESET_B = 50,
MX8MN_IOMUXC_SD1_STROBE = 51,
MX8MN_IOMUXC_SD2_CD_B = 52,
MX8MN_IOMUXC_SD2_CLK = 53,
MX8MN_IOMUXC_SD2_CMD = 54,
MX8MN_IOMUXC_SD2_DATA0 = 55,
MX8MN_IOMUXC_SD2_DATA1 = 56,
MX8MN_IOMUXC_SD2_DATA2 = 57,
MX8MN_IOMUXC_SD2_DATA3 = 58,
MX8MN_IOMUXC_SD2_RESET_B = 59,
MX8MN_IOMUXC_SD2_WP = 60,
MX8MN_IOMUXC_NAND_ALE = 61,
MX8MN_IOMUXC_NAND_CE0 = 62,
MX8MN_IOMUXC_NAND_CE1 = 63,
MX8MN_IOMUXC_NAND_CE2 = 64,
MX8MN_IOMUXC_NAND_CE3 = 65,
MX8MN_IOMUXC_NAND_CLE = 66,
MX8MN_IOMUXC_NAND_DATA00 = 67,
MX8MN_IOMUXC_NAND_DATA01 = 68,
MX8MN_IOMUXC_NAND_DATA02 = 69,
MX8MN_IOMUXC_NAND_DATA03 = 70,
MX8MN_IOMUXC_NAND_DATA04 = 71,
MX8MN_IOMUXC_NAND_DATA05 = 72,
MX8MN_IOMUXC_NAND_DATA06 = 73,
MX8MN_IOMUXC_NAND_DATA07 = 74,
MX8MN_IOMUXC_NAND_DQS = 75,
MX8MN_IOMUXC_NAND_RE_B = 76,
MX8MN_IOMUXC_NAND_READY_B = 77,
MX8MN_IOMUXC_NAND_WE_B = 78,
MX8MN_IOMUXC_NAND_WP_B = 79,
MX8MN_IOMUXC_SAI5_RXFS = 80,
MX8MN_IOMUXC_SAI5_RXC = 81,
MX8MN_IOMUXC_SAI5_RXD0 = 82,
MX8MN_IOMUXC_SAI5_RXD1 = 83,
MX8MN_IOMUXC_SAI5_RXD2 = 84,
MX8MN_IOMUXC_SAI5_RXD3 = 85,
MX8MN_IOMUXC_SAI5_MCLK = 86,
MX8MN_IOMUXC_SAI1_RXFS = 87,
MX8MN_IOMUXC_SAI1_RXC = 88,
MX8MN_IOMUXC_SAI1_RXD0 = 89,
MX8MN_IOMUXC_SAI1_RXD1 = 90,
MX8MN_IOMUXC_SAI1_RXD2 = 91,
MX8MN_IOMUXC_SAI1_RXD3 = 92,
MX8MN_IOMUXC_SAI1_RXD4 = 93,
MX8MN_IOMUXC_SAI1_RXD5 = 94,
MX8MN_IOMUXC_SAI1_RXD6 = 95,
MX8MN_IOMUXC_SAI1_RXD7 = 96,
MX8MN_IOMUXC_SAI1_TXFS = 97,
MX8MN_IOMUXC_SAI1_TXC = 98,
MX8MN_IOMUXC_SAI1_TXD0 = 99,
MX8MN_IOMUXC_SAI1_TXD1 = 100,
MX8MN_IOMUXC_SAI1_TXD2 = 101,
MX8MN_IOMUXC_SAI1_TXD3 = 102,
MX8MN_IOMUXC_SAI1_TXD4 = 103,
MX8MN_IOMUXC_SAI1_TXD5 = 104,
MX8MN_IOMUXC_SAI1_TXD6 = 105,
MX8MN_IOMUXC_SAI1_TXD7 = 106,
MX8MN_IOMUXC_SAI1_MCLK = 107,
MX8MN_IOMUXC_SAI2_RXFS = 108,
MX8MN_IOMUXC_SAI2_RXC = 109,
MX8MN_IOMUXC_SAI2_RXD0 = 110,
MX8MN_IOMUXC_SAI2_TXFS = 111,
MX8MN_IOMUXC_SAI2_TXC = 112,
MX8MN_IOMUXC_SAI2_TXD0 = 113,
MX8MN_IOMUXC_SAI2_MCLK = 114,
MX8MN_IOMUXC_SAI3_RXFS = 115,
MX8MN_IOMUXC_SAI3_RXC = 116,
MX8MN_IOMUXC_SAI3_RXD = 117,
MX8MN_IOMUXC_SAI3_TXFS = 118,
MX8MN_IOMUXC_SAI3_TXC = 119,
MX8MN_IOMUXC_SAI3_TXD = 120,
MX8MN_IOMUXC_SAI3_MCLK = 121,
MX8MN_IOMUXC_SPDIF_TX = 122,
MX8MN_IOMUXC_SPDIF_RX = 123,
MX8MN_IOMUXC_SPDIF_EXT_CLK = 124,
MX8MN_IOMUXC_ECSPI1_SCLK = 125,
MX8MN_IOMUXC_ECSPI1_MOSI = 126,
MX8MN_IOMUXC_ECSPI1_MISO = 127,
MX8MN_IOMUXC_ECSPI1_SS0 = 128,
MX8MN_IOMUXC_ECSPI2_SCLK = 129,
MX8MN_IOMUXC_ECSPI2_MOSI = 130,
MX8MN_IOMUXC_ECSPI2_MISO = 131,
MX8MN_IOMUXC_ECSPI2_SS0 = 132,
MX8MN_IOMUXC_I2C1_SCL = 133,
MX8MN_IOMUXC_I2C1_SDA = 134,
MX8MN_IOMUXC_I2C2_SCL = 135,
MX8MN_IOMUXC_I2C2_SDA = 136,
MX8MN_IOMUXC_I2C3_SCL = 137,
MX8MN_IOMUXC_I2C3_SDA = 138,
MX8MN_IOMUXC_I2C4_SCL = 139,
MX8MN_IOMUXC_I2C4_SDA = 140,
MX8MN_IOMUXC_UART1_RXD = 141,
MX8MN_IOMUXC_UART1_TXD = 142,
MX8MN_IOMUXC_UART2_RXD = 143,
MX8MN_IOMUXC_UART2_TXD = 144,
MX8MN_IOMUXC_UART3_RXD = 145,
MX8MN_IOMUXC_UART3_TXD = 146,
MX8MN_IOMUXC_UART4_RXD = 147,
MX8MN_IOMUXC_UART4_TXD = 148,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO05),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO06),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO07),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO08),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO09),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO10),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO11),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO12),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO13),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO14),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO15),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDIO),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TX_CTL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RX_CTL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_RESET_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_WP),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_ALE),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CLE),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA00),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA01),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA02),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA03),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA04),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA05),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA06),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA07),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DQS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_RE_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_READY_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WE_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WP_B),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_MCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD4),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD5),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD6),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD7),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD1),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD2),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD3),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD4),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD5),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD6),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD7),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_MCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXD0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_MCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXFS),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXC),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_MCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_TX),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_RX),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_EXT_CLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SCL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SDA),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SCL),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SDA),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_RXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_TXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_RXD),
IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD),
};
static const struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
.pins = imx8mn_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mn_pinctrl_pads),
.gpr_compatible = "fsl,imx8mn-iomuxc-gpr",
};
static const struct of_device_id imx8mn_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8mn-iomuxc", .data = &imx8mn_pinctrl_info, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8mn_pinctrl_of_match);
static int imx8mn_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8mn_pinctrl_info);
}
static struct platform_driver imx8mn_pinctrl_driver = {
.driver = {
.name = "imx8mn-pinctrl",
.of_match_table = imx8mn_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mn_pinctrl_probe,
};
static int __init imx8mn_pinctrl_init(void)
{
return platform_driver_register(&imx8mn_pinctrl_driver);
}
arch_initcall(imx8mn_pinctrl_init);
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MN pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8mn.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// Core driver for the imx pin controller in imx1/21/27
//
// Copyright (C) 2013 Pengutronix
// Author: Markus Pargmann <[email protected]>
//
// Based on pinctrl-imx.c:
// Author: Dong Aisheng <[email protected]>
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro Ltd.
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "pinctrl-imx1.h"
struct imx1_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
const struct imx1_pinctrl_soc_info *info;
};
/*
* MX1 register offsets
*/
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
#define MX1_ICONFB 0x14
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
/*
* MUX_ID format defines
*/
#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
/*
* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
* control registers are separated into function, output configuration, input
* configuration A, input configuration B, GPIO in use and data direction.
*
* Those controls that are represented by 1 bit have a direct mapping between
* bit position and pin id. If they are represented by 2 bit, the lower 16 pins
* are in the first register and the upper 16 pins in the second (next)
* register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
*/
/*
* Calculates the register offset from a pin_id
*/
static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
{
unsigned int port = pin_id / 32;
return ipctl->base + port * MX1_PORT_STRIDE;
}
/*
* Write to a register with 2 bits per pin. The function will automatically
* use the next register if the pin is managed in the second register.
*/
static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
u32 old_val;
u32 new_val;
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
reg, offset, value);
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x3; /* Make sure value is really 2 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
int mask = ~BIT_MASK(offset);
u32 old_val;
u32 new_val;
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x1; /* Make sure value is really 1 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = (pin_id % 16) * 2;
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
}
static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
return !!(readl(reg) & BIT(offset));
}
static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
const struct imx1_pinctrl_soc_info *info,
const char *name)
{
const struct imx1_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name)) {
grp = &info->groups[i];
break;
}
}
return grp;
}
static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->ngroups;
}
static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->groups[selector].name;
}
static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned int **pins,
unsigned *npins)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pin_ids;
*npins = info->groups[selector].npins;
return 0;
}
static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
imx1_read_bit(ipctl, offset, MX1_GIUS),
imx1_read_bit(ipctl, offset, MX1_GPR),
imx1_read_bit(ipctl, offset, MX1_DDIR),
imx1_read_2bit(ipctl, offset, MX1_OCR),
imx1_read_2bit(ipctl, offset, MX1_ICONFA),
imx1_read_2bit(ipctl, offset, MX1_ICONFB));
}
static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
const struct imx1_pin_group *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num = 1;
int i, j;
/*
* first find the group of this node and check if we need create
* config maps for pins
*/
grp = imx1_pinctrl_find_group_by_name(info, np->name);
if (!grp) {
dev_err(info->dev, "unable to find group for node %pOFn\n",
np);
return -EINVAL;
}
for (i = 0; i < grp->npins; i++)
map_num++;
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
kfree(new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = j = 0; i < grp->npins; i++) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i].pin_id);
new_map[j].data.configs.configs = &grp->pins[i].config;
new_map[j].data.configs.num_configs = 1;
j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops imx1_pctrl_ops = {
.get_groups_count = imx1_get_groups_count,
.get_group_name = imx1_get_group_name,
.get_group_pins = imx1_get_group_pins,
.pin_dbg_show = imx1_pin_dbg_show,
.dt_node_to_map = imx1_dt_node_to_map,
.dt_free_map = imx1_dt_free_map,
};
static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
const struct imx1_pin *pins;
unsigned int npins;
int i;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
pins = info->groups[group].pins;
npins = info->groups[group].npins;
WARN_ON(!pins || !npins);
dev_dbg(ipctl->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
for (i = 0; i < npins; i++) {
unsigned int mux = pins[i].mux_id;
unsigned int pin_id = pins[i].pin_id;
unsigned int afunction = MX1_MUX_FUNCTION(mux);
unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
unsigned int direction = MX1_MUX_DIR(mux);
unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
__func__, pin_id, afunction, gpio_in_use,
direction, gpio_oconf, gpio_iconfa,
gpio_iconfb);
imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
if (gpio_in_use) {
imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
MX1_ICONFA);
imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
MX1_ICONFB);
} else {
imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
}
}
return 0;
}
static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->nfunctions;
}
static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->functions[selector].name;
}
static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
*groups = info->functions[selector].groups;
*num_groups = info->functions[selector].num_groups;
return 0;
}
static const struct pinmux_ops imx1_pmx_ops = {
.get_functions_count = imx1_pmx_get_funcs_count,
.get_function_name = imx1_pmx_get_func_name,
.get_function_groups = imx1_pmx_get_groups,
.set_mux = imx1_pmx_set,
};
static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
*config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
return 0;
}
static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
int i;
for (i = 0; i != num_configs; ++i) {
imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
pin_desc_get(pctldev, pin_id)->name);
}
return 0;
}
static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
unsigned long config;
imx1_pinconf_get(pctldev, pin_id, &config);
seq_printf(s, "0x%lx", config);
}
static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
struct imx1_pin_group *grp;
unsigned long config;
const char *name;
int i, ret;
if (group >= info->ngroups)
return;
seq_puts(s, "\n");
grp = &info->groups[group];
for (i = 0; i < grp->npins; i++) {
name = pin_get_name(pctldev, grp->pins[i].pin_id);
ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
if (ret)
return;
seq_printf(s, "%s: 0x%lx", name, config);
}
}
static const struct pinconf_ops imx1_pinconf_ops = {
.pin_config_get = imx1_pinconf_get,
.pin_config_set = imx1_pinconf_set,
.pin_config_dbg_show = imx1_pinconf_dbg_show,
.pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
};
static struct pinctrl_desc imx1_pinctrl_desc = {
.pctlops = &imx1_pctrl_ops,
.pmxops = &imx1_pmx_ops,
.confops = &imx1_pinconf_ops,
.owner = THIS_MODULE,
};
static int imx1_pinctrl_parse_groups(struct device_node *np,
struct imx1_pin_group *grp,
struct imx1_pinctrl_soc_info *info,
u32 index)
{
int size;
const __be32 *list;
int i;
dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
/* Initialise group */
grp->name = np->name;
/*
* the binding format is fsl,pins = <PIN MUX_ID CONFIG>
*/
list = of_get_property(np, "fsl,pins", &size);
/* we do not check return since it's safe node passed down */
if (!size || size % 12) {
dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
np);
return -EINVAL;
}
grp->npins = size / 12;
grp->pins = devm_kcalloc(info->dev,
grp->npins, sizeof(struct imx1_pin), GFP_KERNEL);
grp->pin_ids = devm_kcalloc(info->dev,
grp->npins, sizeof(unsigned int), GFP_KERNEL);
if (!grp->pins || !grp->pin_ids)
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
grp->pins[i].pin_id = be32_to_cpu(*list++);
grp->pins[i].mux_id = be32_to_cpu(*list++);
grp->pins[i].config = be32_to_cpu(*list++);
grp->pin_ids[i] = grp->pins[i].pin_id;
}
return 0;
}
static int imx1_pinctrl_parse_functions(struct device_node *np,
struct imx1_pinctrl_soc_info *info,
u32 index)
{
struct device_node *child;
struct imx1_pmx_func *func;
struct imx1_pin_group *grp;
int ret;
static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
func = &info->functions[index];
/* Initialise function */
func->name = np->name;
func->num_groups = of_get_child_count(np);
if (func->num_groups == 0)
return -EINVAL;
func->groups = devm_kcalloc(info->dev,
func->num_groups, sizeof(char *), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
if (ret == -ENOMEM) {
of_node_put(child);
return ret;
}
}
return 0;
}
static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
int ret;
u32 nfuncs = 0;
u32 ngroups = 0;
u32 ifunc = 0;
if (!np)
return -ENODEV;
for_each_child_of_node(np, child) {
++nfuncs;
ngroups += of_get_child_count(child);
}
if (!nfuncs) {
dev_err(&pdev->dev, "No pin functions defined\n");
return -EINVAL;
}
info->nfunctions = nfuncs;
info->functions = devm_kcalloc(&pdev->dev,
nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL);
info->ngroups = ngroups;
info->groups = devm_kcalloc(&pdev->dev,
ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL);
if (!info->functions || !info->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
if (ret == -ENOMEM) {
of_node_put(child);
return -ENOMEM;
}
}
return 0;
}
int imx1_pinctrl_core_probe(struct platform_device *pdev,
struct imx1_pinctrl_soc_info *info)
{
struct imx1_pinctrl *ipctl;
struct resource *res;
struct pinctrl_desc *pctl_desc;
int ret;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
info->dev = &pdev->dev;
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
ipctl->base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!ipctl->base)
return -ENOMEM;
pctl_desc = &imx1_pinctrl_desc;
pctl_desc->name = dev_name(&pdev->dev);
pctl_desc->pins = info->pins;
pctl_desc->npins = info->npins;
ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
if (ret) {
dev_err(&pdev->dev, "fail to probe dt properties\n");
return ret;
}
ipctl->info = info;
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl);
if (IS_ERR(ipctl->pctl)) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return PTR_ERR(ipctl->pctl);
}
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Failed to populate subdevices\n");
return ret;
}
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return 0;
}
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx1-core.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// imx51 pinctrl driver based on imx pinmux core
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx51_pads {
MX51_PAD_RESERVE0 = 0,
MX51_PAD_RESERVE1 = 1,
MX51_PAD_RESERVE2 = 2,
MX51_PAD_RESERVE3 = 3,
MX51_PAD_RESERVE4 = 4,
MX51_PAD_RESERVE5 = 5,
MX51_PAD_RESERVE6 = 6,
MX51_PAD_EIM_DA0 = 7,
MX51_PAD_EIM_DA1 = 8,
MX51_PAD_EIM_DA2 = 9,
MX51_PAD_EIM_DA3 = 10,
MX51_PAD_EIM_DA4 = 11,
MX51_PAD_EIM_DA5 = 12,
MX51_PAD_EIM_DA6 = 13,
MX51_PAD_EIM_DA7 = 14,
MX51_PAD_EIM_DA8 = 15,
MX51_PAD_EIM_DA9 = 16,
MX51_PAD_EIM_DA10 = 17,
MX51_PAD_EIM_DA11 = 18,
MX51_PAD_EIM_DA12 = 19,
MX51_PAD_EIM_DA13 = 20,
MX51_PAD_EIM_DA14 = 21,
MX51_PAD_EIM_DA15 = 22,
MX51_PAD_EIM_D16 = 23,
MX51_PAD_EIM_D17 = 24,
MX51_PAD_EIM_D18 = 25,
MX51_PAD_EIM_D19 = 26,
MX51_PAD_EIM_D20 = 27,
MX51_PAD_EIM_D21 = 28,
MX51_PAD_EIM_D22 = 29,
MX51_PAD_EIM_D23 = 30,
MX51_PAD_EIM_D24 = 31,
MX51_PAD_EIM_D25 = 32,
MX51_PAD_EIM_D26 = 33,
MX51_PAD_EIM_D27 = 34,
MX51_PAD_EIM_D28 = 35,
MX51_PAD_EIM_D29 = 36,
MX51_PAD_EIM_D30 = 37,
MX51_PAD_EIM_D31 = 38,
MX51_PAD_EIM_A16 = 39,
MX51_PAD_EIM_A17 = 40,
MX51_PAD_EIM_A18 = 41,
MX51_PAD_EIM_A19 = 42,
MX51_PAD_EIM_A20 = 43,
MX51_PAD_EIM_A21 = 44,
MX51_PAD_EIM_A22 = 45,
MX51_PAD_EIM_A23 = 46,
MX51_PAD_EIM_A24 = 47,
MX51_PAD_EIM_A25 = 48,
MX51_PAD_EIM_A26 = 49,
MX51_PAD_EIM_A27 = 50,
MX51_PAD_EIM_EB0 = 51,
MX51_PAD_EIM_EB1 = 52,
MX51_PAD_EIM_EB2 = 53,
MX51_PAD_EIM_EB3 = 54,
MX51_PAD_EIM_OE = 55,
MX51_PAD_EIM_CS0 = 56,
MX51_PAD_EIM_CS1 = 57,
MX51_PAD_EIM_CS2 = 58,
MX51_PAD_EIM_CS3 = 59,
MX51_PAD_EIM_CS4 = 60,
MX51_PAD_EIM_CS5 = 61,
MX51_PAD_EIM_DTACK = 62,
MX51_PAD_EIM_LBA = 63,
MX51_PAD_EIM_CRE = 64,
MX51_PAD_DRAM_CS1 = 65,
MX51_PAD_NANDF_WE_B = 66,
MX51_PAD_NANDF_RE_B = 67,
MX51_PAD_NANDF_ALE = 68,
MX51_PAD_NANDF_CLE = 69,
MX51_PAD_NANDF_WP_B = 70,
MX51_PAD_NANDF_RB0 = 71,
MX51_PAD_NANDF_RB1 = 72,
MX51_PAD_NANDF_RB2 = 73,
MX51_PAD_NANDF_RB3 = 74,
MX51_PAD_GPIO_NAND = 75,
MX51_PAD_NANDF_CS0 = 76,
MX51_PAD_NANDF_CS1 = 77,
MX51_PAD_NANDF_CS2 = 78,
MX51_PAD_NANDF_CS3 = 79,
MX51_PAD_NANDF_CS4 = 80,
MX51_PAD_NANDF_CS5 = 81,
MX51_PAD_NANDF_CS6 = 82,
MX51_PAD_NANDF_CS7 = 83,
MX51_PAD_NANDF_RDY_INT = 84,
MX51_PAD_NANDF_D15 = 85,
MX51_PAD_NANDF_D14 = 86,
MX51_PAD_NANDF_D13 = 87,
MX51_PAD_NANDF_D12 = 88,
MX51_PAD_NANDF_D11 = 89,
MX51_PAD_NANDF_D10 = 90,
MX51_PAD_NANDF_D9 = 91,
MX51_PAD_NANDF_D8 = 92,
MX51_PAD_NANDF_D7 = 93,
MX51_PAD_NANDF_D6 = 94,
MX51_PAD_NANDF_D5 = 95,
MX51_PAD_NANDF_D4 = 96,
MX51_PAD_NANDF_D3 = 97,
MX51_PAD_NANDF_D2 = 98,
MX51_PAD_NANDF_D1 = 99,
MX51_PAD_NANDF_D0 = 100,
MX51_PAD_CSI1_D8 = 101,
MX51_PAD_CSI1_D9 = 102,
MX51_PAD_CSI1_D10 = 103,
MX51_PAD_CSI1_D11 = 104,
MX51_PAD_CSI1_D12 = 105,
MX51_PAD_CSI1_D13 = 106,
MX51_PAD_CSI1_D14 = 107,
MX51_PAD_CSI1_D15 = 108,
MX51_PAD_CSI1_D16 = 109,
MX51_PAD_CSI1_D17 = 110,
MX51_PAD_CSI1_D18 = 111,
MX51_PAD_CSI1_D19 = 112,
MX51_PAD_CSI1_VSYNC = 113,
MX51_PAD_CSI1_HSYNC = 114,
MX51_PAD_CSI2_D12 = 115,
MX51_PAD_CSI2_D13 = 116,
MX51_PAD_CSI2_D14 = 117,
MX51_PAD_CSI2_D15 = 118,
MX51_PAD_CSI2_D16 = 119,
MX51_PAD_CSI2_D17 = 120,
MX51_PAD_CSI2_D18 = 121,
MX51_PAD_CSI2_D19 = 122,
MX51_PAD_CSI2_VSYNC = 123,
MX51_PAD_CSI2_HSYNC = 124,
MX51_PAD_CSI2_PIXCLK = 125,
MX51_PAD_I2C1_CLK = 126,
MX51_PAD_I2C1_DAT = 127,
MX51_PAD_AUD3_BB_TXD = 128,
MX51_PAD_AUD3_BB_RXD = 129,
MX51_PAD_AUD3_BB_CK = 130,
MX51_PAD_AUD3_BB_FS = 131,
MX51_PAD_CSPI1_MOSI = 132,
MX51_PAD_CSPI1_MISO = 133,
MX51_PAD_CSPI1_SS0 = 134,
MX51_PAD_CSPI1_SS1 = 135,
MX51_PAD_CSPI1_RDY = 136,
MX51_PAD_CSPI1_SCLK = 137,
MX51_PAD_UART1_RXD = 138,
MX51_PAD_UART1_TXD = 139,
MX51_PAD_UART1_RTS = 140,
MX51_PAD_UART1_CTS = 141,
MX51_PAD_UART2_RXD = 142,
MX51_PAD_UART2_TXD = 143,
MX51_PAD_UART3_RXD = 144,
MX51_PAD_UART3_TXD = 145,
MX51_PAD_OWIRE_LINE = 146,
MX51_PAD_KEY_ROW0 = 147,
MX51_PAD_KEY_ROW1 = 148,
MX51_PAD_KEY_ROW2 = 149,
MX51_PAD_KEY_ROW3 = 150,
MX51_PAD_KEY_COL0 = 151,
MX51_PAD_KEY_COL1 = 152,
MX51_PAD_KEY_COL2 = 153,
MX51_PAD_KEY_COL3 = 154,
MX51_PAD_KEY_COL4 = 155,
MX51_PAD_KEY_COL5 = 156,
MX51_PAD_RESERVE7 = 157,
MX51_PAD_USBH1_CLK = 158,
MX51_PAD_USBH1_DIR = 159,
MX51_PAD_USBH1_STP = 160,
MX51_PAD_USBH1_NXT = 161,
MX51_PAD_USBH1_DATA0 = 162,
MX51_PAD_USBH1_DATA1 = 163,
MX51_PAD_USBH1_DATA2 = 164,
MX51_PAD_USBH1_DATA3 = 165,
MX51_PAD_USBH1_DATA4 = 166,
MX51_PAD_USBH1_DATA5 = 167,
MX51_PAD_USBH1_DATA6 = 168,
MX51_PAD_USBH1_DATA7 = 169,
MX51_PAD_DI1_PIN11 = 170,
MX51_PAD_DI1_PIN12 = 171,
MX51_PAD_DI1_PIN13 = 172,
MX51_PAD_DI1_D0_CS = 173,
MX51_PAD_DI1_D1_CS = 174,
MX51_PAD_DISPB2_SER_DIN = 175,
MX51_PAD_DISPB2_SER_DIO = 176,
MX51_PAD_DISPB2_SER_CLK = 177,
MX51_PAD_DISPB2_SER_RS = 178,
MX51_PAD_DISP1_DAT0 = 179,
MX51_PAD_DISP1_DAT1 = 180,
MX51_PAD_DISP1_DAT2 = 181,
MX51_PAD_DISP1_DAT3 = 182,
MX51_PAD_DISP1_DAT4 = 183,
MX51_PAD_DISP1_DAT5 = 184,
MX51_PAD_DISP1_DAT6 = 185,
MX51_PAD_DISP1_DAT7 = 186,
MX51_PAD_DISP1_DAT8 = 187,
MX51_PAD_DISP1_DAT9 = 188,
MX51_PAD_DISP1_DAT10 = 189,
MX51_PAD_DISP1_DAT11 = 190,
MX51_PAD_DISP1_DAT12 = 191,
MX51_PAD_DISP1_DAT13 = 192,
MX51_PAD_DISP1_DAT14 = 193,
MX51_PAD_DISP1_DAT15 = 194,
MX51_PAD_DISP1_DAT16 = 195,
MX51_PAD_DISP1_DAT17 = 196,
MX51_PAD_DISP1_DAT18 = 197,
MX51_PAD_DISP1_DAT19 = 198,
MX51_PAD_DISP1_DAT20 = 199,
MX51_PAD_DISP1_DAT21 = 200,
MX51_PAD_DISP1_DAT22 = 201,
MX51_PAD_DISP1_DAT23 = 202,
MX51_PAD_DI1_PIN3 = 203,
MX51_PAD_DI1_PIN2 = 204,
MX51_PAD_RESERVE8 = 205,
MX51_PAD_DI_GP2 = 206,
MX51_PAD_DI_GP3 = 207,
MX51_PAD_DI2_PIN4 = 208,
MX51_PAD_DI2_PIN2 = 209,
MX51_PAD_DI2_PIN3 = 210,
MX51_PAD_DI2_DISP_CLK = 211,
MX51_PAD_DI_GP4 = 212,
MX51_PAD_DISP2_DAT0 = 213,
MX51_PAD_DISP2_DAT1 = 214,
MX51_PAD_DISP2_DAT2 = 215,
MX51_PAD_DISP2_DAT3 = 216,
MX51_PAD_DISP2_DAT4 = 217,
MX51_PAD_DISP2_DAT5 = 218,
MX51_PAD_DISP2_DAT6 = 219,
MX51_PAD_DISP2_DAT7 = 220,
MX51_PAD_DISP2_DAT8 = 221,
MX51_PAD_DISP2_DAT9 = 222,
MX51_PAD_DISP2_DAT10 = 223,
MX51_PAD_DISP2_DAT11 = 224,
MX51_PAD_DISP2_DAT12 = 225,
MX51_PAD_DISP2_DAT13 = 226,
MX51_PAD_DISP2_DAT14 = 227,
MX51_PAD_DISP2_DAT15 = 228,
MX51_PAD_SD1_CMD = 229,
MX51_PAD_SD1_CLK = 230,
MX51_PAD_SD1_DATA0 = 231,
MX51_PAD_SD1_DATA1 = 232,
MX51_PAD_SD1_DATA2 = 233,
MX51_PAD_SD1_DATA3 = 234,
MX51_PAD_GPIO1_0 = 235,
MX51_PAD_GPIO1_1 = 236,
MX51_PAD_SD2_CMD = 237,
MX51_PAD_SD2_CLK = 238,
MX51_PAD_SD2_DATA0 = 239,
MX51_PAD_SD2_DATA1 = 240,
MX51_PAD_SD2_DATA2 = 241,
MX51_PAD_SD2_DATA3 = 242,
MX51_PAD_GPIO1_2 = 243,
MX51_PAD_GPIO1_3 = 244,
MX51_PAD_PMIC_INT_REQ = 245,
MX51_PAD_GPIO1_4 = 246,
MX51_PAD_GPIO1_5 = 247,
MX51_PAD_GPIO1_6 = 248,
MX51_PAD_GPIO1_7 = 249,
MX51_PAD_GPIO1_8 = 250,
MX51_PAD_GPIO1_9 = 251,
MX51_PAD_RESERVE9 = 252,
MX51_PAD_RESERVE10 = 253,
MX51_PAD_RESERVE11 = 254,
MX51_PAD_RESERVE12 = 255,
MX51_PAD_RESERVE13 = 256,
MX51_PAD_RESERVE14 = 257,
MX51_PAD_RESERVE15 = 258,
MX51_PAD_RESERVE16 = 259,
MX51_PAD_RESERVE17 = 260,
MX51_PAD_RESERVE18 = 261,
MX51_PAD_RESERVE19 = 262,
MX51_PAD_RESERVE20 = 263,
MX51_PAD_RESERVE21 = 264,
MX51_PAD_RESERVE22 = 265,
MX51_PAD_RESERVE23 = 266,
MX51_PAD_RESERVE24 = 267,
MX51_PAD_RESERVE25 = 268,
MX51_PAD_RESERVE26 = 269,
MX51_PAD_RESERVE27 = 270,
MX51_PAD_RESERVE28 = 271,
MX51_PAD_RESERVE29 = 272,
MX51_PAD_RESERVE30 = 273,
MX51_PAD_RESERVE31 = 274,
MX51_PAD_RESERVE32 = 275,
MX51_PAD_RESERVE33 = 276,
MX51_PAD_RESERVE34 = 277,
MX51_PAD_RESERVE35 = 278,
MX51_PAD_RESERVE36 = 279,
MX51_PAD_RESERVE37 = 280,
MX51_PAD_RESERVE38 = 281,
MX51_PAD_RESERVE39 = 282,
MX51_PAD_RESERVE40 = 283,
MX51_PAD_RESERVE41 = 284,
MX51_PAD_RESERVE42 = 285,
MX51_PAD_RESERVE43 = 286,
MX51_PAD_RESERVE44 = 287,
MX51_PAD_RESERVE45 = 288,
MX51_PAD_RESERVE46 = 289,
MX51_PAD_RESERVE47 = 290,
MX51_PAD_RESERVE48 = 291,
MX51_PAD_RESERVE49 = 292,
MX51_PAD_RESERVE50 = 293,
MX51_PAD_RESERVE51 = 294,
MX51_PAD_RESERVE52 = 295,
MX51_PAD_RESERVE53 = 296,
MX51_PAD_RESERVE54 = 297,
MX51_PAD_RESERVE55 = 298,
MX51_PAD_RESERVE56 = 299,
MX51_PAD_RESERVE57 = 300,
MX51_PAD_RESERVE58 = 301,
MX51_PAD_RESERVE59 = 302,
MX51_PAD_RESERVE60 = 303,
MX51_PAD_RESERVE61 = 304,
MX51_PAD_RESERVE62 = 305,
MX51_PAD_RESERVE63 = 306,
MX51_PAD_RESERVE64 = 307,
MX51_PAD_RESERVE65 = 308,
MX51_PAD_RESERVE66 = 309,
MX51_PAD_RESERVE67 = 310,
MX51_PAD_RESERVE68 = 311,
MX51_PAD_RESERVE69 = 312,
MX51_PAD_RESERVE70 = 313,
MX51_PAD_RESERVE71 = 314,
MX51_PAD_RESERVE72 = 315,
MX51_PAD_RESERVE73 = 316,
MX51_PAD_RESERVE74 = 317,
MX51_PAD_RESERVE75 = 318,
MX51_PAD_RESERVE76 = 319,
MX51_PAD_RESERVE77 = 320,
MX51_PAD_RESERVE78 = 321,
MX51_PAD_RESERVE79 = 322,
MX51_PAD_RESERVE80 = 323,
MX51_PAD_RESERVE81 = 324,
MX51_PAD_RESERVE82 = 325,
MX51_PAD_RESERVE83 = 326,
MX51_PAD_RESERVE84 = 327,
MX51_PAD_RESERVE85 = 328,
MX51_PAD_RESERVE86 = 329,
MX51_PAD_RESERVE87 = 330,
MX51_PAD_RESERVE88 = 331,
MX51_PAD_RESERVE89 = 332,
MX51_PAD_RESERVE90 = 333,
MX51_PAD_RESERVE91 = 334,
MX51_PAD_RESERVE92 = 335,
MX51_PAD_RESERVE93 = 336,
MX51_PAD_RESERVE94 = 337,
MX51_PAD_RESERVE95 = 338,
MX51_PAD_RESERVE96 = 339,
MX51_PAD_RESERVE97 = 340,
MX51_PAD_RESERVE98 = 341,
MX51_PAD_RESERVE99 = 342,
MX51_PAD_RESERVE100 = 343,
MX51_PAD_RESERVE101 = 344,
MX51_PAD_RESERVE102 = 345,
MX51_PAD_RESERVE103 = 346,
MX51_PAD_RESERVE104 = 347,
MX51_PAD_RESERVE105 = 348,
MX51_PAD_RESERVE106 = 349,
MX51_PAD_RESERVE107 = 350,
MX51_PAD_RESERVE108 = 351,
MX51_PAD_RESERVE109 = 352,
MX51_PAD_RESERVE110 = 353,
MX51_PAD_RESERVE111 = 354,
MX51_PAD_RESERVE112 = 355,
MX51_PAD_RESERVE113 = 356,
MX51_PAD_RESERVE114 = 357,
MX51_PAD_RESERVE115 = 358,
MX51_PAD_RESERVE116 = 359,
MX51_PAD_RESERVE117 = 360,
MX51_PAD_RESERVE118 = 361,
MX51_PAD_RESERVE119 = 362,
MX51_PAD_RESERVE120 = 363,
MX51_PAD_RESERVE121 = 364,
MX51_PAD_CSI1_PIXCLK = 365,
MX51_PAD_CSI1_MCLK = 366,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE19),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE20),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE21),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE22),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE23),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE24),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE25),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE26),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE27),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE28),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE29),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE30),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE31),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE32),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE33),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE34),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE35),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE36),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE37),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE38),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE39),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE40),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE41),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE42),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE43),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE44),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE45),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE46),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE47),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE48),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE49),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE50),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE51),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE52),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE53),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE54),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE55),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE56),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE57),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE58),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE59),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE60),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE61),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE62),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE63),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE64),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE65),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE66),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE67),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE68),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE69),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE70),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE71),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE72),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE73),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE74),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE75),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE76),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE77),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE78),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE79),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE80),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE81),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE82),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE83),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE84),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE85),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE86),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE87),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE88),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE89),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE90),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE91),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE92),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE93),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE94),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE95),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE96),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE97),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE98),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE99),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE100),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE101),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE102),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE103),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE104),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE105),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE106),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE107),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE108),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE109),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE110),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE111),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE112),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE113),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE114),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE115),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE116),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE117),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE118),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE119),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE120),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE121),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
};
static const struct imx_pinctrl_soc_info imx51_pinctrl_info = {
.pins = imx51_pinctrl_pads,
.npins = ARRAY_SIZE(imx51_pinctrl_pads),
};
static const struct of_device_id imx51_pinctrl_of_match[] = {
{ .compatible = "fsl,imx51-iomuxc", },
{ /* sentinel */ }
};
static int imx51_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
}
static struct platform_driver imx51_pinctrl_driver = {
.driver = {
.name = "imx51-pinctrl",
.of_match_table = imx51_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx51_pinctrl_probe,
};
static int __init imx51_pinctrl_init(void)
{
return platform_driver_register(&imx51_pinctrl_driver);
}
arch_initcall(imx51_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx51.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Freescale imx6sx pinctrl driver
//
// Author: Anson Huang <[email protected]>
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sx_pads {
MX6Sx_PAD_RESERVE0 = 0,
MX6Sx_PAD_RESERVE1 = 1,
MX6Sx_PAD_RESERVE2 = 2,
MX6Sx_PAD_RESERVE3 = 3,
MX6Sx_PAD_RESERVE4 = 4,
MX6SX_PAD_GPIO1_IO00 = 5,
MX6SX_PAD_GPIO1_IO01 = 6,
MX6SX_PAD_GPIO1_IO02 = 7,
MX6SX_PAD_GPIO1_IO03 = 8,
MX6SX_PAD_GPIO1_IO04 = 9,
MX6SX_PAD_GPIO1_IO05 = 10,
MX6SX_PAD_GPIO1_IO06 = 11,
MX6SX_PAD_GPIO1_IO07 = 12,
MX6SX_PAD_GPIO1_IO08 = 13,
MX6SX_PAD_GPIO1_IO09 = 14,
MX6SX_PAD_GPIO1_IO10 = 15,
MX6SX_PAD_GPIO1_IO11 = 16,
MX6SX_PAD_GPIO1_IO12 = 17,
MX6SX_PAD_GPIO1_IO13 = 18,
MX6SX_PAD_CSI_DATA00 = 19,
MX6SX_PAD_CSI_DATA01 = 20,
MX6SX_PAD_CSI_DATA02 = 21,
MX6SX_PAD_CSI_DATA03 = 22,
MX6SX_PAD_CSI_DATA04 = 23,
MX6SX_PAD_CSI_DATA05 = 24,
MX6SX_PAD_CSI_DATA06 = 25,
MX6SX_PAD_CSI_DATA07 = 26,
MX6SX_PAD_CSI_HSYNC = 27,
MX6SX_PAD_CSI_MCLK = 28,
MX6SX_PAD_CSI_PIXCLK = 29,
MX6SX_PAD_CSI_VSYNC = 30,
MX6SX_PAD_ENET1_COL = 31,
MX6SX_PAD_ENET1_CRS = 32,
MX6SX_PAD_ENET1_MDC = 33,
MX6SX_PAD_ENET1_MDIO = 34,
MX6SX_PAD_ENET1_RX_CLK = 35,
MX6SX_PAD_ENET1_TX_CLK = 36,
MX6SX_PAD_ENET2_COL = 37,
MX6SX_PAD_ENET2_CRS = 38,
MX6SX_PAD_ENET2_RX_CLK = 39,
MX6SX_PAD_ENET2_TX_CLK = 40,
MX6SX_PAD_KEY_COL0 = 41,
MX6SX_PAD_KEY_COL1 = 42,
MX6SX_PAD_KEY_COL2 = 43,
MX6SX_PAD_KEY_COL3 = 44,
MX6SX_PAD_KEY_COL4 = 45,
MX6SX_PAD_KEY_ROW0 = 46,
MX6SX_PAD_KEY_ROW1 = 47,
MX6SX_PAD_KEY_ROW2 = 48,
MX6SX_PAD_KEY_ROW3 = 49,
MX6SX_PAD_KEY_ROW4 = 50,
MX6SX_PAD_LCD1_CLK = 51,
MX6SX_PAD_LCD1_DATA00 = 52,
MX6SX_PAD_LCD1_DATA01 = 53,
MX6SX_PAD_LCD1_DATA02 = 54,
MX6SX_PAD_LCD1_DATA03 = 55,
MX6SX_PAD_LCD1_DATA04 = 56,
MX6SX_PAD_LCD1_DATA05 = 57,
MX6SX_PAD_LCD1_DATA06 = 58,
MX6SX_PAD_LCD1_DATA07 = 59,
MX6SX_PAD_LCD1_DATA08 = 60,
MX6SX_PAD_LCD1_DATA09 = 61,
MX6SX_PAD_LCD1_DATA10 = 62,
MX6SX_PAD_LCD1_DATA11 = 63,
MX6SX_PAD_LCD1_DATA12 = 64,
MX6SX_PAD_LCD1_DATA13 = 65,
MX6SX_PAD_LCD1_DATA14 = 66,
MX6SX_PAD_LCD1_DATA15 = 67,
MX6SX_PAD_LCD1_DATA16 = 68,
MX6SX_PAD_LCD1_DATA17 = 69,
MX6SX_PAD_LCD1_DATA18 = 70,
MX6SX_PAD_LCD1_DATA19 = 71,
MX6SX_PAD_LCD1_DATA20 = 72,
MX6SX_PAD_LCD1_DATA21 = 73,
MX6SX_PAD_LCD1_DATA22 = 74,
MX6SX_PAD_LCD1_DATA23 = 75,
MX6SX_PAD_LCD1_ENABLE = 76,
MX6SX_PAD_LCD1_HSYNC = 77,
MX6SX_PAD_LCD1_RESET = 78,
MX6SX_PAD_LCD1_VSYNC = 79,
MX6SX_PAD_NAND_ALE = 80,
MX6SX_PAD_NAND_CE0_B = 81,
MX6SX_PAD_NAND_CE1_B = 82,
MX6SX_PAD_NAND_CLE = 83,
MX6SX_PAD_NAND_DATA00 = 84 ,
MX6SX_PAD_NAND_DATA01 = 85,
MX6SX_PAD_NAND_DATA02 = 86,
MX6SX_PAD_NAND_DATA03 = 87,
MX6SX_PAD_NAND_DATA04 = 88,
MX6SX_PAD_NAND_DATA05 = 89,
MX6SX_PAD_NAND_DATA06 = 90,
MX6SX_PAD_NAND_DATA07 = 91,
MX6SX_PAD_NAND_RE_B = 92,
MX6SX_PAD_NAND_READY_B = 93,
MX6SX_PAD_NAND_WE_B = 94,
MX6SX_PAD_NAND_WP_B = 95,
MX6SX_PAD_QSPI1A_DATA0 = 96,
MX6SX_PAD_QSPI1A_DATA1 = 97,
MX6SX_PAD_QSPI1A_DATA2 = 98,
MX6SX_PAD_QSPI1A_DATA3 = 99,
MX6SX_PAD_QSPI1A_DQS = 100,
MX6SX_PAD_QSPI1A_SCLK = 101,
MX6SX_PAD_QSPI1A_SS0_B = 102,
MX6SX_PAD_QSPI1A_SS1_B = 103,
MX6SX_PAD_QSPI1B_DATA0 = 104,
MX6SX_PAD_QSPI1B_DATA1 = 105,
MX6SX_PAD_QSPI1B_DATA2 = 106,
MX6SX_PAD_QSPI1B_DATA3 = 107,
MX6SX_PAD_QSPI1B_DQS = 108,
MX6SX_PAD_QSPI1B_SCLK = 109,
MX6SX_PAD_QSPI1B_SS0_B = 110,
MX6SX_PAD_QSPI1B_SS1_B = 111,
MX6SX_PAD_RGMII1_RD0 = 112,
MX6SX_PAD_RGMII1_RD1 = 113,
MX6SX_PAD_RGMII1_RD2 = 114,
MX6SX_PAD_RGMII1_RD3 = 115,
MX6SX_PAD_RGMII1_RX_CTL = 116,
MX6SX_PAD_RGMII1_RXC = 117,
MX6SX_PAD_RGMII1_TD0 = 118,
MX6SX_PAD_RGMII1_TD1 = 119,
MX6SX_PAD_RGMII1_TD2 = 120,
MX6SX_PAD_RGMII1_TD3 = 121,
MX6SX_PAD_RGMII1_TX_CTL = 122,
MX6SX_PAD_RGMII1_TXC = 123,
MX6SX_PAD_RGMII2_RD0 = 124,
MX6SX_PAD_RGMII2_RD1 = 125,
MX6SX_PAD_RGMII2_RD2 = 126,
MX6SX_PAD_RGMII2_RD3 = 127,
MX6SX_PAD_RGMII2_RX_CTL = 128,
MX6SX_PAD_RGMII2_RXC = 129,
MX6SX_PAD_RGMII2_TD0 = 130,
MX6SX_PAD_RGMII2_TD1 = 131,
MX6SX_PAD_RGMII2_TD2 = 132,
MX6SX_PAD_RGMII2_TD3 = 133,
MX6SX_PAD_RGMII2_TX_CTL = 134,
MX6SX_PAD_RGMII2_TXC = 135,
MX6SX_PAD_SD1_CLK = 136,
MX6SX_PAD_SD1_CMD = 137,
MX6SX_PAD_SD1_DATA0 = 138,
MX6SX_PAD_SD1_DATA1 = 139,
MX6SX_PAD_SD1_DATA2 = 140,
MX6SX_PAD_SD1_DATA3 = 141,
MX6SX_PAD_SD2_CLK = 142,
MX6SX_PAD_SD2_CMD = 143,
MX6SX_PAD_SD2_DATA0 = 144,
MX6SX_PAD_SD2_DATA1 = 145,
MX6SX_PAD_SD2_DATA2 = 146,
MX6SX_PAD_SD2_DATA3 = 147,
MX6SX_PAD_SD3_CLK = 148,
MX6SX_PAD_SD3_CMD = 149,
MX6SX_PAD_SD3_DATA0 = 150,
MX6SX_PAD_SD3_DATA1 = 151,
MX6SX_PAD_SD3_DATA2 = 152,
MX6SX_PAD_SD3_DATA3 = 153,
MX6SX_PAD_SD3_DATA4 = 154,
MX6SX_PAD_SD3_DATA5 = 155,
MX6SX_PAD_SD3_DATA6 = 156,
MX6SX_PAD_SD3_DATA7 = 157,
MX6SX_PAD_SD4_CLK = 158,
MX6SX_PAD_SD4_CMD = 159,
MX6SX_PAD_SD4_DATA0 = 160,
MX6SX_PAD_SD4_DATA1 = 161,
MX6SX_PAD_SD4_DATA2 = 162,
MX6SX_PAD_SD4_DATA3 = 163,
MX6SX_PAD_SD4_DATA4 = 164,
MX6SX_PAD_SD4_DATA5 = 165,
MX6SX_PAD_SD4_DATA6 = 166,
MX6SX_PAD_SD4_DATA7 = 167,
MX6SX_PAD_SD4_RESET_B = 168,
MX6SX_PAD_USB_H_DATA = 169,
MX6SX_PAD_USB_H_STROBE = 170,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
};
static const struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.pins = imx6sx_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
.gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
};
static const struct of_device_id imx6sx_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sx-iomuxc", },
{ /* sentinel */ }
};
static int imx6sx_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
}
static struct platform_driver imx6sx_pinctrl_driver = {
.driver = {
.name = "imx6sx-pinctrl",
.of_match_table = imx6sx_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sx_pinctrl_probe,
};
static int __init imx6sx_pinctrl_init(void)
{
return platform_driver_register(&imx6sx_pinctrl_driver);
}
arch_initcall(imx6sx_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6sx.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx93_pads {
IMX93_IOMUXC_DAP_TDI = 0,
IMX93_IOMUXC_DAP_TMS_SWDIO = 1,
IMX93_IOMUXC_DAP_TCLK_SWCLK = 2,
IMX93_IOMUXC_DAP_TDO_TRACESWO = 3,
IMX93_IOMUXC_GPIO_IO00 = 4,
IMX93_IOMUXC_GPIO_IO01 = 5,
IMX93_IOMUXC_GPIO_IO02 = 6,
IMX93_IOMUXC_GPIO_IO03 = 7,
IMX93_IOMUXC_GPIO_IO04 = 8,
IMX93_IOMUXC_GPIO_IO05 = 9,
IMX93_IOMUXC_GPIO_IO06 = 10,
IMX93_IOMUXC_GPIO_IO07 = 11,
IMX93_IOMUXC_GPIO_IO08 = 12,
IMX93_IOMUXC_GPIO_IO09 = 13,
IMX93_IOMUXC_GPIO_IO10 = 14,
IMX93_IOMUXC_GPIO_IO11 = 15,
IMX93_IOMUXC_GPIO_IO12 = 16,
IMX93_IOMUXC_GPIO_IO13 = 17,
IMX93_IOMUXC_GPIO_IO14 = 18,
IMX93_IOMUXC_GPIO_IO15 = 19,
IMX93_IOMUXC_GPIO_IO16 = 20,
IMX93_IOMUXC_GPIO_IO17 = 21,
IMX93_IOMUXC_GPIO_IO18 = 22,
IMX93_IOMUXC_GPIO_IO19 = 23,
IMX93_IOMUXC_GPIO_IO20 = 24,
IMX93_IOMUXC_GPIO_IO21 = 25,
IMX93_IOMUXC_GPIO_IO22 = 26,
IMX93_IOMUXC_GPIO_IO23 = 27,
IMX93_IOMUXC_GPIO_IO24 = 28,
IMX93_IOMUXC_GPIO_IO25 = 29,
IMX93_IOMUXC_GPIO_IO26 = 30,
IMX93_IOMUXC_GPIO_IO27 = 31,
IMX93_IOMUXC_GPIO_IO28 = 32,
IMX93_IOMUXC_GPIO_IO29 = 33,
IMX93_IOMUXC_CCM_CLKO1 = 34,
IMX93_IOMUXC_CCM_CLKO2 = 35,
IMX93_IOMUXC_CCM_CLKO3 = 36,
IMX93_IOMUXC_CCM_CLKO4 = 37,
IMX93_IOMUXC_ENET1_MDC = 38,
IMX93_IOMUXC_ENET1_MDIO = 39,
IMX93_IOMUXC_ENET1_TD3 = 40,
IMX93_IOMUXC_ENET1_TD2 = 41,
IMX93_IOMUXC_ENET1_TD1 = 42,
IMX93_IOMUXC_ENET1_TD0 = 43,
IMX93_IOMUXC_ENET1_TX_CTL = 44,
IMX93_IOMUXC_ENET1_TXC = 45,
IMX93_IOMUXC_ENET1_RX_CTL = 46,
IMX93_IOMUXC_ENET1_RXC = 47,
IMX93_IOMUXC_ENET1_RD0 = 48,
IMX93_IOMUXC_ENET1_RD1 = 49,
IMX93_IOMUXC_ENET1_RD2 = 50,
IMX93_IOMUXC_ENET1_RD3 = 51,
IMX93_IOMUXC_ENET2_MDC = 52,
IMX93_IOMUXC_ENET2_MDIO = 53,
IMX93_IOMUXC_ENET2_TD3 = 54,
IMX93_IOMUXC_ENET2_TD2 = 55,
IMX93_IOMUXC_ENET2_TD1 = 56,
IMX93_IOMUXC_ENET2_TD0 = 57,
IMX93_IOMUXC_ENET2_TX_CTL = 58,
IMX93_IOMUXC_ENET2_TXC = 59,
IMX93_IOMUXC_ENET2_RX_CTL = 60,
IMX93_IOMUXC_ENET2_RXC = 61,
IMX93_IOMUXC_ENET2_RD0 = 62,
IMX93_IOMUXC_ENET2_RD1 = 63,
IMX93_IOMUXC_ENET2_RD2 = 64,
IMX93_IOMUXC_ENET2_RD3 = 65,
IMX93_IOMUXC_SD1_CLK = 66,
IMX93_IOMUXC_SD1_CMD = 67,
IMX93_IOMUXC_SD1_DATA0 = 68,
IMX93_IOMUXC_SD1_DATA1 = 69,
IMX93_IOMUXC_SD1_DATA2 = 70,
IMX93_IOMUXC_SD1_DATA3 = 71,
IMX93_IOMUXC_SD1_DATA4 = 72,
IMX93_IOMUXC_SD1_DATA5 = 73,
IMX93_IOMUXC_SD1_DATA6 = 74,
IMX93_IOMUXC_SD1_DATA7 = 75,
IMX93_IOMUXC_SD1_STROBE = 76,
IMX93_IOMUXC_SD2_VSELECT = 77,
IMX93_IOMUXC_SD3_CLK = 78,
IMX93_IOMUXC_SD3_CMD = 79,
IMX93_IOMUXC_SD3_DATA0 = 80,
IMX93_IOMUXC_SD3_DATA1 = 81,
IMX93_IOMUXC_SD3_DATA2 = 82,
IMX93_IOMUXC_SD3_DATA3 = 83,
IMX93_IOMUXC_SD2_CD_B = 84,
IMX93_IOMUXC_SD2_CLK = 85,
IMX93_IOMUXC_SD2_CMD = 86,
IMX93_IOMUXC_SD2_DATA0 = 87,
IMX93_IOMUXC_SD2_DATA1 = 88,
IMX93_IOMUXC_SD2_DATA2 = 89,
IMX93_IOMUXC_SD2_DATA3 = 90,
IMX93_IOMUXC_SD2_RESET_B = 91,
IMX93_IOMUXC_I2C1_SCL = 92,
IMX93_IOMUXC_I2C1_SDA = 93,
IMX93_IOMUXC_I2C2_SCL = 94,
IMX93_IOMUXC_I2C2_SDA = 95,
IMX93_IOMUXC_UART1_RXD = 96,
IMX93_IOMUXC_UART1_TXD = 97,
IMX93_IOMUXC_UART2_RXD = 98,
IMX93_IOMUXC_UART2_TXD = 99,
IMX93_IOMUXC_PDM_CLK = 100,
IMX93_IOMUXC_PDM_BIT_STREAM0 = 101,
IMX93_IOMUXC_PDM_BIT_STREAM1 = 102,
IMX93_IOMUXC_SAI1_TXFS = 103,
IMX93_IOMUXC_SAI1_TXC = 104,
IMX93_IOMUXC_SAI1_TXD0 = 105,
IMX93_IOMUXC_SAI1_RXD0 = 106,
IMX93_IOMUXC_WDOG_ANY = 107,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28),
IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY),
};
static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {
.pins = imx93_pinctrl_pads,
.npins = ARRAY_SIZE(imx93_pinctrl_pads),
.flags = ZERO_OFFSET_VALID,
.gpr_compatible = "fsl,imx93-iomuxc-gpr",
};
static const struct of_device_id imx93_pinctrl_of_match[] = {
{ .compatible = "fsl,imx93-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx93_pinctrl_of_match);
static int imx93_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx93_pinctrl_info);
}
static struct platform_driver imx93_pinctrl_driver = {
.driver = {
.name = "imx93-pinctrl",
.of_match_table = imx93_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx93_pinctrl_probe,
};
static int __init imx93_pinctrl_init(void)
{
return platform_driver_register(&imx93_pinctrl_driver);
}
arch_initcall(imx93_pinctrl_init);
MODULE_AUTHOR("Bai Ping <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx93.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022
* Author(s): Jesse Taube <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imxrt1170_pads {
IMXRT1170_PAD_RESERVE0,
IMXRT1170_PAD_RESERVE1,
IMXRT1170_PAD_RESERVE2,
IMXRT1170_PAD_RESERVE3,
IMXRT1170_PAD_EMC_B1_00,
IMXRT1170_PAD_EMC_B1_01,
IMXRT1170_PAD_EMC_B1_02,
IMXRT1170_PAD_EMC_B1_03,
IMXRT1170_PAD_EMC_B1_04,
IMXRT1170_PAD_EMC_B1_05,
IMXRT1170_PAD_EMC_B1_06,
IMXRT1170_PAD_EMC_B1_07,
IMXRT1170_PAD_EMC_B1_08,
IMXRT1170_PAD_EMC_B1_09,
IMXRT1170_PAD_EMC_B1_10,
IMXRT1170_PAD_EMC_B1_11,
IMXRT1170_PAD_EMC_B1_12,
IMXRT1170_PAD_EMC_B1_13,
IMXRT1170_PAD_EMC_B1_14,
IMXRT1170_PAD_EMC_B1_15,
IMXRT1170_PAD_EMC_B1_16,
IMXRT1170_PAD_EMC_B1_17,
IMXRT1170_PAD_EMC_B1_18,
IMXRT1170_PAD_EMC_B1_19,
IMXRT1170_PAD_EMC_B1_20,
IMXRT1170_PAD_EMC_B1_21,
IMXRT1170_PAD_EMC_B1_22,
IMXRT1170_PAD_EMC_B1_23,
IMXRT1170_PAD_EMC_B1_24,
IMXRT1170_PAD_EMC_B1_25,
IMXRT1170_PAD_EMC_B1_26,
IMXRT1170_PAD_EMC_B1_27,
IMXRT1170_PAD_EMC_B1_28,
IMXRT1170_PAD_EMC_B1_29,
IMXRT1170_PAD_EMC_B1_30,
IMXRT1170_PAD_EMC_B1_31,
IMXRT1170_PAD_EMC_B1_32,
IMXRT1170_PAD_EMC_B1_33,
IMXRT1170_PAD_EMC_B1_34,
IMXRT1170_PAD_EMC_B1_35,
IMXRT1170_PAD_EMC_B1_36,
IMXRT1170_PAD_EMC_B1_37,
IMXRT1170_PAD_EMC_B1_38,
IMXRT1170_PAD_EMC_B1_39,
IMXRT1170_PAD_EMC_B1_40,
IMXRT1170_PAD_EMC_B1_41,
IMXRT1170_PAD_EMC_B2_00,
IMXRT1170_PAD_EMC_B2_01,
IMXRT1170_PAD_EMC_B2_02,
IMXRT1170_PAD_EMC_B2_03,
IMXRT1170_PAD_EMC_B2_04,
IMXRT1170_PAD_EMC_B2_05,
IMXRT1170_PAD_EMC_B2_06,
IMXRT1170_PAD_EMC_B2_07,
IMXRT1170_PAD_EMC_B2_08,
IMXRT1170_PAD_EMC_B2_09,
IMXRT1170_PAD_EMC_B2_10,
IMXRT1170_PAD_EMC_B2_11,
IMXRT1170_PAD_EMC_B2_12,
IMXRT1170_PAD_EMC_B2_13,
IMXRT1170_PAD_EMC_B2_14,
IMXRT1170_PAD_EMC_B2_15,
IMXRT1170_PAD_EMC_B2_16,
IMXRT1170_PAD_EMC_B2_17,
IMXRT1170_PAD_EMC_B2_18,
IMXRT1170_PAD_EMC_B2_19,
IMXRT1170_PAD_EMC_B2_20,
IMXRT1170_PAD_AD_00,
IMXRT1170_PAD_AD_01,
IMXRT1170_PAD_AD_02,
IMXRT1170_PAD_AD_03,
IMXRT1170_PAD_AD_04,
IMXRT1170_PAD_AD_05,
IMXRT1170_PAD_AD_06,
IMXRT1170_PAD_AD_07,
IMXRT1170_PAD_AD_08,
IMXRT1170_PAD_AD_09,
IMXRT1170_PAD_AD_10,
IMXRT1170_PAD_AD_11,
IMXRT1170_PAD_AD_12,
IMXRT1170_PAD_AD_13,
IMXRT1170_PAD_AD_14,
IMXRT1170_PAD_AD_15,
IMXRT1170_PAD_AD_16,
IMXRT1170_PAD_AD_17,
IMXRT1170_PAD_AD_18,
IMXRT1170_PAD_AD_19,
IMXRT1170_PAD_AD_20,
IMXRT1170_PAD_AD_21,
IMXRT1170_PAD_AD_22,
IMXRT1170_PAD_AD_23,
IMXRT1170_PAD_AD_24,
IMXRT1170_PAD_AD_25,
IMXRT1170_PAD_AD_26,
IMXRT1170_PAD_AD_27,
IMXRT1170_PAD_AD_28,
IMXRT1170_PAD_AD_29,
IMXRT1170_PAD_AD_30,
IMXRT1170_PAD_AD_31,
IMXRT1170_PAD_AD_32,
IMXRT1170_PAD_AD_33,
IMXRT1170_PAD_AD_34,
IMXRT1170_PAD_AD_35,
IMXRT1170_PAD_SD_B1_00,
IMXRT1170_PAD_SD_B1_01,
IMXRT1170_PAD_SD_B1_02,
IMXRT1170_PAD_SD_B1_03,
IMXRT1170_PAD_SD_B1_04,
IMXRT1170_PAD_SD_B1_05,
IMXRT1170_PAD_SD_B2_00,
IMXRT1170_PAD_SD_B2_01,
IMXRT1170_PAD_SD_B2_02,
IMXRT1170_PAD_SD_B2_03,
IMXRT1170_PAD_SD_B2_04,
IMXRT1170_PAD_SD_B2_05,
IMXRT1170_PAD_SD_B2_06,
IMXRT1170_PAD_SD_B2_07,
IMXRT1170_PAD_SD_B2_08,
IMXRT1170_PAD_SD_B2_09,
IMXRT1170_PAD_SD_B2_10,
IMXRT1170_PAD_SD_B2_11,
IMXRT1170_PAD_DISP_B1_00,
IMXRT1170_PAD_DISP_B1_01,
IMXRT1170_PAD_DISP_B1_02,
IMXRT1170_PAD_DISP_B1_03,
IMXRT1170_PAD_DISP_B1_04,
IMXRT1170_PAD_DISP_B1_05,
IMXRT1170_PAD_DISP_B1_06,
IMXRT1170_PAD_DISP_B1_07,
IMXRT1170_PAD_DISP_B1_08,
IMXRT1170_PAD_DISP_B1_09,
IMXRT1170_PAD_DISP_B1_10,
IMXRT1170_PAD_DISP_B1_11,
IMXRT1170_PAD_DISP_B2_00,
IMXRT1170_PAD_DISP_B2_01,
IMXRT1170_PAD_DISP_B2_02,
IMXRT1170_PAD_DISP_B2_03,
IMXRT1170_PAD_DISP_B2_04,
IMXRT1170_PAD_DISP_B2_05,
IMXRT1170_PAD_DISP_B2_06,
IMXRT1170_PAD_DISP_B2_07,
IMXRT1170_PAD_DISP_B2_08,
IMXRT1170_PAD_DISP_B2_09,
IMXRT1170_PAD_DISP_B2_10,
IMXRT1170_PAD_DISP_B2_11,
IMXRT1170_PAD_DISP_B2_12,
IMXRT1170_PAD_DISP_B2_13,
IMXRT1170_PAD_DISP_B2_14,
IMXRT1170_PAD_DISP_B2_15,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imxrt1170_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_21),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_22),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_23),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_24),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_25),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_26),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_27),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_28),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_29),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_30),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_31),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_32),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_33),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_34),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_35),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_36),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_37),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_38),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_39),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_40),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_41),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_15),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_16),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_17),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_18),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_19),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_20),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_21),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_22),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_23),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_24),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_25),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_26),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_27),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_28),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_29),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_30),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_31),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_32),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_33),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_34),
IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_35),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_00),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_01),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_02),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_03),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_04),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_05),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_06),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_07),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_08),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_09),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_10),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_11),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_12),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_13),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_14),
IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_15),
};
static const struct imx_pinctrl_soc_info imxrt1170_pinctrl_info = {
.pins = imxrt1170_pinctrl_pads,
.npins = ARRAY_SIZE(imxrt1170_pinctrl_pads),
.gpr_compatible = "fsl,imxrt1170-iomuxc-gpr",
};
static const struct of_device_id imxrt1170_pinctrl_of_match[] = {
{ .compatible = "fsl,imxrt1170-iomuxc", .data = &imxrt1170_pinctrl_info, },
{ /* sentinel */ }
};
static int imxrt1170_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imxrt1170_pinctrl_info);
}
static struct platform_driver imxrt1170_pinctrl_driver = {
.driver = {
.name = "imxrt1170-pinctrl",
.of_match_table = of_match_ptr(imxrt1170_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imxrt1170_pinctrl_probe,
};
static int __init imxrt1170_pinctrl_init(void)
{
return platform_driver_register(&imxrt1170_pinctrl_driver);
}
arch_initcall(imxrt1170_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imxrt1170.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// VF610 pinctrl driver based on imx pinmux and pinconf core
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum vf610_pads {
VF610_PAD_PTA6 = 0,
VF610_PAD_PTA8 = 1,
VF610_PAD_PTA9 = 2,
VF610_PAD_PTA10 = 3,
VF610_PAD_PTA11 = 4,
VF610_PAD_PTA12 = 5,
VF610_PAD_PTA16 = 6,
VF610_PAD_PTA17 = 7,
VF610_PAD_PTA18 = 8,
VF610_PAD_PTA19 = 9,
VF610_PAD_PTA20 = 10,
VF610_PAD_PTA21 = 11,
VF610_PAD_PTA22 = 12,
VF610_PAD_PTA23 = 13,
VF610_PAD_PTA24 = 14,
VF610_PAD_PTA25 = 15,
VF610_PAD_PTA26 = 16,
VF610_PAD_PTA27 = 17,
VF610_PAD_PTA28 = 18,
VF610_PAD_PTA29 = 19,
VF610_PAD_PTA30 = 20,
VF610_PAD_PTA31 = 21,
VF610_PAD_PTB0 = 22,
VF610_PAD_PTB1 = 23,
VF610_PAD_PTB2 = 24,
VF610_PAD_PTB3 = 25,
VF610_PAD_PTB4 = 26,
VF610_PAD_PTB5 = 27,
VF610_PAD_PTB6 = 28,
VF610_PAD_PTB7 = 29,
VF610_PAD_PTB8 = 30,
VF610_PAD_PTB9 = 31,
VF610_PAD_PTB10 = 32,
VF610_PAD_PTB11 = 33,
VF610_PAD_PTB12 = 34,
VF610_PAD_PTB13 = 35,
VF610_PAD_PTB14 = 36,
VF610_PAD_PTB15 = 37,
VF610_PAD_PTB16 = 38,
VF610_PAD_PTB17 = 39,
VF610_PAD_PTB18 = 40,
VF610_PAD_PTB19 = 41,
VF610_PAD_PTB20 = 42,
VF610_PAD_PTB21 = 43,
VF610_PAD_PTB22 = 44,
VF610_PAD_PTC0 = 45,
VF610_PAD_PTC1 = 46,
VF610_PAD_PTC2 = 47,
VF610_PAD_PTC3 = 48,
VF610_PAD_PTC4 = 49,
VF610_PAD_PTC5 = 50,
VF610_PAD_PTC6 = 51,
VF610_PAD_PTC7 = 52,
VF610_PAD_PTC8 = 53,
VF610_PAD_PTC9 = 54,
VF610_PAD_PTC10 = 55,
VF610_PAD_PTC11 = 56,
VF610_PAD_PTC12 = 57,
VF610_PAD_PTC13 = 58,
VF610_PAD_PTC14 = 59,
VF610_PAD_PTC15 = 60,
VF610_PAD_PTC16 = 61,
VF610_PAD_PTC17 = 62,
VF610_PAD_PTD31 = 63,
VF610_PAD_PTD30 = 64,
VF610_PAD_PTD29 = 65,
VF610_PAD_PTD28 = 66,
VF610_PAD_PTD27 = 67,
VF610_PAD_PTD26 = 68,
VF610_PAD_PTD25 = 69,
VF610_PAD_PTD24 = 70,
VF610_PAD_PTD23 = 71,
VF610_PAD_PTD22 = 72,
VF610_PAD_PTD21 = 73,
VF610_PAD_PTD20 = 74,
VF610_PAD_PTD19 = 75,
VF610_PAD_PTD18 = 76,
VF610_PAD_PTD17 = 77,
VF610_PAD_PTD16 = 78,
VF610_PAD_PTD0 = 79,
VF610_PAD_PTD1 = 80,
VF610_PAD_PTD2 = 81,
VF610_PAD_PTD3 = 82,
VF610_PAD_PTD4 = 83,
VF610_PAD_PTD5 = 84,
VF610_PAD_PTD6 = 85,
VF610_PAD_PTD7 = 86,
VF610_PAD_PTD8 = 87,
VF610_PAD_PTD9 = 88,
VF610_PAD_PTD10 = 89,
VF610_PAD_PTD11 = 90,
VF610_PAD_PTD12 = 91,
VF610_PAD_PTD13 = 92,
VF610_PAD_PTB23 = 93,
VF610_PAD_PTB24 = 94,
VF610_PAD_PTB25 = 95,
VF610_PAD_PTB26 = 96,
VF610_PAD_PTB27 = 97,
VF610_PAD_PTB28 = 98,
VF610_PAD_PTC26 = 99,
VF610_PAD_PTC27 = 100,
VF610_PAD_PTC28 = 101,
VF610_PAD_PTC29 = 102,
VF610_PAD_PTC30 = 103,
VF610_PAD_PTC31 = 104,
VF610_PAD_PTE0 = 105,
VF610_PAD_PTE1 = 106,
VF610_PAD_PTE2 = 107,
VF610_PAD_PTE3 = 108,
VF610_PAD_PTE4 = 109,
VF610_PAD_PTE5 = 110,
VF610_PAD_PTE6 = 111,
VF610_PAD_PTE7 = 112,
VF610_PAD_PTE8 = 113,
VF610_PAD_PTE9 = 114,
VF610_PAD_PTE10 = 115,
VF610_PAD_PTE11 = 116,
VF610_PAD_PTE12 = 117,
VF610_PAD_PTE13 = 118,
VF610_PAD_PTE14 = 119,
VF610_PAD_PTE15 = 120,
VF610_PAD_PTE16 = 121,
VF610_PAD_PTE17 = 122,
VF610_PAD_PTE18 = 123,
VF610_PAD_PTE19 = 124,
VF610_PAD_PTE20 = 125,
VF610_PAD_PTE21 = 126,
VF610_PAD_PTE22 = 127,
VF610_PAD_PTE23 = 128,
VF610_PAD_PTE24 = 129,
VF610_PAD_PTE25 = 130,
VF610_PAD_PTE26 = 131,
VF610_PAD_PTE27 = 132,
VF610_PAD_PTE28 = 133,
VF610_PAD_PTA7 = 134,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
IMX_PINCTRL_PIN(VF610_PAD_PTA6),
IMX_PINCTRL_PIN(VF610_PAD_PTA8),
IMX_PINCTRL_PIN(VF610_PAD_PTA9),
IMX_PINCTRL_PIN(VF610_PAD_PTA10),
IMX_PINCTRL_PIN(VF610_PAD_PTA11),
IMX_PINCTRL_PIN(VF610_PAD_PTA12),
IMX_PINCTRL_PIN(VF610_PAD_PTA16),
IMX_PINCTRL_PIN(VF610_PAD_PTA17),
IMX_PINCTRL_PIN(VF610_PAD_PTA18),
IMX_PINCTRL_PIN(VF610_PAD_PTA19),
IMX_PINCTRL_PIN(VF610_PAD_PTA20),
IMX_PINCTRL_PIN(VF610_PAD_PTA21),
IMX_PINCTRL_PIN(VF610_PAD_PTA22),
IMX_PINCTRL_PIN(VF610_PAD_PTA23),
IMX_PINCTRL_PIN(VF610_PAD_PTA24),
IMX_PINCTRL_PIN(VF610_PAD_PTA25),
IMX_PINCTRL_PIN(VF610_PAD_PTA26),
IMX_PINCTRL_PIN(VF610_PAD_PTA27),
IMX_PINCTRL_PIN(VF610_PAD_PTA28),
IMX_PINCTRL_PIN(VF610_PAD_PTA29),
IMX_PINCTRL_PIN(VF610_PAD_PTA30),
IMX_PINCTRL_PIN(VF610_PAD_PTA31),
IMX_PINCTRL_PIN(VF610_PAD_PTB0),
IMX_PINCTRL_PIN(VF610_PAD_PTB1),
IMX_PINCTRL_PIN(VF610_PAD_PTB2),
IMX_PINCTRL_PIN(VF610_PAD_PTB3),
IMX_PINCTRL_PIN(VF610_PAD_PTB4),
IMX_PINCTRL_PIN(VF610_PAD_PTB5),
IMX_PINCTRL_PIN(VF610_PAD_PTB6),
IMX_PINCTRL_PIN(VF610_PAD_PTB7),
IMX_PINCTRL_PIN(VF610_PAD_PTB8),
IMX_PINCTRL_PIN(VF610_PAD_PTB9),
IMX_PINCTRL_PIN(VF610_PAD_PTB10),
IMX_PINCTRL_PIN(VF610_PAD_PTB11),
IMX_PINCTRL_PIN(VF610_PAD_PTB12),
IMX_PINCTRL_PIN(VF610_PAD_PTB13),
IMX_PINCTRL_PIN(VF610_PAD_PTB14),
IMX_PINCTRL_PIN(VF610_PAD_PTB15),
IMX_PINCTRL_PIN(VF610_PAD_PTB16),
IMX_PINCTRL_PIN(VF610_PAD_PTB17),
IMX_PINCTRL_PIN(VF610_PAD_PTB18),
IMX_PINCTRL_PIN(VF610_PAD_PTB19),
IMX_PINCTRL_PIN(VF610_PAD_PTB20),
IMX_PINCTRL_PIN(VF610_PAD_PTB21),
IMX_PINCTRL_PIN(VF610_PAD_PTB22),
IMX_PINCTRL_PIN(VF610_PAD_PTC0),
IMX_PINCTRL_PIN(VF610_PAD_PTC1),
IMX_PINCTRL_PIN(VF610_PAD_PTC2),
IMX_PINCTRL_PIN(VF610_PAD_PTC3),
IMX_PINCTRL_PIN(VF610_PAD_PTC4),
IMX_PINCTRL_PIN(VF610_PAD_PTC5),
IMX_PINCTRL_PIN(VF610_PAD_PTC6),
IMX_PINCTRL_PIN(VF610_PAD_PTC7),
IMX_PINCTRL_PIN(VF610_PAD_PTC8),
IMX_PINCTRL_PIN(VF610_PAD_PTC9),
IMX_PINCTRL_PIN(VF610_PAD_PTC10),
IMX_PINCTRL_PIN(VF610_PAD_PTC11),
IMX_PINCTRL_PIN(VF610_PAD_PTC12),
IMX_PINCTRL_PIN(VF610_PAD_PTC13),
IMX_PINCTRL_PIN(VF610_PAD_PTC14),
IMX_PINCTRL_PIN(VF610_PAD_PTC15),
IMX_PINCTRL_PIN(VF610_PAD_PTC16),
IMX_PINCTRL_PIN(VF610_PAD_PTC17),
IMX_PINCTRL_PIN(VF610_PAD_PTD31),
IMX_PINCTRL_PIN(VF610_PAD_PTD30),
IMX_PINCTRL_PIN(VF610_PAD_PTD29),
IMX_PINCTRL_PIN(VF610_PAD_PTD28),
IMX_PINCTRL_PIN(VF610_PAD_PTD27),
IMX_PINCTRL_PIN(VF610_PAD_PTD26),
IMX_PINCTRL_PIN(VF610_PAD_PTD25),
IMX_PINCTRL_PIN(VF610_PAD_PTD24),
IMX_PINCTRL_PIN(VF610_PAD_PTD23),
IMX_PINCTRL_PIN(VF610_PAD_PTD22),
IMX_PINCTRL_PIN(VF610_PAD_PTD21),
IMX_PINCTRL_PIN(VF610_PAD_PTD20),
IMX_PINCTRL_PIN(VF610_PAD_PTD19),
IMX_PINCTRL_PIN(VF610_PAD_PTD18),
IMX_PINCTRL_PIN(VF610_PAD_PTD17),
IMX_PINCTRL_PIN(VF610_PAD_PTD16),
IMX_PINCTRL_PIN(VF610_PAD_PTD0),
IMX_PINCTRL_PIN(VF610_PAD_PTD1),
IMX_PINCTRL_PIN(VF610_PAD_PTD2),
IMX_PINCTRL_PIN(VF610_PAD_PTD3),
IMX_PINCTRL_PIN(VF610_PAD_PTD4),
IMX_PINCTRL_PIN(VF610_PAD_PTD5),
IMX_PINCTRL_PIN(VF610_PAD_PTD6),
IMX_PINCTRL_PIN(VF610_PAD_PTD7),
IMX_PINCTRL_PIN(VF610_PAD_PTD8),
IMX_PINCTRL_PIN(VF610_PAD_PTD9),
IMX_PINCTRL_PIN(VF610_PAD_PTD10),
IMX_PINCTRL_PIN(VF610_PAD_PTD11),
IMX_PINCTRL_PIN(VF610_PAD_PTD12),
IMX_PINCTRL_PIN(VF610_PAD_PTD13),
IMX_PINCTRL_PIN(VF610_PAD_PTB23),
IMX_PINCTRL_PIN(VF610_PAD_PTB24),
IMX_PINCTRL_PIN(VF610_PAD_PTB25),
IMX_PINCTRL_PIN(VF610_PAD_PTB26),
IMX_PINCTRL_PIN(VF610_PAD_PTB27),
IMX_PINCTRL_PIN(VF610_PAD_PTB28),
IMX_PINCTRL_PIN(VF610_PAD_PTC26),
IMX_PINCTRL_PIN(VF610_PAD_PTC27),
IMX_PINCTRL_PIN(VF610_PAD_PTC28),
IMX_PINCTRL_PIN(VF610_PAD_PTC29),
IMX_PINCTRL_PIN(VF610_PAD_PTC30),
IMX_PINCTRL_PIN(VF610_PAD_PTC31),
IMX_PINCTRL_PIN(VF610_PAD_PTE0),
IMX_PINCTRL_PIN(VF610_PAD_PTE1),
IMX_PINCTRL_PIN(VF610_PAD_PTE2),
IMX_PINCTRL_PIN(VF610_PAD_PTE3),
IMX_PINCTRL_PIN(VF610_PAD_PTE4),
IMX_PINCTRL_PIN(VF610_PAD_PTE5),
IMX_PINCTRL_PIN(VF610_PAD_PTE6),
IMX_PINCTRL_PIN(VF610_PAD_PTE7),
IMX_PINCTRL_PIN(VF610_PAD_PTE8),
IMX_PINCTRL_PIN(VF610_PAD_PTE9),
IMX_PINCTRL_PIN(VF610_PAD_PTE10),
IMX_PINCTRL_PIN(VF610_PAD_PTE11),
IMX_PINCTRL_PIN(VF610_PAD_PTE12),
IMX_PINCTRL_PIN(VF610_PAD_PTE13),
IMX_PINCTRL_PIN(VF610_PAD_PTE14),
IMX_PINCTRL_PIN(VF610_PAD_PTE15),
IMX_PINCTRL_PIN(VF610_PAD_PTE16),
IMX_PINCTRL_PIN(VF610_PAD_PTE17),
IMX_PINCTRL_PIN(VF610_PAD_PTE18),
IMX_PINCTRL_PIN(VF610_PAD_PTE19),
IMX_PINCTRL_PIN(VF610_PAD_PTE20),
IMX_PINCTRL_PIN(VF610_PAD_PTE21),
IMX_PINCTRL_PIN(VF610_PAD_PTE22),
IMX_PINCTRL_PIN(VF610_PAD_PTE23),
IMX_PINCTRL_PIN(VF610_PAD_PTE24),
IMX_PINCTRL_PIN(VF610_PAD_PTE25),
IMX_PINCTRL_PIN(VF610_PAD_PTE26),
IMX_PINCTRL_PIN(VF610_PAD_PTE27),
IMX_PINCTRL_PIN(VF610_PAD_PTE28),
IMX_PINCTRL_PIN(VF610_PAD_PTA7),
};
static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* IBE always enabled allows us to read the value "on the wire" */
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg &= ~0x2;
else
reg |= 0x2;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
.gpio_set_direction = vf610_pmx_gpio_set_direction,
.mux_mask = 0x700000,
.mux_shift = 20,
};
static const struct of_device_id vf610_pinctrl_of_match[] = {
{ .compatible = "fsl,vf610-iomuxc", },
{ /* sentinel */ }
};
static int vf610_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
}
static struct platform_driver vf610_pinctrl_driver = {
.driver = {
.name = "vf610-pinctrl",
.of_match_table = vf610_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = vf610_pinctrl_probe,
};
static int __init vf610_pinctrl_init(void)
{
return platform_driver_register(&vf610_pinctrl_driver);
}
arch_initcall(vf610_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-vf610.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Freescale imx6ul pinctrl driver
//
// Author: Anson Huang <[email protected]>
// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6ul_pads {
MX6UL_PAD_RESERVE0 = 0,
MX6UL_PAD_RESERVE1 = 1,
MX6UL_PAD_RESERVE2 = 2,
MX6UL_PAD_RESERVE3 = 3,
MX6UL_PAD_RESERVE4 = 4,
MX6UL_PAD_RESERVE5 = 5,
MX6UL_PAD_RESERVE6 = 6,
MX6UL_PAD_RESERVE7 = 7,
MX6UL_PAD_RESERVE8 = 8,
MX6UL_PAD_RESERVE9 = 9,
MX6UL_PAD_RESERVE10 = 10,
MX6UL_PAD_SNVS_TAMPER4 = 11,
MX6UL_PAD_RESERVE12 = 12,
MX6UL_PAD_RESERVE13 = 13,
MX6UL_PAD_RESERVE14 = 14,
MX6UL_PAD_RESERVE15 = 15,
MX6UL_PAD_RESERVE16 = 16,
MX6UL_PAD_JTAG_MOD = 17,
MX6UL_PAD_JTAG_TMS = 18,
MX6UL_PAD_JTAG_TDO = 19,
MX6UL_PAD_JTAG_TDI = 20,
MX6UL_PAD_JTAG_TCK = 21,
MX6UL_PAD_JTAG_TRST_B = 22,
MX6UL_PAD_GPIO1_IO00 = 23,
MX6UL_PAD_GPIO1_IO01 = 24,
MX6UL_PAD_GPIO1_IO02 = 25,
MX6UL_PAD_GPIO1_IO03 = 26,
MX6UL_PAD_GPIO1_IO04 = 27,
MX6UL_PAD_GPIO1_IO05 = 28,
MX6UL_PAD_GPIO1_IO06 = 29,
MX6UL_PAD_GPIO1_IO07 = 30,
MX6UL_PAD_GPIO1_IO08 = 31,
MX6UL_PAD_GPIO1_IO09 = 32,
MX6UL_PAD_UART1_TX_DATA = 33,
MX6UL_PAD_UART1_RX_DATA = 34,
MX6UL_PAD_UART1_CTS_B = 35,
MX6UL_PAD_UART1_RTS_B = 36,
MX6UL_PAD_UART2_TX_DATA = 37,
MX6UL_PAD_UART2_RX_DATA = 38,
MX6UL_PAD_UART2_CTS_B = 39,
MX6UL_PAD_UART2_RTS_B = 40,
MX6UL_PAD_UART3_TX_DATA = 41,
MX6UL_PAD_UART3_RX_DATA = 42,
MX6UL_PAD_UART3_CTS_B = 43,
MX6UL_PAD_UART3_RTS_B = 44,
MX6UL_PAD_UART4_TX_DATA = 45,
MX6UL_PAD_UART4_RX_DATA = 46,
MX6UL_PAD_UART5_TX_DATA = 47,
MX6UL_PAD_UART5_RX_DATA = 48,
MX6UL_PAD_ENET1_RX_DATA0 = 49,
MX6UL_PAD_ENET1_RX_DATA1 = 50,
MX6UL_PAD_ENET1_RX_EN = 51,
MX6UL_PAD_ENET1_TX_DATA0 = 52,
MX6UL_PAD_ENET1_TX_DATA1 = 53,
MX6UL_PAD_ENET1_TX_EN = 54,
MX6UL_PAD_ENET1_TX_CLK = 55,
MX6UL_PAD_ENET1_RX_ER = 56,
MX6UL_PAD_ENET2_RX_DATA0 = 57,
MX6UL_PAD_ENET2_RX_DATA1 = 58,
MX6UL_PAD_ENET2_RX_EN = 59,
MX6UL_PAD_ENET2_TX_DATA0 = 60,
MX6UL_PAD_ENET2_TX_DATA1 = 61,
MX6UL_PAD_ENET2_TX_EN = 62,
MX6UL_PAD_ENET2_TX_CLK = 63,
MX6UL_PAD_ENET2_RX_ER = 64,
MX6UL_PAD_LCD_CLK = 65,
MX6UL_PAD_LCD_ENABLE = 66,
MX6UL_PAD_LCD_HSYNC = 67,
MX6UL_PAD_LCD_VSYNC = 68,
MX6UL_PAD_LCD_RESET = 69,
MX6UL_PAD_LCD_DATA00 = 70,
MX6UL_PAD_LCD_DATA01 = 71,
MX6UL_PAD_LCD_DATA02 = 72,
MX6UL_PAD_LCD_DATA03 = 73,
MX6UL_PAD_LCD_DATA04 = 74,
MX6UL_PAD_LCD_DATA05 = 75,
MX6UL_PAD_LCD_DATA06 = 76,
MX6UL_PAD_LCD_DATA07 = 77,
MX6UL_PAD_LCD_DATA08 = 78,
MX6UL_PAD_LCD_DATA09 = 79,
MX6UL_PAD_LCD_DATA10 = 80,
MX6UL_PAD_LCD_DATA11 = 81,
MX6UL_PAD_LCD_DATA12 = 82,
MX6UL_PAD_LCD_DATA13 = 83,
MX6UL_PAD_LCD_DATA14 = 84,
MX6UL_PAD_LCD_DATA15 = 85,
MX6UL_PAD_LCD_DATA16 = 86,
MX6UL_PAD_LCD_DATA17 = 87,
MX6UL_PAD_LCD_DATA18 = 88,
MX6UL_PAD_LCD_DATA19 = 89,
MX6UL_PAD_LCD_DATA20 = 90,
MX6UL_PAD_LCD_DATA21 = 91,
MX6UL_PAD_LCD_DATA22 = 92,
MX6UL_PAD_LCD_DATA23 = 93,
MX6UL_PAD_NAND_RE_B = 94,
MX6UL_PAD_NAND_WE_B = 95,
MX6UL_PAD_NAND_DATA00 = 96,
MX6UL_PAD_NAND_DATA01 = 97,
MX6UL_PAD_NAND_DATA02 = 98,
MX6UL_PAD_NAND_DATA03 = 99,
MX6UL_PAD_NAND_DATA04 = 100,
MX6UL_PAD_NAND_DATA05 = 101,
MX6UL_PAD_NAND_DATA06 = 102,
MX6UL_PAD_NAND_DATA07 = 103,
MX6UL_PAD_NAND_ALE = 104,
MX6UL_PAD_NAND_WP_B = 105,
MX6UL_PAD_NAND_READY_B = 106,
MX6UL_PAD_NAND_CE0_B = 107,
MX6UL_PAD_NAND_CE1_B = 108,
MX6UL_PAD_NAND_CLE = 109,
MX6UL_PAD_NAND_DQS = 110,
MX6UL_PAD_SD1_CMD = 111,
MX6UL_PAD_SD1_CLK = 112,
MX6UL_PAD_SD1_DATA0 = 113,
MX6UL_PAD_SD1_DATA1 = 114,
MX6UL_PAD_SD1_DATA2 = 115,
MX6UL_PAD_SD1_DATA3 = 116,
MX6UL_PAD_CSI_MCLK = 117,
MX6UL_PAD_CSI_PIXCLK = 118,
MX6UL_PAD_CSI_VSYNC = 119,
MX6UL_PAD_CSI_HSYNC = 120,
MX6UL_PAD_CSI_DATA00 = 121,
MX6UL_PAD_CSI_DATA01 = 122,
MX6UL_PAD_CSI_DATA02 = 123,
MX6UL_PAD_CSI_DATA03 = 124,
MX6UL_PAD_CSI_DATA04 = 125,
MX6UL_PAD_CSI_DATA05 = 126,
MX6UL_PAD_CSI_DATA06 = 127,
MX6UL_PAD_CSI_DATA07 = 128,
};
enum imx6ull_lpsr_pads {
MX6ULL_PAD_BOOT_MODE0 = 0,
MX6ULL_PAD_BOOT_MODE1 = 1,
MX6ULL_PAD_SNVS_TAMPER0 = 2,
MX6ULL_PAD_SNVS_TAMPER1 = 3,
MX6ULL_PAD_SNVS_TAMPER2 = 4,
MX6ULL_PAD_SNVS_TAMPER3 = 5,
MX6ULL_PAD_SNVS_TAMPER4 = 6,
MX6ULL_PAD_SNVS_TAMPER5 = 7,
MX6ULL_PAD_SNVS_TAMPER6 = 8,
MX6ULL_PAD_SNVS_TAMPER7 = 9,
MX6ULL_PAD_SNVS_TAMPER8 = 10,
MX6ULL_PAD_SNVS_TAMPER9 = 11,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
};
/* pad for i.MX6ULL lpsr pinmux */
static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
};
static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
.pins = imx6ul_pinctrl_pads,
.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
.gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
};
static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
.pins = imx6ull_snvs_pinctrl_pads,
.npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
.flags = ZERO_OFFSET_VALID,
};
static const struct of_device_id imx6ul_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
{ /* sentinel */ }
};
static int imx6ul_pinctrl_probe(struct platform_device *pdev)
{
const struct imx_pinctrl_soc_info *pinctrl_info;
pinctrl_info = of_device_get_match_data(&pdev->dev);
if (!pinctrl_info)
return -ENODEV;
return imx_pinctrl_probe(pdev, pinctrl_info);
}
static struct platform_driver imx6ul_pinctrl_driver = {
.driver = {
.name = "imx6ul-pinctrl",
.of_match_table = imx6ul_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6ul_pinctrl_probe,
};
static int __init imx6ul_pinctrl_init(void)
{
return platform_driver_register(&imx6ul_pinctrl_driver);
}
arch_initcall(imx6ul_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6ul.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// imx6q pinctrl driver based on imx pinmux core
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6q_pads {
MX6Q_PAD_RESERVE0 = 0,
MX6Q_PAD_RESERVE1 = 1,
MX6Q_PAD_RESERVE2 = 2,
MX6Q_PAD_RESERVE3 = 3,
MX6Q_PAD_RESERVE4 = 4,
MX6Q_PAD_RESERVE5 = 5,
MX6Q_PAD_RESERVE6 = 6,
MX6Q_PAD_RESERVE7 = 7,
MX6Q_PAD_RESERVE8 = 8,
MX6Q_PAD_RESERVE9 = 9,
MX6Q_PAD_RESERVE10 = 10,
MX6Q_PAD_RESERVE11 = 11,
MX6Q_PAD_RESERVE12 = 12,
MX6Q_PAD_RESERVE13 = 13,
MX6Q_PAD_RESERVE14 = 14,
MX6Q_PAD_RESERVE15 = 15,
MX6Q_PAD_RESERVE16 = 16,
MX6Q_PAD_RESERVE17 = 17,
MX6Q_PAD_RESERVE18 = 18,
MX6Q_PAD_SD2_DAT1 = 19,
MX6Q_PAD_SD2_DAT2 = 20,
MX6Q_PAD_SD2_DAT0 = 21,
MX6Q_PAD_RGMII_TXC = 22,
MX6Q_PAD_RGMII_TD0 = 23,
MX6Q_PAD_RGMII_TD1 = 24,
MX6Q_PAD_RGMII_TD2 = 25,
MX6Q_PAD_RGMII_TD3 = 26,
MX6Q_PAD_RGMII_RX_CTL = 27,
MX6Q_PAD_RGMII_RD0 = 28,
MX6Q_PAD_RGMII_TX_CTL = 29,
MX6Q_PAD_RGMII_RD1 = 30,
MX6Q_PAD_RGMII_RD2 = 31,
MX6Q_PAD_RGMII_RD3 = 32,
MX6Q_PAD_RGMII_RXC = 33,
MX6Q_PAD_EIM_A25 = 34,
MX6Q_PAD_EIM_EB2 = 35,
MX6Q_PAD_EIM_D16 = 36,
MX6Q_PAD_EIM_D17 = 37,
MX6Q_PAD_EIM_D18 = 38,
MX6Q_PAD_EIM_D19 = 39,
MX6Q_PAD_EIM_D20 = 40,
MX6Q_PAD_EIM_D21 = 41,
MX6Q_PAD_EIM_D22 = 42,
MX6Q_PAD_EIM_D23 = 43,
MX6Q_PAD_EIM_EB3 = 44,
MX6Q_PAD_EIM_D24 = 45,
MX6Q_PAD_EIM_D25 = 46,
MX6Q_PAD_EIM_D26 = 47,
MX6Q_PAD_EIM_D27 = 48,
MX6Q_PAD_EIM_D28 = 49,
MX6Q_PAD_EIM_D29 = 50,
MX6Q_PAD_EIM_D30 = 51,
MX6Q_PAD_EIM_D31 = 52,
MX6Q_PAD_EIM_A24 = 53,
MX6Q_PAD_EIM_A23 = 54,
MX6Q_PAD_EIM_A22 = 55,
MX6Q_PAD_EIM_A21 = 56,
MX6Q_PAD_EIM_A20 = 57,
MX6Q_PAD_EIM_A19 = 58,
MX6Q_PAD_EIM_A18 = 59,
MX6Q_PAD_EIM_A17 = 60,
MX6Q_PAD_EIM_A16 = 61,
MX6Q_PAD_EIM_CS0 = 62,
MX6Q_PAD_EIM_CS1 = 63,
MX6Q_PAD_EIM_OE = 64,
MX6Q_PAD_EIM_RW = 65,
MX6Q_PAD_EIM_LBA = 66,
MX6Q_PAD_EIM_EB0 = 67,
MX6Q_PAD_EIM_EB1 = 68,
MX6Q_PAD_EIM_DA0 = 69,
MX6Q_PAD_EIM_DA1 = 70,
MX6Q_PAD_EIM_DA2 = 71,
MX6Q_PAD_EIM_DA3 = 72,
MX6Q_PAD_EIM_DA4 = 73,
MX6Q_PAD_EIM_DA5 = 74,
MX6Q_PAD_EIM_DA6 = 75,
MX6Q_PAD_EIM_DA7 = 76,
MX6Q_PAD_EIM_DA8 = 77,
MX6Q_PAD_EIM_DA9 = 78,
MX6Q_PAD_EIM_DA10 = 79,
MX6Q_PAD_EIM_DA11 = 80,
MX6Q_PAD_EIM_DA12 = 81,
MX6Q_PAD_EIM_DA13 = 82,
MX6Q_PAD_EIM_DA14 = 83,
MX6Q_PAD_EIM_DA15 = 84,
MX6Q_PAD_EIM_WAIT = 85,
MX6Q_PAD_EIM_BCLK = 86,
MX6Q_PAD_DI0_DISP_CLK = 87,
MX6Q_PAD_DI0_PIN15 = 88,
MX6Q_PAD_DI0_PIN2 = 89,
MX6Q_PAD_DI0_PIN3 = 90,
MX6Q_PAD_DI0_PIN4 = 91,
MX6Q_PAD_DISP0_DAT0 = 92,
MX6Q_PAD_DISP0_DAT1 = 93,
MX6Q_PAD_DISP0_DAT2 = 94,
MX6Q_PAD_DISP0_DAT3 = 95,
MX6Q_PAD_DISP0_DAT4 = 96,
MX6Q_PAD_DISP0_DAT5 = 97,
MX6Q_PAD_DISP0_DAT6 = 98,
MX6Q_PAD_DISP0_DAT7 = 99,
MX6Q_PAD_DISP0_DAT8 = 100,
MX6Q_PAD_DISP0_DAT9 = 101,
MX6Q_PAD_DISP0_DAT10 = 102,
MX6Q_PAD_DISP0_DAT11 = 103,
MX6Q_PAD_DISP0_DAT12 = 104,
MX6Q_PAD_DISP0_DAT13 = 105,
MX6Q_PAD_DISP0_DAT14 = 106,
MX6Q_PAD_DISP0_DAT15 = 107,
MX6Q_PAD_DISP0_DAT16 = 108,
MX6Q_PAD_DISP0_DAT17 = 109,
MX6Q_PAD_DISP0_DAT18 = 110,
MX6Q_PAD_DISP0_DAT19 = 111,
MX6Q_PAD_DISP0_DAT20 = 112,
MX6Q_PAD_DISP0_DAT21 = 113,
MX6Q_PAD_DISP0_DAT22 = 114,
MX6Q_PAD_DISP0_DAT23 = 115,
MX6Q_PAD_ENET_MDIO = 116,
MX6Q_PAD_ENET_REF_CLK = 117,
MX6Q_PAD_ENET_RX_ER = 118,
MX6Q_PAD_ENET_CRS_DV = 119,
MX6Q_PAD_ENET_RXD1 = 120,
MX6Q_PAD_ENET_RXD0 = 121,
MX6Q_PAD_ENET_TX_EN = 122,
MX6Q_PAD_ENET_TXD1 = 123,
MX6Q_PAD_ENET_TXD0 = 124,
MX6Q_PAD_ENET_MDC = 125,
MX6Q_PAD_KEY_COL0 = 126,
MX6Q_PAD_KEY_ROW0 = 127,
MX6Q_PAD_KEY_COL1 = 128,
MX6Q_PAD_KEY_ROW1 = 129,
MX6Q_PAD_KEY_COL2 = 130,
MX6Q_PAD_KEY_ROW2 = 131,
MX6Q_PAD_KEY_COL3 = 132,
MX6Q_PAD_KEY_ROW3 = 133,
MX6Q_PAD_KEY_COL4 = 134,
MX6Q_PAD_KEY_ROW4 = 135,
MX6Q_PAD_GPIO_0 = 136,
MX6Q_PAD_GPIO_1 = 137,
MX6Q_PAD_GPIO_9 = 138,
MX6Q_PAD_GPIO_3 = 139,
MX6Q_PAD_GPIO_6 = 140,
MX6Q_PAD_GPIO_2 = 141,
MX6Q_PAD_GPIO_4 = 142,
MX6Q_PAD_GPIO_5 = 143,
MX6Q_PAD_GPIO_7 = 144,
MX6Q_PAD_GPIO_8 = 145,
MX6Q_PAD_GPIO_16 = 146,
MX6Q_PAD_GPIO_17 = 147,
MX6Q_PAD_GPIO_18 = 148,
MX6Q_PAD_GPIO_19 = 149,
MX6Q_PAD_CSI0_PIXCLK = 150,
MX6Q_PAD_CSI0_MCLK = 151,
MX6Q_PAD_CSI0_DATA_EN = 152,
MX6Q_PAD_CSI0_VSYNC = 153,
MX6Q_PAD_CSI0_DAT4 = 154,
MX6Q_PAD_CSI0_DAT5 = 155,
MX6Q_PAD_CSI0_DAT6 = 156,
MX6Q_PAD_CSI0_DAT7 = 157,
MX6Q_PAD_CSI0_DAT8 = 158,
MX6Q_PAD_CSI0_DAT9 = 159,
MX6Q_PAD_CSI0_DAT10 = 160,
MX6Q_PAD_CSI0_DAT11 = 161,
MX6Q_PAD_CSI0_DAT12 = 162,
MX6Q_PAD_CSI0_DAT13 = 163,
MX6Q_PAD_CSI0_DAT14 = 164,
MX6Q_PAD_CSI0_DAT15 = 165,
MX6Q_PAD_CSI0_DAT16 = 166,
MX6Q_PAD_CSI0_DAT17 = 167,
MX6Q_PAD_CSI0_DAT18 = 168,
MX6Q_PAD_CSI0_DAT19 = 169,
MX6Q_PAD_SD3_DAT7 = 170,
MX6Q_PAD_SD3_DAT6 = 171,
MX6Q_PAD_SD3_DAT5 = 172,
MX6Q_PAD_SD3_DAT4 = 173,
MX6Q_PAD_SD3_CMD = 174,
MX6Q_PAD_SD3_CLK = 175,
MX6Q_PAD_SD3_DAT0 = 176,
MX6Q_PAD_SD3_DAT1 = 177,
MX6Q_PAD_SD3_DAT2 = 178,
MX6Q_PAD_SD3_DAT3 = 179,
MX6Q_PAD_SD3_RST = 180,
MX6Q_PAD_NANDF_CLE = 181,
MX6Q_PAD_NANDF_ALE = 182,
MX6Q_PAD_NANDF_WP_B = 183,
MX6Q_PAD_NANDF_RB0 = 184,
MX6Q_PAD_NANDF_CS0 = 185,
MX6Q_PAD_NANDF_CS1 = 186,
MX6Q_PAD_NANDF_CS2 = 187,
MX6Q_PAD_NANDF_CS3 = 188,
MX6Q_PAD_SD4_CMD = 189,
MX6Q_PAD_SD4_CLK = 190,
MX6Q_PAD_NANDF_D0 = 191,
MX6Q_PAD_NANDF_D1 = 192,
MX6Q_PAD_NANDF_D2 = 193,
MX6Q_PAD_NANDF_D3 = 194,
MX6Q_PAD_NANDF_D4 = 195,
MX6Q_PAD_NANDF_D5 = 196,
MX6Q_PAD_NANDF_D6 = 197,
MX6Q_PAD_NANDF_D7 = 198,
MX6Q_PAD_SD4_DAT0 = 199,
MX6Q_PAD_SD4_DAT1 = 200,
MX6Q_PAD_SD4_DAT2 = 201,
MX6Q_PAD_SD4_DAT3 = 202,
MX6Q_PAD_SD4_DAT4 = 203,
MX6Q_PAD_SD4_DAT5 = 204,
MX6Q_PAD_SD4_DAT6 = 205,
MX6Q_PAD_SD4_DAT7 = 206,
MX6Q_PAD_SD1_DAT1 = 207,
MX6Q_PAD_SD1_DAT0 = 208,
MX6Q_PAD_SD1_DAT3 = 209,
MX6Q_PAD_SD1_CMD = 210,
MX6Q_PAD_SD1_DAT2 = 211,
MX6Q_PAD_SD1_CLK = 212,
MX6Q_PAD_SD2_CLK = 213,
MX6Q_PAD_SD2_CMD = 214,
MX6Q_PAD_SD2_DAT3 = 215,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
};
static const struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.pins = imx6q_pinctrl_pads,
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6q_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", },
{ /* sentinel */ }
};
static int imx6q_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
}
static struct platform_driver imx6q_pinctrl_driver = {
.driver = {
.name = "imx6q-pinctrl",
.of_match_table = imx6q_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6q_pinctrl_probe,
};
static int __init imx6q_pinctrl_init(void)
{
return platform_driver_register(&imx6q_pinctrl_driver);
}
arch_initcall(imx6q_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6q.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// Freescale i.MX23 pinctrl driver
//
// Author: Shawn Guo <[email protected]>
// Copyright 2012 Freescale Semiconductor, Inc.
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
enum imx23_pin_enum {
GPMI_D00 = PINID(0, 0),
GPMI_D01 = PINID(0, 1),
GPMI_D02 = PINID(0, 2),
GPMI_D03 = PINID(0, 3),
GPMI_D04 = PINID(0, 4),
GPMI_D05 = PINID(0, 5),
GPMI_D06 = PINID(0, 6),
GPMI_D07 = PINID(0, 7),
GPMI_D08 = PINID(0, 8),
GPMI_D09 = PINID(0, 9),
GPMI_D10 = PINID(0, 10),
GPMI_D11 = PINID(0, 11),
GPMI_D12 = PINID(0, 12),
GPMI_D13 = PINID(0, 13),
GPMI_D14 = PINID(0, 14),
GPMI_D15 = PINID(0, 15),
GPMI_CLE = PINID(0, 16),
GPMI_ALE = PINID(0, 17),
GPMI_CE2N = PINID(0, 18),
GPMI_RDY0 = PINID(0, 19),
GPMI_RDY1 = PINID(0, 20),
GPMI_RDY2 = PINID(0, 21),
GPMI_RDY3 = PINID(0, 22),
GPMI_WPN = PINID(0, 23),
GPMI_WRN = PINID(0, 24),
GPMI_RDN = PINID(0, 25),
AUART1_CTS = PINID(0, 26),
AUART1_RTS = PINID(0, 27),
AUART1_RX = PINID(0, 28),
AUART1_TX = PINID(0, 29),
I2C_SCL = PINID(0, 30),
I2C_SDA = PINID(0, 31),
LCD_D00 = PINID(1, 0),
LCD_D01 = PINID(1, 1),
LCD_D02 = PINID(1, 2),
LCD_D03 = PINID(1, 3),
LCD_D04 = PINID(1, 4),
LCD_D05 = PINID(1, 5),
LCD_D06 = PINID(1, 6),
LCD_D07 = PINID(1, 7),
LCD_D08 = PINID(1, 8),
LCD_D09 = PINID(1, 9),
LCD_D10 = PINID(1, 10),
LCD_D11 = PINID(1, 11),
LCD_D12 = PINID(1, 12),
LCD_D13 = PINID(1, 13),
LCD_D14 = PINID(1, 14),
LCD_D15 = PINID(1, 15),
LCD_D16 = PINID(1, 16),
LCD_D17 = PINID(1, 17),
LCD_RESET = PINID(1, 18),
LCD_RS = PINID(1, 19),
LCD_WR = PINID(1, 20),
LCD_CS = PINID(1, 21),
LCD_DOTCK = PINID(1, 22),
LCD_ENABLE = PINID(1, 23),
LCD_HSYNC = PINID(1, 24),
LCD_VSYNC = PINID(1, 25),
PWM0 = PINID(1, 26),
PWM1 = PINID(1, 27),
PWM2 = PINID(1, 28),
PWM3 = PINID(1, 29),
PWM4 = PINID(1, 30),
SSP1_CMD = PINID(2, 0),
SSP1_DETECT = PINID(2, 1),
SSP1_DATA0 = PINID(2, 2),
SSP1_DATA1 = PINID(2, 3),
SSP1_DATA2 = PINID(2, 4),
SSP1_DATA3 = PINID(2, 5),
SSP1_SCK = PINID(2, 6),
ROTARYA = PINID(2, 7),
ROTARYB = PINID(2, 8),
EMI_A00 = PINID(2, 9),
EMI_A01 = PINID(2, 10),
EMI_A02 = PINID(2, 11),
EMI_A03 = PINID(2, 12),
EMI_A04 = PINID(2, 13),
EMI_A05 = PINID(2, 14),
EMI_A06 = PINID(2, 15),
EMI_A07 = PINID(2, 16),
EMI_A08 = PINID(2, 17),
EMI_A09 = PINID(2, 18),
EMI_A10 = PINID(2, 19),
EMI_A11 = PINID(2, 20),
EMI_A12 = PINID(2, 21),
EMI_BA0 = PINID(2, 22),
EMI_BA1 = PINID(2, 23),
EMI_CASN = PINID(2, 24),
EMI_CE0N = PINID(2, 25),
EMI_CE1N = PINID(2, 26),
GPMI_CE1N = PINID(2, 27),
GPMI_CE0N = PINID(2, 28),
EMI_CKE = PINID(2, 29),
EMI_RASN = PINID(2, 30),
EMI_WEN = PINID(2, 31),
EMI_D00 = PINID(3, 0),
EMI_D01 = PINID(3, 1),
EMI_D02 = PINID(3, 2),
EMI_D03 = PINID(3, 3),
EMI_D04 = PINID(3, 4),
EMI_D05 = PINID(3, 5),
EMI_D06 = PINID(3, 6),
EMI_D07 = PINID(3, 7),
EMI_D08 = PINID(3, 8),
EMI_D09 = PINID(3, 9),
EMI_D10 = PINID(3, 10),
EMI_D11 = PINID(3, 11),
EMI_D12 = PINID(3, 12),
EMI_D13 = PINID(3, 13),
EMI_D14 = PINID(3, 14),
EMI_D15 = PINID(3, 15),
EMI_DQM0 = PINID(3, 16),
EMI_DQM1 = PINID(3, 17),
EMI_DQS0 = PINID(3, 18),
EMI_DQS1 = PINID(3, 19),
EMI_CLK = PINID(3, 20),
EMI_CLKN = PINID(3, 21),
};
static const struct pinctrl_pin_desc imx23_pins[] = {
MXS_PINCTRL_PIN(GPMI_D00),
MXS_PINCTRL_PIN(GPMI_D01),
MXS_PINCTRL_PIN(GPMI_D02),
MXS_PINCTRL_PIN(GPMI_D03),
MXS_PINCTRL_PIN(GPMI_D04),
MXS_PINCTRL_PIN(GPMI_D05),
MXS_PINCTRL_PIN(GPMI_D06),
MXS_PINCTRL_PIN(GPMI_D07),
MXS_PINCTRL_PIN(GPMI_D08),
MXS_PINCTRL_PIN(GPMI_D09),
MXS_PINCTRL_PIN(GPMI_D10),
MXS_PINCTRL_PIN(GPMI_D11),
MXS_PINCTRL_PIN(GPMI_D12),
MXS_PINCTRL_PIN(GPMI_D13),
MXS_PINCTRL_PIN(GPMI_D14),
MXS_PINCTRL_PIN(GPMI_D15),
MXS_PINCTRL_PIN(GPMI_CLE),
MXS_PINCTRL_PIN(GPMI_ALE),
MXS_PINCTRL_PIN(GPMI_CE2N),
MXS_PINCTRL_PIN(GPMI_RDY0),
MXS_PINCTRL_PIN(GPMI_RDY1),
MXS_PINCTRL_PIN(GPMI_RDY2),
MXS_PINCTRL_PIN(GPMI_RDY3),
MXS_PINCTRL_PIN(GPMI_WPN),
MXS_PINCTRL_PIN(GPMI_WRN),
MXS_PINCTRL_PIN(GPMI_RDN),
MXS_PINCTRL_PIN(AUART1_CTS),
MXS_PINCTRL_PIN(AUART1_RTS),
MXS_PINCTRL_PIN(AUART1_RX),
MXS_PINCTRL_PIN(AUART1_TX),
MXS_PINCTRL_PIN(I2C_SCL),
MXS_PINCTRL_PIN(I2C_SDA),
MXS_PINCTRL_PIN(LCD_D00),
MXS_PINCTRL_PIN(LCD_D01),
MXS_PINCTRL_PIN(LCD_D02),
MXS_PINCTRL_PIN(LCD_D03),
MXS_PINCTRL_PIN(LCD_D04),
MXS_PINCTRL_PIN(LCD_D05),
MXS_PINCTRL_PIN(LCD_D06),
MXS_PINCTRL_PIN(LCD_D07),
MXS_PINCTRL_PIN(LCD_D08),
MXS_PINCTRL_PIN(LCD_D09),
MXS_PINCTRL_PIN(LCD_D10),
MXS_PINCTRL_PIN(LCD_D11),
MXS_PINCTRL_PIN(LCD_D12),
MXS_PINCTRL_PIN(LCD_D13),
MXS_PINCTRL_PIN(LCD_D14),
MXS_PINCTRL_PIN(LCD_D15),
MXS_PINCTRL_PIN(LCD_D16),
MXS_PINCTRL_PIN(LCD_D17),
MXS_PINCTRL_PIN(LCD_RESET),
MXS_PINCTRL_PIN(LCD_RS),
MXS_PINCTRL_PIN(LCD_WR),
MXS_PINCTRL_PIN(LCD_CS),
MXS_PINCTRL_PIN(LCD_DOTCK),
MXS_PINCTRL_PIN(LCD_ENABLE),
MXS_PINCTRL_PIN(LCD_HSYNC),
MXS_PINCTRL_PIN(LCD_VSYNC),
MXS_PINCTRL_PIN(PWM0),
MXS_PINCTRL_PIN(PWM1),
MXS_PINCTRL_PIN(PWM2),
MXS_PINCTRL_PIN(PWM3),
MXS_PINCTRL_PIN(PWM4),
MXS_PINCTRL_PIN(SSP1_CMD),
MXS_PINCTRL_PIN(SSP1_DETECT),
MXS_PINCTRL_PIN(SSP1_DATA0),
MXS_PINCTRL_PIN(SSP1_DATA1),
MXS_PINCTRL_PIN(SSP1_DATA2),
MXS_PINCTRL_PIN(SSP1_DATA3),
MXS_PINCTRL_PIN(SSP1_SCK),
MXS_PINCTRL_PIN(ROTARYA),
MXS_PINCTRL_PIN(ROTARYB),
MXS_PINCTRL_PIN(EMI_A00),
MXS_PINCTRL_PIN(EMI_A01),
MXS_PINCTRL_PIN(EMI_A02),
MXS_PINCTRL_PIN(EMI_A03),
MXS_PINCTRL_PIN(EMI_A04),
MXS_PINCTRL_PIN(EMI_A05),
MXS_PINCTRL_PIN(EMI_A06),
MXS_PINCTRL_PIN(EMI_A07),
MXS_PINCTRL_PIN(EMI_A08),
MXS_PINCTRL_PIN(EMI_A09),
MXS_PINCTRL_PIN(EMI_A10),
MXS_PINCTRL_PIN(EMI_A11),
MXS_PINCTRL_PIN(EMI_A12),
MXS_PINCTRL_PIN(EMI_BA0),
MXS_PINCTRL_PIN(EMI_BA1),
MXS_PINCTRL_PIN(EMI_CASN),
MXS_PINCTRL_PIN(EMI_CE0N),
MXS_PINCTRL_PIN(EMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE0N),
MXS_PINCTRL_PIN(EMI_CKE),
MXS_PINCTRL_PIN(EMI_RASN),
MXS_PINCTRL_PIN(EMI_WEN),
MXS_PINCTRL_PIN(EMI_D00),
MXS_PINCTRL_PIN(EMI_D01),
MXS_PINCTRL_PIN(EMI_D02),
MXS_PINCTRL_PIN(EMI_D03),
MXS_PINCTRL_PIN(EMI_D04),
MXS_PINCTRL_PIN(EMI_D05),
MXS_PINCTRL_PIN(EMI_D06),
MXS_PINCTRL_PIN(EMI_D07),
MXS_PINCTRL_PIN(EMI_D08),
MXS_PINCTRL_PIN(EMI_D09),
MXS_PINCTRL_PIN(EMI_D10),
MXS_PINCTRL_PIN(EMI_D11),
MXS_PINCTRL_PIN(EMI_D12),
MXS_PINCTRL_PIN(EMI_D13),
MXS_PINCTRL_PIN(EMI_D14),
MXS_PINCTRL_PIN(EMI_D15),
MXS_PINCTRL_PIN(EMI_DQM0),
MXS_PINCTRL_PIN(EMI_DQM1),
MXS_PINCTRL_PIN(EMI_DQS0),
MXS_PINCTRL_PIN(EMI_DQS1),
MXS_PINCTRL_PIN(EMI_CLK),
MXS_PINCTRL_PIN(EMI_CLKN),
};
static const struct mxs_regs imx23_regs = {
.muxsel = 0x100,
.drive = 0x200,
.pull = 0x400,
};
static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
.regs = &imx23_regs,
.pins = imx23_pins,
.npins = ARRAY_SIZE(imx23_pins),
};
static int imx23_pinctrl_probe(struct platform_device *pdev)
{
return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
}
static const struct of_device_id imx23_pinctrl_of_match[] = {
{ .compatible = "fsl,imx23-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver imx23_pinctrl_driver = {
.driver = {
.name = "imx23-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = imx23_pinctrl_of_match,
},
.probe = imx23_pinctrl_probe,
};
static int __init imx23_pinctrl_init(void)
{
return platform_driver_register(&imx23_pinctrl_driver);
}
postcore_initcall(imx23_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx23.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// imx27 pinctrl driver based on imx pinmux core
//
// Copyright (C) 2013 Pengutronix
//
// Author: Markus Pargmann <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) (port*32 + pin)
#define PA 0
#define PB 1
#define PC 2
#define PD 3
#define PE 4
#define PF 5
enum imx27_pads {
MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
MX27_PAD_LSCLK = PAD_ID(PA, 5),
MX27_PAD_LD0 = PAD_ID(PA, 6),
MX27_PAD_LD1 = PAD_ID(PA, 7),
MX27_PAD_LD2 = PAD_ID(PA, 8),
MX27_PAD_LD3 = PAD_ID(PA, 9),
MX27_PAD_LD4 = PAD_ID(PA, 10),
MX27_PAD_LD5 = PAD_ID(PA, 11),
MX27_PAD_LD6 = PAD_ID(PA, 12),
MX27_PAD_LD7 = PAD_ID(PA, 13),
MX27_PAD_LD8 = PAD_ID(PA, 14),
MX27_PAD_LD9 = PAD_ID(PA, 15),
MX27_PAD_LD10 = PAD_ID(PA, 16),
MX27_PAD_LD11 = PAD_ID(PA, 17),
MX27_PAD_LD12 = PAD_ID(PA, 18),
MX27_PAD_LD13 = PAD_ID(PA, 19),
MX27_PAD_LD14 = PAD_ID(PA, 20),
MX27_PAD_LD15 = PAD_ID(PA, 21),
MX27_PAD_LD16 = PAD_ID(PA, 22),
MX27_PAD_LD17 = PAD_ID(PA, 23),
MX27_PAD_REV = PAD_ID(PA, 24),
MX27_PAD_CLS = PAD_ID(PA, 25),
MX27_PAD_PS = PAD_ID(PA, 26),
MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
MX27_PAD_HSYNC = PAD_ID(PA, 28),
MX27_PAD_VSYNC = PAD_ID(PA, 29),
MX27_PAD_CONTRAST = PAD_ID(PA, 30),
MX27_PAD_OE_ACD = PAD_ID(PA, 31),
MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
MX27_PAD_USB_PWR = PAD_ID(PB, 23),
MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
MX27_PAD_TOUT = PAD_ID(PC, 14),
MX27_PAD_TIN = PAD_ID(PC, 15),
MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
MX27_PAD_PWMO = PAD_ID(PE, 5),
MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
MX27_PAD_RTCK = PAD_ID(PE, 16),
MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
MX27_PAD_NFRB = PAD_ID(PF, 0),
MX27_PAD_NFCLE = PAD_ID(PF, 1),
MX27_PAD_NFWP_B = PAD_ID(PF, 2),
MX27_PAD_NFCE_B = PAD_ID(PF, 3),
MX27_PAD_NFALE = PAD_ID(PF, 4),
MX27_PAD_NFRE_B = PAD_ID(PF, 5),
MX27_PAD_NFWE_B = PAD_ID(PF, 6),
MX27_PAD_PC_POE = PAD_ID(PF, 7),
MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
MX27_PAD_IOIS16 = PAD_ID(PF, 9),
MX27_PAD_PC_RST = PAD_ID(PF, 10),
MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
MX27_PAD_CLKO = PAD_ID(PF, 15),
MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
MX27_PAD_PC_READY = PAD_ID(PF, 17),
MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
MX27_PAD_CS4_B = PAD_ID(PF, 21),
MX27_PAD_CS5_B = PAD_ID(PF, 22),
MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
IMX_PINCTRL_PIN(MX27_PAD_LD0),
IMX_PINCTRL_PIN(MX27_PAD_LD1),
IMX_PINCTRL_PIN(MX27_PAD_LD2),
IMX_PINCTRL_PIN(MX27_PAD_LD3),
IMX_PINCTRL_PIN(MX27_PAD_LD4),
IMX_PINCTRL_PIN(MX27_PAD_LD5),
IMX_PINCTRL_PIN(MX27_PAD_LD6),
IMX_PINCTRL_PIN(MX27_PAD_LD7),
IMX_PINCTRL_PIN(MX27_PAD_LD8),
IMX_PINCTRL_PIN(MX27_PAD_LD9),
IMX_PINCTRL_PIN(MX27_PAD_LD10),
IMX_PINCTRL_PIN(MX27_PAD_LD11),
IMX_PINCTRL_PIN(MX27_PAD_LD12),
IMX_PINCTRL_PIN(MX27_PAD_LD13),
IMX_PINCTRL_PIN(MX27_PAD_LD14),
IMX_PINCTRL_PIN(MX27_PAD_LD15),
IMX_PINCTRL_PIN(MX27_PAD_LD16),
IMX_PINCTRL_PIN(MX27_PAD_LD17),
IMX_PINCTRL_PIN(MX27_PAD_REV),
IMX_PINCTRL_PIN(MX27_PAD_CLS),
IMX_PINCTRL_PIN(MX27_PAD_PS),
IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
IMX_PINCTRL_PIN(MX27_PAD_TOUT),
IMX_PINCTRL_PIN(MX27_PAD_TIN),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX27_PAD_PWMO),
IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX27_PAD_RTCK),
IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_NFRB),
IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
IMX_PINCTRL_PIN(MX27_PAD_NFALE),
IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
IMX_PINCTRL_PIN(MX27_PAD_CLKO),
IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
};
static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
.pins = imx27_pinctrl_pads,
.npins = ARRAY_SIZE(imx27_pinctrl_pads),
};
static const struct of_device_id imx27_pinctrl_of_match[] = {
{ .compatible = "fsl,imx27-iomuxc", },
{ /* sentinel */ }
};
static int imx27_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
}
static struct platform_driver imx27_pinctrl_driver = {
.driver = {
.name = "imx27-pinctrl",
.of_match_table = imx27_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx27_pinctrl_probe,
};
static int __init imx27_pinctrl_init(void)
{
return platform_driver_register(&imx27_pinctrl_driver);
}
arch_initcall(imx27_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx27.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Copyright (C) 2018 Pengutronix, Lucas Stach <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx8mq_pads {
MX8MQ_PAD_RESERVE0 = 0,
MX8MQ_PAD_RESERVE1 = 1,
MX8MQ_PAD_RESERVE2 = 2,
MX8MQ_PAD_RESERVE3 = 3,
MX8MQ_PAD_RESERVE4 = 4,
MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,
MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,
MX8MQ_IOMUXC_POR_B_SNVSMIX = 8,
MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,
MX8MQ_IOMUXC_GPIO1_IO00 = 10,
MX8MQ_IOMUXC_GPIO1_IO01 = 11,
MX8MQ_IOMUXC_GPIO1_IO02 = 12,
MX8MQ_IOMUXC_GPIO1_IO03 = 13,
MX8MQ_IOMUXC_GPIO1_IO04 = 14,
MX8MQ_IOMUXC_GPIO1_IO05 = 15,
MX8MQ_IOMUXC_GPIO1_IO06 = 16,
MX8MQ_IOMUXC_GPIO1_IO07 = 17,
MX8MQ_IOMUXC_GPIO1_IO08 = 18,
MX8MQ_IOMUXC_GPIO1_IO09 = 19,
MX8MQ_IOMUXC_GPIO1_IO10 = 20,
MX8MQ_IOMUXC_GPIO1_IO11 = 21,
MX8MQ_IOMUXC_GPIO1_IO12 = 22,
MX8MQ_IOMUXC_GPIO1_IO13 = 23,
MX8MQ_IOMUXC_GPIO1_IO14 = 24,
MX8MQ_IOMUXC_GPIO1_IO15 = 25,
MX8MQ_IOMUXC_ENET_MDC = 26,
MX8MQ_IOMUXC_ENET_MDIO = 27,
MX8MQ_IOMUXC_ENET_TD3 = 28,
MX8MQ_IOMUXC_ENET_TD2 = 29,
MX8MQ_IOMUXC_ENET_TD1 = 30,
MX8MQ_IOMUXC_ENET_TD0 = 31,
MX8MQ_IOMUXC_ENET_TX_CTL = 32,
MX8MQ_IOMUXC_ENET_TXC = 33,
MX8MQ_IOMUXC_ENET_RX_CTL = 34,
MX8MQ_IOMUXC_ENET_RXC = 35,
MX8MQ_IOMUXC_ENET_RD0 = 36,
MX8MQ_IOMUXC_ENET_RD1 = 37,
MX8MQ_IOMUXC_ENET_RD2 = 38,
MX8MQ_IOMUXC_ENET_RD3 = 39,
MX8MQ_IOMUXC_SD1_CLK = 40,
MX8MQ_IOMUXC_SD1_CMD = 41,
MX8MQ_IOMUXC_SD1_DATA0 = 42,
MX8MQ_IOMUXC_SD1_DATA1 = 43,
MX8MQ_IOMUXC_SD1_DATA2 = 44,
MX8MQ_IOMUXC_SD1_DATA3 = 45,
MX8MQ_IOMUXC_SD1_DATA4 = 46,
MX8MQ_IOMUXC_SD1_DATA5 = 47,
MX8MQ_IOMUXC_SD1_DATA6 = 48,
MX8MQ_IOMUXC_SD1_DATA7 = 49,
MX8MQ_IOMUXC_SD1_RESET_B = 50,
MX8MQ_IOMUXC_SD1_STROBE = 51,
MX8MQ_IOMUXC_SD2_CD_B = 52,
MX8MQ_IOMUXC_SD2_CLK = 53,
MX8MQ_IOMUXC_SD2_CMD = 54,
MX8MQ_IOMUXC_SD2_DATA0 = 55,
MX8MQ_IOMUXC_SD2_DATA1 = 56,
MX8MQ_IOMUXC_SD2_DATA2 = 57,
MX8MQ_IOMUXC_SD2_DATA3 = 58,
MX8MQ_IOMUXC_SD2_RESET_B = 59,
MX8MQ_IOMUXC_SD2_WP = 60,
MX8MQ_IOMUXC_NAND_ALE = 61,
MX8MQ_IOMUXC_NAND_CE0_B = 62,
MX8MQ_IOMUXC_NAND_CE1_B = 63,
MX8MQ_IOMUXC_NAND_CE2_B = 64,
MX8MQ_IOMUXC_NAND_CE3_B = 65,
MX8MQ_IOMUXC_NAND_CLE = 66,
MX8MQ_IOMUXC_NAND_DATA00 = 67,
MX8MQ_IOMUXC_NAND_DATA01 = 68,
MX8MQ_IOMUXC_NAND_DATA02 = 69,
MX8MQ_IOMUXC_NAND_DATA03 = 70,
MX8MQ_IOMUXC_NAND_DATA04 = 71,
MX8MQ_IOMUXC_NAND_DATA05 = 72,
MX8MQ_IOMUXC_NAND_DATA06 = 73,
MX8MQ_IOMUXC_NAND_DATA07 = 74,
MX8MQ_IOMUXC_NAND_DQS = 75,
MX8MQ_IOMUXC_NAND_RE_B = 76,
MX8MQ_IOMUXC_NAND_READY_B = 77,
MX8MQ_IOMUXC_NAND_WE_B = 78,
MX8MQ_IOMUXC_NAND_WP_B = 79,
MX8MQ_IOMUXC_SAI5_RXFS = 80,
MX8MQ_IOMUXC_SAI5_RXC = 81,
MX8MQ_IOMUXC_SAI5_RXD0 = 82,
MX8MQ_IOMUXC_SAI5_RXD1 = 83,
MX8MQ_IOMUXC_SAI5_RXD2 = 84,
MX8MQ_IOMUXC_SAI5_RXD3 = 85,
MX8MQ_IOMUXC_SAI5_MCLK = 86,
MX8MQ_IOMUXC_SAI1_RXFS = 87,
MX8MQ_IOMUXC_SAI1_RXC = 88,
MX8MQ_IOMUXC_SAI1_RXD0 = 89,
MX8MQ_IOMUXC_SAI1_RXD1 = 90,
MX8MQ_IOMUXC_SAI1_RXD2 = 91,
MX8MQ_IOMUXC_SAI1_RXD3 = 92,
MX8MQ_IOMUXC_SAI1_RXD4 = 93,
MX8MQ_IOMUXC_SAI1_RXD5 = 94,
MX8MQ_IOMUXC_SAI1_RXD6 = 95,
MX8MQ_IOMUXC_SAI1_RXD7 = 96,
MX8MQ_IOMUXC_SAI1_TXFS = 97,
MX8MQ_IOMUXC_SAI1_TXC = 98,
MX8MQ_IOMUXC_SAI1_TXD0 = 99,
MX8MQ_IOMUXC_SAI1_TXD1 = 100,
MX8MQ_IOMUXC_SAI1_TXD2 = 101,
MX8MQ_IOMUXC_SAI1_TXD3 = 102,
MX8MQ_IOMUXC_SAI1_TXD4 = 103,
MX8MQ_IOMUXC_SAI1_TXD5 = 104,
MX8MQ_IOMUXC_SAI1_TXD6 = 105,
MX8MQ_IOMUXC_SAI1_TXD7 = 106,
MX8MQ_IOMUXC_SAI1_MCLK = 107,
MX8MQ_IOMUXC_SAI2_RXFS = 108,
MX8MQ_IOMUXC_SAI2_RXC = 109,
MX8MQ_IOMUXC_SAI2_RXD0 = 110,
MX8MQ_IOMUXC_SAI2_TXFS = 111,
MX8MQ_IOMUXC_SAI2_TXC = 112,
MX8MQ_IOMUXC_SAI2_TXD0 = 113,
MX8MQ_IOMUXC_SAI2_MCLK = 114,
MX8MQ_IOMUXC_SAI3_RXFS = 115,
MX8MQ_IOMUXC_SAI3_RXC = 116,
MX8MQ_IOMUXC_SAI3_RXD = 117,
MX8MQ_IOMUXC_SAI3_TXFS = 118,
MX8MQ_IOMUXC_SAI3_TXC = 119,
MX8MQ_IOMUXC_SAI3_TXD = 120,
MX8MQ_IOMUXC_SAI3_MCLK = 121,
MX8MQ_IOMUXC_SPDIF_TX = 122,
MX8MQ_IOMUXC_SPDIF_RX = 123,
MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124,
MX8MQ_IOMUXC_ECSPI1_SCLK = 125,
MX8MQ_IOMUXC_ECSPI1_MOSI = 126,
MX8MQ_IOMUXC_ECSPI1_MISO = 127,
MX8MQ_IOMUXC_ECSPI1_SS0 = 128,
MX8MQ_IOMUXC_ECSPI2_SCLK = 129,
MX8MQ_IOMUXC_ECSPI2_MOSI = 130,
MX8MQ_IOMUXC_ECSPI2_MISO = 131,
MX8MQ_IOMUXC_ECSPI2_SS0 = 132,
MX8MQ_IOMUXC_I2C1_SCL = 133,
MX8MQ_IOMUXC_I2C1_SDA = 134,
MX8MQ_IOMUXC_I2C2_SCL = 135,
MX8MQ_IOMUXC_I2C2_SDA = 136,
MX8MQ_IOMUXC_I2C3_SCL = 137,
MX8MQ_IOMUXC_I2C3_SDA = 138,
MX8MQ_IOMUXC_I2C4_SCL = 139,
MX8MQ_IOMUXC_I2C4_SDA = 140,
MX8MQ_IOMUXC_UART1_RXD = 141,
MX8MQ_IOMUXC_UART1_TXD = 142,
MX8MQ_IOMUXC_UART2_RXD = 143,
MX8MQ_IOMUXC_UART2_TXD = 144,
MX8MQ_IOMUXC_UART3_RXD = 145,
MX8MQ_IOMUXC_UART3_TXD = 146,
MX8MQ_IOMUXC_UART4_RXD = 147,
MX8MQ_IOMUXC_UART4_TXD = 148,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD),
};
static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = {
.pins = imx8mq_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mq_pinctrl_pads),
.gpr_compatible = "fsl,imx8mq-iomuxc-gpr",
};
static const struct of_device_id imx8mq_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8mq_pinctrl_of_match);
static int imx8mq_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8mq_pinctrl_info);
}
static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = imx8mq_pinctrl_of_match,
.pm = &imx_pinctrl_pm_ops,
.suppress_bind_attrs = true,
},
.probe = imx8mq_pinctrl_probe,
};
static int __init imx8mq_pinctrl_init(void)
{
return platform_driver_register(&imx8mq_pinctrl_driver);
}
arch_initcall(imx8mq_pinctrl_init);
MODULE_AUTHOR("Lucas Stach <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MQ pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8mq.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2017-2018 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx8mm_pads {
MX8MM_PAD_RESERVE0 = 0,
MX8MM_PAD_RESERVE1 = 1,
MX8MM_PAD_RESERVE2 = 2,
MX8MM_PAD_RESERVE3 = 3,
MX8MM_PAD_RESERVE4 = 4,
MX8MM_PAD_RESERVE5 = 5,
MX8MM_PAD_RESERVE6 = 6,
MX8MM_PAD_RESERVE7 = 7,
MX8MM_PAD_RESERVE8 = 8,
MX8MM_PAD_RESERVE9 = 9,
MX8MM_IOMUXC_GPIO1_IO00 = 10,
MX8MM_IOMUXC_GPIO1_IO01 = 11,
MX8MM_IOMUXC_GPIO1_IO02 = 12,
MX8MM_IOMUXC_GPIO1_IO03 = 13,
MX8MM_IOMUXC_GPIO1_IO04 = 14,
MX8MM_IOMUXC_GPIO1_IO05 = 15,
MX8MM_IOMUXC_GPIO1_IO06 = 16,
MX8MM_IOMUXC_GPIO1_IO07 = 17,
MX8MM_IOMUXC_GPIO1_IO08 = 18,
MX8MM_IOMUXC_GPIO1_IO09 = 19,
MX8MM_IOMUXC_GPIO1_IO10 = 20,
MX8MM_IOMUXC_GPIO1_IO11 = 21,
MX8MM_IOMUXC_GPIO1_IO12 = 22,
MX8MM_IOMUXC_GPIO1_IO13 = 23,
MX8MM_IOMUXC_GPIO1_IO14 = 24,
MX8MM_IOMUXC_GPIO1_IO15 = 25,
MX8MM_IOMUXC_ENET_MDC = 26,
MX8MM_IOMUXC_ENET_MDIO = 27,
MX8MM_IOMUXC_ENET_TD3 = 28,
MX8MM_IOMUXC_ENET_TD2 = 29,
MX8MM_IOMUXC_ENET_TD1 = 30,
MX8MM_IOMUXC_ENET_TD0 = 31,
MX8MM_IOMUXC_ENET_TX_CTL = 32,
MX8MM_IOMUXC_ENET_TXC = 33,
MX8MM_IOMUXC_ENET_RX_CTL = 34,
MX8MM_IOMUXC_ENET_RXC = 35,
MX8MM_IOMUXC_ENET_RD0 = 36,
MX8MM_IOMUXC_ENET_RD1 = 37,
MX8MM_IOMUXC_ENET_RD2 = 38,
MX8MM_IOMUXC_ENET_RD3 = 39,
MX8MM_IOMUXC_SD1_CLK = 40,
MX8MM_IOMUXC_SD1_CMD = 41,
MX8MM_IOMUXC_SD1_DATA0 = 42,
MX8MM_IOMUXC_SD1_DATA1 = 43,
MX8MM_IOMUXC_SD1_DATA2 = 44,
MX8MM_IOMUXC_SD1_DATA3 = 45,
MX8MM_IOMUXC_SD1_DATA4 = 46,
MX8MM_IOMUXC_SD1_DATA5 = 47,
MX8MM_IOMUXC_SD1_DATA6 = 48,
MX8MM_IOMUXC_SD1_DATA7 = 49,
MX8MM_IOMUXC_SD1_RESET_B = 50,
MX8MM_IOMUXC_SD1_STROBE = 51,
MX8MM_IOMUXC_SD2_CD_B = 52,
MX8MM_IOMUXC_SD2_CLK = 53,
MX8MM_IOMUXC_SD2_CMD = 54,
MX8MM_IOMUXC_SD2_DATA0 = 55,
MX8MM_IOMUXC_SD2_DATA1 = 56,
MX8MM_IOMUXC_SD2_DATA2 = 57,
MX8MM_IOMUXC_SD2_DATA3 = 58,
MX8MM_IOMUXC_SD2_RESET_B = 59,
MX8MM_IOMUXC_SD2_WP = 60,
MX8MM_IOMUXC_NAND_ALE = 61,
MX8MM_IOMUXC_NAND_CE0 = 62,
MX8MM_IOMUXC_NAND_CE1 = 63,
MX8MM_IOMUXC_NAND_CE2 = 64,
MX8MM_IOMUXC_NAND_CE3 = 65,
MX8MM_IOMUXC_NAND_CLE = 66,
MX8MM_IOMUXC_NAND_DATA00 = 67,
MX8MM_IOMUXC_NAND_DATA01 = 68,
MX8MM_IOMUXC_NAND_DATA02 = 69,
MX8MM_IOMUXC_NAND_DATA03 = 70,
MX8MM_IOMUXC_NAND_DATA04 = 71,
MX8MM_IOMUXC_NAND_DATA05 = 72,
MX8MM_IOMUXC_NAND_DATA06 = 73,
MX8MM_IOMUXC_NAND_DATA07 = 74,
MX8MM_IOMUXC_NAND_DQS = 75,
MX8MM_IOMUXC_NAND_RE_B = 76,
MX8MM_IOMUXC_NAND_READY_B = 77,
MX8MM_IOMUXC_NAND_WE_B = 78,
MX8MM_IOMUXC_NAND_WP_B = 79,
MX8MM_IOMUXC_SAI5_RXFS = 80,
MX8MM_IOMUXC_SAI5_RXC = 81,
MX8MM_IOMUXC_SAI5_RXD0 = 82,
MX8MM_IOMUXC_SAI5_RXD1 = 83,
MX8MM_IOMUXC_SAI5_RXD2 = 84,
MX8MM_IOMUXC_SAI5_RXD3 = 85,
MX8MM_IOMUXC_SAI5_MCLK = 86,
MX8MM_IOMUXC_SAI1_RXFS = 87,
MX8MM_IOMUXC_SAI1_RXC = 88,
MX8MM_IOMUXC_SAI1_RXD0 = 89,
MX8MM_IOMUXC_SAI1_RXD1 = 90,
MX8MM_IOMUXC_SAI1_RXD2 = 91,
MX8MM_IOMUXC_SAI1_RXD3 = 92,
MX8MM_IOMUXC_SAI1_RXD4 = 93,
MX8MM_IOMUXC_SAI1_RXD5 = 94,
MX8MM_IOMUXC_SAI1_RXD6 = 95,
MX8MM_IOMUXC_SAI1_RXD7 = 96,
MX8MM_IOMUXC_SAI1_TXFS = 97,
MX8MM_IOMUXC_SAI1_TXC = 98,
MX8MM_IOMUXC_SAI1_TXD0 = 99,
MX8MM_IOMUXC_SAI1_TXD1 = 100,
MX8MM_IOMUXC_SAI1_TXD2 = 101,
MX8MM_IOMUXC_SAI1_TXD3 = 102,
MX8MM_IOMUXC_SAI1_TXD4 = 103,
MX8MM_IOMUXC_SAI1_TXD5 = 104,
MX8MM_IOMUXC_SAI1_TXD6 = 105,
MX8MM_IOMUXC_SAI1_TXD7 = 106,
MX8MM_IOMUXC_SAI1_MCLK = 107,
MX8MM_IOMUXC_SAI2_RXFS = 108,
MX8MM_IOMUXC_SAI2_RXC = 109,
MX8MM_IOMUXC_SAI2_RXD0 = 110,
MX8MM_IOMUXC_SAI2_TXFS = 111,
MX8MM_IOMUXC_SAI2_TXC = 112,
MX8MM_IOMUXC_SAI2_TXD0 = 113,
MX8MM_IOMUXC_SAI2_MCLK = 114,
MX8MM_IOMUXC_SAI3_RXFS = 115,
MX8MM_IOMUXC_SAI3_RXC = 116,
MX8MM_IOMUXC_SAI3_RXD = 117,
MX8MM_IOMUXC_SAI3_TXFS = 118,
MX8MM_IOMUXC_SAI3_TXC = 119,
MX8MM_IOMUXC_SAI3_TXD = 120,
MX8MM_IOMUXC_SAI3_MCLK = 121,
MX8MM_IOMUXC_SPDIF_TX = 122,
MX8MM_IOMUXC_SPDIF_RX = 123,
MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
MX8MM_IOMUXC_ECSPI1_SCLK = 125,
MX8MM_IOMUXC_ECSPI1_MOSI = 126,
MX8MM_IOMUXC_ECSPI1_MISO = 127,
MX8MM_IOMUXC_ECSPI1_SS0 = 128,
MX8MM_IOMUXC_ECSPI2_SCLK = 129,
MX8MM_IOMUXC_ECSPI2_MOSI = 130,
MX8MM_IOMUXC_ECSPI2_MISO = 131,
MX8MM_IOMUXC_ECSPI2_SS0 = 132,
MX8MM_IOMUXC_I2C1_SCL = 133,
MX8MM_IOMUXC_I2C1_SDA = 134,
MX8MM_IOMUXC_I2C2_SCL = 135,
MX8MM_IOMUXC_I2C2_SDA = 136,
MX8MM_IOMUXC_I2C3_SCL = 137,
MX8MM_IOMUXC_I2C3_SDA = 138,
MX8MM_IOMUXC_I2C4_SCL = 139,
MX8MM_IOMUXC_I2C4_SDA = 140,
MX8MM_IOMUXC_UART1_RXD = 141,
MX8MM_IOMUXC_UART1_TXD = 142,
MX8MM_IOMUXC_UART2_RXD = 143,
MX8MM_IOMUXC_UART2_TXD = 144,
MX8MM_IOMUXC_UART3_RXD = 145,
MX8MM_IOMUXC_UART3_TXD = 146,
MX8MM_IOMUXC_UART4_RXD = 147,
MX8MM_IOMUXC_UART4_TXD = 148,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
};
static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
.pins = imx8mm_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
.gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
};
static const struct of_device_id imx8mm_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8mm_pinctrl_of_match);
static int imx8mm_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
}
static struct platform_driver imx8mm_pinctrl_driver = {
.driver = {
.name = "imx8mm-pinctrl",
.of_match_table = imx8mm_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mm_pinctrl_probe,
};
static int __init imx8mm_pinctrl_init(void)
{
return platform_driver_register(&imx8mm_pinctrl_driver);
}
arch_initcall(imx8mm_pinctrl_init);
MODULE_AUTHOR("Bai Ping <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MM pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8mm.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017~2018 NXP
* Dong Aisheng <[email protected]>
*/
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8qm_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QM_SIM0_CLK),
IMX_PINCTRL_PIN(IMX8QM_SIM0_RST),
IMX_PINCTRL_PIN(IMX8QM_SIM0_IO),
IMX_PINCTRL_PIN(IMX8QM_SIM0_PD),
IMX_PINCTRL_PIN(IMX8QM_SIM0_POWER_EN),
IMX_PINCTRL_PIN(IMX8QM_SIM0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM),
IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_M40_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_M40_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_M41_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_M41_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_GPT0_CLK),
IMX_PINCTRL_PIN(IMX8QM_GPT0_CAPTURE),
IMX_PINCTRL_PIN(IMX8QM_GPT0_COMPARE),
IMX_PINCTRL_PIN(IMX8QM_GPT1_CLK),
IMX_PINCTRL_PIN(IMX8QM_GPT1_CAPTURE),
IMX_PINCTRL_PIN(IMX8QM_GPT1_COMPARE),
IMX_PINCTRL_PIN(IMX8QM_UART0_RX),
IMX_PINCTRL_PIN(IMX8QM_UART0_TX),
IMX_PINCTRL_PIN(IMX8QM_UART0_RTS_B),
IMX_PINCTRL_PIN(IMX8QM_UART0_CTS_B),
IMX_PINCTRL_PIN(IMX8QM_UART1_TX),
IMX_PINCTRL_PIN(IMX8QM_UART1_RX),
IMX_PINCTRL_PIN(IMX8QM_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8QM_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8QM_SCU_PMIC_MEMC_ON),
IMX_PINCTRL_PIN(IMX8QM_SCU_WDOG_OUT),
IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8QM_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8QM_PMIC_EARLY_WARNING),
IMX_PINCTRL_PIN(IMX8QM_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_02),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_03),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_04),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_05),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_06),
IMX_PINCTRL_PIN(IMX8QM_SCU_GPIO0_07),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE3),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE4),
IMX_PINCTRL_PIN(IMX8QM_SCU_BOOT_MODE5),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO00),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_GPIO01),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SCL),
IMX_PINCTRL_PIN(IMX8QM_LVDS0_I2C1_SDA),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO00),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_GPIO01),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SCL),
IMX_PINCTRL_PIN(IMX8QM_LVDS1_I2C1_SDA),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_MIPI_DSI1_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_MCLK_OUT),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_MCLK_OUT),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QM_MIPI_CSI1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SCL),
IMX_PINCTRL_PIN(IMX8QM_HDMI_TX0_TS_SDA),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_FSR),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_FST),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKR),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_SCKT),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX0),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX1),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX2_RX3),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX3_RX2),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX4_RX1),
IMX_PINCTRL_PIN(IMX8QM_ESAI1_TX5_RX0),
IMX_PINCTRL_PIN(IMX8QM_SPDIF0_RX),
IMX_PINCTRL_PIN(IMX8QM_SPDIF0_TX),
IMX_PINCTRL_PIN(IMX8QM_SPDIF0_EXT_CLK),
IMX_PINCTRL_PIN(IMX8QM_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8QM_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8QM_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8QM_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8QM_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_FSR),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_FST),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKR),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_SCKT),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX0),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX1),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX2_RX3),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX3_RX2),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX4_RX1),
IMX_PINCTRL_PIN(IMX8QM_ESAI0_TX5_RX0),
IMX_PINCTRL_PIN(IMX8QM_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8QM_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC),
IMX_PINCTRL_PIN(IMX8QM_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8QM_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8QM_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8QM_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8QM_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8QM_SPI2_SCK),
IMX_PINCTRL_PIN(IMX8QM_SPI2_SDO),
IMX_PINCTRL_PIN(IMX8QM_SPI2_SDI),
IMX_PINCTRL_PIN(IMX8QM_SPI2_CS0),
IMX_PINCTRL_PIN(IMX8QM_SPI2_CS1),
IMX_PINCTRL_PIN(IMX8QM_SAI1_RXC),
IMX_PINCTRL_PIN(IMX8QM_SAI1_RXD),
IMX_PINCTRL_PIN(IMX8QM_SAI1_RXFS),
IMX_PINCTRL_PIN(IMX8QM_SAI1_TXC),
IMX_PINCTRL_PIN(IMX8QM_SAI1_TXD),
IMX_PINCTRL_PIN(IMX8QM_SAI1_TXFS),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN7),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN6),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN5),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN4),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN3),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN2),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN1),
IMX_PINCTRL_PIN(IMX8QM_ADC_IN0),
IMX_PINCTRL_PIN(IMX8QM_MLB_SIG),
IMX_PINCTRL_PIN(IMX8QM_MLB_CLK),
IMX_PINCTRL_PIN(IMX8QM_MLB_DATA),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8QM_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR),
IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8QM_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_RESET_B),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_VSELECT),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_WP),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_CD_B),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8QM_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8QM_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8QM_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8QM_ENET1_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8QM_ENET1_MDIO),
IMX_PINCTRL_PIN(IMX8QM_ENET1_MDC),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS0_B),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SS1_B),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_SCLK),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DQS),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA3),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA2),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA1),
IMX_PINCTRL_PIN(IMX8QM_QSPI1A_DATA0),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SS1_B),
IMX_PINCTRL_PIN(IMX8QM_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8QM_QSPI0B_SS1_B),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_WAKE_B),
IMX_PINCTRL_PIN(IMX8QM_PCIE_CTRL1_PERST_B),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_DATA),
IMX_PINCTRL_PIN(IMX8QM_USB_HSIC0_STROBE),
IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_0_HSIC),
IMX_PINCTRL_PIN(IMX8QM_CALIBRATION_1_HSIC),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8QM_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_CLK),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_CMD),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA0),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA1),
IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA2),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA3),
IMX_PINCTRL_PIN(IMX8QM_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA4),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA5),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA6),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_DATA7),
IMX_PINCTRL_PIN(IMX8QM_USDHC1_STROBE),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_CLK),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_CMD),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA0),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA1),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA2),
IMX_PINCTRL_PIN(IMX8QM_USDHC2_DATA3),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8QM_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8QM_ENET1_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA),
};
static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = {
.pins = imx8qm_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qm_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qm_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8qm-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8qm_pinctrl_of_match);
static int imx8qm_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8qm_pinctrl_info);
}
static struct platform_driver imx8qm_pinctrl_driver = {
.driver = {
.name = "imx8qm-pinctrl",
.of_match_table = imx8qm_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8qm_pinctrl_probe,
};
static int __init imx8qm_pinctrl_init(void)
{
return platform_driver_register(&imx8qm_pinctrl_driver);
}
arch_initcall(imx8qm_pinctrl_init);
MODULE_AUTHOR("Aisheng Dong <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8qm.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// i.MX1 pinctrl driver based on imx pinmux core
//
// Copyright (C) 2014 Alexander Shiyan <[email protected]>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) ((port) * 32 + (pin))
#define PA 0
#define PB 1
#define PC 2
#define PD 3
enum imx1_pads {
MX1_PAD_A24 = PAD_ID(PA, 0),
MX1_PAD_TIN = PAD_ID(PA, 1),
MX1_PAD_PWMO = PAD_ID(PA, 2),
MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
MX1_PAD_DTACK = PAD_ID(PA, 17),
MX1_PAD_BCLK = PAD_ID(PA, 18),
MX1_PAD_LBA = PAD_ID(PA, 19),
MX1_PAD_ECB = PAD_ID(PA, 20),
MX1_PAD_A0 = PAD_ID(PA, 21),
MX1_PAD_CS4 = PAD_ID(PA, 22),
MX1_PAD_CS5 = PAD_ID(PA, 23),
MX1_PAD_A16 = PAD_ID(PA, 24),
MX1_PAD_A17 = PAD_ID(PA, 25),
MX1_PAD_A18 = PAD_ID(PA, 26),
MX1_PAD_A19 = PAD_ID(PA, 27),
MX1_PAD_A20 = PAD_ID(PA, 28),
MX1_PAD_A21 = PAD_ID(PA, 29),
MX1_PAD_A22 = PAD_ID(PA, 30),
MX1_PAD_A23 = PAD_ID(PA, 31),
MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
MX1_PAD_SD_CMD = PAD_ID(PB, 13),
MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
MX1_PAD_SIM_PD = PAD_ID(PB, 15),
MX1_PAD_SIM_TX = PAD_ID(PB, 16),
MX1_PAD_SIM_RX = PAD_ID(PB, 17),
MX1_PAD_SIM_RST = PAD_ID(PB, 18),
MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
MX1_PAD_USBD_OE = PAD_ID(PB, 21),
MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
MX1_PAD_USBD_VP = PAD_ID(PB, 24),
MX1_PAD_USBD_VM = PAD_ID(PB, 25),
MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
MX1_PAD_BT13 = PAD_ID(PC, 19),
MX1_PAD_BT12 = PAD_ID(PC, 20),
MX1_PAD_BT11 = PAD_ID(PC, 21),
MX1_PAD_BT10 = PAD_ID(PC, 22),
MX1_PAD_BT9 = PAD_ID(PC, 23),
MX1_PAD_BT8 = PAD_ID(PC, 24),
MX1_PAD_BT7 = PAD_ID(PC, 25),
MX1_PAD_BT6 = PAD_ID(PC, 26),
MX1_PAD_BT5 = PAD_ID(PC, 27),
MX1_PAD_BT4 = PAD_ID(PC, 28),
MX1_PAD_BT3 = PAD_ID(PC, 29),
MX1_PAD_BT2 = PAD_ID(PC, 30),
MX1_PAD_BT1 = PAD_ID(PC, 31),
MX1_PAD_LSCLK = PAD_ID(PD, 6),
MX1_PAD_REV = PAD_ID(PD, 7),
MX1_PAD_CLS = PAD_ID(PD, 8),
MX1_PAD_PS = PAD_ID(PD, 9),
MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
MX1_PAD_CONTRAST = PAD_ID(PD, 11),
MX1_PAD_ACD_OE = PAD_ID(PD, 12),
MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
MX1_PAD_LD0 = PAD_ID(PD, 15),
MX1_PAD_LD1 = PAD_ID(PD, 16),
MX1_PAD_LD2 = PAD_ID(PD, 17),
MX1_PAD_LD3 = PAD_ID(PD, 18),
MX1_PAD_LD4 = PAD_ID(PD, 19),
MX1_PAD_LD5 = PAD_ID(PD, 20),
MX1_PAD_LD6 = PAD_ID(PD, 21),
MX1_PAD_LD7 = PAD_ID(PD, 22),
MX1_PAD_LD8 = PAD_ID(PD, 23),
MX1_PAD_LD9 = PAD_ID(PD, 24),
MX1_PAD_LD10 = PAD_ID(PD, 25),
MX1_PAD_LD11 = PAD_ID(PD, 26),
MX1_PAD_LD12 = PAD_ID(PD, 27),
MX1_PAD_LD13 = PAD_ID(PD, 28),
MX1_PAD_LD14 = PAD_ID(PD, 29),
MX1_PAD_LD15 = PAD_ID(PD, 30),
MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX1_PAD_A24),
IMX_PINCTRL_PIN(MX1_PAD_TIN),
IMX_PINCTRL_PIN(MX1_PAD_PWMO),
IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
IMX_PINCTRL_PIN(MX1_PAD_DTACK),
IMX_PINCTRL_PIN(MX1_PAD_BCLK),
IMX_PINCTRL_PIN(MX1_PAD_LBA),
IMX_PINCTRL_PIN(MX1_PAD_ECB),
IMX_PINCTRL_PIN(MX1_PAD_A0),
IMX_PINCTRL_PIN(MX1_PAD_CS4),
IMX_PINCTRL_PIN(MX1_PAD_CS5),
IMX_PINCTRL_PIN(MX1_PAD_A16),
IMX_PINCTRL_PIN(MX1_PAD_A17),
IMX_PINCTRL_PIN(MX1_PAD_A18),
IMX_PINCTRL_PIN(MX1_PAD_A19),
IMX_PINCTRL_PIN(MX1_PAD_A20),
IMX_PINCTRL_PIN(MX1_PAD_A21),
IMX_PINCTRL_PIN(MX1_PAD_A22),
IMX_PINCTRL_PIN(MX1_PAD_A23),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
IMX_PINCTRL_PIN(MX1_PAD_BT13),
IMX_PINCTRL_PIN(MX1_PAD_BT12),
IMX_PINCTRL_PIN(MX1_PAD_BT11),
IMX_PINCTRL_PIN(MX1_PAD_BT10),
IMX_PINCTRL_PIN(MX1_PAD_BT9),
IMX_PINCTRL_PIN(MX1_PAD_BT8),
IMX_PINCTRL_PIN(MX1_PAD_BT7),
IMX_PINCTRL_PIN(MX1_PAD_BT6),
IMX_PINCTRL_PIN(MX1_PAD_BT5),
IMX_PINCTRL_PIN(MX1_PAD_BT4),
IMX_PINCTRL_PIN(MX1_PAD_BT3),
IMX_PINCTRL_PIN(MX1_PAD_BT2),
IMX_PINCTRL_PIN(MX1_PAD_BT1),
IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
IMX_PINCTRL_PIN(MX1_PAD_REV),
IMX_PINCTRL_PIN(MX1_PAD_CLS),
IMX_PINCTRL_PIN(MX1_PAD_PS),
IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
IMX_PINCTRL_PIN(MX1_PAD_LD0),
IMX_PINCTRL_PIN(MX1_PAD_LD1),
IMX_PINCTRL_PIN(MX1_PAD_LD2),
IMX_PINCTRL_PIN(MX1_PAD_LD3),
IMX_PINCTRL_PIN(MX1_PAD_LD4),
IMX_PINCTRL_PIN(MX1_PAD_LD5),
IMX_PINCTRL_PIN(MX1_PAD_LD6),
IMX_PINCTRL_PIN(MX1_PAD_LD7),
IMX_PINCTRL_PIN(MX1_PAD_LD8),
IMX_PINCTRL_PIN(MX1_PAD_LD9),
IMX_PINCTRL_PIN(MX1_PAD_LD10),
IMX_PINCTRL_PIN(MX1_PAD_LD11),
IMX_PINCTRL_PIN(MX1_PAD_LD12),
IMX_PINCTRL_PIN(MX1_PAD_LD13),
IMX_PINCTRL_PIN(MX1_PAD_LD14),
IMX_PINCTRL_PIN(MX1_PAD_LD15),
IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
};
static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
.pins = imx1_pinctrl_pads,
.npins = ARRAY_SIZE(imx1_pinctrl_pads),
};
static int __init imx1_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
}
static const struct of_device_id imx1_pinctrl_of_match[] = {
{ .compatible = "fsl,imx1-iomuxc", },
{ }
};
static struct platform_driver imx1_pinctrl_driver = {
.driver = {
.name = "imx1-pinctrl",
.of_match_table = imx1_pinctrl_of_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx1.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019~2020 NXP
*/
#include <dt-bindings/pinctrl/pads-imx8dxl.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8DXL_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_WP),
IMX_PINCTRL_PIN(IMX8DXL_USDHC1_CD_B),
IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8DXL_ENET1_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN1),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8DXL_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8DXL_UART1_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART1_RX),
IMX_PINCTRL_PIN(IMX8DXL_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8DXL_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN1),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN0),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN3),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN2),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN5),
IMX_PINCTRL_PIN(IMX8DXL_ADC_IN4),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART0_RX),
IMX_PINCTRL_PIN(IMX8DXL_UART0_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART2_TX),
IMX_PINCTRL_PIN(IMX8DXL_UART2_RX),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8DXL_JTAG_TRST_B),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8DXL_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8DXL_SCU_PMIC_STANDBY),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT1),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT3),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT4),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN0),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN1),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN2),
IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN3),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SCK),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDO),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDI),
IMX_PINCTRL_PIN(IMX8DXL_SPI1_CS0),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B)
};
static const struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
.pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8dxl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8dxl-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8dxl_pinctrl_of_match);
static int imx8dxl_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8dxl_pinctrl_info);
}
static struct platform_driver imx8dxl_pinctrl_driver = {
.driver = {
.name = "fsl,imx8dxl-iomuxc",
.of_match_table = imx8dxl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8dxl_pinctrl_probe,
};
static int __init imx8dxl_pinctrl_init(void)
{
return platform_driver_register(&imx8dxl_pinctrl_driver);
}
arch_initcall(imx8dxl_pinctrl_init);
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8DXL pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// Freescale i.MX28 pinctrl driver
//
// Author: Shawn Guo <[email protected]>
// Copyright 2012 Freescale Semiconductor, Inc.
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
enum imx28_pin_enum {
GPMI_D00 = PINID(0, 0),
GPMI_D01 = PINID(0, 1),
GPMI_D02 = PINID(0, 2),
GPMI_D03 = PINID(0, 3),
GPMI_D04 = PINID(0, 4),
GPMI_D05 = PINID(0, 5),
GPMI_D06 = PINID(0, 6),
GPMI_D07 = PINID(0, 7),
GPMI_CE0N = PINID(0, 16),
GPMI_CE1N = PINID(0, 17),
GPMI_CE2N = PINID(0, 18),
GPMI_CE3N = PINID(0, 19),
GPMI_RDY0 = PINID(0, 20),
GPMI_RDY1 = PINID(0, 21),
GPMI_RDY2 = PINID(0, 22),
GPMI_RDY3 = PINID(0, 23),
GPMI_RDN = PINID(0, 24),
GPMI_WRN = PINID(0, 25),
GPMI_ALE = PINID(0, 26),
GPMI_CLE = PINID(0, 27),
GPMI_RESETN = PINID(0, 28),
LCD_D00 = PINID(1, 0),
LCD_D01 = PINID(1, 1),
LCD_D02 = PINID(1, 2),
LCD_D03 = PINID(1, 3),
LCD_D04 = PINID(1, 4),
LCD_D05 = PINID(1, 5),
LCD_D06 = PINID(1, 6),
LCD_D07 = PINID(1, 7),
LCD_D08 = PINID(1, 8),
LCD_D09 = PINID(1, 9),
LCD_D10 = PINID(1, 10),
LCD_D11 = PINID(1, 11),
LCD_D12 = PINID(1, 12),
LCD_D13 = PINID(1, 13),
LCD_D14 = PINID(1, 14),
LCD_D15 = PINID(1, 15),
LCD_D16 = PINID(1, 16),
LCD_D17 = PINID(1, 17),
LCD_D18 = PINID(1, 18),
LCD_D19 = PINID(1, 19),
LCD_D20 = PINID(1, 20),
LCD_D21 = PINID(1, 21),
LCD_D22 = PINID(1, 22),
LCD_D23 = PINID(1, 23),
LCD_RD_E = PINID(1, 24),
LCD_WR_RWN = PINID(1, 25),
LCD_RS = PINID(1, 26),
LCD_CS = PINID(1, 27),
LCD_VSYNC = PINID(1, 28),
LCD_HSYNC = PINID(1, 29),
LCD_DOTCLK = PINID(1, 30),
LCD_ENABLE = PINID(1, 31),
SSP0_DATA0 = PINID(2, 0),
SSP0_DATA1 = PINID(2, 1),
SSP0_DATA2 = PINID(2, 2),
SSP0_DATA3 = PINID(2, 3),
SSP0_DATA4 = PINID(2, 4),
SSP0_DATA5 = PINID(2, 5),
SSP0_DATA6 = PINID(2, 6),
SSP0_DATA7 = PINID(2, 7),
SSP0_CMD = PINID(2, 8),
SSP0_DETECT = PINID(2, 9),
SSP0_SCK = PINID(2, 10),
SSP1_SCK = PINID(2, 12),
SSP1_CMD = PINID(2, 13),
SSP1_DATA0 = PINID(2, 14),
SSP1_DATA3 = PINID(2, 15),
SSP2_SCK = PINID(2, 16),
SSP2_MOSI = PINID(2, 17),
SSP2_MISO = PINID(2, 18),
SSP2_SS0 = PINID(2, 19),
SSP2_SS1 = PINID(2, 20),
SSP2_SS2 = PINID(2, 21),
SSP3_SCK = PINID(2, 24),
SSP3_MOSI = PINID(2, 25),
SSP3_MISO = PINID(2, 26),
SSP3_SS0 = PINID(2, 27),
AUART0_RX = PINID(3, 0),
AUART0_TX = PINID(3, 1),
AUART0_CTS = PINID(3, 2),
AUART0_RTS = PINID(3, 3),
AUART1_RX = PINID(3, 4),
AUART1_TX = PINID(3, 5),
AUART1_CTS = PINID(3, 6),
AUART1_RTS = PINID(3, 7),
AUART2_RX = PINID(3, 8),
AUART2_TX = PINID(3, 9),
AUART2_CTS = PINID(3, 10),
AUART2_RTS = PINID(3, 11),
AUART3_RX = PINID(3, 12),
AUART3_TX = PINID(3, 13),
AUART3_CTS = PINID(3, 14),
AUART3_RTS = PINID(3, 15),
PWM0 = PINID(3, 16),
PWM1 = PINID(3, 17),
PWM2 = PINID(3, 18),
SAIF0_MCLK = PINID(3, 20),
SAIF0_LRCLK = PINID(3, 21),
SAIF0_BITCLK = PINID(3, 22),
SAIF0_SDATA0 = PINID(3, 23),
I2C0_SCL = PINID(3, 24),
I2C0_SDA = PINID(3, 25),
SAIF1_SDATA0 = PINID(3, 26),
SPDIF = PINID(3, 27),
PWM3 = PINID(3, 28),
PWM4 = PINID(3, 29),
LCD_RESET = PINID(3, 30),
ENET0_MDC = PINID(4, 0),
ENET0_MDIO = PINID(4, 1),
ENET0_RX_EN = PINID(4, 2),
ENET0_RXD0 = PINID(4, 3),
ENET0_RXD1 = PINID(4, 4),
ENET0_TX_CLK = PINID(4, 5),
ENET0_TX_EN = PINID(4, 6),
ENET0_TXD0 = PINID(4, 7),
ENET0_TXD1 = PINID(4, 8),
ENET0_RXD2 = PINID(4, 9),
ENET0_RXD3 = PINID(4, 10),
ENET0_TXD2 = PINID(4, 11),
ENET0_TXD3 = PINID(4, 12),
ENET0_RX_CLK = PINID(4, 13),
ENET0_COL = PINID(4, 14),
ENET0_CRS = PINID(4, 15),
ENET_CLK = PINID(4, 16),
JTAG_RTCK = PINID(4, 20),
EMI_D00 = PINID(5, 0),
EMI_D01 = PINID(5, 1),
EMI_D02 = PINID(5, 2),
EMI_D03 = PINID(5, 3),
EMI_D04 = PINID(5, 4),
EMI_D05 = PINID(5, 5),
EMI_D06 = PINID(5, 6),
EMI_D07 = PINID(5, 7),
EMI_D08 = PINID(5, 8),
EMI_D09 = PINID(5, 9),
EMI_D10 = PINID(5, 10),
EMI_D11 = PINID(5, 11),
EMI_D12 = PINID(5, 12),
EMI_D13 = PINID(5, 13),
EMI_D14 = PINID(5, 14),
EMI_D15 = PINID(5, 15),
EMI_ODT0 = PINID(5, 16),
EMI_DQM0 = PINID(5, 17),
EMI_ODT1 = PINID(5, 18),
EMI_DQM1 = PINID(5, 19),
EMI_DDR_OPEN_FB = PINID(5, 20),
EMI_CLK = PINID(5, 21),
EMI_DQS0 = PINID(5, 22),
EMI_DQS1 = PINID(5, 23),
EMI_DDR_OPEN = PINID(5, 26),
EMI_A00 = PINID(6, 0),
EMI_A01 = PINID(6, 1),
EMI_A02 = PINID(6, 2),
EMI_A03 = PINID(6, 3),
EMI_A04 = PINID(6, 4),
EMI_A05 = PINID(6, 5),
EMI_A06 = PINID(6, 6),
EMI_A07 = PINID(6, 7),
EMI_A08 = PINID(6, 8),
EMI_A09 = PINID(6, 9),
EMI_A10 = PINID(6, 10),
EMI_A11 = PINID(6, 11),
EMI_A12 = PINID(6, 12),
EMI_A13 = PINID(6, 13),
EMI_A14 = PINID(6, 14),
EMI_BA0 = PINID(6, 16),
EMI_BA1 = PINID(6, 17),
EMI_BA2 = PINID(6, 18),
EMI_CASN = PINID(6, 19),
EMI_RASN = PINID(6, 20),
EMI_WEN = PINID(6, 21),
EMI_CE0N = PINID(6, 22),
EMI_CE1N = PINID(6, 23),
EMI_CKE = PINID(6, 24),
};
static const struct pinctrl_pin_desc imx28_pins[] = {
MXS_PINCTRL_PIN(GPMI_D00),
MXS_PINCTRL_PIN(GPMI_D01),
MXS_PINCTRL_PIN(GPMI_D02),
MXS_PINCTRL_PIN(GPMI_D03),
MXS_PINCTRL_PIN(GPMI_D04),
MXS_PINCTRL_PIN(GPMI_D05),
MXS_PINCTRL_PIN(GPMI_D06),
MXS_PINCTRL_PIN(GPMI_D07),
MXS_PINCTRL_PIN(GPMI_CE0N),
MXS_PINCTRL_PIN(GPMI_CE1N),
MXS_PINCTRL_PIN(GPMI_CE2N),
MXS_PINCTRL_PIN(GPMI_CE3N),
MXS_PINCTRL_PIN(GPMI_RDY0),
MXS_PINCTRL_PIN(GPMI_RDY1),
MXS_PINCTRL_PIN(GPMI_RDY2),
MXS_PINCTRL_PIN(GPMI_RDY3),
MXS_PINCTRL_PIN(GPMI_RDN),
MXS_PINCTRL_PIN(GPMI_WRN),
MXS_PINCTRL_PIN(GPMI_ALE),
MXS_PINCTRL_PIN(GPMI_CLE),
MXS_PINCTRL_PIN(GPMI_RESETN),
MXS_PINCTRL_PIN(LCD_D00),
MXS_PINCTRL_PIN(LCD_D01),
MXS_PINCTRL_PIN(LCD_D02),
MXS_PINCTRL_PIN(LCD_D03),
MXS_PINCTRL_PIN(LCD_D04),
MXS_PINCTRL_PIN(LCD_D05),
MXS_PINCTRL_PIN(LCD_D06),
MXS_PINCTRL_PIN(LCD_D07),
MXS_PINCTRL_PIN(LCD_D08),
MXS_PINCTRL_PIN(LCD_D09),
MXS_PINCTRL_PIN(LCD_D10),
MXS_PINCTRL_PIN(LCD_D11),
MXS_PINCTRL_PIN(LCD_D12),
MXS_PINCTRL_PIN(LCD_D13),
MXS_PINCTRL_PIN(LCD_D14),
MXS_PINCTRL_PIN(LCD_D15),
MXS_PINCTRL_PIN(LCD_D16),
MXS_PINCTRL_PIN(LCD_D17),
MXS_PINCTRL_PIN(LCD_D18),
MXS_PINCTRL_PIN(LCD_D19),
MXS_PINCTRL_PIN(LCD_D20),
MXS_PINCTRL_PIN(LCD_D21),
MXS_PINCTRL_PIN(LCD_D22),
MXS_PINCTRL_PIN(LCD_D23),
MXS_PINCTRL_PIN(LCD_RD_E),
MXS_PINCTRL_PIN(LCD_WR_RWN),
MXS_PINCTRL_PIN(LCD_RS),
MXS_PINCTRL_PIN(LCD_CS),
MXS_PINCTRL_PIN(LCD_VSYNC),
MXS_PINCTRL_PIN(LCD_HSYNC),
MXS_PINCTRL_PIN(LCD_DOTCLK),
MXS_PINCTRL_PIN(LCD_ENABLE),
MXS_PINCTRL_PIN(SSP0_DATA0),
MXS_PINCTRL_PIN(SSP0_DATA1),
MXS_PINCTRL_PIN(SSP0_DATA2),
MXS_PINCTRL_PIN(SSP0_DATA3),
MXS_PINCTRL_PIN(SSP0_DATA4),
MXS_PINCTRL_PIN(SSP0_DATA5),
MXS_PINCTRL_PIN(SSP0_DATA6),
MXS_PINCTRL_PIN(SSP0_DATA7),
MXS_PINCTRL_PIN(SSP0_CMD),
MXS_PINCTRL_PIN(SSP0_DETECT),
MXS_PINCTRL_PIN(SSP0_SCK),
MXS_PINCTRL_PIN(SSP1_SCK),
MXS_PINCTRL_PIN(SSP1_CMD),
MXS_PINCTRL_PIN(SSP1_DATA0),
MXS_PINCTRL_PIN(SSP1_DATA3),
MXS_PINCTRL_PIN(SSP2_SCK),
MXS_PINCTRL_PIN(SSP2_MOSI),
MXS_PINCTRL_PIN(SSP2_MISO),
MXS_PINCTRL_PIN(SSP2_SS0),
MXS_PINCTRL_PIN(SSP2_SS1),
MXS_PINCTRL_PIN(SSP2_SS2),
MXS_PINCTRL_PIN(SSP3_SCK),
MXS_PINCTRL_PIN(SSP3_MOSI),
MXS_PINCTRL_PIN(SSP3_MISO),
MXS_PINCTRL_PIN(SSP3_SS0),
MXS_PINCTRL_PIN(AUART0_RX),
MXS_PINCTRL_PIN(AUART0_TX),
MXS_PINCTRL_PIN(AUART0_CTS),
MXS_PINCTRL_PIN(AUART0_RTS),
MXS_PINCTRL_PIN(AUART1_RX),
MXS_PINCTRL_PIN(AUART1_TX),
MXS_PINCTRL_PIN(AUART1_CTS),
MXS_PINCTRL_PIN(AUART1_RTS),
MXS_PINCTRL_PIN(AUART2_RX),
MXS_PINCTRL_PIN(AUART2_TX),
MXS_PINCTRL_PIN(AUART2_CTS),
MXS_PINCTRL_PIN(AUART2_RTS),
MXS_PINCTRL_PIN(AUART3_RX),
MXS_PINCTRL_PIN(AUART3_TX),
MXS_PINCTRL_PIN(AUART3_CTS),
MXS_PINCTRL_PIN(AUART3_RTS),
MXS_PINCTRL_PIN(PWM0),
MXS_PINCTRL_PIN(PWM1),
MXS_PINCTRL_PIN(PWM2),
MXS_PINCTRL_PIN(SAIF0_MCLK),
MXS_PINCTRL_PIN(SAIF0_LRCLK),
MXS_PINCTRL_PIN(SAIF0_BITCLK),
MXS_PINCTRL_PIN(SAIF0_SDATA0),
MXS_PINCTRL_PIN(I2C0_SCL),
MXS_PINCTRL_PIN(I2C0_SDA),
MXS_PINCTRL_PIN(SAIF1_SDATA0),
MXS_PINCTRL_PIN(SPDIF),
MXS_PINCTRL_PIN(PWM3),
MXS_PINCTRL_PIN(PWM4),
MXS_PINCTRL_PIN(LCD_RESET),
MXS_PINCTRL_PIN(ENET0_MDC),
MXS_PINCTRL_PIN(ENET0_MDIO),
MXS_PINCTRL_PIN(ENET0_RX_EN),
MXS_PINCTRL_PIN(ENET0_RXD0),
MXS_PINCTRL_PIN(ENET0_RXD1),
MXS_PINCTRL_PIN(ENET0_TX_CLK),
MXS_PINCTRL_PIN(ENET0_TX_EN),
MXS_PINCTRL_PIN(ENET0_TXD0),
MXS_PINCTRL_PIN(ENET0_TXD1),
MXS_PINCTRL_PIN(ENET0_RXD2),
MXS_PINCTRL_PIN(ENET0_RXD3),
MXS_PINCTRL_PIN(ENET0_TXD2),
MXS_PINCTRL_PIN(ENET0_TXD3),
MXS_PINCTRL_PIN(ENET0_RX_CLK),
MXS_PINCTRL_PIN(ENET0_COL),
MXS_PINCTRL_PIN(ENET0_CRS),
MXS_PINCTRL_PIN(ENET_CLK),
MXS_PINCTRL_PIN(JTAG_RTCK),
MXS_PINCTRL_PIN(EMI_D00),
MXS_PINCTRL_PIN(EMI_D01),
MXS_PINCTRL_PIN(EMI_D02),
MXS_PINCTRL_PIN(EMI_D03),
MXS_PINCTRL_PIN(EMI_D04),
MXS_PINCTRL_PIN(EMI_D05),
MXS_PINCTRL_PIN(EMI_D06),
MXS_PINCTRL_PIN(EMI_D07),
MXS_PINCTRL_PIN(EMI_D08),
MXS_PINCTRL_PIN(EMI_D09),
MXS_PINCTRL_PIN(EMI_D10),
MXS_PINCTRL_PIN(EMI_D11),
MXS_PINCTRL_PIN(EMI_D12),
MXS_PINCTRL_PIN(EMI_D13),
MXS_PINCTRL_PIN(EMI_D14),
MXS_PINCTRL_PIN(EMI_D15),
MXS_PINCTRL_PIN(EMI_ODT0),
MXS_PINCTRL_PIN(EMI_DQM0),
MXS_PINCTRL_PIN(EMI_ODT1),
MXS_PINCTRL_PIN(EMI_DQM1),
MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
MXS_PINCTRL_PIN(EMI_CLK),
MXS_PINCTRL_PIN(EMI_DQS0),
MXS_PINCTRL_PIN(EMI_DQS1),
MXS_PINCTRL_PIN(EMI_DDR_OPEN),
MXS_PINCTRL_PIN(EMI_A00),
MXS_PINCTRL_PIN(EMI_A01),
MXS_PINCTRL_PIN(EMI_A02),
MXS_PINCTRL_PIN(EMI_A03),
MXS_PINCTRL_PIN(EMI_A04),
MXS_PINCTRL_PIN(EMI_A05),
MXS_PINCTRL_PIN(EMI_A06),
MXS_PINCTRL_PIN(EMI_A07),
MXS_PINCTRL_PIN(EMI_A08),
MXS_PINCTRL_PIN(EMI_A09),
MXS_PINCTRL_PIN(EMI_A10),
MXS_PINCTRL_PIN(EMI_A11),
MXS_PINCTRL_PIN(EMI_A12),
MXS_PINCTRL_PIN(EMI_A13),
MXS_PINCTRL_PIN(EMI_A14),
MXS_PINCTRL_PIN(EMI_BA0),
MXS_PINCTRL_PIN(EMI_BA1),
MXS_PINCTRL_PIN(EMI_BA2),
MXS_PINCTRL_PIN(EMI_CASN),
MXS_PINCTRL_PIN(EMI_RASN),
MXS_PINCTRL_PIN(EMI_WEN),
MXS_PINCTRL_PIN(EMI_CE0N),
MXS_PINCTRL_PIN(EMI_CE1N),
MXS_PINCTRL_PIN(EMI_CKE),
};
static const struct mxs_regs imx28_regs = {
.muxsel = 0x100,
.drive = 0x300,
.pull = 0x600,
};
static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
.regs = &imx28_regs,
.pins = imx28_pins,
.npins = ARRAY_SIZE(imx28_pins),
};
static int imx28_pinctrl_probe(struct platform_device *pdev)
{
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
}
static const struct of_device_id imx28_pinctrl_of_match[] = {
{ .compatible = "fsl,imx28-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver imx28_pinctrl_driver = {
.driver = {
.name = "imx28-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = imx28_pinctrl_of_match,
},
.probe = imx28_pinctrl_probe,
};
static int __init imx28_pinctrl_init(void)
{
return platform_driver_register(&imx28_pinctrl_driver);
}
postcore_initcall(imx28_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx28.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Freescale imx6sl pinctrl driver
//
// Author: Shawn Guo <[email protected]>
// Copyright (C) 2013 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sl_pads {
MX6SL_PAD_RESERVE0 = 0,
MX6SL_PAD_RESERVE1 = 1,
MX6SL_PAD_RESERVE2 = 2,
MX6SL_PAD_RESERVE3 = 3,
MX6SL_PAD_RESERVE4 = 4,
MX6SL_PAD_RESERVE5 = 5,
MX6SL_PAD_RESERVE6 = 6,
MX6SL_PAD_RESERVE7 = 7,
MX6SL_PAD_RESERVE8 = 8,
MX6SL_PAD_RESERVE9 = 9,
MX6SL_PAD_RESERVE10 = 10,
MX6SL_PAD_RESERVE11 = 11,
MX6SL_PAD_RESERVE12 = 12,
MX6SL_PAD_RESERVE13 = 13,
MX6SL_PAD_RESERVE14 = 14,
MX6SL_PAD_RESERVE15 = 15,
MX6SL_PAD_RESERVE16 = 16,
MX6SL_PAD_RESERVE17 = 17,
MX6SL_PAD_RESERVE18 = 18,
MX6SL_PAD_AUD_MCLK = 19,
MX6SL_PAD_AUD_RXC = 20,
MX6SL_PAD_AUD_RXD = 21,
MX6SL_PAD_AUD_RXFS = 22,
MX6SL_PAD_AUD_TXC = 23,
MX6SL_PAD_AUD_TXD = 24,
MX6SL_PAD_AUD_TXFS = 25,
MX6SL_PAD_ECSPI1_MISO = 26,
MX6SL_PAD_ECSPI1_MOSI = 27,
MX6SL_PAD_ECSPI1_SCLK = 28,
MX6SL_PAD_ECSPI1_SS0 = 29,
MX6SL_PAD_ECSPI2_MISO = 30,
MX6SL_PAD_ECSPI2_MOSI = 31,
MX6SL_PAD_ECSPI2_SCLK = 32,
MX6SL_PAD_ECSPI2_SS0 = 33,
MX6SL_PAD_EPDC_BDR0 = 34,
MX6SL_PAD_EPDC_BDR1 = 35,
MX6SL_PAD_EPDC_D0 = 36,
MX6SL_PAD_EPDC_D1 = 37,
MX6SL_PAD_EPDC_D10 = 38,
MX6SL_PAD_EPDC_D11 = 39,
MX6SL_PAD_EPDC_D12 = 40,
MX6SL_PAD_EPDC_D13 = 41,
MX6SL_PAD_EPDC_D14 = 42,
MX6SL_PAD_EPDC_D15 = 43,
MX6SL_PAD_EPDC_D2 = 44,
MX6SL_PAD_EPDC_D3 = 45,
MX6SL_PAD_EPDC_D4 = 46,
MX6SL_PAD_EPDC_D5 = 47,
MX6SL_PAD_EPDC_D6 = 48,
MX6SL_PAD_EPDC_D7 = 49,
MX6SL_PAD_EPDC_D8 = 50,
MX6SL_PAD_EPDC_D9 = 51,
MX6SL_PAD_EPDC_GDCLK = 52,
MX6SL_PAD_EPDC_GDOE = 53,
MX6SL_PAD_EPDC_GDRL = 54,
MX6SL_PAD_EPDC_GDSP = 55,
MX6SL_PAD_EPDC_PWRCOM = 56,
MX6SL_PAD_EPDC_PWRCTRL0 = 57,
MX6SL_PAD_EPDC_PWRCTRL1 = 58,
MX6SL_PAD_EPDC_PWRCTRL2 = 59,
MX6SL_PAD_EPDC_PWRCTRL3 = 60,
MX6SL_PAD_EPDC_PWRINT = 61,
MX6SL_PAD_EPDC_PWRSTAT = 62,
MX6SL_PAD_EPDC_PWRWAKEUP = 63,
MX6SL_PAD_EPDC_SDCE0 = 64,
MX6SL_PAD_EPDC_SDCE1 = 65,
MX6SL_PAD_EPDC_SDCE2 = 66,
MX6SL_PAD_EPDC_SDCE3 = 67,
MX6SL_PAD_EPDC_SDCLK = 68,
MX6SL_PAD_EPDC_SDLE = 69,
MX6SL_PAD_EPDC_SDOE = 70,
MX6SL_PAD_EPDC_SDSHR = 71,
MX6SL_PAD_EPDC_VCOM0 = 72,
MX6SL_PAD_EPDC_VCOM1 = 73,
MX6SL_PAD_FEC_CRS_DV = 74,
MX6SL_PAD_FEC_MDC = 75,
MX6SL_PAD_FEC_MDIO = 76,
MX6SL_PAD_FEC_REF_CLK = 77,
MX6SL_PAD_FEC_RX_ER = 78,
MX6SL_PAD_FEC_RXD0 = 79,
MX6SL_PAD_FEC_RXD1 = 80,
MX6SL_PAD_FEC_TX_CLK = 81,
MX6SL_PAD_FEC_TX_EN = 82,
MX6SL_PAD_FEC_TXD0 = 83,
MX6SL_PAD_FEC_TXD1 = 84,
MX6SL_PAD_HSIC_DAT = 85,
MX6SL_PAD_HSIC_STROBE = 86,
MX6SL_PAD_I2C1_SCL = 87,
MX6SL_PAD_I2C1_SDA = 88,
MX6SL_PAD_I2C2_SCL = 89,
MX6SL_PAD_I2C2_SDA = 90,
MX6SL_PAD_KEY_COL0 = 91,
MX6SL_PAD_KEY_COL1 = 92,
MX6SL_PAD_KEY_COL2 = 93,
MX6SL_PAD_KEY_COL3 = 94,
MX6SL_PAD_KEY_COL4 = 95,
MX6SL_PAD_KEY_COL5 = 96,
MX6SL_PAD_KEY_COL6 = 97,
MX6SL_PAD_KEY_COL7 = 98,
MX6SL_PAD_KEY_ROW0 = 99,
MX6SL_PAD_KEY_ROW1 = 100,
MX6SL_PAD_KEY_ROW2 = 101,
MX6SL_PAD_KEY_ROW3 = 102,
MX6SL_PAD_KEY_ROW4 = 103,
MX6SL_PAD_KEY_ROW5 = 104,
MX6SL_PAD_KEY_ROW6 = 105,
MX6SL_PAD_KEY_ROW7 = 106,
MX6SL_PAD_LCD_CLK = 107,
MX6SL_PAD_LCD_DAT0 = 108,
MX6SL_PAD_LCD_DAT1 = 109,
MX6SL_PAD_LCD_DAT10 = 110,
MX6SL_PAD_LCD_DAT11 = 111,
MX6SL_PAD_LCD_DAT12 = 112,
MX6SL_PAD_LCD_DAT13 = 113,
MX6SL_PAD_LCD_DAT14 = 114,
MX6SL_PAD_LCD_DAT15 = 115,
MX6SL_PAD_LCD_DAT16 = 116,
MX6SL_PAD_LCD_DAT17 = 117,
MX6SL_PAD_LCD_DAT18 = 118,
MX6SL_PAD_LCD_DAT19 = 119,
MX6SL_PAD_LCD_DAT2 = 120,
MX6SL_PAD_LCD_DAT20 = 121,
MX6SL_PAD_LCD_DAT21 = 122,
MX6SL_PAD_LCD_DAT22 = 123,
MX6SL_PAD_LCD_DAT23 = 124,
MX6SL_PAD_LCD_DAT3 = 125,
MX6SL_PAD_LCD_DAT4 = 126,
MX6SL_PAD_LCD_DAT5 = 127,
MX6SL_PAD_LCD_DAT6 = 128,
MX6SL_PAD_LCD_DAT7 = 129,
MX6SL_PAD_LCD_DAT8 = 130,
MX6SL_PAD_LCD_DAT9 = 131,
MX6SL_PAD_LCD_ENABLE = 132,
MX6SL_PAD_LCD_HSYNC = 133,
MX6SL_PAD_LCD_RESET = 134,
MX6SL_PAD_LCD_VSYNC = 135,
MX6SL_PAD_PWM1 = 136,
MX6SL_PAD_REF_CLK_24M = 137,
MX6SL_PAD_REF_CLK_32K = 138,
MX6SL_PAD_SD1_CLK = 139,
MX6SL_PAD_SD1_CMD = 140,
MX6SL_PAD_SD1_DAT0 = 141,
MX6SL_PAD_SD1_DAT1 = 142,
MX6SL_PAD_SD1_DAT2 = 143,
MX6SL_PAD_SD1_DAT3 = 144,
MX6SL_PAD_SD1_DAT4 = 145,
MX6SL_PAD_SD1_DAT5 = 146,
MX6SL_PAD_SD1_DAT6 = 147,
MX6SL_PAD_SD1_DAT7 = 148,
MX6SL_PAD_SD2_CLK = 149,
MX6SL_PAD_SD2_CMD = 150,
MX6SL_PAD_SD2_DAT0 = 151,
MX6SL_PAD_SD2_DAT1 = 152,
MX6SL_PAD_SD2_DAT2 = 153,
MX6SL_PAD_SD2_DAT3 = 154,
MX6SL_PAD_SD2_DAT4 = 155,
MX6SL_PAD_SD2_DAT5 = 156,
MX6SL_PAD_SD2_DAT6 = 157,
MX6SL_PAD_SD2_DAT7 = 158,
MX6SL_PAD_SD2_RST = 159,
MX6SL_PAD_SD3_CLK = 160,
MX6SL_PAD_SD3_CMD = 161,
MX6SL_PAD_SD3_DAT0 = 162,
MX6SL_PAD_SD3_DAT1 = 163,
MX6SL_PAD_SD3_DAT2 = 164,
MX6SL_PAD_SD3_DAT3 = 165,
MX6SL_PAD_UART1_RXD = 166,
MX6SL_PAD_UART1_TXD = 167,
MX6SL_PAD_WDOG_B = 168,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD),
IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0),
IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1),
IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT),
IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6),
IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX6SL_PAD_PWM1),
IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M),
IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7),
IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
};
static const struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.pins = imx6sl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
.gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
};
static const struct of_device_id imx6sl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sl-iomuxc", },
{ /* sentinel */ }
};
static int imx6sl_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info);
}
static struct platform_driver imx6sl_pinctrl_driver = {
.driver = {
.name = "imx6sl-pinctrl",
.of_match_table = imx6sl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sl_pinctrl_probe,
};
static int __init imx6sl_pinctrl_init(void)
{
return platform_driver_register(&imx6sl_pinctrl_driver);
}
arch_initcall(imx6sl_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6sl.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 NXP
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imx8mp_pads {
MX8MP_IOMUXC_RESERVE0 = 0,
MX8MP_IOMUXC_RESERVE1 = 1,
MX8MP_IOMUXC_RESERVE2 = 2,
MX8MP_IOMUXC_RESERVE3 = 3,
MX8MP_IOMUXC_RESERVE4 = 4,
MX8MP_IOMUXC_GPIO1_IO00 = 5,
MX8MP_IOMUXC_GPIO1_IO01 = 6,
MX8MP_IOMUXC_GPIO1_IO02 = 7,
MX8MP_IOMUXC_GPIO1_IO03 = 8,
MX8MP_IOMUXC_GPIO1_IO04 = 9,
MX8MP_IOMUXC_GPIO1_IO05 = 10,
MX8MP_IOMUXC_GPIO1_IO06 = 11,
MX8MP_IOMUXC_GPIO1_IO07 = 12,
MX8MP_IOMUXC_GPIO1_IO08 = 13,
MX8MP_IOMUXC_GPIO1_IO09 = 14,
MX8MP_IOMUXC_GPIO1_IO10 = 15,
MX8MP_IOMUXC_GPIO1_IO11 = 16,
MX8MP_IOMUXC_GPIO1_IO12 = 17,
MX8MP_IOMUXC_GPIO1_IO13 = 18,
MX8MP_IOMUXC_GPIO1_IO14 = 19,
MX8MP_IOMUXC_GPIO1_IO15 = 20,
MX8MP_IOMUXC_ENET_MDC = 21,
MX8MP_IOMUXC_ENET_MDIO = 22,
MX8MP_IOMUXC_ENET_TD3 = 23,
MX8MP_IOMUXC_ENET_TD2 = 24,
MX8MP_IOMUXC_ENET_TD1 = 25,
MX8MP_IOMUXC_ENET_TD0 = 26,
MX8MP_IOMUXC_ENET_TX_CTL = 27,
MX8MP_IOMUXC_ENET_TXC = 28,
MX8MP_IOMUXC_ENET_RX_CTL = 29,
MX8MP_IOMUXC_ENET_RXC = 30,
MX8MP_IOMUXC_ENET_RD0 = 31,
MX8MP_IOMUXC_ENET_RD1 = 32,
MX8MP_IOMUXC_ENET_RD2 = 33,
MX8MP_IOMUXC_ENET_RD3 = 34,
MX8MP_IOMUXC_SD1_CLK = 35,
MX8MP_IOMUXC_SD1_CMD = 36,
MX8MP_IOMUXC_SD1_DATA0 = 37,
MX8MP_IOMUXC_SD1_DATA1 = 38,
MX8MP_IOMUXC_SD1_DATA2 = 39,
MX8MP_IOMUXC_SD1_DATA3 = 40,
MX8MP_IOMUXC_SD1_DATA4 = 41,
MX8MP_IOMUXC_SD1_DATA5 = 42,
MX8MP_IOMUXC_SD1_DATA6 = 43,
MX8MP_IOMUXC_SD1_DATA7 = 44,
MX8MP_IOMUXC_SD1_RESET_B = 45,
MX8MP_IOMUXC_SD1_STROBE = 46,
MX8MP_IOMUXC_SD2_CD_B = 47,
MX8MP_IOMUXC_SD2_CLK = 48,
MX8MP_IOMUXC_SD2_CMD = 49,
MX8MP_IOMUXC_SD2_DATA0 = 50,
MX8MP_IOMUXC_SD2_DATA1 = 51,
MX8MP_IOMUXC_SD2_DATA2 = 52,
MX8MP_IOMUXC_SD2_DATA3 = 53,
MX8MP_IOMUXC_SD2_RESET_B = 54,
MX8MP_IOMUXC_SD2_WP = 55,
MX8MP_IOMUXC_NAND_ALE = 56,
MX8MP_IOMUXC_NAND_CE0_B = 57,
MX8MP_IOMUXC_NAND_CE1_B = 58,
MX8MP_IOMUXC_NAND_CE2_B = 59,
MX8MP_IOMUXC_NAND_CE3_B = 60,
MX8MP_IOMUXC_NAND_CLE = 61,
MX8MP_IOMUXC_NAND_DATA00 = 62,
MX8MP_IOMUXC_NAND_DATA01 = 63,
MX8MP_IOMUXC_NAND_DATA02 = 64,
MX8MP_IOMUXC_NAND_DATA03 = 65,
MX8MP_IOMUXC_NAND_DATA04 = 66,
MX8MP_IOMUXC_NAND_DATA05 = 67,
MX8MP_IOMUXC_NAND_DATA06 = 68,
MX8MP_IOMUXC_NAND_DATA07 = 69,
MX8MP_IOMUXC_NAND_DQS = 70,
MX8MP_IOMUXC_NAND_RE_B = 71,
MX8MP_IOMUXC_NAND_READY_B = 72,
MX8MP_IOMUXC_NAND_WE_B = 73,
MX8MP_IOMUXC_NAND_WP_B = 74,
MX8MP_IOMUXC_SAI5_RXFS = 75,
MX8MP_IOMUXC_SAI5_RXC = 76,
MX8MP_IOMUXC_SAI5_RXD0 = 77,
MX8MP_IOMUXC_SAI5_RXD1 = 78,
MX8MP_IOMUXC_SAI5_RXD2 = 79,
MX8MP_IOMUXC_SAI5_RXD3 = 80,
MX8MP_IOMUXC_SAI5_MCLK = 81,
MX8MP_IOMUXC_SAI1_RXFS = 82,
MX8MP_IOMUXC_SAI1_RXC = 83,
MX8MP_IOMUXC_SAI1_RXD0 = 84,
MX8MP_IOMUXC_SAI1_RXD1 = 85,
MX8MP_IOMUXC_SAI1_RXD2 = 86,
MX8MP_IOMUXC_SAI1_RXD3 = 87,
MX8MP_IOMUXC_SAI1_RXD4 = 88,
MX8MP_IOMUXC_SAI1_RXD5 = 89,
MX8MP_IOMUXC_SAI1_RXD6 = 90,
MX8MP_IOMUXC_SAI1_RXD7 = 91,
MX8MP_IOMUXC_SAI1_TXFS = 92,
MX8MP_IOMUXC_SAI1_TXC = 93,
MX8MP_IOMUXC_SAI1_TXD0 = 94,
MX8MP_IOMUXC_SAI1_TXD1 = 95,
MX8MP_IOMUXC_SAI1_TXD2 = 96,
MX8MP_IOMUXC_SAI1_TXD3 = 97,
MX8MP_IOMUXC_SAI1_TXD4 = 98,
MX8MP_IOMUXC_SAI1_TXD5 = 99,
MX8MP_IOMUXC_SAI1_TXD6 = 100,
MX8MP_IOMUXC_SAI1_TXD7 = 101,
MX8MP_IOMUXC_SAI1_MCLK = 102,
MX8MP_IOMUXC_SAI2_RXFS = 103,
MX8MP_IOMUXC_SAI2_RXC = 104,
MX8MP_IOMUXC_SAI2_RXD0 = 105,
MX8MP_IOMUXC_SAI2_TXFS = 106,
MX8MP_IOMUXC_SAI2_TXC = 107,
MX8MP_IOMUXC_SAI2_TXD0 = 108,
MX8MP_IOMUXC_SAI2_MCLK = 109,
MX8MP_IOMUXC_SAI3_RXFS = 110,
MX8MP_IOMUXC_SAI3_RXC = 111,
MX8MP_IOMUXC_SAI3_RXD = 112,
MX8MP_IOMUXC_SAI3_TXFS = 113,
MX8MP_IOMUXC_SAI3_TXC = 114,
MX8MP_IOMUXC_SAI3_TXD = 115,
MX8MP_IOMUXC_SAI3_MCLK = 116,
MX8MP_IOMUXC_SPDIF_TX = 117,
MX8MP_IOMUXC_SPDIF_RX = 118,
MX8MP_IOMUXC_SPDIF_EXT_CLK = 119,
MX8MP_IOMUXC_ECSPI1_SCLK = 120,
MX8MP_IOMUXC_ECSPI1_MOSI = 121,
MX8MP_IOMUXC_ECSPI1_MISO = 122,
MX8MP_IOMUXC_ECSPI1_SS0 = 123,
MX8MP_IOMUXC_ECSPI2_SCLK = 124,
MX8MP_IOMUXC_ECSPI2_MOSI = 125,
MX8MP_IOMUXC_ECSPI2_MISO = 126,
MX8MP_IOMUXC_ECSPI2_SS0 = 127,
MX8MP_IOMUXC_I2C1_SCL = 128,
MX8MP_IOMUXC_I2C1_SDA = 129,
MX8MP_IOMUXC_I2C2_SCL = 130,
MX8MP_IOMUXC_I2C2_SDA = 131,
MX8MP_IOMUXC_I2C3_SCL = 132,
MX8MP_IOMUXC_I2C3_SDA = 133,
MX8MP_IOMUXC_I2C4_SCL = 134,
MX8MP_IOMUXC_I2C4_SDA = 135,
MX8MP_IOMUXC_UART1_RXD = 136,
MX8MP_IOMUXC_UART1_TXD = 137,
MX8MP_IOMUXC_UART2_RXD = 138,
MX8MP_IOMUXC_UART2_TXD = 139,
MX8MP_IOMUXC_UART3_RXD = 140,
MX8MP_IOMUXC_UART3_TXD = 141,
MX8MP_IOMUXC_UART4_RXD = 142,
MX8MP_IOMUXC_UART4_TXD = 143,
MX8MP_IOMUXC_HDMI_DDC_SCL = 144,
MX8MP_IOMUXC_HDMI_DDC_SDA = 145,
MX8MP_IOMUXC_HDMI_CEC = 146,
MX8MP_IOMUXC_HDMI_HPD = 147,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC),
IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD),
};
static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = {
.pins = imx8mp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mp_pinctrl_pads),
.gpr_compatible = "fsl,imx8mp-iomuxc-gpr",
};
static const struct of_device_id imx8mp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8mp_pinctrl_of_match);
static int imx8mp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info);
}
static struct platform_driver imx8mp_pinctrl_driver = {
.driver = {
.name = "imx8mp-pinctrl",
.of_match_table = imx8mp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mp_pinctrl_probe,
};
static int __init imx8mp_pinctrl_init(void)
{
return platform_driver_register(&imx8mp_pinctrl_driver);
}
arch_initcall(imx8mp_pinctrl_init);
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MP pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8mp.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <[email protected]>
*/
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
};
static const struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx8qxp_pinctrl_of_match);
static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
}
static struct platform_driver imx8qxp_pinctrl_driver = {
.driver = {
.name = "imx8qxp-pinctrl",
.of_match_table = imx8qxp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8qxp_pinctrl_probe,
};
static int __init imx8qxp_pinctrl_init(void)
{
return platform_driver_register(&imx8qxp_pinctrl_driver);
}
arch_initcall(imx8qxp_pinctrl_init);
MODULE_AUTHOR("Aisheng Dong <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "pinctrl-mxs.h"
#define SUFFIX_LEN 4
struct mxs_pinctrl_data {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct mxs_pinctrl_soc_data *soc;
};
static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->ngroups;
}
static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->groups[group].name;
}
static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
const unsigned **pins, unsigned *num_pins)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*pins = d->soc->groups[group].pins;
*num_pins = d->soc->groups[group].npins;
return 0;
}
static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct pinctrl_map *new_map;
char *group = NULL;
unsigned new_num = 1;
unsigned long config = 0;
unsigned long *pconfig;
int length = strlen(np->name) + SUFFIX_LEN;
bool purecfg = false;
u32 val, reg;
int ret, i = 0;
/* Check for pin config node which has no 'reg' property */
if (of_property_read_u32(np, "reg", ®))
purecfg = true;
ret = of_property_read_u32(np, "fsl,drive-strength", &val);
if (!ret)
config = val | MA_PRESENT;
ret = of_property_read_u32(np, "fsl,voltage", &val);
if (!ret)
config |= val << VOL_SHIFT | VOL_PRESENT;
ret = of_property_read_u32(np, "fsl,pull-up", &val);
if (!ret)
config |= val << PULL_SHIFT | PULL_PRESENT;
/* Check for group node which has both mux and config settings */
if (!purecfg && config)
new_num = 2;
new_map = kcalloc(new_num, sizeof(*new_map), GFP_KERNEL);
if (!new_map)
return -ENOMEM;
if (!purecfg) {
new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[i].data.mux.function = np->name;
/* Compose group name */
group = kzalloc(length, GFP_KERNEL);
if (!group) {
ret = -ENOMEM;
goto free;
}
snprintf(group, length, "%s.%d", np->name, reg);
new_map[i].data.mux.group = group;
i++;
}
if (config) {
pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
if (!pconfig) {
ret = -ENOMEM;
goto free_group;
}
new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
new_map[i].data.configs.group_or_pin = purecfg ? np->name :
group;
new_map[i].data.configs.configs = pconfig;
new_map[i].data.configs.num_configs = 1;
}
*map = new_map;
*num_maps = new_num;
return 0;
free_group:
if (!purecfg)
kfree(group);
free:
kfree(new_map);
return ret;
}
static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
u32 i;
for (i = 0; i < num_maps; i++) {
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
kfree(map[i].data.mux.group);
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
kfree(map[i].data.configs.configs);
}
kfree(map);
}
static const struct pinctrl_ops mxs_pinctrl_ops = {
.get_groups_count = mxs_get_groups_count,
.get_group_name = mxs_get_group_name,
.get_group_pins = mxs_get_group_pins,
.pin_dbg_show = mxs_pin_dbg_show,
.dt_node_to_map = mxs_dt_node_to_map,
.dt_free_map = mxs_dt_free_map,
};
static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->nfunctions;
}
static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
return d->soc->functions[function].name;
}
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned group,
const char * const **groups,
unsigned * const num_groups)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*groups = d->soc->functions[group].groups;
*num_groups = d->soc->functions[group].ngroups;
return 0;
}
static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
{
u32 tmp;
tmp = readl(reg);
tmp &= ~(mask << shift);
tmp |= value << shift;
writel(tmp, reg);
}
static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
void __iomem *reg;
u8 bank, shift;
u16 pin;
u32 i;
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
reg = d->base + d->soc->regs->muxsel;
reg += bank * 0x20 + pin / 16 * 0x10;
shift = pin % 16 * 2;
mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
}
return 0;
}
static const struct pinmux_ops mxs_pinmux_ops = {
.get_functions_count = mxs_pinctrl_get_funcs_count,
.get_function_name = mxs_pinctrl_get_func_name,
.get_function_groups = mxs_pinctrl_get_func_groups,
.set_mux = mxs_pinctrl_set_mux,
};
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
return -ENOTSUPP;
}
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
return -ENOTSUPP;
}
static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
*config = d->soc->groups[group].config;
return 0;
}
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
void __iomem *reg;
u8 ma, vol, pull, bank, shift;
u16 pin;
u32 i;
int n;
unsigned long config;
for (n = 0; n < num_configs; n++) {
config = configs[n];
ma = PIN_CONFIG_TO_MA(config);
vol = PIN_CONFIG_TO_VOL(config);
pull = PIN_CONFIG_TO_PULL(config);
for (i = 0; i < g->npins; i++) {
bank = PINID_TO_BANK(g->pins[i]);
pin = PINID_TO_PIN(g->pins[i]);
/* drive */
reg = d->base + d->soc->regs->drive;
reg += bank * 0x40 + pin / 8 * 0x10;
/* mA */
if (config & MA_PRESENT) {
shift = pin % 8 * 4;
mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
}
/* vol */
if (config & VOL_PRESENT) {
shift = pin % 8 * 4 + 2;
if (vol)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
/* pull */
if (config & PULL_PRESENT) {
reg = d->base + d->soc->regs->pull;
reg += bank * 0x10;
shift = pin;
if (pull)
writel(1 << shift, reg + SET);
else
writel(1 << shift, reg + CLR);
}
}
/* cache the config value for mxs_pinconf_group_get() */
g->config = config;
} /* for each config */
return 0;
}
static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin)
{
/* Not support */
}
static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
unsigned long config;
if (!mxs_pinconf_group_get(pctldev, group, &config))
seq_printf(s, "0x%lx", config);
}
static const struct pinconf_ops mxs_pinconf_ops = {
.pin_config_get = mxs_pinconf_get,
.pin_config_set = mxs_pinconf_set,
.pin_config_group_get = mxs_pinconf_group_get,
.pin_config_group_set = mxs_pinconf_group_set,
.pin_config_dbg_show = mxs_pinconf_dbg_show,
.pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
};
static struct pinctrl_desc mxs_pinctrl_desc = {
.pctlops = &mxs_pinctrl_ops,
.pmxops = &mxs_pinmux_ops,
.confops = &mxs_pinconf_ops,
.owner = THIS_MODULE,
};
static int mxs_pinctrl_parse_group(struct platform_device *pdev,
struct device_node *np, int idx,
const char **out_name)
{
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
struct mxs_group *g = &d->soc->groups[idx];
struct property *prop;
const char *propname = "fsl,pinmux-ids";
char *group;
int length = strlen(np->name) + SUFFIX_LEN;
u32 val, i;
group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
if (!group)
return -ENOMEM;
if (of_property_read_u32(np, "reg", &val))
snprintf(group, length, "%s", np->name);
else
snprintf(group, length, "%s.%d", np->name, val);
g->name = group;
prop = of_find_property(np, propname, &length);
if (!prop)
return -EINVAL;
g->npins = length / sizeof(u32);
g->pins = devm_kcalloc(&pdev->dev, g->npins, sizeof(*g->pins),
GFP_KERNEL);
if (!g->pins)
return -ENOMEM;
g->muxsel = devm_kcalloc(&pdev->dev, g->npins, sizeof(*g->muxsel),
GFP_KERNEL);
if (!g->muxsel)
return -ENOMEM;
of_property_read_u32_array(np, propname, g->pins, g->npins);
for (i = 0; i < g->npins; i++) {
g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
g->pins[i] = MUXID_TO_PINID(g->pins[i]);
}
if (out_name)
*out_name = g->name;
return 0;
}
static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
struct mxs_pinctrl_data *d)
{
struct mxs_pinctrl_soc_data *soc = d->soc;
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct mxs_function *f;
const char *gpio_compat = "fsl,mxs-gpio";
const char *fn, *fnull = "";
int i = 0, idxf = 0, idxg = 0;
int ret;
u32 val;
child = of_get_next_child(np, NULL);
if (!child) {
dev_err(&pdev->dev, "no group is defined\n");
return -ENOENT;
}
/* Count total functions and groups */
fn = fnull;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
soc->ngroups++;
/* Skip pure pinconf node */
if (of_property_read_u32(child, "reg", &val))
continue;
if (strcmp(fn, child->name)) {
fn = child->name;
soc->nfunctions++;
}
}
soc->functions = devm_kcalloc(&pdev->dev,
soc->nfunctions,
sizeof(*soc->functions),
GFP_KERNEL);
if (!soc->functions)
return -ENOMEM;
soc->groups = devm_kcalloc(&pdev->dev,
soc->ngroups, sizeof(*soc->groups),
GFP_KERNEL);
if (!soc->groups)
return -ENOMEM;
/* Count groups for each function */
fn = fnull;
f = &soc->functions[idxf];
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
if (of_property_read_u32(child, "reg", &val))
continue;
if (strcmp(fn, child->name)) {
struct device_node *child2;
/*
* This reference is dropped by
* of_get_next_child(np, * child)
*/
of_node_get(child);
/*
* The logic parsing the functions from dt currently
* doesn't handle if functions with the same name are
* not grouped together. Only the first contiguous
* cluster is usable for each function name. This is a
* bug that is not trivial to fix, but at least warn
* about it.
*/
for (child2 = of_get_next_child(np, child);
child2 != NULL;
child2 = of_get_next_child(np, child2)) {
if (!strcmp(child2->name, fn))
dev_warn(&pdev->dev,
"function nodes must be grouped by name (failed for: %s)",
fn);
}
f = &soc->functions[idxf++];
f->name = fn = child->name;
}
f->ngroups++;
}
/* Get groups for each function */
idxf = 0;
fn = fnull;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
if (of_property_read_u32(child, "reg", &val)) {
ret = mxs_pinctrl_parse_group(pdev, child,
idxg++, NULL);
if (ret) {
of_node_put(child);
return ret;
}
continue;
}
if (strcmp(fn, child->name)) {
f = &soc->functions[idxf++];
f->groups = devm_kcalloc(&pdev->dev,
f->ngroups,
sizeof(*f->groups),
GFP_KERNEL);
if (!f->groups) {
of_node_put(child);
return -ENOMEM;
}
fn = child->name;
i = 0;
}
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
&f->groups[i++]);
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;
}
int mxs_pinctrl_probe(struct platform_device *pdev,
struct mxs_pinctrl_soc_data *soc)
{
struct device_node *np = pdev->dev.of_node;
struct mxs_pinctrl_data *d;
int ret;
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
if (!d)
return -ENOMEM;
d->dev = &pdev->dev;
d->soc = soc;
d->base = of_iomap(np, 0);
if (!d->base)
return -EADDRNOTAVAIL;
mxs_pinctrl_desc.pins = d->soc->pins;
mxs_pinctrl_desc.npins = d->soc->npins;
mxs_pinctrl_desc.name = dev_name(&pdev->dev);
platform_set_drvdata(pdev, d);
ret = mxs_pinctrl_probe_dt(pdev, d);
if (ret) {
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
goto err;
}
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
if (IS_ERR(d->pctl)) {
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
ret = PTR_ERR(d->pctl);
goto err;
}
return 0;
err:
iounmap(d->base);
return ret;
}
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-mxs.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// imx53 pinctrl driver based on imx pinmux core
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx53_pads {
MX53_PAD_RESERVE0 = 0,
MX53_PAD_RESERVE1 = 1,
MX53_PAD_RESERVE2 = 2,
MX53_PAD_RESERVE3 = 3,
MX53_PAD_RESERVE4 = 4,
MX53_PAD_RESERVE5 = 5,
MX53_PAD_RESERVE6 = 6,
MX53_PAD_RESERVE7 = 7,
MX53_PAD_GPIO_19 = 8,
MX53_PAD_KEY_COL0 = 9,
MX53_PAD_KEY_ROW0 = 10,
MX53_PAD_KEY_COL1 = 11,
MX53_PAD_KEY_ROW1 = 12,
MX53_PAD_KEY_COL2 = 13,
MX53_PAD_KEY_ROW2 = 14,
MX53_PAD_KEY_COL3 = 15,
MX53_PAD_KEY_ROW3 = 16,
MX53_PAD_KEY_COL4 = 17,
MX53_PAD_KEY_ROW4 = 18,
MX53_PAD_DI0_DISP_CLK = 19,
MX53_PAD_DI0_PIN15 = 20,
MX53_PAD_DI0_PIN2 = 21,
MX53_PAD_DI0_PIN3 = 22,
MX53_PAD_DI0_PIN4 = 23,
MX53_PAD_DISP0_DAT0 = 24,
MX53_PAD_DISP0_DAT1 = 25,
MX53_PAD_DISP0_DAT2 = 26,
MX53_PAD_DISP0_DAT3 = 27,
MX53_PAD_DISP0_DAT4 = 28,
MX53_PAD_DISP0_DAT5 = 29,
MX53_PAD_DISP0_DAT6 = 30,
MX53_PAD_DISP0_DAT7 = 31,
MX53_PAD_DISP0_DAT8 = 32,
MX53_PAD_DISP0_DAT9 = 33,
MX53_PAD_DISP0_DAT10 = 34,
MX53_PAD_DISP0_DAT11 = 35,
MX53_PAD_DISP0_DAT12 = 36,
MX53_PAD_DISP0_DAT13 = 37,
MX53_PAD_DISP0_DAT14 = 38,
MX53_PAD_DISP0_DAT15 = 39,
MX53_PAD_DISP0_DAT16 = 40,
MX53_PAD_DISP0_DAT17 = 41,
MX53_PAD_DISP0_DAT18 = 42,
MX53_PAD_DISP0_DAT19 = 43,
MX53_PAD_DISP0_DAT20 = 44,
MX53_PAD_DISP0_DAT21 = 45,
MX53_PAD_DISP0_DAT22 = 46,
MX53_PAD_DISP0_DAT23 = 47,
MX53_PAD_CSI0_PIXCLK = 48,
MX53_PAD_CSI0_MCLK = 49,
MX53_PAD_CSI0_DATA_EN = 50,
MX53_PAD_CSI0_VSYNC = 51,
MX53_PAD_CSI0_DAT4 = 52,
MX53_PAD_CSI0_DAT5 = 53,
MX53_PAD_CSI0_DAT6 = 54,
MX53_PAD_CSI0_DAT7 = 55,
MX53_PAD_CSI0_DAT8 = 56,
MX53_PAD_CSI0_DAT9 = 57,
MX53_PAD_CSI0_DAT10 = 58,
MX53_PAD_CSI0_DAT11 = 59,
MX53_PAD_CSI0_DAT12 = 60,
MX53_PAD_CSI0_DAT13 = 61,
MX53_PAD_CSI0_DAT14 = 62,
MX53_PAD_CSI0_DAT15 = 63,
MX53_PAD_CSI0_DAT16 = 64,
MX53_PAD_CSI0_DAT17 = 65,
MX53_PAD_CSI0_DAT18 = 66,
MX53_PAD_CSI0_DAT19 = 67,
MX53_PAD_EIM_A25 = 68,
MX53_PAD_EIM_EB2 = 69,
MX53_PAD_EIM_D16 = 70,
MX53_PAD_EIM_D17 = 71,
MX53_PAD_EIM_D18 = 72,
MX53_PAD_EIM_D19 = 73,
MX53_PAD_EIM_D20 = 74,
MX53_PAD_EIM_D21 = 75,
MX53_PAD_EIM_D22 = 76,
MX53_PAD_EIM_D23 = 77,
MX53_PAD_EIM_EB3 = 78,
MX53_PAD_EIM_D24 = 79,
MX53_PAD_EIM_D25 = 80,
MX53_PAD_EIM_D26 = 81,
MX53_PAD_EIM_D27 = 82,
MX53_PAD_EIM_D28 = 83,
MX53_PAD_EIM_D29 = 84,
MX53_PAD_EIM_D30 = 85,
MX53_PAD_EIM_D31 = 86,
MX53_PAD_EIM_A24 = 87,
MX53_PAD_EIM_A23 = 88,
MX53_PAD_EIM_A22 = 89,
MX53_PAD_EIM_A21 = 90,
MX53_PAD_EIM_A20 = 91,
MX53_PAD_EIM_A19 = 92,
MX53_PAD_EIM_A18 = 93,
MX53_PAD_EIM_A17 = 94,
MX53_PAD_EIM_A16 = 95,
MX53_PAD_EIM_CS0 = 96,
MX53_PAD_EIM_CS1 = 97,
MX53_PAD_EIM_OE = 98,
MX53_PAD_EIM_RW = 99,
MX53_PAD_EIM_LBA = 100,
MX53_PAD_EIM_EB0 = 101,
MX53_PAD_EIM_EB1 = 102,
MX53_PAD_EIM_DA0 = 103,
MX53_PAD_EIM_DA1 = 104,
MX53_PAD_EIM_DA2 = 105,
MX53_PAD_EIM_DA3 = 106,
MX53_PAD_EIM_DA4 = 107,
MX53_PAD_EIM_DA5 = 108,
MX53_PAD_EIM_DA6 = 109,
MX53_PAD_EIM_DA7 = 110,
MX53_PAD_EIM_DA8 = 111,
MX53_PAD_EIM_DA9 = 112,
MX53_PAD_EIM_DA10 = 113,
MX53_PAD_EIM_DA11 = 114,
MX53_PAD_EIM_DA12 = 115,
MX53_PAD_EIM_DA13 = 116,
MX53_PAD_EIM_DA14 = 117,
MX53_PAD_EIM_DA15 = 118,
MX53_PAD_NANDF_WE_B = 119,
MX53_PAD_NANDF_RE_B = 120,
MX53_PAD_EIM_WAIT = 121,
MX53_PAD_RESERVE8 = 122,
MX53_PAD_LVDS1_TX3_P = 123,
MX53_PAD_LVDS1_TX2_P = 124,
MX53_PAD_LVDS1_CLK_P = 125,
MX53_PAD_LVDS1_TX1_P = 126,
MX53_PAD_LVDS1_TX0_P = 127,
MX53_PAD_LVDS0_TX3_P = 128,
MX53_PAD_LVDS0_CLK_P = 129,
MX53_PAD_LVDS0_TX2_P = 130,
MX53_PAD_LVDS0_TX1_P = 131,
MX53_PAD_LVDS0_TX0_P = 132,
MX53_PAD_GPIO_10 = 133,
MX53_PAD_GPIO_11 = 134,
MX53_PAD_GPIO_12 = 135,
MX53_PAD_GPIO_13 = 136,
MX53_PAD_GPIO_14 = 137,
MX53_PAD_NANDF_CLE = 138,
MX53_PAD_NANDF_ALE = 139,
MX53_PAD_NANDF_WP_B = 140,
MX53_PAD_NANDF_RB0 = 141,
MX53_PAD_NANDF_CS0 = 142,
MX53_PAD_NANDF_CS1 = 143,
MX53_PAD_NANDF_CS2 = 144,
MX53_PAD_NANDF_CS3 = 145,
MX53_PAD_FEC_MDIO = 146,
MX53_PAD_FEC_REF_CLK = 147,
MX53_PAD_FEC_RX_ER = 148,
MX53_PAD_FEC_CRS_DV = 149,
MX53_PAD_FEC_RXD1 = 150,
MX53_PAD_FEC_RXD0 = 151,
MX53_PAD_FEC_TX_EN = 152,
MX53_PAD_FEC_TXD1 = 153,
MX53_PAD_FEC_TXD0 = 154,
MX53_PAD_FEC_MDC = 155,
MX53_PAD_PATA_DIOW = 156,
MX53_PAD_PATA_DMACK = 157,
MX53_PAD_PATA_DMARQ = 158,
MX53_PAD_PATA_BUFFER_EN = 159,
MX53_PAD_PATA_INTRQ = 160,
MX53_PAD_PATA_DIOR = 161,
MX53_PAD_PATA_RESET_B = 162,
MX53_PAD_PATA_IORDY = 163,
MX53_PAD_PATA_DA_0 = 164,
MX53_PAD_PATA_DA_1 = 165,
MX53_PAD_PATA_DA_2 = 166,
MX53_PAD_PATA_CS_0 = 167,
MX53_PAD_PATA_CS_1 = 168,
MX53_PAD_PATA_DATA0 = 169,
MX53_PAD_PATA_DATA1 = 170,
MX53_PAD_PATA_DATA2 = 171,
MX53_PAD_PATA_DATA3 = 172,
MX53_PAD_PATA_DATA4 = 173,
MX53_PAD_PATA_DATA5 = 174,
MX53_PAD_PATA_DATA6 = 175,
MX53_PAD_PATA_DATA7 = 176,
MX53_PAD_PATA_DATA8 = 177,
MX53_PAD_PATA_DATA9 = 178,
MX53_PAD_PATA_DATA10 = 179,
MX53_PAD_PATA_DATA11 = 180,
MX53_PAD_PATA_DATA12 = 181,
MX53_PAD_PATA_DATA13 = 182,
MX53_PAD_PATA_DATA14 = 183,
MX53_PAD_PATA_DATA15 = 184,
MX53_PAD_SD1_DATA0 = 185,
MX53_PAD_SD1_DATA1 = 186,
MX53_PAD_SD1_CMD = 187,
MX53_PAD_SD1_DATA2 = 188,
MX53_PAD_SD1_CLK = 189,
MX53_PAD_SD1_DATA3 = 190,
MX53_PAD_SD2_CLK = 191,
MX53_PAD_SD2_CMD = 192,
MX53_PAD_SD2_DATA3 = 193,
MX53_PAD_SD2_DATA2 = 194,
MX53_PAD_SD2_DATA1 = 195,
MX53_PAD_SD2_DATA0 = 196,
MX53_PAD_GPIO_0 = 197,
MX53_PAD_GPIO_1 = 198,
MX53_PAD_GPIO_9 = 199,
MX53_PAD_GPIO_3 = 200,
MX53_PAD_GPIO_6 = 201,
MX53_PAD_GPIO_2 = 202,
MX53_PAD_GPIO_4 = 203,
MX53_PAD_GPIO_5 = 204,
MX53_PAD_GPIO_7 = 205,
MX53_PAD_GPIO_8 = 206,
MX53_PAD_GPIO_16 = 207,
MX53_PAD_GPIO_17 = 208,
MX53_PAD_GPIO_18 = 209,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX53_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX53_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX53_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P),
IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_10),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_11),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_12),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_13),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_14),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER),
IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1),
IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1),
IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0),
IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ),
IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN),
IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR),
IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B),
IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2),
IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14),
IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
};
static const struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.pins = imx53_pinctrl_pads,
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
.gpr_compatible = "fsl,imx53-iomuxc-gpr",
};
static const struct of_device_id imx53_pinctrl_of_match[] = {
{ .compatible = "fsl,imx53-iomuxc", },
{ /* sentinel */ }
};
static int imx53_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx53_pinctrl_info);
}
static struct platform_driver imx53_pinctrl_driver = {
.driver = {
.name = "imx53-pinctrl",
.of_match_table = imx53_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx53_pinctrl_probe,
};
static int __init imx53_pinctrl_init(void)
{
return platform_driver_register(&imx53_pinctrl_driver);
}
arch_initcall(imx53_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx53.c
|
// SPDX-License-Identifier: GPL-2.0
//
// imx25 pinctrl driver.
//
// Copyright 2013 Eukréa Electromatique <[email protected]>
//
// This driver was mostly copied from the imx51 pinctrl driver which has:
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
//
// Author: Denis Carikli <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx25_pads {
MX25_PAD_RESERVE0 = 0,
MX25_PAD_RESERVE1 = 1,
MX25_PAD_A10 = 2,
MX25_PAD_A13 = 3,
MX25_PAD_A14 = 4,
MX25_PAD_A15 = 5,
MX25_PAD_A16 = 6,
MX25_PAD_A17 = 7,
MX25_PAD_A18 = 8,
MX25_PAD_A19 = 9,
MX25_PAD_A20 = 10,
MX25_PAD_A21 = 11,
MX25_PAD_A22 = 12,
MX25_PAD_A23 = 13,
MX25_PAD_A24 = 14,
MX25_PAD_A25 = 15,
MX25_PAD_EB0 = 16,
MX25_PAD_EB1 = 17,
MX25_PAD_OE = 18,
MX25_PAD_CS0 = 19,
MX25_PAD_CS1 = 20,
MX25_PAD_CS4 = 21,
MX25_PAD_CS5 = 22,
MX25_PAD_NF_CE0 = 23,
MX25_PAD_ECB = 24,
MX25_PAD_LBA = 25,
MX25_PAD_BCLK = 26,
MX25_PAD_RW = 27,
MX25_PAD_NFWE_B = 28,
MX25_PAD_NFRE_B = 29,
MX25_PAD_NFALE = 30,
MX25_PAD_NFCLE = 31,
MX25_PAD_NFWP_B = 32,
MX25_PAD_NFRB = 33,
MX25_PAD_D15 = 34,
MX25_PAD_D14 = 35,
MX25_PAD_D13 = 36,
MX25_PAD_D12 = 37,
MX25_PAD_D11 = 38,
MX25_PAD_D10 = 39,
MX25_PAD_D9 = 40,
MX25_PAD_D8 = 41,
MX25_PAD_D7 = 42,
MX25_PAD_D6 = 43,
MX25_PAD_D5 = 44,
MX25_PAD_D4 = 45,
MX25_PAD_D3 = 46,
MX25_PAD_D2 = 47,
MX25_PAD_D1 = 48,
MX25_PAD_D0 = 49,
MX25_PAD_LD0 = 50,
MX25_PAD_LD1 = 51,
MX25_PAD_LD2 = 52,
MX25_PAD_LD3 = 53,
MX25_PAD_LD4 = 54,
MX25_PAD_LD5 = 55,
MX25_PAD_LD6 = 56,
MX25_PAD_LD7 = 57,
MX25_PAD_LD8 = 58,
MX25_PAD_LD9 = 59,
MX25_PAD_LD10 = 60,
MX25_PAD_LD11 = 61,
MX25_PAD_LD12 = 62,
MX25_PAD_LD13 = 63,
MX25_PAD_LD14 = 64,
MX25_PAD_LD15 = 65,
MX25_PAD_HSYNC = 66,
MX25_PAD_VSYNC = 67,
MX25_PAD_LSCLK = 68,
MX25_PAD_OE_ACD = 69,
MX25_PAD_CONTRAST = 70,
MX25_PAD_PWM = 71,
MX25_PAD_CSI_D2 = 72,
MX25_PAD_CSI_D3 = 73,
MX25_PAD_CSI_D4 = 74,
MX25_PAD_CSI_D5 = 75,
MX25_PAD_CSI_D6 = 76,
MX25_PAD_CSI_D7 = 77,
MX25_PAD_CSI_D8 = 78,
MX25_PAD_CSI_D9 = 79,
MX25_PAD_CSI_MCLK = 80,
MX25_PAD_CSI_VSYNC = 81,
MX25_PAD_CSI_HSYNC = 82,
MX25_PAD_CSI_PIXCLK = 83,
MX25_PAD_I2C1_CLK = 84,
MX25_PAD_I2C1_DAT = 85,
MX25_PAD_CSPI1_MOSI = 86,
MX25_PAD_CSPI1_MISO = 87,
MX25_PAD_CSPI1_SS0 = 88,
MX25_PAD_CSPI1_SS1 = 89,
MX25_PAD_CSPI1_SCLK = 90,
MX25_PAD_CSPI1_RDY = 91,
MX25_PAD_UART1_RXD = 92,
MX25_PAD_UART1_TXD = 93,
MX25_PAD_UART1_RTS = 94,
MX25_PAD_UART1_CTS = 95,
MX25_PAD_UART2_RXD = 96,
MX25_PAD_UART2_TXD = 97,
MX25_PAD_UART2_RTS = 98,
MX25_PAD_UART2_CTS = 99,
MX25_PAD_SD1_CMD = 100,
MX25_PAD_SD1_CLK = 101,
MX25_PAD_SD1_DATA0 = 102,
MX25_PAD_SD1_DATA1 = 103,
MX25_PAD_SD1_DATA2 = 104,
MX25_PAD_SD1_DATA3 = 105,
MX25_PAD_KPP_ROW0 = 106,
MX25_PAD_KPP_ROW1 = 107,
MX25_PAD_KPP_ROW2 = 108,
MX25_PAD_KPP_ROW3 = 109,
MX25_PAD_KPP_COL0 = 110,
MX25_PAD_KPP_COL1 = 111,
MX25_PAD_KPP_COL2 = 112,
MX25_PAD_KPP_COL3 = 113,
MX25_PAD_FEC_MDC = 114,
MX25_PAD_FEC_MDIO = 115,
MX25_PAD_FEC_TDATA0 = 116,
MX25_PAD_FEC_TDATA1 = 117,
MX25_PAD_FEC_TX_EN = 118,
MX25_PAD_FEC_RDATA0 = 119,
MX25_PAD_FEC_RDATA1 = 120,
MX25_PAD_FEC_RX_DV = 121,
MX25_PAD_FEC_TX_CLK = 122,
MX25_PAD_RTCK = 123,
MX25_PAD_DE_B = 124,
MX25_PAD_GPIO_A = 125,
MX25_PAD_GPIO_B = 126,
MX25_PAD_GPIO_C = 127,
MX25_PAD_GPIO_D = 128,
MX25_PAD_GPIO_E = 129,
MX25_PAD_GPIO_F = 130,
MX25_PAD_EXT_ARMCLK = 131,
MX25_PAD_UPLL_BYPCLK = 132,
MX25_PAD_VSTBY_REQ = 133,
MX25_PAD_VSTBY_ACK = 134,
MX25_PAD_POWER_FAIL = 135,
MX25_PAD_CLKO = 136,
MX25_PAD_BOOT_MODE0 = 137,
MX25_PAD_BOOT_MODE1 = 138,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX25_PAD_A10),
IMX_PINCTRL_PIN(MX25_PAD_A13),
IMX_PINCTRL_PIN(MX25_PAD_A14),
IMX_PINCTRL_PIN(MX25_PAD_A15),
IMX_PINCTRL_PIN(MX25_PAD_A16),
IMX_PINCTRL_PIN(MX25_PAD_A17),
IMX_PINCTRL_PIN(MX25_PAD_A18),
IMX_PINCTRL_PIN(MX25_PAD_A19),
IMX_PINCTRL_PIN(MX25_PAD_A20),
IMX_PINCTRL_PIN(MX25_PAD_A21),
IMX_PINCTRL_PIN(MX25_PAD_A22),
IMX_PINCTRL_PIN(MX25_PAD_A23),
IMX_PINCTRL_PIN(MX25_PAD_A24),
IMX_PINCTRL_PIN(MX25_PAD_A25),
IMX_PINCTRL_PIN(MX25_PAD_EB0),
IMX_PINCTRL_PIN(MX25_PAD_EB1),
IMX_PINCTRL_PIN(MX25_PAD_OE),
IMX_PINCTRL_PIN(MX25_PAD_CS0),
IMX_PINCTRL_PIN(MX25_PAD_CS1),
IMX_PINCTRL_PIN(MX25_PAD_CS4),
IMX_PINCTRL_PIN(MX25_PAD_CS5),
IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
IMX_PINCTRL_PIN(MX25_PAD_ECB),
IMX_PINCTRL_PIN(MX25_PAD_LBA),
IMX_PINCTRL_PIN(MX25_PAD_BCLK),
IMX_PINCTRL_PIN(MX25_PAD_RW),
IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
IMX_PINCTRL_PIN(MX25_PAD_NFALE),
IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
IMX_PINCTRL_PIN(MX25_PAD_NFRB),
IMX_PINCTRL_PIN(MX25_PAD_D15),
IMX_PINCTRL_PIN(MX25_PAD_D14),
IMX_PINCTRL_PIN(MX25_PAD_D13),
IMX_PINCTRL_PIN(MX25_PAD_D12),
IMX_PINCTRL_PIN(MX25_PAD_D11),
IMX_PINCTRL_PIN(MX25_PAD_D10),
IMX_PINCTRL_PIN(MX25_PAD_D9),
IMX_PINCTRL_PIN(MX25_PAD_D8),
IMX_PINCTRL_PIN(MX25_PAD_D7),
IMX_PINCTRL_PIN(MX25_PAD_D6),
IMX_PINCTRL_PIN(MX25_PAD_D5),
IMX_PINCTRL_PIN(MX25_PAD_D4),
IMX_PINCTRL_PIN(MX25_PAD_D3),
IMX_PINCTRL_PIN(MX25_PAD_D2),
IMX_PINCTRL_PIN(MX25_PAD_D1),
IMX_PINCTRL_PIN(MX25_PAD_D0),
IMX_PINCTRL_PIN(MX25_PAD_LD0),
IMX_PINCTRL_PIN(MX25_PAD_LD1),
IMX_PINCTRL_PIN(MX25_PAD_LD2),
IMX_PINCTRL_PIN(MX25_PAD_LD3),
IMX_PINCTRL_PIN(MX25_PAD_LD4),
IMX_PINCTRL_PIN(MX25_PAD_LD5),
IMX_PINCTRL_PIN(MX25_PAD_LD6),
IMX_PINCTRL_PIN(MX25_PAD_LD7),
IMX_PINCTRL_PIN(MX25_PAD_LD8),
IMX_PINCTRL_PIN(MX25_PAD_LD9),
IMX_PINCTRL_PIN(MX25_PAD_LD10),
IMX_PINCTRL_PIN(MX25_PAD_LD11),
IMX_PINCTRL_PIN(MX25_PAD_LD12),
IMX_PINCTRL_PIN(MX25_PAD_LD13),
IMX_PINCTRL_PIN(MX25_PAD_LD14),
IMX_PINCTRL_PIN(MX25_PAD_LD15),
IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX25_PAD_PWM),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
IMX_PINCTRL_PIN(MX25_PAD_RTCK),
IMX_PINCTRL_PIN(MX25_PAD_DE_B),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
IMX_PINCTRL_PIN(MX25_PAD_CLKO),
IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
};
static const struct imx_pinctrl_soc_info imx25_pinctrl_info = {
.pins = imx25_pinctrl_pads,
.npins = ARRAY_SIZE(imx25_pinctrl_pads),
};
static const struct of_device_id imx25_pinctrl_of_match[] = {
{ .compatible = "fsl,imx25-iomuxc", },
{ /* sentinel */ }
};
static int imx25_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
}
static struct platform_driver imx25_pinctrl_driver = {
.driver = {
.name = "imx25-pinctrl",
.of_match_table = imx25_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx25_pinctrl_probe,
};
static int __init imx25_pinctrl_init(void)
{
return platform_driver_register(&imx25_pinctrl_driver);
}
arch_initcall(imx25_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx25.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2016 Freescale Semiconductor, Inc.
// Copyright 2017-2018 NXP.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sll_pads {
MX6SLL_PAD_RESERVE0 = 0,
MX6SLL_PAD_RESERVE1 = 1,
MX6SLL_PAD_RESERVE2 = 2,
MX6SLL_PAD_RESERVE3 = 3,
MX6SLL_PAD_RESERVE4 = 4,
MX6SLL_PAD_WDOG_B = 5,
MX6SLL_PAD_REF_CLK_24M = 6,
MX6SLL_PAD_REF_CLK_32K = 7,
MX6SLL_PAD_PWM1 = 8,
MX6SLL_PAD_KEY_COL0 = 9,
MX6SLL_PAD_KEY_ROW0 = 10,
MX6SLL_PAD_KEY_COL1 = 11,
MX6SLL_PAD_KEY_ROW1 = 12,
MX6SLL_PAD_KEY_COL2 = 13,
MX6SLL_PAD_KEY_ROW2 = 14,
MX6SLL_PAD_KEY_COL3 = 15,
MX6SLL_PAD_KEY_ROW3 = 16,
MX6SLL_PAD_KEY_COL4 = 17,
MX6SLL_PAD_KEY_ROW4 = 18,
MX6SLL_PAD_KEY_COL5 = 19,
MX6SLL_PAD_KEY_ROW5 = 20,
MX6SLL_PAD_KEY_COL6 = 21,
MX6SLL_PAD_KEY_ROW6 = 22,
MX6SLL_PAD_KEY_COL7 = 23,
MX6SLL_PAD_KEY_ROW7 = 24,
MX6SLL_PAD_EPDC_DATA00 = 25,
MX6SLL_PAD_EPDC_DATA01 = 26,
MX6SLL_PAD_EPDC_DATA02 = 27,
MX6SLL_PAD_EPDC_DATA03 = 28,
MX6SLL_PAD_EPDC_DATA04 = 29,
MX6SLL_PAD_EPDC_DATA05 = 30,
MX6SLL_PAD_EPDC_DATA06 = 31,
MX6SLL_PAD_EPDC_DATA07 = 32,
MX6SLL_PAD_EPDC_DATA08 = 33,
MX6SLL_PAD_EPDC_DATA09 = 34,
MX6SLL_PAD_EPDC_DATA10 = 35,
MX6SLL_PAD_EPDC_DATA11 = 36,
MX6SLL_PAD_EPDC_DATA12 = 37,
MX6SLL_PAD_EPDC_DATA13 = 38,
MX6SLL_PAD_EPDC_DATA14 = 39,
MX6SLL_PAD_EPDC_DATA15 = 40,
MX6SLL_PAD_EPDC_SDCLK = 41,
MX6SLL_PAD_EPDC_SDLE = 42,
MX6SLL_PAD_EPDC_SDOE = 43,
MX6SLL_PAD_EPDC_SDSHR = 44,
MX6SLL_PAD_EPDC_SDCE0 = 45,
MX6SLL_PAD_EPDC_SDCE1 = 46,
MX6SLL_PAD_EPDC_SDCE2 = 47,
MX6SLL_PAD_EPDC_SDCE3 = 48,
MX6SLL_PAD_EPDC_GDCLK = 49,
MX6SLL_PAD_EPDC_GDOE = 50,
MX6SLL_PAD_EPDC_GDRL = 51,
MX6SLL_PAD_EPDC_GDSP = 52,
MX6SLL_PAD_EPDC_VCOM0 = 53,
MX6SLL_PAD_EPDC_VCOM1 = 54,
MX6SLL_PAD_EPDC_BDR0 = 55,
MX6SLL_PAD_EPDC_BDR1 = 56,
MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
MX6SLL_PAD_EPDC_PWR_COM = 61,
MX6SLL_PAD_EPDC_PWR_INT = 62,
MX6SLL_PAD_EPDC_PWR_STAT = 63,
MX6SLL_PAD_EPDC_PWR_WAKE = 64,
MX6SLL_PAD_LCD_CLK = 65,
MX6SLL_PAD_LCD_ENABLE = 66,
MX6SLL_PAD_LCD_HSYNC = 67,
MX6SLL_PAD_LCD_VSYNC = 68,
MX6SLL_PAD_LCD_RESET = 69,
MX6SLL_PAD_LCD_DATA00 = 70,
MX6SLL_PAD_LCD_DATA01 = 71,
MX6SLL_PAD_LCD_DATA02 = 72,
MX6SLL_PAD_LCD_DATA03 = 73,
MX6SLL_PAD_LCD_DATA04 = 74,
MX6SLL_PAD_LCD_DATA05 = 75,
MX6SLL_PAD_LCD_DATA06 = 76,
MX6SLL_PAD_LCD_DATA07 = 77,
MX6SLL_PAD_LCD_DATA08 = 78,
MX6SLL_PAD_LCD_DATA09 = 79,
MX6SLL_PAD_LCD_DATA10 = 80,
MX6SLL_PAD_LCD_DATA11 = 81,
MX6SLL_PAD_LCD_DATA12 = 82,
MX6SLL_PAD_LCD_DATA13 = 83,
MX6SLL_PAD_LCD_DATA14 = 84,
MX6SLL_PAD_LCD_DATA15 = 85,
MX6SLL_PAD_LCD_DATA16 = 86,
MX6SLL_PAD_LCD_DATA17 = 87,
MX6SLL_PAD_LCD_DATA18 = 88,
MX6SLL_PAD_LCD_DATA19 = 89,
MX6SLL_PAD_LCD_DATA20 = 90,
MX6SLL_PAD_LCD_DATA21 = 91,
MX6SLL_PAD_LCD_DATA22 = 92,
MX6SLL_PAD_LCD_DATA23 = 93,
MX6SLL_PAD_AUD_RXFS = 94,
MX6SLL_PAD_AUD_RXC = 95,
MX6SLL_PAD_AUD_RXD = 96,
MX6SLL_PAD_AUD_TXC = 97,
MX6SLL_PAD_AUD_TXFS = 98,
MX6SLL_PAD_AUD_TXD = 99,
MX6SLL_PAD_AUD_MCLK = 100,
MX6SLL_PAD_UART1_RXD = 101,
MX6SLL_PAD_UART1_TXD = 102,
MX6SLL_PAD_I2C1_SCL = 103,
MX6SLL_PAD_I2C1_SDA = 104,
MX6SLL_PAD_I2C2_SCL = 105,
MX6SLL_PAD_I2C2_SDA = 106,
MX6SLL_PAD_ECSPI1_SCLK = 107,
MX6SLL_PAD_ECSPI1_MOSI = 108,
MX6SLL_PAD_ECSPI1_MISO = 109,
MX6SLL_PAD_ECSPI1_SS0 = 110,
MX6SLL_PAD_ECSPI2_SCLK = 111,
MX6SLL_PAD_ECSPI2_MOSI = 112,
MX6SLL_PAD_ECSPI2_MISO = 113,
MX6SLL_PAD_ECSPI2_SS0 = 114,
MX6SLL_PAD_SD1_CLK = 115,
MX6SLL_PAD_SD1_CMD = 116,
MX6SLL_PAD_SD1_DATA0 = 117,
MX6SLL_PAD_SD1_DATA1 = 118,
MX6SLL_PAD_SD1_DATA2 = 119,
MX6SLL_PAD_SD1_DATA3 = 120,
MX6SLL_PAD_SD1_DATA4 = 121,
MX6SLL_PAD_SD1_DATA5 = 122,
MX6SLL_PAD_SD1_DATA6 = 123,
MX6SLL_PAD_SD1_DATA7 = 124,
MX6SLL_PAD_SD2_RESET = 125,
MX6SLL_PAD_SD2_CLK = 126,
MX6SLL_PAD_SD2_CMD = 127,
MX6SLL_PAD_SD2_DATA0 = 128,
MX6SLL_PAD_SD2_DATA1 = 129,
MX6SLL_PAD_SD2_DATA2 = 130,
MX6SLL_PAD_SD2_DATA3 = 131,
MX6SLL_PAD_SD2_DATA4 = 132,
MX6SLL_PAD_SD2_DATA5 = 133,
MX6SLL_PAD_SD2_DATA6 = 134,
MX6SLL_PAD_SD2_DATA7 = 135,
MX6SLL_PAD_SD3_CLK = 136,
MX6SLL_PAD_SD3_CMD = 137,
MX6SLL_PAD_SD3_DATA0 = 138,
MX6SLL_PAD_SD3_DATA1 = 139,
MX6SLL_PAD_SD3_DATA2 = 140,
MX6SLL_PAD_SD3_DATA3 = 141,
MX6SLL_PAD_GPIO4_IO20 = 142,
MX6SLL_PAD_GPIO4_IO21 = 143,
MX6SLL_PAD_GPIO4_IO19 = 144,
MX6SLL_PAD_GPIO4_IO25 = 145,
MX6SLL_PAD_GPIO4_IO18 = 146,
MX6SLL_PAD_GPIO4_IO24 = 147,
MX6SLL_PAD_GPIO4_IO23 = 148,
MX6SLL_PAD_GPIO4_IO17 = 149,
MX6SLL_PAD_GPIO4_IO22 = 150,
MX6SLL_PAD_GPIO4_IO16 = 151,
MX6SLL_PAD_GPIO4_IO26 = 152,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
};
static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
.pins = imx6sll_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
.gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
};
static const struct of_device_id imx6sll_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
{ /* sentinel */ }
};
static int imx6sll_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
}
static struct platform_driver imx6sll_pinctrl_driver = {
.driver = {
.name = "imx6sll-pinctrl",
.of_match_table = imx6sll_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sll_pinctrl_probe,
};
static int __init imx6sll_pinctrl_init(void)
{
return platform_driver_register(&imx6sll_pinctrl_driver);
}
arch_initcall(imx6sll_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6sll.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020
* Author(s): Giulio Benetti <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-imx.h"
enum imxrt1050_pads {
IMXRT1050_PAD_RESERVE0,
IMXRT1050_PAD_RESERVE1,
IMXRT1050_PAD_RESERVE2,
IMXRT1050_PAD_RESERVE3,
IMXRT1050_PAD_RESERVE4,
IMXRT1050_PAD_EMC_00,
IMXRT1050_PAD_EMC_01,
IMXRT1050_PAD_EMC_02,
IMXRT1050_PAD_EMC_03,
IMXRT1050_PAD_EMC_04,
IMXRT1050_PAD_EMC_05,
IMXRT1050_PAD_EMC_06,
IMXRT1050_PAD_EMC_07,
IMXRT1050_PAD_EMC_08,
IMXRT1050_PAD_EMC_09,
IMXRT1050_PAD_EMC_10,
IMXRT1050_PAD_EMC_11,
IMXRT1050_PAD_EMC_12,
IMXRT1050_PAD_EMC_13,
IMXRT1050_PAD_EMC_14,
IMXRT1050_PAD_EMC_15,
IMXRT1050_PAD_EMC_16,
IMXRT1050_PAD_EMC_17,
IMXRT1050_PAD_EMC_18,
IMXRT1050_PAD_EMC_19,
IMXRT1050_PAD_EMC_20,
IMXRT1050_PAD_EMC_21,
IMXRT1050_PAD_EMC_22,
IMXRT1050_PAD_EMC_23,
IMXRT1050_PAD_EMC_24,
IMXRT1050_PAD_EMC_25,
IMXRT1050_PAD_EMC_26,
IMXRT1050_PAD_EMC_27,
IMXRT1050_PAD_EMC_28,
IMXRT1050_PAD_EMC_29,
IMXRT1050_PAD_EMC_30,
IMXRT1050_PAD_EMC_31,
IMXRT1050_PAD_EMC_32,
IMXRT1050_PAD_EMC_33,
IMXRT1050_PAD_EMC_34,
IMXRT1050_PAD_EMC_35,
IMXRT1050_PAD_EMC_36,
IMXRT1050_PAD_EMC_37,
IMXRT1050_PAD_EMC_38,
IMXRT1050_PAD_EMC_39,
IMXRT1050_PAD_EMC_40,
IMXRT1050_PAD_EMC_41,
IMXRT1050_PAD_AD_B0_00,
IMXRT1050_PAD_AD_B0_01,
IMXRT1050_PAD_AD_B0_02,
IMXRT1050_PAD_AD_B0_03,
IMXRT1050_PAD_AD_B0_04,
IMXRT1050_PAD_AD_B0_05,
IMXRT1050_PAD_AD_B0_06,
IMXRT1050_PAD_AD_B0_07,
IMXRT1050_PAD_AD_B0_08,
IMXRT1050_PAD_AD_B0_09,
IMXRT1050_PAD_AD_B0_10,
IMXRT1050_PAD_AD_B0_11,
IMXRT1050_PAD_AD_B0_12,
IMXRT1050_PAD_AD_B0_13,
IMXRT1050_PAD_AD_B0_14,
IMXRT1050_PAD_AD_B0_15,
IMXRT1050_PAD_AD_B1_00,
IMXRT1050_PAD_AD_B1_01,
IMXRT1050_PAD_AD_B1_02,
IMXRT1050_PAD_AD_B1_03,
IMXRT1050_PAD_AD_B1_04,
IMXRT1050_PAD_AD_B1_05,
IMXRT1050_PAD_AD_B1_06,
IMXRT1050_PAD_AD_B1_07,
IMXRT1050_PAD_AD_B1_08,
IMXRT1050_PAD_AD_B1_09,
IMXRT1050_PAD_AD_B1_10,
IMXRT1050_PAD_AD_B1_11,
IMXRT1050_PAD_AD_B1_12,
IMXRT1050_PAD_AD_B1_13,
IMXRT1050_PAD_AD_B1_14,
IMXRT1050_PAD_AD_B1_15,
IMXRT1050_PAD_B0_00,
IMXRT1050_PAD_B0_01,
IMXRT1050_PAD_B0_02,
IMXRT1050_PAD_B0_03,
IMXRT1050_PAD_B0_04,
IMXRT1050_PAD_B0_05,
IMXRT1050_PAD_B0_06,
IMXRT1050_PAD_B0_07,
IMXRT1050_PAD_B0_08,
IMXRT1050_PAD_B0_09,
IMXRT1050_PAD_B0_10,
IMXRT1050_PAD_B0_11,
IMXRT1050_PAD_B0_12,
IMXRT1050_PAD_B0_13,
IMXRT1050_PAD_B0_14,
IMXRT1050_PAD_B0_15,
IMXRT1050_PAD_B1_00,
IMXRT1050_PAD_B1_01,
IMXRT1050_PAD_B1_02,
IMXRT1050_PAD_B1_03,
IMXRT1050_PAD_B1_04,
IMXRT1050_PAD_B1_05,
IMXRT1050_PAD_B1_06,
IMXRT1050_PAD_B1_07,
IMXRT1050_PAD_B1_08,
IMXRT1050_PAD_B1_09,
IMXRT1050_PAD_B1_10,
IMXRT1050_PAD_B1_11,
IMXRT1050_PAD_B1_12,
IMXRT1050_PAD_B1_13,
IMXRT1050_PAD_B1_14,
IMXRT1050_PAD_B1_15,
IMXRT1050_PAD_SD_B0_00,
IMXRT1050_PAD_SD_B0_01,
IMXRT1050_PAD_SD_B0_02,
IMXRT1050_PAD_SD_B0_03,
IMXRT1050_PAD_SD_B0_04,
IMXRT1050_PAD_SD_B0_05,
IMXRT1050_PAD_SD_B1_00,
IMXRT1050_PAD_SD_B1_01,
IMXRT1050_PAD_SD_B1_02,
IMXRT1050_PAD_SD_B1_03,
IMXRT1050_PAD_SD_B1_04,
IMXRT1050_PAD_SD_B1_05,
IMXRT1050_PAD_SD_B1_06,
IMXRT1050_PAD_SD_B1_07,
IMXRT1050_PAD_SD_B1_08,
IMXRT1050_PAD_SD_B1_09,
IMXRT1050_PAD_SD_B1_10,
IMXRT1050_PAD_SD_B1_11,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40),
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14),
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14),
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10),
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11),
};
static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
.pins = imxrt1050_pinctrl_pads,
.npins = ARRAY_SIZE(imxrt1050_pinctrl_pads),
.gpr_compatible = "fsl,imxrt1050-iomuxc-gpr",
};
static const struct of_device_id imxrt1050_pinctrl_of_match[] = {
{ .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, },
{ /* sentinel */ }
};
static int imxrt1050_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info);
}
static struct platform_driver imxrt1050_pinctrl_driver = {
.driver = {
.name = "imxrt1050-pinctrl",
.of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imxrt1050_pinctrl_probe,
};
static int __init imxrt1050_pinctrl_init(void)
{
return platform_driver_register(&imxrt1050_pinctrl_driver);
}
arch_initcall(imxrt1050_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imxrt1050.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Freescale imx6dl pinctrl driver
//
// Author: Shawn Guo <[email protected]>
// Copyright (C) 2013 Freescale Semiconductor, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6dl_pads {
MX6DL_PAD_RESERVE0 = 0,
MX6DL_PAD_RESERVE1 = 1,
MX6DL_PAD_RESERVE2 = 2,
MX6DL_PAD_RESERVE3 = 3,
MX6DL_PAD_RESERVE4 = 4,
MX6DL_PAD_RESERVE5 = 5,
MX6DL_PAD_RESERVE6 = 6,
MX6DL_PAD_RESERVE7 = 7,
MX6DL_PAD_RESERVE8 = 8,
MX6DL_PAD_RESERVE9 = 9,
MX6DL_PAD_RESERVE10 = 10,
MX6DL_PAD_RESERVE11 = 11,
MX6DL_PAD_RESERVE12 = 12,
MX6DL_PAD_RESERVE13 = 13,
MX6DL_PAD_RESERVE14 = 14,
MX6DL_PAD_RESERVE15 = 15,
MX6DL_PAD_RESERVE16 = 16,
MX6DL_PAD_RESERVE17 = 17,
MX6DL_PAD_RESERVE18 = 18,
MX6DL_PAD_CSI0_DAT10 = 19,
MX6DL_PAD_CSI0_DAT11 = 20,
MX6DL_PAD_CSI0_DAT12 = 21,
MX6DL_PAD_CSI0_DAT13 = 22,
MX6DL_PAD_CSI0_DAT14 = 23,
MX6DL_PAD_CSI0_DAT15 = 24,
MX6DL_PAD_CSI0_DAT16 = 25,
MX6DL_PAD_CSI0_DAT17 = 26,
MX6DL_PAD_CSI0_DAT18 = 27,
MX6DL_PAD_CSI0_DAT19 = 28,
MX6DL_PAD_CSI0_DAT4 = 29,
MX6DL_PAD_CSI0_DAT5 = 30,
MX6DL_PAD_CSI0_DAT6 = 31,
MX6DL_PAD_CSI0_DAT7 = 32,
MX6DL_PAD_CSI0_DAT8 = 33,
MX6DL_PAD_CSI0_DAT9 = 34,
MX6DL_PAD_CSI0_DATA_EN = 35,
MX6DL_PAD_CSI0_MCLK = 36,
MX6DL_PAD_CSI0_PIXCLK = 37,
MX6DL_PAD_CSI0_VSYNC = 38,
MX6DL_PAD_DI0_DISP_CLK = 39,
MX6DL_PAD_DI0_PIN15 = 40,
MX6DL_PAD_DI0_PIN2 = 41,
MX6DL_PAD_DI0_PIN3 = 42,
MX6DL_PAD_DI0_PIN4 = 43,
MX6DL_PAD_DISP0_DAT0 = 44,
MX6DL_PAD_DISP0_DAT1 = 45,
MX6DL_PAD_DISP0_DAT10 = 46,
MX6DL_PAD_DISP0_DAT11 = 47,
MX6DL_PAD_DISP0_DAT12 = 48,
MX6DL_PAD_DISP0_DAT13 = 49,
MX6DL_PAD_DISP0_DAT14 = 50,
MX6DL_PAD_DISP0_DAT15 = 51,
MX6DL_PAD_DISP0_DAT16 = 52,
MX6DL_PAD_DISP0_DAT17 = 53,
MX6DL_PAD_DISP0_DAT18 = 54,
MX6DL_PAD_DISP0_DAT19 = 55,
MX6DL_PAD_DISP0_DAT2 = 56,
MX6DL_PAD_DISP0_DAT20 = 57,
MX6DL_PAD_DISP0_DAT21 = 58,
MX6DL_PAD_DISP0_DAT22 = 59,
MX6DL_PAD_DISP0_DAT23 = 60,
MX6DL_PAD_DISP0_DAT3 = 61,
MX6DL_PAD_DISP0_DAT4 = 62,
MX6DL_PAD_DISP0_DAT5 = 63,
MX6DL_PAD_DISP0_DAT6 = 64,
MX6DL_PAD_DISP0_DAT7 = 65,
MX6DL_PAD_DISP0_DAT8 = 66,
MX6DL_PAD_DISP0_DAT9 = 67,
MX6DL_PAD_EIM_A16 = 68,
MX6DL_PAD_EIM_A17 = 69,
MX6DL_PAD_EIM_A18 = 70,
MX6DL_PAD_EIM_A19 = 71,
MX6DL_PAD_EIM_A20 = 72,
MX6DL_PAD_EIM_A21 = 73,
MX6DL_PAD_EIM_A22 = 74,
MX6DL_PAD_EIM_A23 = 75,
MX6DL_PAD_EIM_A24 = 76,
MX6DL_PAD_EIM_A25 = 77,
MX6DL_PAD_EIM_BCLK = 78,
MX6DL_PAD_EIM_CS0 = 79,
MX6DL_PAD_EIM_CS1 = 80,
MX6DL_PAD_EIM_D16 = 81,
MX6DL_PAD_EIM_D17 = 82,
MX6DL_PAD_EIM_D18 = 83,
MX6DL_PAD_EIM_D19 = 84,
MX6DL_PAD_EIM_D20 = 85,
MX6DL_PAD_EIM_D21 = 86,
MX6DL_PAD_EIM_D22 = 87,
MX6DL_PAD_EIM_D23 = 88,
MX6DL_PAD_EIM_D24 = 89,
MX6DL_PAD_EIM_D25 = 90,
MX6DL_PAD_EIM_D26 = 91,
MX6DL_PAD_EIM_D27 = 92,
MX6DL_PAD_EIM_D28 = 93,
MX6DL_PAD_EIM_D29 = 94,
MX6DL_PAD_EIM_D30 = 95,
MX6DL_PAD_EIM_D31 = 96,
MX6DL_PAD_EIM_DA0 = 97,
MX6DL_PAD_EIM_DA1 = 98,
MX6DL_PAD_EIM_DA10 = 99,
MX6DL_PAD_EIM_DA11 = 100,
MX6DL_PAD_EIM_DA12 = 101,
MX6DL_PAD_EIM_DA13 = 102,
MX6DL_PAD_EIM_DA14 = 103,
MX6DL_PAD_EIM_DA15 = 104,
MX6DL_PAD_EIM_DA2 = 105,
MX6DL_PAD_EIM_DA3 = 106,
MX6DL_PAD_EIM_DA4 = 107,
MX6DL_PAD_EIM_DA5 = 108,
MX6DL_PAD_EIM_DA6 = 109,
MX6DL_PAD_EIM_DA7 = 110,
MX6DL_PAD_EIM_DA8 = 111,
MX6DL_PAD_EIM_DA9 = 112,
MX6DL_PAD_EIM_EB0 = 113,
MX6DL_PAD_EIM_EB1 = 114,
MX6DL_PAD_EIM_EB2 = 115,
MX6DL_PAD_EIM_EB3 = 116,
MX6DL_PAD_EIM_LBA = 117,
MX6DL_PAD_EIM_OE = 118,
MX6DL_PAD_EIM_RW = 119,
MX6DL_PAD_EIM_WAIT = 120,
MX6DL_PAD_ENET_CRS_DV = 121,
MX6DL_PAD_ENET_MDC = 122,
MX6DL_PAD_ENET_MDIO = 123,
MX6DL_PAD_ENET_REF_CLK = 124,
MX6DL_PAD_ENET_RX_ER = 125,
MX6DL_PAD_ENET_RXD0 = 126,
MX6DL_PAD_ENET_RXD1 = 127,
MX6DL_PAD_ENET_TX_EN = 128,
MX6DL_PAD_ENET_TXD0 = 129,
MX6DL_PAD_ENET_TXD1 = 130,
MX6DL_PAD_GPIO_0 = 131,
MX6DL_PAD_GPIO_1 = 132,
MX6DL_PAD_GPIO_16 = 133,
MX6DL_PAD_GPIO_17 = 134,
MX6DL_PAD_GPIO_18 = 135,
MX6DL_PAD_GPIO_19 = 136,
MX6DL_PAD_GPIO_2 = 137,
MX6DL_PAD_GPIO_3 = 138,
MX6DL_PAD_GPIO_4 = 139,
MX6DL_PAD_GPIO_5 = 140,
MX6DL_PAD_GPIO_6 = 141,
MX6DL_PAD_GPIO_7 = 142,
MX6DL_PAD_GPIO_8 = 143,
MX6DL_PAD_GPIO_9 = 144,
MX6DL_PAD_KEY_COL0 = 145,
MX6DL_PAD_KEY_COL1 = 146,
MX6DL_PAD_KEY_COL2 = 147,
MX6DL_PAD_KEY_COL3 = 148,
MX6DL_PAD_KEY_COL4 = 149,
MX6DL_PAD_KEY_ROW0 = 150,
MX6DL_PAD_KEY_ROW1 = 151,
MX6DL_PAD_KEY_ROW2 = 152,
MX6DL_PAD_KEY_ROW3 = 153,
MX6DL_PAD_KEY_ROW4 = 154,
MX6DL_PAD_NANDF_ALE = 155,
MX6DL_PAD_NANDF_CLE = 156,
MX6DL_PAD_NANDF_CS0 = 157,
MX6DL_PAD_NANDF_CS1 = 158,
MX6DL_PAD_NANDF_CS2 = 159,
MX6DL_PAD_NANDF_CS3 = 160,
MX6DL_PAD_NANDF_D0 = 161,
MX6DL_PAD_NANDF_D1 = 162,
MX6DL_PAD_NANDF_D2 = 163,
MX6DL_PAD_NANDF_D3 = 164,
MX6DL_PAD_NANDF_D4 = 165,
MX6DL_PAD_NANDF_D5 = 166,
MX6DL_PAD_NANDF_D6 = 167,
MX6DL_PAD_NANDF_D7 = 168,
MX6DL_PAD_NANDF_RB0 = 169,
MX6DL_PAD_NANDF_WP_B = 170,
MX6DL_PAD_RGMII_RD0 = 171,
MX6DL_PAD_RGMII_RD1 = 172,
MX6DL_PAD_RGMII_RD2 = 173,
MX6DL_PAD_RGMII_RD3 = 174,
MX6DL_PAD_RGMII_RX_CTL = 175,
MX6DL_PAD_RGMII_RXC = 176,
MX6DL_PAD_RGMII_TD0 = 177,
MX6DL_PAD_RGMII_TD1 = 178,
MX6DL_PAD_RGMII_TD2 = 179,
MX6DL_PAD_RGMII_TD3 = 180,
MX6DL_PAD_RGMII_TX_CTL = 181,
MX6DL_PAD_RGMII_TXC = 182,
MX6DL_PAD_SD1_CLK = 183,
MX6DL_PAD_SD1_CMD = 184,
MX6DL_PAD_SD1_DAT0 = 185,
MX6DL_PAD_SD1_DAT1 = 186,
MX6DL_PAD_SD1_DAT2 = 187,
MX6DL_PAD_SD1_DAT3 = 188,
MX6DL_PAD_SD2_CLK = 189,
MX6DL_PAD_SD2_CMD = 190,
MX6DL_PAD_SD2_DAT0 = 191,
MX6DL_PAD_SD2_DAT1 = 192,
MX6DL_PAD_SD2_DAT2 = 193,
MX6DL_PAD_SD2_DAT3 = 194,
MX6DL_PAD_SD3_CLK = 195,
MX6DL_PAD_SD3_CMD = 196,
MX6DL_PAD_SD3_DAT0 = 197,
MX6DL_PAD_SD3_DAT1 = 198,
MX6DL_PAD_SD3_DAT2 = 199,
MX6DL_PAD_SD3_DAT3 = 200,
MX6DL_PAD_SD3_DAT4 = 201,
MX6DL_PAD_SD3_DAT5 = 202,
MX6DL_PAD_SD3_DAT6 = 203,
MX6DL_PAD_SD3_DAT7 = 204,
MX6DL_PAD_SD3_RST = 205,
MX6DL_PAD_SD4_CLK = 206,
MX6DL_PAD_SD4_CMD = 207,
MX6DL_PAD_SD4_DAT0 = 208,
MX6DL_PAD_SD4_DAT1 = 209,
MX6DL_PAD_SD4_DAT2 = 210,
MX6DL_PAD_SD4_DAT3 = 211,
MX6DL_PAD_SD4_DAT4 = 212,
MX6DL_PAD_SD4_DAT5 = 213,
MX6DL_PAD_SD4_DAT6 = 214,
MX6DL_PAD_SD4_DAT7 = 215,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT10),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT11),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT12),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT13),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT14),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT15),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT16),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT17),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT18),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT19),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT8),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DAT9),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_DATA_EN),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_MCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_PIXCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_CSI0_VSYNC),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_DISP_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN15),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN2),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN3),
IMX_PINCTRL_PIN(MX6DL_PAD_DI0_PIN4),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT10),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT11),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT12),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT13),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT14),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT15),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT16),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT17),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT18),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT19),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT20),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT21),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT22),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT23),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT8),
IMX_PINCTRL_PIN(MX6DL_PAD_DISP0_DAT9),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A16),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A17),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A18),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A19),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A20),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A21),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A22),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A23),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A24),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_A25),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D16),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D17),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D18),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D19),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D20),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D21),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D22),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D23),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D24),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D25),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D26),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D27),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D28),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D29),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D30),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_D31),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB2),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_EB3),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX6DL_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_CRS_DV),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDC),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_MDIO),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_REF_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RX_ER),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD0),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_RXD1),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TX_EN),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD0),
IMX_PINCTRL_PIN(MX6DL_PAD_ENET_TXD1),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_0),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_1),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_16),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_17),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_18),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_2),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_3),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_4),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_5),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_6),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_7),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_8),
IMX_PINCTRL_PIN(MX6DL_PAD_GPIO_9),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6DL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_ALE),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CLE),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS1),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS2),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_CS3),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D1),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D2),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D3),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D4),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D5),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D6),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_D7),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_RB0),
IMX_PINCTRL_PIN(MX6DL_PAD_NANDF_WP_B),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD0),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD1),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD2),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RD3),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RX_CTL),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_RXC),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD0),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD1),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD2),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TD3),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TX_CTL),
IMX_PINCTRL_PIN(MX6DL_PAD_RGMII_TXC),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD1_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD2_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_DAT7),
IMX_PINCTRL_PIN(MX6DL_PAD_SD3_RST),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CLK),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_CMD),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT0),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT1),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT2),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT3),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT4),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT5),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT6),
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
};
static const struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.pins = imx6dl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6dl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6dl-iomuxc", },
{ /* sentinel */ }
};
static int imx6dl_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6dl_pinctrl_info);
}
static struct platform_driver imx6dl_pinctrl_driver = {
.driver = {
.name = "imx6dl-pinctrl",
.of_match_table = imx6dl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6dl_pinctrl_probe,
};
static int __init imx6dl_pinctrl_init(void)
{
return platform_driver_register(&imx6dl_pinctrl_driver);
}
arch_initcall(imx6dl_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx6dl.c
|
// SPDX-License-Identifier: GPL-2.0
//
// imx35 pinctrl driver.
//
// This driver was mostly copied from the imx51 pinctrl driver which has:
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx35_pads {
MX35_PAD_RESERVE0 = 0,
MX35_PAD_CAPTURE = 1,
MX35_PAD_COMPARE = 2,
MX35_PAD_WDOG_RST = 3,
MX35_PAD_GPIO1_0 = 4,
MX35_PAD_GPIO1_1 = 5,
MX35_PAD_GPIO2_0 = 6,
MX35_PAD_GPIO3_0 = 7,
MX35_PAD_CLKO = 8,
MX35_PAD_VSTBY = 9,
MX35_PAD_A0 = 10,
MX35_PAD_A1 = 11,
MX35_PAD_A2 = 12,
MX35_PAD_A3 = 13,
MX35_PAD_A4 = 14,
MX35_PAD_A5 = 15,
MX35_PAD_A6 = 16,
MX35_PAD_A7 = 17,
MX35_PAD_A8 = 18,
MX35_PAD_A9 = 19,
MX35_PAD_A10 = 20,
MX35_PAD_MA10 = 21,
MX35_PAD_A11 = 22,
MX35_PAD_A12 = 23,
MX35_PAD_A13 = 24,
MX35_PAD_A14 = 25,
MX35_PAD_A15 = 26,
MX35_PAD_A16 = 27,
MX35_PAD_A17 = 28,
MX35_PAD_A18 = 29,
MX35_PAD_A19 = 30,
MX35_PAD_A20 = 31,
MX35_PAD_A21 = 32,
MX35_PAD_A22 = 33,
MX35_PAD_A23 = 34,
MX35_PAD_A24 = 35,
MX35_PAD_A25 = 36,
MX35_PAD_EB0 = 37,
MX35_PAD_EB1 = 38,
MX35_PAD_OE = 39,
MX35_PAD_CS0 = 40,
MX35_PAD_CS1 = 41,
MX35_PAD_CS2 = 42,
MX35_PAD_CS3 = 43,
MX35_PAD_CS4 = 44,
MX35_PAD_CS5 = 45,
MX35_PAD_NF_CE0 = 46,
MX35_PAD_LBA = 47,
MX35_PAD_BCLK = 48,
MX35_PAD_RW = 49,
MX35_PAD_NFWE_B = 50,
MX35_PAD_NFRE_B = 51,
MX35_PAD_NFALE = 52,
MX35_PAD_NFCLE = 53,
MX35_PAD_NFWP_B = 54,
MX35_PAD_NFRB = 55,
MX35_PAD_CSI_D8 = 56,
MX35_PAD_CSI_D9 = 57,
MX35_PAD_CSI_D10 = 58,
MX35_PAD_CSI_D11 = 59,
MX35_PAD_CSI_D12 = 60,
MX35_PAD_CSI_D13 = 61,
MX35_PAD_CSI_D14 = 62,
MX35_PAD_CSI_D15 = 63,
MX35_PAD_CSI_MCLK = 64,
MX35_PAD_CSI_VSYNC = 65,
MX35_PAD_CSI_HSYNC = 66,
MX35_PAD_CSI_PIXCLK = 67,
MX35_PAD_I2C1_CLK = 68,
MX35_PAD_I2C1_DAT = 69,
MX35_PAD_I2C2_CLK = 70,
MX35_PAD_I2C2_DAT = 71,
MX35_PAD_STXD4 = 72,
MX35_PAD_SRXD4 = 73,
MX35_PAD_SCK4 = 74,
MX35_PAD_STXFS4 = 75,
MX35_PAD_STXD5 = 76,
MX35_PAD_SRXD5 = 77,
MX35_PAD_SCK5 = 78,
MX35_PAD_STXFS5 = 79,
MX35_PAD_SCKR = 80,
MX35_PAD_FSR = 81,
MX35_PAD_HCKR = 82,
MX35_PAD_SCKT = 83,
MX35_PAD_FST = 84,
MX35_PAD_HCKT = 85,
MX35_PAD_TX5_RX0 = 86,
MX35_PAD_TX4_RX1 = 87,
MX35_PAD_TX3_RX2 = 88,
MX35_PAD_TX2_RX3 = 89,
MX35_PAD_TX1 = 90,
MX35_PAD_TX0 = 91,
MX35_PAD_CSPI1_MOSI = 92,
MX35_PAD_CSPI1_MISO = 93,
MX35_PAD_CSPI1_SS0 = 94,
MX35_PAD_CSPI1_SS1 = 95,
MX35_PAD_CSPI1_SCLK = 96,
MX35_PAD_CSPI1_SPI_RDY = 97,
MX35_PAD_RXD1 = 98,
MX35_PAD_TXD1 = 99,
MX35_PAD_RTS1 = 100,
MX35_PAD_CTS1 = 101,
MX35_PAD_RXD2 = 102,
MX35_PAD_TXD2 = 103,
MX35_PAD_RTS2 = 104,
MX35_PAD_CTS2 = 105,
MX35_PAD_USBOTG_PWR = 106,
MX35_PAD_USBOTG_OC = 107,
MX35_PAD_LD0 = 108,
MX35_PAD_LD1 = 109,
MX35_PAD_LD2 = 110,
MX35_PAD_LD3 = 111,
MX35_PAD_LD4 = 112,
MX35_PAD_LD5 = 113,
MX35_PAD_LD6 = 114,
MX35_PAD_LD7 = 115,
MX35_PAD_LD8 = 116,
MX35_PAD_LD9 = 117,
MX35_PAD_LD10 = 118,
MX35_PAD_LD11 = 119,
MX35_PAD_LD12 = 120,
MX35_PAD_LD13 = 121,
MX35_PAD_LD14 = 122,
MX35_PAD_LD15 = 123,
MX35_PAD_LD16 = 124,
MX35_PAD_LD17 = 125,
MX35_PAD_LD18 = 126,
MX35_PAD_LD19 = 127,
MX35_PAD_LD20 = 128,
MX35_PAD_LD21 = 129,
MX35_PAD_LD22 = 130,
MX35_PAD_LD23 = 131,
MX35_PAD_D3_HSYNC = 132,
MX35_PAD_D3_FPSHIFT = 133,
MX35_PAD_D3_DRDY = 134,
MX35_PAD_CONTRAST = 135,
MX35_PAD_D3_VSYNC = 136,
MX35_PAD_D3_REV = 137,
MX35_PAD_D3_CLS = 138,
MX35_PAD_D3_SPL = 139,
MX35_PAD_SD1_CMD = 140,
MX35_PAD_SD1_CLK = 141,
MX35_PAD_SD1_DATA0 = 142,
MX35_PAD_SD1_DATA1 = 143,
MX35_PAD_SD1_DATA2 = 144,
MX35_PAD_SD1_DATA3 = 145,
MX35_PAD_SD2_CMD = 146,
MX35_PAD_SD2_CLK = 147,
MX35_PAD_SD2_DATA0 = 148,
MX35_PAD_SD2_DATA1 = 149,
MX35_PAD_SD2_DATA2 = 150,
MX35_PAD_SD2_DATA3 = 151,
MX35_PAD_ATA_CS0 = 152,
MX35_PAD_ATA_CS1 = 153,
MX35_PAD_ATA_DIOR = 154,
MX35_PAD_ATA_DIOW = 155,
MX35_PAD_ATA_DMACK = 156,
MX35_PAD_ATA_RESET_B = 157,
MX35_PAD_ATA_IORDY = 158,
MX35_PAD_ATA_DATA0 = 159,
MX35_PAD_ATA_DATA1 = 160,
MX35_PAD_ATA_DATA2 = 161,
MX35_PAD_ATA_DATA3 = 162,
MX35_PAD_ATA_DATA4 = 163,
MX35_PAD_ATA_DATA5 = 164,
MX35_PAD_ATA_DATA6 = 165,
MX35_PAD_ATA_DATA7 = 166,
MX35_PAD_ATA_DATA8 = 167,
MX35_PAD_ATA_DATA9 = 168,
MX35_PAD_ATA_DATA10 = 169,
MX35_PAD_ATA_DATA11 = 170,
MX35_PAD_ATA_DATA12 = 171,
MX35_PAD_ATA_DATA13 = 172,
MX35_PAD_ATA_DATA14 = 173,
MX35_PAD_ATA_DATA15 = 174,
MX35_PAD_ATA_INTRQ = 175,
MX35_PAD_ATA_BUFF_EN = 176,
MX35_PAD_ATA_DMARQ = 177,
MX35_PAD_ATA_DA0 = 178,
MX35_PAD_ATA_DA1 = 179,
MX35_PAD_ATA_DA2 = 180,
MX35_PAD_MLB_CLK = 181,
MX35_PAD_MLB_DAT = 182,
MX35_PAD_MLB_SIG = 183,
MX35_PAD_FEC_TX_CLK = 184,
MX35_PAD_FEC_RX_CLK = 185,
MX35_PAD_FEC_RX_DV = 186,
MX35_PAD_FEC_COL = 187,
MX35_PAD_FEC_RDATA0 = 188,
MX35_PAD_FEC_TDATA0 = 189,
MX35_PAD_FEC_TX_EN = 190,
MX35_PAD_FEC_MDC = 191,
MX35_PAD_FEC_MDIO = 192,
MX35_PAD_FEC_TX_ERR = 193,
MX35_PAD_FEC_RX_ERR = 194,
MX35_PAD_FEC_CRS = 195,
MX35_PAD_FEC_RDATA1 = 196,
MX35_PAD_FEC_TDATA1 = 197,
MX35_PAD_FEC_RDATA2 = 198,
MX35_PAD_FEC_TDATA2 = 199,
MX35_PAD_FEC_RDATA3 = 200,
MX35_PAD_FEC_TDATA3 = 201,
MX35_PAD_RESERVE1 = 202,
MX35_PAD_RESERVE2 = 203,
MX35_PAD_RESERVE3 = 204,
MX35_PAD_RESERVE4 = 205,
MX35_PAD_RESERVE5 = 206,
MX35_PAD_RESERVE6 = 207,
MX35_PAD_RESERVE7 = 208,
MX35_PAD_RESET_IN_B = 209,
MX35_PAD_POR_B = 210,
MX35_PAD_RESERVE8 = 211,
MX35_PAD_BOOT_MODE0 = 212,
MX35_PAD_BOOT_MODE1 = 213,
MX35_PAD_CLK_MODE0 = 214,
MX35_PAD_CLK_MODE1 = 215,
MX35_PAD_POWER_FAIL = 216,
MX35_PAD_RESERVE9 = 217,
MX35_PAD_RESERVE10 = 218,
MX35_PAD_RESERVE11 = 219,
MX35_PAD_RESERVE12 = 220,
MX35_PAD_RESERVE13 = 221,
MX35_PAD_RESERVE14 = 222,
MX35_PAD_RESERVE15 = 223,
MX35_PAD_RESERVE16 = 224,
MX35_PAD_RESERVE17 = 225,
MX35_PAD_RESERVE18 = 226,
MX35_PAD_RESERVE19 = 227,
MX35_PAD_RESERVE20 = 228,
MX35_PAD_RESERVE21 = 229,
MX35_PAD_RESERVE22 = 230,
MX35_PAD_RESERVE23 = 231,
MX35_PAD_RESERVE24 = 232,
MX35_PAD_RESERVE25 = 233,
MX35_PAD_RESERVE26 = 234,
MX35_PAD_RESERVE27 = 235,
MX35_PAD_RESERVE28 = 236,
MX35_PAD_RESERVE29 = 237,
MX35_PAD_RESERVE30 = 238,
MX35_PAD_RESERVE31 = 239,
MX35_PAD_RESERVE32 = 240,
MX35_PAD_RESERVE33 = 241,
MX35_PAD_RESERVE34 = 242,
MX35_PAD_RESERVE35 = 243,
MX35_PAD_RESERVE36 = 244,
MX35_PAD_SDBA1 = 245,
MX35_PAD_SDBA0 = 246,
MX35_PAD_SD0 = 247,
MX35_PAD_SD1 = 248,
MX35_PAD_SD2 = 249,
MX35_PAD_SD3 = 250,
MX35_PAD_SD4 = 251,
MX35_PAD_SD5 = 252,
MX35_PAD_SD6 = 253,
MX35_PAD_SD7 = 254,
MX35_PAD_SD8 = 255,
MX35_PAD_SD9 = 256,
MX35_PAD_SD10 = 257,
MX35_PAD_SD11 = 258,
MX35_PAD_SD12 = 259,
MX35_PAD_SD13 = 260,
MX35_PAD_SD14 = 261,
MX35_PAD_SD15 = 262,
MX35_PAD_SD16 = 263,
MX35_PAD_SD17 = 264,
MX35_PAD_SD18 = 265,
MX35_PAD_SD19 = 266,
MX35_PAD_SD20 = 267,
MX35_PAD_SD21 = 268,
MX35_PAD_SD22 = 269,
MX35_PAD_SD23 = 270,
MX35_PAD_SD24 = 271,
MX35_PAD_SD25 = 272,
MX35_PAD_SD26 = 273,
MX35_PAD_SD27 = 274,
MX35_PAD_SD28 = 275,
MX35_PAD_SD29 = 276,
MX35_PAD_SD30 = 277,
MX35_PAD_SD31 = 278,
MX35_PAD_DQM0 = 279,
MX35_PAD_DQM1 = 280,
MX35_PAD_DQM2 = 281,
MX35_PAD_DQM3 = 282,
MX35_PAD_RESERVE37 = 283,
MX35_PAD_RESERVE38 = 284,
MX35_PAD_RESERVE39 = 285,
MX35_PAD_RESERVE40 = 286,
MX35_PAD_RESERVE41 = 287,
MX35_PAD_RESERVE42 = 288,
MX35_PAD_RESERVE43 = 289,
MX35_PAD_RESERVE44 = 290,
MX35_PAD_RESERVE45 = 291,
MX35_PAD_RESERVE46 = 292,
MX35_PAD_ECB = 293,
MX35_PAD_RESERVE47 = 294,
MX35_PAD_RESERVE48 = 295,
MX35_PAD_RESERVE49 = 296,
MX35_PAD_RAS = 297,
MX35_PAD_CAS = 298,
MX35_PAD_SDWE = 299,
MX35_PAD_SDCKE0 = 300,
MX35_PAD_SDCKE1 = 301,
MX35_PAD_SDCLK = 302,
MX35_PAD_SDQS0 = 303,
MX35_PAD_SDQS1 = 304,
MX35_PAD_SDQS2 = 305,
MX35_PAD_SDQS3 = 306,
MX35_PAD_RESERVE50 = 307,
MX35_PAD_RESERVE51 = 308,
MX35_PAD_RESERVE52 = 309,
MX35_PAD_RESERVE53 = 310,
MX35_PAD_RESERVE54 = 311,
MX35_PAD_RESERVE55 = 312,
MX35_PAD_D15 = 313,
MX35_PAD_D14 = 314,
MX35_PAD_D13 = 315,
MX35_PAD_D12 = 316,
MX35_PAD_D11 = 317,
MX35_PAD_D10 = 318,
MX35_PAD_D9 = 319,
MX35_PAD_D8 = 320,
MX35_PAD_D7 = 321,
MX35_PAD_D6 = 322,
MX35_PAD_D5 = 323,
MX35_PAD_D4 = 324,
MX35_PAD_D3 = 325,
MX35_PAD_D2 = 326,
MX35_PAD_D1 = 327,
MX35_PAD_D0 = 328,
MX35_PAD_RESERVE56 = 329,
MX35_PAD_RESERVE57 = 330,
MX35_PAD_RESERVE58 = 331,
MX35_PAD_RESERVE59 = 332,
MX35_PAD_RESERVE60 = 333,
MX35_PAD_RESERVE61 = 334,
MX35_PAD_RESERVE62 = 335,
MX35_PAD_RESERVE63 = 336,
MX35_PAD_RESERVE64 = 337,
MX35_PAD_RESERVE65 = 338,
MX35_PAD_RESERVE66 = 339,
MX35_PAD_RESERVE67 = 340,
MX35_PAD_RESERVE68 = 341,
MX35_PAD_RESERVE69 = 342,
MX35_PAD_RESERVE70 = 343,
MX35_PAD_RESERVE71 = 344,
MX35_PAD_RESERVE72 = 345,
MX35_PAD_RESERVE73 = 346,
MX35_PAD_RESERVE74 = 347,
MX35_PAD_RESERVE75 = 348,
MX35_PAD_RESERVE76 = 349,
MX35_PAD_RESERVE77 = 350,
MX35_PAD_RESERVE78 = 351,
MX35_PAD_RESERVE79 = 352,
MX35_PAD_RESERVE80 = 353,
MX35_PAD_RESERVE81 = 354,
MX35_PAD_RESERVE82 = 355,
MX35_PAD_RESERVE83 = 356,
MX35_PAD_RESERVE84 = 357,
MX35_PAD_RESERVE85 = 358,
MX35_PAD_RESERVE86 = 359,
MX35_PAD_RESERVE87 = 360,
MX35_PAD_RESERVE88 = 361,
MX35_PAD_RESERVE89 = 362,
MX35_PAD_RESERVE90 = 363,
MX35_PAD_RESERVE91 = 364,
MX35_PAD_RESERVE92 = 365,
MX35_PAD_RESERVE93 = 366,
MX35_PAD_RESERVE94 = 367,
MX35_PAD_RESERVE95 = 368,
MX35_PAD_RESERVE96 = 369,
MX35_PAD_RESERVE97 = 370,
MX35_PAD_RESERVE98 = 371,
MX35_PAD_RESERVE99 = 372,
MX35_PAD_RESERVE100 = 373,
MX35_PAD_RESERVE101 = 374,
MX35_PAD_RESERVE102 = 375,
MX35_PAD_RESERVE103 = 376,
MX35_PAD_RESERVE104 = 377,
MX35_PAD_RESERVE105 = 378,
MX35_PAD_RTCK = 379,
MX35_PAD_TCK = 380,
MX35_PAD_TMS = 381,
MX35_PAD_TDI = 382,
MX35_PAD_TDO = 383,
MX35_PAD_TRSTB = 384,
MX35_PAD_DE_B = 385,
MX35_PAD_SJC_MOD = 386,
MX35_PAD_RESERVE106 = 387,
MX35_PAD_RESERVE107 = 388,
MX35_PAD_RESERVE108 = 389,
MX35_PAD_RESERVE109 = 390,
MX35_PAD_RESERVE110 = 391,
MX35_PAD_RESERVE111 = 392,
MX35_PAD_RESERVE112 = 393,
MX35_PAD_RESERVE113 = 394,
MX35_PAD_RESERVE114 = 395,
MX35_PAD_RESERVE115 = 396,
MX35_PAD_RESERVE116 = 397,
MX35_PAD_RESERVE117 = 398,
MX35_PAD_RESERVE118 = 399,
MX35_PAD_RESERVE119 = 400,
MX35_PAD_RESERVE120 = 401,
MX35_PAD_RESERVE121 = 402,
MX35_PAD_RESERVE122 = 403,
MX35_PAD_RESERVE123 = 404,
MX35_PAD_RESERVE124 = 405,
MX35_PAD_RESERVE125 = 406,
MX35_PAD_RESERVE126 = 407,
MX35_PAD_RESERVE127 = 408,
MX35_PAD_RESERVE128 = 409,
MX35_PAD_RESERVE129 = 410,
MX35_PAD_RESERVE130 = 411,
MX35_PAD_RESERVE131 = 412,
MX35_PAD_RESERVE132 = 413,
MX35_PAD_RESERVE133 = 414,
MX35_PAD_RESERVE134 = 415,
MX35_PAD_RESERVE135 = 416,
MX35_PAD_RESERVE136 = 417,
MX35_PAD_RESERVE137 = 418,
MX35_PAD_RESERVE138 = 419,
MX35_PAD_RESERVE139 = 420,
MX35_PAD_RESERVE140 = 421,
MX35_PAD_RESERVE141 = 422,
MX35_PAD_RESERVE142 = 423,
MX35_PAD_RESERVE143 = 424,
MX35_PAD_RESERVE144 = 425,
MX35_PAD_RESERVE145 = 426,
MX35_PAD_RESERVE146 = 427,
MX35_PAD_RESERVE147 = 428,
MX35_PAD_RESERVE148 = 429,
MX35_PAD_RESERVE149 = 430,
MX35_PAD_RESERVE150 = 431,
MX35_PAD_RESERVE151 = 432,
MX35_PAD_RESERVE152 = 433,
MX35_PAD_RESERVE153 = 434,
MX35_PAD_RESERVE154 = 435,
MX35_PAD_RESERVE155 = 436,
MX35_PAD_RESERVE156 = 437,
MX35_PAD_RESERVE157 = 438,
MX35_PAD_RESERVE158 = 439,
MX35_PAD_RESERVE159 = 440,
MX35_PAD_RESERVE160 = 441,
MX35_PAD_RESERVE161 = 442,
MX35_PAD_RESERVE162 = 443,
MX35_PAD_RESERVE163 = 444,
MX35_PAD_RESERVE164 = 445,
MX35_PAD_RESERVE165 = 446,
MX35_PAD_RESERVE166 = 447,
MX35_PAD_RESERVE167 = 448,
MX35_PAD_RESERVE168 = 449,
MX35_PAD_RESERVE169 = 450,
MX35_PAD_RESERVE170 = 451,
MX35_PAD_RESERVE171 = 452,
MX35_PAD_RESERVE172 = 453,
MX35_PAD_RESERVE173 = 454,
MX35_PAD_RESERVE174 = 455,
MX35_PAD_RESERVE175 = 456,
MX35_PAD_RESERVE176 = 457,
MX35_PAD_RESERVE177 = 458,
MX35_PAD_RESERVE178 = 459,
MX35_PAD_RESERVE179 = 460,
MX35_PAD_RESERVE180 = 461,
MX35_PAD_RESERVE181 = 462,
MX35_PAD_RESERVE182 = 463,
MX35_PAD_RESERVE183 = 464,
MX35_PAD_RESERVE184 = 465,
MX35_PAD_RESERVE185 = 466,
MX35_PAD_RESERVE186 = 467,
MX35_PAD_RESERVE187 = 468,
MX35_PAD_RESERVE188 = 469,
MX35_PAD_RESERVE189 = 470,
MX35_PAD_RESERVE190 = 471,
MX35_PAD_RESERVE191 = 472,
MX35_PAD_RESERVE192 = 473,
MX35_PAD_RESERVE193 = 474,
MX35_PAD_RESERVE194 = 475,
MX35_PAD_RESERVE195 = 476,
MX35_PAD_RESERVE196 = 477,
MX35_PAD_RESERVE197 = 478,
MX35_PAD_RESERVE198 = 479,
MX35_PAD_RESERVE199 = 480,
MX35_PAD_RESERVE200 = 481,
MX35_PAD_RESERVE201 = 482,
MX35_PAD_EXT_ARMCLK = 483,
MX35_PAD_TEST_MODE = 484,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX35_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
IMX_PINCTRL_PIN(MX35_PAD_CLKO),
IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
IMX_PINCTRL_PIN(MX35_PAD_A0),
IMX_PINCTRL_PIN(MX35_PAD_A1),
IMX_PINCTRL_PIN(MX35_PAD_A2),
IMX_PINCTRL_PIN(MX35_PAD_A3),
IMX_PINCTRL_PIN(MX35_PAD_A4),
IMX_PINCTRL_PIN(MX35_PAD_A5),
IMX_PINCTRL_PIN(MX35_PAD_A6),
IMX_PINCTRL_PIN(MX35_PAD_A7),
IMX_PINCTRL_PIN(MX35_PAD_A8),
IMX_PINCTRL_PIN(MX35_PAD_A9),
IMX_PINCTRL_PIN(MX35_PAD_A10),
IMX_PINCTRL_PIN(MX35_PAD_MA10),
IMX_PINCTRL_PIN(MX35_PAD_A11),
IMX_PINCTRL_PIN(MX35_PAD_A12),
IMX_PINCTRL_PIN(MX35_PAD_A13),
IMX_PINCTRL_PIN(MX35_PAD_A14),
IMX_PINCTRL_PIN(MX35_PAD_A15),
IMX_PINCTRL_PIN(MX35_PAD_A16),
IMX_PINCTRL_PIN(MX35_PAD_A17),
IMX_PINCTRL_PIN(MX35_PAD_A18),
IMX_PINCTRL_PIN(MX35_PAD_A19),
IMX_PINCTRL_PIN(MX35_PAD_A20),
IMX_PINCTRL_PIN(MX35_PAD_A21),
IMX_PINCTRL_PIN(MX35_PAD_A22),
IMX_PINCTRL_PIN(MX35_PAD_A23),
IMX_PINCTRL_PIN(MX35_PAD_A24),
IMX_PINCTRL_PIN(MX35_PAD_A25),
IMX_PINCTRL_PIN(MX35_PAD_EB0),
IMX_PINCTRL_PIN(MX35_PAD_EB1),
IMX_PINCTRL_PIN(MX35_PAD_OE),
IMX_PINCTRL_PIN(MX35_PAD_CS0),
IMX_PINCTRL_PIN(MX35_PAD_CS1),
IMX_PINCTRL_PIN(MX35_PAD_CS2),
IMX_PINCTRL_PIN(MX35_PAD_CS3),
IMX_PINCTRL_PIN(MX35_PAD_CS4),
IMX_PINCTRL_PIN(MX35_PAD_CS5),
IMX_PINCTRL_PIN(MX35_PAD_NF_CE0),
IMX_PINCTRL_PIN(MX35_PAD_LBA),
IMX_PINCTRL_PIN(MX35_PAD_BCLK),
IMX_PINCTRL_PIN(MX35_PAD_RW),
IMX_PINCTRL_PIN(MX35_PAD_NFWE_B),
IMX_PINCTRL_PIN(MX35_PAD_NFRE_B),
IMX_PINCTRL_PIN(MX35_PAD_NFALE),
IMX_PINCTRL_PIN(MX35_PAD_NFCLE),
IMX_PINCTRL_PIN(MX35_PAD_NFWP_B),
IMX_PINCTRL_PIN(MX35_PAD_NFRB),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D8),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D9),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D10),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D11),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D12),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D13),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D14),
IMX_PINCTRL_PIN(MX35_PAD_CSI_D15),
IMX_PINCTRL_PIN(MX35_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX35_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX35_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX35_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX35_PAD_I2C1_CLK),
IMX_PINCTRL_PIN(MX35_PAD_I2C1_DAT),
IMX_PINCTRL_PIN(MX35_PAD_I2C2_CLK),
IMX_PINCTRL_PIN(MX35_PAD_I2C2_DAT),
IMX_PINCTRL_PIN(MX35_PAD_STXD4),
IMX_PINCTRL_PIN(MX35_PAD_SRXD4),
IMX_PINCTRL_PIN(MX35_PAD_SCK4),
IMX_PINCTRL_PIN(MX35_PAD_STXFS4),
IMX_PINCTRL_PIN(MX35_PAD_STXD5),
IMX_PINCTRL_PIN(MX35_PAD_SRXD5),
IMX_PINCTRL_PIN(MX35_PAD_SCK5),
IMX_PINCTRL_PIN(MX35_PAD_STXFS5),
IMX_PINCTRL_PIN(MX35_PAD_SCKR),
IMX_PINCTRL_PIN(MX35_PAD_FSR),
IMX_PINCTRL_PIN(MX35_PAD_HCKR),
IMX_PINCTRL_PIN(MX35_PAD_SCKT),
IMX_PINCTRL_PIN(MX35_PAD_FST),
IMX_PINCTRL_PIN(MX35_PAD_HCKT),
IMX_PINCTRL_PIN(MX35_PAD_TX5_RX0),
IMX_PINCTRL_PIN(MX35_PAD_TX4_RX1),
IMX_PINCTRL_PIN(MX35_PAD_TX3_RX2),
IMX_PINCTRL_PIN(MX35_PAD_TX2_RX3),
IMX_PINCTRL_PIN(MX35_PAD_TX1),
IMX_PINCTRL_PIN(MX35_PAD_TX0),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX35_PAD_CSPI1_SPI_RDY),
IMX_PINCTRL_PIN(MX35_PAD_RXD1),
IMX_PINCTRL_PIN(MX35_PAD_TXD1),
IMX_PINCTRL_PIN(MX35_PAD_RTS1),
IMX_PINCTRL_PIN(MX35_PAD_CTS1),
IMX_PINCTRL_PIN(MX35_PAD_RXD2),
IMX_PINCTRL_PIN(MX35_PAD_TXD2),
IMX_PINCTRL_PIN(MX35_PAD_RTS2),
IMX_PINCTRL_PIN(MX35_PAD_CTS2),
IMX_PINCTRL_PIN(MX35_PAD_USBOTG_PWR),
IMX_PINCTRL_PIN(MX35_PAD_USBOTG_OC),
IMX_PINCTRL_PIN(MX35_PAD_LD0),
IMX_PINCTRL_PIN(MX35_PAD_LD1),
IMX_PINCTRL_PIN(MX35_PAD_LD2),
IMX_PINCTRL_PIN(MX35_PAD_LD3),
IMX_PINCTRL_PIN(MX35_PAD_LD4),
IMX_PINCTRL_PIN(MX35_PAD_LD5),
IMX_PINCTRL_PIN(MX35_PAD_LD6),
IMX_PINCTRL_PIN(MX35_PAD_LD7),
IMX_PINCTRL_PIN(MX35_PAD_LD8),
IMX_PINCTRL_PIN(MX35_PAD_LD9),
IMX_PINCTRL_PIN(MX35_PAD_LD10),
IMX_PINCTRL_PIN(MX35_PAD_LD11),
IMX_PINCTRL_PIN(MX35_PAD_LD12),
IMX_PINCTRL_PIN(MX35_PAD_LD13),
IMX_PINCTRL_PIN(MX35_PAD_LD14),
IMX_PINCTRL_PIN(MX35_PAD_LD15),
IMX_PINCTRL_PIN(MX35_PAD_LD16),
IMX_PINCTRL_PIN(MX35_PAD_LD17),
IMX_PINCTRL_PIN(MX35_PAD_LD18),
IMX_PINCTRL_PIN(MX35_PAD_LD19),
IMX_PINCTRL_PIN(MX35_PAD_LD20),
IMX_PINCTRL_PIN(MX35_PAD_LD21),
IMX_PINCTRL_PIN(MX35_PAD_LD22),
IMX_PINCTRL_PIN(MX35_PAD_LD23),
IMX_PINCTRL_PIN(MX35_PAD_D3_HSYNC),
IMX_PINCTRL_PIN(MX35_PAD_D3_FPSHIFT),
IMX_PINCTRL_PIN(MX35_PAD_D3_DRDY),
IMX_PINCTRL_PIN(MX35_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX35_PAD_D3_VSYNC),
IMX_PINCTRL_PIN(MX35_PAD_D3_REV),
IMX_PINCTRL_PIN(MX35_PAD_D3_CLS),
IMX_PINCTRL_PIN(MX35_PAD_D3_SPL),
IMX_PINCTRL_PIN(MX35_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX35_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX35_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX35_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX35_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX35_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX35_PAD_ATA_CS0),
IMX_PINCTRL_PIN(MX35_PAD_ATA_CS1),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOR),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DIOW),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DMACK),
IMX_PINCTRL_PIN(MX35_PAD_ATA_RESET_B),
IMX_PINCTRL_PIN(MX35_PAD_ATA_IORDY),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA0),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA1),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA2),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA3),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA4),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA5),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA6),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA7),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA8),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA9),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA10),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA11),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA12),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA13),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA14),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DATA15),
IMX_PINCTRL_PIN(MX35_PAD_ATA_INTRQ),
IMX_PINCTRL_PIN(MX35_PAD_ATA_BUFF_EN),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DMARQ),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DA0),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DA1),
IMX_PINCTRL_PIN(MX35_PAD_ATA_DA2),
IMX_PINCTRL_PIN(MX35_PAD_MLB_CLK),
IMX_PINCTRL_PIN(MX35_PAD_MLB_DAT),
IMX_PINCTRL_PIN(MX35_PAD_MLB_SIG),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_CLK),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_CLK),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_DV),
IMX_PINCTRL_PIN(MX35_PAD_FEC_COL),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA0),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA0),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_EN),
IMX_PINCTRL_PIN(MX35_PAD_FEC_MDC),
IMX_PINCTRL_PIN(MX35_PAD_FEC_MDIO),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TX_ERR),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RX_ERR),
IMX_PINCTRL_PIN(MX35_PAD_FEC_CRS),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA1),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA1),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA2),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA2),
IMX_PINCTRL_PIN(MX35_PAD_FEC_RDATA3),
IMX_PINCTRL_PIN(MX35_PAD_FEC_TDATA3),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX35_PAD_RESET_IN_B),
IMX_PINCTRL_PIN(MX35_PAD_POR_B),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE0),
IMX_PINCTRL_PIN(MX35_PAD_BOOT_MODE1),
IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE0),
IMX_PINCTRL_PIN(MX35_PAD_CLK_MODE1),
IMX_PINCTRL_PIN(MX35_PAD_POWER_FAIL),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE15),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE16),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE17),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE18),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE19),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE20),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE21),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE22),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE23),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE24),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE25),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE26),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE27),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE28),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE29),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE30),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE31),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE32),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE33),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE34),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE35),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE36),
IMX_PINCTRL_PIN(MX35_PAD_SDBA1),
IMX_PINCTRL_PIN(MX35_PAD_SDBA0),
IMX_PINCTRL_PIN(MX35_PAD_SD0),
IMX_PINCTRL_PIN(MX35_PAD_SD1),
IMX_PINCTRL_PIN(MX35_PAD_SD2),
IMX_PINCTRL_PIN(MX35_PAD_SD3),
IMX_PINCTRL_PIN(MX35_PAD_SD4),
IMX_PINCTRL_PIN(MX35_PAD_SD5),
IMX_PINCTRL_PIN(MX35_PAD_SD6),
IMX_PINCTRL_PIN(MX35_PAD_SD7),
IMX_PINCTRL_PIN(MX35_PAD_SD8),
IMX_PINCTRL_PIN(MX35_PAD_SD9),
IMX_PINCTRL_PIN(MX35_PAD_SD10),
IMX_PINCTRL_PIN(MX35_PAD_SD11),
IMX_PINCTRL_PIN(MX35_PAD_SD12),
IMX_PINCTRL_PIN(MX35_PAD_SD13),
IMX_PINCTRL_PIN(MX35_PAD_SD14),
IMX_PINCTRL_PIN(MX35_PAD_SD15),
IMX_PINCTRL_PIN(MX35_PAD_SD16),
IMX_PINCTRL_PIN(MX35_PAD_SD17),
IMX_PINCTRL_PIN(MX35_PAD_SD18),
IMX_PINCTRL_PIN(MX35_PAD_SD19),
IMX_PINCTRL_PIN(MX35_PAD_SD20),
IMX_PINCTRL_PIN(MX35_PAD_SD21),
IMX_PINCTRL_PIN(MX35_PAD_SD22),
IMX_PINCTRL_PIN(MX35_PAD_SD23),
IMX_PINCTRL_PIN(MX35_PAD_SD24),
IMX_PINCTRL_PIN(MX35_PAD_SD25),
IMX_PINCTRL_PIN(MX35_PAD_SD26),
IMX_PINCTRL_PIN(MX35_PAD_SD27),
IMX_PINCTRL_PIN(MX35_PAD_SD28),
IMX_PINCTRL_PIN(MX35_PAD_SD29),
IMX_PINCTRL_PIN(MX35_PAD_SD30),
IMX_PINCTRL_PIN(MX35_PAD_SD31),
IMX_PINCTRL_PIN(MX35_PAD_DQM0),
IMX_PINCTRL_PIN(MX35_PAD_DQM1),
IMX_PINCTRL_PIN(MX35_PAD_DQM2),
IMX_PINCTRL_PIN(MX35_PAD_DQM3),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE37),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE38),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE39),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE40),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE41),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE42),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE43),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE44),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE45),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE46),
IMX_PINCTRL_PIN(MX35_PAD_ECB),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE47),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE48),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE49),
IMX_PINCTRL_PIN(MX35_PAD_RAS),
IMX_PINCTRL_PIN(MX35_PAD_CAS),
IMX_PINCTRL_PIN(MX35_PAD_SDWE),
IMX_PINCTRL_PIN(MX35_PAD_SDCKE0),
IMX_PINCTRL_PIN(MX35_PAD_SDCKE1),
IMX_PINCTRL_PIN(MX35_PAD_SDCLK),
IMX_PINCTRL_PIN(MX35_PAD_SDQS0),
IMX_PINCTRL_PIN(MX35_PAD_SDQS1),
IMX_PINCTRL_PIN(MX35_PAD_SDQS2),
IMX_PINCTRL_PIN(MX35_PAD_SDQS3),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE50),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE51),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE52),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE53),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE54),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE55),
IMX_PINCTRL_PIN(MX35_PAD_D15),
IMX_PINCTRL_PIN(MX35_PAD_D14),
IMX_PINCTRL_PIN(MX35_PAD_D13),
IMX_PINCTRL_PIN(MX35_PAD_D12),
IMX_PINCTRL_PIN(MX35_PAD_D11),
IMX_PINCTRL_PIN(MX35_PAD_D10),
IMX_PINCTRL_PIN(MX35_PAD_D9),
IMX_PINCTRL_PIN(MX35_PAD_D8),
IMX_PINCTRL_PIN(MX35_PAD_D7),
IMX_PINCTRL_PIN(MX35_PAD_D6),
IMX_PINCTRL_PIN(MX35_PAD_D5),
IMX_PINCTRL_PIN(MX35_PAD_D4),
IMX_PINCTRL_PIN(MX35_PAD_D3),
IMX_PINCTRL_PIN(MX35_PAD_D2),
IMX_PINCTRL_PIN(MX35_PAD_D1),
IMX_PINCTRL_PIN(MX35_PAD_D0),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE56),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE57),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE58),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE59),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE60),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE61),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE62),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE63),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE64),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE65),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE66),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE67),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE68),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE69),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE70),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE71),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE72),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE73),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE74),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE75),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE76),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE77),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE78),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE79),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE80),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE81),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE82),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE83),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE84),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE85),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE86),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE87),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE88),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE89),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE90),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE91),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE92),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE93),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE94),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE95),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE96),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE97),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE98),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE99),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE100),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE101),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE102),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE103),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE104),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE105),
IMX_PINCTRL_PIN(MX35_PAD_RTCK),
IMX_PINCTRL_PIN(MX35_PAD_TCK),
IMX_PINCTRL_PIN(MX35_PAD_TMS),
IMX_PINCTRL_PIN(MX35_PAD_TDI),
IMX_PINCTRL_PIN(MX35_PAD_TDO),
IMX_PINCTRL_PIN(MX35_PAD_TRSTB),
IMX_PINCTRL_PIN(MX35_PAD_DE_B),
IMX_PINCTRL_PIN(MX35_PAD_SJC_MOD),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE106),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE107),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE108),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE109),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE110),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE111),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE112),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE113),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE114),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE115),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE116),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE117),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE118),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE119),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE120),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE121),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE122),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE123),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE124),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE125),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE126),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE127),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE128),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE129),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE130),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE131),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE132),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE133),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE134),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE135),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE136),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE137),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE138),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE139),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE140),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE141),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE142),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE143),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE144),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE145),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE146),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE147),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE148),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE149),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE150),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE151),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE152),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE153),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE154),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE155),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE156),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE157),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE158),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE159),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE160),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE161),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE162),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE163),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE164),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE165),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE166),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE167),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE168),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE169),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE170),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE171),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE172),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE173),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE174),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE175),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE176),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE177),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE178),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE179),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE180),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE181),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE182),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE183),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE184),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE185),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE186),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE187),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE188),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE189),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE190),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE191),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE192),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE193),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE194),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE195),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE196),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE197),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE198),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE199),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE200),
IMX_PINCTRL_PIN(MX35_PAD_RESERVE201),
IMX_PINCTRL_PIN(MX35_PAD_EXT_ARMCLK),
IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
};
static const struct imx_pinctrl_soc_info imx35_pinctrl_info = {
.pins = imx35_pinctrl_pads,
.npins = ARRAY_SIZE(imx35_pinctrl_pads),
};
static const struct of_device_id imx35_pinctrl_of_match[] = {
{ .compatible = "fsl,imx35-iomuxc", },
{ /* sentinel */ }
};
static int imx35_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx35_pinctrl_info);
}
static struct platform_driver imx35_pinctrl_driver = {
.driver = {
.name = "imx35-pinctrl",
.of_match_table = imx35_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx35_pinctrl_probe,
};
static int __init imx35_pinctrl_init(void)
{
return platform_driver_register(&imx35_pinctrl_driver);
}
arch_initcall(imx35_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx35.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// Core driver for the imx pin controller
//
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro Ltd.
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinmux.h"
#include "pinctrl-imx.h"
/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
#define IMX_PAD_SION 0x40000000 /* set SION */
static inline const struct group_desc *imx_pinctrl_find_group_by_name(
struct pinctrl_dev *pctldev,
const char *name)
{
const struct group_desc *grp = NULL;
int i;
for (i = 0; i < pctldev->num_groups; i++) {
grp = pinctrl_generic_get_group(pctldev, i);
if (grp && !strcmp(grp->name, name))
break;
}
return grp;
}
static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
struct imx_pin *pin;
int map_num = 1;
int i, j;
/*
* first find the group of this node and check if we need create
* config maps for pins
*/
grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
if (!grp) {
dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
return -EINVAL;
}
if (info->flags & IMX_USE_SCU) {
map_num += grp->num_pins;
} else {
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
map_num++;
}
}
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
kfree(new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
/*
* We only create config maps for SCU pads or MMIO pads that
* are not using the default config(a.k.a IMX_NO_PAD_CTL)
*/
if (!(info->flags & IMX_USE_SCU) &&
(pin->conf.mmio.config & IMX_NO_PAD_CTL))
continue;
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
if (info->flags & IMX_USE_SCU) {
/*
* For SCU case, we set mux and conf together
* in one IPC call
*/
new_map[j].data.configs.configs =
(unsigned long *)&pin->conf.scu;
new_map[j].data.configs.num_configs = 2;
} else {
new_map[j].data.configs.configs =
&pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
}
j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void imx_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops imx_pctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
};
static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
struct imx_pin *pin)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
const struct imx_pin_reg *pin_reg;
unsigned int pin_id;
pin_id = pin->pin;
pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->mux_reg == -1) {
dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
return 0;
}
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~info->mux_mask;
reg |= (pin_mmio->mux_mode << info->mux_shift);
writel(reg, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, reg);
} else {
writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, pin_mmio->mux_mode);
}
/*
* If the select input value begins with 0xff, it's a quirky
* select input and the value should be interpreted as below.
* 31 23 15 7 0
* | 0xff | shift | width | select |
* It's used to work around the problem that the select
* input for some pin is not implemented in the select
* input register but in some general purpose register.
* We encode the select input value, width and shift of
* the bit field into input_val cell of pin function ID
* in device tree, and then decode them here for setting
* up the select input bits in general purpose register.
*/
if (pin_mmio->input_val >> 24 == 0xff) {
u32 val = pin_mmio->input_val;
u8 select = val & 0xff;
u8 width = (val >> 8) & 0xff;
u8 shift = (val >> 16) & 0xff;
u32 mask = ((1 << width) - 1) << shift;
/*
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
val = readl(ipctl->base + pin_mmio->input_reg);
val &= ~mask;
val |= select << shift;
writel(val, ipctl->base + pin_mmio->input_reg);
} else if (pin_mmio->input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
if (ipctl->input_sel_base)
writel(pin_mmio->input_val, ipctl->input_sel_base +
pin_mmio->input_reg);
else
writel(pin_mmio->input_val, ipctl->base +
pin_mmio->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin_mmio->input_reg, pin_mmio->input_val);
}
return 0;
}
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct function_desc *func;
struct group_desc *grp;
struct imx_pin *pin;
unsigned int npins;
int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
* function.
*/
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
npins = grp->num_pins;
dev_dbg(ipctl->dev, "enable function %s group %s\n",
func->name, grp->name);
for (i = 0; i < npins; i++) {
/*
* For IMX_USE_SCU case, we postpone the mux setting
* until config is set as we can set them together
* in one IPC call
*/
pin = &((struct imx_pin *)(grp->data))[i];
if (!(info->flags & IMX_USE_SCU)) {
err = imx_pmx_set_one_pin_mmio(ipctl, pin);
if (err)
return err;
}
}
return 0;
}
struct pinmux_ops imx_pmx_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = imx_pmx_set,
};
static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->conf_reg == -1) {
dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
*config = readl(ipctl->base + pin_reg->conf_reg);
if (info->flags & SHARE_MUX_CONF_REG)
*config &= ~info->mux_mask;
return 0;
}
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return info->imx_pinconf_get(pctldev, pin_id, config);
else
return imx_pinconf_get_mmio(pctldev, pin_id, config);
}
static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
int i;
if (pin_reg->conf_reg == -1) {
dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
info->pins[pin_id].name);
for (i = 0; i < num_configs; i++) {
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->conf_reg);
reg &= info->mux_mask;
reg |= configs[i];
writel(reg, ipctl->base + pin_reg->conf_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->conf_reg, reg);
} else {
writel(configs[i], ipctl->base + pin_reg->conf_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
pin_reg->conf_reg, configs[i]);
}
} /* for each config */
return 0;
}
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return info->imx_pinconf_set(pctldev, pin_id,
configs, num_configs);
else
return imx_pinconf_set_mmio(pctldev, pin_id,
configs, num_configs);
}
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
unsigned long config;
int ret;
if (info->flags & IMX_USE_SCU) {
ret = info->imx_pinconf_get(pctldev, pin_id, &config);
if (ret) {
dev_err(ipctl->dev, "failed to get %s pinconf\n",
pin_get_name(pctldev, pin_id));
seq_puts(s, "N/A");
return;
}
} else {
pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->conf_reg == -1) {
seq_puts(s, "N/A");
return;
}
config = readl(ipctl->base + pin_reg->conf_reg);
}
seq_printf(s, "0x%lx", config);
}
static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
struct group_desc *grp;
unsigned long config;
const char *name;
int i, ret;
if (group >= pctldev->num_groups)
return;
seq_puts(s, "\n");
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return;
for (i = 0; i < grp->num_pins; i++) {
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
name = pin_get_name(pctldev, pin->pin);
ret = imx_pinconf_get(pctldev, pin->pin, &config);
if (ret)
return;
seq_printf(s, " %s: 0x%lx\n", name, config);
}
}
static const struct pinconf_ops imx_pinconf_ops = {
.pin_config_get = imx_pinconf_get,
.pin_config_set = imx_pinconf_set,
.pin_config_dbg_show = imx_pinconf_dbg_show,
.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};
/*
* Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
* and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
*
* PIN_FUNC_ID format:
* Default:
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
* IMX_USE_SCU:
* <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
#define FSL_SCU_PIN_SIZE 12
static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p,
struct device_node *np)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
struct imx_pin_reg *pin_reg;
const __be32 *list = *list_p;
u32 mux_reg, conf_reg;
u32 config;
mux_reg = be32_to_cpu(*list++);
if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
mux_reg = -1;
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
if (!conf_reg)
conf_reg = -1;
}
*pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = &ipctl->pin_regs[*pin_id];
pin->pin = *pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
pin_mmio->input_reg = be32_to_cpu(*list++);
pin_mmio->mux_mode = be32_to_cpu(*list++);
pin_mmio->input_val = be32_to_cpu(*list++);
config = be32_to_cpu(*list++);
/* SION bit is in mux register */
if (config & IMX_PAD_SION)
pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
pin_mmio->config = config & ~IMX_PAD_SION;
*list_p = list;
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
pin_mmio->mux_mode, pin_mmio->config);
}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
struct imx_pinctrl *ipctl,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
if (info->flags & IMX_USE_SCU)
pin_size = FSL_SCU_PIN_SIZE;
else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
/* Initialise group */
grp->name = np->name;
/*
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
* do sanity check and calculate pins number
*
* First try legacy 'fsl,pins' property, then fall back to the
* generic 'pinmux'.
*
* Note: for generic 'pinmux' case, there's no CONFIG part in
* the binding format.
*/
list = of_get_property(np, "fsl,pins", &size);
if (!list) {
list = of_get_property(np, "pinmux", &size);
if (!list) {
dev_err(ipctl->dev,
"no fsl,pins and pins property in node %pOF\n", np);
return -EINVAL;
}
}
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
return -EINVAL;
}
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
GFP_KERNEL);
grp->pins = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(unsigned int),
GFP_KERNEL);
if (!grp->pins || !grp->data)
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (info->flags & IMX_USE_SCU)
info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
pin, &list);
else
imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
pin, &list, np);
}
return 0;
}
static int imx_pinctrl_parse_functions(struct device_node *np,
struct imx_pinctrl *ipctl,
u32 index)
{
struct pinctrl_dev *pctl = ipctl->pctl;
struct device_node *child;
struct function_desc *func;
struct group_desc *grp;
const char **group_names;
u32 i;
dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
func = pinmux_generic_get_function(pctl, index);
if (!func)
return -EINVAL;
/* Initialise function */
func->name = np->name;
func->num_group_names = of_get_child_count(np);
if (func->num_group_names == 0) {
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
sizeof(char *), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
i = 0;
for_each_child_of_node(np, child)
group_names[i++] = child->name;
func->group_names = group_names;
i = 0;
for_each_child_of_node(np, child) {
grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
GFP_KERNEL);
if (!grp) {
of_node_put(child);
return -ENOMEM;
}
mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_group_tree,
ipctl->group_index++, grp);
mutex_unlock(&ipctl->mutex);
imx_pinctrl_parse_groups(child, grp, ipctl, i++);
}
return 0;
}
/*
* Check if the DT contains pins in the direct child nodes. This indicates the
* newer DT format to store pins. This function returns true if the first found
* fsl,pins property is in a child of np. Otherwise false is returned.
*/
static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
{
struct device_node *function_np;
struct device_node *pinctrl_np;
for_each_child_of_node(np, function_np) {
if (of_property_read_bool(function_np, "fsl,pins")) {
of_node_put(function_np);
return true;
}
for_each_child_of_node(function_np, pinctrl_np) {
if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
of_node_put(pinctrl_np);
of_node_put(function_np);
return false;
}
}
}
return true;
}
static int imx_pinctrl_probe_dt(struct platform_device *pdev,
struct imx_pinctrl *ipctl)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct pinctrl_dev *pctl = ipctl->pctl;
u32 nfuncs = 0;
u32 i = 0;
bool flat_funcs;
if (!np)
return -ENODEV;
flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
if (flat_funcs) {
nfuncs = 1;
} else {
nfuncs = of_get_child_count(np);
if (nfuncs == 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
}
for (i = 0; i < nfuncs; i++) {
struct function_desc *function;
function = devm_kzalloc(&pdev->dev, sizeof(*function),
GFP_KERNEL);
if (!function)
return -ENOMEM;
mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_function_tree, i, function);
mutex_unlock(&ipctl->mutex);
}
pctl->num_functions = nfuncs;
ipctl->group_index = 0;
if (flat_funcs) {
pctl->num_groups = of_get_child_count(np);
} else {
pctl->num_groups = 0;
for_each_child_of_node(np, child)
pctl->num_groups += of_get_child_count(child);
}
if (flat_funcs) {
imx_pinctrl_parse_functions(np, ipctl, 0);
} else {
i = 0;
for_each_child_of_node(np, child)
imx_pinctrl_parse_functions(child, ipctl, i++);
}
return 0;
}
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info)
{
struct regmap_config config = { .name = "gpr" };
struct device_node *dev_np = pdev->dev.of_node;
struct pinctrl_desc *imx_pinctrl_desc;
struct device_node *np;
struct imx_pinctrl *ipctl;
struct regmap *gpr;
int ret, i;
if (!info || !info->pins || !info->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
if (info->gpr_compatible) {
gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
if (!IS_ERR(gpr))
regmap_attach_dev(&pdev->dev, gpr, &config);
}
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
return -ENOMEM;
if (!(info->flags & IMX_USE_SCU)) {
ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
sizeof(*ipctl->pin_regs),
GFP_KERNEL);
if (!ipctl->pin_regs)
return -ENOMEM;
for (i = 0; i < info->npins; i++) {
ipctl->pin_regs[i].mux_reg = -1;
ipctl->pin_regs[i].conf_reg = -1;
}
ipctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
if (of_property_read_bool(dev_np, "fsl,input-sel")) {
np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
if (!np) {
dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
return -EINVAL;
}
ipctl->input_sel_base = of_iomap(np, 0);
of_node_put(np);
if (!ipctl->input_sel_base) {
dev_err(&pdev->dev,
"iomuxc input select base address not found\n");
return -ENOMEM;
}
}
}
imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
GFP_KERNEL);
if (!imx_pinctrl_desc)
return -ENOMEM;
imx_pinctrl_desc->name = dev_name(&pdev->dev);
imx_pinctrl_desc->pins = info->pins;
imx_pinctrl_desc->npins = info->npins;
imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
imx_pinctrl_desc->pmxops = &imx_pmx_ops;
imx_pinctrl_desc->confops = &imx_pinconf_ops;
imx_pinctrl_desc->owner = THIS_MODULE;
/* platform specific callback */
imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
mutex_init(&ipctl->mutex);
ipctl->info = info;
ipctl->dev = &pdev->dev;
platform_set_drvdata(pdev, ipctl);
ret = devm_pinctrl_register_and_init(&pdev->dev,
imx_pinctrl_desc, ipctl,
&ipctl->pctl);
if (ret) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return ret;
}
ret = imx_pinctrl_probe_dt(pdev, ipctl);
if (ret) {
dev_err(&pdev->dev, "fail to probe dt properties\n");
return ret;
}
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
return pinctrl_enable(ipctl->pctl);
}
EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_sleep(ipctl->pctl);
}
static int __maybe_unused imx_pinctrl_resume(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_default(ipctl->pctl);
}
const struct dev_pm_ops imx_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
imx_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
MODULE_AUTHOR("Dong Aisheng <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2016 Freescale Semiconductor, Inc.
// Copyright (C) 2017 NXP
//
// Author: Dong Aisheng <[email protected]>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx7ulp_pads {
IMX7ULP_PAD_PTC0 = 0,
IMX7ULP_PAD_PTC1,
IMX7ULP_PAD_PTC2,
IMX7ULP_PAD_PTC3,
IMX7ULP_PAD_PTC4,
IMX7ULP_PAD_PTC5,
IMX7ULP_PAD_PTC6,
IMX7ULP_PAD_PTC7,
IMX7ULP_PAD_PTC8,
IMX7ULP_PAD_PTC9,
IMX7ULP_PAD_PTC10,
IMX7ULP_PAD_PTC11,
IMX7ULP_PAD_PTC12,
IMX7ULP_PAD_PTC13,
IMX7ULP_PAD_PTC14,
IMX7ULP_PAD_PTC15,
IMX7ULP_PAD_PTC16,
IMX7ULP_PAD_PTC17,
IMX7ULP_PAD_PTC18,
IMX7ULP_PAD_PTC19,
IMX7ULP_PAD_RESERVE0,
IMX7ULP_PAD_RESERVE1,
IMX7ULP_PAD_RESERVE2,
IMX7ULP_PAD_RESERVE3,
IMX7ULP_PAD_RESERVE4,
IMX7ULP_PAD_RESERVE5,
IMX7ULP_PAD_RESERVE6,
IMX7ULP_PAD_RESERVE7,
IMX7ULP_PAD_RESERVE8,
IMX7ULP_PAD_RESERVE9,
IMX7ULP_PAD_RESERVE10,
IMX7ULP_PAD_RESERVE11,
IMX7ULP_PAD_PTD0,
IMX7ULP_PAD_PTD1,
IMX7ULP_PAD_PTD2,
IMX7ULP_PAD_PTD3,
IMX7ULP_PAD_PTD4,
IMX7ULP_PAD_PTD5,
IMX7ULP_PAD_PTD6,
IMX7ULP_PAD_PTD7,
IMX7ULP_PAD_PTD8,
IMX7ULP_PAD_PTD9,
IMX7ULP_PAD_PTD10,
IMX7ULP_PAD_PTD11,
IMX7ULP_PAD_RESERVE12,
IMX7ULP_PAD_RESERVE13,
IMX7ULP_PAD_RESERVE14,
IMX7ULP_PAD_RESERVE15,
IMX7ULP_PAD_RESERVE16,
IMX7ULP_PAD_RESERVE17,
IMX7ULP_PAD_RESERVE18,
IMX7ULP_PAD_RESERVE19,
IMX7ULP_PAD_RESERVE20,
IMX7ULP_PAD_RESERVE21,
IMX7ULP_PAD_RESERVE22,
IMX7ULP_PAD_RESERVE23,
IMX7ULP_PAD_RESERVE24,
IMX7ULP_PAD_RESERVE25,
IMX7ULP_PAD_RESERVE26,
IMX7ULP_PAD_RESERVE27,
IMX7ULP_PAD_RESERVE28,
IMX7ULP_PAD_RESERVE29,
IMX7ULP_PAD_RESERVE30,
IMX7ULP_PAD_RESERVE31,
IMX7ULP_PAD_PTE0,
IMX7ULP_PAD_PTE1,
IMX7ULP_PAD_PTE2,
IMX7ULP_PAD_PTE3,
IMX7ULP_PAD_PTE4,
IMX7ULP_PAD_PTE5,
IMX7ULP_PAD_PTE6,
IMX7ULP_PAD_PTE7,
IMX7ULP_PAD_PTE8,
IMX7ULP_PAD_PTE9,
IMX7ULP_PAD_PTE10,
IMX7ULP_PAD_PTE11,
IMX7ULP_PAD_PTE12,
IMX7ULP_PAD_PTE13,
IMX7ULP_PAD_PTE14,
IMX7ULP_PAD_PTE15,
IMX7ULP_PAD_RESERVE32,
IMX7ULP_PAD_RESERVE33,
IMX7ULP_PAD_RESERVE34,
IMX7ULP_PAD_RESERVE35,
IMX7ULP_PAD_RESERVE36,
IMX7ULP_PAD_RESERVE37,
IMX7ULP_PAD_RESERVE38,
IMX7ULP_PAD_RESERVE39,
IMX7ULP_PAD_RESERVE40,
IMX7ULP_PAD_RESERVE41,
IMX7ULP_PAD_RESERVE42,
IMX7ULP_PAD_RESERVE43,
IMX7ULP_PAD_RESERVE44,
IMX7ULP_PAD_RESERVE45,
IMX7ULP_PAD_RESERVE46,
IMX7ULP_PAD_RESERVE47,
IMX7ULP_PAD_PTF0,
IMX7ULP_PAD_PTF1,
IMX7ULP_PAD_PTF2,
IMX7ULP_PAD_PTF3,
IMX7ULP_PAD_PTF4,
IMX7ULP_PAD_PTF5,
IMX7ULP_PAD_PTF6,
IMX7ULP_PAD_PTF7,
IMX7ULP_PAD_PTF8,
IMX7ULP_PAD_PTF9,
IMX7ULP_PAD_PTF10,
IMX7ULP_PAD_PTF11,
IMX7ULP_PAD_PTF12,
IMX7ULP_PAD_PTF13,
IMX7ULP_PAD_PTF14,
IMX7ULP_PAD_PTF15,
IMX7ULP_PAD_PTF16,
IMX7ULP_PAD_PTF17,
IMX7ULP_PAD_PTF18,
IMX7ULP_PAD_PTF19,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
};
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
else
reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.pins = imx7ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
};
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7ulp-iomuxc1", },
{ /* sentinel */ }
};
static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
}
static struct platform_driver imx7ulp_pinctrl_driver = {
.driver = {
.name = "imx7ulp-pinctrl",
.of_match_table = imx7ulp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx7ulp_pinctrl_probe,
};
static int __init imx7ulp_pinctrl_init(void)
{
return platform_driver_register(&imx7ulp_pinctrl_driver);
}
arch_initcall(imx7ulp_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
|
// SPDX-License-Identifier: GPL-2.0+
//
// imx50 pinctrl driver based on imx pinmux core
//
// Copyright (C) 2013 Greg Ungerer <[email protected]>
// Copyright (C) 2012 Freescale Semiconductor, Inc.
// Copyright (C) 2012 Linaro, Inc.
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx50_pads {
MX50_PAD_RESERVE0 = 0,
MX50_PAD_RESERVE1 = 1,
MX50_PAD_RESERVE2 = 2,
MX50_PAD_RESERVE3 = 3,
MX50_PAD_RESERVE4 = 4,
MX50_PAD_RESERVE5 = 5,
MX50_PAD_RESERVE6 = 6,
MX50_PAD_RESERVE7 = 7,
MX50_PAD_KEY_COL0 = 8,
MX50_PAD_KEY_ROW0 = 9,
MX50_PAD_KEY_COL1 = 10,
MX50_PAD_KEY_ROW1 = 11,
MX50_PAD_KEY_COL2 = 12,
MX50_PAD_KEY_ROW2 = 13,
MX50_PAD_KEY_COL3 = 14,
MX50_PAD_KEY_ROW3 = 15,
MX50_PAD_I2C1_SCL = 16,
MX50_PAD_I2C1_SDA = 17,
MX50_PAD_I2C2_SCL = 18,
MX50_PAD_I2C2_SDA = 19,
MX50_PAD_I2C3_SCL = 20,
MX50_PAD_I2C3_SDA = 21,
MX50_PAD_PWM1 = 22,
MX50_PAD_PWM2 = 23,
MX50_PAD_0WIRE = 24,
MX50_PAD_EPITO = 25,
MX50_PAD_WDOG = 26,
MX50_PAD_SSI_TXFS = 27,
MX50_PAD_SSI_TXC = 28,
MX50_PAD_SSI_TXD = 29,
MX50_PAD_SSI_RXD = 30,
MX50_PAD_SSI_RXF = 31,
MX50_PAD_SSI_RXC = 32,
MX50_PAD_UART1_TXD = 33,
MX50_PAD_UART1_RXD = 34,
MX50_PAD_UART1_CTS = 35,
MX50_PAD_UART1_RTS = 36,
MX50_PAD_UART2_TXD = 37,
MX50_PAD_UART2_RXD = 38,
MX50_PAD_UART2_CTS = 39,
MX50_PAD_UART2_RTS = 40,
MX50_PAD_UART3_TXD = 41,
MX50_PAD_UART3_RXD = 42,
MX50_PAD_UART4_TXD = 43,
MX50_PAD_UART4_RXD = 44,
MX50_PAD_CSPI_CLK = 45,
MX50_PAD_CSPI_MOSI = 46,
MX50_PAD_CSPI_MISO = 47,
MX50_PAD_CSPI_SS0 = 48,
MX50_PAD_ECSPI1_CLK = 49,
MX50_PAD_ECSPI1_MOSI = 50,
MX50_PAD_ECSPI1_MISO = 51,
MX50_PAD_ECSPI1_SS0 = 52,
MX50_PAD_ECSPI2_CLK = 53,
MX50_PAD_ECSPI2_MOSI = 54,
MX50_PAD_ECSPI2_MISO = 55,
MX50_PAD_ECSPI2_SS0 = 56,
MX50_PAD_SD1_CLK = 57,
MX50_PAD_SD1_CMD = 58,
MX50_PAD_SD1_D0 = 59,
MX50_PAD_SD1_D1 = 60,
MX50_PAD_SD1_D2 = 61,
MX50_PAD_SD1_D3 = 62,
MX50_PAD_SD2_CLK = 63,
MX50_PAD_SD2_CMD = 64,
MX50_PAD_SD2_D0 = 65,
MX50_PAD_SD2_D1 = 66,
MX50_PAD_SD2_D2 = 67,
MX50_PAD_SD2_D3 = 68,
MX50_PAD_SD2_D4 = 69,
MX50_PAD_SD2_D5 = 70,
MX50_PAD_SD2_D6 = 71,
MX50_PAD_SD2_D7 = 72,
MX50_PAD_SD2_WP = 73,
MX50_PAD_SD2_CD = 74,
MX50_PAD_DISP_D0 = 75,
MX50_PAD_DISP_D1 = 76,
MX50_PAD_DISP_D2 = 77,
MX50_PAD_DISP_D3 = 78,
MX50_PAD_DISP_D4 = 79,
MX50_PAD_DISP_D5 = 80,
MX50_PAD_DISP_D6 = 81,
MX50_PAD_DISP_D7 = 82,
MX50_PAD_DISP_WR = 83,
MX50_PAD_DISP_RD = 84,
MX50_PAD_DISP_RS = 85,
MX50_PAD_DISP_CS = 86,
MX50_PAD_DISP_BUSY = 87,
MX50_PAD_DISP_RESET = 88,
MX50_PAD_SD3_CLK = 89,
MX50_PAD_SD3_CMD = 90,
MX50_PAD_SD3_D0 = 91,
MX50_PAD_SD3_D1 = 92,
MX50_PAD_SD3_D2 = 93,
MX50_PAD_SD3_D3 = 94,
MX50_PAD_SD3_D4 = 95,
MX50_PAD_SD3_D5 = 96,
MX50_PAD_SD3_D6 = 97,
MX50_PAD_SD3_D7 = 98,
MX50_PAD_SD3_WP = 99,
MX50_PAD_DISP_D8 = 100,
MX50_PAD_DISP_D9 = 101,
MX50_PAD_DISP_D10 = 102,
MX50_PAD_DISP_D11 = 103,
MX50_PAD_DISP_D12 = 104,
MX50_PAD_DISP_D13 = 105,
MX50_PAD_DISP_D14 = 106,
MX50_PAD_DISP_D15 = 107,
MX50_PAD_EPDC_D0 = 108,
MX50_PAD_EPDC_D1 = 109,
MX50_PAD_EPDC_D2 = 110,
MX50_PAD_EPDC_D3 = 111,
MX50_PAD_EPDC_D4 = 112,
MX50_PAD_EPDC_D5 = 113,
MX50_PAD_EPDC_D6 = 114,
MX50_PAD_EPDC_D7 = 115,
MX50_PAD_EPDC_D8 = 116,
MX50_PAD_EPDC_D9 = 117,
MX50_PAD_EPDC_D10 = 118,
MX50_PAD_EPDC_D11 = 119,
MX50_PAD_EPDC_D12 = 120,
MX50_PAD_EPDC_D13 = 121,
MX50_PAD_EPDC_D14 = 122,
MX50_PAD_EPDC_D15 = 123,
MX50_PAD_EPDC_GDCLK = 124,
MX50_PAD_EPDC_GDSP = 125,
MX50_PAD_EPDC_GDOE = 126,
MX50_PAD_EPDC_GDRL = 127,
MX50_PAD_EPDC_SDCLK = 128,
MX50_PAD_EPDC_SDOEZ = 129,
MX50_PAD_EPDC_SDOED = 130,
MX50_PAD_EPDC_SDOE = 131,
MX50_PAD_EPDC_SDLE = 132,
MX50_PAD_EPDC_SDCLKN = 133,
MX50_PAD_EPDC_SDSHR = 134,
MX50_PAD_EPDC_PWRCOM = 135,
MX50_PAD_EPDC_PWRSTAT = 136,
MX50_PAD_EPDC_PWRCTRL0 = 137,
MX50_PAD_EPDC_PWRCTRL1 = 138,
MX50_PAD_EPDC_PWRCTRL2 = 139,
MX50_PAD_EPDC_PWRCTRL3 = 140,
MX50_PAD_EPDC_VCOM0 = 141,
MX50_PAD_EPDC_VCOM1 = 142,
MX50_PAD_EPDC_BDR0 = 143,
MX50_PAD_EPDC_BDR1 = 144,
MX50_PAD_EPDC_SDCE0 = 145,
MX50_PAD_EPDC_SDCE1 = 146,
MX50_PAD_EPDC_SDCE2 = 147,
MX50_PAD_EPDC_SDCE3 = 148,
MX50_PAD_EPDC_SDCE4 = 149,
MX50_PAD_EPDC_SDCE5 = 150,
MX50_PAD_EIM_DA0 = 151,
MX50_PAD_EIM_DA1 = 152,
MX50_PAD_EIM_DA2 = 153,
MX50_PAD_EIM_DA3 = 154,
MX50_PAD_EIM_DA4 = 155,
MX50_PAD_EIM_DA5 = 156,
MX50_PAD_EIM_DA6 = 157,
MX50_PAD_EIM_DA7 = 158,
MX50_PAD_EIM_DA8 = 159,
MX50_PAD_EIM_DA9 = 160,
MX50_PAD_EIM_DA10 = 161,
MX50_PAD_EIM_DA11 = 162,
MX50_PAD_EIM_DA12 = 163,
MX50_PAD_EIM_DA13 = 164,
MX50_PAD_EIM_DA14 = 165,
MX50_PAD_EIM_DA15 = 166,
MX50_PAD_EIM_CS2 = 167,
MX50_PAD_EIM_CS1 = 168,
MX50_PAD_EIM_CS0 = 169,
MX50_PAD_EIM_EB0 = 170,
MX50_PAD_EIM_EB1 = 171,
MX50_PAD_EIM_WAIT = 172,
MX50_PAD_EIM_BCLK = 173,
MX50_PAD_EIM_RDY = 174,
MX50_PAD_EIM_OE = 175,
MX50_PAD_EIM_RW = 176,
MX50_PAD_EIM_LBA = 177,
MX50_PAD_EIM_CRE = 178,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
IMX_PINCTRL_PIN(MX50_PAD_PWM1),
IMX_PINCTRL_PIN(MX50_PAD_PWM2),
IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
IMX_PINCTRL_PIN(MX50_PAD_EPITO),
IMX_PINCTRL_PIN(MX50_PAD_WDOG),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
};
static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.pins = imx50_pinctrl_pads,
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
.gpr_compatible = "fsl,imx50-iomuxc-gpr",
};
static const struct of_device_id imx50_pinctrl_of_match[] = {
{ .compatible = "fsl,imx50-iomuxc", },
{ /* sentinel */ }
};
static int imx50_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
}
static struct platform_driver imx50_pinctrl_driver = {
.driver = {
.name = "imx50-pinctrl",
.of_match_table = imx50_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx50_pinctrl_probe,
};
static int __init imx50_pinctrl_init(void)
{
return platform_driver_register(&imx50_pinctrl_driver);
}
arch_initcall(imx50_pinctrl_init);
|
linux-master
|
drivers/pinctrl/freescale/pinctrl-imx50.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* OWL S900 Pinctrl driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <[email protected]>
*
* Copyright (c) 2018 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
#define MFCTL0 (0x0040)
#define MFCTL1 (0x0044)
#define MFCTL2 (0x0048)
#define MFCTL3 (0x004C)
#define PAD_PULLCTL0 (0x0060)
#define PAD_PULLCTL1 (0x0064)
#define PAD_PULLCTL2 (0x0068)
#define PAD_ST0 (0x006C)
#define PAD_ST1 (0x0070)
#define PAD_CTL (0x0074)
#define PAD_DRV0 (0x0080)
#define PAD_DRV1 (0x0084)
#define PAD_DRV2 (0x0088)
#define PAD_SR0 (0x0270)
#define PAD_SR1 (0x0274)
#define PAD_SR2 (0x0278)
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
#define _GPIOD(offset) (76 + (offset))
#define _GPIOE(offset) (106 + (offset))
#define _GPIOF(offset) (138 + (offset))
#define NUM_GPIOS (_GPIOF(7) + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
#define ETH_TXD0 _GPIOA(0)
#define ETH_TXD1 _GPIOA(1)
#define ETH_TXEN _GPIOA(2)
#define ETH_RXER _GPIOA(3)
#define ETH_CRS_DV _GPIOA(4)
#define ETH_RXD1 _GPIOA(5)
#define ETH_RXD0 _GPIOA(6)
#define ETH_REF_CLK _GPIOA(7)
#define ETH_MDC _GPIOA(8)
#define ETH_MDIO _GPIOA(9)
#define SIRQ0 _GPIOA(10)
#define SIRQ1 _GPIOA(11)
#define SIRQ2 _GPIOA(12)
#define I2S_D0 _GPIOA(13)
#define I2S_BCLK0 _GPIOA(14)
#define I2S_LRCLK0 _GPIOA(15)
#define I2S_MCLK0 _GPIOA(16)
#define I2S_D1 _GPIOA(17)
#define I2S_BCLK1 _GPIOA(18)
#define I2S_LRCLK1 _GPIOA(19)
#define I2S_MCLK1 _GPIOA(20)
#define ERAM_A5 _GPIOA(21)
#define ERAM_A6 _GPIOA(22)
#define ERAM_A7 _GPIOA(23)
#define ERAM_A8 _GPIOA(24)
#define ERAM_A9 _GPIOA(25)
#define ERAM_A10 _GPIOA(26)
#define ERAM_A11 _GPIOA(27)
#define SD0_D0 _GPIOA(28)
#define SD0_D1 _GPIOA(29)
#define SD0_D2 _GPIOA(30)
#define SD0_D3 _GPIOA(31)
#define SD1_D0 _GPIOB(0)
#define SD1_D1 _GPIOB(1)
#define SD1_D2 _GPIOB(2)
#define SD1_D3 _GPIOB(3)
#define SD0_CMD _GPIOB(4)
#define SD0_CLK _GPIOB(5)
#define SD1_CMD _GPIOB(6)
#define SD1_CLK _GPIOB(7)
#define SPI0_SCLK _GPIOB(8)
#define SPI0_SS _GPIOB(9)
#define SPI0_MISO _GPIOB(10)
#define SPI0_MOSI _GPIOB(11)
#define UART0_RX _GPIOB(12)
#define UART0_TX _GPIOB(13)
#define UART2_RX _GPIOB(14)
#define UART2_TX _GPIOB(15)
#define UART2_RTSB _GPIOB(16)
#define UART2_CTSB _GPIOB(17)
#define UART4_RX _GPIOB(18)
#define UART4_TX _GPIOB(19)
#define I2C0_SCLK _GPIOB(20)
#define I2C0_SDATA _GPIOB(21)
#define I2C1_SCLK _GPIOB(22)
#define I2C1_SDATA _GPIOB(23)
#define I2C2_SCLK _GPIOB(24)
#define I2C2_SDATA _GPIOB(25)
#define CSI0_DN0 _GPIOB(26)
#define CSI0_DP0 _GPIOB(27)
#define CSI0_DN1 _GPIOB(28)
#define CSI0_DP1 _GPIOB(29)
#define CSI0_CN _GPIOB(30)
#define CSI0_CP _GPIOB(31)
#define CSI0_DN2 _GPIOC(0)
#define CSI0_DP2 _GPIOC(1)
#define CSI0_DN3 _GPIOC(2)
#define CSI0_DP3 _GPIOC(3)
#define SENSOR0_PCLK _GPIOC(4)
#define CSI1_DN0 _GPIOC(5)
#define CSI1_DP0 _GPIOC(6)
#define CSI1_DN1 _GPIOC(7)
#define CSI1_DP1 _GPIOC(8)
#define CSI1_CN _GPIOC(9)
#define CSI1_CP _GPIOC(10)
#define SENSOR0_CKOUT _GPIOC(11)
#define LVDS_OEP _GPIOD(0)
#define LVDS_OEN _GPIOD(1)
#define LVDS_ODP _GPIOD(2)
#define LVDS_ODN _GPIOD(3)
#define LVDS_OCP _GPIOD(4)
#define LVDS_OCN _GPIOD(5)
#define LVDS_OBP _GPIOD(6)
#define LVDS_OBN _GPIOD(7)
#define LVDS_OAP _GPIOD(8)
#define LVDS_OAN _GPIOD(9)
#define LVDS_EEP _GPIOD(10)
#define LVDS_EEN _GPIOD(11)
#define LVDS_EDP _GPIOD(12)
#define LVDS_EDN _GPIOD(13)
#define LVDS_ECP _GPIOD(14)
#define LVDS_ECN _GPIOD(15)
#define LVDS_EBP _GPIOD(16)
#define LVDS_EBN _GPIOD(17)
#define LVDS_EAP _GPIOD(18)
#define LVDS_EAN _GPIOD(19)
#define DSI_DP3 _GPIOD(20)
#define DSI_DN3 _GPIOD(21)
#define DSI_DP1 _GPIOD(22)
#define DSI_DN1 _GPIOD(23)
#define DSI_CP _GPIOD(24)
#define DSI_CN _GPIOD(25)
#define DSI_DP0 _GPIOD(26)
#define DSI_DN0 _GPIOD(27)
#define DSI_DP2 _GPIOD(28)
#define DSI_DN2 _GPIOD(29)
#define NAND0_D0 _GPIOE(0)
#define NAND0_D1 _GPIOE(1)
#define NAND0_D2 _GPIOE(2)
#define NAND0_D3 _GPIOE(3)
#define NAND0_D4 _GPIOE(4)
#define NAND0_D5 _GPIOE(5)
#define NAND0_D6 _GPIOE(6)
#define NAND0_D7 _GPIOE(7)
#define NAND0_DQS _GPIOE(8)
#define NAND0_DQSN _GPIOE(9)
#define NAND0_ALE _GPIOE(10)
#define NAND0_CLE _GPIOE(11)
#define NAND0_CEB0 _GPIOE(12)
#define NAND0_CEB1 _GPIOE(13)
#define NAND0_CEB2 _GPIOE(14)
#define NAND0_CEB3 _GPIOE(15)
#define NAND1_D0 _GPIOE(16)
#define NAND1_D1 _GPIOE(17)
#define NAND1_D2 _GPIOE(18)
#define NAND1_D3 _GPIOE(19)
#define NAND1_D4 _GPIOE(20)
#define NAND1_D5 _GPIOE(21)
#define NAND1_D6 _GPIOE(22)
#define NAND1_D7 _GPIOE(23)
#define NAND1_DQS _GPIOE(24)
#define NAND1_DQSN _GPIOE(25)
#define NAND1_ALE _GPIOE(26)
#define NAND1_CLE _GPIOE(27)
#define NAND1_CEB0 _GPIOE(28)
#define NAND1_CEB1 _GPIOE(29)
#define NAND1_CEB2 _GPIOE(30)
#define NAND1_CEB3 _GPIOE(31)
#define PCM1_IN _GPIOF(0)
#define PCM1_CLK _GPIOF(1)
#define PCM1_SYNC _GPIOF(2)
#define PCM1_OUT _GPIOF(3)
#define UART3_RX _GPIOF(4)
#define UART3_TX _GPIOF(5)
#define UART3_RTSB _GPIOF(6)
#define UART3_CTSB _GPIOF(7)
/* System */
#define SGPIO0 _PIN(0)
#define SGPIO1 _PIN(1)
#define SGPIO2 _PIN(2)
#define SGPIO3 _PIN(3)
#define NUM_PADS (_PIN(3) + 1)
/* Pad names as specified in datasheet */
static const struct pinctrl_pin_desc s900_pads[] = {
PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
PINCTRL_PIN(ETH_TXEN, "eth_txen"),
PINCTRL_PIN(ETH_RXER, "eth_rxer"),
PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
PINCTRL_PIN(ETH_MDC, "eth_mdc"),
PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
PINCTRL_PIN(SIRQ0, "sirq0"),
PINCTRL_PIN(SIRQ1, "sirq1"),
PINCTRL_PIN(SIRQ2, "sirq2"),
PINCTRL_PIN(I2S_D0, "i2s_d0"),
PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
PINCTRL_PIN(I2S_D1, "i2s_d1"),
PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
PINCTRL_PIN(PCM1_IN, "pcm1_in"),
PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
PINCTRL_PIN(ERAM_A5, "eram_a5"),
PINCTRL_PIN(ERAM_A6, "eram_a6"),
PINCTRL_PIN(ERAM_A7, "eram_a7"),
PINCTRL_PIN(ERAM_A8, "eram_a8"),
PINCTRL_PIN(ERAM_A9, "eram_a9"),
PINCTRL_PIN(ERAM_A10, "eram_a10"),
PINCTRL_PIN(ERAM_A11, "eram_a11"),
PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
PINCTRL_PIN(LVDS_EEN, "lvds_een"),
PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
PINCTRL_PIN(SD0_D0, "sd0_d0"),
PINCTRL_PIN(SD0_D1, "sd0_d1"),
PINCTRL_PIN(SD0_D2, "sd0_d2"),
PINCTRL_PIN(SD0_D3, "sd0_d3"),
PINCTRL_PIN(SD1_D0, "sd1_d0"),
PINCTRL_PIN(SD1_D1, "sd1_d1"),
PINCTRL_PIN(SD1_D2, "sd1_d2"),
PINCTRL_PIN(SD1_D3, "sd1_d3"),
PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
PINCTRL_PIN(SD0_CLK, "sd0_clk"),
PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
PINCTRL_PIN(SD1_CLK, "sd1_clk"),
PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
PINCTRL_PIN(SPI0_SS, "spi0_ss"),
PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
PINCTRL_PIN(UART0_RX, "uart0_rx"),
PINCTRL_PIN(UART0_TX, "uart0_tx"),
PINCTRL_PIN(UART2_RX, "uart2_rx"),
PINCTRL_PIN(UART2_TX, "uart2_tx"),
PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
PINCTRL_PIN(UART3_RX, "uart3_rx"),
PINCTRL_PIN(UART3_TX, "uart3_tx"),
PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
PINCTRL_PIN(UART4_RX, "uart4_rx"),
PINCTRL_PIN(UART4_TX, "uart4_tx"),
PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
PINCTRL_PIN(CSI0_DN0, "csi0_dn0"),
PINCTRL_PIN(CSI0_DP0, "csi0_dp0"),
PINCTRL_PIN(CSI0_DN1, "csi0_dn1"),
PINCTRL_PIN(CSI0_DP1, "csi0_dp1"),
PINCTRL_PIN(CSI0_CN, "csi0_cn"),
PINCTRL_PIN(CSI0_CP, "csi0_cp"),
PINCTRL_PIN(CSI0_DN2, "csi0_dn2"),
PINCTRL_PIN(CSI0_DP2, "csi0_dp2"),
PINCTRL_PIN(CSI0_DN3, "csi0_dn3"),
PINCTRL_PIN(CSI0_DP3, "csi0_dp3"),
PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
PINCTRL_PIN(DSI_CP, "dsi_cp"),
PINCTRL_PIN(DSI_CN, "dsi_cn"),
PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
PINCTRL_PIN(CSI1_DN0, "csi1_dn0"),
PINCTRL_PIN(CSI1_DP0, "csi1_dp0"),
PINCTRL_PIN(CSI1_DN1, "csi1_dn1"),
PINCTRL_PIN(CSI1_DP1, "csi1_dp1"),
PINCTRL_PIN(CSI1_CN, "csi1_cn"),
PINCTRL_PIN(CSI1_CP, "csi1_cp"),
PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
PINCTRL_PIN(NAND0_D0, "nand0_d0"),
PINCTRL_PIN(NAND0_D1, "nand0_d1"),
PINCTRL_PIN(NAND0_D2, "nand0_d2"),
PINCTRL_PIN(NAND0_D3, "nand0_d3"),
PINCTRL_PIN(NAND0_D4, "nand0_d4"),
PINCTRL_PIN(NAND0_D5, "nand0_d5"),
PINCTRL_PIN(NAND0_D6, "nand0_d6"),
PINCTRL_PIN(NAND0_D7, "nand0_d7"),
PINCTRL_PIN(NAND0_DQS, "nand0_dqs"),
PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"),
PINCTRL_PIN(NAND0_ALE, "nand0_ale"),
PINCTRL_PIN(NAND0_CLE, "nand0_cle"),
PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"),
PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"),
PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"),
PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"),
PINCTRL_PIN(NAND1_D0, "nand1_d0"),
PINCTRL_PIN(NAND1_D1, "nand1_d1"),
PINCTRL_PIN(NAND1_D2, "nand1_d2"),
PINCTRL_PIN(NAND1_D3, "nand1_d3"),
PINCTRL_PIN(NAND1_D4, "nand1_d4"),
PINCTRL_PIN(NAND1_D5, "nand1_d5"),
PINCTRL_PIN(NAND1_D6, "nand1_d6"),
PINCTRL_PIN(NAND1_D7, "nand1_d7"),
PINCTRL_PIN(NAND1_DQS, "nand1_dqs"),
PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"),
PINCTRL_PIN(NAND1_ALE, "nand1_ale"),
PINCTRL_PIN(NAND1_CLE, "nand1_cle"),
PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"),
PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"),
PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"),
PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"),
PINCTRL_PIN(SGPIO0, "sgpio0"),
PINCTRL_PIN(SGPIO1, "sgpio1"),
PINCTRL_PIN(SGPIO2, "sgpio2"),
PINCTRL_PIN(SGPIO3, "sgpio3")
};
enum s900_pinmux_functions {
S900_MUX_ERAM,
S900_MUX_ETH_RMII,
S900_MUX_ETH_SMII,
S900_MUX_SPI0,
S900_MUX_SPI1,
S900_MUX_SPI2,
S900_MUX_SPI3,
S900_MUX_SENS0,
S900_MUX_UART0,
S900_MUX_UART1,
S900_MUX_UART2,
S900_MUX_UART3,
S900_MUX_UART4,
S900_MUX_UART5,
S900_MUX_UART6,
S900_MUX_I2S0,
S900_MUX_I2S1,
S900_MUX_PCM0,
S900_MUX_PCM1,
S900_MUX_JTAG,
S900_MUX_PWM0,
S900_MUX_PWM1,
S900_MUX_PWM2,
S900_MUX_PWM3,
S900_MUX_PWM4,
S900_MUX_PWM5,
S900_MUX_SD0,
S900_MUX_SD1,
S900_MUX_SD2,
S900_MUX_SD3,
S900_MUX_I2C0,
S900_MUX_I2C1,
S900_MUX_I2C2,
S900_MUX_I2C3,
S900_MUX_I2C4,
S900_MUX_I2C5,
S900_MUX_LVDS,
S900_MUX_USB20,
S900_MUX_USB30,
S900_MUX_GPU,
S900_MUX_MIPI_CSI0,
S900_MUX_MIPI_CSI1,
S900_MUX_MIPI_DSI,
S900_MUX_NAND0,
S900_MUX_NAND1,
S900_MUX_SPDIF,
S900_MUX_SIRQ0,
S900_MUX_SIRQ1,
S900_MUX_SIRQ2,
S900_MUX_AUX_START,
S900_MUX_MAX,
S900_MUX_RESERVED
};
/* mfp0_22 */
static unsigned int lvds_oxx_uart4_mfp_pads[] = { LVDS_OAP, LVDS_OAN };
static unsigned int lvds_oxx_uart4_mfp_funcs[] = { S900_MUX_ERAM,
S900_MUX_UART4 };
/* mfp0_21_20 */
static unsigned int rmii_mdc_mfp_pads[] = { ETH_MDC };
static unsigned int rmii_mdc_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_PWM2,
S900_MUX_UART2,
S900_MUX_RESERVED };
static unsigned int rmii_mdio_mfp_pads[] = { ETH_MDIO };
static unsigned int rmii_mdio_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_PWM3,
S900_MUX_UART2,
S900_MUX_RESERVED };
/* mfp0_19 */
static unsigned int sirq0_mfp_pads[] = { SIRQ0 };
static unsigned int sirq0_mfp_funcs[] = { S900_MUX_SIRQ0,
S900_MUX_PWM0 };
static unsigned int sirq1_mfp_pads[] = { SIRQ1 };
static unsigned int sirq1_mfp_funcs[] = { S900_MUX_SIRQ1,
S900_MUX_PWM1 };
/* mfp0_18_16 */
static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };
static unsigned int rmii_txd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_ETH_SMII,
S900_MUX_SPI2,
S900_MUX_UART6,
S900_MUX_SENS0,
S900_MUX_PWM0 };
static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };
static unsigned int rmii_txd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_ETH_SMII,
S900_MUX_SPI2,
S900_MUX_UART6,
S900_MUX_SENS0,
S900_MUX_PWM1 };
/* mfp0_15_13 */
static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };
static unsigned int rmii_txen_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_UART2,
S900_MUX_SPI3,
S900_MUX_RESERVED,
S900_MUX_RESERVED,
S900_MUX_PWM2,
S900_MUX_SENS0 };
static unsigned int rmii_rxer_mfp_pads[] = { ETH_RXER };
static unsigned int rmii_rxer_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_UART2,
S900_MUX_SPI3,
S900_MUX_RESERVED,
S900_MUX_RESERVED,
S900_MUX_PWM3,
S900_MUX_SENS0 };
/* mfp0_12_11 */
static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };
static unsigned int rmii_crs_dv_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_ETH_SMII,
S900_MUX_SPI2,
S900_MUX_UART4 };
/* mfp0_10_8 */
static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };
static unsigned int rmii_rxd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_UART2,
S900_MUX_SPI3,
S900_MUX_RESERVED,
S900_MUX_UART5,
S900_MUX_PWM0,
S900_MUX_SENS0 };
static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };
static unsigned int rmii_rxd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_UART2,
S900_MUX_SPI3,
S900_MUX_RESERVED,
S900_MUX_UART5,
S900_MUX_PWM1,
S900_MUX_SENS0 };
/* mfp0_7_6 */
static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
static unsigned int rmii_ref_clk_mfp_funcs[] = { S900_MUX_ETH_RMII,
S900_MUX_UART4,
S900_MUX_SPI2,
S900_MUX_RESERVED };
/* mfp0_5 */
static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
static unsigned int i2s_d0_mfp_funcs[] = { S900_MUX_I2S0,
S900_MUX_PCM0 };
static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
static unsigned int i2s_d1_mfp_funcs[] = { S900_MUX_I2S1,
S900_MUX_PCM0 };
/* mfp0_4_3 */
static unsigned int i2s_lr_m_clk0_mfp_pads[] = { I2S_LRCLK0,
I2S_MCLK0 };
static unsigned int i2s_lr_m_clk0_mfp_funcs[] = { S900_MUX_I2S0,
S900_MUX_PCM0,
S900_MUX_PCM1,
S900_MUX_RESERVED };
/* mfp0_2 */
static unsigned int i2s_bclk0_mfp_pads[] = { I2S_BCLK0 };
static unsigned int i2s_bclk0_mfp_funcs[] = { S900_MUX_I2S0,
S900_MUX_PCM0 };
static unsigned int i2s_bclk1_mclk1_mfp_pads[] = { I2S_BCLK1,
I2S_LRCLK1,
I2S_MCLK1 };
static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1,
S900_MUX_PCM0 };
/* mfp0_1_0 */
static unsigned int pcm1_in_out_mfp_pads[] = { PCM1_IN,
PCM1_OUT };
static unsigned int pcm1_in_out_mfp_funcs[] = { S900_MUX_PCM1,
S900_MUX_SPI1,
S900_MUX_I2C3,
S900_MUX_UART4 };
static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
static unsigned int pcm1_clk_mfp_funcs[] = { S900_MUX_PCM1,
S900_MUX_SPI1,
S900_MUX_PWM4,
S900_MUX_UART4 };
static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
static unsigned int pcm1_sync_mfp_funcs[] = { S900_MUX_PCM1,
S900_MUX_SPI1,
S900_MUX_PWM5,
S900_MUX_UART4 };
/* mfp1_31_29 */
static unsigned int eram_a5_mfp_pads[] = { ERAM_A5 };
static unsigned int eram_a5_mfp_funcs[] = { S900_MUX_UART4,
S900_MUX_JTAG,
S900_MUX_ERAM,
S900_MUX_PWM0,
S900_MUX_RESERVED,
S900_MUX_SENS0 };
static unsigned int eram_a6_mfp_pads[] = { ERAM_A6 };
static unsigned int eram_a6_mfp_funcs[] = { S900_MUX_UART4,
S900_MUX_JTAG,
S900_MUX_ERAM,
S900_MUX_PWM1,
S900_MUX_RESERVED,
S900_MUX_SENS0,
};
static unsigned int eram_a7_mfp_pads[] = { ERAM_A7 };
static unsigned int eram_a7_mfp_funcs[] = { S900_MUX_RESERVED,
S900_MUX_JTAG,
S900_MUX_ERAM,
S900_MUX_RESERVED,
S900_MUX_RESERVED,
S900_MUX_SENS0 };
/* mfp1_28_26 */
static unsigned int eram_a8_mfp_pads[] = { ERAM_A8 };
static unsigned int eram_a8_mfp_funcs[] = { S900_MUX_RESERVED,
S900_MUX_JTAG,
S900_MUX_ERAM,
S900_MUX_PWM1,
S900_MUX_RESERVED,
S900_MUX_SENS0 };
static unsigned int eram_a9_mfp_pads[] = { ERAM_A9 };
static unsigned int eram_a9_mfp_funcs[] = { S900_MUX_USB20,
S900_MUX_UART5,
S900_MUX_ERAM,
S900_MUX_PWM2,
S900_MUX_RESERVED,
S900_MUX_SENS0 };
static unsigned int eram_a10_mfp_pads[] = { ERAM_A10 };
static unsigned int eram_a10_mfp_funcs[] = { S900_MUX_USB30,
S900_MUX_JTAG,
S900_MUX_ERAM,
S900_MUX_PWM3,
S900_MUX_RESERVED,
S900_MUX_SENS0,
S900_MUX_RESERVED,
S900_MUX_RESERVED };
/* mfp1_25_23 */
static unsigned int eram_a11_mfp_pads[] = { ERAM_A11 };
static unsigned int eram_a11_mfp_funcs[] = { S900_MUX_RESERVED,
S900_MUX_RESERVED,
S900_MUX_ERAM,
S900_MUX_PWM2,
S900_MUX_UART5,
S900_MUX_RESERVED,
S900_MUX_SENS0,
S900_MUX_RESERVED };
/* mfp1_22 */
static unsigned int lvds_oep_odn_mfp_pads[] = { LVDS_OEP,
LVDS_OEN,
LVDS_ODP,
LVDS_ODN };
static unsigned int lvds_oep_odn_mfp_funcs[] = { S900_MUX_LVDS,
S900_MUX_UART2 };
static unsigned int lvds_ocp_obn_mfp_pads[] = { LVDS_OCP,
LVDS_OCN,
LVDS_OBP,
LVDS_OBN };
static unsigned int lvds_ocp_obn_mfp_funcs[] = { S900_MUX_LVDS,
S900_MUX_PCM1 };
static unsigned int lvds_oap_oan_mfp_pads[] = { LVDS_OAP,
LVDS_OAN };
static unsigned int lvds_oap_oan_mfp_funcs[] = { S900_MUX_LVDS,
S900_MUX_ERAM };
/* mfp1_21 */
static unsigned int lvds_e_mfp_pads[] = { LVDS_EEP,
LVDS_EEN,
LVDS_EDP,
LVDS_EDN,
LVDS_ECP,
LVDS_ECN,
LVDS_EBP,
LVDS_EBN,
LVDS_EAP,
LVDS_EAN };
static unsigned int lvds_e_mfp_funcs[] = { S900_MUX_LVDS,
S900_MUX_ERAM };
/* mfp1_5_4 */
static unsigned int spi0_sclk_mosi_mfp_pads[] = { SPI0_SCLK,
SPI0_MOSI };
static unsigned int spi0_sclk_mosi_mfp_funcs[] = { S900_MUX_SPI0,
S900_MUX_ERAM,
S900_MUX_I2C3,
S900_MUX_PCM0 };
/* mfp1_3_1 */
static unsigned int spi0_ss_mfp_pads[] = { SPI0_SS };
static unsigned int spi0_ss_mfp_funcs[] = { S900_MUX_SPI0,
S900_MUX_ERAM,
S900_MUX_I2S1,
S900_MUX_PCM1,
S900_MUX_PCM0,
S900_MUX_PWM4 };
static unsigned int spi0_miso_mfp_pads[] = { SPI0_MISO };
static unsigned int spi0_miso_mfp_funcs[] = { S900_MUX_SPI0,
S900_MUX_ERAM,
S900_MUX_I2S1,
S900_MUX_PCM1,
S900_MUX_PCM0,
S900_MUX_PWM5 };
/* mfp2_23 */
static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
static unsigned int uart2_rtsb_mfp_funcs[] = { S900_MUX_UART2,
S900_MUX_UART0 };
/* mfp2_22 */
static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
static unsigned int uart2_ctsb_mfp_funcs[] = { S900_MUX_UART2,
S900_MUX_UART0 };
/* mfp2_21 */
static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
static unsigned int uart3_rtsb_mfp_funcs[] = { S900_MUX_UART3,
S900_MUX_UART5 };
/* mfp2_20 */
static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
static unsigned int uart3_ctsb_mfp_funcs[] = { S900_MUX_UART3,
S900_MUX_UART5 };
/* mfp2_19_17 */
static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
static unsigned int sd0_d0_mfp_funcs[] = { S900_MUX_SD0,
S900_MUX_ERAM,
S900_MUX_RESERVED,
S900_MUX_JTAG,
S900_MUX_UART2,
S900_MUX_UART5,
S900_MUX_GPU };
/* mfp2_16_14 */
static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
static unsigned int sd0_d1_mfp_funcs[] = { S900_MUX_SD0,
S900_MUX_ERAM,
S900_MUX_GPU,
S900_MUX_RESERVED,
S900_MUX_UART2,
S900_MUX_UART5 };
/* mfp_13_11 */
static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
SD0_D3 };
static unsigned int sd0_d2_d3_mfp_funcs[] = { S900_MUX_SD0,
S900_MUX_ERAM,
S900_MUX_RESERVED,
S900_MUX_JTAG,
S900_MUX_UART2,
S900_MUX_UART1,
S900_MUX_GPU };
/* mfp2_10_9 */
static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,
SD1_D2, SD1_D3 };
static unsigned int sd1_d0_d3_mfp_funcs[] = { S900_MUX_SD1,
S900_MUX_ERAM };
/* mfp2_8_7 */
static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
static unsigned int sd0_cmd_mfp_funcs[] = { S900_MUX_SD0,
S900_MUX_ERAM,
S900_MUX_GPU,
S900_MUX_JTAG };
/* mfp2_6_5 */
static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
static unsigned int sd0_clk_mfp_funcs[] = { S900_MUX_SD0,
S900_MUX_ERAM,
S900_MUX_JTAG,
S900_MUX_GPU };
/* mfp2_4_3 */
static unsigned int sd1_cmd_clk_mfp_pads[] = { SD1_CMD, SD1_CLK };
static unsigned int sd1_cmd_clk_mfp_funcs[] = { S900_MUX_SD1,
S900_MUX_ERAM };
/* mfp2_2_0 */
static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
static unsigned int uart0_rx_mfp_funcs[] = { S900_MUX_UART0,
S900_MUX_UART2,
S900_MUX_SPI1,
S900_MUX_I2C5,
S900_MUX_PCM1,
S900_MUX_I2S1 };
/* mfp3_27 */
static unsigned int nand0_d0_ceb3_mfp_pads[] = { NAND0_D0, NAND0_D1,
NAND0_D2, NAND0_D3,
NAND0_D4, NAND0_D5,
NAND0_D6, NAND0_D7,
NAND0_DQSN, NAND0_CEB3 };
static unsigned int nand0_d0_ceb3_mfp_funcs[] = { S900_MUX_NAND0,
S900_MUX_SD2 };
/* mfp3_21_19 */
static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
static unsigned int uart0_tx_mfp_funcs[] = { S900_MUX_UART0,
S900_MUX_UART2,
S900_MUX_SPI1,
S900_MUX_I2C5,
S900_MUX_SPDIF,
S900_MUX_PCM1,
S900_MUX_I2S1 };
/* mfp3_18_16 */
static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, I2C0_SDATA };
static unsigned int i2c0_mfp_funcs[] = { S900_MUX_I2C0,
S900_MUX_UART2,
S900_MUX_I2C1,
S900_MUX_UART1,
S900_MUX_SPI1 };
/* mfp3_15 */
static unsigned int csi0_cn_cp_mfp_pads[] = { CSI0_CN, CSI0_CP };
static unsigned int csi0_cn_cp_mfp_funcs[] = { S900_MUX_SENS0,
S900_MUX_SENS0 };
/* mfp3_14 */
static unsigned int csi0_dn0_dp3_mfp_pads[] = { CSI0_DN0, CSI0_DP0,
CSI0_DN1, CSI0_DP1,
CSI0_CN, CSI0_CP,
CSI0_DP2, CSI0_DN2,
CSI0_DN3, CSI0_DP3 };
static unsigned int csi0_dn0_dp3_mfp_funcs[] = { S900_MUX_MIPI_CSI0,
S900_MUX_SENS0 };
/* mfp3_13 */
static unsigned int csi1_dn0_cp_mfp_pads[] = { CSI1_DN0, CSI1_DP0,
CSI1_DN1, CSI1_DP1,
CSI1_CN, CSI1_CP };
static unsigned int csi1_dn0_cp_mfp_funcs[] = { S900_MUX_MIPI_CSI1,
S900_MUX_SENS0 };
/* mfp3_12_dsi */
static unsigned int dsi_dp3_dn1_mfp_pads[] = { DSI_DP3, DSI_DN2,
DSI_DP1, DSI_DN1 };
static unsigned int dsi_dp3_dn1_mfp_funcs[] = { S900_MUX_MIPI_DSI,
S900_MUX_UART2 };
static unsigned int dsi_cp_dn0_mfp_pads[] = { DSI_CP, DSI_CN,
DSI_DP0, DSI_DN0 };
static unsigned int dsi_cp_dn0_mfp_funcs[] = { S900_MUX_MIPI_DSI,
S900_MUX_PCM1 };
static unsigned int dsi_dp2_dn2_mfp_pads[] = { DSI_DP2, DSI_DN2 };
static unsigned int dsi_dp2_dn2_mfp_funcs[] = { S900_MUX_MIPI_DSI,
S900_MUX_UART4 };
/* mfp3_11 */
static unsigned int nand1_d0_ceb1_mfp_pads[] = { NAND1_D0, NAND1_D1,
NAND1_D2, NAND1_D3,
NAND1_D4, NAND1_D5,
NAND1_D6, NAND1_D7,
NAND1_DQSN, NAND1_CEB1 };
static unsigned int nand1_d0_ceb1_mfp_funcs[] = { S900_MUX_NAND1,
S900_MUX_SD3 };
/* mfp3_10 */
static unsigned int nand1_ceb3_mfp_pads[] = { NAND1_CEB3 };
static unsigned int nand1_ceb3_mfp_funcs[] = { S900_MUX_NAND1,
S900_MUX_PWM0 };
static unsigned int nand1_ceb0_mfp_pads[] = { NAND1_CEB0 };
static unsigned int nand1_ceb0_mfp_funcs[] = { S900_MUX_NAND1,
S900_MUX_PWM1 };
/* mfp3_9 */
static unsigned int csi1_dn0_dp0_mfp_pads[] = { CSI1_DN0, CSI1_DP0 };
static unsigned int csi1_dn0_dp0_mfp_funcs[] = { S900_MUX_SENS0,
S900_MUX_SENS0 };
/* mfp3_8 */
static unsigned int uart4_rx_tx_mfp_pads[] = { UART4_RX, UART4_TX };
static unsigned int uart4_rx_tx_mfp_funcs[] = { S900_MUX_UART4,
S900_MUX_I2C4 };
/* PADDRV group data */
/* drv0 */
static unsigned int sgpio3_drv_pads[] = { SGPIO3 };
static unsigned int sgpio2_drv_pads[] = { SGPIO2 };
static unsigned int sgpio1_drv_pads[] = { SGPIO1 };
static unsigned int sgpio0_drv_pads[] = { SGPIO0 };
static unsigned int rmii_tx_d0_d1_drv_pads[] = { ETH_TXD0, ETH_TXD1 };
static unsigned int rmii_txen_rxer_drv_pads[] = { ETH_TXEN, ETH_RXER };
static unsigned int rmii_crs_dv_drv_pads[] = { ETH_CRS_DV };
static unsigned int rmii_rx_d1_d0_drv_pads[] = { ETH_RXD1, ETH_RXD0 };
static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
static unsigned int rmii_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
static unsigned int sirq_0_1_drv_pads[] = { SIRQ0, SIRQ1 };
static unsigned int sirq2_drv_pads[] = { SIRQ2 };
static unsigned int i2s_d0_d1_drv_pads[] = { I2S_D0, I2S_D1 };
static unsigned int i2s_lr_m_clk0_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
static unsigned int i2s_blk1_mclk1_drv_pads[] = { I2S_BCLK0, I2S_BCLK1,
I2S_LRCLK1, I2S_MCLK1 };
static unsigned int pcm1_in_out_drv_pads[] = { PCM1_IN, PCM1_CLK,
PCM1_SYNC, PCM1_OUT };
/* drv1 */
static unsigned int lvds_oap_oan_drv_pads[] = { LVDS_OAP, LVDS_OAN };
static unsigned int lvds_oep_odn_drv_pads[] = { LVDS_OEP, LVDS_OEN,
LVDS_ODP, LVDS_ODN };
static unsigned int lvds_ocp_obn_drv_pads[] = { LVDS_OCP, LVDS_OCN,
LVDS_OBP, LVDS_OBN };
static unsigned int lvds_e_drv_pads[] = { LVDS_EEP, LVDS_EEN,
LVDS_EDP, LVDS_EDN,
LVDS_ECP, LVDS_ECN,
LVDS_EBP, LVDS_EBN };
static unsigned int sd0_d3_d0_drv_pads[] = { SD0_D3, SD0_D2,
SD0_D1, SD0_D0 };
static unsigned int sd1_d3_d0_drv_pads[] = { SD1_D3, SD1_D2,
SD1_D1, SD1_D0 };
static unsigned int sd0_sd1_cmd_clk_drv_pads[] = { SD0_CLK, SD0_CMD,
SD1_CLK, SD1_CMD };
static unsigned int spi0_sclk_mosi_drv_pads[] = { SPI0_SCLK, SPI0_MOSI };
static unsigned int spi0_ss_miso_drv_pads[] = { SPI0_SS, SPI0_MISO };
static unsigned int uart0_rx_tx_drv_pads[] = { UART0_RX, UART0_TX };
static unsigned int uart4_rx_tx_drv_pads[] = { UART4_RX, UART4_TX };
static unsigned int uart2_drv_pads[] = { UART2_RX, UART2_TX,
UART2_RTSB, UART2_CTSB };
static unsigned int uart3_drv_pads[] = { UART3_RX, UART3_TX,
UART3_RTSB, UART3_CTSB };
/* drv2 */
static unsigned int i2c0_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };
static unsigned int i2c1_drv_pads[] = { I2C1_SCLK, I2C1_SDATA };
static unsigned int i2c2_drv_pads[] = { I2C2_SCLK, I2C2_SDATA };
static unsigned int sensor0_drv_pads[] = { SENSOR0_PCLK,
SENSOR0_CKOUT };
/* SR group data */
/* sr0 */
static unsigned int sgpio3_sr_pads[] = { SGPIO3 };
static unsigned int sgpio2_sr_pads[] = { SGPIO2 };
static unsigned int sgpio1_sr_pads[] = { SGPIO1 };
static unsigned int sgpio0_sr_pads[] = { SGPIO0 };
static unsigned int rmii_tx_d0_d1_sr_pads[] = { ETH_TXD0, ETH_TXD1 };
static unsigned int rmii_txen_rxer_sr_pads[] = { ETH_TXEN, ETH_RXER };
static unsigned int rmii_crs_dv_sr_pads[] = { ETH_CRS_DV };
static unsigned int rmii_rx_d1_d0_sr_pads[] = { ETH_RXD1, ETH_RXD0 };
static unsigned int rmii_ref_clk_sr_pads[] = { ETH_REF_CLK };
static unsigned int rmii_mdc_mdio_sr_pads[] = { ETH_MDC, ETH_MDIO };
static unsigned int sirq_0_1_sr_pads[] = { SIRQ0, SIRQ1 };
static unsigned int sirq2_sr_pads[] = { SIRQ2 };
static unsigned int i2s_do_d1_sr_pads[] = { I2S_D0, I2S_D1 };
static unsigned int i2s_lr_m_clk0_sr_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
static unsigned int i2s_bclk0_mclk1_sr_pads[] = { I2S_BCLK0, I2S_BCLK1,
I2S_LRCLK1, I2S_MCLK1 };
static unsigned int pcm1_in_out_sr_pads[] = { PCM1_IN, PCM1_CLK,
PCM1_SYNC, PCM1_OUT };
/* sr1 */
static unsigned int sd1_d3_d0_sr_pads[] = { SD1_D3, SD1_D2,
SD1_D1, SD1_D0 };
static unsigned int sd0_sd1_clk_cmd_sr_pads[] = { SD0_CLK, SD0_CMD,
SD1_CLK, SD1_CMD };
static unsigned int spi0_sclk_mosi_sr_pads[] = { SPI0_SCLK, SPI0_MOSI };
static unsigned int spi0_ss_miso_sr_pads[] = { SPI0_SS, SPI0_MISO };
static unsigned int uart0_rx_tx_sr_pads[] = { UART0_RX, UART0_TX };
static unsigned int uart4_rx_tx_sr_pads[] = { UART4_RX, UART4_TX };
static unsigned int uart2_sr_pads[] = { UART2_RX, UART2_TX,
UART2_RTSB, UART2_CTSB };
static unsigned int uart3_sr_pads[] = { UART3_RX, UART3_TX,
UART3_RTSB, UART3_CTSB };
/* sr2 */
static unsigned int i2c0_sr_pads[] = { I2C0_SCLK, I2C0_SDATA };
static unsigned int i2c1_sr_pads[] = { I2C1_SCLK, I2C1_SDATA };
static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
SENSOR0_CKOUT };
/* Pinctrl groups */
static const struct owl_pingroup s900_groups[] = {
MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1),
MUX_PG(rmii_mdc_mfp, 0, 20, 2),
MUX_PG(rmii_mdio_mfp, 0, 20, 2),
MUX_PG(sirq0_mfp, 0, 19, 1),
MUX_PG(sirq1_mfp, 0, 19, 1),
MUX_PG(rmii_txd0_mfp, 0, 16, 3),
MUX_PG(rmii_txd1_mfp, 0, 16, 3),
MUX_PG(rmii_txen_mfp, 0, 13, 3),
MUX_PG(rmii_rxer_mfp, 0, 13, 3),
MUX_PG(rmii_crs_dv_mfp, 0, 11, 2),
MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
MUX_PG(i2s_d0_mfp, 0, 5, 1),
MUX_PG(i2s_d1_mfp, 0, 5, 1),
MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2),
MUX_PG(i2s_bclk0_mfp, 0, 2, 1),
MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1),
MUX_PG(pcm1_in_out_mfp, 0, 0, 2),
MUX_PG(pcm1_clk_mfp, 0, 0, 2),
MUX_PG(pcm1_sync_mfp, 0, 0, 2),
MUX_PG(eram_a5_mfp, 1, 29, 3),
MUX_PG(eram_a6_mfp, 1, 29, 3),
MUX_PG(eram_a7_mfp, 1, 29, 3),
MUX_PG(eram_a8_mfp, 1, 26, 3),
MUX_PG(eram_a9_mfp, 1, 26, 3),
MUX_PG(eram_a10_mfp, 1, 26, 3),
MUX_PG(eram_a11_mfp, 1, 23, 3),
MUX_PG(lvds_oep_odn_mfp, 1, 22, 1),
MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1),
MUX_PG(lvds_oap_oan_mfp, 1, 22, 1),
MUX_PG(lvds_e_mfp, 1, 21, 1),
MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2),
MUX_PG(spi0_ss_mfp, 1, 1, 3),
MUX_PG(spi0_miso_mfp, 1, 1, 3),
MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
MUX_PG(sd0_d0_mfp, 2, 17, 3),
MUX_PG(sd0_d1_mfp, 2, 14, 3),
MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
MUX_PG(sd0_cmd_mfp, 2, 7, 2),
MUX_PG(sd0_clk_mfp, 2, 5, 2),
MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2),
MUX_PG(uart0_rx_mfp, 2, 0, 3),
MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1),
MUX_PG(uart0_tx_mfp, 3, 19, 3),
MUX_PG(i2c0_mfp, 3, 16, 3),
MUX_PG(csi0_cn_cp_mfp, 3, 15, 1),
MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1),
MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1),
MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1),
MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1),
MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1),
MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1),
MUX_PG(nand1_ceb3_mfp, 3, 10, 1),
MUX_PG(nand1_ceb0_mfp, 3, 10, 1),
MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1),
MUX_PG(uart4_rx_tx_mfp, 3, 8, 1),
DRV_PG(sgpio3_drv, 0, 30, 2),
DRV_PG(sgpio2_drv, 0, 28, 2),
DRV_PG(sgpio1_drv, 0, 26, 2),
DRV_PG(sgpio0_drv, 0, 24, 2),
DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2),
DRV_PG(rmii_txen_rxer_drv, 0, 20, 2),
DRV_PG(rmii_crs_dv_drv, 0, 18, 2),
DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2),
DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2),
DRV_PG(sirq_0_1_drv, 0, 10, 2),
DRV_PG(sirq2_drv, 0, 8, 2),
DRV_PG(i2s_d0_d1_drv, 0, 6, 2),
DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2),
DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2),
DRV_PG(pcm1_in_out_drv, 0, 0, 2),
DRV_PG(lvds_oap_oan_drv, 1, 28, 2),
DRV_PG(lvds_oep_odn_drv, 1, 26, 2),
DRV_PG(lvds_ocp_obn_drv, 1, 24, 2),
DRV_PG(lvds_e_drv, 1, 22, 2),
DRV_PG(sd0_d3_d0_drv, 1, 20, 2),
DRV_PG(sd1_d3_d0_drv, 1, 18, 2),
DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2),
DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2),
DRV_PG(spi0_ss_miso_drv, 1, 12, 2),
DRV_PG(uart0_rx_tx_drv, 1, 10, 2),
DRV_PG(uart4_rx_tx_drv, 1, 8, 2),
DRV_PG(uart2_drv, 1, 6, 2),
DRV_PG(uart3_drv, 1, 4, 2),
DRV_PG(i2c0_drv, 2, 30, 2),
DRV_PG(i2c1_drv, 2, 28, 2),
DRV_PG(i2c2_drv, 2, 26, 2),
DRV_PG(sensor0_drv, 2, 20, 2),
SR_PG(sgpio3_sr, 0, 15, 1),
SR_PG(sgpio2_sr, 0, 14, 1),
SR_PG(sgpio1_sr, 0, 13, 1),
SR_PG(sgpio0_sr, 0, 12, 1),
SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1),
SR_PG(rmii_txen_rxer_sr, 0, 10, 1),
SR_PG(rmii_crs_dv_sr, 0, 9, 1),
SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1),
SR_PG(rmii_ref_clk_sr, 0, 7, 1),
SR_PG(rmii_mdc_mdio_sr, 0, 6, 1),
SR_PG(sirq_0_1_sr, 0, 5, 1),
SR_PG(sirq2_sr, 0, 4, 1),
SR_PG(i2s_do_d1_sr, 0, 3, 1),
SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1),
SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1),
SR_PG(pcm1_in_out_sr, 0, 0, 1),
SR_PG(sd1_d3_d0_sr, 1, 25, 1),
SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1),
SR_PG(spi0_sclk_mosi_sr, 1, 23, 1),
SR_PG(spi0_ss_miso_sr, 1, 22, 1),
SR_PG(uart0_rx_tx_sr, 1, 21, 1),
SR_PG(uart4_rx_tx_sr, 1, 20, 1),
SR_PG(uart2_sr, 1, 19, 1),
SR_PG(uart3_sr, 1, 18, 1),
SR_PG(i2c0_sr, 2, 31, 1),
SR_PG(i2c1_sr, 2, 30, 1),
SR_PG(i2c2_sr, 2, 29, 1),
SR_PG(sensor0_sr, 2, 25, 1)
};
static const char * const eram_groups[] = {
"lvds_oxx_uart4_mfp",
"eram_a5_mfp",
"eram_a6_mfp",
"eram_a7_mfp",
"eram_a8_mfp",
"eram_a9_mfp",
"eram_a10_mfp",
"eram_a11_mfp",
"lvds_oap_oan_mfp",
"lvds_e_mfp",
"spi0_sclk_mosi_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd1_d0_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
"sd1_cmd_clk_mfp",
};
static const char * const eth_rmii_groups[] = {
"rmii_mdc_mfp",
"rmii_mdio_mfp",
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_txen_mfp",
"rmii_rxer_mfp",
"rmii_crs_dv_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"rmii_ref_clk_mfp",
"eth_smi_dummy",
};
static const char * const eth_smii_groups[] = {
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_crs_dv_mfp",
"eth_smi_dummy",
};
static const char * const spi0_groups[] = {
"spi0_sclk_mosi_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
"spi0_sclk_mosi_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
};
static const char * const spi1_groups[] = {
"pcm1_in_out_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const spi2_groups[] = {
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_crs_dv_mfp",
"rmii_ref_clk_mfp",
};
static const char * const spi3_groups[] = {
"rmii_txen_mfp",
"rmii_rxer_mfp",
};
static const char * const sens0_groups[] = {
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_txen_mfp",
"rmii_rxer_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"eram_a5_mfp",
"eram_a6_mfp",
"eram_a7_mfp",
"eram_a8_mfp",
"eram_a9_mfp",
"csi0_cn_cp_mfp",
"csi0_dn0_dp3_mfp",
"csi1_dn0_cp_mfp",
"csi1_dn0_dp0_mfp",
};
static const char * const uart0_groups[] = {
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const uart1_groups[] = {
"sd0_d2_d3_mfp",
"i2c0_mfp",
};
static const char * const uart2_groups[] = {
"rmii_mdc_mfp",
"rmii_mdio_mfp",
"rmii_txen_mfp",
"rmii_rxer_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"lvds_oep_odn_mfp",
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp_pads",
"i2c0_mfp_pads",
"dsi_dp3_dn1_mfp",
"uart2_dummy"
};
static const char * const uart3_groups[] = {
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
"uart3_dummy"
};
static const char * const uart4_groups[] = {
"lvds_oxx_uart4_mfp",
"rmii_crs_dv_mfp",
"rmii_ref_clk_mfp",
"pcm1_in_out_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"eram_a5_mfp",
"eram_a6_mfp",
"dsi_dp2_dn2_mfp",
"uart4_rx_tx_mfp_pads",
"uart4_dummy"
};
static const char * const uart5_groups[] = {
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"eram_a9_mfp",
"eram_a11_mfp",
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
};
static const char * const uart6_groups[] = {
"rmii_txd0_mfp",
"rmii_txd1_mfp",
};
static const char * const i2s0_groups[] = {
"i2s_d0_mfp",
"i2s_lr_m_clk0_mfp",
"i2s_bclk0_mfp",
"i2s0_dummy",
};
static const char * const i2s1_groups[] = {
"i2s_d1_mfp",
"i2s_bclk1_mclk1_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2s1_dummy",
};
static const char * const pcm0_groups[] = {
"i2s_d0_mfp",
"i2s_d1_mfp",
"i2s_lr_m_clk0_mfp",
"i2s_bclk0_mfp",
"i2s_bclk1_mclk1_mfp",
"spi0_sclk_mosi_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
};
static const char * const pcm1_groups[] = {
"i2s_lr_m_clk0_mfp",
"pcm1_in_out_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"lvds_oep_odn_mfp",
"spi0_ss_mfp",
"spi0_miso_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"dsi_cp_dn0_mfp",
"pcm1_dummy",
};
static const char * const jtag_groups[] = {
"eram_a5_mfp",
"eram_a6_mfp",
"eram_a7_mfp",
"eram_a8_mfp",
"eram_a10_mfp",
"eram_a10_mfp",
"sd0_d2_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const pwm0_groups[] = {
"sirq0_mfp",
"rmii_txd0_mfp",
"rmii_rxd1_mfp",
"eram_a5_mfp",
"nand1_ceb3_mfp",
};
static const char * const pwm1_groups[] = {
"sirq1_mfp",
"rmii_txd1_mfp",
"rmii_rxd0_mfp",
"eram_a6_mfp",
"eram_a8_mfp",
"nand1_ceb0_mfp",
};
static const char * const pwm2_groups[] = {
"rmii_mdc_mfp",
"rmii_txen_mfp",
"eram_a9_mfp",
"eram_a11_mfp",
};
static const char * const pwm3_groups[] = {
"rmii_mdio_mfp",
"rmii_rxer_mfp",
"eram_a10_mfp",
};
static const char * const pwm4_groups[] = {
"pcm1_clk_mfp",
"spi0_ss_mfp",
};
static const char * const pwm5_groups[] = {
"pcm1_sync_mfp",
"spi0_miso_mfp",
};
static const char * const sd0_groups[] = {
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const sd1_groups[] = {
"sd1_d0_d3_mfp",
"sd1_cmd_clk_mfp",
"sd1_dummy",
};
static const char * const sd2_groups[] = {
"nand0_d0_ceb3_mfp",
};
static const char * const sd3_groups[] = {
"nand1_d0_ceb1_mfp",
};
static const char * const i2c0_groups[] = {
"i2c0_mfp",
};
static const char * const i2c1_groups[] = {
"i2c0_mfp",
"i2c1_dummy"
};
static const char * const i2c2_groups[] = {
"i2c2_dummy"
};
static const char * const i2c3_groups[] = {
"pcm1_in_out_mfp",
"spi0_sclk_mosi_mfp",
};
static const char * const i2c4_groups[] = {
"uart4_rx_tx_mfp",
};
static const char * const i2c5_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const lvds_groups[] = {
"lvds_oep_odn_mfp",
"lvds_ocp_obn_mfp",
"lvds_oap_oan_mfp",
"lvds_e_mfp",
};
static const char * const usb20_groups[] = {
"eram_a9_mfp",
};
static const char * const usb30_groups[] = {
"eram_a10_mfp",
};
static const char * const gpu_groups[] = {
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const mipi_csi0_groups[] = {
"csi0_dn0_dp3_mfp",
};
static const char * const mipi_csi1_groups[] = {
"csi1_dn0_cp_mfp",
};
static const char * const mipi_dsi_groups[] = {
"dsi_dp3_dn1_mfp",
"dsi_cp_dn0_mfp",
"dsi_dp2_dn2_mfp",
"mipi_dsi_dummy",
};
static const char * const nand0_groups[] = {
"nand0_d0_ceb3_mfp",
"nand0_dummy",
};
static const char * const nand1_groups[] = {
"nand1_d0_ceb1_mfp",
"nand1_ceb3_mfp",
"nand1_ceb0_mfp",
"nand1_dummy",
};
static const char * const spdif_groups[] = {
"uart0_tx_mfp",
};
static const char * const sirq0_groups[] = {
"sirq0_mfp",
"sirq0_dummy",
};
static const char * const sirq1_groups[] = {
"sirq1_mfp",
"sirq1_dummy",
};
static const char * const sirq2_groups[] = {
"sirq2_dummy",
};
static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_ERAM] = FUNCTION(eram),
[S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
[S900_MUX_ETH_SMII] = FUNCTION(eth_smii),
[S900_MUX_SPI0] = FUNCTION(spi0),
[S900_MUX_SPI1] = FUNCTION(spi1),
[S900_MUX_SPI2] = FUNCTION(spi2),
[S900_MUX_SPI3] = FUNCTION(spi3),
[S900_MUX_SENS0] = FUNCTION(sens0),
[S900_MUX_UART0] = FUNCTION(uart0),
[S900_MUX_UART1] = FUNCTION(uart1),
[S900_MUX_UART2] = FUNCTION(uart2),
[S900_MUX_UART3] = FUNCTION(uart3),
[S900_MUX_UART4] = FUNCTION(uart4),
[S900_MUX_UART5] = FUNCTION(uart5),
[S900_MUX_UART6] = FUNCTION(uart6),
[S900_MUX_I2S0] = FUNCTION(i2s0),
[S900_MUX_I2S1] = FUNCTION(i2s1),
[S900_MUX_PCM0] = FUNCTION(pcm0),
[S900_MUX_PCM1] = FUNCTION(pcm1),
[S900_MUX_JTAG] = FUNCTION(jtag),
[S900_MUX_PWM0] = FUNCTION(pwm0),
[S900_MUX_PWM1] = FUNCTION(pwm1),
[S900_MUX_PWM2] = FUNCTION(pwm2),
[S900_MUX_PWM3] = FUNCTION(pwm3),
[S900_MUX_PWM4] = FUNCTION(pwm4),
[S900_MUX_PWM5] = FUNCTION(pwm5),
[S900_MUX_SD0] = FUNCTION(sd0),
[S900_MUX_SD1] = FUNCTION(sd1),
[S900_MUX_SD2] = FUNCTION(sd2),
[S900_MUX_SD3] = FUNCTION(sd3),
[S900_MUX_I2C0] = FUNCTION(i2c0),
[S900_MUX_I2C1] = FUNCTION(i2c1),
[S900_MUX_I2C2] = FUNCTION(i2c2),
[S900_MUX_I2C3] = FUNCTION(i2c3),
[S900_MUX_I2C4] = FUNCTION(i2c4),
[S900_MUX_I2C5] = FUNCTION(i2c5),
[S900_MUX_LVDS] = FUNCTION(lvds),
[S900_MUX_USB30] = FUNCTION(usb30),
[S900_MUX_USB20] = FUNCTION(usb20),
[S900_MUX_GPU] = FUNCTION(gpu),
[S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0),
[S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1),
[S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi),
[S900_MUX_NAND0] = FUNCTION(nand0),
[S900_MUX_NAND1] = FUNCTION(nand1),
[S900_MUX_SPDIF] = FUNCTION(spdif),
[S900_MUX_SIRQ0] = FUNCTION(sirq0),
[S900_MUX_SIRQ1] = FUNCTION(sirq1),
[S900_MUX_SIRQ2] = FUNCTION(sirq2)
};
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2);
static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2);
static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2);
static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2);
static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2);
static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2);
static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2);
static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2);
static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2);
/* PAD_PULLCTL1 */
static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2);
static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2);
static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2);
static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2);
static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2);
static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2);
static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2);
static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2);
static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2);
static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2);
static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2);
static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2);
static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2);
static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2);
static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2);
/* PAD_PULLCTL2 */
static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2);
static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2);
static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2);
static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2);
static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2);
static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2);
static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1);
static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1);
static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1);
static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1);
static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1);
static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1);
static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2);
static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2);
static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2);
static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2);
/* PAD_ST0 */
static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
static PAD_ST_CONF(UART0_RX, 0, 29, 1);
static PAD_ST_CONF(ETH_MDC, 0, 28, 1);
static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
static PAD_ST_CONF(SGPIO2, 0, 18, 1);
static PAD_ST_CONF(SGPIO3, 0, 17, 1);
static PAD_ST_CONF(UART4_TX, 0, 16, 1);
static PAD_ST_CONF(I2S_D1, 0, 15, 1);
static PAD_ST_CONF(UART0_TX, 0, 14, 1);
static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
static PAD_ST_CONF(ERAM_A5, 0, 11, 1);
static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
static PAD_ST_CONF(ERAM_A9, 0, 6, 1);
static PAD_ST_CONF(LVDS_OEP, 0, 5, 1);
static PAD_ST_CONF(LVDS_ODN, 0, 4, 1);
static PAD_ST_CONF(LVDS_OAP, 0, 3, 1);
static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1);
/* PAD_ST1 */
static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
static PAD_ST_CONF(UART4_RX, 1, 28, 1);
static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
static PAD_ST_CONF(UART3_RX, 1, 25, 1);
static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
static PAD_ST_CONF(UART2_RX, 1, 22, 1);
static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
static PAD_ST_CONF(LVDS_OCP, 1, 16, 1);
static PAD_ST_CONF(LVDS_OBP, 1, 15, 1);
static PAD_ST_CONF(LVDS_OBN, 1, 14, 1);
static PAD_ST_CONF(PCM1_OUT, 1, 12, 1);
static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
/* Pad info table */
static const struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
[ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
[ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
[ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
[ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
[ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
[ETH_MDC] = PAD_INFO_ST(ETH_MDC),
[ETH_MDIO] = PAD_INFO(ETH_MDIO),
[SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
[SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
[SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
[I2S_D0] = PAD_INFO(I2S_D0),
[I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
[I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
[I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
[I2S_D1] = PAD_INFO_ST(I2S_D1),
[I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1),
[I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
[I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
[PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN),
[PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
[PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC),
[PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT),
[ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5),
[ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6),
[ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7),
[ERAM_A8] = PAD_INFO(ERAM_A8),
[ERAM_A9] = PAD_INFO_ST(ERAM_A9),
[ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10),
[ERAM_A11] = PAD_INFO(ERAM_A11),
[LVDS_OEP] = PAD_INFO_ST(LVDS_OEP),
[LVDS_OEN] = PAD_INFO(LVDS_OEN),
[LVDS_ODP] = PAD_INFO(LVDS_ODP),
[LVDS_ODN] = PAD_INFO_ST(LVDS_ODN),
[LVDS_OCP] = PAD_INFO_ST(LVDS_OCP),
[LVDS_OCN] = PAD_INFO(LVDS_OCN),
[LVDS_OBP] = PAD_INFO_ST(LVDS_OBP),
[LVDS_OBN] = PAD_INFO_ST(LVDS_OBN),
[LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
[LVDS_OAN] = PAD_INFO(LVDS_OAN),
[LVDS_EEP] = PAD_INFO(LVDS_EEP),
[LVDS_EEN] = PAD_INFO(LVDS_EEN),
[LVDS_EDP] = PAD_INFO(LVDS_EDP),
[LVDS_EDN] = PAD_INFO(LVDS_EDN),
[LVDS_ECP] = PAD_INFO(LVDS_ECP),
[LVDS_ECN] = PAD_INFO(LVDS_ECN),
[LVDS_EBP] = PAD_INFO(LVDS_EBP),
[LVDS_EBN] = PAD_INFO(LVDS_EBN),
[LVDS_EAP] = PAD_INFO(LVDS_EAP),
[LVDS_EAN] = PAD_INFO(LVDS_EAN),
[SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
[SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
[SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
[SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
[SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
[SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
[SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
[SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
[SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
[SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
[SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
[SD1_CLK] = PAD_INFO(SD1_CLK),
[SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
[SPI0_SS] = PAD_INFO_ST(SPI0_SS),
[SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
[SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
[UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
[UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
[UART2_RX] = PAD_INFO_ST(UART2_RX),
[UART2_TX] = PAD_INFO(UART2_TX),
[UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
[UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
[UART3_RX] = PAD_INFO_ST(UART3_RX),
[UART3_TX] = PAD_INFO(UART3_TX),
[UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
[UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
[UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX),
[UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX),
[I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
[I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
[I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
[I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
[I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
[I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
[CSI0_DN0] = PAD_INFO(CSI0_DN0),
[CSI0_DP0] = PAD_INFO(CSI0_DP0),
[CSI0_DN1] = PAD_INFO(CSI0_DN1),
[CSI0_DP1] = PAD_INFO(CSI0_DP1),
[CSI0_CN] = PAD_INFO(CSI0_CN),
[CSI0_CP] = PAD_INFO(CSI0_CP),
[CSI0_DN2] = PAD_INFO(CSI0_DN2),
[CSI0_DP2] = PAD_INFO(CSI0_DP2),
[CSI0_DN3] = PAD_INFO(CSI0_DN3),
[CSI0_DP3] = PAD_INFO(CSI0_DP3),
[DSI_DP3] = PAD_INFO(DSI_DP3),
[DSI_DN3] = PAD_INFO(DSI_DN3),
[DSI_DP1] = PAD_INFO(DSI_DP1),
[DSI_DN1] = PAD_INFO(DSI_DN1),
[DSI_CP] = PAD_INFO(DSI_CP),
[DSI_CN] = PAD_INFO(DSI_CN),
[DSI_DP0] = PAD_INFO(DSI_DP0),
[DSI_DN0] = PAD_INFO(DSI_DN0),
[DSI_DP2] = PAD_INFO(DSI_DP2),
[DSI_DN2] = PAD_INFO(DSI_DN2),
[SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK),
[CSI1_DN0] = PAD_INFO(CSI1_DN0),
[CSI1_DP0] = PAD_INFO(CSI1_DP0),
[CSI1_DN1] = PAD_INFO(CSI1_DN1),
[CSI1_DP1] = PAD_INFO(CSI1_DP1),
[CSI1_CN] = PAD_INFO(CSI1_CN),
[CSI1_CP] = PAD_INFO(CSI1_CP),
[SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
[NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0),
[NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1),
[NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2),
[NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3),
[NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4),
[NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5),
[NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6),
[NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7),
[NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS),
[NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN),
[NAND0_ALE] = PAD_INFO(NAND0_ALE),
[NAND0_CLE] = PAD_INFO(NAND0_CLE),
[NAND0_CEB0] = PAD_INFO(NAND0_CEB0),
[NAND0_CEB1] = PAD_INFO(NAND0_CEB1),
[NAND0_CEB2] = PAD_INFO(NAND0_CEB2),
[NAND0_CEB3] = PAD_INFO(NAND0_CEB3),
[NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0),
[NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1),
[NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2),
[NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3),
[NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4),
[NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5),
[NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6),
[NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7),
[NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS),
[NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN),
[NAND1_ALE] = PAD_INFO(NAND1_ALE),
[NAND1_CLE] = PAD_INFO(NAND1_CLE),
[NAND1_CEB0] = PAD_INFO(NAND1_CEB0),
[NAND1_CEB1] = PAD_INFO(NAND1_CEB1),
[NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
[NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
[SGPIO0] = PAD_INFO(SGPIO0),
[SGPIO1] = PAD_INFO(SGPIO1),
[SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
};
static const struct owl_gpio_port s900_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
};
enum s900_pinconf_pull {
OWL_PINCONF_PULL_HIZ,
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
OWL_PINCONF_PULL_HOLD,
};
static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = *arg == OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = *arg == OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.padinfo = s900_padinfo,
.pins = (const struct pinctrl_pin_desc *)s900_pads,
.npins = ARRAY_SIZE(s900_pads),
.functions = s900_functions,
.nfunctions = ARRAY_SIZE(s900_functions),
.groups = s900_groups,
.ngroups = ARRAY_SIZE(s900_groups),
.ngpios = NUM_GPIOS,
.ports = s900_gpio_ports,
.nports = ARRAY_SIZE(s900_gpio_ports),
.padctl_arg2val = s900_pad_pinconf_arg2val,
.padctl_val2arg = s900_pad_pinconf_val2arg,
};
static int s900_pinctrl_probe(struct platform_device *pdev)
{
return owl_pinctrl_probe(pdev, &s900_pinctrl_data);
}
static const struct of_device_id s900_pinctrl_of_match[] = {
{ .compatible = "actions,s900-pinctrl", },
{ }
};
static struct platform_driver s900_pinctrl_driver = {
.driver = {
.name = "pinctrl-s900",
.of_match_table = of_match_ptr(s900_pinctrl_of_match),
},
.probe = s900_pinctrl_probe,
};
static int __init s900_pinctrl_init(void)
{
return platform_driver_register(&s900_pinctrl_driver);
}
arch_initcall(s900_pinctrl_init);
static void __exit s900_pinctrl_exit(void)
{
platform_driver_unregister(&s900_pinctrl_driver);
}
module_exit(s900_pinctrl_exit);
MODULE_AUTHOR("Actions Semi Inc.");
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/actions/pinctrl-s900.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Actions Semi Owl S700 Pinctrl driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <[email protected]>
*
* Author: Pathiban Nallathambi <[email protected]>
* Author: Saravanan Sekar <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
#define MFCTL0 (0x0040)
#define MFCTL1 (0x0044)
#define MFCTL2 (0x0048)
#define MFCTL3 (0x004C)
#define PAD_PULLCTL0 (0x0060)
#define PAD_PULLCTL1 (0x0064)
#define PAD_PULLCTL2 (0x0068)
#define PAD_ST0 (0x006C)
#define PAD_ST1 (0x0070)
#define PAD_CTL (0x0074)
#define PAD_DRV0 (0x0080)
#define PAD_DRV1 (0x0084)
#define PAD_DRV2 (0x0088)
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
#define _GPIOD(offset) (96 + (offset))
#define _GPIOE(offset) (128 + (offset))
/* All non-GPIO pins follow */
#define NUM_GPIOS (_GPIOE(7) + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
/* Ethernet MAC */
#define ETH_TXD0 _GPIOA(14)
#define ETH_TXD1 _GPIOA(15)
#define ETH_TXD2 _GPIOE(4)
#define ETH_TXD3 _GPIOE(5)
#define ETH_TXEN _GPIOA(16)
#define ETH_RXER _GPIOA(17)
#define ETH_CRS_DV _GPIOA(18)
#define ETH_RXD1 _GPIOA(19)
#define ETH_RXD0 _GPIOA(20)
#define ETH_RXD2 _GPIOE(6)
#define ETH_RXD3 _GPIOE(7)
#define ETH_REF_CLK _GPIOA(21)
#define ETH_MDC _GPIOA(22)
#define ETH_MDIO _GPIOA(23)
/* SIRQ */
#define SIRQ0 _GPIOA(24)
#define SIRQ1 _GPIOA(25)
#define SIRQ2 _GPIOA(26)
/* I2S */
#define I2S_D0 _GPIOA(27)
#define I2S_BCLK0 _GPIOA(28)
#define I2S_LRCLK0 _GPIOA(29)
#define I2S_MCLK0 _GPIOA(30)
#define I2S_D1 _GPIOA(31)
#define I2S_BCLK1 _GPIOB(0)
#define I2S_LRCLK1 _GPIOB(1)
#define I2S_MCLK1 _GPIOB(2)
/* PCM1 */
#define PCM1_IN _GPIOD(28)
#define PCM1_CLK _GPIOD(29)
#define PCM1_SYNC _GPIOD(30)
#define PCM1_OUT _GPIOD(31)
/* KEY */
#define KS_IN0 _GPIOB(3)
#define KS_IN1 _GPIOB(4)
#define KS_IN2 _GPIOB(5)
#define KS_IN3 _GPIOB(6)
#define KS_OUT0 _GPIOB(7)
#define KS_OUT1 _GPIOB(8)
#define KS_OUT2 _GPIOB(9)
/* LVDS */
#define LVDS_OEP _GPIOB(10)
#define LVDS_OEN _GPIOB(11)
#define LVDS_ODP _GPIOB(12)
#define LVDS_ODN _GPIOB(13)
#define LVDS_OCP _GPIOB(14)
#define LVDS_OCN _GPIOB(15)
#define LVDS_OBP _GPIOB(16)
#define LVDS_OBN _GPIOB(17)
#define LVDS_OAP _GPIOB(18)
#define LVDS_OAN _GPIOB(19)
#define LVDS_EEP _GPIOB(20)
#define LVDS_EEN _GPIOB(21)
#define LVDS_EDP _GPIOB(22)
#define LVDS_EDN _GPIOB(23)
#define LVDS_ECP _GPIOB(24)
#define LVDS_ECN _GPIOB(25)
#define LVDS_EBP _GPIOB(26)
#define LVDS_EBN _GPIOB(27)
#define LVDS_EAP _GPIOB(28)
#define LVDS_EAN _GPIOB(29)
#define LCD0_D18 _GPIOB(30)
#define LCD0_D2 _GPIOB(31)
/* DSI */
#define DSI_DP3 _GPIOC(0)
#define DSI_DN3 _GPIOC(1)
#define DSI_DP1 _GPIOC(2)
#define DSI_DN1 _GPIOC(3)
#define DSI_CP _GPIOC(4)
#define DSI_CN _GPIOC(5)
#define DSI_DP0 _GPIOC(6)
#define DSI_DN0 _GPIOC(7)
#define DSI_DP2 _GPIOC(8)
#define DSI_DN2 _GPIOC(9)
/* SD */
#define SD0_D0 _GPIOC(10)
#define SD0_D1 _GPIOC(11)
#define SD0_D2 _GPIOC(12)
#define SD0_D3 _GPIOC(13)
#define SD0_D4 _GPIOC(14)
#define SD0_D5 _GPIOC(15)
#define SD0_D6 _GPIOC(16)
#define SD0_D7 _GPIOC(17)
#define SD0_CMD _GPIOC(18)
#define SD0_CLK _GPIOC(19)
#define SD1_CMD _GPIOC(20)
#define SD1_CLK _GPIOC(21)
#define SD1_D0 SD0_D4
#define SD1_D1 SD0_D5
#define SD1_D2 SD0_D6
#define SD1_D3 SD0_D7
/* SPI */
#define SPI0_SS _GPIOC(23)
#define SPI0_MISO _GPIOC(24)
/* UART for console */
#define UART0_RX _GPIOC(26)
#define UART0_TX _GPIOC(27)
/* UART for Bluetooth */
#define UART2_RX _GPIOD(18)
#define UART2_TX _GPIOD(19)
#define UART2_RTSB _GPIOD(20)
#define UART2_CTSB _GPIOD(21)
/* UART for 3G */
#define UART3_RX _GPIOD(22)
#define UART3_TX _GPIOD(23)
#define UART3_RTSB _GPIOD(24)
#define UART3_CTSB _GPIOD(25)
/* I2C */
#define I2C0_SCLK _GPIOC(28)
#define I2C0_SDATA _GPIOC(29)
#define I2C1_SCLK _GPIOE(0)
#define I2C1_SDATA _GPIOE(1)
#define I2C2_SCLK _GPIOE(2)
#define I2C2_SDATA _GPIOE(3)
/* CSI*/
#define CSI_DN0 _PIN(0)
#define CSI_DP0 _PIN(1)
#define CSI_DN1 _PIN(2)
#define CSI_DP1 _PIN(3)
#define CSI_CN _PIN(4)
#define CSI_CP _PIN(5)
#define CSI_DN2 _PIN(6)
#define CSI_DP2 _PIN(7)
#define CSI_DN3 _PIN(8)
#define CSI_DP3 _PIN(9)
/* Sensor */
#define SENSOR0_PCLK _GPIOC(31)
#define SENSOR0_CKOUT _GPIOD(10)
/* NAND (1.8v / 3.3v) */
#define DNAND_D0 _PIN(10)
#define DNAND_D1 _PIN(11)
#define DNAND_D2 _PIN(12)
#define DNAND_D3 _PIN(13)
#define DNAND_D4 _PIN(14)
#define DNAND_D5 _PIN(15)
#define DNAND_D6 _PIN(16)
#define DNAND_D7 _PIN(17)
#define DNAND_WRB _PIN(18)
#define DNAND_RDB _PIN(19)
#define DNAND_RDBN _PIN(20)
#define DNAND_DQS _GPIOA(12)
#define DNAND_DQSN _GPIOA(13)
#define DNAND_RB0 _PIN(21)
#define DNAND_ALE _GPIOD(12)
#define DNAND_CLE _GPIOD(13)
#define DNAND_CEB0 _GPIOD(14)
#define DNAND_CEB1 _GPIOD(15)
#define DNAND_CEB2 _GPIOD(16)
#define DNAND_CEB3 _GPIOD(17)
/* System */
#define PORB _PIN(22)
#define CLKO_25M _PIN(23)
#define BSEL _PIN(24)
#define PKG0 _PIN(25)
#define PKG1 _PIN(26)
#define PKG2 _PIN(27)
#define PKG3 _PIN(28)
#define _FIRSTPAD _GPIOA(0)
#define _LASTPAD PKG3
#define NUM_PADS (_PIN(28) + 1)
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc s700_pads[] = {
PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
PINCTRL_PIN(ETH_TXD2, "eth_txd2"),
PINCTRL_PIN(ETH_TXD3, "eth_txd3"),
PINCTRL_PIN(ETH_TXEN, "eth_txen"),
PINCTRL_PIN(ETH_RXER, "eth_rxer"),
PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
PINCTRL_PIN(ETH_RXD2, "eth_rxd2"),
PINCTRL_PIN(ETH_RXD3, "eth_rxd3"),
PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
PINCTRL_PIN(ETH_MDC, "eth_mdc"),
PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
PINCTRL_PIN(SIRQ0, "sirq0"),
PINCTRL_PIN(SIRQ1, "sirq1"),
PINCTRL_PIN(SIRQ2, "sirq2"),
PINCTRL_PIN(I2S_D0, "i2s_d0"),
PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
PINCTRL_PIN(I2S_D1, "i2s_d1"),
PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
PINCTRL_PIN(PCM1_IN, "pcm1_in"),
PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
PINCTRL_PIN(KS_IN0, "ks_in0"),
PINCTRL_PIN(KS_IN1, "ks_in1"),
PINCTRL_PIN(KS_IN2, "ks_in2"),
PINCTRL_PIN(KS_IN3, "ks_in3"),
PINCTRL_PIN(KS_OUT0, "ks_out0"),
PINCTRL_PIN(KS_OUT1, "ks_out1"),
PINCTRL_PIN(KS_OUT2, "ks_out2"),
PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
PINCTRL_PIN(LVDS_EEN, "lvds_een"),
PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
PINCTRL_PIN(LCD0_D2, "lcd0_d2"),
PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
PINCTRL_PIN(DSI_CP, "dsi_cp"),
PINCTRL_PIN(DSI_CN, "dsi_cn"),
PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
PINCTRL_PIN(SD0_D0, "sd0_d0"),
PINCTRL_PIN(SD0_D1, "sd0_d1"),
PINCTRL_PIN(SD0_D2, "sd0_d2"),
PINCTRL_PIN(SD0_D3, "sd0_d3"),
PINCTRL_PIN(SD1_D0, "sd1_d0"),
PINCTRL_PIN(SD1_D1, "sd1_d1"),
PINCTRL_PIN(SD1_D2, "sd1_d2"),
PINCTRL_PIN(SD1_D3, "sd1_d3"),
PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
PINCTRL_PIN(SD0_CLK, "sd0_clk"),
PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
PINCTRL_PIN(SD1_CLK, "sd1_clk"),
PINCTRL_PIN(SPI0_SS, "spi0_ss"),
PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
PINCTRL_PIN(UART0_RX, "uart0_rx"),
PINCTRL_PIN(UART0_TX, "uart0_tx"),
PINCTRL_PIN(UART2_RX, "uart2_rx"),
PINCTRL_PIN(UART2_TX, "uart2_tx"),
PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
PINCTRL_PIN(UART3_RX, "uart3_rx"),
PINCTRL_PIN(UART3_TX, "uart3_tx"),
PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
PINCTRL_PIN(CSI_DN0, "csi_dn0"),
PINCTRL_PIN(CSI_DP0, "csi_dp0"),
PINCTRL_PIN(CSI_DN1, "csi_dn1"),
PINCTRL_PIN(CSI_DP1, "csi_dp1"),
PINCTRL_PIN(CSI_CN, "csi_cn"),
PINCTRL_PIN(CSI_CP, "csi_cp"),
PINCTRL_PIN(CSI_DN2, "csi_dn2"),
PINCTRL_PIN(CSI_DP2, "csi_dp2"),
PINCTRL_PIN(CSI_DN3, "csi_dn3"),
PINCTRL_PIN(CSI_DP3, "csi_dp3"),
PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
PINCTRL_PIN(DNAND_D0, "dnand_d0"),
PINCTRL_PIN(DNAND_D1, "dnand_d1"),
PINCTRL_PIN(DNAND_D2, "dnand_d2"),
PINCTRL_PIN(DNAND_D3, "dnand_d3"),
PINCTRL_PIN(DNAND_D4, "dnand_d4"),
PINCTRL_PIN(DNAND_D5, "dnand_d5"),
PINCTRL_PIN(DNAND_D6, "dnand_d6"),
PINCTRL_PIN(DNAND_D7, "dnand_d7"),
PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
PINCTRL_PIN(DNAND_RB0, "dnand_rb0"),
PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
PINCTRL_PIN(PORB, "porb"),
PINCTRL_PIN(CLKO_25M, "clko_25m"),
PINCTRL_PIN(BSEL, "bsel"),
PINCTRL_PIN(PKG0, "pkg0"),
PINCTRL_PIN(PKG1, "pkg1"),
PINCTRL_PIN(PKG2, "pkg2"),
PINCTRL_PIN(PKG3, "pkg3"),
};
enum s700_pinmux_functions {
S700_MUX_NOR,
S700_MUX_ETH_RGMII,
S700_MUX_ETH_SGMII,
S700_MUX_SPI0,
S700_MUX_SPI1,
S700_MUX_SPI2,
S700_MUX_SPI3,
S700_MUX_SENS0,
S700_MUX_SENS1,
S700_MUX_UART0,
S700_MUX_UART1,
S700_MUX_UART2,
S700_MUX_UART3,
S700_MUX_UART4,
S700_MUX_UART5,
S700_MUX_UART6,
S700_MUX_I2S0,
S700_MUX_I2S1,
S700_MUX_PCM1,
S700_MUX_PCM0,
S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_PWM0,
S700_MUX_PWM1,
S700_MUX_PWM2,
S700_MUX_PWM3,
S700_MUX_PWM4,
S700_MUX_PWM5,
S700_MUX_P0,
S700_MUX_SD0,
S700_MUX_SD1,
S700_MUX_SD2,
S700_MUX_I2C0,
S700_MUX_I2C1,
S700_MUX_I2C2,
S700_MUX_I2C3,
S700_MUX_DSI,
S700_MUX_LVDS,
S700_MUX_USB30,
S700_MUX_CLKO_25M,
S700_MUX_MIPI_CSI,
S700_MUX_NAND,
S700_MUX_SPDIF,
S700_MUX_SIRQ0,
S700_MUX_SIRQ1,
S700_MUX_SIRQ2,
S700_MUX_BT,
S700_MUX_LCD0,
S700_MUX_RESERVED,
};
/* mfp0_31_30 reserved */
/* rgmii_txd23 */
static unsigned int rgmii_txd23_mfp_pads[] = { ETH_TXD2, ETH_TXD3};
static unsigned int rgmii_txd23_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_I2C1,
S700_MUX_UART3 };
/* rgmii_rxd2 */
static unsigned int rgmii_rxd2_mfp_pads[] = { ETH_RXD2 };
static unsigned int rgmii_rxd2_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_PWM0,
S700_MUX_UART3 };
/* rgmii_rxd3 */
static unsigned int rgmii_rxd3_mfp_pads[] = { ETH_RXD3};
static unsigned int rgmii_rxd3_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_PWM2,
S700_MUX_UART3 };
/* lcd0_d18 */
static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };
static unsigned int lcd0_d18_mfp_funcs[] = { S700_MUX_NOR,
S700_MUX_SENS1,
S700_MUX_PWM2,
S700_MUX_PWM4,
S700_MUX_LCD0 };
/* rgmii_txd01 */
static unsigned int rgmii_txd01_mfp_pads[] = { ETH_CRS_DV };
static unsigned int rgmii_txd01_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_RESERVED,
S700_MUX_SPI2,
S700_MUX_UART4,
S700_MUX_PWM4 };
/* rgmii_txd0 */
static unsigned int rgmii_txd0_mfp_pads[] = { ETH_TXD0 };
static unsigned int rgmii_txd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_ETH_SGMII,
S700_MUX_SPI2,
S700_MUX_UART6,
S700_MUX_PWM4 };
/* rgmii_txd1 */
static unsigned int rgmii_txd1_mfp_pads[] = { ETH_TXD1 };
static unsigned int rgmii_txd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_ETH_SGMII,
S700_MUX_SPI2,
S700_MUX_UART6,
S700_MUX_PWM5 };
/* rgmii_txen */
static unsigned int rgmii_txen_mfp_pads[] = { ETH_TXEN };
static unsigned int rgmii_txen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_UART2,
S700_MUX_SPI3,
S700_MUX_PWM0 };
/* rgmii_rxen */
static unsigned int rgmii_rxen_mfp_pads[] = { ETH_RXER };
static unsigned int rgmii_rxen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_UART2,
S700_MUX_SPI3,
S700_MUX_PWM1 };
/* mfp0_12_11 reserved */
/* rgmii_rxd1*/
static unsigned int rgmii_rxd1_mfp_pads[] = { ETH_RXD1 };
static unsigned int rgmii_rxd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_UART2,
S700_MUX_SPI3,
S700_MUX_PWM2,
S700_MUX_UART5,
S700_MUX_ETH_SGMII };
/* rgmii_rxd0 */
static unsigned int rgmii_rxd0_mfp_pads[] = { ETH_RXD0 };
static unsigned int rgmii_rxd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_UART2,
S700_MUX_SPI3,
S700_MUX_PWM3,
S700_MUX_UART5,
S700_MUX_ETH_SGMII };
/* rgmii_ref_clk */
static unsigned int rgmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
static unsigned int rgmii_ref_clk_mfp_funcs[] = { S700_MUX_ETH_RGMII,
S700_MUX_UART4,
S700_MUX_SPI2,
S700_MUX_RESERVED,
S700_MUX_ETH_SGMII };
/* i2s_d0 */
static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
static unsigned int i2s_d0_mfp_funcs[] = { S700_MUX_I2S0,
S700_MUX_NOR };
/* i2s_pcm1 */
static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0,
I2S_MCLK0 };
static unsigned int i2s_pcm1_mfp_funcs[] = { S700_MUX_I2S0,
S700_MUX_NOR,
S700_MUX_PCM1,
S700_MUX_BT };
/* i2s0_pcm0 */
static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };
static unsigned int i2s0_pcm0_mfp_funcs[] = { S700_MUX_I2S0,
S700_MUX_NOR,
S700_MUX_PCM0,
S700_MUX_BT };
/* i2s1_pcm0 */
static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1,
I2S_LRCLK1,
I2S_MCLK1 };
static unsigned int i2s1_pcm0_mfp_funcs[] = { S700_MUX_I2S1,
S700_MUX_NOR,
S700_MUX_PCM0,
S700_MUX_BT };
/* i2s_d1 */
static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
static unsigned int i2s_d1_mfp_funcs[] = { S700_MUX_I2S1,
S700_MUX_NOR };
/* ks_in2 */
static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };
static unsigned int ks_in2_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_NOR,
S700_MUX_BT,
S700_MUX_PWM0,
S700_MUX_SENS1,
S700_MUX_PWM0,
S700_MUX_P0 };
/* ks_in1 */
static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };
static unsigned int ks_in1_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_NOR,
S700_MUX_BT,
S700_MUX_PWM5,
S700_MUX_SENS1,
S700_MUX_PWM1,
S700_MUX_USB30 };
/* ks_in0 */
static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };
static unsigned int ks_in0_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_NOR,
S700_MUX_BT,
S700_MUX_PWM4,
S700_MUX_SENS1,
S700_MUX_PWM4,
S700_MUX_P0 };
/* ks_in3 */
static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };
static unsigned int ks_in3_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_NOR,
S700_MUX_PWM1,
S700_MUX_BT,
S700_MUX_SENS1 };
/* ks_out0 */
static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };
static unsigned int ks_out0_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_UART5,
S700_MUX_NOR,
S700_MUX_PWM2,
S700_MUX_BT,
S700_MUX_SENS1,
S700_MUX_SD0,
S700_MUX_UART4 };
/* ks_out1 */
static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };
static unsigned int ks_out1_mfp_funcs[] = { S700_MUX_KS,
S700_MUX_JTAG,
S700_MUX_NOR,
S700_MUX_PWM3,
S700_MUX_BT,
S700_MUX_SENS1,
S700_MUX_SD0,
S700_MUX_UART4 };
/* ks_out2 */
static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };
static unsigned int ks_out2_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_KS,
S700_MUX_NOR,
S700_MUX_PWM2,
S700_MUX_UART5,
S700_MUX_SENS1,
S700_MUX_BT };
/* lvds_o_pn */
static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP,
LVDS_OEN,
LVDS_ODP,
LVDS_ODN,
LVDS_OCP,
LVDS_OCN,
LVDS_OBP,
LVDS_OBN,
LVDS_OAP,
LVDS_OAN };
static unsigned int lvds_o_pn_mfp_funcs[] = { S700_MUX_LVDS,
S700_MUX_BT,
S700_MUX_LCD0 };
/* dsi_dn0 */
static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };
static unsigned int dsi_dn0_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_UART2,
S700_MUX_SPI0 };
/* dsi_dp2 */
static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };
static unsigned int dsi_dp2_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_UART2,
S700_MUX_SPI0,
S700_MUX_SD1 };
/* lcd0_d2 */
static unsigned int lcd0_d2_mfp_pads[] = { LCD0_D2 };
static unsigned int lcd0_d2_mfp_funcs[] = { S700_MUX_NOR,
S700_MUX_SD0,
S700_MUX_RESERVED,
S700_MUX_PWM3,
S700_MUX_LCD0 };
/* dsi_dp3 */
static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };
static unsigned int dsi_dp3_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_SD0,
S700_MUX_SD1,
S700_MUX_LCD0 };
/* dsi_dn3 */
static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };
static unsigned int dsi_dn3_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_SD0,
S700_MUX_SD1,
S700_MUX_LCD0 };
/* dsi_dp0 */
static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };
static unsigned int dsi_dp0_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_RESERVED,
S700_MUX_SD0,
S700_MUX_UART2,
S700_MUX_SPI0 };
/* lvds_ee_pn */
static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP,
LVDS_EEN };
static unsigned int lvds_ee_pn_mfp_funcs[] = { S700_MUX_LVDS,
S700_MUX_NOR,
S700_MUX_BT,
S700_MUX_LCD0 };
/* uart2_rx_tx */
static unsigned int uart2_rx_tx_mfp_pads[] = { UART2_RX,
UART2_TX };
static unsigned int uart2_rx_tx_mfp_funcs[] = { S700_MUX_UART2,
S700_MUX_NOR,
S700_MUX_SPI0,
S700_MUX_PCM0 };
/* spi0_i2c_pcm */
static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SS,
SPI0_MISO };
static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S700_MUX_SPI0,
S700_MUX_NOR,
S700_MUX_I2S1,
S700_MUX_PCM1,
S700_MUX_PCM0,
S700_MUX_I2C2 };
/* mfp2_31 reserved */
/* dsi_dnp1_cp_d2 */
static unsigned int dsi_dnp1_cp_d2_mfp_pads[] = { DSI_DP1,
DSI_CP,
DSI_CN };
static unsigned int dsi_dnp1_cp_d2_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_LCD0,
S700_MUX_RESERVED };
/* dsi_dnp1_cp_d17 */
static unsigned int dsi_dnp1_cp_d17_mfp_pads[] = { DSI_DP1,
DSI_CP,
DSI_CN };
static unsigned int dsi_dnp1_cp_d17_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_RESERVED,
S700_MUX_LCD0 };
/* lvds_e_pn */
static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP,
LVDS_EDN,
LVDS_ECP,
LVDS_ECN,
LVDS_EBP,
LVDS_EBN,
LVDS_EAP,
LVDS_EAN };
static unsigned int lvds_e_pn_mfp_funcs[] = { S700_MUX_LVDS,
S700_MUX_NOR,
S700_MUX_LCD0 };
/* dsi_dn2 */
static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };
static unsigned int dsi_dn2_mfp_funcs[] = { S700_MUX_DSI,
S700_MUX_RESERVED,
S700_MUX_SD1,
S700_MUX_UART2,
S700_MUX_SPI0 };
/* uart2_rtsb */
static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
static unsigned int uart2_rtsb_mfp_funcs[] = { S700_MUX_UART2,
S700_MUX_UART0 };
/* uart2_ctsb */
static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
static unsigned int uart2_ctsb_mfp_funcs[] = { S700_MUX_UART2,
S700_MUX_UART0 };
/* uart3_rtsb */
static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
static unsigned int uart3_rtsb_mfp_funcs[] = { S700_MUX_UART3,
S700_MUX_UART5 };
/* uart3_ctsb */
static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
static unsigned int uart3_ctsb_mfp_funcs[] = { S700_MUX_UART3,
S700_MUX_UART5 };
/* sd0_d0 */
static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
static unsigned int sd0_d0_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_NOR,
S700_MUX_RESERVED,
S700_MUX_JTAG,
S700_MUX_UART2,
S700_MUX_UART5 };
/* sd0_d1 */
static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
static unsigned int sd0_d1_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_NOR,
S700_MUX_RESERVED,
S700_MUX_RESERVED,
S700_MUX_UART2,
S700_MUX_UART5 };
/* sd0_d2_d3 */
static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
SD0_D3 };
static unsigned int sd0_d2_d3_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_NOR,
S700_MUX_RESERVED,
S700_MUX_JTAG,
S700_MUX_UART2,
S700_MUX_UART1 };
/* sd1_d0_d3 */
static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0,
SD1_D1,
SD1_D2,
SD1_D3 };
static unsigned int sd1_d0_d3_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_NOR,
S700_MUX_RESERVED,
S700_MUX_SD1 };
/* sd0_cmd */
static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
static unsigned int sd0_cmd_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_NOR,
S700_MUX_RESERVED,
S700_MUX_JTAG };
/* sd0_clk */
static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
static unsigned int sd0_clk_mfp_funcs[] = { S700_MUX_SD0,
S700_MUX_RESERVED,
S700_MUX_JTAG };
/* sd1_cmd */
static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };
static unsigned int sd1_cmd_mfp_funcs[] = { S700_MUX_SD1,
S700_MUX_NOR };
/* uart0_rx */
static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
static unsigned int uart0_rx_mfp_funcs[] = { S700_MUX_UART0,
S700_MUX_UART2,
S700_MUX_SPI1,
S700_MUX_I2C0,
S700_MUX_PCM1,
S700_MUX_I2S1 };
/* dnand_data_wr1 reserved */
/* clko_25m */
static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };
static unsigned int clko_25m_mfp_funcs[] = { S700_MUX_RESERVED,
S700_MUX_CLKO_25M };
/* csi_cn_cp */
static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN,
CSI_CP };
static unsigned int csi_cn_cp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
S700_MUX_SENS0 };
/* dnand_acle_ce07_24 reserved */
/* sens0_ckout */
static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };
static unsigned int sens0_ckout_mfp_funcs[] = { S700_MUX_SENS0,
S700_MUX_NOR,
S700_MUX_SENS1,
S700_MUX_PWM1 };
/* uart0_tx */
static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
static unsigned int uart0_tx_mfp_funcs[] = { S700_MUX_UART0,
S700_MUX_UART2,
S700_MUX_SPI1,
S700_MUX_I2C0,
S700_MUX_SPDIF,
S700_MUX_PCM1,
S700_MUX_I2S1 };
/* i2c0_mfp */
static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,
I2C0_SDATA };
static unsigned int i2c0_mfp_funcs[] = { S700_MUX_I2C0,
S700_MUX_UART2,
S700_MUX_I2C1,
S700_MUX_UART1,
S700_MUX_SPI1 };
/* csi_dn_dp */
static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0,
CSI_DN1,
CSI_DN2,
CSI_DN3,
CSI_DP0,
CSI_DP1,
CSI_DP2,
CSI_DP3 };
static unsigned int csi_dn_dp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
S700_MUX_SENS0 };
/* sen0_pclk */
static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };
static unsigned int sen0_pclk_mfp_funcs[] = { S700_MUX_SENS0,
S700_MUX_NOR,
S700_MUX_PWM0 };
/* pcm1_in */
static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };
static unsigned int pcm1_in_mfp_funcs[] = { S700_MUX_PCM1,
S700_MUX_SENS1,
S700_MUX_BT,
S700_MUX_PWM4 };
/* pcm1_clk */
static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
static unsigned int pcm1_clk_mfp_funcs[] = { S700_MUX_PCM1,
S700_MUX_SENS1,
S700_MUX_BT,
S700_MUX_PWM5 };
/* pcm1_sync */
static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
static unsigned int pcm1_sync_mfp_funcs[] = { S700_MUX_PCM1,
S700_MUX_SENS1,
S700_MUX_BT,
S700_MUX_I2C3 };
/* pcm1_out */
static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };
static unsigned int pcm1_out_mfp_funcs[] = { S700_MUX_PCM1,
S700_MUX_SENS1,
S700_MUX_BT,
S700_MUX_I2C3 };
/* dnand_data_wr */
static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0,
DNAND_D1,
DNAND_D2,
DNAND_D3,
DNAND_D4,
DNAND_D5,
DNAND_D6,
DNAND_D7,
DNAND_RDB,
DNAND_RDBN };
static unsigned int dnand_data_wr_mfp_funcs[] = { S700_MUX_NAND,
S700_MUX_SD2 };
/* dnand_acle_ce0 */
static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,
DNAND_CLE,
DNAND_CEB0,
DNAND_CEB1 };
static unsigned int dnand_acle_ce0_mfp_funcs[] = { S700_MUX_NAND,
S700_MUX_SPI2 };
/* nand_ceb2 */
static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };
static unsigned int nand_ceb2_mfp_funcs[] = { S700_MUX_NAND,
S700_MUX_PWM5 };
/* nand_ceb3 */
static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };
static unsigned int nand_ceb3_mfp_funcs[] = { S700_MUX_NAND,
S700_MUX_PWM4 };
/*****End MFP group data****************************/
/*****PADDRV group data****************************/
/*PAD_DRV0*/
static unsigned int sirq_drv_pads[] = { SIRQ0,
SIRQ1,
SIRQ2 };
static unsigned int rgmii_txd23_drv_pads[] = { ETH_TXD2,
ETH_TXD3 };
static unsigned int rgmii_rxd23_drv_pads[] = { ETH_RXD2,
ETH_RXD3 };
static unsigned int rgmii_txd01_txen_drv_pads[] = { ETH_TXD0,
ETH_TXD1,
ETH_TXEN };
static unsigned int rgmii_rxer_drv_pads[] = { ETH_RXER };
static unsigned int rgmii_crs_drv_pads[] = { ETH_CRS_DV };
static unsigned int rgmii_rxd10_drv_pads[] = { ETH_RXD0,
ETH_RXD1 };
static unsigned int rgmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC,
ETH_MDIO };
static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };
static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };
static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0,
I2S_MCLK0,
I2S_D1 };
static unsigned int i2s13_drv_pads[] = { I2S_BCLK1,
I2S_LRCLK1,
I2S_MCLK1 };
static unsigned int pcm1_drv_pads[] = { PCM1_IN,
PCM1_CLK,
PCM1_SYNC,
PCM1_OUT };
static unsigned int ks_in_drv_pads[] = { KS_IN0,
KS_IN1,
KS_IN2,
KS_IN3 };
/*PAD_DRV1*/
static unsigned int ks_out_drv_pads[] = { KS_OUT0,
KS_OUT1,
KS_OUT2 };
static unsigned int lvds_all_drv_pads[] = { LVDS_OEP,
LVDS_OEN,
LVDS_ODP,
LVDS_ODN,
LVDS_OCP,
LVDS_OCN,
LVDS_OBP,
LVDS_OBN,
LVDS_OAP,
LVDS_OAN,
LVDS_EEP,
LVDS_EEN,
LVDS_EDP,
LVDS_EDN,
LVDS_ECP,
LVDS_ECN,
LVDS_EBP,
LVDS_EBN,
LVDS_EAP,
LVDS_EAN };
static unsigned int lcd_d18_d2_drv_pads[] = { LCD0_D18,
LCD0_D2 };
static unsigned int dsi_all_drv_pads[] = { DSI_DP0,
DSI_DN0,
DSI_DP2,
DSI_DN2,
DSI_DP3,
DSI_DN3,
DSI_DP1,
DSI_DN1,
DSI_CP,
DSI_CN };
static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0,
SD0_D1,
SD0_D2,
SD0_D3 };
static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };
static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };
static unsigned int spi0_all_drv_pads[] = { SPI0_SS,
SPI0_MISO };
/*PAD_DRV2*/
static unsigned int uart0_rx_drv_pads[] = { UART0_RX };
static unsigned int uart0_tx_drv_pads[] = { UART0_TX };
static unsigned int uart2_all_drv_pads[] = { UART2_RX,
UART2_TX,
UART2_RTSB,
UART2_CTSB };
static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK,
I2C0_SDATA };
static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK,
I2C1_SDATA,
I2C2_SCLK,
I2C2_SDATA };
static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };
static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };
static unsigned int uart3_all_drv_pads[] = { UART3_RX,
UART3_TX,
UART3_RTSB,
UART3_CTSB };
/* all pinctrl groups of S700 board */
static const struct owl_pingroup s700_groups[] = {
MUX_PG(rgmii_txd23_mfp, 0, 28, 2),
MUX_PG(rgmii_rxd2_mfp, 0, 26, 2),
MUX_PG(rgmii_rxd3_mfp, 0, 26, 2),
MUX_PG(lcd0_d18_mfp, 0, 23, 3),
MUX_PG(rgmii_txd01_mfp, 0, 20, 3),
MUX_PG(rgmii_txd0_mfp, 0, 16, 3),
MUX_PG(rgmii_txd1_mfp, 0, 16, 3),
MUX_PG(rgmii_txen_mfp, 0, 13, 3),
MUX_PG(rgmii_rxen_mfp, 0, 13, 3),
MUX_PG(rgmii_rxd1_mfp, 0, 8, 3),
MUX_PG(rgmii_rxd0_mfp, 0, 8, 3),
MUX_PG(rgmii_ref_clk_mfp, 0, 6, 2),
MUX_PG(i2s_d0_mfp, 0, 5, 1),
MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
MUX_PG(i2s_d1_mfp, 0, 0, 1),
MUX_PG(ks_in2_mfp, 1, 29, 3),
MUX_PG(ks_in1_mfp, 1, 29, 3),
MUX_PG(ks_in0_mfp, 1, 29, 3),
MUX_PG(ks_in3_mfp, 1, 26, 3),
MUX_PG(ks_out0_mfp, 1, 26, 3),
MUX_PG(ks_out1_mfp, 1, 26, 3),
MUX_PG(ks_out2_mfp, 1, 23, 3),
MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
MUX_PG(dsi_dn0_mfp, 1, 19, 2),
MUX_PG(dsi_dp2_mfp, 1, 17, 2),
MUX_PG(lcd0_d2_mfp, 1, 14, 3),
MUX_PG(dsi_dp3_mfp, 1, 12, 2),
MUX_PG(dsi_dn3_mfp, 1, 10, 2),
MUX_PG(dsi_dp0_mfp, 1, 7, 3),
MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
MUX_PG(uart2_rx_tx_mfp, 1, 3, 2),
MUX_PG(spi0_i2c_pcm_mfp, 1, 0, 3),
MUX_PG(dsi_dnp1_cp_d2_mfp, 2, 29, 2),
MUX_PG(dsi_dnp1_cp_d17_mfp, 2, 29, 2),
MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
MUX_PG(dsi_dn2_mfp, 2, 24, 3),
MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
MUX_PG(sd0_d0_mfp, 2, 17, 3),
MUX_PG(sd0_d1_mfp, 2, 14, 3),
MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
MUX_PG(sd0_cmd_mfp, 2, 7, 2),
MUX_PG(sd0_clk_mfp, 2, 5, 2),
MUX_PG(sd1_cmd_mfp, 2, 3, 2),
MUX_PG(uart0_rx_mfp, 2, 0, 3),
MUX_PG(clko_25m_mfp, 3, 30, 1),
MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
MUX_PG(sens0_ckout_mfp, 3, 22, 2),
MUX_PG(uart0_tx_mfp, 3, 19, 3),
MUX_PG(i2c0_mfp, 3, 16, 3),
MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
MUX_PG(sen0_pclk_mfp, 3, 12, 2),
MUX_PG(pcm1_in_mfp, 3, 10, 2),
MUX_PG(pcm1_clk_mfp, 3, 8, 2),
MUX_PG(pcm1_sync_mfp, 3, 6, 2),
MUX_PG(pcm1_out_mfp, 3, 4, 2),
MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
MUX_PG(nand_ceb2_mfp, 3, 0, 2),
MUX_PG(nand_ceb3_mfp, 3, 0, 2),
DRV_PG(sirq_drv, 0, 28, 2),
DRV_PG(rgmii_txd23_drv, 0, 26, 2),
DRV_PG(rgmii_rxd23_drv, 0, 24, 2),
DRV_PG(rgmii_txd01_txen_drv, 0, 22, 2),
DRV_PG(rgmii_rxer_drv, 0, 20, 2),
DRV_PG(rgmii_crs_drv, 0, 18, 2),
DRV_PG(rgmii_rxd10_drv, 0, 16, 2),
DRV_PG(rgmii_ref_clk_drv, 0, 14, 2),
DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
DRV_PG(i2s_d0_drv, 0, 10, 2),
DRV_PG(i2s_bclk0_drv, 0, 8, 2),
DRV_PG(i2s3_drv, 0, 6, 2),
DRV_PG(i2s13_drv, 0, 4, 2),
DRV_PG(pcm1_drv, 0, 2, 2),
DRV_PG(ks_in_drv, 0, 0, 2),
DRV_PG(ks_out_drv, 1, 30, 2),
DRV_PG(lvds_all_drv, 1, 28, 2),
DRV_PG(lcd_d18_d2_drv, 1, 26, 2),
DRV_PG(dsi_all_drv, 1, 24, 2),
DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
DRV_PG(sd0_cmd_drv, 1, 18, 2),
DRV_PG(sd0_clk_drv, 1, 16, 2),
DRV_PG(spi0_all_drv, 1, 10, 2),
DRV_PG(uart0_rx_drv, 2, 30, 2),
DRV_PG(uart0_tx_drv, 2, 28, 2),
DRV_PG(uart2_all_drv, 2, 26, 2),
DRV_PG(i2c0_all_drv, 2, 23, 2),
DRV_PG(i2c12_all_drv, 2, 21, 2),
DRV_PG(sens0_pclk_drv, 2, 18, 2),
DRV_PG(sens0_ckout_drv, 2, 12, 2),
DRV_PG(uart3_all_drv, 2, 2, 2),
};
static const char * const nor_groups[] = {
"lcd0_d18_mfp",
"i2s_d0_mfp",
"i2s0_pcm0_mfp",
"i2s1_pcm0_mfp",
"i2s_d1_mfp",
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"lcd0_d2_mfp",
"lvds_ee_pn_mfp",
"uart2_rx_tx_mfp",
"spi0_i2c_pcm_mfp",
"lvds_e_pn_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd1_d0_d3_mfp",
"sd0_cmd_mfp",
"sd1_cmd_mfp",
"sens0_ckout_mfp",
"sen0_pclk_mfp",
};
static const char * const eth_rmii_groups[] = {
"rgmii_txd23_mfp",
"rgmii_rxd2_mfp",
"rgmii_rxd3_mfp",
"rgmii_txd01_mfp",
"rgmii_txd0_mfp",
"rgmii_txd1_mfp",
"rgmii_txen_mfp",
"rgmii_rxen_mfp",
"rgmii_rxd1_mfp",
"rgmii_rxd0_mfp",
"rgmii_ref_clk_mfp",
"eth_smi_dummy",
};
static const char * const eth_smii_groups[] = {
"rgmii_txd0_mfp",
"rgmii_txd1_mfp",
"rgmii_rxd0_mfp",
"rgmii_rxd1_mfp",
"rgmii_ref_clk_mfp",
"eth_smi_dummy",
};
static const char * const spi0_groups[] = {
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp0_mfp",
"uart2_rx_tx_mfp",
"spi0_i2c_pcm_mfp",
"dsi_dn2_mfp",
};
static const char * const spi1_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const spi2_groups[] = {
"rgmii_txd01_mfp",
"rgmii_txd0_mfp",
"rgmii_txd1_mfp",
"rgmii_ref_clk_mfp",
"dnand_acle_ce0_mfp",
};
static const char * const spi3_groups[] = {
"rgmii_txen_mfp",
"rgmii_rxen_mfp",
"rgmii_rxd1_mfp",
"rgmii_rxd0_mfp",
};
static const char * const sens0_groups[] = {
"csi_cn_cp_mfp",
"sens0_ckout_mfp",
"csi_dn_dp_mfp",
"sen0_pclk_mfp",
};
static const char * const sens1_groups[] = {
"lcd0_d18_mfp",
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"sens0_ckout_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const uart0_groups[] = {
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const uart1_groups[] = {
"sd0_d2_d3_mfp",
"i2c0_mfp",
};
static const char * const uart2_groups[] = {
"rgmii_txen_mfp",
"rgmii_rxen_mfp",
"rgmii_rxd1_mfp",
"rgmii_rxd0_mfp",
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp0_mfp",
"uart2_rx_tx_mfp",
"dsi_dn2_mfp",
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
"uart2_dummy"
};
static const char * const uart3_groups[] = {
"rgmii_txd23_mfp",
"rgmii_rxd2_mfp",
"rgmii_rxd3_mfp",
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
"uart3_dummy"
};
static const char * const uart4_groups[] = {
"rgmii_txd01_mfp",
"rgmii_ref_clk_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
};
static const char * const uart5_groups[] = {
"rgmii_rxd1_mfp",
"rgmii_rxd0_mfp",
"ks_out0_mfp",
"ks_out2_mfp",
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
};
static const char * const uart6_groups[] = {
"rgmii_txd0_mfp",
"rgmii_txd1_mfp",
};
static const char * const i2s0_groups[] = {
"i2s_d0_mfp",
"i2s_pcm1_mfp",
"i2s0_pcm0_mfp",
};
static const char * const i2s1_groups[] = {
"i2s1_pcm0_mfp",
"i2s_d1_mfp",
"i2s1_dummy",
"spi0_i2c_pcm_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const pcm1_groups[] = {
"i2s_pcm1_mfp",
"spi0_i2c_pcm_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const pcm0_groups[] = {
"i2s0_pcm0_mfp",
"i2s1_pcm0_mfp",
"uart2_rx_tx_mfp",
"spi0_i2c_pcm_mfp",
};
static const char * const ks_groups[] = {
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
};
static const char * const jtag_groups[] = {
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out1_mfp",
"sd0_d0_mfp",
"sd0_d2_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const pwm0_groups[] = {
"rgmii_rxd2_mfp",
"rgmii_txen_mfp",
"ks_in2_mfp",
"sen0_pclk_mfp",
};
static const char * const pwm1_groups[] = {
"rgmii_rxen_mfp",
"ks_in1_mfp",
"ks_in3_mfp",
"sens0_ckout_mfp",
};
static const char * const pwm2_groups[] = {
"lcd0_d18_mfp",
"rgmii_rxd3_mfp",
"rgmii_rxd1_mfp",
"ks_out0_mfp",
"ks_out2_mfp",
};
static const char * const pwm3_groups[] = {
"rgmii_rxd0_mfp",
"ks_out1_mfp",
"lcd0_d2_mfp",
};
static const char * const pwm4_groups[] = {
"lcd0_d18_mfp",
"rgmii_txd01_mfp",
"rgmii_txd0_mfp",
"ks_in0_mfp",
"pcm1_in_mfp",
"nand_ceb3_mfp",
};
static const char * const pwm5_groups[] = {
"rgmii_txd1_mfp",
"ks_in1_mfp",
"pcm1_clk_mfp",
"nand_ceb2_mfp",
};
static const char * const p0_groups[] = {
"ks_in2_mfp",
"ks_in0_mfp",
};
static const char * const sd0_groups[] = {
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"lcd0_d2_mfp",
"dsi_dp3_mfp",
"dsi_dp0_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd1_d0_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const sd1_groups[] = {
"dsi_dp2_mfp",
"mfp1_16_14_mfp",
"lcd0_d2_mfp",
"mfp1_16_14_d17_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"dsi_dnp1_cp_d2_mfp",
"dsi_dnp1_cp_d17_mfp",
"dsi_dn2_mfp",
"sd1_d0_d3_mfp",
"sd1_cmd_mfp",
"sd1_dummy",
};
static const char * const sd2_groups[] = {
"dnand_data_wr_mfp",
};
static const char * const i2c0_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const i2c1_groups[] = {
"i2c0_mfp",
"i2c1_dummy"
};
static const char * const i2c2_groups[] = {
"i2c2_dummy"
};
static const char * const i2c3_groups[] = {
"uart2_rx_tx_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const lvds_groups[] = {
"lvds_o_pn_mfp",
"lvds_ee_pn_mfp",
"lvds_e_pn_mfp",
};
static const char * const bt_groups[] = {
"i2s_pcm1_mfp",
"i2s0_pcm0_mfp",
"i2s1_pcm0_mfp",
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"lvds_o_pn_mfp",
"lvds_ee_pn_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const lcd0_groups[] = {
"lcd0_d18_mfp",
"lcd0_d2_mfp",
"mfp1_16_14_d17_mfp",
"lvds_o_pn_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"lvds_ee_pn_mfp",
"dsi_dnp1_cp_d2_mfp",
"dsi_dnp1_cp_d17_mfp",
"lvds_e_pn_mfp",
};
static const char * const usb30_groups[] = {
"ks_in1_mfp",
};
static const char * const clko_25m_groups[] = {
"clko_25m_mfp",
};
static const char * const mipi_csi_groups[] = {
"csi_cn_cp_mfp",
"csi_dn_dp_mfp",
};
static const char * const dsi_groups[] = {
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"dsi_dp0_mfp",
"dsi_dnp1_cp_d2_mfp",
"dsi_dnp1_cp_d17_mfp",
"dsi_dn2_mfp",
"dsi_dummy",
};
static const char * const nand_groups[] = {
"dnand_data_wr_mfp",
"dnand_acle_ce0_mfp",
"nand_ceb2_mfp",
"nand_ceb3_mfp",
"nand_dummy",
};
static const char * const spdif_groups[] = {
"uart0_tx_mfp",
};
static const char * const sirq0_groups[] = {
"sirq0_dummy",
};
static const char * const sirq1_groups[] = {
"sirq1_dummy",
};
static const char * const sirq2_groups[] = {
"sirq2_dummy",
};
static const struct owl_pinmux_func s700_functions[] = {
[S700_MUX_NOR] = FUNCTION(nor),
[S700_MUX_ETH_RGMII] = FUNCTION(eth_rmii),
[S700_MUX_ETH_SGMII] = FUNCTION(eth_smii),
[S700_MUX_SPI0] = FUNCTION(spi0),
[S700_MUX_SPI1] = FUNCTION(spi1),
[S700_MUX_SPI2] = FUNCTION(spi2),
[S700_MUX_SPI3] = FUNCTION(spi3),
[S700_MUX_SENS0] = FUNCTION(sens0),
[S700_MUX_SENS1] = FUNCTION(sens1),
[S700_MUX_UART0] = FUNCTION(uart0),
[S700_MUX_UART1] = FUNCTION(uart1),
[S700_MUX_UART2] = FUNCTION(uart2),
[S700_MUX_UART3] = FUNCTION(uart3),
[S700_MUX_UART4] = FUNCTION(uart4),
[S700_MUX_UART5] = FUNCTION(uart5),
[S700_MUX_UART6] = FUNCTION(uart6),
[S700_MUX_I2S0] = FUNCTION(i2s0),
[S700_MUX_I2S1] = FUNCTION(i2s1),
[S700_MUX_PCM1] = FUNCTION(pcm1),
[S700_MUX_PCM0] = FUNCTION(pcm0),
[S700_MUX_KS] = FUNCTION(ks),
[S700_MUX_JTAG] = FUNCTION(jtag),
[S700_MUX_PWM0] = FUNCTION(pwm0),
[S700_MUX_PWM1] = FUNCTION(pwm1),
[S700_MUX_PWM2] = FUNCTION(pwm2),
[S700_MUX_PWM3] = FUNCTION(pwm3),
[S700_MUX_PWM4] = FUNCTION(pwm4),
[S700_MUX_PWM5] = FUNCTION(pwm5),
[S700_MUX_P0] = FUNCTION(p0),
[S700_MUX_SD0] = FUNCTION(sd0),
[S700_MUX_SD1] = FUNCTION(sd1),
[S700_MUX_SD2] = FUNCTION(sd2),
[S700_MUX_I2C0] = FUNCTION(i2c0),
[S700_MUX_I2C1] = FUNCTION(i2c1),
[S700_MUX_I2C2] = FUNCTION(i2c2),
[S700_MUX_I2C3] = FUNCTION(i2c3),
[S700_MUX_DSI] = FUNCTION(dsi),
[S700_MUX_LVDS] = FUNCTION(lvds),
[S700_MUX_USB30] = FUNCTION(usb30),
[S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
[S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
[S700_MUX_NAND] = FUNCTION(nand),
[S700_MUX_SPDIF] = FUNCTION(spdif),
[S700_MUX_SIRQ0] = FUNCTION(sirq0),
[S700_MUX_SIRQ1] = FUNCTION(sirq1),
[S700_MUX_SIRQ2] = FUNCTION(sirq2),
[S700_MUX_BT] = FUNCTION(bt),
[S700_MUX_LCD0] = FUNCTION(lcd0),
};
/* PAD_ST0 */
static PAD_ST_CONF(UART2_TX, 0, 31, 1);
static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
static PAD_ST_CONF(UART0_RX, 0, 29, 1);
static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
static PAD_ST_CONF(UART0_TX, 0, 14, 1);
static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
static PAD_ST_CONF(KS_IN0, 0, 11, 1);
static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
static PAD_ST_CONF(ETH_TXD3, 0, 3, 1);
static PAD_ST_CONF(ETH_TXD2, 0, 2, 1);
/* PAD_ST1 */
static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
static PAD_ST_CONF(UART3_RX, 1, 25, 1);
static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
static PAD_ST_CONF(UART2_RX, 1, 22, 1);
static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
static PAD_PULLCTL_CONF(LCD0_D2, 0, 27, 1);
static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
/* PAD_PULLCTL1 */
static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
/* PAD_PULLCTL2 */
static PAD_PULLCTL_CONF(ETH_TXD2, 2, 18, 1);
static PAD_PULLCTL_CONF(ETH_TXD3, 2, 17, 1);
static PAD_PULLCTL_CONF(SPI0_SS, 2, 16, 1);
static PAD_PULLCTL_CONF(SPI0_MISO, 2, 15, 1);
static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
/* Pad info table for the pinmux subsystem */
static const struct owl_padinfo s700_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
[ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
[ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
[ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
[ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
[ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
[ETH_MDC] = PAD_INFO(ETH_MDC),
[ETH_MDIO] = PAD_INFO(ETH_MDIO),
[SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
[SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
[SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
[I2S_D0] = PAD_INFO(I2S_D0),
[I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
[I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
[I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
[I2S_D1] = PAD_INFO(I2S_D1),
[I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
[I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
[I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
[KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
[KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
[KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
[KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
[KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
[KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
[KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
[LVDS_OEP] = PAD_INFO(LVDS_OEP),
[LVDS_OEN] = PAD_INFO(LVDS_OEN),
[LVDS_ODP] = PAD_INFO(LVDS_ODP),
[LVDS_ODN] = PAD_INFO(LVDS_ODN),
[LVDS_OCP] = PAD_INFO(LVDS_OCP),
[LVDS_OCN] = PAD_INFO(LVDS_OCN),
[LVDS_OBP] = PAD_INFO(LVDS_OBP),
[LVDS_OBN] = PAD_INFO(LVDS_OBN),
[LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
[LVDS_OAN] = PAD_INFO(LVDS_OAN),
[LVDS_EEP] = PAD_INFO(LVDS_EEP),
[LVDS_EEN] = PAD_INFO(LVDS_EEN),
[LVDS_EDP] = PAD_INFO(LVDS_EDP),
[LVDS_EDN] = PAD_INFO(LVDS_EDN),
[LVDS_ECP] = PAD_INFO(LVDS_ECP),
[LVDS_ECN] = PAD_INFO(LVDS_ECN),
[LVDS_EBP] = PAD_INFO(LVDS_EBP),
[LVDS_EBN] = PAD_INFO(LVDS_EBN),
[LVDS_EAP] = PAD_INFO(LVDS_EAP),
[LVDS_EAN] = PAD_INFO(LVDS_EAN),
[LCD0_D18] = PAD_INFO(LCD0_D18),
[LCD0_D2] = PAD_INFO_PULLCTL(LCD0_D2),
[DSI_DP3] = PAD_INFO(DSI_DP3),
[DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
[DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
[DSI_DN1] = PAD_INFO(DSI_DN1),
[DSI_DP0] = PAD_INFO_ST(DSI_DP0),
[DSI_DN0] = PAD_INFO_ST(DSI_DN0),
[DSI_DP2] = PAD_INFO_ST(DSI_DP2),
[DSI_DN2] = PAD_INFO_ST(DSI_DN2),
[SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
[SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
[SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
[SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
[SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
[SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
[SD1_CLK] = PAD_INFO(SD1_CLK),
[SPI0_SS] = PAD_INFO_PULLCTL_ST(SPI0_SS),
[SPI0_MISO] = PAD_INFO_PULLCTL_ST(SPI0_MISO),
[UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
[UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
[I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
[I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
[SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
[SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
[DNAND_ALE] = PAD_INFO(DNAND_ALE),
[DNAND_CLE] = PAD_INFO(DNAND_CLE),
[DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
[DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
[DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
[DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
[UART2_RX] = PAD_INFO_ST(UART2_RX),
[UART2_TX] = PAD_INFO_ST(UART2_TX),
[UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
[UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
[UART3_RX] = PAD_INFO_ST(UART3_RX),
[UART3_TX] = PAD_INFO(UART3_TX),
[UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
[UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
[PCM1_IN] = PAD_INFO_ST(PCM1_IN),
[PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
[PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
[PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
[I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
[I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
[I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
[I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
[CSI_DN0] = PAD_INFO(CSI_DN0),
[CSI_DP0] = PAD_INFO(CSI_DP0),
[CSI_DN1] = PAD_INFO(CSI_DN1),
[CSI_DP1] = PAD_INFO(CSI_DP1),
[CSI_CN] = PAD_INFO(CSI_CN),
[CSI_CP] = PAD_INFO(CSI_CP),
[CSI_DN2] = PAD_INFO(CSI_DN2),
[CSI_DP2] = PAD_INFO(CSI_DP2),
[CSI_DN3] = PAD_INFO(CSI_DN3),
[CSI_DP3] = PAD_INFO(CSI_DP3),
[DNAND_WRB] = PAD_INFO(DNAND_WRB),
[DNAND_RDB] = PAD_INFO(DNAND_RDB),
[DNAND_RB0] = PAD_INFO(DNAND_RB0),
[PORB] = PAD_INFO(PORB),
[CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
[BSEL] = PAD_INFO(BSEL),
[PKG0] = PAD_INFO(PKG0),
[PKG1] = PAD_INFO(PKG1),
[PKG2] = PAD_INFO(PKG2),
[PKG3] = PAD_INFO(PKG3),
[ETH_TXD2] = PAD_INFO_PULLCTL_ST(ETH_TXD2),
[ETH_TXD3] = PAD_INFO_PULLCTL_ST(ETH_TXD3),
};
static const struct owl_gpio_port s700_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x204, 0x210, 0x214, 0x238, 1),
OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x204, 0x218, 0x21C, 0x240, 2),
OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x204, 0x220, 0x224, 0x248, 3),
/* 0x24C (INTC_GPIOD_TYPE1) used to tweak the driver to handle generic */
OWL_GPIO_PORT(E, 0x0030, 8, 0x0, 0x4, 0x8, 0x204, 0x228, 0x22C, 0x24C, 4),
};
enum s700_pinconf_pull {
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
};
static int s700_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int s700_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static struct owl_pinctrl_soc_data s700_pinctrl_data = {
.padinfo = s700_padinfo,
.pins = (const struct pinctrl_pin_desc *)s700_pads,
.npins = ARRAY_SIZE(s700_pads),
.functions = s700_functions,
.nfunctions = ARRAY_SIZE(s700_functions),
.groups = s700_groups,
.ngroups = ARRAY_SIZE(s700_groups),
.ngpios = NUM_GPIOS,
.ports = s700_gpio_ports,
.nports = ARRAY_SIZE(s700_gpio_ports),
.padctl_arg2val = s700_pad_pinconf_arg2val,
.padctl_val2arg = s700_pad_pinconf_val2arg,
};
static int s700_pinctrl_probe(struct platform_device *pdev)
{
return owl_pinctrl_probe(pdev, &s700_pinctrl_data);
}
static const struct of_device_id s700_pinctrl_of_match[] = {
{ .compatible = "actions,s700-pinctrl", },
{}
};
static struct platform_driver s700_pinctrl_driver = {
.probe = s700_pinctrl_probe,
.driver = {
.name = "pinctrl-s700",
.of_match_table = of_match_ptr(s700_pinctrl_of_match),
},
};
static int __init s700_pinctrl_init(void)
{
return platform_driver_register(&s700_pinctrl_driver);
}
arch_initcall(s700_pinctrl_init);
static void __exit s700_pinctrl_exit(void)
{
platform_driver_unregister(&s700_pinctrl_driver);
}
module_exit(s700_pinctrl_exit);
MODULE_AUTHOR("Actions Semi Inc.");
MODULE_DESCRIPTION("Actions Semi S700 Soc Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/actions/pinctrl-s700.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* OWL SoC's Pinctrl driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Author: David Liu <[email protected]>
*
* Copyright (c) 2018 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-owl.h"
/**
* struct owl_pinctrl - pinctrl state of the device
* @dev: device handle
* @pctrldev: pinctrl handle
* @chip: gpio chip
* @lock: spinlock to protect registers
* @clk: clock control
* @soc: reference to soc_data
* @base: pinctrl register base address
* @num_irq: number of possible interrupts
* @irq: interrupt numbers
*/
struct owl_pinctrl {
struct device *dev;
struct pinctrl_dev *pctrldev;
struct gpio_chip chip;
raw_spinlock_t lock;
struct clk *clk;
const struct owl_pinctrl_soc_data *soc;
void __iomem *base;
unsigned int num_irq;
unsigned int *irq;
};
static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
{
u32 reg_val;
reg_val = readl_relaxed(base);
reg_val = (reg_val & ~mask) | (val & mask);
writel_relaxed(reg_val, base);
}
static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
u32 bit, u32 width)
{
u32 tmp, mask;
tmp = readl_relaxed(pctrl->base + reg);
mask = (1 << width) - 1;
return (tmp >> bit) & mask;
}
static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
u32 bit, u32 width)
{
u32 mask;
mask = (1 << width) - 1;
mask = mask << bit;
owl_update_bits(pctrl->base + reg, mask, (arg << bit));
}
static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->ngroups;
}
static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
unsigned int group)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->groups[group].name;
}
static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
*pins = pctrl->soc->groups[group].pads;
*num_pins = pctrl->soc->groups[group].npads;
return 0;
}
static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
struct seq_file *s,
unsigned int offset)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
seq_printf(s, "%s", dev_name(pctrl->dev));
}
static const struct pinctrl_ops owl_pinctrl_ops = {
.get_groups_count = owl_get_groups_count,
.get_group_name = owl_get_group_name,
.get_group_pins = owl_get_group_pins,
.pin_dbg_show = owl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->nfunctions;
}
static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
unsigned int function)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
return pctrl->soc->functions[function].name;
}
static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
*groups = pctrl->soc->functions[function].groups;
*num_groups = pctrl->soc->functions[function].ngroups;
return 0;
}
static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
int function,
u32 *mask,
u32 *val)
{
int id;
u32 option_num;
u32 option_mask;
for (id = 0; id < g->nfuncs; id++) {
if (g->funcs[id] == function)
break;
}
if (WARN_ON(id == g->nfuncs))
return -EINVAL;
option_num = (1 << g->mfpctl_width);
if (id > option_num)
id -= option_num;
option_mask = option_num - 1;
*mask = (option_mask << g->mfpctl_shift);
*val = (id << g->mfpctl_shift);
return 0;
}
static int owl_set_mux(struct pinctrl_dev *pctrldev,
unsigned int function,
unsigned int group)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_pingroup *g;
unsigned long flags;
u32 val, mask;
g = &pctrl->soc->groups[group];
if (get_group_mfp_mask_val(g, function, &mask, &val))
return -EINVAL;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static const struct pinmux_ops owl_pinmux_ops = {
.get_functions_count = owl_get_funcs_count,
.get_function_name = owl_get_func_name,
.get_function_groups = owl_get_func_groups,
.set_mux = owl_set_mux,
};
static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
unsigned int param,
u32 *reg,
u32 *bit,
u32 *width)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
if (!info->pullctl)
return -EINVAL;
*reg = info->pullctl->reg;
*bit = info->pullctl->shift;
*width = info->pullctl->width;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!info->st)
return -EINVAL;
*reg = info->st->reg;
*bit = info->st->shift;
*width = info->st->width;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
{
int ret = 0;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_padinfo *info;
unsigned int param = pinconf_to_config_param(*config);
u32 reg, bit, width, arg;
info = &pctrl->soc->padinfo[pin];
ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
if (ret)
return ret;
arg = owl_read_field(pctrl, reg, bit, width);
if (!pctrl->soc->padctl_val2arg)
return -ENOTSUPP;
ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return ret;
}
static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *configs,
unsigned int num_configs)
{
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
const struct owl_padinfo *info;
unsigned long flags;
unsigned int param;
u32 reg, bit, width, arg;
int ret = 0, i;
info = &pctrl->soc->padinfo[pin];
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
if (ret)
return ret;
if (!pctrl->soc->padctl_arg2val)
return -ENOTSUPP;
ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_write_field(pctrl, reg, arg, bit, width);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
return ret;
}
static int owl_group_pinconf_reg(const struct owl_pingroup *g,
unsigned int param,
u32 *reg,
u32 *bit,
u32 *width)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
if (g->drv_reg < 0)
return -EINVAL;
*reg = g->drv_reg;
*bit = g->drv_shift;
*width = g->drv_width;
break;
case PIN_CONFIG_SLEW_RATE:
if (g->sr_reg < 0)
return -EINVAL;
*reg = g->sr_reg;
*bit = g->sr_shift;
*width = g->sr_width;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
switch (*arg) {
case 2:
*arg = OWL_PINCONF_DRV_2MA;
break;
case 4:
*arg = OWL_PINCONF_DRV_4MA;
break;
case 8:
*arg = OWL_PINCONF_DRV_8MA;
break;
case 12:
*arg = OWL_PINCONF_DRV_12MA;
break;
default:
return -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
if (*arg)
*arg = OWL_PINCONF_SLEW_FAST;
else
*arg = OWL_PINCONF_SLEW_SLOW;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
switch (*arg) {
case OWL_PINCONF_DRV_2MA:
*arg = 2;
break;
case OWL_PINCONF_DRV_4MA:
*arg = 4;
break;
case OWL_PINCONF_DRV_8MA:
*arg = 8;
break;
case OWL_PINCONF_DRV_12MA:
*arg = 12;
break;
default:
return -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
if (*arg)
*arg = 1;
else
*arg = 0;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_group_config_get(struct pinctrl_dev *pctrldev,
unsigned int group,
unsigned long *config)
{
const struct owl_pingroup *g;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
unsigned int param = pinconf_to_config_param(*config);
u32 reg, bit, width, arg;
int ret;
g = &pctrl->soc->groups[group];
ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
if (ret)
return ret;
arg = owl_read_field(pctrl, reg, bit, width);
ret = owl_group_pinconf_val2arg(g, param, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return ret;
}
static int owl_group_config_set(struct pinctrl_dev *pctrldev,
unsigned int group,
unsigned long *configs,
unsigned int num_configs)
{
const struct owl_pingroup *g;
struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
unsigned long flags;
unsigned int param;
u32 reg, bit, width, arg;
int ret, i;
g = &pctrl->soc->groups[group];
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
if (ret)
return ret;
ret = owl_group_pinconf_arg2val(g, param, &arg);
if (ret)
return ret;
/* Update register */
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_write_field(pctrl, reg, arg, bit, width);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
return 0;
}
static const struct pinconf_ops owl_pinconf_ops = {
.is_generic = true,
.pin_config_get = owl_pin_config_get,
.pin_config_set = owl_pin_config_set,
.pin_config_group_get = owl_group_config_get,
.pin_config_group_set = owl_group_config_set,
};
static struct pinctrl_desc owl_pinctrl_desc = {
.pctlops = &owl_pinctrl_ops,
.pmxops = &owl_pinmux_ops,
.confops = &owl_pinconf_ops,
.owner = THIS_MODULE,
};
static const struct owl_gpio_port *
owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
{
unsigned int start = 0, i;
for (i = 0; i < pctrl->soc->nports; i++) {
const struct owl_gpio_port *port = &pctrl->soc->ports[i];
if (*pin >= start && *pin < start + port->pins) {
*pin -= start;
return port;
}
start += port->pins;
}
return NULL;
}
static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
{
u32 val;
val = readl_relaxed(base);
if (flag)
val |= BIT(pin);
else
val &= ~BIT(pin);
writel_relaxed(val, base);
}
static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
/*
* GPIOs have higher priority over other modules, so either setting
* them as OUT or IN is sufficient
*/
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->outen, offset, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* disable gpio output */
owl_gpio_update_reg(gpio_base + port->outen, offset, false);
/* disable gpio input */
owl_gpio_update_reg(gpio_base + port->inen, offset, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
u32 val;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
val = readl_relaxed(gpio_base + port->dat);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return !!(val & BIT(offset));
}
static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->outen, offset, false);
owl_gpio_update_reg(gpio_base + port->inen, offset, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int owl_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->inen, offset, false);
owl_gpio_update_reg(gpio_base + port->outen, offset, true);
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
{
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int offset, value, irq_type = 0;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
/*
* Since the hardware doesn't support interrupts on both edges,
* emulate it in the software by setting the single edge
* interrupt and switching to the opposite edge while ACKing
* the interrupt
*/
if (owl_gpio_get(&pctrl->chip, gpio))
irq_type = OWL_GPIO_INT_EDGE_FALLING;
else
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_RISING:
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
irq_type = OWL_GPIO_INT_EDGE_FALLING;
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_type = OWL_GPIO_INT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
irq_type = OWL_GPIO_INT_LEVEL_LOW;
break;
default:
break;
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
offset = (gpio < 16) ? 4 : 0;
value = readl_relaxed(gpio_base + port->intc_type + offset);
value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
value |= irq_type << ((gpio % 16) * 2);
writel_relaxed(value, gpio_base + port->intc_type + offset);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
u32 val;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
/* disable port interrupt if no interrupt pending bit is active */
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
gpiochip_disable_irq(gc, hwirq);
}
static void owl_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
u32 value;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpiochip_enable_irq(gc, hwirq);
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
<< port->shared_ctl_offset * 5);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(data);
const struct owl_gpio_port *port;
unsigned int gpio = hwirq;
void __iomem *gpio_base;
unsigned long flags;
/*
* Switch the interrupt edge to the opposite edge of the interrupt
* which got triggered for the case of emulating both edges
*/
if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
if (owl_gpio_get(gc, hwirq))
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING);
else
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING);
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);
irq_set_type(pctrl, data->hwirq, type);
return 0;
}
static const struct irq_chip owl_gpio_irqchip = {
.name = "owl-irq",
.irq_ack = owl_gpio_irq_ack,
.irq_mask = owl_gpio_irq_mask,
.irq_unmask = owl_gpio_irq_unmask,
.irq_set_type = owl_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void owl_gpio_irq_handler(struct irq_desc *desc)
{
struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *domain = pctrl->chip.irq.domain;
unsigned int parent = irq_desc_get_irq(desc);
const struct owl_gpio_port *port;
void __iomem *base;
unsigned int pin, offset = 0, i;
unsigned long pending_irq;
chained_irq_enter(chip, desc);
for (i = 0; i < pctrl->soc->nports; i++) {
port = &pctrl->soc->ports[i];
base = pctrl->base + port->offset;
/* skip ports that are not associated with this irq */
if (parent != pctrl->irq[i])
goto skip;
pending_irq = readl_relaxed(base + port->intc_pd);
for_each_set_bit(pin, &pending_irq, port->pins) {
generic_handle_domain_irq(domain, offset + pin);
/* clear pending interrupt */
owl_gpio_update_reg(base + port->intc_pd, pin, true);
}
skip:
offset += port->pins;
}
chained_irq_exit(chip, desc);
}
static int owl_gpio_init(struct owl_pinctrl *pctrl)
{
struct gpio_chip *chip;
struct gpio_irq_chip *gpio_irq;
int ret, i, j, offset;
chip = &pctrl->chip;
chip->base = -1;
chip->ngpio = pctrl->soc->ngpios;
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
gpio_irq = &chip->irq;
gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip);
gpio_irq->handler = handle_simple_irq;
gpio_irq->default_type = IRQ_TYPE_NONE;
gpio_irq->parent_handler = owl_gpio_irq_handler;
gpio_irq->parent_handler_data = pctrl;
gpio_irq->num_parents = pctrl->num_irq;
gpio_irq->parents = pctrl->irq;
gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
sizeof(*gpio_irq->map), GFP_KERNEL);
if (!gpio_irq->map)
return -ENOMEM;
for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
const struct owl_gpio_port *port = &pctrl->soc->ports[i];
for (j = 0; j < port->pins; j++)
gpio_irq->map[offset + j] = gpio_irq->parents[i];
offset += port->pins;
}
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to register gpiochip\n");
return ret;
}
return 0;
}
int owl_pinctrl_probe(struct platform_device *pdev,
struct owl_pinctrl_soc_data *soc_data)
{
struct owl_pinctrl *pctrl;
int ret, i;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);
/* enable GPIO/MFP clock */
pctrl->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pctrl->clk)) {
dev_err(&pdev->dev, "no clock defined\n");
return PTR_ERR(pctrl->clk);
}
ret = clk_prepare_enable(pctrl->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
return ret;
}
raw_spin_lock_init(&pctrl->lock);
owl_pinctrl_desc.name = dev_name(&pdev->dev);
owl_pinctrl_desc.pins = soc_data->pins;
owl_pinctrl_desc.npins = soc_data->npins;
pctrl->chip.direction_input = owl_gpio_direction_input;
pctrl->chip.direction_output = owl_gpio_direction_output;
pctrl->chip.get = owl_gpio_get;
pctrl->chip.set = owl_gpio_set;
pctrl->chip.request = owl_gpio_request;
pctrl->chip.free = owl_gpio_free;
pctrl->soc = soc_data;
pctrl->dev = &pdev->dev;
pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
&owl_pinctrl_desc, pctrl);
if (IS_ERR(pctrl->pctrldev)) {
dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
ret = PTR_ERR(pctrl->pctrldev);
goto err_exit;
}
ret = platform_irq_count(pdev);
if (ret < 0)
goto err_exit;
pctrl->num_irq = ret;
pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
sizeof(*pctrl->irq), GFP_KERNEL);
if (!pctrl->irq) {
ret = -ENOMEM;
goto err_exit;
}
for (i = 0; i < pctrl->num_irq ; i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0)
goto err_exit;
pctrl->irq[i] = ret;
}
ret = owl_gpio_init(pctrl);
if (ret)
goto err_exit;
platform_set_drvdata(pdev, pctrl);
return 0;
err_exit:
clk_disable_unprepare(pctrl->clk);
return ret;
}
|
linux-master
|
drivers/pinctrl/actions/pinctrl-owl.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Actions Semi S500 SoC Pinctrl driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Copyright (c) 2020 Cristian Ciocaltea <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
#define MFCTL0 (0x0040)
#define MFCTL1 (0x0044)
#define MFCTL2 (0x0048)
#define MFCTL3 (0x004C)
#define PAD_PULLCTL0 (0x0060)
#define PAD_PULLCTL1 (0x0064)
#define PAD_PULLCTL2 (0x0068)
#define PAD_ST0 (0x006C)
#define PAD_ST1 (0x0070)
#define PAD_CTL (0x0074)
#define PAD_DRV0 (0x0080)
#define PAD_DRV1 (0x0084)
#define PAD_DRV2 (0x0088)
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
#define _GPIOD(offset) (96 + (offset))
#define _GPIOE(offset) (128 + (offset))
#define NUM_GPIOS (_GPIOE(3) + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
#define DNAND_DQS _GPIOA(12)
#define DNAND_DQSN _GPIOA(13)
#define ETH_TXD0 _GPIOA(14)
#define ETH_TXD1 _GPIOA(15)
#define ETH_TXEN _GPIOA(16)
#define ETH_RXER _GPIOA(17)
#define ETH_CRS_DV _GPIOA(18)
#define ETH_RXD1 _GPIOA(19)
#define ETH_RXD0 _GPIOA(20)
#define ETH_REF_CLK _GPIOA(21)
#define ETH_MDC _GPIOA(22)
#define ETH_MDIO _GPIOA(23)
#define SIRQ0 _GPIOA(24)
#define SIRQ1 _GPIOA(25)
#define SIRQ2 _GPIOA(26)
#define I2S_D0 _GPIOA(27)
#define I2S_BCLK0 _GPIOA(28)
#define I2S_LRCLK0 _GPIOA(29)
#define I2S_MCLK0 _GPIOA(30)
#define I2S_D1 _GPIOA(31)
#define I2S_BCLK1 _GPIOB(0)
#define I2S_LRCLK1 _GPIOB(1)
#define I2S_MCLK1 _GPIOB(2)
#define KS_IN0 _GPIOB(3)
#define KS_IN1 _GPIOB(4)
#define KS_IN2 _GPIOB(5)
#define KS_IN3 _GPIOB(6)
#define KS_OUT0 _GPIOB(7)
#define KS_OUT1 _GPIOB(8)
#define KS_OUT2 _GPIOB(9)
#define LVDS_OEP _GPIOB(10)
#define LVDS_OEN _GPIOB(11)
#define LVDS_ODP _GPIOB(12)
#define LVDS_ODN _GPIOB(13)
#define LVDS_OCP _GPIOB(14)
#define LVDS_OCN _GPIOB(15)
#define LVDS_OBP _GPIOB(16)
#define LVDS_OBN _GPIOB(17)
#define LVDS_OAP _GPIOB(18)
#define LVDS_OAN _GPIOB(19)
#define LVDS_EEP _GPIOB(20)
#define LVDS_EEN _GPIOB(21)
#define LVDS_EDP _GPIOB(22)
#define LVDS_EDN _GPIOB(23)
#define LVDS_ECP _GPIOB(24)
#define LVDS_ECN _GPIOB(25)
#define LVDS_EBP _GPIOB(26)
#define LVDS_EBN _GPIOB(27)
#define LVDS_EAP _GPIOB(28)
#define LVDS_EAN _GPIOB(29)
#define LCD0_D18 _GPIOB(30)
#define LCD0_D17 _GPIOB(31)
#define DSI_DP3 _GPIOC(0)
#define DSI_DN3 _GPIOC(1)
#define DSI_DP1 _GPIOC(2)
#define DSI_DN1 _GPIOC(3)
#define DSI_CP _GPIOC(4)
#define DSI_CN _GPIOC(5)
#define DSI_DP0 _GPIOC(6)
#define DSI_DN0 _GPIOC(7)
#define DSI_DP2 _GPIOC(8)
#define DSI_DN2 _GPIOC(9)
#define SD0_D0 _GPIOC(10)
#define SD0_D1 _GPIOC(11)
#define SD0_D2 _GPIOC(12)
#define SD0_D3 _GPIOC(13)
#define SD1_D0 _GPIOC(14) /* SD0_D4 */
#define SD1_D1 _GPIOC(15) /* SD0_D5 */
#define SD1_D2 _GPIOC(16) /* SD0_D6 */
#define SD1_D3 _GPIOC(17) /* SD0_D7 */
#define SD0_CMD _GPIOC(18)
#define SD0_CLK _GPIOC(19)
#define SD1_CMD _GPIOC(20)
#define SD1_CLK _GPIOC(21)
#define SPI0_SCLK _GPIOC(22)
#define SPI0_SS _GPIOC(23)
#define SPI0_MISO _GPIOC(24)
#define SPI0_MOSI _GPIOC(25)
#define UART0_RX _GPIOC(26)
#define UART0_TX _GPIOC(27)
#define I2C0_SCLK _GPIOC(28)
#define I2C0_SDATA _GPIOC(29)
#define SENSOR0_PCLK _GPIOC(31)
#define SENSOR0_CKOUT _GPIOD(10)
#define DNAND_ALE _GPIOD(12)
#define DNAND_CLE _GPIOD(13)
#define DNAND_CEB0 _GPIOD(14)
#define DNAND_CEB1 _GPIOD(15)
#define DNAND_CEB2 _GPIOD(16)
#define DNAND_CEB3 _GPIOD(17)
#define UART2_RX _GPIOD(18)
#define UART2_TX _GPIOD(19)
#define UART2_RTSB _GPIOD(20)
#define UART2_CTSB _GPIOD(21)
#define UART3_RX _GPIOD(22)
#define UART3_TX _GPIOD(23)
#define UART3_RTSB _GPIOD(24)
#define UART3_CTSB _GPIOD(25)
#define PCM1_IN _GPIOD(28)
#define PCM1_CLK _GPIOD(29)
#define PCM1_SYNC _GPIOD(30)
#define PCM1_OUT _GPIOD(31)
#define I2C1_SCLK _GPIOE(0)
#define I2C1_SDATA _GPIOE(1)
#define I2C2_SCLK _GPIOE(2)
#define I2C2_SDATA _GPIOE(3)
#define CSI_DN0 _PIN(0)
#define CSI_DP0 _PIN(1)
#define CSI_DN1 _PIN(2)
#define CSI_DP1 _PIN(3)
#define CSI_CN _PIN(4)
#define CSI_CP _PIN(5)
#define CSI_DN2 _PIN(6)
#define CSI_DP2 _PIN(7)
#define CSI_DN3 _PIN(8)
#define CSI_DP3 _PIN(9)
#define DNAND_D0 _PIN(10)
#define DNAND_D1 _PIN(11)
#define DNAND_D2 _PIN(12)
#define DNAND_D3 _PIN(13)
#define DNAND_D4 _PIN(14)
#define DNAND_D5 _PIN(15)
#define DNAND_D6 _PIN(16)
#define DNAND_D7 _PIN(17)
#define DNAND_WRB _PIN(18)
#define DNAND_RDB _PIN(19)
#define DNAND_RDBN _PIN(20)
#define DNAND_RB _PIN(21)
#define PORB _PIN(22)
#define CLKO_25M _PIN(23)
#define BSEL _PIN(24)
#define PKG0 _PIN(25)
#define PKG1 _PIN(26)
#define PKG2 _PIN(27)
#define PKG3 _PIN(28)
#define _FIRSTPAD _GPIOA(0)
#define _LASTPAD PKG3
#define NUM_PADS (_PIN(28) + 1)
static const struct pinctrl_pin_desc s500_pads[] = {
PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
PINCTRL_PIN(ETH_TXEN, "eth_txen"),
PINCTRL_PIN(ETH_RXER, "eth_rxer"),
PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
PINCTRL_PIN(ETH_MDC, "eth_mdc"),
PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
PINCTRL_PIN(SIRQ0, "sirq0"),
PINCTRL_PIN(SIRQ1, "sirq1"),
PINCTRL_PIN(SIRQ2, "sirq2"),
PINCTRL_PIN(I2S_D0, "i2s_d0"),
PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
PINCTRL_PIN(I2S_D1, "i2s_d1"),
PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
PINCTRL_PIN(KS_IN0, "ks_in0"),
PINCTRL_PIN(KS_IN1, "ks_in1"),
PINCTRL_PIN(KS_IN2, "ks_in2"),
PINCTRL_PIN(KS_IN3, "ks_in3"),
PINCTRL_PIN(KS_OUT0, "ks_out0"),
PINCTRL_PIN(KS_OUT1, "ks_out1"),
PINCTRL_PIN(KS_OUT2, "ks_out2"),
PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
PINCTRL_PIN(LVDS_EEN, "lvds_een"),
PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
PINCTRL_PIN(LCD0_D17, "lcd0_d17"),
PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
PINCTRL_PIN(DSI_CP, "dsi_cp"),
PINCTRL_PIN(DSI_CN, "dsi_cn"),
PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
PINCTRL_PIN(SD0_D0, "sd0_d0"),
PINCTRL_PIN(SD0_D1, "sd0_d1"),
PINCTRL_PIN(SD0_D2, "sd0_d2"),
PINCTRL_PIN(SD0_D3, "sd0_d3"),
PINCTRL_PIN(SD1_D0, "sd1_d0"),
PINCTRL_PIN(SD1_D1, "sd1_d1"),
PINCTRL_PIN(SD1_D2, "sd1_d2"),
PINCTRL_PIN(SD1_D3, "sd1_d3"),
PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
PINCTRL_PIN(SD0_CLK, "sd0_clk"),
PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
PINCTRL_PIN(SD1_CLK, "sd1_clk"),
PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
PINCTRL_PIN(SPI0_SS, "spi0_ss"),
PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
PINCTRL_PIN(UART0_RX, "uart0_rx"),
PINCTRL_PIN(UART0_TX, "uart0_tx"),
PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
PINCTRL_PIN(UART2_RX, "uart2_rx"),
PINCTRL_PIN(UART2_TX, "uart2_tx"),
PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
PINCTRL_PIN(UART3_RX, "uart3_rx"),
PINCTRL_PIN(UART3_TX, "uart3_tx"),
PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
PINCTRL_PIN(PCM1_IN, "pcm1_in"),
PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
PINCTRL_PIN(CSI_DN0, "csi_dn0"),
PINCTRL_PIN(CSI_DP0, "csi_dp0"),
PINCTRL_PIN(CSI_DN1, "csi_dn1"),
PINCTRL_PIN(CSI_DP1, "csi_dp1"),
PINCTRL_PIN(CSI_DN2, "csi_dn2"),
PINCTRL_PIN(CSI_DP2, "csi_dp2"),
PINCTRL_PIN(CSI_DN3, "csi_dn3"),
PINCTRL_PIN(CSI_DP3, "csi_dp3"),
PINCTRL_PIN(CSI_CN, "csi_cn"),
PINCTRL_PIN(CSI_CP, "csi_cp"),
PINCTRL_PIN(DNAND_D0, "dnand_d0"),
PINCTRL_PIN(DNAND_D1, "dnand_d1"),
PINCTRL_PIN(DNAND_D2, "dnand_d2"),
PINCTRL_PIN(DNAND_D3, "dnand_d3"),
PINCTRL_PIN(DNAND_D4, "dnand_d4"),
PINCTRL_PIN(DNAND_D5, "dnand_d5"),
PINCTRL_PIN(DNAND_D6, "dnand_d6"),
PINCTRL_PIN(DNAND_D7, "dnand_d7"),
PINCTRL_PIN(DNAND_RB, "dnand_rb"),
PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
PINCTRL_PIN(PORB, "porb"),
PINCTRL_PIN(CLKO_25M, "clko_25m"),
PINCTRL_PIN(BSEL, "bsel"),
PINCTRL_PIN(PKG0, "pkg0"),
PINCTRL_PIN(PKG1, "pkg1"),
PINCTRL_PIN(PKG2, "pkg2"),
PINCTRL_PIN(PKG3, "pkg3"),
};
enum s500_pinmux_functions {
S500_MUX_NOR,
S500_MUX_ETH_RMII,
S500_MUX_ETH_SMII,
S500_MUX_SPI0,
S500_MUX_SPI1,
S500_MUX_SPI2,
S500_MUX_SPI3,
S500_MUX_SENS0,
S500_MUX_SENS1,
S500_MUX_UART0,
S500_MUX_UART1,
S500_MUX_UART2,
S500_MUX_UART3,
S500_MUX_UART4,
S500_MUX_UART5,
S500_MUX_UART6,
S500_MUX_I2S0,
S500_MUX_I2S1,
S500_MUX_PCM1,
S500_MUX_PCM0,
S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_PWM0,
S500_MUX_PWM1,
S500_MUX_PWM2,
S500_MUX_PWM3,
S500_MUX_PWM4,
S500_MUX_PWM5,
S500_MUX_P0,
S500_MUX_SD0,
S500_MUX_SD1,
S500_MUX_SD2,
S500_MUX_I2C0,
S500_MUX_I2C1,
/*S500_MUX_I2C2,*/
S500_MUX_I2C3,
S500_MUX_DSI,
S500_MUX_LVDS,
S500_MUX_USB30,
S500_MUX_CLKO_25M,
S500_MUX_MIPI_CSI,
S500_MUX_NAND,
S500_MUX_SPDIF,
/*S500_MUX_SIRQ0,*/
/*S500_MUX_SIRQ1,*/
/*S500_MUX_SIRQ2,*/
S500_MUX_TS,
S500_MUX_LCD0,
S500_MUX_RESERVED,
};
/* MFPCTL group data */
/* mfp0_31_26 reserved */
/* mfp0_25_23 */
static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };
static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR,
S500_MUX_SENS1,
S500_MUX_PWM2,
S500_MUX_PWM4,
S500_MUX_LCD0 };
/* mfp0_22_20 */
static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };
static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_ETH_SMII,
S500_MUX_SPI2,
S500_MUX_UART4,
S500_MUX_PWM4 };
/* mfp0_18_16_eth_txd0 */
static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };
static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_ETH_SMII,
S500_MUX_SPI2,
S500_MUX_UART6,
S500_MUX_PWM4 };
/* mfp0_18_16_eth_txd1 */
static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };
static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_ETH_SMII,
S500_MUX_SPI2,
S500_MUX_UART6,
S500_MUX_PWM5 };
/* mfp0_15_13_rmii_txen */
static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };
static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_UART2,
S500_MUX_SPI3,
S500_MUX_PWM0 };
/* mfp0_15_13_rmii_rxen */
static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER };
static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_UART2,
S500_MUX_SPI3,
S500_MUX_PWM1 };
/* mfp0_12_11 reserved */
/* mfp0_10_8_rmii_rxd1 */
static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };
static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_UART2,
S500_MUX_SPI3,
S500_MUX_PWM2,
S500_MUX_UART5 };
/* mfp0_10_8_rmii_rxd0 */
static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };
static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_UART2,
S500_MUX_SPI3,
S500_MUX_PWM3,
S500_MUX_UART5 };
/* mfp0_7_6 */
static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII,
S500_MUX_UART4,
S500_MUX_SPI2,
S500_MUX_RESERVED,
S500_MUX_ETH_SMII };
/* mfp0_5 */
static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0,
S500_MUX_NOR };
/* mfp0_4_3 */
static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0,
S500_MUX_NOR,
S500_MUX_PCM1 };
/* mfp0_2_1_i2s0 */
static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };
static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0,
S500_MUX_NOR,
S500_MUX_PCM0 };
/* mfp0_2_1_i2s1 */
static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1,
I2S_MCLK1 };
static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1,
S500_MUX_NOR,
S500_MUX_PCM0 };
/* mfp0_0 */
static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1,
S500_MUX_NOR };
/* mfp1_31_29_ks_in0 */
static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };
static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_NOR,
S500_MUX_PWM0,
S500_MUX_PWM4,
S500_MUX_SENS1,
S500_MUX_PWM4,
S500_MUX_P0 };
/* mfp1_31_29_ks_in1 */
static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };
static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_NOR,
S500_MUX_PWM1,
S500_MUX_PWM5,
S500_MUX_SENS1,
S500_MUX_PWM1,
S500_MUX_USB30 };
/* mfp1_31_29_ks_in2 */
static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };
static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_NOR,
S500_MUX_PWM0,
S500_MUX_PWM0,
S500_MUX_SENS1,
S500_MUX_PWM0,
S500_MUX_P0 };
/* mfp1_28_26_ks_in3 */
static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };
static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_NOR,
S500_MUX_PWM1,
S500_MUX_RESERVED,
S500_MUX_SENS1 };
/* mfp1_28_26_ks_out0 */
static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };
static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_UART5,
S500_MUX_NOR,
S500_MUX_PWM2,
S500_MUX_RESERVED,
S500_MUX_SENS1,
S500_MUX_SD0 };
/* mfp1_28_26_ks_out1 */
static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };
static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS,
S500_MUX_JTAG,
S500_MUX_NOR,
S500_MUX_PWM3,
S500_MUX_RESERVED,
S500_MUX_SENS1,
S500_MUX_SD0 };
/* mfp1_25_23 */
static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };
static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_KS,
S500_MUX_NOR,
S500_MUX_PWM2,
S500_MUX_UART5,
S500_MUX_SENS1 };
/* mfp1_22_21 */
static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN,
LVDS_ODP, LVDS_ODN,
LVDS_OCP, LVDS_OCN,
LVDS_OBP, LVDS_OBN,
LVDS_OAP, LVDS_OAN };
static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS,
S500_MUX_TS,
S500_MUX_LCD0 };
/* mfp1_20_19 */
static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };
static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_UART2,
S500_MUX_SPI0 };
/* mfp1_18_17 */
static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };
static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_UART2,
S500_MUX_SPI0,
S500_MUX_SD1 };
/* mfp1_16_14 */
static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 };
static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR,
S500_MUX_SD0,
S500_MUX_SD1,
S500_MUX_PWM3,
S500_MUX_LCD0 };
/* mfp1_13_12 */
static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };
static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_SD0,
S500_MUX_SD1,
S500_MUX_LCD0 };
/* mfp1_11_10 */
static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };
static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_RESERVED,
S500_MUX_SD1,
S500_MUX_LCD0 };
/* mfp1_9_7 */
static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };
static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_RESERVED,
S500_MUX_SD0,
S500_MUX_UART2,
S500_MUX_SPI0 };
/* mfp1_6_5 */
static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN };
static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS,
S500_MUX_NOR,
S500_MUX_TS,
S500_MUX_LCD0 };
/* mfp1_4_3 */
static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI };
static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0,
S500_MUX_NOR,
S500_MUX_I2C3,
S500_MUX_PCM0 };
/* mfp1_2_0 */
static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO };
static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0,
S500_MUX_NOR,
S500_MUX_I2S1,
S500_MUX_PCM1,
S500_MUX_PCM0 };
/* mfp2_31 reserved */
/* mfp2_30_29 */
static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN };
static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_SD1,
S500_MUX_LCD0 };
/* mfp2_28_27 */
static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN,
LVDS_ECP, LVDS_ECN,
LVDS_EBP, LVDS_EBN,
LVDS_EAP, LVDS_EAN };
static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS,
S500_MUX_NOR,
S500_MUX_LCD0 };
/* mfp2_26_24 */
static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };
static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI,
S500_MUX_RESERVED,
S500_MUX_SD1,
S500_MUX_UART2,
S500_MUX_SPI0 };
/* mfp2_23 */
static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2,
S500_MUX_UART0 };
/* mfp2_22 */
static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2,
S500_MUX_UART0 };
/* mfp2_21 */
static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3,
S500_MUX_UART5 };
/* mfp2_20 */
static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3,
S500_MUX_UART5 };
/* mfp2_19_17 */
static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_NOR,
S500_MUX_RESERVED,
S500_MUX_JTAG,
S500_MUX_UART2,
S500_MUX_UART5 };
/* mfp2_16_14 */
static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_NOR,
S500_MUX_RESERVED,
S500_MUX_RESERVED,
S500_MUX_UART2,
S500_MUX_UART5 };
/* mfp2_13_11 */
static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 };
static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_NOR,
S500_MUX_RESERVED,
S500_MUX_JTAG,
S500_MUX_UART2,
S500_MUX_UART1 };
/* mfp2_10_9 */
static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,
SD1_D2, SD1_D3 };
static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_NOR,
S500_MUX_RESERVED,
S500_MUX_SD1 };
/* mfp2_8_7 */
static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_NOR,
S500_MUX_RESERVED,
S500_MUX_JTAG };
/* mfp2_6_5 */
static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0,
S500_MUX_RESERVED,
S500_MUX_JTAG };
/* mfp2_4_3 */
static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };
static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1,
S500_MUX_NOR };
/* mfp2_2_0 */
static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0,
S500_MUX_UART2,
S500_MUX_SPI1,
S500_MUX_I2C0,
S500_MUX_PCM1,
S500_MUX_I2S1 };
/* mfp3_31 reserved */
/* mfp3_30 */
static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };
static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED,
S500_MUX_CLKO_25M };
/* mfp3_29_28 */
static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP };
static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI,
S500_MUX_SENS0 };
/* mfp3_27_24 reserved */
/* mfp3_23_22 */
static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };
static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0,
S500_MUX_NOR,
S500_MUX_SENS1,
S500_MUX_PWM1 };
/* mfp3_21_19 */
static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0,
S500_MUX_UART2,
S500_MUX_SPI1,
S500_MUX_I2C0,
S500_MUX_SPDIF,
S500_MUX_PCM1,
S500_MUX_I2S1 };
/* mfp3_18_16 */
static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,
I2C0_SDATA };
static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0,
S500_MUX_UART2,
S500_MUX_I2C1,
S500_MUX_UART1,
S500_MUX_SPI1 };
/* mfp3_15_14 */
static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1,
CSI_DN2, CSI_DN3,
CSI_DP0, CSI_DP1,
CSI_DP2, CSI_DP3 };
static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI,
S500_MUX_SENS0 };
/* mfp3_13_12 */
static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };
static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0,
S500_MUX_NOR,
S500_MUX_PWM0 };
/* mfp3_11_10 */
static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };
static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1,
S500_MUX_SENS1,
S500_MUX_UART4,
S500_MUX_PWM4 };
/* mfp3_9_8 */
static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1,
S500_MUX_SENS1,
S500_MUX_UART4,
S500_MUX_PWM5 };
/* mfp3_7_6 */
static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1,
S500_MUX_SENS1,
S500_MUX_UART6,
S500_MUX_I2C3 };
/* mfp3_5_4 */
static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };
static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1,
S500_MUX_SENS1,
S500_MUX_UART6,
S500_MUX_I2C3 };
/* mfp3_3 */
static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1,
DNAND_D2, DNAND_D3,
DNAND_D4, DNAND_D5,
DNAND_D6, DNAND_D7,
DNAND_RDB, DNAND_RDBN };
static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND,
S500_MUX_SD2 };
/* mfp3_2 */
static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,
DNAND_CLE,
DNAND_CEB0,
DNAND_CEB1 };
static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND,
S500_MUX_SPI2 };
/* mfp3_1_0_nand_ceb2 */
static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };
static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND,
S500_MUX_PWM5 };
/* mfp3_1_0_nand_ceb3 */
static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };
static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND,
S500_MUX_PWM4 };
/* PADDRV group data */
/* paddrv0_29_28 */
static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 };
/* paddrv0_23_22 */
static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1,
ETH_TXEN };
/* paddrv0_21_20 */
static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER };
/* paddrv0_19_18 */
static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV };
/* paddrv0_17_16 */
static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 };
/* paddrv0_15_14 */
static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
/* paddrv0_13_12 */
static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
/* paddrv0_11_10 */
static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };
/* paddrv0_9_8 */
static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };
/* paddrv0_7_6 */
static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0,
I2S_D1 };
/* paddrv0_5_4 */
static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1,
I2S_MCLK1 };
/* paddrv0_3_2 */
static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK,
PCM1_SYNC, PCM1_OUT };
/* paddrv0_1_0 */
static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1,
KS_IN2, KS_IN3 };
/* paddrv1_31_30 */
static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 };
/* paddrv1_29_28 */
static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN,
LVDS_ODP, LVDS_ODN,
LVDS_OCP, LVDS_OCN,
LVDS_OBP, LVDS_OBN,
LVDS_OAP, LVDS_OAN,
LVDS_EEP, LVDS_EEN,
LVDS_EDP, LVDS_EDN,
LVDS_ECP, LVDS_ECN,
LVDS_EBP, LVDS_EBN,
LVDS_EAP, LVDS_EAN };
/* paddrv1_27_26 */
static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1,
DSI_DN1, DSI_CP, DSI_CN };
/* paddrv1_25_24 */
static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0,
DSI_DP2, DSI_DN2 };
/* paddrv1_23_22 */
static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1,
SD0_D2, SD0_D3 };
/* paddrv1_21_20 */
static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1,
SD1_D2, SD1_D3 };
/* paddrv1_19_18 */
static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };
/* paddrv1_17_16 */
static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };
/* paddrv1_15_14 */
static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD };
/* paddrv1_13_12 */
static unsigned int sd1_clk_drv_pads[] = { SD1_CLK };
/* paddrv1_11_10 */
static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS,
SPI0_MISO, SPI0_MOSI };
/* paddrv2_31_30 */
static unsigned int uart0_rx_drv_pads[] = { UART0_RX };
/* paddrv2_29_28 */
static unsigned int uart0_tx_drv_pads[] = { UART0_TX };
/* paddrv2_27_26 */
static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX,
UART2_RTSB, UART2_CTSB };
/* paddrv2_24_23 */
static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };
/* paddrv2_22_21 */
static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA,
I2C2_SCLK, I2C2_SDATA };
/* paddrv2_19_18 */
static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };
/* paddrv2_13_12 */
static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };
/* paddrv2_3_2 */
static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX,
UART3_RTSB, UART3_CTSB };
/* Pinctrl groups */
static const struct owl_pingroup s500_groups[] = {
MUX_PG(lcd0_d18_mfp, 0, 23, 3),
MUX_PG(rmii_crs_dv_mfp, 0, 20, 3),
MUX_PG(rmii_txd0_mfp, 0, 16, 3),
MUX_PG(rmii_txd1_mfp, 0, 16, 3),
MUX_PG(rmii_txen_mfp, 0, 13, 3),
MUX_PG(rmii_rxen_mfp, 0, 13, 3),
MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
MUX_PG(i2s_d0_mfp, 0, 5, 1),
MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
MUX_PG(i2s_d1_mfp, 0, 0, 1),
MUX_PG(ks_in2_mfp, 1, 29, 3),
MUX_PG(ks_in1_mfp, 1, 29, 3),
MUX_PG(ks_in0_mfp, 1, 29, 3),
MUX_PG(ks_in3_mfp, 1, 26, 3),
MUX_PG(ks_out0_mfp, 1, 26, 3),
MUX_PG(ks_out1_mfp, 1, 26, 3),
MUX_PG(ks_out2_mfp, 1, 23, 3),
MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
MUX_PG(dsi_dn0_mfp, 1, 19, 2),
MUX_PG(dsi_dp2_mfp, 1, 17, 2),
MUX_PG(lcd0_d17_mfp, 1, 14, 3),
MUX_PG(dsi_dp3_mfp, 1, 12, 2),
MUX_PG(dsi_dn3_mfp, 1, 10, 2),
MUX_PG(dsi_dp0_mfp, 1, 7, 3),
MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2),
MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3),
MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2),
MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
MUX_PG(dsi_dn2_mfp, 2, 24, 3),
MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
MUX_PG(sd0_d0_mfp, 2, 17, 3),
MUX_PG(sd0_d1_mfp, 2, 14, 3),
MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
MUX_PG(sd0_cmd_mfp, 2, 7, 2),
MUX_PG(sd0_clk_mfp, 2, 5, 2),
MUX_PG(sd1_cmd_mfp, 2, 3, 2),
MUX_PG(uart0_rx_mfp, 2, 0, 3),
MUX_PG(clko_25m_mfp, 3, 30, 1),
MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
MUX_PG(sens0_ckout_mfp, 3, 22, 2),
MUX_PG(uart0_tx_mfp, 3, 19, 3),
MUX_PG(i2c0_mfp, 3, 16, 3),
MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
MUX_PG(sen0_pclk_mfp, 3, 12, 2),
MUX_PG(pcm1_in_mfp, 3, 10, 2),
MUX_PG(pcm1_clk_mfp, 3, 8, 2),
MUX_PG(pcm1_sync_mfp, 3, 6, 2),
MUX_PG(pcm1_out_mfp, 3, 4, 2),
MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
MUX_PG(nand_ceb2_mfp, 3, 0, 2),
MUX_PG(nand_ceb3_mfp, 3, 0, 2),
DRV_PG(sirq_drv, 0, 28, 2),
DRV_PG(rmii_txd01_txen_drv, 0, 22, 2),
DRV_PG(rmii_rxer_drv, 0, 20, 2),
DRV_PG(rmii_crs_drv, 0, 18, 2),
DRV_PG(rmii_rxd10_drv, 0, 16, 2),
DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
DRV_PG(i2s_d0_drv, 0, 10, 2),
DRV_PG(i2s_bclk0_drv, 0, 8, 2),
DRV_PG(i2s3_drv, 0, 6, 2),
DRV_PG(i2s13_drv, 0, 4, 2),
DRV_PG(pcm1_drv, 0, 2, 2),
DRV_PG(ks_in_drv, 0, 0, 2),
DRV_PG(ks_out_drv, 1, 30, 2),
DRV_PG(lvds_all_drv, 1, 28, 2),
DRV_PG(lcd_dsi_drv, 1, 26, 2),
DRV_PG(dsi_drv, 1, 24, 2),
DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
DRV_PG(sd1_d0_d3_drv, 1, 20, 2),
DRV_PG(sd0_cmd_drv, 1, 18, 2),
DRV_PG(sd0_clk_drv, 1, 16, 2),
DRV_PG(sd1_cmd_drv, 1, 14, 2),
DRV_PG(sd1_clk_drv, 1, 12, 2),
DRV_PG(spi0_all_drv, 1, 10, 2),
DRV_PG(uart0_rx_drv, 2, 30, 2),
DRV_PG(uart0_tx_drv, 2, 28, 2),
DRV_PG(uart2_all_drv, 2, 26, 2),
DRV_PG(i2c0_all_drv, 2, 23, 2),
DRV_PG(i2c12_all_drv, 2, 21, 2),
DRV_PG(sens0_pclk_drv, 2, 18, 2),
DRV_PG(sens0_ckout_drv, 2, 12, 2),
DRV_PG(uart3_all_drv, 2, 2, 2),
};
static const char * const nor_groups[] = {
"lcd0_d18_mfp",
"i2s_d0_mfp",
"i2s0_pcm0_mfp",
"i2s1_pcm0_mfp",
"i2s_d1_mfp",
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"lcd0_d17_mfp",
"lvds_ee_pn_mfp",
"spi0_i2c_pcm_mfp",
"spi0_i2s_pcm_mfp",
"lvds_e_pn_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd1_d0_d3_mfp",
"sd0_cmd_mfp",
"sd1_cmd_mfp",
"sens0_ckout_mfp",
"sen0_pclk_mfp",
};
static const char * const eth_rmii_groups[] = {
"rmii_crs_dv_mfp",
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_txen_mfp",
"rmii_rxen_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"rmii_ref_clk_mfp",
};
static const char * const eth_smii_groups[] = {
"rmii_crs_dv_mfp",
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_ref_clk_mfp",
};
static const char * const spi0_groups[] = {
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp0_mfp",
"spi0_i2c_pcm_mfp",
"spi0_i2s_pcm_mfp",
"dsi_dn2_mfp",
};
static const char * const spi1_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const spi2_groups[] = {
"rmii_crs_dv_mfp",
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"rmii_ref_clk_mfp",
"dnand_acle_ce0_mfp",
};
static const char * const spi3_groups[] = {
"rmii_txen_mfp",
"rmii_rxen_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
};
static const char * const sens0_groups[] = {
"csi_cn_cp_mfp",
"sens0_ckout_mfp",
"csi_dn_dp_mfp",
"sen0_pclk_mfp",
};
static const char * const sens1_groups[] = {
"lcd0_d18_mfp",
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"sens0_ckout_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const uart0_groups[] = {
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const uart1_groups[] = {
"sd0_d2_d3_mfp",
"i2c0_mfp",
};
static const char * const uart2_groups[] = {
"rmii_txen_mfp",
"rmii_rxen_mfp",
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp0_mfp",
"dsi_dn2_mfp",
"uart2_rtsb_mfp",
"uart2_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const uart3_groups[] = {
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
};
static const char * const uart4_groups[] = {
"rmii_crs_dv_mfp",
"rmii_ref_clk_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
};
static const char * const uart5_groups[] = {
"rmii_rxd1_mfp",
"rmii_rxd0_mfp",
"ks_out0_mfp",
"ks_out2_mfp",
"uart3_rtsb_mfp",
"uart3_ctsb_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
};
static const char * const uart6_groups[] = {
"rmii_txd0_mfp",
"rmii_txd1_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const i2s0_groups[] = {
"i2s_d0_mfp",
"i2s_pcm1_mfp",
"i2s0_pcm0_mfp",
};
static const char * const i2s1_groups[] = {
"i2s1_pcm0_mfp",
"i2s_d1_mfp",
"spi0_i2s_pcm_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
};
static const char * const pcm1_groups[] = {
"i2s_pcm1_mfp",
"spi0_i2s_pcm_mfp",
"uart0_rx_mfp",
"uart0_tx_mfp",
"pcm1_in_mfp",
"pcm1_clk_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const pcm0_groups[] = {
"i2s0_pcm0_mfp",
"i2s1_pcm0_mfp",
"spi0_i2c_pcm_mfp",
"spi0_i2s_pcm_mfp",
};
static const char * const ks_groups[] = {
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
};
static const char * const jtag_groups[] = {
"ks_in2_mfp",
"ks_in1_mfp",
"ks_in0_mfp",
"ks_in3_mfp",
"ks_out1_mfp",
"sd0_d0_mfp",
"sd0_d2_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const pwm0_groups[] = {
"ks_in2_mfp",
"ks_in0_mfp",
"rmii_txen_mfp",
"sen0_pclk_mfp",
};
static const char * const pwm1_groups[] = {
"rmii_rxen_mfp",
"ks_in1_mfp",
"ks_in3_mfp",
"sens0_ckout_mfp",
};
static const char * const pwm2_groups[] = {
"lcd0_d18_mfp",
"rmii_rxd1_mfp",
"ks_out0_mfp",
"ks_out2_mfp",
};
static const char * const pwm3_groups[] = {
"rmii_rxd0_mfp",
"ks_out1_mfp",
"lcd0_d17_mfp",
};
static const char * const pwm4_groups[] = {
"lcd0_d18_mfp",
"rmii_crs_dv_mfp",
"rmii_txd0_mfp",
"ks_in0_mfp",
"pcm1_in_mfp",
"nand_ceb3_mfp",
};
static const char * const pwm5_groups[] = {
"rmii_txd1_mfp",
"ks_in1_mfp",
"pcm1_clk_mfp",
"nand_ceb2_mfp",
};
static const char * const p0_groups[] = {
"ks_in2_mfp",
"ks_in0_mfp",
};
static const char * const sd0_groups[] = {
"ks_out0_mfp",
"ks_out1_mfp",
"ks_out2_mfp",
"lcd0_d17_mfp",
"dsi_dp3_mfp",
"dsi_dp0_mfp",
"sd0_d0_mfp",
"sd0_d1_mfp",
"sd0_d2_d3_mfp",
"sd1_d0_d3_mfp",
"sd0_cmd_mfp",
"sd0_clk_mfp",
};
static const char * const sd1_groups[] = {
"dsi_dp2_mfp",
"lcd0_d17_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"dsi_dnp1_cp_mfp",
"dsi_dn2_mfp",
"sd1_d0_d3_mfp",
"sd1_cmd_mfp",
};
static const char * const sd2_groups[] = {
"dnand_data_wr_mfp",
};
static const char * const i2c0_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp",
};
static const char * const i2c1_groups[] = {
"i2c0_mfp",
};
static const char * const i2c3_groups[] = {
"spi0_i2c_pcm_mfp",
"pcm1_sync_mfp",
"pcm1_out_mfp",
};
static const char * const lvds_groups[] = {
"lvds_o_pn_mfp",
"lvds_ee_pn_mfp",
"lvds_e_pn_mfp",
};
static const char * const ts_groups[] = {
"lvds_o_pn_mfp",
"lvds_ee_pn_mfp",
};
static const char * const lcd0_groups[] = {
"lcd0_d18_mfp",
"lcd0_d17_mfp",
"lvds_o_pn_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"lvds_ee_pn_mfp",
"dsi_dnp1_cp_mfp",
"lvds_e_pn_mfp",
};
static const char * const usb30_groups[] = {
"ks_in1_mfp",
};
static const char * const clko_25m_groups[] = {
"clko_25m_mfp",
};
static const char * const mipi_csi_groups[] = {
"csi_cn_cp_mfp",
"csi_dn_dp_mfp",
};
static const char * const dsi_groups[] = {
"dsi_dn0_mfp",
"dsi_dp2_mfp",
"dsi_dp3_mfp",
"dsi_dn3_mfp",
"dsi_dp0_mfp",
"dsi_dnp1_cp_mfp",
"dsi_dn2_mfp",
};
static const char * const nand_groups[] = {
"dnand_data_wr_mfp",
"dnand_acle_ce0_mfp",
"nand_ceb2_mfp",
"nand_ceb3_mfp",
};
static const char * const spdif_groups[] = {
"uart0_tx_mfp",
};
static const struct owl_pinmux_func s500_functions[] = {
[S500_MUX_NOR] = FUNCTION(nor),
[S500_MUX_ETH_RMII] = FUNCTION(eth_rmii),
[S500_MUX_ETH_SMII] = FUNCTION(eth_smii),
[S500_MUX_SPI0] = FUNCTION(spi0),
[S500_MUX_SPI1] = FUNCTION(spi1),
[S500_MUX_SPI2] = FUNCTION(spi2),
[S500_MUX_SPI3] = FUNCTION(spi3),
[S500_MUX_SENS0] = FUNCTION(sens0),
[S500_MUX_SENS1] = FUNCTION(sens1),
[S500_MUX_UART0] = FUNCTION(uart0),
[S500_MUX_UART1] = FUNCTION(uart1),
[S500_MUX_UART2] = FUNCTION(uart2),
[S500_MUX_UART3] = FUNCTION(uart3),
[S500_MUX_UART4] = FUNCTION(uart4),
[S500_MUX_UART5] = FUNCTION(uart5),
[S500_MUX_UART6] = FUNCTION(uart6),
[S500_MUX_I2S0] = FUNCTION(i2s0),
[S500_MUX_I2S1] = FUNCTION(i2s1),
[S500_MUX_PCM1] = FUNCTION(pcm1),
[S500_MUX_PCM0] = FUNCTION(pcm0),
[S500_MUX_KS] = FUNCTION(ks),
[S500_MUX_JTAG] = FUNCTION(jtag),
[S500_MUX_PWM0] = FUNCTION(pwm0),
[S500_MUX_PWM1] = FUNCTION(pwm1),
[S500_MUX_PWM2] = FUNCTION(pwm2),
[S500_MUX_PWM3] = FUNCTION(pwm3),
[S500_MUX_PWM4] = FUNCTION(pwm4),
[S500_MUX_PWM5] = FUNCTION(pwm5),
[S500_MUX_P0] = FUNCTION(p0),
[S500_MUX_SD0] = FUNCTION(sd0),
[S500_MUX_SD1] = FUNCTION(sd1),
[S500_MUX_SD2] = FUNCTION(sd2),
[S500_MUX_I2C0] = FUNCTION(i2c0),
[S500_MUX_I2C1] = FUNCTION(i2c1),
/*[S500_MUX_I2C2] = FUNCTION(i2c2),*/
[S500_MUX_I2C3] = FUNCTION(i2c3),
[S500_MUX_DSI] = FUNCTION(dsi),
[S500_MUX_LVDS] = FUNCTION(lvds),
[S500_MUX_USB30] = FUNCTION(usb30),
[S500_MUX_CLKO_25M] = FUNCTION(clko_25m),
[S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
[S500_MUX_NAND] = FUNCTION(nand),
[S500_MUX_SPDIF] = FUNCTION(spdif),
/*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/
/*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/
/*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/
[S500_MUX_TS] = FUNCTION(ts),
[S500_MUX_LCD0] = FUNCTION(lcd0),
};
/* PAD_ST0 */
static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
static PAD_ST_CONF(UART0_RX, 0, 29, 1);
static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
static PAD_ST_CONF(UART0_TX, 0, 14, 1);
static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
static PAD_ST_CONF(KS_IN0, 0, 11, 1);
static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
/* PAD_ST1 */
static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
static PAD_ST_CONF(UART3_RX, 1, 25, 1);
static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
static PAD_ST_CONF(UART2_RX, 1, 22, 1);
static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1);
static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
/* PAD_PULLCTL1 */
static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1);
static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1);
static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1);
static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1);
static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1);
static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1);
static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1);
static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1);
static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1);
static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
/* PAD_PULLCTL2 */
static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1);
static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1);
static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2);
static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2);
static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);
static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);
/* Pad info table */
static const struct owl_padinfo s500_padinfo[NUM_PADS] = {
[DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS),
[DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN),
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
[ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
[ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
[ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
[ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
[ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
[ETH_MDC] = PAD_INFO(ETH_MDC),
[ETH_MDIO] = PAD_INFO(ETH_MDIO),
[SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
[SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
[SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
[I2S_D0] = PAD_INFO(I2S_D0),
[I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
[I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
[I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
[I2S_D1] = PAD_INFO(I2S_D1),
[I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
[I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
[I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
[KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
[KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
[KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
[KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
[KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
[KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
[KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
[LVDS_OEP] = PAD_INFO(LVDS_OEP),
[LVDS_OEN] = PAD_INFO(LVDS_OEN),
[LVDS_ODP] = PAD_INFO(LVDS_ODP),
[LVDS_ODN] = PAD_INFO(LVDS_ODN),
[LVDS_OCP] = PAD_INFO(LVDS_OCP),
[LVDS_OCN] = PAD_INFO(LVDS_OCN),
[LVDS_OBP] = PAD_INFO(LVDS_OBP),
[LVDS_OBN] = PAD_INFO(LVDS_OBN),
[LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
[LVDS_OAN] = PAD_INFO(LVDS_OAN),
[LVDS_EEP] = PAD_INFO(LVDS_EEP),
[LVDS_EEN] = PAD_INFO(LVDS_EEN),
[LVDS_EDP] = PAD_INFO(LVDS_EDP),
[LVDS_EDN] = PAD_INFO(LVDS_EDN),
[LVDS_ECP] = PAD_INFO(LVDS_ECP),
[LVDS_ECN] = PAD_INFO(LVDS_ECN),
[LVDS_EBP] = PAD_INFO(LVDS_EBP),
[LVDS_EBN] = PAD_INFO(LVDS_EBN),
[LVDS_EAP] = PAD_INFO(LVDS_EAP),
[LVDS_EAN] = PAD_INFO(LVDS_EAN),
[LCD0_D18] = PAD_INFO(LCD0_D18),
[LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17),
[DSI_DP3] = PAD_INFO(DSI_DP3),
[DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
[DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
[DSI_DN1] = PAD_INFO(DSI_DN1),
[DSI_CP] = PAD_INFO_PULLCTL(DSI_CP),
[DSI_CN] = PAD_INFO_PULLCTL(DSI_CN),
[DSI_DP0] = PAD_INFO_ST(DSI_DP0),
[DSI_DN0] = PAD_INFO_ST(DSI_DN0),
[DSI_DP2] = PAD_INFO_ST(DSI_DP2),
[DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2),
[SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
[SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
[SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
[SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
[SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
[SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
[SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
[SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
[SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
[SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
[SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
[SD1_CLK] = PAD_INFO(SD1_CLK),
[SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
[SPI0_SS] = PAD_INFO_ST(SPI0_SS),
[SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
[SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
[UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
[UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
[I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
[I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
[SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
[SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
[DNAND_ALE] = PAD_INFO(DNAND_ALE),
[DNAND_CLE] = PAD_INFO(DNAND_CLE),
[DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
[DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
[DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
[DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
[UART2_RX] = PAD_INFO_ST(UART2_RX),
[UART2_TX] = PAD_INFO(UART2_TX),
[UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
[UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
[UART3_RX] = PAD_INFO_ST(UART3_RX),
[UART3_TX] = PAD_INFO(UART3_TX),
[UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
[UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
[PCM1_IN] = PAD_INFO_ST(PCM1_IN),
[PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
[PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
[PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
[I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
[I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
[I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
[I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
[CSI_DN0] = PAD_INFO(CSI_DN0),
[CSI_DP0] = PAD_INFO(CSI_DP0),
[CSI_DN1] = PAD_INFO(CSI_DN1),
[CSI_DP1] = PAD_INFO(CSI_DP1),
[CSI_CN] = PAD_INFO(CSI_CN),
[CSI_CP] = PAD_INFO(CSI_CP),
[CSI_DN2] = PAD_INFO(CSI_DN2),
[CSI_DP2] = PAD_INFO(CSI_DP2),
[CSI_DN3] = PAD_INFO(CSI_DN3),
[CSI_DP3] = PAD_INFO(CSI_DP3),
[DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0),
[DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1),
[DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2),
[DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3),
[DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4),
[DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5),
[DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6),
[DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7),
[DNAND_WRB] = PAD_INFO(DNAND_WRB),
[DNAND_RDB] = PAD_INFO(DNAND_RDB),
[DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN),
[DNAND_RB] = PAD_INFO(DNAND_RB),
[PORB] = PAD_INFO(PORB),
[CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
[BSEL] = PAD_INFO(BSEL),
[PKG0] = PAD_INFO(PKG0),
[PKG1] = PAD_INFO(PKG1),
[PKG2] = PAD_INFO(PKG2),
[PKG3] = PAD_INFO(PKG3),
};
static const struct owl_gpio_port s500_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1),
OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2),
OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3),
OWL_GPIO_PORT(E, 0x0030, 4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4),
};
enum s500_pinconf_pull {
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
};
static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param, u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param, u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static struct owl_pinctrl_soc_data s500_pinctrl_data = {
.padinfo = s500_padinfo,
.pins = (const struct pinctrl_pin_desc *)s500_pads,
.npins = ARRAY_SIZE(s500_pads),
.functions = s500_functions,
.nfunctions = ARRAY_SIZE(s500_functions),
.groups = s500_groups,
.ngroups = ARRAY_SIZE(s500_groups),
.ngpios = NUM_GPIOS,
.ports = s500_gpio_ports,
.nports = ARRAY_SIZE(s500_gpio_ports),
.padctl_arg2val = s500_pad_pinconf_arg2val,
.padctl_val2arg = s500_pad_pinconf_val2arg,
};
static int s500_pinctrl_probe(struct platform_device *pdev)
{
return owl_pinctrl_probe(pdev, &s500_pinctrl_data);
}
static const struct of_device_id s500_pinctrl_of_match[] = {
{ .compatible = "actions,s500-pinctrl", },
{ }
};
static struct platform_driver s500_pinctrl_driver = {
.driver = {
.name = "pinctrl-s500",
.of_match_table = of_match_ptr(s500_pinctrl_of_match),
},
.probe = s500_pinctrl_probe,
};
static int __init s500_pinctrl_init(void)
{
return platform_driver_register(&s500_pinctrl_driver);
}
arch_initcall(s500_pinctrl_init);
static void __exit s500_pinctrl_exit(void)
{
platform_driver_unregister(&s500_pinctrl_driver);
}
module_exit(s500_pinctrl_exit);
MODULE_AUTHOR("Actions Semi Inc.");
MODULE_AUTHOR("Cristian Ciocaltea <[email protected]>");
MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/actions/pinctrl-s500.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6358 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6358_NUM_GPIOS 40
#define BCM6358_MODE_REG 0x18
#define BCM6358_MODE_MUX_NONE 0
#define BCM6358_MODE_MUX_EBI_CS BIT(5)
#define BCM6358_MODE_MUX_UART1 BIT(6)
#define BCM6358_MODE_MUX_SPI_CS BIT(7)
#define BCM6358_MODE_MUX_ASYNC_MODEM BIT(8)
#define BCM6358_MODE_MUX_LEGACY_LED BIT(9)
#define BCM6358_MODE_MUX_SERIAL_LED BIT(10)
#define BCM6358_MODE_MUX_LED BIT(11)
#define BCM6358_MODE_MUX_UTOPIA BIT(12)
#define BCM6358_MODE_MUX_CLKRST BIT(13)
#define BCM6358_MODE_MUX_PWM_SYN_CLK BIT(14)
#define BCM6358_MODE_MUX_SYS_IRQ BIT(15)
struct bcm6358_pingroup {
struct pingroup grp;
const uint16_t mode_val;
/* non-GPIO function muxes require the gpio direction to be set */
const uint16_t direction;
};
struct bcm6358_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
};
struct bcm6358_priv {
struct regmap_field *overlays;
};
#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(BCM6358_MODE_MUX_##bit1 | \
BCM6358_MODE_MUX_##bit2 | \
BCM6358_MODE_MUX_##bit3), \
}
static const struct pinctrl_pin_desc bcm6358_pins[] = {
BCM6358_GPIO_PIN(0, "gpio0", LED, NONE, NONE),
BCM6358_GPIO_PIN(1, "gpio1", LED, NONE, NONE),
BCM6358_GPIO_PIN(2, "gpio2", LED, NONE, NONE),
BCM6358_GPIO_PIN(3, "gpio3", LED, NONE, NONE),
PINCTRL_PIN(4, "gpio4"),
BCM6358_GPIO_PIN(5, "gpio5", SYS_IRQ, NONE, NONE),
BCM6358_GPIO_PIN(6, "gpio6", SERIAL_LED, NONE, NONE),
BCM6358_GPIO_PIN(7, "gpio7", SERIAL_LED, NONE, NONE),
BCM6358_GPIO_PIN(8, "gpio8", PWM_SYN_CLK, NONE, NONE),
BCM6358_GPIO_PIN(9, "gpio09", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(10, "gpio10", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(11, "gpio11", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(12, "gpio12", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(13, "gpio13", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(14, "gpio14", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(15, "gpio15", LEGACY_LED, ASYNC_MODEM, UTOPIA),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
BCM6358_GPIO_PIN(22, "gpio22", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(23, "gpio23", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(24, "gpio24", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(25, "gpio25", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(26, "gpio26", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(27, "gpio27", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(28, "gpio28", UTOPIA, UART1, NONE),
BCM6358_GPIO_PIN(29, "gpio29", UTOPIA, UART1, NONE),
BCM6358_GPIO_PIN(30, "gpio30", UTOPIA, UART1, EBI_CS),
BCM6358_GPIO_PIN(31, "gpio31", UTOPIA, UART1, EBI_CS),
BCM6358_GPIO_PIN(32, "gpio32", SPI_CS, NONE, NONE),
BCM6358_GPIO_PIN(33, "gpio33", SPI_CS, NONE, NONE),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
};
static unsigned ebi_cs_grp_pins[] = { 30, 31 };
static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 };
static unsigned spi_cs_grp_pins[] = { 32, 33 };
static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 };
static unsigned serial_led_grp_pins[] = { 6, 7 };
static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 };
static unsigned led_grp_pins[] = { 0, 1, 2, 3 };
static unsigned utopia_grp_pins[] = {
12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
};
static unsigned pwm_syn_clk_grp_pins[] = { 8 };
static unsigned sys_irq_grp_pins[] = { 5 };
#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \
{ \
.grp = BCM_PIN_GROUP(n), \
.mode_val = BCM6358_MODE_MUX_##bit, \
.direction = dir, \
}
static const struct bcm6358_pingroup bcm6358_groups[] = {
BCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3),
BCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2),
BCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6),
BCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6),
BCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f),
BCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3),
BCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf),
BCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f),
BCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1),
BCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1),
};
static const char * const ebi_cs_groups[] = {
"ebi_cs_grp"
};
static const char * const uart1_groups[] = {
"uart1_grp"
};
static const char * const spi_cs_2_3_groups[] = {
"spi_cs_2_3_grp"
};
static const char * const async_modem_groups[] = {
"async_modem_grp"
};
static const char * const legacy_led_groups[] = {
"legacy_led_grp",
};
static const char * const serial_led_groups[] = {
"serial_led_grp",
};
static const char * const led_groups[] = {
"led_grp",
};
static const char * const clkrst_groups[] = {
"clkrst_grp",
};
static const char * const pwm_syn_clk_groups[] = {
"pwm_syn_clk_grp",
};
static const char * const sys_irq_groups[] = {
"sys_irq_grp",
};
#define BCM6358_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
}
static const struct bcm6358_function bcm6358_funcs[] = {
BCM6358_FUN(ebi_cs),
BCM6358_FUN(uart1),
BCM6358_FUN(spi_cs_2_3),
BCM6358_FUN(async_modem),
BCM6358_FUN(legacy_led),
BCM6358_FUN(serial_led),
BCM6358_FUN(led),
BCM6358_FUN(clkrst),
BCM6358_FUN(pwm_syn_clk),
BCM6358_FUN(sys_irq),
};
static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6358_groups);
}
static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6358_groups[group].grp.name;
}
static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *npins)
{
*pins = bcm6358_groups[group].grp.pins;
*npins = bcm6358_groups[group].grp.npins;
return 0;
}
static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6358_funcs);
}
static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6358_funcs[selector].name;
}
static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6358_funcs[selector].groups;
*num_groups = bcm6358_funcs[selector].num_groups;
return 0;
}
static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6358_priv *priv = pc->driver_data;
const struct bcm6358_pingroup *pg = &bcm6358_groups[group];
unsigned int val = pg->mode_val;
unsigned int mask = val;
unsigned pin;
for (pin = 0; pin < pg->grp.npins; pin++)
mask |= (unsigned long)bcm6358_pins[pin].drv_data;
regmap_field_update_bits(priv->overlays, mask, val);
for (pin = 0; pin < pg->grp.npins; pin++) {
struct pinctrl_gpio_range *range;
unsigned int hw_gpio = bcm6358_pins[pin].number;
range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);
if (range) {
struct gpio_chip *gc = range->gc;
if (pg->direction & BIT(pin))
gc->direction_output(gc, hw_gpio, 0);
else
gc->direction_input(gc, hw_gpio);
}
}
return 0;
}
static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6358_priv *priv = pc->driver_data;
unsigned int mask;
mask = (unsigned long) bcm6358_pins[offset].drv_data;
if (!mask)
return 0;
/* disable all functions using this pin */
return regmap_field_update_bits(priv->overlays, mask, 0);
}
static const struct pinctrl_ops bcm6358_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6358_pinctrl_get_group_name,
.get_group_pins = bcm6358_pinctrl_get_group_pins,
.get_groups_count = bcm6358_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm6358_pmx_ops = {
.get_function_groups = bcm6358_pinctrl_get_groups,
.get_function_name = bcm6358_pinctrl_get_func_name,
.get_functions_count = bcm6358_pinctrl_get_func_count,
.gpio_request_enable = bcm6358_gpio_request_enable,
.set_mux = bcm6358_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6358_soc = {
.ngpios = BCM6358_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6358_pins),
.pctl_ops = &bcm6358_pctl_ops,
.pins = bcm6358_pins,
.pmx_ops = &bcm6358_pmx_ops,
};
static int bcm6358_pinctrl_probe(struct platform_device *pdev)
{
struct reg_field overlays = REG_FIELD(BCM6358_MODE_REG, 0, 15);
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct bcm6358_priv *priv;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
err = bcm63xx_pinctrl_probe(pdev, &bcm6358_soc, (void *) priv);
if (err)
return err;
pc = platform_get_drvdata(pdev);
priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
if (IS_ERR(priv->overlays))
return PTR_ERR(priv->overlays);
return 0;
}
static const struct of_device_id bcm6358_pinctrl_match[] = {
{ .compatible = "brcm,bcm6358-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6358_pinctrl_driver = {
.probe = bcm6358_pinctrl_probe,
.driver = {
.name = "bcm6358-pinctrl",
.of_match_table = bcm6358_pinctrl_match,
},
};
builtin_platform_driver(bcm6358_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm6358.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6318 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6318_NUM_GPIOS 50
#define BCM6318_NUM_MUX 48
#define BCM6318_MODE_REG 0x18
#define BCM6318_MUX_REG 0x1c
#define BCM6328_MUX_MASK GENMASK(1, 0)
#define BCM6318_PAD_REG 0x54
#define BCM6328_PAD_MASK GENMASK(3, 0)
struct bcm6318_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned mode_val:1;
unsigned mux_val:2;
};
static const struct pinctrl_pin_desc bcm6318_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
PINCTRL_PIN(48, "gpio48"),
PINCTRL_PIN(49, "gpio49"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
static struct pingroup bcm6318_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
};
/* GPIO_MODE */
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
/* PINMUX_SEL */
static const char * const ephy0_spd_led_groups[] = {
"gpio0",
};
static const char * const ephy1_spd_led_groups[] = {
"gpio1",
};
static const char * const ephy2_spd_led_groups[] = {
"gpio2",
};
static const char * const ephy3_spd_led_groups[] = {
"gpio3",
};
static const char * const ephy0_act_led_groups[] = {
"gpio4",
};
static const char * const ephy1_act_led_groups[] = {
"gpio5",
};
static const char * const ephy2_act_led_groups[] = {
"gpio6",
};
static const char * const ephy3_act_led_groups[] = {
"gpio7",
};
static const char * const serial_led_data_groups[] = {
"gpio6",
};
static const char * const serial_led_clk_groups[] = {
"gpio7",
};
static const char * const inet_act_led_groups[] = {
"gpio8",
};
static const char * const inet_fail_led_groups[] = {
"gpio9",
};
static const char * const dsl_led_groups[] = {
"gpio10",
};
static const char * const post_fail_led_groups[] = {
"gpio11",
};
static const char * const wlan_wps_led_groups[] = {
"gpio12",
};
static const char * const usb_pwron_groups[] = {
"gpio13",
};
static const char * const usb_device_led_groups[] = {
"gpio13",
};
static const char * const usb_active_groups[] = {
"gpio40",
};
#define BCM6318_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mode_val = 1, \
}
#define BCM6318_MUX_FUN(n, mux) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mux_val = mux, \
}
static const struct bcm6318_function bcm6318_funcs[] = {
BCM6318_MODE_FUN(led),
BCM6318_MUX_FUN(ephy0_spd_led, 1),
BCM6318_MUX_FUN(ephy1_spd_led, 1),
BCM6318_MUX_FUN(ephy2_spd_led, 1),
BCM6318_MUX_FUN(ephy3_spd_led, 1),
BCM6318_MUX_FUN(ephy0_act_led, 1),
BCM6318_MUX_FUN(ephy1_act_led, 1),
BCM6318_MUX_FUN(ephy2_act_led, 1),
BCM6318_MUX_FUN(ephy3_act_led, 1),
BCM6318_MUX_FUN(serial_led_data, 3),
BCM6318_MUX_FUN(serial_led_clk, 3),
BCM6318_MUX_FUN(inet_act_led, 1),
BCM6318_MUX_FUN(inet_fail_led, 1),
BCM6318_MUX_FUN(dsl_led, 1),
BCM6318_MUX_FUN(post_fail_led, 1),
BCM6318_MUX_FUN(wlan_wps_led, 1),
BCM6318_MUX_FUN(usb_pwron, 1),
BCM6318_MUX_FUN(usb_device_led, 2),
BCM6318_MUX_FUN(usb_active, 2),
};
static inline unsigned int bcm6318_mux_off(unsigned int pin)
{
return BCM6318_MUX_REG + (pin / 16) * 4;
}
static inline unsigned int bcm6318_pad_off(unsigned int pin)
{
return BCM6318_PAD_REG + (pin / 8) * 4;
}
static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6318_groups);
}
static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6318_groups[group].name;
}
static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *npins)
{
*pins = bcm6318_groups[group].pins;
*npins = bcm6318_groups[group].npins;
return 0;
}
static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6318_funcs);
}
static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6318_funcs[selector].name;
}
static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6318_funcs[selector].groups;
*num_groups = bcm6318_funcs[selector].num_groups;
return 0;
}
static inline void bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,
unsigned int mode, unsigned int mux)
{
if (pin < BCM63XX_BANK_GPIOS)
regmap_update_bits(pc->regs, BCM6318_MODE_REG, BIT(pin),
mode ? BIT(pin) : 0);
if (pin < BCM6318_NUM_MUX)
regmap_update_bits(pc->regs,
bcm6318_mux_off(pin),
BCM6328_MUX_MASK << ((pin % 16) * 2),
mux << ((pin % 16) * 2));
}
static inline void bcm6318_set_pad(struct bcm63xx_pinctrl *pc, unsigned pin,
uint8_t val)
{
regmap_update_bits(pc->regs, bcm6318_pad_off(pin),
BCM6328_PAD_MASK << ((pin % 8) * 4),
val << ((pin % 8) * 4));
}
static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct pingroup *pg = &bcm6318_groups[group];
const struct bcm6318_function *f = &bcm6318_funcs[selector];
bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
return 0;
}
static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
if (offset < 13) {
/* GPIOs 0-12 use mux 0 as GPIO function */
bcm6318_rmw_mux(pc, offset, 0, 0);
} else if (offset < 42) {
/* GPIOs 13-41 use mux 3 as GPIO function */
bcm6318_rmw_mux(pc, offset, 0, 3);
bcm6318_set_pad(pc, offset, 0);
}
return 0;
}
static const struct pinctrl_ops bcm6318_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6318_pinctrl_get_group_name,
.get_group_pins = bcm6318_pinctrl_get_group_pins,
.get_groups_count = bcm6318_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm6318_pmx_ops = {
.get_function_groups = bcm6318_pinctrl_get_groups,
.get_function_name = bcm6318_pinctrl_get_func_name,
.get_functions_count = bcm6318_pinctrl_get_func_count,
.gpio_request_enable = bcm6318_gpio_request_enable,
.set_mux = bcm6318_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6318_soc = {
.ngpios = BCM6318_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6318_pins),
.pctl_ops = &bcm6318_pctl_ops,
.pins = bcm6318_pins,
.pmx_ops = &bcm6318_pmx_ops,
};
static int bcm6318_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6318_soc, NULL);
}
static const struct of_device_id bcm6318_pinctrl_match[] = {
{ .compatible = "brcm,bcm6318-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6318_pinctrl_driver = {
.probe = bcm6318_pinctrl_probe,
.driver = {
.name = "bcm6318-pinctrl",
.of_match_table = bcm6318_pinctrl_match,
},
};
builtin_platform_driver(bcm6318_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm6318.c
|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2021 Rafał Miłecki <[email protected]> */
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
#include "../core.h"
#include "../pinmux.h"
#define BCM4908_NUM_PINS 86
#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
#define BCM4908_TEST_PORT_COMMAND 0x0c
#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
struct bcm4908_pinctrl {
struct device *dev;
void __iomem *base;
struct mutex mutex;
struct pinctrl_dev *pctldev;
struct pinctrl_desc pctldesc;
};
/*
* Groups
*/
struct bcm4908_pinctrl_pin_setup {
unsigned int number;
unsigned int function;
};
static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
{ 0, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
{ 1, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
{ 2, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
{ 3, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
{ 4, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
{ 5, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
{ 6, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
{ 7, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
{ 8, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
{ 9, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
{ 10, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
{ 11, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
{ 12, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
{ 13, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
{ 14, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
{ 15, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
{ 16, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
{ 17, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
{ 18, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
{ 19, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
{ 20, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
{ 21, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
{ 22, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
{ 23, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
{ 24, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
{ 25, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
{ 26, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
{ 27, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
{ 28, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
{ 29, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
{ 30, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
{ 31, 3 },
};
static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
{ 8, 2 },
};
static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
{ 9, 2 },
};
static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
{ 0, 2 },
};
static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
{ 1, 2 },
};
static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
{ 30, 2 },
};
static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
{ 10, 0 }, /* CTS */
{ 11, 0 }, /* RTS */
{ 12, 0 }, /* RXD */
{ 13, 0 }, /* TXD */
};
static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
{ 18, 0 }, /* SDA */
{ 19, 0 }, /* SCL */
};
static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
{ 22, 0 }, /* SDA */
{ 23, 0 }, /* SCL */
};
static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
{ 27, 0 }, /* MCLK */
{ 28, 0 }, /* LRCK */
{ 29, 0 }, /* SDATA */
{ 30, 0 }, /* SCLK */
};
static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
{ 32, 0 },
{ 33, 0 },
{ 34, 0 },
{ 43, 0 },
{ 44, 0 },
{ 45, 0 },
{ 56, 1 },
};
static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
{ 35, 0 },
{ 36, 0 },
{ 37, 0 },
{ 38, 0 },
{ 39, 0 },
{ 40, 0 },
{ 41, 0 },
{ 42, 0 },
};
static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
{ 46, 0 },
{ 47, 0 },
};
static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
{ 63, 0 },
{ 64, 0 },
};
static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
{ 66, 0 },
{ 67, 0 },
};
struct bcm4908_pinctrl_grp {
const char *name;
const struct bcm4908_pinctrl_pin_setup *pins;
const unsigned int num_pins;
};
static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
{ "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
{ "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
{ "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
{ "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
{ "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
{ "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
{ "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
{ "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
{ "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
{ "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
{ "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
{ "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
{ "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
{ "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
{ "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
{ "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
{ "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
{ "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
{ "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
{ "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
{ "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
{ "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
{ "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
{ "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
{ "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
{ "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
{ "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
{ "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
{ "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
{ "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
{ "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
{ "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
{ "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
{ "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
{ "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
{ "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
{ "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
{ "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
{ "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
{ "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
{ "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
{ "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
{ "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
{ "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
{ "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
{ "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
};
/*
* Functions
*/
struct bcm4908_pinctrl_function {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
static const char * const led_0_groups[] = { "led_0_grp_a" };
static const char * const led_1_groups[] = { "led_1_grp_a" };
static const char * const led_2_groups[] = { "led_2_grp_a" };
static const char * const led_3_groups[] = { "led_3_grp_a" };
static const char * const led_4_groups[] = { "led_4_grp_a" };
static const char * const led_5_groups[] = { "led_5_grp_a" };
static const char * const led_6_groups[] = { "led_6_grp_a" };
static const char * const led_7_groups[] = { "led_7_grp_a" };
static const char * const led_8_groups[] = { "led_8_grp_a" };
static const char * const led_9_groups[] = { "led_9_grp_a" };
static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
static const char * const led_14_groups[] = { "led_14_grp_a" };
static const char * const led_15_groups[] = { "led_15_grp_a" };
static const char * const led_16_groups[] = { "led_16_grp_a" };
static const char * const led_17_groups[] = { "led_17_grp_a" };
static const char * const led_18_groups[] = { "led_18_grp_a" };
static const char * const led_19_groups[] = { "led_19_grp_a" };
static const char * const led_20_groups[] = { "led_20_grp_a" };
static const char * const led_21_groups[] = { "led_21_grp_a" };
static const char * const led_22_groups[] = { "led_22_grp_a" };
static const char * const led_23_groups[] = { "led_23_grp_a" };
static const char * const led_24_groups[] = { "led_24_grp_a" };
static const char * const led_25_groups[] = { "led_25_grp_a" };
static const char * const led_26_groups[] = { "led_26_grp_a" };
static const char * const led_27_groups[] = { "led_27_grp_a" };
static const char * const led_28_groups[] = { "led_28_grp_a" };
static const char * const led_29_groups[] = { "led_29_grp_a" };
static const char * const led_30_groups[] = { "led_30_grp_a" };
static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
static const char * const hs_uart_groups[] = { "hs_uart_grp" };
static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
static const char * const i2s_groups[] = { "i2s_grp" };
static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
static const char * const nand_data_groups[] = { "nand_data_grp" };
static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
{ "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
{ "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
{ "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
{ "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
{ "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
{ "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
{ "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
{ "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
{ "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
{ "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
{ "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
{ "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
{ "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
{ "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
{ "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
{ "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
{ "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
{ "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
{ "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
{ "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
{ "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
{ "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
{ "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
{ "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
{ "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
{ "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
{ "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
{ "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
{ "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
{ "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
{ "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
{ "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
{ "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
{ "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
{ "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
{ "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
{ "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
{ "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
{ "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
{ "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
};
/*
* Groups code
*/
static const struct pinctrl_ops bcm4908_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinconf_generic_dt_free_map,
};
/*
* Functions code
*/
static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
unsigned int func_selector,
unsigned int group_selector)
{
struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct bcm4908_pinctrl_grp *group;
struct group_desc *group_desc;
int i;
group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
if (!group_desc)
return -EINVAL;
group = group_desc->data;
mutex_lock(&bcm4908_pinctrl->mutex);
for (i = 0; i < group->num_pins; i++) {
u32 lsb = 0;
lsb |= group->pins[i].number;
lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
}
mutex_unlock(&bcm4908_pinctrl->mutex);
return 0;
}
static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = bcm4908_pinctrl_set_mux,
};
/*
* Controller code
*/
static struct pinctrl_desc bcm4908_pinctrl_desc = {
.name = "bcm4908-pinctrl",
.pctlops = &bcm4908_pinctrl_ops,
.pmxops = &bcm4908_pinctrl_pmxops,
};
static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
{ .compatible = "brcm,bcm4908-pinctrl", },
{ }
};
static int bcm4908_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct bcm4908_pinctrl *bcm4908_pinctrl;
struct pinctrl_desc *pctldesc;
struct pinctrl_pin_desc *pins;
char **pin_names;
int i;
bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
if (!bcm4908_pinctrl)
return -ENOMEM;
pctldesc = &bcm4908_pinctrl->pctldesc;
platform_set_drvdata(pdev, bcm4908_pinctrl);
/* Set basic properties */
bcm4908_pinctrl->dev = dev;
bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(bcm4908_pinctrl->base))
return PTR_ERR(bcm4908_pinctrl->base);
mutex_init(&bcm4908_pinctrl->mutex);
memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
/* Set pinctrl properties */
pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS);
if (IS_ERR(pin_names))
return PTR_ERR(pin_names);
pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < BCM4908_NUM_PINS; i++) {
pins[i].number = i;
pins[i].name = pin_names[i];
}
pctldesc->pins = pins;
pctldesc->npins = BCM4908_NUM_PINS;
/* Register */
bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
if (IS_ERR(bcm4908_pinctrl->pctldev))
return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
"Failed to register pinctrl\n");
/* Groups */
for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
int *pins;
int j;
pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (j = 0; j < group->num_pins; j++)
pins[j] = group->pins[j].number;
pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
pins, group->num_pins, (void *)group);
}
/* Functions */
for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
function->name,
function->groups,
function->num_groups, NULL);
}
return 0;
}
static struct platform_driver bcm4908_pinctrl_driver = {
.probe = bcm4908_pinctrl_probe,
.driver = {
.name = "bcm4908-pinctrl",
.of_match_table = bcm4908_pinctrl_of_match_table,
},
};
module_platform_driver(bcm4908_pinctrl_driver);
MODULE_AUTHOR("Rafał Miłecki");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm4908.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM63xx GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/gpio/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-bcm63xx.h"
#define BCM63XX_BANK_SIZE 4
#define BCM63XX_DIROUT_REG 0x04
#define BCM63XX_DATA_REG 0x0c
static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
unsigned int line = offset % BCM63XX_BANK_GPIOS;
unsigned int stride = offset / BCM63XX_BANK_GPIOS;
*reg = base - stride * BCM63XX_BANK_SIZE;
*mask = BIT(line);
return 0;
}
static const struct of_device_id bcm63xx_gpio_of_match[] = {
{ .compatible = "brcm,bcm6318-gpio", },
{ .compatible = "brcm,bcm6328-gpio", },
{ .compatible = "brcm,bcm6358-gpio", },
{ .compatible = "brcm,bcm6362-gpio", },
{ .compatible = "brcm,bcm6368-gpio", },
{ .compatible = "brcm,bcm63268-gpio", },
{ /* sentinel */ }
};
static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node,
const struct bcm63xx_pinctrl_soc *soc,
struct bcm63xx_pinctrl *pc)
{
struct gpio_regmap_config grc = {0};
grc.parent = dev;
grc.fwnode = &node->fwnode;
grc.ngpio = soc->ngpios;
grc.ngpio_per_reg = BCM63XX_BANK_GPIOS;
grc.regmap = pc->regs;
grc.reg_dat_base = BCM63XX_DATA_REG;
grc.reg_dir_out_base = BCM63XX_DIROUT_REG;
grc.reg_set_base = BCM63XX_DATA_REG;
grc.reg_mask_xlate = bcm63xx_reg_mask_xlate;
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc));
}
int bcm63xx_pinctrl_probe(struct platform_device *pdev,
const struct bcm63xx_pinctrl_soc *soc,
void *driver_data)
{
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct device_node *node;
int err;
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
if (!pc)
return -ENOMEM;
platform_set_drvdata(pdev, pc);
pc->dev = dev;
pc->driver_data = driver_data;
pc->regs = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
pc->pctl_desc.name = dev_name(dev);
pc->pctl_desc.pins = soc->pins;
pc->pctl_desc.npins = soc->npins;
pc->pctl_desc.pctlops = soc->pctl_ops;
pc->pctl_desc.pmxops = soc->pmx_ops;
pc->pctl_desc.owner = THIS_MODULE;
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
if (IS_ERR(pc->pctl_dev))
return PTR_ERR(pc->pctl_dev);
for_each_child_of_node(dev->parent->of_node, node) {
if (of_match_node(bcm63xx_gpio_of_match, node)) {
err = bcm63xx_gpio_probe(dev, node, soc, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
of_node_put(node);
return err;
}
}
}
return 0;
}
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm63xx.c
|
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2015 Broadcom Corporation
*
* This file contains the Northstar plus (NSP) IOMUX driver that supports
* group based PINMUX configuration. The Northstar plus IOMUX controller
* allows pins to be individually muxed to GPIO function. The NAND and MMC is
* a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
* To select PWM, one need to enable the corresponding gpio_b as well.
*
* gpio_a (8 - 11)
* +----------
* |
* gpio_a (8-11) | gpio_b (0 - 3)
* ------------------------+-------+----------
* |
* | pwm (0 - 3)
* +----------
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#define NSP_MUX_BASE0 0x00
#define NSP_MUX_BASE1 0x01
#define NSP_MUX_BASE2 0x02
/*
* nsp IOMUX register description
*
* @base: base 0 or base 1
* @shift: bit shift for mux configuration of a group
* @mask: bit mask of the function
* @alt: alternate function to set to
*/
struct nsp_mux {
unsigned int base;
unsigned int shift;
unsigned int mask;
unsigned int alt;
};
/*
* Keep track of nsp IOMUX configuration and prevent double configuration
*
* @nsp_mux: nsp IOMUX register description
* @is_configured: flag to indicate whether a mux setting has already been
* configured
*/
struct nsp_mux_log {
struct nsp_mux mux;
bool is_configured;
};
/*
* Group based IOMUX configuration
*
* @name: name of the group
* @pins: array of pins used by this group
* @num_pins: total number of pins used by this group
* @mux: nsp group based IOMUX configuration
*/
struct nsp_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
const struct nsp_mux mux;
};
/*
* nsp mux function and supported pin groups
*
* @name: name of the function
* @groups: array of groups that can be supported by this function
* @num_groups: total number of groups that can be supported by this function
*/
struct nsp_pin_function {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
/*
* nsp IOMUX pinctrl core
*
* @pctl: pointer to pinctrl_dev
* @dev: pointer to device
* @base0: first mux register
* @base1: second mux register
* @base2: third mux register
* @groups: pointer to array of groups
* @num_groups: total number of groups
* @functions: pointer to array of functions
* @num_functions: total number of functions
* @mux_log: pointer to the array of mux logs
* @lock: lock to protect register access
*/
struct nsp_pinctrl {
struct pinctrl_dev *pctl;
struct device *dev;
void __iomem *base0;
void __iomem *base1;
void __iomem *base2;
const struct nsp_pin_group *groups;
unsigned int num_groups;
const struct nsp_pin_function *functions;
unsigned int num_functions;
struct nsp_mux_log *mux_log;
spinlock_t lock;
};
/*
* Description of a pin in nsp
*
* @pin: pin number
* @name: pin name
* @gpio_select: reg data to select GPIO
*/
struct nsp_pin {
unsigned int pin;
char *name;
unsigned int gpio_select;
};
#define NSP_PIN_DESC(p, n, g) \
{ \
.pin = p, \
.name = n, \
.gpio_select = g, \
}
/*
* List of muxable pins in nsp
*/
static struct nsp_pin nsp_pins[] = {
NSP_PIN_DESC(0, "spi_clk", 1),
NSP_PIN_DESC(1, "spi_ss", 1),
NSP_PIN_DESC(2, "spi_mosi", 1),
NSP_PIN_DESC(3, "spi_miso", 1),
NSP_PIN_DESC(4, "scl", 1),
NSP_PIN_DESC(5, "sda", 1),
NSP_PIN_DESC(6, "mdc", 1),
NSP_PIN_DESC(7, "mdio", 1),
NSP_PIN_DESC(8, "pwm0", 1),
NSP_PIN_DESC(9, "pwm1", 1),
NSP_PIN_DESC(10, "pwm2", 1),
NSP_PIN_DESC(11, "pwm3", 1),
NSP_PIN_DESC(12, "uart1_rx", 1),
NSP_PIN_DESC(13, "uart1_tx", 1),
NSP_PIN_DESC(14, "uart1_cts", 1),
NSP_PIN_DESC(15, "uart1_rts", 1),
NSP_PIN_DESC(16, "uart2_rx", 1),
NSP_PIN_DESC(17, "uart2_tx", 1),
NSP_PIN_DESC(18, "synce", 0),
NSP_PIN_DESC(19, "sata0_led", 0),
NSP_PIN_DESC(20, "sata1_led", 0),
NSP_PIN_DESC(21, "xtal_out", 1),
NSP_PIN_DESC(22, "sdio_pwr", 1),
NSP_PIN_DESC(23, "sdio_en_1p8v", 1),
NSP_PIN_DESC(24, "gpio_24", 1),
NSP_PIN_DESC(25, "gpio_25", 1),
NSP_PIN_DESC(26, "p5_led0", 0),
NSP_PIN_DESC(27, "p5_led1", 0),
NSP_PIN_DESC(28, "gpio_28", 1),
NSP_PIN_DESC(29, "gpio_29", 1),
NSP_PIN_DESC(30, "gpio_30", 1),
NSP_PIN_DESC(31, "gpio_31", 1),
NSP_PIN_DESC(32, "nand_ale", 0),
NSP_PIN_DESC(33, "nand_ce0", 0),
NSP_PIN_DESC(34, "nand_r/b", 0),
NSP_PIN_DESC(35, "nand_dq0", 0),
NSP_PIN_DESC(36, "nand_dq1", 0),
NSP_PIN_DESC(37, "nand_dq2", 0),
NSP_PIN_DESC(38, "nand_dq3", 0),
NSP_PIN_DESC(39, "nand_dq4", 0),
NSP_PIN_DESC(40, "nand_dq5", 0),
NSP_PIN_DESC(41, "nand_dq6", 0),
NSP_PIN_DESC(42, "nand_dq7", 0),
};
/*
* List of groups of pins
*/
static const unsigned int spi_pins[] = {0, 1, 2, 3};
static const unsigned int i2c_pins[] = {4, 5};
static const unsigned int mdio_pins[] = {6, 7};
static const unsigned int pwm0_pins[] = {8};
static const unsigned int gpio_b_0_pins[] = {8};
static const unsigned int pwm1_pins[] = {9};
static const unsigned int gpio_b_1_pins[] = {9};
static const unsigned int pwm2_pins[] = {10};
static const unsigned int gpio_b_2_pins[] = {10};
static const unsigned int pwm3_pins[] = {11};
static const unsigned int gpio_b_3_pins[] = {11};
static const unsigned int uart1_pins[] = {12, 13, 14, 15};
static const unsigned int uart2_pins[] = {16, 17};
static const unsigned int synce_pins[] = {18};
static const unsigned int sata0_led_pins[] = {19};
static const unsigned int sata1_led_pins[] = {20};
static const unsigned int xtal_out_pins[] = {21};
static const unsigned int sdio_pwr_pins[] = {22};
static const unsigned int sdio_1p8v_pins[] = {23};
static const unsigned int switch_p05_led0_pins[] = {26};
static const unsigned int switch_p05_led1_pins[] = {27};
static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
40, 41, 42};
static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
40, 41, 42};
#define NSP_PIN_GROUP(group_name, ba, sh, ma, al) \
{ \
.name = __stringify(group_name) "_grp", \
.pins = group_name ## _pins, \
.num_pins = ARRAY_SIZE(group_name ## _pins), \
.mux = { \
.base = ba, \
.shift = sh, \
.mask = ma, \
.alt = al, \
} \
}
/*
* List of nsp pin groups
*/
static const struct nsp_pin_group nsp_pin_groups[] = {
NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
};
/*
* List of groups supported by functions
*/
static const char * const spi_grps[] = {"spi_grp"};
static const char * const i2c_grps[] = {"i2c_grp"};
static const char * const mdio_grps[] = {"mdio_grp"};
static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp"
, "pwm3_grp"};
static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp",
"gpio_b_2_grp", "gpio_b_3_grp"};
static const char * const uart1_grps[] = {"uart1_grp"};
static const char * const uart2_grps[] = {"uart2_grp"};
static const char * const synce_grps[] = {"synce_grp"};
static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"};
static const char * const xtal_out_grps[] = {"xtal_out_grp"};
static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"};
static const char * const switch_led_grps[] = {"switch_p05_led0_grp",
"switch_p05_led1_grp"};
static const char * const nand_grps[] = {"nand_grp"};
static const char * const emmc_grps[] = {"emmc_grp"};
#define NSP_PIN_FUNCTION(func) \
{ \
.name = #func, \
.groups = func ## _grps, \
.num_groups = ARRAY_SIZE(func ## _grps), \
}
/*
* List of supported functions in nsp
*/
static const struct nsp_pin_function nsp_pin_functions[] = {
NSP_PIN_FUNCTION(spi),
NSP_PIN_FUNCTION(i2c),
NSP_PIN_FUNCTION(mdio),
NSP_PIN_FUNCTION(pwm),
NSP_PIN_FUNCTION(gpio_b),
NSP_PIN_FUNCTION(uart1),
NSP_PIN_FUNCTION(uart2),
NSP_PIN_FUNCTION(synce),
NSP_PIN_FUNCTION(sata_led),
NSP_PIN_FUNCTION(xtal_out),
NSP_PIN_FUNCTION(sdio),
NSP_PIN_FUNCTION(switch_led),
NSP_PIN_FUNCTION(nand),
NSP_PIN_FUNCTION(emmc)
};
static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_groups;
}
static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev,
unsigned int selector)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->groups[selector].name;
}
static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev,
unsigned int selector, const unsigned int **pins,
unsigned int *num_pins)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*pins = pinctrl->groups[selector].pins;
*num_pins = pinctrl->groups[selector].num_pins;
return 0;
}
static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, " %s", dev_name(pctrl_dev->dev));
}
static const struct pinctrl_ops nsp_pinctrl_ops = {
.get_groups_count = nsp_get_groups_count,
.get_group_name = nsp_get_group_name,
.get_group_pins = nsp_get_group_pins,
.pin_dbg_show = nsp_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
};
static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_functions;
}
static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev,
unsigned int selector)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->functions[selector].name;
}
static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*groups = pinctrl->functions[selector].groups;
*num_groups = pinctrl->functions[selector].num_groups;
return 0;
}
static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,
const struct nsp_pin_function *func,
const struct nsp_pin_group *grp,
struct nsp_mux_log *mux_log)
{
const struct nsp_mux *mux = &grp->mux;
int i;
u32 val, mask;
unsigned long flags;
void __iomem *base_address;
for (i = 0; i < pinctrl->num_groups; i++) {
if ((mux->shift != mux_log[i].mux.shift) ||
(mux->base != mux_log[i].mux.base))
continue;
/* if this is a new configuration, just do it! */
if (!mux_log[i].is_configured)
break;
/*
* IOMUX has been configured previously and one is trying to
* configure it to a different function
*/
if (mux_log[i].mux.alt != mux->alt) {
dev_err(pinctrl->dev,
"double configuration error detected!\n");
dev_err(pinctrl->dev, "func:%s grp:%s\n",
func->name, grp->name);
return -EINVAL;
}
return 0;
}
if (i == pinctrl->num_groups)
return -EINVAL;
mask = mux->mask;
mux_log[i].mux.alt = mux->alt;
mux_log[i].is_configured = true;
switch (mux->base) {
case NSP_MUX_BASE0:
base_address = pinctrl->base0;
break;
case NSP_MUX_BASE1:
base_address = pinctrl->base1;
break;
case NSP_MUX_BASE2:
base_address = pinctrl->base2;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address);
val &= ~(mask << grp->mux.shift);
val |= grp->mux.alt << grp->mux.shift;
writel(val, base_address);
spin_unlock_irqrestore(&pinctrl->lock, flags);
return 0;
}
static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
unsigned int func_select, unsigned int grp_select)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct nsp_pin_function *func;
const struct nsp_pin_group *grp;
if (grp_select >= pinctrl->num_groups ||
func_select >= pinctrl->num_functions)
return -EINVAL;
func = &pinctrl->functions[func_select];
grp = &pinctrl->groups[grp_select];
dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
func_select, func->name, grp_select, grp->name);
dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,
grp->mux.alt);
return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
}
static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->base0);
if ((val & BIT(pin)) != (*gpio_select << pin)) {
val &= ~BIT(pin);
val |= *gpio_select << pin;
writel(val, pinctrl->base0);
}
spin_unlock_irqrestore(&pinctrl->lock, flags);
return 0;
}
static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->base0);
if ((val & (1 << pin)) == (*gpio_select << pin)) {
val &= ~(1 << pin);
if (!(*gpio_select))
val |= (1 << pin);
writel(val, pinctrl->base0);
}
spin_unlock_irqrestore(&pinctrl->lock, flags);
}
static const struct pinmux_ops nsp_pinmux_ops = {
.get_functions_count = nsp_get_functions_count,
.get_function_name = nsp_get_function_name,
.get_function_groups = nsp_get_function_groups,
.set_mux = nsp_pinmux_enable,
.gpio_request_enable = nsp_gpio_request_enable,
.gpio_disable_free = nsp_gpio_disable_free,
};
static struct pinctrl_desc nsp_pinctrl_desc = {
.name = "nsp-pinmux",
.pctlops = &nsp_pinctrl_ops,
.pmxops = &nsp_pinmux_ops,
};
static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
{
struct nsp_mux_log *log;
unsigned int i;
u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups);
pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,
sizeof(struct nsp_mux_log),
GFP_KERNEL);
if (!pinctrl->mux_log)
return -ENOMEM;
for (i = 0; i < no_of_groups; i++) {
log = &pinctrl->mux_log[i];
log->mux.base = nsp_pin_groups[i].mux.base;
log->mux.shift = nsp_pin_groups[i].mux.shift;
log->mux.alt = 0;
log->is_configured = false;
}
return 0;
}
static int nsp_pinmux_probe(struct platform_device *pdev)
{
struct nsp_pinctrl *pinctrl;
struct resource *res;
int i, ret;
struct pinctrl_pin_desc *pins;
unsigned int num_pins = ARRAY_SIZE(nsp_pins);
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
return -ENOMEM;
pinctrl->dev = &pdev->dev;
platform_set_drvdata(pdev, pinctrl);
spin_lock_init(&pinctrl->lock);
pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pinctrl->base0))
return PTR_ERR(pinctrl->base0);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
return -EINVAL;
pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pinctrl->base1) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return -ENOMEM;
}
pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(pinctrl->base2))
return PTR_ERR(pinctrl->base2);
ret = nsp_mux_log_init(pinctrl);
if (ret) {
dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
return ret;
}
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < num_pins; i++) {
pins[i].number = nsp_pins[i].pin;
pins[i].name = nsp_pins[i].name;
pins[i].drv_data = &nsp_pins[i].gpio_select;
}
pinctrl->groups = nsp_pin_groups;
pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);
pinctrl->functions = nsp_pin_functions;
pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
nsp_pinctrl_desc.pins = pins;
nsp_pinctrl_desc.npins = num_pins;
pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
pinctrl);
if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");
return PTR_ERR(pinctrl->pctl);
}
return 0;
}
static const struct of_device_id nsp_pinmux_of_match[] = {
{ .compatible = "brcm,nsp-pinmux" },
{ }
};
static struct platform_driver nsp_pinmux_driver = {
.driver = {
.name = "nsp-pinmux",
.of_match_table = nsp_pinmux_of_match,
},
.probe = nsp_pinmux_probe,
};
static int __init nsp_pinmux_init(void)
{
return platform_driver_register(&nsp_pinmux_driver);
}
arch_initcall(nsp_pinmux_init);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
|
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2016 Broadcom Corporation
*
* This file contains the Northstar2 IOMUX driver that supports group
* based PINMUX configuration. The PWM is functional only when the
* corresponding mfio pin group is selected as gpio.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#define NS2_NUM_IOMUX 19
#define NS2_NUM_PWM_MUX 4
#define NS2_PIN_MUX_BASE0 0x00
#define NS2_PIN_MUX_BASE1 0x01
#define NS2_PIN_CONF_BASE 0x02
#define NS2_MUX_PAD_FUNC1_OFFSET 0x04
#define NS2_PIN_SRC_MASK 0x01
#define NS2_PIN_PULL_MASK 0x03
#define NS2_PIN_DRIVE_STRENGTH_MASK 0x07
#define NS2_PIN_PULL_UP 0x01
#define NS2_PIN_PULL_DOWN 0x02
#define NS2_PIN_INPUT_EN_MASK 0x01
/*
* Northstar2 IOMUX register description
*
* @base: base address number
* @offset: register offset for mux configuration of a group
* @shift: bit shift for mux configuration of a group
* @mask: mask bits
* @alt: alternate function to set to
*/
struct ns2_mux {
unsigned int base;
unsigned int offset;
unsigned int shift;
unsigned int mask;
unsigned int alt;
};
/*
* Keep track of Northstar2 IOMUX configuration and prevent double
* configuration
*
* @ns2_mux: Northstar2 IOMUX register description
* @is_configured: flag to indicate whether a mux setting has already
* been configured
*/
struct ns2_mux_log {
struct ns2_mux mux;
bool is_configured;
};
/*
* Group based IOMUX configuration
*
* @name: name of the group
* @pins: array of pins used by this group
* @num_pins: total number of pins used by this group
* @mux: Northstar2 group based IOMUX configuration
*/
struct ns2_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
const struct ns2_mux mux;
};
/*
* Northstar2 mux function and supported pin groups
*
* @name: name of the function
* @groups: array of groups that can be supported by this function
* @num_groups: total number of groups that can be supported by function
*/
struct ns2_pin_function {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
/*
* Northstar2 IOMUX pinctrl core
*
* @pctl: pointer to pinctrl_dev
* @dev: pointer to device
* @base0: first IOMUX register base
* @base1: second IOMUX register base
* @pinconf_base: configuration register base
* @groups: pointer to array of groups
* @num_groups: total number of groups
* @functions: pointer to array of functions
* @num_functions: total number of functions
* @mux_log: pointer to the array of mux logs
* @lock: lock to protect register access
*/
struct ns2_pinctrl {
struct pinctrl_dev *pctl;
struct device *dev;
void __iomem *base0;
void __iomem *base1;
void __iomem *pinconf_base;
const struct ns2_pin_group *groups;
unsigned int num_groups;
const struct ns2_pin_function *functions;
unsigned int num_functions;
struct ns2_mux_log *mux_log;
spinlock_t lock;
};
/*
* Pin configuration info
*
* @base: base address number
* @offset: register offset from base
* @src_shift: slew rate control bit shift in the register
* @input_en: input enable control bit shift
* @pull_shift: pull-up/pull-down control bit shift in the register
* @drive_shift: drive strength control bit shift in the register
*/
struct ns2_pinconf {
unsigned int base;
unsigned int offset;
unsigned int src_shift;
unsigned int input_en;
unsigned int pull_shift;
unsigned int drive_shift;
};
/*
* Description of a pin in Northstar2
*
* @pin: pin number
* @name: pin name
* @pin_conf: pin configuration structure
*/
struct ns2_pin {
unsigned int pin;
char *name;
struct ns2_pinconf pin_conf;
};
#define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \
{ \
.pin = p, \
.name = n, \
.pin_conf = { \
.base = b, \
.offset = o, \
.src_shift = s, \
.input_en = i, \
.pull_shift = pu, \
.drive_shift = d, \
} \
}
/*
* List of pins in Northstar2
*/
static struct ns2_pin ns2_pins[] = {
NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
};
/*
* List of groups of pins
*/
static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
static const unsigned int gpio_0_1_pins[] = {24, 25};
static const unsigned int pwm_0_pins[] = {24};
static const unsigned int pwm_1_pins[] = {25};
static const unsigned int uart1_ext_clk_pins[] = {26};
static const unsigned int nor_adv_pins[] = {26};
static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
static const unsigned int pwm_2_pins[] = {27};
static const unsigned int pwm_3_pins[] = {28};
static const unsigned int gpio_6_7_pins[] = {31, 32};
static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
static const unsigned int nor_addr_4_5_pins[] = {31, 32};
static const unsigned int gpio_8_9_pins[] = {33, 34};
static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
static const unsigned int nor_addr_6_7_pins[] = {33, 34};
static const unsigned int gpio_10_11_pins[] = {35, 36};
static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
static const unsigned int nor_addr_8_9_pins[] = {35, 36};
static const unsigned int gpio_12_13_pins[] = {37, 38};
static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
static const unsigned int nor_addr_10_11_pins[] = {37, 38};
static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
static const unsigned int gpio_18_19_pins[] = {43, 44};
static const unsigned int uart0_rts_cts_pins[] = {43, 44};
static const unsigned int gpio_20_21_pins[] = {45, 46};
static const unsigned int uart0_in_out_pins[] = {45, 46};
static const unsigned int gpio_22_23_pins[] = {47, 48};
static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
static const unsigned int gpio_24_25_pins[] = {49, 50};
static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
static const unsigned int gpio_26_27_pins[] = {51, 52};
static const unsigned int uart1_rts_cts_pins[] = {51, 52};
static const unsigned int gpio_28_29_pins[] = {53, 54};
static const unsigned int uart1_in_out_pins[] = {53, 54};
static const unsigned int gpio_30_31_pins[] = {55, 56};
static const unsigned int uart2_rts_cts_pins[] = {55, 56};
#define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al) \
{ \
.name = __stringify(group_name) "_grp", \
.pins = group_name ## _pins, \
.num_pins = ARRAY_SIZE(group_name ## _pins), \
.mux = { \
.base = ba, \
.offset = off, \
.shift = sh, \
.mask = ma, \
.alt = al, \
} \
}
/*
* List of Northstar2 pin groups
*/
static const struct ns2_pin_group ns2_pin_groups[] = {
NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
};
/*
* List of groups supported by functions
*/
static const char * const nand_grps[] = {"nand_grp"};
static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
"nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
"nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
"gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
"gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
"gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
"gpio_30_31_grp"};
static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
"pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
"pcie_a2_clk_wak_grp"};
static const char * const uart0_grps[] = {"uart0_modem_grp",
"uart0_rts_cts_grp", "uart0_in_out_grp"};
static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
"uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
"uart1_in_out_grp"};
static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
"pwm_2_grp", "pwm_3_grp"};
#define NS2_PIN_FUNCTION(func) \
{ \
.name = #func, \
.groups = func ## _grps, \
.num_groups = ARRAY_SIZE(func ## _grps), \
}
/*
* List of supported functions
*/
static const struct ns2_pin_function ns2_pin_functions[] = {
NS2_PIN_FUNCTION(nand),
NS2_PIN_FUNCTION(nor),
NS2_PIN_FUNCTION(gpio),
NS2_PIN_FUNCTION(pcie),
NS2_PIN_FUNCTION(uart0),
NS2_PIN_FUNCTION(uart1),
NS2_PIN_FUNCTION(uart2),
NS2_PIN_FUNCTION(pwm),
};
static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_groups;
}
static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
unsigned int selector)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->groups[selector].name;
}
static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
unsigned int selector, const unsigned int **pins,
unsigned int *num_pins)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*pins = pinctrl->groups[selector].pins;
*num_pins = pinctrl->groups[selector].num_pins;
return 0;
}
static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, " %s", dev_name(pctrl_dev->dev));
}
static const struct pinctrl_ops ns2_pinctrl_ops = {
.get_groups_count = ns2_get_groups_count,
.get_group_name = ns2_get_group_name,
.get_group_pins = ns2_get_group_pins,
.pin_dbg_show = ns2_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_functions;
}
static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
unsigned int selector)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->functions[selector].name;
}
static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*groups = pinctrl->functions[selector].groups;
*num_groups = pinctrl->functions[selector].num_groups;
return 0;
}
static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
const struct ns2_pin_function *func,
const struct ns2_pin_group *grp,
struct ns2_mux_log *mux_log)
{
const struct ns2_mux *mux = &grp->mux;
int i;
u32 val, mask;
unsigned long flags;
void __iomem *base_address;
for (i = 0; i < NS2_NUM_IOMUX; i++) {
if ((mux->shift != mux_log[i].mux.shift) ||
(mux->base != mux_log[i].mux.base) ||
(mux->offset != mux_log[i].mux.offset))
continue;
/* if this is a new configuration, just do it! */
if (!mux_log[i].is_configured)
break;
/*
* IOMUX has been configured previously and one is trying to
* configure it to a different function
*/
if (mux_log[i].mux.alt != mux->alt) {
dev_err(pinctrl->dev,
"double configuration error detected!\n");
dev_err(pinctrl->dev, "func:%s grp:%s\n",
func->name, grp->name);
return -EINVAL;
}
return 0;
}
if (i == NS2_NUM_IOMUX)
return -EINVAL;
mask = mux->mask;
mux_log[i].mux.alt = mux->alt;
mux_log[i].is_configured = true;
switch (mux->base) {
case NS2_PIN_MUX_BASE0:
base_address = pinctrl->base0;
break;
case NS2_PIN_MUX_BASE1:
base_address = pinctrl->base1;
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address + grp->mux.offset);
val &= ~(mask << grp->mux.shift);
val |= grp->mux.alt << grp->mux.shift;
writel(val, (base_address + grp->mux.offset));
spin_unlock_irqrestore(&pinctrl->lock, flags);
return 0;
}
static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
unsigned int func_select, unsigned int grp_select)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct ns2_pin_function *func;
const struct ns2_pin_group *grp;
if (grp_select >= pinctrl->num_groups ||
func_select >= pinctrl->num_functions)
return -EINVAL;
func = &pinctrl->functions[func_select];
grp = &pinctrl->groups[grp_select];
dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
func_select, func->name, grp_select, grp->name);
dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
grp->mux.offset, grp->mux.shift, grp->mux.alt);
return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
}
static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
u16 enable)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
u32 val;
void __iomem *base_address;
base_address = pinctrl->pinconf_base;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address + pin_data->pin_conf.offset);
val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
if (!enable)
val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
writel(val, (base_address + pin_data->pin_conf.offset));
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
return 0;
}
static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
int enable;
spin_lock_irqsave(&pinctrl->lock, flags);
enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
enable = (enable >> pin_data->pin_conf.input_en) &
NS2_PIN_INPUT_EN_MASK;
spin_unlock_irqrestore(&pinctrl->lock, flags);
if (!enable)
enable = NS2_PIN_INPUT_EN_MASK;
else
enable = 0;
dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
return enable;
}
static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
u32 slew)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
u32 val;
void __iomem *base_address;
base_address = pinctrl->pinconf_base;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address + pin_data->pin_conf.offset);
val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
if (slew)
val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
writel(val, (base_address + pin_data->pin_conf.offset));
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
return 0;
}
static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
u16 *slew)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
u32 val;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
*slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
return 0;
}
static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
bool pull_up, bool pull_down)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
u32 val;
void __iomem *base_address;
base_address = pinctrl->pinconf_base;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address + pin_data->pin_conf.offset);
val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
if (pull_up == true)
val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
if (pull_down == true)
val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
writel(val, (base_address + pin_data->pin_conf.offset));
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
pin, pull_up, pull_down);
return 0;
}
static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
unsigned int pin, bool *pull_up,
bool *pull_down)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
unsigned long flags;
u32 val;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
*pull_up = false;
*pull_down = false;
if (val == NS2_PIN_PULL_UP)
*pull_up = true;
if (val == NS2_PIN_PULL_DOWN)
*pull_down = true;
spin_unlock_irqrestore(&pinctrl->lock, flags);
}
static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
u32 strength)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
void __iomem *base_address;
/* make sure drive strength is supported */
if (strength < 2 || strength > 16 || (strength % 2))
return -ENOTSUPP;
base_address = pinctrl->pinconf_base;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(base_address + pin_data->pin_conf.offset);
val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
writel(val, (base_address + pin_data->pin_conf.offset));
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
pin, strength);
return 0;
}
static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
u16 *strength)
{
struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
*strength = (val >> pin_data->pin_conf.drive_shift) &
NS2_PIN_DRIVE_STRENGTH_MASK;
*strength = (*strength + 1) * 2;
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
pin, *strength);
return 0;
}
static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
enum pin_config_param param = pinconf_to_config_param(*config);
bool pull_up, pull_down;
u16 arg = 0;
int ret;
if (pin_data->pin_conf.base == -1)
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
if (!pull_up && !pull_down)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_UP:
ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
if (pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_DOWN:
ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
if (pull_down)
return 0;
else
return -EINVAL;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = ns2_pin_get_strength(pctldev, pin, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return 0;
case PIN_CONFIG_SLEW_RATE:
ret = ns2_pin_get_slew(pctldev, pin, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return 0;
case PIN_CONFIG_INPUT_ENABLE:
ret = ns2_pin_get_enable(pctldev, pin);
if (ret)
return 0;
else
return -EINVAL;
default:
return -ENOTSUPP;
}
}
static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
enum pin_config_param param;
unsigned int i;
u32 arg;
int ret = -ENOTSUPP;
if (pin_data->pin_conf.base == -1)
return -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = ns2_pin_set_pull(pctrldev, pin, false, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = ns2_pin_set_pull(pctrldev, pin, true, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = ns2_pin_set_pull(pctrldev, pin, false, true);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = ns2_pin_set_strength(pctrldev, pin, arg);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_SLEW_RATE:
ret = ns2_pin_set_slew(pctrldev, pin, arg);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_INPUT_ENABLE:
ret = ns2_pin_set_enable(pctrldev, pin, arg);
if (ret < 0)
goto out;
break;
default:
dev_err(pctrldev->dev, "invalid configuration\n");
return -ENOTSUPP;
}
}
out:
return ret;
}
static const struct pinmux_ops ns2_pinmux_ops = {
.get_functions_count = ns2_get_functions_count,
.get_function_name = ns2_get_function_name,
.get_function_groups = ns2_get_function_groups,
.set_mux = ns2_pinmux_enable,
};
static const struct pinconf_ops ns2_pinconf_ops = {
.is_generic = true,
.pin_config_get = ns2_pin_config_get,
.pin_config_set = ns2_pin_config_set,
};
static struct pinctrl_desc ns2_pinctrl_desc = {
.name = "ns2-pinmux",
.pctlops = &ns2_pinctrl_ops,
.pmxops = &ns2_pinmux_ops,
.confops = &ns2_pinconf_ops,
};
static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
{
struct ns2_mux_log *log;
unsigned int i;
pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
sizeof(struct ns2_mux_log),
GFP_KERNEL);
if (!pinctrl->mux_log)
return -ENOMEM;
for (i = 0; i < NS2_NUM_IOMUX; i++)
pinctrl->mux_log[i].is_configured = false;
/* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
log = &pinctrl->mux_log[0];
log->mux.base = NS2_PIN_MUX_BASE0;
log->mux.offset = 0;
log->mux.shift = 31;
log->mux.alt = 0;
/*
* Groups 1 through 14 use two bits each in the
* IOMUX_PAD_FUNCTION_1 register starting with
* bit position 30.
*/
for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
log = &pinctrl->mux_log[i];
log->mux.base = NS2_PIN_MUX_BASE0;
log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
log->mux.shift = 32 - (i * 2);
log->mux.alt = 0;
}
/*
* Groups 15 through 18 use one bit each in the
* AUX_SEL register.
*/
for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
log->mux.base = NS2_PIN_MUX_BASE1;
log->mux.offset = 0;
log->mux.shift = i;
log->mux.alt = 0;
}
return 0;
}
static int ns2_pinmux_probe(struct platform_device *pdev)
{
struct ns2_pinctrl *pinctrl;
struct resource *res;
int i, ret;
struct pinctrl_pin_desc *pins;
unsigned int num_pins = ARRAY_SIZE(ns2_pins);
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
return -ENOMEM;
pinctrl->dev = &pdev->dev;
platform_set_drvdata(pdev, pinctrl);
spin_lock_init(&pinctrl->lock);
pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pinctrl->base0))
return PTR_ERR(pinctrl->base0);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
return -EINVAL;
pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!pinctrl->base1) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return -ENOMEM;
}
pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(pinctrl->pinconf_base))
return PTR_ERR(pinctrl->pinconf_base);
ret = ns2_mux_log_init(pinctrl);
if (ret) {
dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
return ret;
}
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < num_pins; i++) {
pins[i].number = ns2_pins[i].pin;
pins[i].name = ns2_pins[i].name;
pins[i].drv_data = &ns2_pins[i];
}
pinctrl->groups = ns2_pin_groups;
pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
pinctrl->functions = ns2_pin_functions;
pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
ns2_pinctrl_desc.pins = pins;
ns2_pinctrl_desc.npins = num_pins;
pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
pinctrl);
if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
return PTR_ERR(pinctrl->pctl);
}
return 0;
}
static const struct of_device_id ns2_pinmux_of_match[] = {
{.compatible = "brcm,ns2-pinmux"},
{ }
};
static struct platform_driver ns2_pinmux_driver = {
.driver = {
.name = "ns2-pinmux",
.of_match_table = ns2_pinmux_of_match,
},
.probe = ns2_pinmux_probe,
};
static int __init ns2_pinmux_init(void)
{
return platform_driver_register(&ns2_pinmux_driver);
}
arch_initcall(ns2_pinmux_init);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
|
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2013-2017 Broadcom
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
/* BCM281XX Pin Control Registers Definitions */
/* Function Select bits are the same for all pin control registers */
#define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
#define BCM281XX_PIN_REG_F_SEL_SHIFT 8
/* Standard pin register */
#define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
#define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
#define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
#define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3
#define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
#define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4
#define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
#define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5
#define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
#define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6
#define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
#define BCM281XX_STD_PIN_REG_HYST_SHIFT 7
/* I2C pin register */
#define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
#define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2
#define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
#define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3
#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
/* HDMI pin register */
#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
#define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
#define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
/*
* bcm281xx_pin_type - types of pin register
*/
enum bcm281xx_pin_type {
BCM281XX_PIN_TYPE_UNKNOWN = 0,
BCM281XX_PIN_TYPE_STD,
BCM281XX_PIN_TYPE_I2C,
BCM281XX_PIN_TYPE_HDMI,
};
static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
/*
* bcm281xx_pin_function- define pin function
*/
struct bcm281xx_pin_function {
const char *name;
const char * const *groups;
const unsigned ngroups;
};
/*
* bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
* @reg_base - base of pinctrl registers
*/
struct bcm281xx_pinctrl_data {
void __iomem *reg_base;
/* List of all pins */
const struct pinctrl_pin_desc *pins;
const unsigned npins;
const struct bcm281xx_pin_function *functions;
const unsigned nfunctions;
struct regmap *regmap;
};
/*
* Pin number definition. The order here must be the same as defined in the
* PADCTRLREG block in the RDB.
*/
#define BCM281XX_PIN_ADCSYNC 0
#define BCM281XX_PIN_BAT_RM 1
#define BCM281XX_PIN_BSC1_SCL 2
#define BCM281XX_PIN_BSC1_SDA 3
#define BCM281XX_PIN_BSC2_SCL 4
#define BCM281XX_PIN_BSC2_SDA 5
#define BCM281XX_PIN_CLASSGPWR 6
#define BCM281XX_PIN_CLK_CX8 7
#define BCM281XX_PIN_CLKOUT_0 8
#define BCM281XX_PIN_CLKOUT_1 9
#define BCM281XX_PIN_CLKOUT_2 10
#define BCM281XX_PIN_CLKOUT_3 11
#define BCM281XX_PIN_CLKREQ_IN_0 12
#define BCM281XX_PIN_CLKREQ_IN_1 13
#define BCM281XX_PIN_CWS_SYS_REQ1 14
#define BCM281XX_PIN_CWS_SYS_REQ2 15
#define BCM281XX_PIN_CWS_SYS_REQ3 16
#define BCM281XX_PIN_DIGMIC1_CLK 17
#define BCM281XX_PIN_DIGMIC1_DQ 18
#define BCM281XX_PIN_DIGMIC2_CLK 19
#define BCM281XX_PIN_DIGMIC2_DQ 20
#define BCM281XX_PIN_GPEN13 21
#define BCM281XX_PIN_GPEN14 22
#define BCM281XX_PIN_GPEN15 23
#define BCM281XX_PIN_GPIO00 24
#define BCM281XX_PIN_GPIO01 25
#define BCM281XX_PIN_GPIO02 26
#define BCM281XX_PIN_GPIO03 27
#define BCM281XX_PIN_GPIO04 28
#define BCM281XX_PIN_GPIO05 29
#define BCM281XX_PIN_GPIO06 30
#define BCM281XX_PIN_GPIO07 31
#define BCM281XX_PIN_GPIO08 32
#define BCM281XX_PIN_GPIO09 33
#define BCM281XX_PIN_GPIO10 34
#define BCM281XX_PIN_GPIO11 35
#define BCM281XX_PIN_GPIO12 36
#define BCM281XX_PIN_GPIO13 37
#define BCM281XX_PIN_GPIO14 38
#define BCM281XX_PIN_GPS_PABLANK 39
#define BCM281XX_PIN_GPS_TMARK 40
#define BCM281XX_PIN_HDMI_SCL 41
#define BCM281XX_PIN_HDMI_SDA 42
#define BCM281XX_PIN_IC_DM 43
#define BCM281XX_PIN_IC_DP 44
#define BCM281XX_PIN_KP_COL_IP_0 45
#define BCM281XX_PIN_KP_COL_IP_1 46
#define BCM281XX_PIN_KP_COL_IP_2 47
#define BCM281XX_PIN_KP_COL_IP_3 48
#define BCM281XX_PIN_KP_ROW_OP_0 49
#define BCM281XX_PIN_KP_ROW_OP_1 50
#define BCM281XX_PIN_KP_ROW_OP_2 51
#define BCM281XX_PIN_KP_ROW_OP_3 52
#define BCM281XX_PIN_LCD_B_0 53
#define BCM281XX_PIN_LCD_B_1 54
#define BCM281XX_PIN_LCD_B_2 55
#define BCM281XX_PIN_LCD_B_3 56
#define BCM281XX_PIN_LCD_B_4 57
#define BCM281XX_PIN_LCD_B_5 58
#define BCM281XX_PIN_LCD_B_6 59
#define BCM281XX_PIN_LCD_B_7 60
#define BCM281XX_PIN_LCD_G_0 61
#define BCM281XX_PIN_LCD_G_1 62
#define BCM281XX_PIN_LCD_G_2 63
#define BCM281XX_PIN_LCD_G_3 64
#define BCM281XX_PIN_LCD_G_4 65
#define BCM281XX_PIN_LCD_G_5 66
#define BCM281XX_PIN_LCD_G_6 67
#define BCM281XX_PIN_LCD_G_7 68
#define BCM281XX_PIN_LCD_HSYNC 69
#define BCM281XX_PIN_LCD_OE 70
#define BCM281XX_PIN_LCD_PCLK 71
#define BCM281XX_PIN_LCD_R_0 72
#define BCM281XX_PIN_LCD_R_1 73
#define BCM281XX_PIN_LCD_R_2 74
#define BCM281XX_PIN_LCD_R_3 75
#define BCM281XX_PIN_LCD_R_4 76
#define BCM281XX_PIN_LCD_R_5 77
#define BCM281XX_PIN_LCD_R_6 78
#define BCM281XX_PIN_LCD_R_7 79
#define BCM281XX_PIN_LCD_VSYNC 80
#define BCM281XX_PIN_MDMGPIO0 81
#define BCM281XX_PIN_MDMGPIO1 82
#define BCM281XX_PIN_MDMGPIO2 83
#define BCM281XX_PIN_MDMGPIO3 84
#define BCM281XX_PIN_MDMGPIO4 85
#define BCM281XX_PIN_MDMGPIO5 86
#define BCM281XX_PIN_MDMGPIO6 87
#define BCM281XX_PIN_MDMGPIO7 88
#define BCM281XX_PIN_MDMGPIO8 89
#define BCM281XX_PIN_MPHI_DATA_0 90
#define BCM281XX_PIN_MPHI_DATA_1 91
#define BCM281XX_PIN_MPHI_DATA_2 92
#define BCM281XX_PIN_MPHI_DATA_3 93
#define BCM281XX_PIN_MPHI_DATA_4 94
#define BCM281XX_PIN_MPHI_DATA_5 95
#define BCM281XX_PIN_MPHI_DATA_6 96
#define BCM281XX_PIN_MPHI_DATA_7 97
#define BCM281XX_PIN_MPHI_DATA_8 98
#define BCM281XX_PIN_MPHI_DATA_9 99
#define BCM281XX_PIN_MPHI_DATA_10 100
#define BCM281XX_PIN_MPHI_DATA_11 101
#define BCM281XX_PIN_MPHI_DATA_12 102
#define BCM281XX_PIN_MPHI_DATA_13 103
#define BCM281XX_PIN_MPHI_DATA_14 104
#define BCM281XX_PIN_MPHI_DATA_15 105
#define BCM281XX_PIN_MPHI_HA0 106
#define BCM281XX_PIN_MPHI_HAT0 107
#define BCM281XX_PIN_MPHI_HAT1 108
#define BCM281XX_PIN_MPHI_HCE0_N 109
#define BCM281XX_PIN_MPHI_HCE1_N 110
#define BCM281XX_PIN_MPHI_HRD_N 111
#define BCM281XX_PIN_MPHI_HWR_N 112
#define BCM281XX_PIN_MPHI_RUN0 113
#define BCM281XX_PIN_MPHI_RUN1 114
#define BCM281XX_PIN_MTX_SCAN_CLK 115
#define BCM281XX_PIN_MTX_SCAN_DATA 116
#define BCM281XX_PIN_NAND_AD_0 117
#define BCM281XX_PIN_NAND_AD_1 118
#define BCM281XX_PIN_NAND_AD_2 119
#define BCM281XX_PIN_NAND_AD_3 120
#define BCM281XX_PIN_NAND_AD_4 121
#define BCM281XX_PIN_NAND_AD_5 122
#define BCM281XX_PIN_NAND_AD_6 123
#define BCM281XX_PIN_NAND_AD_7 124
#define BCM281XX_PIN_NAND_ALE 125
#define BCM281XX_PIN_NAND_CEN_0 126
#define BCM281XX_PIN_NAND_CEN_1 127
#define BCM281XX_PIN_NAND_CLE 128
#define BCM281XX_PIN_NAND_OEN 129
#define BCM281XX_PIN_NAND_RDY_0 130
#define BCM281XX_PIN_NAND_RDY_1 131
#define BCM281XX_PIN_NAND_WEN 132
#define BCM281XX_PIN_NAND_WP 133
#define BCM281XX_PIN_PC1 134
#define BCM281XX_PIN_PC2 135
#define BCM281XX_PIN_PMU_INT 136
#define BCM281XX_PIN_PMU_SCL 137
#define BCM281XX_PIN_PMU_SDA 138
#define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139
#define BCM281XX_PIN_RGMII_0_RX_CTL 140
#define BCM281XX_PIN_RGMII_0_RXC 141
#define BCM281XX_PIN_RGMII_0_RXD_0 142
#define BCM281XX_PIN_RGMII_0_RXD_1 143
#define BCM281XX_PIN_RGMII_0_RXD_2 144
#define BCM281XX_PIN_RGMII_0_RXD_3 145
#define BCM281XX_PIN_RGMII_0_TX_CTL 146
#define BCM281XX_PIN_RGMII_0_TXC 147
#define BCM281XX_PIN_RGMII_0_TXD_0 148
#define BCM281XX_PIN_RGMII_0_TXD_1 149
#define BCM281XX_PIN_RGMII_0_TXD_2 150
#define BCM281XX_PIN_RGMII_0_TXD_3 151
#define BCM281XX_PIN_RGMII_1_RX_CTL 152
#define BCM281XX_PIN_RGMII_1_RXC 153
#define BCM281XX_PIN_RGMII_1_RXD_0 154
#define BCM281XX_PIN_RGMII_1_RXD_1 155
#define BCM281XX_PIN_RGMII_1_RXD_2 156
#define BCM281XX_PIN_RGMII_1_RXD_3 157
#define BCM281XX_PIN_RGMII_1_TX_CTL 158
#define BCM281XX_PIN_RGMII_1_TXC 159
#define BCM281XX_PIN_RGMII_1_TXD_0 160
#define BCM281XX_PIN_RGMII_1_TXD_1 161
#define BCM281XX_PIN_RGMII_1_TXD_2 162
#define BCM281XX_PIN_RGMII_1_TXD_3 163
#define BCM281XX_PIN_RGMII_GPIO_0 164
#define BCM281XX_PIN_RGMII_GPIO_1 165
#define BCM281XX_PIN_RGMII_GPIO_2 166
#define BCM281XX_PIN_RGMII_GPIO_3 167
#define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168
#define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169
#define BCM281XX_PIN_RXDATA3G0 170
#define BCM281XX_PIN_RXDATA3G1 171
#define BCM281XX_PIN_RXDATA3G2 172
#define BCM281XX_PIN_SDIO1_CLK 173
#define BCM281XX_PIN_SDIO1_CMD 174
#define BCM281XX_PIN_SDIO1_DATA_0 175
#define BCM281XX_PIN_SDIO1_DATA_1 176
#define BCM281XX_PIN_SDIO1_DATA_2 177
#define BCM281XX_PIN_SDIO1_DATA_3 178
#define BCM281XX_PIN_SDIO4_CLK 179
#define BCM281XX_PIN_SDIO4_CMD 180
#define BCM281XX_PIN_SDIO4_DATA_0 181
#define BCM281XX_PIN_SDIO4_DATA_1 182
#define BCM281XX_PIN_SDIO4_DATA_2 183
#define BCM281XX_PIN_SDIO4_DATA_3 184
#define BCM281XX_PIN_SIM_CLK 185
#define BCM281XX_PIN_SIM_DATA 186
#define BCM281XX_PIN_SIM_DET 187
#define BCM281XX_PIN_SIM_RESETN 188
#define BCM281XX_PIN_SIM2_CLK 189
#define BCM281XX_PIN_SIM2_DATA 190
#define BCM281XX_PIN_SIM2_DET 191
#define BCM281XX_PIN_SIM2_RESETN 192
#define BCM281XX_PIN_SRI_C 193
#define BCM281XX_PIN_SRI_D 194
#define BCM281XX_PIN_SRI_E 195
#define BCM281XX_PIN_SSP_EXTCLK 196
#define BCM281XX_PIN_SSP0_CLK 197
#define BCM281XX_PIN_SSP0_FS 198
#define BCM281XX_PIN_SSP0_RXD 199
#define BCM281XX_PIN_SSP0_TXD 200
#define BCM281XX_PIN_SSP2_CLK 201
#define BCM281XX_PIN_SSP2_FS_0 202
#define BCM281XX_PIN_SSP2_FS_1 203
#define BCM281XX_PIN_SSP2_FS_2 204
#define BCM281XX_PIN_SSP2_FS_3 205
#define BCM281XX_PIN_SSP2_RXD_0 206
#define BCM281XX_PIN_SSP2_RXD_1 207
#define BCM281XX_PIN_SSP2_TXD_0 208
#define BCM281XX_PIN_SSP2_TXD_1 209
#define BCM281XX_PIN_SSP3_CLK 210
#define BCM281XX_PIN_SSP3_FS 211
#define BCM281XX_PIN_SSP3_RXD 212
#define BCM281XX_PIN_SSP3_TXD 213
#define BCM281XX_PIN_SSP4_CLK 214
#define BCM281XX_PIN_SSP4_FS 215
#define BCM281XX_PIN_SSP4_RXD 216
#define BCM281XX_PIN_SSP4_TXD 217
#define BCM281XX_PIN_SSP5_CLK 218
#define BCM281XX_PIN_SSP5_FS 219
#define BCM281XX_PIN_SSP5_RXD 220
#define BCM281XX_PIN_SSP5_TXD 221
#define BCM281XX_PIN_SSP6_CLK 222
#define BCM281XX_PIN_SSP6_FS 223
#define BCM281XX_PIN_SSP6_RXD 224
#define BCM281XX_PIN_SSP6_TXD 225
#define BCM281XX_PIN_STAT_1 226
#define BCM281XX_PIN_STAT_2 227
#define BCM281XX_PIN_SYSCLKEN 228
#define BCM281XX_PIN_TRACECLK 229
#define BCM281XX_PIN_TRACEDT00 230
#define BCM281XX_PIN_TRACEDT01 231
#define BCM281XX_PIN_TRACEDT02 232
#define BCM281XX_PIN_TRACEDT03 233
#define BCM281XX_PIN_TRACEDT04 234
#define BCM281XX_PIN_TRACEDT05 235
#define BCM281XX_PIN_TRACEDT06 236
#define BCM281XX_PIN_TRACEDT07 237
#define BCM281XX_PIN_TRACEDT08 238
#define BCM281XX_PIN_TRACEDT09 239
#define BCM281XX_PIN_TRACEDT10 240
#define BCM281XX_PIN_TRACEDT11 241
#define BCM281XX_PIN_TRACEDT12 242
#define BCM281XX_PIN_TRACEDT13 243
#define BCM281XX_PIN_TRACEDT14 244
#define BCM281XX_PIN_TRACEDT15 245
#define BCM281XX_PIN_TXDATA3G0 246
#define BCM281XX_PIN_TXPWRIND 247
#define BCM281XX_PIN_UARTB1_UCTS 248
#define BCM281XX_PIN_UARTB1_URTS 249
#define BCM281XX_PIN_UARTB1_URXD 250
#define BCM281XX_PIN_UARTB1_UTXD 251
#define BCM281XX_PIN_UARTB2_URXD 252
#define BCM281XX_PIN_UARTB2_UTXD 253
#define BCM281XX_PIN_UARTB3_UCTS 254
#define BCM281XX_PIN_UARTB3_URTS 255
#define BCM281XX_PIN_UARTB3_URXD 256
#define BCM281XX_PIN_UARTB3_UTXD 257
#define BCM281XX_PIN_UARTB4_UCTS 258
#define BCM281XX_PIN_UARTB4_URTS 259
#define BCM281XX_PIN_UARTB4_URXD 260
#define BCM281XX_PIN_UARTB4_UTXD 261
#define BCM281XX_PIN_VC_CAM1_SCL 262
#define BCM281XX_PIN_VC_CAM1_SDA 263
#define BCM281XX_PIN_VC_CAM2_SCL 264
#define BCM281XX_PIN_VC_CAM2_SDA 265
#define BCM281XX_PIN_VC_CAM3_SCL 266
#define BCM281XX_PIN_VC_CAM3_SDA 267
#define BCM281XX_PIN_DESC(a, b, c) \
{ .number = a, .name = b, .drv_data = &c##_pin }
/*
* Pin description definition. The order here must be the same as defined in
* the PADCTRLREG block in the RDB, since the pin number is used as an index
* into this array.
*/
static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
"rtxdata2g_txdata3g1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
};
static const char * const bcm281xx_alt_groups[] = {
"adcsync",
"bat_rm",
"bsc1_scl",
"bsc1_sda",
"bsc2_scl",
"bsc2_sda",
"classgpwr",
"clk_cx8",
"clkout_0",
"clkout_1",
"clkout_2",
"clkout_3",
"clkreq_in_0",
"clkreq_in_1",
"cws_sys_req1",
"cws_sys_req2",
"cws_sys_req3",
"digmic1_clk",
"digmic1_dq",
"digmic2_clk",
"digmic2_dq",
"gpen13",
"gpen14",
"gpen15",
"gpio00",
"gpio01",
"gpio02",
"gpio03",
"gpio04",
"gpio05",
"gpio06",
"gpio07",
"gpio08",
"gpio09",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gps_pablank",
"gps_tmark",
"hdmi_scl",
"hdmi_sda",
"ic_dm",
"ic_dp",
"kp_col_ip_0",
"kp_col_ip_1",
"kp_col_ip_2",
"kp_col_ip_3",
"kp_row_op_0",
"kp_row_op_1",
"kp_row_op_2",
"kp_row_op_3",
"lcd_b_0",
"lcd_b_1",
"lcd_b_2",
"lcd_b_3",
"lcd_b_4",
"lcd_b_5",
"lcd_b_6",
"lcd_b_7",
"lcd_g_0",
"lcd_g_1",
"lcd_g_2",
"lcd_g_3",
"lcd_g_4",
"lcd_g_5",
"lcd_g_6",
"lcd_g_7",
"lcd_hsync",
"lcd_oe",
"lcd_pclk",
"lcd_r_0",
"lcd_r_1",
"lcd_r_2",
"lcd_r_3",
"lcd_r_4",
"lcd_r_5",
"lcd_r_6",
"lcd_r_7",
"lcd_vsync",
"mdmgpio0",
"mdmgpio1",
"mdmgpio2",
"mdmgpio3",
"mdmgpio4",
"mdmgpio5",
"mdmgpio6",
"mdmgpio7",
"mdmgpio8",
"mphi_data_0",
"mphi_data_1",
"mphi_data_2",
"mphi_data_3",
"mphi_data_4",
"mphi_data_5",
"mphi_data_6",
"mphi_data_7",
"mphi_data_8",
"mphi_data_9",
"mphi_data_10",
"mphi_data_11",
"mphi_data_12",
"mphi_data_13",
"mphi_data_14",
"mphi_data_15",
"mphi_ha0",
"mphi_hat0",
"mphi_hat1",
"mphi_hce0_n",
"mphi_hce1_n",
"mphi_hrd_n",
"mphi_hwr_n",
"mphi_run0",
"mphi_run1",
"mtx_scan_clk",
"mtx_scan_data",
"nand_ad_0",
"nand_ad_1",
"nand_ad_2",
"nand_ad_3",
"nand_ad_4",
"nand_ad_5",
"nand_ad_6",
"nand_ad_7",
"nand_ale",
"nand_cen_0",
"nand_cen_1",
"nand_cle",
"nand_oen",
"nand_rdy_0",
"nand_rdy_1",
"nand_wen",
"nand_wp",
"pc1",
"pc2",
"pmu_int",
"pmu_scl",
"pmu_sda",
"rfst2g_mtsloten3g",
"rgmii_0_rx_ctl",
"rgmii_0_rxc",
"rgmii_0_rxd_0",
"rgmii_0_rxd_1",
"rgmii_0_rxd_2",
"rgmii_0_rxd_3",
"rgmii_0_tx_ctl",
"rgmii_0_txc",
"rgmii_0_txd_0",
"rgmii_0_txd_1",
"rgmii_0_txd_2",
"rgmii_0_txd_3",
"rgmii_1_rx_ctl",
"rgmii_1_rxc",
"rgmii_1_rxd_0",
"rgmii_1_rxd_1",
"rgmii_1_rxd_2",
"rgmii_1_rxd_3",
"rgmii_1_tx_ctl",
"rgmii_1_txc",
"rgmii_1_txd_0",
"rgmii_1_txd_1",
"rgmii_1_txd_2",
"rgmii_1_txd_3",
"rgmii_gpio_0",
"rgmii_gpio_1",
"rgmii_gpio_2",
"rgmii_gpio_3",
"rtxdata2g_txdata3g1",
"rtxen2g_txdata3g2",
"rxdata3g0",
"rxdata3g1",
"rxdata3g2",
"sdio1_clk",
"sdio1_cmd",
"sdio1_data_0",
"sdio1_data_1",
"sdio1_data_2",
"sdio1_data_3",
"sdio4_clk",
"sdio4_cmd",
"sdio4_data_0",
"sdio4_data_1",
"sdio4_data_2",
"sdio4_data_3",
"sim_clk",
"sim_data",
"sim_det",
"sim_resetn",
"sim2_clk",
"sim2_data",
"sim2_det",
"sim2_resetn",
"sri_c",
"sri_d",
"sri_e",
"ssp_extclk",
"ssp0_clk",
"ssp0_fs",
"ssp0_rxd",
"ssp0_txd",
"ssp2_clk",
"ssp2_fs_0",
"ssp2_fs_1",
"ssp2_fs_2",
"ssp2_fs_3",
"ssp2_rxd_0",
"ssp2_rxd_1",
"ssp2_txd_0",
"ssp2_txd_1",
"ssp3_clk",
"ssp3_fs",
"ssp3_rxd",
"ssp3_txd",
"ssp4_clk",
"ssp4_fs",
"ssp4_rxd",
"ssp4_txd",
"ssp5_clk",
"ssp5_fs",
"ssp5_rxd",
"ssp5_txd",
"ssp6_clk",
"ssp6_fs",
"ssp6_rxd",
"ssp6_txd",
"stat_1",
"stat_2",
"sysclken",
"traceclk",
"tracedt00",
"tracedt01",
"tracedt02",
"tracedt03",
"tracedt04",
"tracedt05",
"tracedt06",
"tracedt07",
"tracedt08",
"tracedt09",
"tracedt10",
"tracedt11",
"tracedt12",
"tracedt13",
"tracedt14",
"tracedt15",
"txdata3g0",
"txpwrind",
"uartb1_ucts",
"uartb1_urts",
"uartb1_urxd",
"uartb1_utxd",
"uartb2_urxd",
"uartb2_utxd",
"uartb3_ucts",
"uartb3_urts",
"uartb3_urxd",
"uartb3_utxd",
"uartb4_ucts",
"uartb4_urts",
"uartb4_urxd",
"uartb4_utxd",
"vc_cam1_scl",
"vc_cam1_sda",
"vc_cam2_scl",
"vc_cam2_sda",
"vc_cam3_scl",
"vc_cam3_sda",
};
/* Every pin can implement all ALT1-ALT4 functions */
#define BCM281XX_PIN_FUNCTION(fcn_name) \
{ \
.name = #fcn_name, \
.groups = bcm281xx_alt_groups, \
.ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
}
static const struct bcm281xx_pin_function bcm281xx_functions[] = {
BCM281XX_PIN_FUNCTION(alt1),
BCM281XX_PIN_FUNCTION(alt2),
BCM281XX_PIN_FUNCTION(alt3),
BCM281XX_PIN_FUNCTION(alt4),
};
static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
.pins = bcm281xx_pinctrl_pins,
.npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
.functions = bcm281xx_functions,
.nfunctions = ARRAY_SIZE(bcm281xx_functions),
};
static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
unsigned pin)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
if (pin >= pdata->npins)
return BCM281XX_PIN_TYPE_UNKNOWN;
return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
}
#define BCM281XX_PIN_SHIFT(type, param) \
(BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
#define BCM281XX_PIN_MASK(type, param) \
(BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
/*
* This helper function is used to build up the value and mask used to write to
* a pin register, but does not actually write to the register.
*/
static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
u32 param_val, u32 param_shift,
u32 param_mask)
{
*reg_val &= ~param_mask;
*reg_val |= (param_val << param_shift) & param_mask;
*reg_mask |= param_mask;
}
static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = BCM281XX_PIN_VC_CAM3_SDA,
};
static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->npins;
}
static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pins[group].name;
}
static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*pins = &pdata->pins[group].number;
*num_pins = 1;
return 0;
}
static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
.get_groups_count = bcm281xx_pinctrl_get_groups_count,
.get_group_name = bcm281xx_pinctrl_get_group_name,
.get_group_pins = bcm281xx_pinctrl_get_group_pins,
.pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->nfunctions;
}
static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->functions[function].name;
}
static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*groups = pdata->functions[function].groups;
*num_groups = pdata->functions[function].ngroups;
return 0;
}
static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct bcm281xx_pin_function *f = &pdata->functions[function];
u32 offset = 4 * pdata->pins[group].number;
int rc = 0;
dev_dbg(pctldev->dev,
"%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
__func__, f->name, function, pdata->pins[group].name,
pdata->pins[group].number, offset);
rc = regmap_update_bits(pdata->regmap, offset,
BCM281XX_PIN_REG_F_SEL_MASK,
function << BCM281XX_PIN_REG_F_SEL_SHIFT);
if (rc)
dev_err(pctldev->dev,
"Error updating register for pin %s (%d).\n",
pdata->pins[group].name, pdata->pins[group].number);
return rc;
}
static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
.get_functions_count = bcm281xx_pinctrl_get_fcns_count,
.get_function_name = bcm281xx_pinctrl_get_fcn_name,
.get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
.set_mux = bcm281xx_pinmux_set,
};
static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *config)
{
return -ENOTSUPP;
}
/* Goes through the configs and update register val/mask */
static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs,
u32 *val,
u32 *mask)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
int i;
enum pin_config_param param;
u32 arg;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
arg = (arg >= 1 ? 1 : 0);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(STD, HYST),
BCM281XX_PIN_MASK(STD, HYST));
break;
/*
* The pin bias can only be one of pull-up, pull-down, or
* disable. The user does not need to specify a value for the
* property, and the default value from pinconf-generic is
* ignored.
*/
case PIN_CONFIG_BIAS_DISABLE:
bcm281xx_pin_update(val, mask, 0,
BCM281XX_PIN_SHIFT(STD, PULL_UP),
BCM281XX_PIN_MASK(STD, PULL_UP));
bcm281xx_pin_update(val, mask, 0,
BCM281XX_PIN_SHIFT(STD, PULL_DN),
BCM281XX_PIN_MASK(STD, PULL_DN));
break;
case PIN_CONFIG_BIAS_PULL_UP:
bcm281xx_pin_update(val, mask, 1,
BCM281XX_PIN_SHIFT(STD, PULL_UP),
BCM281XX_PIN_MASK(STD, PULL_UP));
bcm281xx_pin_update(val, mask, 0,
BCM281XX_PIN_SHIFT(STD, PULL_DN),
BCM281XX_PIN_MASK(STD, PULL_DN));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bcm281xx_pin_update(val, mask, 0,
BCM281XX_PIN_SHIFT(STD, PULL_UP),
BCM281XX_PIN_MASK(STD, PULL_UP));
bcm281xx_pin_update(val, mask, 1,
BCM281XX_PIN_SHIFT(STD, PULL_DN),
BCM281XX_PIN_MASK(STD, PULL_DN));
break;
case PIN_CONFIG_SLEW_RATE:
arg = (arg >= 1 ? 1 : 0);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(STD, SLEW),
BCM281XX_PIN_MASK(STD, SLEW));
break;
case PIN_CONFIG_INPUT_ENABLE:
/* inversed since register is for input _disable_ */
arg = (arg >= 1 ? 0 : 1);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
BCM281XX_PIN_MASK(STD, INPUT_DIS));
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* Valid range is 2-16 mA, even numbers only */
if ((arg < 2) || (arg > 16) || (arg % 2)) {
dev_err(pctldev->dev,
"Invalid Drive Strength value (%d) for "
"pin %s (%d). Valid values are "
"(2..16) mA, even numbers only.\n",
arg, pdata->pins[pin].name, pin);
return -EINVAL;
}
bcm281xx_pin_update(val, mask, (arg/2)-1,
BCM281XX_PIN_SHIFT(STD, DRV_STR),
BCM281XX_PIN_MASK(STD, DRV_STR));
break;
default:
dev_err(pctldev->dev,
"Unrecognized pin config %d for pin %s (%d).\n",
param, pdata->pins[pin].name, pin);
return -EINVAL;
} /* switch config */
} /* for each config */
return 0;
}
/*
* The pull-up strength for an I2C pin is represented by bits 4-6 in the
* register with the following mapping:
* 0b000: No pull-up
* 0b001: 1200 Ohm
* 0b010: 1800 Ohm
* 0b011: 720 Ohm
* 0b100: 2700 Ohm
* 0b101: 831 Ohm
* 0b110: 1080 Ohm
* 0b111: 568 Ohm
* This array maps pull-up strength in Ohms to register values (1+index).
*/
static const u16 bcm281xx_pullup_map[] = {
1200, 1800, 720, 2700, 831, 1080, 568
};
/* Goes through the configs and update register val/mask */
static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs,
u32 *val,
u32 *mask)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
int i, j;
enum pin_config_param param;
u32 arg;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
if (bcm281xx_pullup_map[j] == arg)
break;
if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
dev_err(pctldev->dev,
"Invalid pull-up value (%d) for pin %s "
"(%d). Valid values are 568, 720, 831, "
"1080, 1200, 1800, 2700 Ohms.\n",
arg, pdata->pins[pin].name, pin);
return -EINVAL;
}
bcm281xx_pin_update(val, mask, j+1,
BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
break;
case PIN_CONFIG_BIAS_DISABLE:
bcm281xx_pin_update(val, mask, 0,
BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
break;
case PIN_CONFIG_SLEW_RATE:
arg = (arg >= 1 ? 1 : 0);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(I2C, SLEW),
BCM281XX_PIN_MASK(I2C, SLEW));
break;
case PIN_CONFIG_INPUT_ENABLE:
/* inversed since register is for input _disable_ */
arg = (arg >= 1 ? 0 : 1);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
BCM281XX_PIN_MASK(I2C, INPUT_DIS));
break;
default:
dev_err(pctldev->dev,
"Unrecognized pin config %d for pin %s (%d).\n",
param, pdata->pins[pin].name, pin);
return -EINVAL;
} /* switch config */
} /* for each config */
return 0;
}
/* Goes through the configs and update register val/mask */
static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs,
u32 *val,
u32 *mask)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
int i;
enum pin_config_param param;
u32 arg;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_SLEW_RATE:
arg = (arg >= 1 ? 1 : 0);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(HDMI, MODE),
BCM281XX_PIN_MASK(HDMI, MODE));
break;
case PIN_CONFIG_INPUT_ENABLE:
/* inversed since register is for input _disable_ */
arg = (arg >= 1 ? 0 : 1);
bcm281xx_pin_update(val, mask, arg,
BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
break;
default:
dev_err(pctldev->dev,
"Unrecognized pin config %d for pin %s (%d).\n",
param, pdata->pins[pin].name, pin);
return -EINVAL;
} /* switch config */
} /* for each config */
return 0;
}
static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
enum bcm281xx_pin_type pin_type;
u32 offset = 4 * pin;
u32 cfg_val, cfg_mask;
int rc;
cfg_val = 0;
cfg_mask = 0;
pin_type = pin_type_get(pctldev, pin);
/* Different pins have different configuration options */
switch (pin_type) {
case BCM281XX_PIN_TYPE_STD:
rc = bcm281xx_std_pin_update(pctldev, pin, configs,
num_configs, &cfg_val, &cfg_mask);
break;
case BCM281XX_PIN_TYPE_I2C:
rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
num_configs, &cfg_val, &cfg_mask);
break;
case BCM281XX_PIN_TYPE_HDMI:
rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
num_configs, &cfg_val, &cfg_mask);
break;
default:
dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
pdata->pins[pin].name, pin);
return -EINVAL;
} /* switch pin type */
if (rc)
return rc;
dev_dbg(pctldev->dev,
"%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
__func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
if (rc) {
dev_err(pctldev->dev,
"Error updating register for pin %s (%d).\n",
pdata->pins[pin].name, pin);
return rc;
}
return 0;
}
static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
.pin_config_get = bcm281xx_pinctrl_pin_config_get,
.pin_config_set = bcm281xx_pinctrl_pin_config_set,
};
static struct pinctrl_desc bcm281xx_pinctrl_desc = {
/* name, pins, npins members initialized in probe function */
.pctlops = &bcm281xx_pinctrl_ops,
.pmxops = &bcm281xx_pinctrl_pinmux_ops,
.confops = &bcm281xx_pinctrl_pinconf_ops,
.owner = THIS_MODULE,
};
static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
{
struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
struct pinctrl_dev *pctl;
/* So far We can assume there is only 1 bank of registers */
pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->reg_base)) {
dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
return PTR_ERR(pdata->reg_base);
}
/* Initialize the dynamic part of pinctrl_desc */
pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
&bcm281xx_pinctrl_regmap_config);
if (IS_ERR(pdata->regmap)) {
dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
return -ENODEV;
}
bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
if (IS_ERR(pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(pctl);
}
platform_set_drvdata(pdev, pdata);
return 0;
}
static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
{ .compatible = "brcm,bcm11351-pinctrl", },
{ },
};
static struct platform_driver bcm281xx_pinctrl_driver = {
.driver = {
.name = "bcm281xx-pinctrl",
.of_match_table = bcm281xx_pinctrl_of_match,
},
};
builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
|
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014-2017 Broadcom
/*
* Broadcom Cygnus IOMUX driver
*
* This file contains the Cygnus IOMUX driver that supports group based PINMUX
* configuration. Although PINMUX configuration is mainly group based, the
* Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO
* function, and therefore be controlled by the Cygnus ASIU GPIO controller
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#define CYGNUS_NUM_IOMUX_REGS 8
#define CYGNUS_NUM_MUX_PER_REG 8
#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
CYGNUS_NUM_MUX_PER_REG)
/*
* Cygnus IOMUX register description
*
* @offset: register offset for mux configuration of a group
* @shift: bit shift for mux configuration of a group
* @alt: alternate function to set to
*/
struct cygnus_mux {
unsigned int offset;
unsigned int shift;
unsigned int alt;
};
/*
* Keep track of Cygnus IOMUX configuration and prevent double configuration
*
* @cygnus_mux: Cygnus IOMUX register description
* @is_configured: flag to indicate whether a mux setting has already been
* configured
*/
struct cygnus_mux_log {
struct cygnus_mux mux;
bool is_configured;
};
/*
* Group based IOMUX configuration
*
* @name: name of the group
* @pins: array of pins used by this group
* @num_pins: total number of pins used by this group
* @mux: Cygnus group based IOMUX configuration
*/
struct cygnus_pin_group {
const char *name;
const unsigned *pins;
unsigned num_pins;
struct cygnus_mux mux;
};
/*
* Cygnus mux function and supported pin groups
*
* @name: name of the function
* @groups: array of groups that can be supported by this function
* @num_groups: total number of groups that can be supported by this function
*/
struct cygnus_pin_function {
const char *name;
const char * const *groups;
unsigned num_groups;
};
/*
* Cygnus IOMUX pinctrl core
*
* @pctl: pointer to pinctrl_dev
* @dev: pointer to device
* @base0: first I/O register base of the Cygnus IOMUX controller
* @base1: second I/O register base
* @groups: pointer to array of groups
* @num_groups: total number of groups
* @functions: pointer to array of functions
* @num_functions: total number of functions
* @mux_log: pointer to the array of mux logs
* @lock: lock to protect register access
*/
struct cygnus_pinctrl {
struct pinctrl_dev *pctl;
struct device *dev;
void __iomem *base0;
void __iomem *base1;
const struct cygnus_pin_group *groups;
unsigned num_groups;
const struct cygnus_pin_function *functions;
unsigned num_functions;
struct cygnus_mux_log *mux_log;
spinlock_t lock;
};
/*
* Certain pins can be individually muxed to GPIO function
*
* @is_supported: flag to indicate GPIO mux is supported for this pin
* @offset: register offset for GPIO mux override of a pin
* @shift: bit shift for GPIO mux override of a pin
*/
struct cygnus_gpio_mux {
int is_supported;
unsigned int offset;
unsigned int shift;
};
/*
* Description of a pin in Cygnus
*
* @pin: pin number
* @name: pin name
* @gpio_mux: GPIO override related information
*/
struct cygnus_pin {
unsigned pin;
char *name;
struct cygnus_gpio_mux gpio_mux;
};
#define CYGNUS_PIN_DESC(p, n, i, o, s) \
{ \
.pin = p, \
.name = n, \
.gpio_mux = { \
.is_supported = i, \
.offset = o, \
.shift = s, \
}, \
}
/*
* List of pins in Cygnus
*/
static struct cygnus_pin cygnus_pins[] = {
CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
};
/*
* List of groups of pins
*/
static const unsigned bsc1_pins[] = { 8, 9 };
static const unsigned pcie_clkreq_pins[] = { 8, 9 };
static const unsigned i2s2_0_pins[] = { 12 };
static const unsigned i2s2_1_pins[] = { 13 };
static const unsigned i2s2_2_pins[] = { 14 };
static const unsigned i2s2_3_pins[] = { 15 };
static const unsigned i2s2_4_pins[] = { 16 };
static const unsigned pwm4_pins[] = { 17 };
static const unsigned pwm5_pins[] = { 18 };
static const unsigned key0_pins[] = { 20 };
static const unsigned key1_pins[] = { 21 };
static const unsigned key2_pins[] = { 22 };
static const unsigned key3_pins[] = { 23 };
static const unsigned key4_pins[] = { 24 };
static const unsigned key5_pins[] = { 25 };
static const unsigned key6_pins[] = { 26 };
static const unsigned audio_dte0_pins[] = { 26 };
static const unsigned key7_pins[] = { 27 };
static const unsigned audio_dte1_pins[] = { 27 };
static const unsigned key8_pins[] = { 28 };
static const unsigned key9_pins[] = { 29 };
static const unsigned key10_pins[] = { 30 };
static const unsigned key11_pins[] = { 31 };
static const unsigned key12_pins[] = { 32 };
static const unsigned key13_pins[] = { 33 };
static const unsigned key14_pins[] = { 34 };
static const unsigned audio_dte2_pins[] = { 34 };
static const unsigned key15_pins[] = { 35 };
static const unsigned audio_dte3_pins[] = { 35 };
static const unsigned pwm0_pins[] = { 38 };
static const unsigned pwm1_pins[] = { 39 };
static const unsigned pwm2_pins[] = { 40 };
static const unsigned pwm3_pins[] = { 41 };
static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };
static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };
static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };
static const unsigned spdif_pins[] = { 47 };
static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };
static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };
static const unsigned spi0_pins[] = { 54, 55, 56, 57 };
static const unsigned spi1_pins[] = { 58, 59, 60, 61 };
static const unsigned spi2_pins[] = { 62, 63, 64, 65 };
static const unsigned spi3_pins[] = { 66, 67, 68, 69 };
static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };
static const unsigned d1w_pins[] = { 10, 11 };
static const unsigned uart4_pins[] = { 10, 11 };
static const unsigned sw_led2_0_pins[] = { 10, 11 };
static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
148, 149, 150, 151, 152, 153, 154, 155 };
static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
148, 149, 150, 151, 152, 153, 154, 155 };
static const unsigned spi5_pins[] = { 141, 142, 143, 144 };
static const unsigned uart0_pins[] = { 70, 71, 72, 73 };
static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };
static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };
static const unsigned uart2_pins[] = { 75, 76, 77, 78 };
static const unsigned uart1_pins[] = { 74, 79, 80, 81 };
static const unsigned uart3_pins[] = { 82, 83 };
static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };
static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
118, 119, 120, 121, 122, 123, 124, 125 };
static const unsigned sdio0_cd_pins[] = { 103 };
static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };
static const unsigned sdio1_data_0_pins[] = { 86, 87 };
static const unsigned can0_pins[] = { 86, 87 };
static const unsigned spi4_0_pins[] = { 86, 87 };
static const unsigned sdio1_data_1_pins[] = { 88, 89 };
static const unsigned can1_pins[] = { 88, 89 };
static const unsigned spi4_1_pins[] = { 88, 89 };
static const unsigned sdio1_cd_pins[] = { 93 };
static const unsigned sdio1_led_pins[] = { 84, 85 };
static const unsigned sw_led2_1_pins[] = { 84, 85 };
static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };
static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };
static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };
static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };
static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
168 };
static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
168 };
static const unsigned qspi_1_pins[] = { 108, 109 };
static const unsigned smart_card0_fcb_pins[] = { 45 };
static const unsigned i2s0_1_pins[] = { 45 };
static const unsigned smart_card1_fcb_pins[] = { 51 };
static const unsigned i2s1_1_pins[] = { 51 };
static const unsigned gpio0_3p3_pins[] = { 176 };
static const unsigned usb0_oc_pins[] = { 176 };
static const unsigned gpio1_3p3_pins[] = { 177 };
static const unsigned usb1_oc_pins[] = { 177 };
static const unsigned gpio2_3p3_pins[] = { 178 };
static const unsigned usb2_oc_pins[] = { 178 };
#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \
{ \
.name = __stringify(group_name) "_grp", \
.pins = group_name ## _pins, \
.num_pins = ARRAY_SIZE(group_name ## _pins), \
.mux = { \
.offset = off, \
.shift = sh, \
.alt = al, \
} \
}
/*
* List of Cygnus pin groups
*/
static const struct cygnus_pin_group cygnus_pin_groups[] = {
CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),
CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),
CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),
CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),
CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),
CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),
CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),
CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),
CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),
CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),
CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),
CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),
CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),
CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),
CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),
CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),
CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),
CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),
CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),
CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),
CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),
CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),
CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),
CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),
CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),
CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),
CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),
CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),
CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),
CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),
CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),
CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),
CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),
CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),
CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),
CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),
CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),
CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),
CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),
CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),
CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),
CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),
CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),
CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),
CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),
CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),
CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),
CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),
CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),
CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),
CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),
CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),
CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),
CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),
CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),
CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),
CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),
CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),
CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),
CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),
CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),
CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),
CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),
CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),
CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),
CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),
CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),
CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),
CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),
CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),
CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),
CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),
CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),
CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),
CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),
CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),
CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),
CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),
CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),
CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),
CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),
CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),
CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),
CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),
CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),
};
/*
* List of groups supported by functions
*/
static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };
static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };
static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",
"i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };
static const char * const spdif_grps[] = { "spdif_grp" };
static const char * const pwm0_grps[] = { "pwm0_grp" };
static const char * const pwm1_grps[] = { "pwm1_grp" };
static const char * const pwm2_grps[] = { "pwm2_grp" };
static const char * const pwm3_grps[] = { "pwm3_grp" };
static const char * const pwm4_grps[] = { "pwm4_grp" };
static const char * const pwm5_grps[] = { "pwm5_grp" };
static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",
"key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",
"key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",
"key14_grp", "key15_grp" };
static const char * const audio_dte_grps[] = { "audio_dte0_grp",
"audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };
static const char * const smart_card0_grps[] = { "smart_card0_grp",
"smart_card0_fcb_grp" };
static const char * const smart_card1_grps[] = { "smart_card1_grp",
"smart_card1_fcb_grp" };
static const char * const spi0_grps[] = { "spi0_grp" };
static const char * const spi1_grps[] = { "spi1_grp" };
static const char * const spi2_grps[] = { "spi2_grp" };
static const char * const spi3_grps[] = { "spi3_grp" };
static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };
static const char * const spi5_grps[] = { "spi5_grp" };
static const char * const sw_led0_grps[] = { "sw_led0_0_grp",
"sw_led0_1_grp" };
static const char * const sw_led1_grps[] = { "sw_led1_grp" };
static const char * const sw_led2_grps[] = { "sw_led2_0_grp",
"sw_led2_1_grp" };
static const char * const d1w_grps[] = { "d1w_grp" };
static const char * const lcd_grps[] = { "lcd_grp" };
static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };
static const char * const uart0_grps[] = { "uart0_grp" };
static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };
static const char * const uart2_grps[] = { "uart2_grp" };
static const char * const uart3_grps[] = { "uart3_grp" };
static const char * const uart4_grps[] = { "uart4_grp" };
static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };
static const char * const nand_grps[] = { "nand_grp" };
static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",
"sdio0_mmc_grp" };
static const char * const sdio1_grps[] = { "sdio1_data_0_grp",
"sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };
static const char * const can0_grps[] = { "can0_grp" };
static const char * const can1_grps[] = { "can1_grp" };
static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",
"cam_1_grp" };
static const char * const bsc1_grps[] = { "bsc1_grp" };
static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };
static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };
static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };
static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };
#define CYGNUS_PIN_FUNCTION(func) \
{ \
.name = #func, \
.groups = func ## _grps, \
.num_groups = ARRAY_SIZE(func ## _grps), \
}
/*
* List of supported functions in Cygnus
*/
static const struct cygnus_pin_function cygnus_pin_functions[] = {
CYGNUS_PIN_FUNCTION(i2s0),
CYGNUS_PIN_FUNCTION(i2s1),
CYGNUS_PIN_FUNCTION(i2s2),
CYGNUS_PIN_FUNCTION(spdif),
CYGNUS_PIN_FUNCTION(pwm0),
CYGNUS_PIN_FUNCTION(pwm1),
CYGNUS_PIN_FUNCTION(pwm2),
CYGNUS_PIN_FUNCTION(pwm3),
CYGNUS_PIN_FUNCTION(pwm4),
CYGNUS_PIN_FUNCTION(pwm5),
CYGNUS_PIN_FUNCTION(key),
CYGNUS_PIN_FUNCTION(audio_dte),
CYGNUS_PIN_FUNCTION(smart_card0),
CYGNUS_PIN_FUNCTION(smart_card1),
CYGNUS_PIN_FUNCTION(spi0),
CYGNUS_PIN_FUNCTION(spi1),
CYGNUS_PIN_FUNCTION(spi2),
CYGNUS_PIN_FUNCTION(spi3),
CYGNUS_PIN_FUNCTION(spi4),
CYGNUS_PIN_FUNCTION(spi5),
CYGNUS_PIN_FUNCTION(sw_led0),
CYGNUS_PIN_FUNCTION(sw_led1),
CYGNUS_PIN_FUNCTION(sw_led2),
CYGNUS_PIN_FUNCTION(d1w),
CYGNUS_PIN_FUNCTION(lcd),
CYGNUS_PIN_FUNCTION(sram),
CYGNUS_PIN_FUNCTION(uart0),
CYGNUS_PIN_FUNCTION(uart1),
CYGNUS_PIN_FUNCTION(uart2),
CYGNUS_PIN_FUNCTION(uart3),
CYGNUS_PIN_FUNCTION(uart4),
CYGNUS_PIN_FUNCTION(qspi),
CYGNUS_PIN_FUNCTION(nand),
CYGNUS_PIN_FUNCTION(sdio0),
CYGNUS_PIN_FUNCTION(sdio1),
CYGNUS_PIN_FUNCTION(can0),
CYGNUS_PIN_FUNCTION(can1),
CYGNUS_PIN_FUNCTION(cam),
CYGNUS_PIN_FUNCTION(bsc1),
CYGNUS_PIN_FUNCTION(pcie_clkreq),
CYGNUS_PIN_FUNCTION(usb0_oc),
CYGNUS_PIN_FUNCTION(usb1_oc),
CYGNUS_PIN_FUNCTION(usb2_oc),
};
static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_groups;
}
static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,
unsigned selector)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->groups[selector].name;
}
static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,
unsigned selector, const unsigned **pins,
unsigned *num_pins)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*pins = pinctrl->groups[selector].pins;
*num_pins = pinctrl->groups[selector].num_pins;
return 0;
}
static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
struct seq_file *s, unsigned offset)
{
seq_printf(s, " %s", dev_name(pctrl_dev->dev));
}
static const struct pinctrl_ops cygnus_pinctrl_ops = {
.get_groups_count = cygnus_get_groups_count,
.get_group_name = cygnus_get_group_name,
.get_group_pins = cygnus_get_group_pins,
.pin_dbg_show = cygnus_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
};
static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->num_functions;
}
static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,
unsigned selector)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pinctrl->functions[selector].name;
}
static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*groups = pinctrl->functions[selector].groups;
*num_groups = pinctrl->functions[selector].num_groups;
return 0;
}
static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,
const struct cygnus_pin_function *func,
const struct cygnus_pin_group *grp,
struct cygnus_mux_log *mux_log)
{
const struct cygnus_mux *mux = &grp->mux;
int i;
u32 val, mask = 0x7;
unsigned long flags;
for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {
if (mux->offset != mux_log[i].mux.offset ||
mux->shift != mux_log[i].mux.shift)
continue;
/* match found if we reach here */
/* if this is a new configuration, just do it! */
if (!mux_log[i].is_configured)
break;
/*
* IOMUX has been configured previously and one is trying to
* configure it to a different function
*/
if (mux_log[i].mux.alt != mux->alt) {
dev_err(pinctrl->dev,
"double configuration error detected!\n");
dev_err(pinctrl->dev, "func:%s grp:%s\n",
func->name, grp->name);
return -EINVAL;
} else {
/*
* One tries to configure it to the same function.
* Just quit and don't bother
*/
return 0;
}
}
mux_log[i].mux.alt = mux->alt;
mux_log[i].is_configured = true;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->base0 + grp->mux.offset);
val &= ~(mask << grp->mux.shift);
val |= grp->mux.alt << grp->mux.shift;
writel(val, pinctrl->base0 + grp->mux.offset);
spin_unlock_irqrestore(&pinctrl->lock, flags);
return 0;
}
static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
unsigned func_select, unsigned grp_select)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct cygnus_pin_function *func =
&pinctrl->functions[func_select];
const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];
dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
func_select, func->name, grp_select, grp->name);
dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
grp->mux.offset, grp->mux.shift, grp->mux.alt);
return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
}
static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
/* not all pins support GPIO pinmux override */
if (!mux->is_supported)
return -ENOTSUPP;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->base1 + mux->offset);
val |= 0x3 << mux->shift;
writel(val, pinctrl->base1 + mux->offset);
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_dbg(pctrl_dev->dev,
"gpio request enable pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
return 0;
}
static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
u32 val;
unsigned long flags;
if (!mux->is_supported)
return;
spin_lock_irqsave(&pinctrl->lock, flags);
val = readl(pinctrl->base1 + mux->offset);
val &= ~(0x3 << mux->shift);
writel(val, pinctrl->base1 + mux->offset);
spin_unlock_irqrestore(&pinctrl->lock, flags);
dev_err(pctrl_dev->dev,
"gpio disable free pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
}
static const struct pinmux_ops cygnus_pinmux_ops = {
.get_functions_count = cygnus_get_functions_count,
.get_function_name = cygnus_get_function_name,
.get_function_groups = cygnus_get_function_groups,
.set_mux = cygnus_pinmux_set_mux,
.gpio_request_enable = cygnus_gpio_request_enable,
.gpio_disable_free = cygnus_gpio_disable_free,
};
static struct pinctrl_desc cygnus_pinctrl_desc = {
.name = "cygnus-pinmux",
.pctlops = &cygnus_pinctrl_ops,
.pmxops = &cygnus_pinmux_ops,
};
static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
{
struct cygnus_mux_log *log;
unsigned int i, j;
pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
sizeof(struct cygnus_mux_log),
GFP_KERNEL);
if (!pinctrl->mux_log)
return -ENOMEM;
for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
+ j];
log->mux.offset = i * 4;
log->mux.shift = j * 4;
log->mux.alt = 0;
log->is_configured = false;
}
}
return 0;
}
static int cygnus_pinmux_probe(struct platform_device *pdev)
{
struct cygnus_pinctrl *pinctrl;
int i, ret;
struct pinctrl_pin_desc *pins;
unsigned num_pins = ARRAY_SIZE(cygnus_pins);
pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
if (!pinctrl)
return -ENOMEM;
pinctrl->dev = &pdev->dev;
platform_set_drvdata(pdev, pinctrl);
spin_lock_init(&pinctrl->lock);
pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pinctrl->base0)) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return PTR_ERR(pinctrl->base0);
}
pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(pinctrl->base1)) {
dev_err(&pdev->dev, "unable to map I/O space\n");
return PTR_ERR(pinctrl->base1);
}
ret = cygnus_mux_log_init(pinctrl);
if (ret) {
dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
return ret;
}
pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < num_pins; i++) {
pins[i].number = cygnus_pins[i].pin;
pins[i].name = cygnus_pins[i].name;
pins[i].drv_data = &cygnus_pins[i].gpio_mux;
}
pinctrl->groups = cygnus_pin_groups;
pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);
pinctrl->functions = cygnus_pin_functions;
pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
cygnus_pinctrl_desc.pins = pins;
cygnus_pinctrl_desc.npins = num_pins;
pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
pinctrl);
if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
return PTR_ERR(pinctrl->pctl);
}
return 0;
}
static const struct of_device_id cygnus_pinmux_of_match[] = {
{ .compatible = "brcm,cygnus-pinmux" },
{ }
};
static struct platform_driver cygnus_pinmux_driver = {
.driver = {
.name = "cygnus-pinmux",
.of_match_table = cygnus_pinmux_of_match,
.suppress_bind_attrs = true,
},
.probe = cygnus_pinmux_probe,
};
static int __init cygnus_pinmux_init(void)
{
return platform_driver_register(&cygnus_pinmux_driver);
}
arch_initcall(cygnus_pinmux_init);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2017 Broadcom
*/
/*
* This file contains the Broadcom Iproc GPIO driver that supports 3
* GPIO controllers on Iproc including the ASIU GPIO controller, the
* chipCommonG GPIO controller, and the always-on GPIO controller. Basic
* PINCONF such as bias pull up/down, and drive strength are also supported
* in this driver.
*
* It provides the functionality where pins from the GPIO can be
* individually muxed to GPIO function, if individual pad
* configuration is supported, through the interaction with respective
* SoCs IOMUX controller.
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include "../pinctrl-utils.h"
#define IPROC_GPIO_DATA_IN_OFFSET 0x00
#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
#define IPROC_GPIO_OUT_EN_OFFSET 0x08
#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
#define IPROC_GPIO_INT_DE_OFFSET 0x10
#define IPROC_GPIO_INT_EDGE_OFFSET 0x14
#define IPROC_GPIO_INT_MSK_OFFSET 0x18
#define IPROC_GPIO_INT_STAT_OFFSET 0x1c
#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
#define IPROC_GPIO_INT_CLR_OFFSET 0x24
#define IPROC_GPIO_PAD_RES_OFFSET 0x34
#define IPROC_GPIO_RES_EN_OFFSET 0x38
/* drive strength control for ASIU GPIO */
#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
/* pinconf for CCM GPIO */
#define IPROC_GPIO_PULL_DN_OFFSET 0x10
#define IPROC_GPIO_PULL_UP_OFFSET 0x14
/* pinconf for CRMU(aon) GPIO and CCM GPIO*/
#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
#define GPIO_BANK_SIZE 0x200
#define NGPIOS_PER_BANK 32
#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
#define GPIO_DRV_STRENGTH_BITS 3
#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
enum iproc_pinconf_param {
IPROC_PINCONF_DRIVE_STRENGTH = 0,
IPROC_PINCONF_BIAS_DISABLE,
IPROC_PINCONF_BIAS_PULL_UP,
IPROC_PINCONF_BIAS_PULL_DOWN,
IPROC_PINCON_MAX,
};
enum iproc_pinconf_ctrl_type {
IOCTRL_TYPE_AON = 1,
IOCTRL_TYPE_CDRU,
IOCTRL_TYPE_INVALID,
};
/*
* Iproc GPIO core
*
* @dev: pointer to device
* @base: I/O register base for Iproc GPIO controller
* @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
* has the PINCONF support implemented outside of the GPIO block
* @lock: lock to protect access to I/O registers
* @gc: GPIO chip
* @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
* @pinmux_is_supported: flag to indicate this GPIO controller contains pins
* that can be individually muxed to GPIO
* @pinconf_disable: contains a list of PINCONF parameters that need to be
* disabled
* @nr_pinconf_disable: total number of PINCONF parameters that need to be
* disabled
* @pctl: pointer to pinctrl_dev
* @pctldesc: pinctrl descriptor
*/
struct iproc_gpio {
struct device *dev;
void __iomem *base;
void __iomem *io_ctrl;
enum iproc_pinconf_ctrl_type io_ctrl_type;
raw_spinlock_t lock;
struct gpio_chip gc;
unsigned num_banks;
bool pinmux_is_supported;
enum pin_config_param *pinconf_disable;
unsigned int nr_pinconf_disable;
struct pinctrl_dev *pctl;
struct pinctrl_desc pctldesc;
};
/*
* Mapping from PINCONF pins to GPIO pins is 1-to-1
*/
static inline unsigned iproc_pin_to_gpio(unsigned pin)
{
return pin;
}
/**
* iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* Iproc GPIO register
*
* @chip: Iproc GPIO device
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
*/
static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
unsigned gpio, bool set)
{
unsigned int offset = IPROC_GPIO_REG(gpio, reg);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
u32 val;
val = readl(chip->base + offset);
if (set)
val |= BIT(shift);
else
val &= ~BIT(shift);
writel(val, chip->base + offset);
}
static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
unsigned gpio)
{
unsigned int offset = IPROC_GPIO_REG(gpio, reg);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
return !!(readl(chip->base + offset) & BIT(shift));
}
static void iproc_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct iproc_gpio *chip = gpiochip_get_data(gc);
struct irq_chip *irq_chip = irq_desc_get_chip(desc);
int i, bit;
chained_irq_enter(irq_chip, desc);
/* go through the entire GPIO banks and handle all interrupts */
for (i = 0; i < chip->num_banks; i++) {
unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
IPROC_GPIO_INT_MSTAT_OFFSET);
for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
unsigned pin = NGPIOS_PER_BANK * i + bit;
/*
* Clear the interrupt before invoking the
* handler, so we do not leave any window
*/
writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
IPROC_GPIO_INT_CLR_OFFSET);
generic_handle_domain_irq(gc->irq.domain, pin);
}
}
chained_irq_exit(irq_chip, desc);
}
static void iproc_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = d->hwirq;
unsigned int offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_INT_CLR_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
u32 val = BIT(shift);
writel(val, chip->base + offset);
}
/**
* iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
*
* @d: IRQ chip data
* @unmask: mask/unmask GPIO interrupt
*/
static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = irqd_to_hwirq(d);
iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
}
static void iproc_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_gpio_irq_set_mask(d, false);
raw_spin_unlock_irqrestore(&chip->lock, flags);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void iproc_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_gpio_irq_set_mask(d, true);
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = d->hwirq;
bool level_triggered = false;
bool dual_edge = false;
bool rising_or_high = false;
unsigned long flags;
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
rising_or_high = true;
break;
case IRQ_TYPE_EDGE_FALLING:
break;
case IRQ_TYPE_EDGE_BOTH:
dual_edge = true;
break;
case IRQ_TYPE_LEVEL_HIGH:
level_triggered = true;
rising_or_high = true;
break;
case IRQ_TYPE_LEVEL_LOW:
level_triggered = true;
break;
default:
dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
type);
return -EINVAL;
}
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
level_triggered);
iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
rising_or_high);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev,
"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
gpio, level_triggered, dual_edge, rising_or_high);
return 0;
}
static void iproc_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct iproc_gpio *chip = gpiochip_get_data(gc);
seq_printf(p, dev_name(chip->dev));
}
static const struct irq_chip iproc_gpio_irq_chip = {
.irq_ack = iproc_gpio_irq_ack,
.irq_mask = iproc_gpio_irq_mask,
.irq_unmask = iproc_gpio_irq_unmask,
.irq_set_type = iproc_gpio_irq_set_type,
.irq_enable = iproc_gpio_irq_unmask,
.irq_disable = iproc_gpio_irq_mask,
.irq_print_chip = iproc_gpio_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/*
* Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
*/
static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = gc->base + offset;
/* not all Iproc GPIO pins can be muxed individually */
if (!chip->pinmux_is_supported)
return 0;
return pinctrl_gpio_request(gpio);
}
static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = gc->base + offset;
if (!chip->pinmux_is_supported)
return;
pinctrl_gpio_free(gpio);
}
static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
return 0;
}
static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
int val)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
return 0;
}
static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
if (readl(chip->base + offset) & BIT(shift))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned int offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_DATA_IN_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
return !!(readl(chip->base + offset) & BIT(shift));
}
/*
* Mapping of the iProc PINCONF parameters to the generic pin configuration
* parameters
*/
static const enum pin_config_param iproc_pinconf_disable_map[] = {
[IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
[IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
[IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
[IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
};
static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
enum pin_config_param param)
{
unsigned int i;
if (!chip->nr_pinconf_disable)
return false;
for (i = 0; i < chip->nr_pinconf_disable; i++)
if (chip->pinconf_disable[i] == param)
return true;
return false;
}
static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
unsigned long disable_mask)
{
unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
unsigned int bit, nbits = 0;
/* figure out total number of PINCONF parameters to disable */
for_each_set_bit(bit, &disable_mask, map_size)
nbits++;
if (!nbits)
return 0;
/*
* Allocate an array to store PINCONF parameters that need to be
* disabled
*/
chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
sizeof(*chip->pinconf_disable),
GFP_KERNEL);
if (!chip->pinconf_disable)
return -ENOMEM;
chip->nr_pinconf_disable = nbits;
/* now store these parameters */
nbits = 0;
for_each_set_bit(bit, &disable_mask, map_size)
chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
return 0;
}
static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
{
return 1;
}
/*
* Only one group: "gpio_grp", since this local pinctrl device only performs
* GPIO specific PINCONF configurations
*/
static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return "gpio_grp";
}
static const struct pinctrl_ops iproc_pctrl_ops = {
.get_groups_count = iproc_get_groups_count,
.get_group_name = iproc_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
bool disable, bool pull_up)
{
void __iomem *base;
unsigned long flags;
unsigned int shift;
u32 val_1, val_2;
raw_spin_lock_irqsave(&chip->lock, flags);
if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
base = chip->io_ctrl;
shift = IPROC_GPIO_SHIFT(gpio);
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
if (disable) {
/* no pull-up or pull-down */
val_1 &= ~BIT(shift);
val_2 &= ~BIT(shift);
} else if (pull_up) {
val_1 |= BIT(shift);
val_2 &= ~BIT(shift);
} else {
val_1 &= ~BIT(shift);
val_2 |= BIT(shift);
}
writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
} else {
if (disable) {
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
false);
} else {
iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
pull_up);
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
true);
}
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
return 0;
}
static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
bool *disable, bool *pull_up)
{
void __iomem *base;
unsigned long flags;
unsigned int shift;
u32 val_1, val_2;
raw_spin_lock_irqsave(&chip->lock, flags);
if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
base = chip->io_ctrl;
shift = IPROC_GPIO_SHIFT(gpio);
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
*pull_up = val_1 ? true : false;
*disable = (val_1 | val_2) ? false : true;
} else {
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
((type) == IOCTRL_TYPE_CDRU) ? \
((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
unsigned strength)
{
void __iomem *base;
unsigned int i, offset, shift;
u32 val;
unsigned long flags;
/* make sure drive strength is supported */
if (strength < 2 || strength > 16 || (strength % 2))
return -ENOTSUPP;
if (chip->io_ctrl) {
base = chip->io_ctrl;
} else {
base = chip->base;
}
shift = IPROC_GPIO_SHIFT(gpio);
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
raw_spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
val = readl(base + offset);
val &= ~BIT(shift);
val |= ((strength >> i) & 0x1) << shift;
writel(val, base + offset);
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
u16 *strength)
{
void __iomem *base;
unsigned int i, offset, shift;
u32 val;
unsigned long flags;
if (chip->io_ctrl) {
base = chip->io_ctrl;
} else {
base = chip->base;
}
shift = IPROC_GPIO_SHIFT(gpio);
raw_spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
val = readl(base + offset) & BIT(shift);
val >>= shift;
*strength += (val << i);
}
/* convert to mA */
*strength = (*strength + 1) * 2;
raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned gpio = iproc_pin_to_gpio(pin);
u16 arg;
bool disable, pull_up;
int ret;
if (iproc_pinconf_param_is_disabled(chip, param))
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (disable)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_UP:
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (!disable && pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_DOWN:
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
if (!disable && !pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = iproc_gpio_get_strength(chip, gpio, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return 0;
default:
return -ENOTSUPP;
}
return -ENOTSUPP;
}
static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 arg;
unsigned i, gpio = iproc_pin_to_gpio(pin);
int ret = -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
if (iproc_pinconf_param_is_disabled(chip, param))
return -ENOTSUPP;
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = iproc_gpio_set_pull(chip, gpio, true, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = iproc_gpio_set_pull(chip, gpio, false, true);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = iproc_gpio_set_pull(chip, gpio, false, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = iproc_gpio_set_strength(chip, gpio, arg);
if (ret < 0)
goto out;
break;
default:
dev_err(chip->dev, "invalid configuration\n");
return -ENOTSUPP;
}
} /* for each config */
out:
return ret;
}
static const struct pinconf_ops iproc_pconf_ops = {
.is_generic = true,
.pin_config_get = iproc_pin_config_get,
.pin_config_set = iproc_pin_config_set,
};
/*
* Iproc GPIO controller supports some PINCONF related configurations such as
* pull up, pull down, and drive strength, when the pin is configured to GPIO
*
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
* local GPIO pins
*/
static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
{
struct pinctrl_desc *pctldesc = &chip->pctldesc;
struct pinctrl_pin_desc *pins;
struct gpio_chip *gc = &chip->gc;
int i;
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < gc->ngpio; i++) {
pins[i].number = i;
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
"gpio-%d", i);
if (!pins[i].name)
return -ENOMEM;
}
pctldesc->name = dev_name(chip->dev);
pctldesc->pctlops = &iproc_pctrl_ops;
pctldesc->pins = pins;
pctldesc->npins = gc->ngpio;
pctldesc->confops = &iproc_pconf_ops;
chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
if (IS_ERR(chip->pctl)) {
dev_err(chip->dev, "unable to register pinctrl device\n");
return PTR_ERR(chip->pctl);
}
return 0;
}
static const struct of_device_id iproc_gpio_of_match[] = {
{ .compatible = "brcm,iproc-gpio" },
{ .compatible = "brcm,cygnus-ccm-gpio" },
{ .compatible = "brcm,cygnus-asiu-gpio" },
{ .compatible = "brcm,cygnus-crmu-gpio" },
{ .compatible = "brcm,iproc-nsp-gpio" },
{ .compatible = "brcm,iproc-stingray-gpio" },
{ /* sentinel */ }
};
static int iproc_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct iproc_gpio *chip;
struct gpio_chip *gc;
u32 ngpios, pinconf_disable_mask = 0;
int irq, ret;
bool no_pinconf = false;
enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
/* NSP does not support drive strength config */
if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
/* Stingray does not support pinconf in this controller */
else if (of_device_is_compatible(dev->of_node,
"brcm,iproc-stingray-gpio"))
no_pinconf = true;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = dev;
platform_set_drvdata(pdev, chip);
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->base);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (res) {
chip->io_ctrl = devm_ioremap_resource(dev, res);
if (IS_ERR(chip->io_ctrl))
return PTR_ERR(chip->io_ctrl);
if (of_device_is_compatible(dev->of_node,
"brcm,cygnus-ccm-gpio"))
io_ctrl_type = IOCTRL_TYPE_CDRU;
else
io_ctrl_type = IOCTRL_TYPE_AON;
}
chip->io_ctrl_type = io_ctrl_type;
if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
dev_err(&pdev->dev, "missing ngpios DT property\n");
return -ENODEV;
}
raw_spin_lock_init(&chip->lock);
gc = &chip->gc;
gc->base = -1;
gc->ngpio = ngpios;
chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
gc->label = dev_name(dev);
gc->parent = dev;
gc->request = iproc_gpio_request;
gc->free = iproc_gpio_free;
gc->direction_input = iproc_gpio_direction_input;
gc->direction_output = iproc_gpio_direction_output;
gc->get_direction = iproc_gpio_get_direction;
gc->set = iproc_gpio_set;
gc->get = iproc_gpio_get;
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
"gpio-ranges");
/* optional GPIO interrupt support */
irq = platform_get_irq_optional(pdev, 0);
if (irq > 0) {
struct gpio_irq_chip *girq;
girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &iproc_gpio_irq_chip);
girq->parent_handler = iproc_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
ret = gpiochip_add_data(gc, chip);
if (ret < 0)
return dev_err_probe(dev, ret, "unable to add GPIO chip\n");
if (!no_pinconf) {
ret = iproc_gpio_register_pinconf(chip);
if (ret) {
dev_err(dev, "unable to register pinconf\n");
goto err_rm_gpiochip;
}
if (pinconf_disable_mask) {
ret = iproc_pinconf_disable_map_create(chip,
pinconf_disable_mask);
if (ret) {
dev_err(dev,
"unable to create pinconf disable map\n");
goto err_rm_gpiochip;
}
}
}
return 0;
err_rm_gpiochip:
gpiochip_remove(gc);
return ret;
}
static struct platform_driver iproc_gpio_driver = {
.driver = {
.name = "iproc-gpio",
.of_match_table = iproc_gpio_of_match,
},
.probe = iproc_gpio_probe,
};
static int __init iproc_gpio_init(void)
{
return platform_driver_register(&iproc_gpio_driver);
}
arch_initcall_sync(iproc_gpio_init);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Rafał Miłecki <[email protected]>
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "../core.h"
#include "../pinmux.h"
#define FLAG_BCM4708 BIT(1)
#define FLAG_BCM4709 BIT(2)
#define FLAG_BCM53012 BIT(3)
struct ns_pinctrl {
struct device *dev;
unsigned int chipset_flag;
struct pinctrl_dev *pctldev;
void __iomem *base;
struct pinctrl_desc pctldesc;
};
/*
* Pins
*/
static const struct pinctrl_pin_desc ns_pinctrl_pins[] = {
{ 0, "spi_clk", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 1, "spi_ss", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 2, "spi_mosi", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 3, "spi_miso", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 4, "i2c_scl", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 5, "i2c_sda", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 6, "mdc", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
{ 7, "mdio", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
{ 8, "pwm0", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 9, "pwm1", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 10, "pwm2", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 11, "pwm3", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 12, "uart1_rx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 13, "uart1_tx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 14, "uart1_cts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 15, "uart1_rts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
{ 16, "uart2_rx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
{ 17, "uart2_tx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
/* TODO { ??, "xtal_out", (void *)(FLAG_BCM4709) }, */
{ 22, "sdio_pwr", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
{ 23, "sdio_en_1p8v", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
};
/*
* Groups
*/
struct ns_pinctrl_group {
const char *name;
unsigned int *pins;
const unsigned int num_pins;
unsigned int chipsets;
};
static unsigned int spi_pins[] = { 0, 1, 2, 3 };
static unsigned int i2c_pins[] = { 4, 5 };
static unsigned int mdio_pins[] = { 6, 7 };
static unsigned int pwm0_pins[] = { 8 };
static unsigned int pwm1_pins[] = { 9 };
static unsigned int pwm2_pins[] = { 10 };
static unsigned int pwm3_pins[] = { 11 };
static unsigned int uart1_pins[] = { 12, 13, 14, 15 };
static unsigned int uart2_pins[] = { 16, 17 };
static unsigned int sdio_pwr_pins[] = { 22 };
static unsigned int sdio_1p8v_pins[] = { 23 };
#define NS_GROUP(_name, _pins, _chipsets) \
{ \
.name = _name, \
.pins = _pins, \
.num_pins = ARRAY_SIZE(_pins), \
.chipsets = _chipsets, \
}
static const struct ns_pinctrl_group ns_pinctrl_groups[] = {
NS_GROUP("spi_grp", spi_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("i2c_grp", i2c_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("mdio_grp", mdio_pins, FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("pwm0_grp", pwm0_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("pwm1_grp", pwm1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("pwm2_grp", pwm2_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("pwm3_grp", pwm3_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("uart1_grp", uart1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("uart2_grp", uart2_pins, FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("sdio_pwr_grp", sdio_pwr_pins, FLAG_BCM4709 | FLAG_BCM53012),
NS_GROUP("sdio_1p8v_grp", sdio_1p8v_pins, FLAG_BCM4709 | FLAG_BCM53012),
};
/*
* Functions
*/
struct ns_pinctrl_function {
const char *name;
const char * const *groups;
const unsigned int num_groups;
unsigned int chipsets;
};
static const char * const spi_groups[] = { "spi_grp" };
static const char * const i2c_groups[] = { "i2c_grp" };
static const char * const mdio_groups[] = { "mdio_grp" };
static const char * const pwm_groups[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp" };
static const char * const uart1_groups[] = { "uart1_grp" };
static const char * const uart2_groups[] = { "uart2_grp" };
static const char * const sdio_groups[] = { "sdio_pwr_grp", "sdio_1p8v_grp" };
#define NS_FUNCTION(_name, _groups, _chipsets) \
{ \
.name = _name, \
.groups = _groups, \
.num_groups = ARRAY_SIZE(_groups), \
.chipsets = _chipsets, \
}
static const struct ns_pinctrl_function ns_pinctrl_functions[] = {
NS_FUNCTION("spi", spi_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("i2c", i2c_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("mdio", mdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("pwm", pwm_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("uart1", uart1_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("uart2", uart2_groups, FLAG_BCM4709 | FLAG_BCM53012),
NS_FUNCTION("sdio", sdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
};
/*
* Groups code
*/
static const struct pinctrl_ops ns_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinconf_generic_dt_free_map,
};
/*
* Functions code
*/
static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
unsigned int func_select,
unsigned int group_selector)
{
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
struct group_desc *group;
u32 unset = 0;
u32 tmp;
int i;
group = pinctrl_generic_get_group(pctrl_dev, group_selector);
if (!group)
return -EINVAL;
for (i = 0; i < group->num_pins; i++)
unset |= BIT(group->pins[i]);
tmp = readl(ns_pinctrl->base);
tmp &= ~unset;
writel(tmp, ns_pinctrl->base);
return 0;
}
static const struct pinmux_ops ns_pinctrl_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = ns_pinctrl_set_mux,
};
/*
* Controller code
*/
static struct pinctrl_desc ns_pinctrl_desc = {
.name = "pinctrl-ns",
.pctlops = &ns_pinctrl_ops,
.pmxops = &ns_pinctrl_pmxops,
};
static const struct of_device_id ns_pinctrl_of_match_table[] = {
{ .compatible = "brcm,bcm4708-pinmux", .data = (void *)FLAG_BCM4708, },
{ .compatible = "brcm,bcm4709-pinmux", .data = (void *)FLAG_BCM4709, },
{ .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, },
{ }
};
static int ns_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *of_id;
struct ns_pinctrl *ns_pinctrl;
struct pinctrl_desc *pctldesc;
struct pinctrl_pin_desc *pin;
struct resource *res;
int i;
ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
if (!ns_pinctrl)
return -ENOMEM;
pctldesc = &ns_pinctrl->pctldesc;
platform_set_drvdata(pdev, ns_pinctrl);
/* Set basic properties */
ns_pinctrl->dev = dev;
of_id = of_match_device(ns_pinctrl_of_match_table, dev);
if (!of_id)
return -EINVAL;
ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
ns_pinctrl->base = devm_ioremap_resource(dev, res);
if (IS_ERR(ns_pinctrl->base))
return PTR_ERR(ns_pinctrl->base);
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
/* Set pinctrl properties */
pctldesc->pins = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_pins),
sizeof(struct pinctrl_pin_desc),
GFP_KERNEL);
if (!pctldesc->pins)
return -ENOMEM;
for (i = 0, pin = (struct pinctrl_pin_desc *)&pctldesc->pins[0];
i < ARRAY_SIZE(ns_pinctrl_pins); i++) {
const struct pinctrl_pin_desc *src = &ns_pinctrl_pins[i];
unsigned int chipsets = (uintptr_t)src->drv_data;
if (chipsets & ns_pinctrl->chipset_flag) {
memcpy(pin++, src, sizeof(*src));
pctldesc->npins++;
}
}
/* Register */
ns_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, ns_pinctrl);
if (IS_ERR(ns_pinctrl->pctldev)) {
dev_err(dev, "Failed to register pinctrl\n");
return PTR_ERR(ns_pinctrl->pctldev);
}
for (i = 0; i < ARRAY_SIZE(ns_pinctrl_groups); i++) {
const struct ns_pinctrl_group *group = &ns_pinctrl_groups[i];
if (!(group->chipsets & ns_pinctrl->chipset_flag))
continue;
pinctrl_generic_add_group(ns_pinctrl->pctldev, group->name,
group->pins, group->num_pins, NULL);
}
for (i = 0; i < ARRAY_SIZE(ns_pinctrl_functions); i++) {
const struct ns_pinctrl_function *function = &ns_pinctrl_functions[i];
if (!(function->chipsets & ns_pinctrl->chipset_flag))
continue;
pinmux_generic_add_function(ns_pinctrl->pctldev, function->name,
function->groups,
function->num_groups, NULL);
}
return 0;
}
static struct platform_driver ns_pinctrl_driver = {
.probe = ns_pinctrl_probe,
.driver = {
.name = "ns-pinmux",
.of_match_table = ns_pinctrl_of_match_table,
},
};
module_platform_driver(ns_pinctrl_driver);
MODULE_AUTHOR("Rafał Miłecki");
MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-ns.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM63268 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM63268_NUM_GPIOS 52
#define BCM63268_NUM_LEDS 24
#define BCM63268_LED_REG 0x10
#define BCM63268_MODE_REG 0x18
#define BCM63268_CTRL_REG 0x1c
#define BCM63268_BASEMODE_REG 0x38
#define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */
#define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */
#define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */
#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */
#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */
#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */
#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */
enum bcm63268_pinctrl_reg {
BCM63268_LEDCTRL,
BCM63268_MODE,
BCM63268_CTRL,
BCM63268_BASEMODE,
};
struct bcm63268_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
enum bcm63268_pinctrl_reg reg;
uint32_t mask;
};
#define BCM63268_PIN(a, b, basemode) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(basemode) \
}
static const struct pinctrl_pin_desc bcm63268_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
BCM63268_PIN(24, "gpio24",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_PIN(25, "gpio25",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_PIN(26, "gpio26",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
BCM63268_PIN(27, "gpio27",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
PINCTRL_PIN(48, "gpio48"),
PINCTRL_PIN(49, "gpio49"),
PINCTRL_PIN(50, "gpio50"),
PINCTRL_PIN(51, "gpio51"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
static unsigned gpio50_pins[] = { 50 };
static unsigned gpio51_pins[] = { 51 };
static unsigned nand_grp_pins[] = {
2, 3, 4, 5, 6, 7, 24,
25, 26, 27, 28, 29, 30, 31,
};
static unsigned dectpd_grp_pins[] = { 8, 9 };
static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
static struct pingroup bcm63268_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
BCM_PIN_GROUP(gpio50),
BCM_PIN_GROUP(gpio51),
/* multi pin groups */
BCM_PIN_GROUP(nand_grp),
BCM_PIN_GROUP(dectpd_grp),
BCM_PIN_GROUP(vdsl_phy0_grp),
BCM_PIN_GROUP(vdsl_phy1_grp),
BCM_PIN_GROUP(vdsl_phy2_grp),
BCM_PIN_GROUP(vdsl_phy3_grp),
};
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
static const char * const serial_led_clk_groups[] = {
"gpio0",
};
static const char * const serial_led_data_groups[] = {
"gpio1",
};
static const char * const hsspi_cs4_groups[] = {
"gpio16",
};
static const char * const hsspi_cs5_groups[] = {
"gpio17",
};
static const char * const hsspi_cs6_groups[] = {
"gpio8",
};
static const char * const hsspi_cs7_groups[] = {
"gpio9",
};
static const char * const uart1_scts_groups[] = {
"gpio10",
"gpio24",
};
static const char * const uart1_srts_groups[] = {
"gpio11",
"gpio25",
};
static const char * const uart1_sdin_groups[] = {
"gpio12",
"gpio26",
};
static const char * const uart1_sdout_groups[] = {
"gpio13",
"gpio27",
};
static const char * const ntr_pulse_in_groups[] = {
"gpio14",
"gpio28",
};
static const char * const dsl_ntr_pulse_out_groups[] = {
"gpio15",
"gpio29",
};
static const char * const adsl_spi_miso_groups[] = {
"gpio18",
};
static const char * const adsl_spi_mosi_groups[] = {
"gpio19",
};
static const char * const vreg_clk_groups[] = {
"gpio22",
};
static const char * const pcie_clkreq_b_groups[] = {
"gpio23",
};
static const char * const switch_led_clk_groups[] = {
"gpio30",
};
static const char * const switch_led_data_groups[] = {
"gpio31",
};
static const char * const wifi_groups[] = {
"gpio32",
"gpio33",
"gpio34",
"gpio35",
"gpio36",
"gpio37",
"gpio38",
"gpio39",
"gpio40",
"gpio41",
"gpio42",
"gpio43",
"gpio44",
"gpio45",
"gpio46",
"gpio47",
"gpio48",
"gpio49",
"gpio50",
"gpio51",
};
static const char * const nand_groups[] = {
"nand_grp",
};
static const char * const dectpd_groups[] = {
"dectpd_grp",
};
static const char * const vdsl_phy_override_0_groups[] = {
"vdsl_phy_override_0_grp",
};
static const char * const vdsl_phy_override_1_groups[] = {
"vdsl_phy_override_1_grp",
};
static const char * const vdsl_phy_override_2_groups[] = {
"vdsl_phy_override_2_grp",
};
static const char * const vdsl_phy_override_3_groups[] = {
"vdsl_phy_override_3_grp",
};
#define BCM63268_LED_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_LEDCTRL, \
}
#define BCM63268_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_MODE, \
}
#define BCM63268_CTRL_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_CTRL, \
}
#define BCM63268_BASEMODE_FUN(n, val) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_BASEMODE, \
.mask = val, \
}
static const struct bcm63268_function bcm63268_funcs[] = {
BCM63268_LED_FUN(led),
BCM63268_MODE_FUN(serial_led_clk),
BCM63268_MODE_FUN(serial_led_data),
BCM63268_MODE_FUN(hsspi_cs6),
BCM63268_MODE_FUN(hsspi_cs7),
BCM63268_MODE_FUN(uart1_scts),
BCM63268_MODE_FUN(uart1_srts),
BCM63268_MODE_FUN(uart1_sdin),
BCM63268_MODE_FUN(uart1_sdout),
BCM63268_MODE_FUN(ntr_pulse_in),
BCM63268_MODE_FUN(dsl_ntr_pulse_out),
BCM63268_MODE_FUN(hsspi_cs4),
BCM63268_MODE_FUN(hsspi_cs5),
BCM63268_MODE_FUN(adsl_spi_miso),
BCM63268_MODE_FUN(adsl_spi_mosi),
BCM63268_MODE_FUN(vreg_clk),
BCM63268_MODE_FUN(pcie_clkreq_b),
BCM63268_MODE_FUN(switch_led_clk),
BCM63268_MODE_FUN(switch_led_data),
BCM63268_CTRL_FUN(wifi),
BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
BCM63268_BASEMODE_VDSL_PHY_1),
BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
BCM63268_BASEMODE_VDSL_PHY_3),
};
static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm63268_groups);
}
static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm63268_groups[group].name;
}
static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *npins)
{
*pins = bcm63268_groups[group].pins;
*npins = bcm63268_groups[group].npins;
return 0;
}
static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm63268_funcs);
}
static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm63268_funcs[selector].name;
}
static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm63268_funcs[selector].groups;
*num_groups = bcm63268_funcs[selector].num_groups;
return 0;
}
static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
{
const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
unsigned int basemode = (unsigned long) desc->drv_data;
unsigned int mask = BIT(bcm63xx_bank_pin(pin));
if (basemode)
regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
0);
if (pin < BCM63XX_BANK_GPIOS) {
/* base mode: 0 => gpio, 1 => mux function */
regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
/* pins 0-23 might be muxed to led */
if (pin < BCM63268_NUM_LEDS)
regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
0);
} else if (pin < BCM63268_NUM_GPIOS) {
/* ctrl reg: 0 => wifi function, 1 => gpio */
regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
}
}
static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct pingroup *pg = &bcm63268_groups[group];
const struct bcm63268_function *f = &bcm63268_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->npins; i++)
bcm63268_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
case BCM63268_LEDCTRL:
reg = BCM63268_LED_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM63268_MODE:
reg = BCM63268_MODE_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM63268_CTRL:
reg = BCM63268_CTRL_REG;
mask = BIT(pg->pins[0]);
val = 0;
break;
case BCM63268_BASEMODE:
reg = BCM63268_BASEMODE_REG;
mask = f->mask;
val = f->mask;
break;
default:
WARN_ON(1);
return -EINVAL;
}
regmap_update_bits(pc->regs, reg, mask, val);
return 0;
}
static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm63268_set_gpio(pc, offset);
return 0;
}
static const struct pinctrl_ops bcm63268_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm63268_pinctrl_get_group_name,
.get_group_pins = bcm63268_pinctrl_get_group_pins,
.get_groups_count = bcm63268_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm63268_pmx_ops = {
.get_function_groups = bcm63268_pinctrl_get_groups,
.get_function_name = bcm63268_pinctrl_get_func_name,
.get_functions_count = bcm63268_pinctrl_get_func_count,
.gpio_request_enable = bcm63268_gpio_request_enable,
.set_mux = bcm63268_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm63268_soc = {
.ngpios = BCM63268_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm63268_pins),
.pctl_ops = &bcm63268_pctl_ops,
.pins = bcm63268_pins,
.pmx_ops = &bcm63268_pmx_ops,
};
static int bcm63268_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);
}
static const struct of_device_id bcm63268_pinctrl_match[] = {
{ .compatible = "brcm,bcm63268-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm63268_pinctrl_driver = {
.probe = bcm63268_pinctrl_probe,
.driver = {
.name = "bcm63268-pinctrl",
.of_match_table = bcm63268_pinctrl_match,
},
};
builtin_platform_driver(bcm63268_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm63268.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
*
* This driver is inspired by:
* pinctrl-nomadik.c, please see original file for copyright information
* pinctrl-tegra.c, please see original file for copyright information
*/
#include <linux/bitmap.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdesc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <dt-bindings/pinctrl/bcm2835.h>
#define MODULE_NAME "pinctrl-bcm2835"
#define BCM2835_NUM_GPIOS 54
#define BCM2711_NUM_GPIOS 58
#define BCM2835_NUM_BANKS 2
#define BCM2835_NUM_IRQS 3
/* GPIO register offsets */
#define GPFSEL0 0x0 /* Function Select */
#define GPSET0 0x1c /* Pin Output Set */
#define GPCLR0 0x28 /* Pin Output Clear */
#define GPLEV0 0x34 /* Pin Level */
#define GPEDS0 0x40 /* Pin Event Detect Status */
#define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
#define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
#define GPHEN0 0x64 /* Pin High Detect Enable */
#define GPLEN0 0x70 /* Pin Low Detect Enable */
#define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
#define GPPUD 0x94 /* Pin Pull-up/down Enable */
#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
#define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
#define FSEL_SHIFT(p) (((p) % 10) * 3)
#define GPIO_REG_OFFSET(p) ((p) / 32)
#define GPIO_REG_SHIFT(p) ((p) % 32)
#define PUD_2711_MASK 0x3
#define PUD_2711_REG_OFFSET(p) ((p) / 16)
#define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
/* argument: bcm2835_pinconf_pull */
#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
#define BCM2711_PULL_NONE 0x0
#define BCM2711_PULL_UP 0x1
#define BCM2711_PULL_DOWN 0x2
struct bcm2835_pinctrl {
struct device *dev;
void __iomem *base;
int *wake_irq;
/* note: locking assumes each bank will have its own unsigned long */
unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
unsigned int irq_type[BCM2711_NUM_GPIOS];
struct pinctrl_dev *pctl_dev;
struct gpio_chip gpio_chip;
struct pinctrl_desc pctl_desc;
struct pinctrl_gpio_range gpio_range;
raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
/* Protect FSEL registers */
spinlock_t fsel_lock;
};
/* pins are just named GPIO0..GPIO53 */
#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
BCM2835_GPIO_PIN(0),
BCM2835_GPIO_PIN(1),
BCM2835_GPIO_PIN(2),
BCM2835_GPIO_PIN(3),
BCM2835_GPIO_PIN(4),
BCM2835_GPIO_PIN(5),
BCM2835_GPIO_PIN(6),
BCM2835_GPIO_PIN(7),
BCM2835_GPIO_PIN(8),
BCM2835_GPIO_PIN(9),
BCM2835_GPIO_PIN(10),
BCM2835_GPIO_PIN(11),
BCM2835_GPIO_PIN(12),
BCM2835_GPIO_PIN(13),
BCM2835_GPIO_PIN(14),
BCM2835_GPIO_PIN(15),
BCM2835_GPIO_PIN(16),
BCM2835_GPIO_PIN(17),
BCM2835_GPIO_PIN(18),
BCM2835_GPIO_PIN(19),
BCM2835_GPIO_PIN(20),
BCM2835_GPIO_PIN(21),
BCM2835_GPIO_PIN(22),
BCM2835_GPIO_PIN(23),
BCM2835_GPIO_PIN(24),
BCM2835_GPIO_PIN(25),
BCM2835_GPIO_PIN(26),
BCM2835_GPIO_PIN(27),
BCM2835_GPIO_PIN(28),
BCM2835_GPIO_PIN(29),
BCM2835_GPIO_PIN(30),
BCM2835_GPIO_PIN(31),
BCM2835_GPIO_PIN(32),
BCM2835_GPIO_PIN(33),
BCM2835_GPIO_PIN(34),
BCM2835_GPIO_PIN(35),
BCM2835_GPIO_PIN(36),
BCM2835_GPIO_PIN(37),
BCM2835_GPIO_PIN(38),
BCM2835_GPIO_PIN(39),
BCM2835_GPIO_PIN(40),
BCM2835_GPIO_PIN(41),
BCM2835_GPIO_PIN(42),
BCM2835_GPIO_PIN(43),
BCM2835_GPIO_PIN(44),
BCM2835_GPIO_PIN(45),
BCM2835_GPIO_PIN(46),
BCM2835_GPIO_PIN(47),
BCM2835_GPIO_PIN(48),
BCM2835_GPIO_PIN(49),
BCM2835_GPIO_PIN(50),
BCM2835_GPIO_PIN(51),
BCM2835_GPIO_PIN(52),
BCM2835_GPIO_PIN(53),
BCM2835_GPIO_PIN(54),
BCM2835_GPIO_PIN(55),
BCM2835_GPIO_PIN(56),
BCM2835_GPIO_PIN(57),
};
/* one pin per group */
static const char * const bcm2835_gpio_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
"gpio24",
"gpio25",
"gpio26",
"gpio27",
"gpio28",
"gpio29",
"gpio30",
"gpio31",
"gpio32",
"gpio33",
"gpio34",
"gpio35",
"gpio36",
"gpio37",
"gpio38",
"gpio39",
"gpio40",
"gpio41",
"gpio42",
"gpio43",
"gpio44",
"gpio45",
"gpio46",
"gpio47",
"gpio48",
"gpio49",
"gpio50",
"gpio51",
"gpio52",
"gpio53",
"gpio54",
"gpio55",
"gpio56",
"gpio57",
};
enum bcm2835_fsel {
BCM2835_FSEL_COUNT = 8,
BCM2835_FSEL_MASK = 0x7,
};
static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
[BCM2835_FSEL_GPIO_IN] = "gpio_in",
[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
[BCM2835_FSEL_ALT0] = "alt0",
[BCM2835_FSEL_ALT1] = "alt1",
[BCM2835_FSEL_ALT2] = "alt2",
[BCM2835_FSEL_ALT3] = "alt3",
[BCM2835_FSEL_ALT4] = "alt4",
[BCM2835_FSEL_ALT5] = "alt5",
};
static const char * const irq_type_names[] = {
[IRQ_TYPE_NONE] = "none",
[IRQ_TYPE_EDGE_RISING] = "edge-rising",
[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
[IRQ_TYPE_EDGE_BOTH] = "edge-both",
[IRQ_TYPE_LEVEL_HIGH] = "level-high",
[IRQ_TYPE_LEVEL_LOW] = "level-low",
};
static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
{
return readl(pc->base + reg);
}
static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
u32 val)
{
writel(val, pc->base + reg);
}
static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
unsigned bit)
{
reg += GPIO_REG_OFFSET(bit) * 4;
return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
}
/* note NOT a read/modify/write cycle */
static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
unsigned reg, unsigned bit)
{
reg += GPIO_REG_OFFSET(bit) * 4;
bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
}
static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
struct bcm2835_pinctrl *pc, unsigned pin)
{
u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
bcm2835_functions[status]);
return status;
}
static inline void bcm2835_pinctrl_fsel_set(
struct bcm2835_pinctrl *pc, unsigned pin,
enum bcm2835_fsel fsel)
{
u32 val;
enum bcm2835_fsel cur;
unsigned long flags;
spin_lock_irqsave(&pc->fsel_lock, flags);
val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
bcm2835_functions[cur]);
if (cur == fsel)
goto unlock;
if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
/* always transition through GPIO_IN */
val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
}
val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
val |= fsel << FSEL_SHIFT(pin);
dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
bcm2835_functions[fsel]);
bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
unlock:
spin_unlock_irqrestore(&pc->fsel_lock, flags);
}
static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
return 0;
}
static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
}
static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
/* Alternative function doesn't clearly provide a direction */
if (fsel > BCM2835_FSEL_GPIO_OUT)
return -EINVAL;
if (fsel == BCM2835_FSEL_GPIO_IN)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
}
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
return 0;
}
static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
{
struct device_node *np = dev_of_node(gc->parent);
struct pinctrl_dev *pctldev = of_pinctrl_get(np);
if (!pctldev)
return 0;
return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
gc->ngpio);
}
static const struct gpio_chip bcm2835_gpio_chip = {
.label = MODULE_NAME,
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.direction_input = bcm2835_gpio_direction_input,
.direction_output = bcm2835_gpio_direction_output,
.get_direction = bcm2835_gpio_get_direction,
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
.base = -1,
.ngpio = BCM2835_NUM_GPIOS,
.can_sleep = false,
.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
};
static const struct gpio_chip bcm2711_gpio_chip = {
.label = "pinctrl-bcm2711",
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.direction_input = bcm2835_gpio_direction_input,
.direction_output = bcm2835_gpio_direction_output,
.get_direction = bcm2835_gpio_get_direction,
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
.base = -1,
.ngpio = BCM2711_NUM_GPIOS,
.can_sleep = false,
.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
};
static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
unsigned int bank, u32 mask)
{
unsigned long events;
unsigned offset;
unsigned gpio;
events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
events &= mask;
events &= pc->enabled_irq_map[bank];
for_each_set_bit(offset, &events, 32) {
gpio = (32 * bank) + offset;
generic_handle_domain_irq(pc->gpio_chip.irq.domain,
gpio);
}
}
static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
struct irq_chip *host_chip = irq_desc_get_chip(desc);
int irq = irq_desc_get_irq(desc);
int group = 0;
int i;
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
if (chip->irq.parents[i] == irq) {
group = i;
break;
}
}
/* This should not happen, every IRQ has a bank */
BUG_ON(i == BCM2835_NUM_IRQS);
chained_irq_enter(host_chip, desc);
switch (group) {
case 0: /* IRQ0 covers GPIOs 0-27 */
bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
break;
case 1: /* IRQ1 covers GPIOs 28-45 */
bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
break;
case 2: /* IRQ2 covers GPIOs 46-57 */
bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
break;
}
chained_irq_exit(host_chip, desc);
}
static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
{
return IRQ_HANDLED;
}
static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
unsigned reg, unsigned offset, bool enable)
{
u32 value;
reg += GPIO_REG_OFFSET(offset) * 4;
value = bcm2835_gpio_rd(pc, reg);
if (enable)
value |= BIT(GPIO_REG_SHIFT(offset));
else
value &= ~(BIT(GPIO_REG_SHIFT(offset)));
bcm2835_gpio_wr(pc, reg, value);
}
/* fast path for IRQ handler */
static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
unsigned offset, bool enable)
{
switch (pc->irq_type[offset]) {
case IRQ_TYPE_EDGE_RISING:
__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
break;
case IRQ_TYPE_EDGE_FALLING:
__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
break;
case IRQ_TYPE_EDGE_BOTH:
__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
break;
case IRQ_TYPE_LEVEL_HIGH:
__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
break;
case IRQ_TYPE_LEVEL_LOW:
__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
break;
}
}
static void bcm2835_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
unsigned gpio = irqd_to_hwirq(data);
unsigned offset = GPIO_REG_SHIFT(gpio);
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
gpiochip_enable_irq(chip, gpio);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
set_bit(offset, &pc->enabled_irq_map[bank]);
bcm2835_gpio_irq_config(pc, gpio, true);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static void bcm2835_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
unsigned gpio = irqd_to_hwirq(data);
unsigned offset = GPIO_REG_SHIFT(gpio);
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
bcm2835_gpio_irq_config(pc, gpio, false);
/* Clear events that were latched prior to clearing event sources */
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
clear_bit(offset, &pc->enabled_irq_map[bank]);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
gpiochip_disable_irq(chip, gpio);
}
static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
unsigned offset, unsigned int type)
{
switch (type) {
case IRQ_TYPE_NONE:
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
case IRQ_TYPE_LEVEL_HIGH:
case IRQ_TYPE_LEVEL_LOW:
pc->irq_type[offset] = type;
break;
default:
return -EINVAL;
}
return 0;
}
/* slower path for reconfiguring IRQ type */
static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
unsigned offset, unsigned int type)
{
switch (type) {
case IRQ_TYPE_NONE:
if (pc->irq_type[offset] != type) {
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
}
break;
case IRQ_TYPE_EDGE_RISING:
if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
/* RISING already enabled, disable FALLING */
pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
} else if (pc->irq_type[offset] != type) {
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
bcm2835_gpio_irq_config(pc, offset, true);
}
break;
case IRQ_TYPE_EDGE_FALLING:
if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
/* FALLING already enabled, disable RISING */
pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
} else if (pc->irq_type[offset] != type) {
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
bcm2835_gpio_irq_config(pc, offset, true);
}
break;
case IRQ_TYPE_EDGE_BOTH:
if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
/* RISING already enabled, enable FALLING too */
pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
bcm2835_gpio_irq_config(pc, offset, true);
pc->irq_type[offset] = type;
} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
/* FALLING already enabled, enable RISING too */
pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
bcm2835_gpio_irq_config(pc, offset, true);
pc->irq_type[offset] = type;
} else if (pc->irq_type[offset] != type) {
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
bcm2835_gpio_irq_config(pc, offset, true);
}
break;
case IRQ_TYPE_LEVEL_HIGH:
case IRQ_TYPE_LEVEL_LOW:
if (pc->irq_type[offset] != type) {
bcm2835_gpio_irq_config(pc, offset, false);
pc->irq_type[offset] = type;
bcm2835_gpio_irq_config(pc, offset, true);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
unsigned gpio = irqd_to_hwirq(data);
unsigned offset = GPIO_REG_SHIFT(gpio);
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
int ret;
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
if (test_bit(offset, &pc->enabled_irq_map[bank]))
ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
else
ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(data, handle_edge_irq);
else
irq_set_handler_locked(data, handle_level_irq);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
return ret;
}
static void bcm2835_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
unsigned gpio = irqd_to_hwirq(data);
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
}
static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
unsigned gpio = irqd_to_hwirq(data);
unsigned int irqgroup;
int ret = -EINVAL;
if (!pc->wake_irq)
return ret;
if (gpio <= 27)
irqgroup = 0;
else if (gpio >= 28 && gpio <= 45)
irqgroup = 1;
else if (gpio >= 46 && gpio <= 57)
irqgroup = 2;
else
return ret;
if (on)
ret = enable_irq_wake(pc->wake_irq[irqgroup]);
else
ret = disable_irq_wake(pc->wake_irq[irqgroup]);
return ret;
}
static const struct irq_chip bcm2835_gpio_irq_chip = {
.name = MODULE_NAME,
.irq_set_type = bcm2835_gpio_irq_set_type,
.irq_ack = bcm2835_gpio_irq_ack,
.irq_mask = bcm2835_gpio_irq_mask,
.irq_unmask = bcm2835_gpio_irq_unmask,
.irq_set_wake = bcm2835_gpio_irq_set_wake,
.flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
return BCM2835_NUM_GPIOS;
}
static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm2835_gpio_groups[selector];
}
static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
*pins = &bcm2835_gpio_pins[selector].number;
*num_pins = 1;
return 0;
}
static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned offset)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pc->gpio_chip;
enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
const char *fname = bcm2835_functions[fsel];
int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
int irq = irq_find_mapping(chip->irq.domain, offset);
seq_printf(s, "function %s in %s; irq %d (%s)",
fname, value ? "hi" : "lo",
irq, irq_type_names[pc->irq_type[offset]]);
}
static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *maps, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree(maps[i].data.configs.configs);
kfree(maps);
}
static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
struct device_node *np, u32 pin, u32 fnum,
struct pinctrl_map **maps)
{
struct pinctrl_map *map = *maps;
if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
return -EINVAL;
}
map->type = PIN_MAP_TYPE_MUX_GROUP;
map->data.mux.group = bcm2835_gpio_groups[pin];
map->data.mux.function = bcm2835_functions[fnum];
(*maps)++;
return 0;
}
static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
struct device_node *np, u32 pin, u32 pull,
struct pinctrl_map **maps)
{
struct pinctrl_map *map = *maps;
unsigned long *configs;
if (pull > 2) {
dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
return -EINVAL;
}
configs = kzalloc(sizeof(*configs), GFP_KERNEL);
if (!configs)
return -ENOMEM;
configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
map->type = PIN_MAP_TYPE_CONFIGS_PIN;
map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
map->data.configs.configs = configs;
map->data.configs.num_configs = 1;
(*maps)++;
return 0;
}
static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned int *num_maps)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct property *pins, *funcs, *pulls;
int num_pins, num_funcs, num_pulls, maps_per_pin;
struct pinctrl_map *maps, *cur_map;
int i, err;
u32 pin, func, pull;
/* Check for generic binding in this node */
err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
if (err || *num_maps)
return err;
/* Generic binding did not find anything continue with legacy parse */
pins = of_find_property(np, "brcm,pins", NULL);
if (!pins) {
dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
return -EINVAL;
}
funcs = of_find_property(np, "brcm,function", NULL);
pulls = of_find_property(np, "brcm,pull", NULL);
if (!funcs && !pulls) {
dev_err(pc->dev,
"%pOF: neither brcm,function nor brcm,pull specified\n",
np);
return -EINVAL;
}
num_pins = pins->length / 4;
num_funcs = funcs ? (funcs->length / 4) : 0;
num_pulls = pulls ? (pulls->length / 4) : 0;
if (num_funcs > 1 && num_funcs != num_pins) {
dev_err(pc->dev,
"%pOF: brcm,function must have 1 or %d entries\n",
np, num_pins);
return -EINVAL;
}
if (num_pulls > 1 && num_pulls != num_pins) {
dev_err(pc->dev,
"%pOF: brcm,pull must have 1 or %d entries\n",
np, num_pins);
return -EINVAL;
}
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (num_pulls)
maps_per_pin++;
cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
GFP_KERNEL);
if (!maps)
return -ENOMEM;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
if (err)
goto out;
if (pin >= pc->pctl_desc.npins) {
dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
np, pin);
err = -EINVAL;
goto out;
}
if (num_funcs) {
err = of_property_read_u32_index(np, "brcm,function",
(num_funcs > 1) ? i : 0, &func);
if (err)
goto out;
err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
func, &cur_map);
if (err)
goto out;
}
if (num_pulls) {
err = of_property_read_u32_index(np, "brcm,pull",
(num_pulls > 1) ? i : 0, &pull);
if (err)
goto out;
err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
pull, &cur_map);
if (err)
goto out;
}
}
*map = maps;
*num_maps = num_pins * maps_per_pin;
return 0;
out:
bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
return err;
}
static const struct pinctrl_ops bcm2835_pctl_ops = {
.get_groups_count = bcm2835_pctl_get_groups_count,
.get_group_name = bcm2835_pctl_get_group_name,
.get_group_pins = bcm2835_pctl_get_group_pins,
.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
.dt_free_map = bcm2835_pctl_dt_free_map,
};
static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
unsigned offset)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable by setting to GPIO_IN */
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
return 0;
}
static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
{
return BCM2835_FSEL_COUNT;
}
static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm2835_functions[selector];
}
static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
/* every pin can do every function */
*groups = bcm2835_gpio_groups;
*num_groups = BCM2835_NUM_GPIOS;
return 0;
}
static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
unsigned func_selector,
unsigned group_selector)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
return 0;
}
static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable by setting to GPIO_IN */
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
}
static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset,
bool input)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
enum bcm2835_fsel fsel = input ?
BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
bcm2835_pinctrl_fsel_set(pc, offset, fsel);
return 0;
}
static const struct pinmux_ops bcm2835_pmx_ops = {
.free = bcm2835_pmx_free,
.get_functions_count = bcm2835_pmx_get_functions_count,
.get_function_name = bcm2835_pmx_get_function_name,
.get_function_groups = bcm2835_pmx_get_function_groups,
.set_mux = bcm2835_pmx_set,
.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
};
static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
/* No way to read back config in HW */
return -ENOTSUPP;
}
static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
unsigned int pin, unsigned int arg)
{
u32 off, bit;
off = GPIO_REG_OFFSET(pin);
bit = GPIO_REG_SHIFT(pin);
bcm2835_gpio_wr(pc, GPPUD, arg & 3);
/*
* BCM2835 datasheet say to wait 150 cycles, but not of what.
* But the VideoCore firmware delay for this operation
* based nearly on the same amount of VPU cycles and this clock
* runs at 250 MHz.
*/
udelay(1);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
udelay(1);
bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
}
static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
u32 param, arg;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
/* Set legacy brcm,pull */
case BCM2835_PINCONF_PARAM_PULL:
bcm2835_pull_config_set(pc, pin, arg);
break;
/* Set pull generic bindings */
case PIN_CONFIG_BIAS_DISABLE:
bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
break;
case PIN_CONFIG_BIAS_PULL_UP:
bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
break;
/* Set output-high or output-low */
case PIN_CONFIG_OUTPUT:
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
break;
default:
return -ENOTSUPP;
} /* switch param type */
} /* for each config */
return 0;
}
static const struct pinconf_ops bcm2835_pinconf_ops = {
.is_generic = true,
.pin_config_get = bcm2835_pinconf_get,
.pin_config_set = bcm2835_pinconf_set,
};
static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
unsigned int pin, unsigned int arg)
{
u32 shifter;
u32 value;
u32 off;
off = PUD_2711_REG_OFFSET(pin);
shifter = PUD_2711_REG_SHIFT(pin);
value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
value &= ~(PUD_2711_MASK << shifter);
value |= (arg << shifter);
bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
}
static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
u32 param, arg;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
/* convert legacy brcm,pull */
case BCM2835_PINCONF_PARAM_PULL:
if (arg == BCM2835_PUD_UP)
arg = BCM2711_PULL_UP;
else if (arg == BCM2835_PUD_DOWN)
arg = BCM2711_PULL_DOWN;
else
arg = BCM2711_PULL_NONE;
bcm2711_pull_config_set(pc, pin, arg);
break;
/* Set pull generic bindings */
case PIN_CONFIG_BIAS_DISABLE:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
break;
case PIN_CONFIG_BIAS_PULL_UP:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
break;
/* Set output-high or output-low */
case PIN_CONFIG_OUTPUT:
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
break;
default:
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
static const struct pinconf_ops bcm2711_pinconf_ops = {
.is_generic = true,
.pin_config_get = bcm2835_pinconf_get,
.pin_config_set = bcm2711_pinconf_set,
};
static const struct pinctrl_desc bcm2835_pinctrl_desc = {
.name = MODULE_NAME,
.pins = bcm2835_gpio_pins,
.npins = BCM2835_NUM_GPIOS,
.pctlops = &bcm2835_pctl_ops,
.pmxops = &bcm2835_pmx_ops,
.confops = &bcm2835_pinconf_ops,
.owner = THIS_MODULE,
};
static const struct pinctrl_desc bcm2711_pinctrl_desc = {
.name = "pinctrl-bcm2711",
.pins = bcm2835_gpio_pins,
.npins = BCM2711_NUM_GPIOS,
.pctlops = &bcm2835_pctl_ops,
.pmxops = &bcm2835_pmx_ops,
.confops = &bcm2711_pinconf_ops,
.owner = THIS_MODULE,
};
static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
.name = MODULE_NAME,
.npins = BCM2835_NUM_GPIOS,
};
static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
.name = "pinctrl-bcm2711",
.npins = BCM2711_NUM_GPIOS,
};
struct bcm_plat_data {
const struct gpio_chip *gpio_chip;
const struct pinctrl_desc *pctl_desc;
const struct pinctrl_gpio_range *gpio_range;
};
static const struct bcm_plat_data bcm2835_plat_data = {
.gpio_chip = &bcm2835_gpio_chip,
.pctl_desc = &bcm2835_pinctrl_desc,
.gpio_range = &bcm2835_pinctrl_gpio_range,
};
static const struct bcm_plat_data bcm2711_plat_data = {
.gpio_chip = &bcm2711_gpio_chip,
.pctl_desc = &bcm2711_pinctrl_desc,
.gpio_range = &bcm2711_pinctrl_gpio_range,
};
static const struct of_device_id bcm2835_pinctrl_match[] = {
{
.compatible = "brcm,bcm2835-gpio",
.data = &bcm2835_plat_data,
},
{
.compatible = "brcm,bcm2711-gpio",
.data = &bcm2711_plat_data,
},
{
.compatible = "brcm,bcm7211-gpio",
.data = &bcm2711_plat_data,
},
{}
};
static int bcm2835_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
const struct bcm_plat_data *pdata;
struct bcm2835_pinctrl *pc;
struct gpio_irq_chip *girq;
struct resource iomem;
int err, i;
const struct of_device_id *match;
int is_7211 = 0;
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
if (!pc)
return -ENOMEM;
platform_set_drvdata(pdev, pc);
pc->dev = dev;
err = of_address_to_resource(np, 0, &iomem);
if (err) {
dev_err(dev, "could not get IO memory\n");
return err;
}
pc->base = devm_ioremap_resource(dev, &iomem);
if (IS_ERR(pc->base))
return PTR_ERR(pc->base);
match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
if (!match)
return -EINVAL;
pdata = match->data;
is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
pc->gpio_chip = *pdata->gpio_chip;
pc->gpio_chip.parent = dev;
spin_lock_init(&pc->fsel_lock);
for (i = 0; i < BCM2835_NUM_BANKS; i++) {
unsigned long events;
unsigned offset;
/* clear event detection flags */
bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
/* clear all the events */
events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
for_each_set_bit(offset, &events, 32)
bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
raw_spin_lock_init(&pc->irq_lock[i]);
}
pc->pctl_desc = *pdata->pctl_desc;
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
if (IS_ERR(pc->pctl_dev)) {
gpiochip_remove(&pc->gpio_chip);
return PTR_ERR(pc->pctl_dev);
}
pc->gpio_range = *pdata->gpio_range;
pc->gpio_range.base = pc->gpio_chip.base;
pc->gpio_range.gc = &pc->gpio_chip;
pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
girq = &pc->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
girq->parent_handler = bcm2835_gpio_irq_handler;
girq->num_parents = BCM2835_NUM_IRQS;
girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
err = -ENOMEM;
goto out_remove;
}
if (is_7211) {
pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
sizeof(*pc->wake_irq),
GFP_KERNEL);
if (!pc->wake_irq) {
err = -ENOMEM;
goto out_remove;
}
}
/*
* Use the same handler for all groups: this is necessary
* since we use one gpiochip to cover all lines - the
* irq handler then needs to figure out which group and
* bank that was firing the IRQ and look up the per-group
* and bank data.
*/
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
int len;
char *name;
girq->parents[i] = irq_of_parse_and_map(np, i);
if (!is_7211) {
if (!girq->parents[i]) {
girq->num_parents = i;
break;
}
continue;
}
/* Skip over the all banks interrupts */
pc->wake_irq[i] = irq_of_parse_and_map(np, i +
BCM2835_NUM_IRQS + 1);
len = strlen(dev_name(pc->dev)) + 16;
name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
if (!name) {
err = -ENOMEM;
goto out_remove;
}
snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
/* These are optional interrupts */
err = devm_request_irq(dev, pc->wake_irq[i],
bcm2835_gpio_wake_irq_handler,
IRQF_SHARED, name, pc);
if (err)
dev_warn(dev, "unable to request wake IRQ %d\n",
pc->wake_irq[i]);
}
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
err = gpiochip_add_data(&pc->gpio_chip, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
goto out_remove;
}
return 0;
out_remove:
pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
return err;
}
static struct platform_driver bcm2835_pinctrl_driver = {
.probe = bcm2835_pinctrl_probe,
.driver = {
.name = MODULE_NAME,
.of_match_table = bcm2835_pinctrl_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(bcm2835_pinctrl_driver);
MODULE_AUTHOR("Chris Boot");
MODULE_AUTHOR("Simon Arlott");
MODULE_AUTHOR("Stephen Warren");
MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm2835.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6368 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6368_NUM_GPIOS 38
#define BCM6368_MODE_REG 0x18
#define BCM6368_BASEMODE_REG 0x38
#define BCM6368_BASEMODE_MASK 0x7
#define BCM6368_BASEMODE_GPIO 0x0
#define BCM6368_BASEMODE_UART1 0x1
struct bcm6368_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned dir_out:16;
unsigned basemode:3;
};
struct bcm6368_priv {
struct regmap_field *overlays;
};
#define BCM6368_BASEMODE_PIN(a, b) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)true \
}
static const struct pinctrl_pin_desc bcm6368_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
BCM6368_BASEMODE_PIN(30, "gpio30"),
BCM6368_BASEMODE_PIN(31, "gpio31"),
BCM6368_BASEMODE_PIN(32, "gpio32"),
BCM6368_BASEMODE_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
static struct pingroup bcm6368_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(uart1_grp),
};
static const char * const analog_afe_0_groups[] = {
"gpio0",
};
static const char * const analog_afe_1_groups[] = {
"gpio1",
};
static const char * const sys_irq_groups[] = {
"gpio2",
};
static const char * const serial_led_data_groups[] = {
"gpio3",
};
static const char * const serial_led_clk_groups[] = {
"gpio4",
};
static const char * const inet_led_groups[] = {
"gpio5",
};
static const char * const ephy0_led_groups[] = {
"gpio6",
};
static const char * const ephy1_led_groups[] = {
"gpio7",
};
static const char * const ephy2_led_groups[] = {
"gpio8",
};
static const char * const ephy3_led_groups[] = {
"gpio9",
};
static const char * const robosw_led_data_groups[] = {
"gpio10",
};
static const char * const robosw_led_clk_groups[] = {
"gpio11",
};
static const char * const robosw_led0_groups[] = {
"gpio12",
};
static const char * const robosw_led1_groups[] = {
"gpio13",
};
static const char * const usb_device_led_groups[] = {
"gpio14",
};
static const char * const pci_req1_groups[] = {
"gpio16",
};
static const char * const pci_gnt1_groups[] = {
"gpio17",
};
static const char * const pci_intb_groups[] = {
"gpio18",
};
static const char * const pci_req0_groups[] = {
"gpio19",
};
static const char * const pci_gnt0_groups[] = {
"gpio20",
};
static const char * const pcmcia_cd1_groups[] = {
"gpio22",
};
static const char * const pcmcia_cd2_groups[] = {
"gpio23",
};
static const char * const pcmcia_vs1_groups[] = {
"gpio24",
};
static const char * const pcmcia_vs2_groups[] = {
"gpio25",
};
static const char * const ebi_cs2_groups[] = {
"gpio26",
};
static const char * const ebi_cs3_groups[] = {
"gpio27",
};
static const char * const spi_cs2_groups[] = {
"gpio28",
};
static const char * const spi_cs3_groups[] = {
"gpio29",
};
static const char * const spi_cs4_groups[] = {
"gpio30",
};
static const char * const spi_cs5_groups[] = {
"gpio31",
};
static const char * const uart1_groups[] = {
"uart1_grp",
};
#define BCM6368_FUN(n, out) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.dir_out = out, \
}
#define BCM6368_BASEMODE_FUN(n, val, out) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.basemode = BCM6368_BASEMODE_##val, \
.dir_out = out, \
}
static const struct bcm6368_function bcm6368_funcs[] = {
BCM6368_FUN(analog_afe_0, 1),
BCM6368_FUN(analog_afe_1, 1),
BCM6368_FUN(sys_irq, 1),
BCM6368_FUN(serial_led_data, 1),
BCM6368_FUN(serial_led_clk, 1),
BCM6368_FUN(inet_led, 1),
BCM6368_FUN(ephy0_led, 1),
BCM6368_FUN(ephy1_led, 1),
BCM6368_FUN(ephy2_led, 1),
BCM6368_FUN(ephy3_led, 1),
BCM6368_FUN(robosw_led_data, 1),
BCM6368_FUN(robosw_led_clk, 1),
BCM6368_FUN(robosw_led0, 1),
BCM6368_FUN(robosw_led1, 1),
BCM6368_FUN(usb_device_led, 1),
BCM6368_FUN(pci_req1, 0),
BCM6368_FUN(pci_gnt1, 0),
BCM6368_FUN(pci_intb, 0),
BCM6368_FUN(pci_req0, 0),
BCM6368_FUN(pci_gnt0, 0),
BCM6368_FUN(pcmcia_cd1, 0),
BCM6368_FUN(pcmcia_cd2, 0),
BCM6368_FUN(pcmcia_vs1, 0),
BCM6368_FUN(pcmcia_vs2, 0),
BCM6368_FUN(ebi_cs2, 1),
BCM6368_FUN(ebi_cs3, 1),
BCM6368_FUN(spi_cs2, 1),
BCM6368_FUN(spi_cs3, 1),
BCM6368_FUN(spi_cs4, 1),
BCM6368_FUN(spi_cs5, 1),
BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
};
static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6368_groups);
}
static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6368_groups[group].name;
}
static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *npins)
{
*pins = bcm6368_groups[group].pins;
*npins = bcm6368_groups[group].npins;
return 0;
}
static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6368_funcs);
}
static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6368_funcs[selector].name;
}
static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6368_funcs[selector].groups;
*num_groups = bcm6368_funcs[selector].num_groups;
return 0;
}
static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
const struct pingroup *pg = &bcm6368_groups[group];
const struct bcm6368_function *fun = &bcm6368_funcs[selector];
int i, pin;
if (fun->basemode) {
unsigned int mask = 0;
for (i = 0; i < pg->npins; i++) {
pin = pg->pins[i];
if (pin < BCM63XX_BANK_GPIOS)
mask |= BIT(pin);
}
regmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0);
regmap_field_write(priv->overlays, fun->basemode);
} else {
pin = pg->pins[0];
if (bcm6368_pins[pin].drv_data)
regmap_field_write(priv->overlays,
BCM6368_BASEMODE_GPIO);
regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin),
BIT(pin));
}
for (pin = 0; pin < pg->npins; pin++) {
struct pinctrl_gpio_range *range;
int hw_gpio = bcm6368_pins[pin].number;
range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);
if (range) {
struct gpio_chip *gc = range->gc;
if (fun->dir_out & BIT(pin))
gc->direction_output(gc, hw_gpio, 0);
else
gc->direction_input(gc, hw_gpio);
}
}
return 0;
}
static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
if (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data)
return 0;
/* disable all functions using this pin */
if (offset < BCM63XX_BANK_GPIOS)
regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0);
if (bcm6368_pins[offset].drv_data)
regmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO);
return 0;
}
static const struct pinctrl_ops bcm6368_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6368_pinctrl_get_group_name,
.get_group_pins = bcm6368_pinctrl_get_group_pins,
.get_groups_count = bcm6368_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm6368_pmx_ops = {
.get_function_groups = bcm6368_pinctrl_get_groups,
.get_function_name = bcm6368_pinctrl_get_func_name,
.get_functions_count = bcm6368_pinctrl_get_func_count,
.gpio_request_enable = bcm6368_gpio_request_enable,
.set_mux = bcm6368_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6368_soc = {
.ngpios = BCM6368_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6368_pins),
.pctl_ops = &bcm6368_pctl_ops,
.pins = bcm6368_pins,
.pmx_ops = &bcm6368_pmx_ops,
};
static int bcm6368_pinctrl_probe(struct platform_device *pdev)
{
struct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15);
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct bcm6368_priv *priv;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
err = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv);
if (err)
return err;
pc = platform_get_drvdata(pdev);
priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
if (IS_ERR(priv->overlays))
return PTR_ERR(priv->overlays);
return 0;
}
static const struct of_device_id bcm6368_pinctrl_match[] = {
{ .compatible = "brcm,bcm6368-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6368_pinctrl_driver = {
.probe = bcm6368_pinctrl_probe,
.driver = {
.name = "bcm6368-pinctrl",
.of_match_table = bcm6368_pinctrl_match,
},
};
builtin_platform_driver(bcm6368_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm6368.c
|
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014-2017 Broadcom
/*
* This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
* supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
* pull up/down, slew and drive strength are also supported in this driver.
*
* Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
* through the interaction with the NSP IOMUX controller.
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "../pinctrl-utils.h"
#define NSP_CHIP_A_INT_STATUS 0x00
#define NSP_CHIP_A_INT_MASK 0x04
#define NSP_GPIO_DATA_IN 0x40
#define NSP_GPIO_DATA_OUT 0x44
#define NSP_GPIO_OUT_EN 0x48
#define NSP_GPIO_INT_POLARITY 0x50
#define NSP_GPIO_INT_MASK 0x54
#define NSP_GPIO_EVENT 0x58
#define NSP_GPIO_EVENT_INT_MASK 0x5c
#define NSP_GPIO_EVENT_INT_POLARITY 0x64
#define NSP_CHIP_A_GPIO_INT_BIT 0x01
/* I/O parameters offset for chipcommon A GPIO */
#define NSP_GPIO_DRV_CTRL 0x00
#define NSP_GPIO_HYSTERESIS_EN 0x10
#define NSP_GPIO_SLEW_RATE_EN 0x14
#define NSP_PULL_UP_EN 0x18
#define NSP_PULL_DOWN_EN 0x1c
#define GPIO_DRV_STRENGTH_BITS 0x03
/*
* nsp GPIO core
*
* @dev: pointer to device
* @base: I/O register base for nsp GPIO controller
* @io_ctrl: I/O register base for PINCONF support outside the GPIO block
* @gc: GPIO chip
* @pctl: pointer to pinctrl_dev
* @pctldesc: pinctrl descriptor
* @lock: lock to protect access to I/O registers
*/
struct nsp_gpio {
struct device *dev;
void __iomem *base;
void __iomem *io_ctrl;
struct gpio_chip gc;
struct pinctrl_dev *pctl;
struct pinctrl_desc pctldesc;
raw_spinlock_t lock;
};
enum base_type {
REG,
IO_CTRL
};
/*
* Mapping from PINCONF pins to GPIO pins is 1-to-1
*/
static inline unsigned nsp_pin_to_gpio(unsigned pin)
{
return pin;
}
/*
* nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
* nsp GPIO register
*
* @nsp_gpio: nsp GPIO device
* @base_type: reg base to modify
* @reg: register offset
* @gpio: GPIO pin
* @set: set or clear
*/
static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
unsigned int reg, unsigned gpio, bool set)
{
u32 val;
void __iomem *base_address;
if (address == IO_CTRL)
base_address = chip->io_ctrl;
else
base_address = chip->base;
val = readl(base_address + reg);
if (set)
val |= BIT(gpio);
else
val &= ~BIT(gpio);
writel(val, base_address + reg);
}
/*
* nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
* nsp GPIO register
*/
static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
unsigned int reg, unsigned gpio)
{
if (address == IO_CTRL)
return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
else
return !!(readl(chip->base + reg) & BIT(gpio));
}
static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
{
struct gpio_chip *gc = (struct gpio_chip *)data;
struct nsp_gpio *chip = gpiochip_get_data(gc);
int bit;
unsigned long int_bits = 0;
u32 int_status;
/* go through the entire GPIOs and handle all interrupts */
int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
unsigned int event, level;
/* Get level and edge interrupts */
event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
readl(chip->base + NSP_GPIO_EVENT);
level = readl(chip->base + NSP_GPIO_DATA_IN) ^
readl(chip->base + NSP_GPIO_INT_POLARITY);
level &= readl(chip->base + NSP_GPIO_INT_MASK);
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, bit);
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;
}
static void nsp_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = d->hwirq;
u32 val = BIT(gpio);
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
writel(val, chip->base + NSP_GPIO_EVENT);
}
/*
* nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
*
* @d: IRQ chip data
* @unmask: mask/unmask GPIO interrupt
*/
static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = d->hwirq;
u32 trigger_type;
trigger_type = irq_get_trigger_type(d->irq);
if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
else
nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
}
static void nsp_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, false);
raw_spin_unlock_irqrestore(&chip->lock, flags);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void nsp_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_gpio_irq_set_mask(d, true);
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned gpio = d->hwirq;
bool level_low;
bool falling;
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
falling = false;
break;
case IRQ_TYPE_EDGE_FALLING:
falling = true;
break;
case IRQ_TYPE_LEVEL_HIGH:
level_low = false;
break;
case IRQ_TYPE_LEVEL_LOW:
level_low = true;
break;
default:
dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
type);
raw_spin_unlock_irqrestore(&chip->lock, flags);
return -EINVAL;
}
nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
level_low ? "true" : "false", falling ? "true" : "false");
return 0;
}
static const struct irq_chip nsp_gpio_irq_chip = {
.name = "gpio-a",
.irq_ack = nsp_gpio_irq_ack,
.irq_mask = nsp_gpio_irq_mask,
.irq_unmask = nsp_gpio_irq_unmask,
.irq_set_type = nsp_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
return 0;
}
static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
int val)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
return 0;
}
static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
int val;
raw_spin_lock_irqsave(&chip->lock, flags);
val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
raw_spin_unlock_irqrestore(&chip->lock, flags);
return !val;
}
static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
}
static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
}
static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
{
return 1;
}
/*
* Only one group: "gpio_grp", since this local pinctrl device only performs
* GPIO specific PINCONF configurations
*/
static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return "gpio_grp";
}
static const struct pinctrl_ops nsp_pctrl_ops = {
.get_groups_count = nsp_get_groups_count,
.get_group_name = nsp_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
{
if (slew)
nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
else
nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
return 0;
}
static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
bool pull_up, bool pull_down)
{
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
gpio, pull_up, pull_down);
return 0;
}
static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
bool *pull_up, bool *pull_down)
{
unsigned long flags;
raw_spin_lock_irqsave(&chip->lock, flags);
*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
u32 strength)
{
u32 offset, shift, i;
u32 val;
unsigned long flags;
/* make sure drive strength is supported */
if (strength < 2 || strength > 16 || (strength % 2))
return -ENOTSUPP;
shift = gpio;
offset = NSP_GPIO_DRV_CTRL;
dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
strength);
raw_spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
val = readl(chip->io_ctrl + offset);
val &= ~BIT(shift);
val |= ((strength >> (i-1)) & 0x1) << shift;
writel(val, chip->io_ctrl + offset);
offset += 4;
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
u16 *strength)
{
unsigned int offset, shift;
u32 val;
unsigned long flags;
int i;
offset = NSP_GPIO_DRV_CTRL;
shift = gpio;
raw_spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
val = readl(chip->io_ctrl + offset) & BIT(shift);
val >>= shift;
*strength += (val << i);
offset += 4;
}
/* convert to mA */
*strength = (*strength + 1) * 2;
raw_spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long *config)
{
return 0;
}
static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long *configs, unsigned num_configs)
{
return 0;
}
static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int gpio;
u16 arg = 0;
bool pull_up, pull_down;
int ret;
gpio = nsp_pin_to_gpio(pin);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if ((pull_up == false) && (pull_down == false))
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_UP:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if (pull_up)
return 0;
else
return -EINVAL;
case PIN_CONFIG_BIAS_PULL_DOWN:
nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
if (pull_down)
return 0;
else
return -EINVAL;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = nsp_gpio_get_strength(chip, gpio, &arg);
if (ret)
return ret;
*config = pinconf_to_config_packed(param, arg);
return 0;
default:
return -ENOTSUPP;
}
}
static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 arg;
unsigned int i, gpio;
int ret = -ENOTSUPP;
gpio = nsp_pin_to_gpio(pin);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = nsp_gpio_set_pull(chip, gpio, false, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = nsp_gpio_set_pull(chip, gpio, true, false);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = nsp_gpio_set_pull(chip, gpio, false, true);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = nsp_gpio_set_strength(chip, gpio, arg);
if (ret < 0)
goto out;
break;
case PIN_CONFIG_SLEW_RATE:
ret = nsp_gpio_set_slew(chip, gpio, arg);
if (ret < 0)
goto out;
break;
default:
dev_err(chip->dev, "invalid configuration\n");
return -ENOTSUPP;
}
}
out:
return ret;
}
static const struct pinconf_ops nsp_pconf_ops = {
.is_generic = true,
.pin_config_get = nsp_pin_config_get,
.pin_config_set = nsp_pin_config_set,
.pin_config_group_get = nsp_pin_config_group_get,
.pin_config_group_set = nsp_pin_config_group_set,
};
/*
* NSP GPIO controller supports some PINCONF related configurations such as
* pull up, pull down, slew and drive strength, when the pin is configured
* to GPIO.
*
* Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
* local GPIO pins
*/
static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
{
struct pinctrl_desc *pctldesc = &chip->pctldesc;
struct pinctrl_pin_desc *pins;
struct gpio_chip *gc = &chip->gc;
int i;
pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < gc->ngpio; i++) {
pins[i].number = i;
pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
"gpio-%d", i);
if (!pins[i].name)
return -ENOMEM;
}
pctldesc->name = dev_name(chip->dev);
pctldesc->pctlops = &nsp_pctrl_ops;
pctldesc->pins = pins;
pctldesc->npins = gc->ngpio;
pctldesc->confops = &nsp_pconf_ops;
chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
if (IS_ERR(chip->pctl)) {
dev_err(chip->dev, "unable to register pinctrl device\n");
return PTR_ERR(chip->pctl);
}
return 0;
}
static const struct of_device_id nsp_gpio_of_match[] = {
{.compatible = "brcm,nsp-gpio-a",},
{}
};
static int nsp_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct nsp_gpio *chip;
struct gpio_chip *gc;
u32 val;
int irq, ret;
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
dev_err(&pdev->dev, "Missing ngpios OF property\n");
return -ENODEV;
}
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = dev;
platform_set_drvdata(pdev, chip);
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->base);
}
chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(chip->io_ctrl)) {
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->io_ctrl);
}
raw_spin_lock_init(&chip->lock);
gc = &chip->gc;
gc->base = -1;
gc->can_sleep = false;
gc->ngpio = val;
gc->label = dev_name(dev);
gc->parent = dev;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->direction_input = nsp_gpio_direction_input;
gc->direction_output = nsp_gpio_direction_output;
gc->get_direction = nsp_gpio_get_direction;
gc->set = nsp_gpio_set;
gc->get = nsp_gpio_get;
/* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
struct gpio_irq_chip *girq;
val = readl(chip->base + NSP_CHIP_A_INT_MASK);
val = val | NSP_CHIP_A_GPIO_INT_BIT;
writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
/* Install ISR for this GPIO controller. */
ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
IRQF_SHARED, "gpio-a", &chip->gc);
if (ret) {
dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
irq, ret);
return ret;
}
girq = &chip->gc.irq;
gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
ret = devm_gpiochip_add_data(dev, gc, chip);
if (ret < 0)
return dev_err_probe(dev, ret, "unable to add GPIO chip\n");
ret = nsp_gpio_register_pinconf(chip);
if (ret) {
dev_err(dev, "unable to register pinconf\n");
return ret;
}
return 0;
}
static struct platform_driver nsp_gpio_driver = {
.driver = {
.name = "nsp-gpio-a",
.of_match_table = nsp_gpio_of_match,
},
.probe = nsp_gpio_probe,
};
static int __init nsp_gpio_init(void)
{
return platform_driver_register(&nsp_gpio_driver);
}
arch_initcall_sync(nsp_gpio_init);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6362 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6362_BANK_GPIOS 32
#define BCM6362_NUM_GPIOS 48
#define BCM6362_NUM_LEDS 24
#define BCM6362_LED_REG 0x10
#define BCM6362_MODE_REG 0x18
#define BCM6362_CTRL_REG 0x1c
#define BCM6362_BASEMODE_REG 0x38
#define BASEMODE_NAND BIT(2)
enum bcm6362_pinctrl_reg {
BCM6362_LEDCTRL,
BCM6362_MODE,
BCM6362_CTRL,
BCM6362_BASEMODE,
};
struct bcm6362_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
enum bcm6362_pinctrl_reg reg;
uint32_t basemode_mask;
};
#define BCM6362_PIN(a, b, mask) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(mask), \
}
static const struct pinctrl_pin_desc bcm6362_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
BCM6362_PIN(8, "gpio8", BASEMODE_NAND),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
BCM6362_PIN(12, "gpio12", BASEMODE_NAND),
BCM6362_PIN(13, "gpio13", BASEMODE_NAND),
BCM6362_PIN(14, "gpio14", BASEMODE_NAND),
BCM6362_PIN(15, "gpio15", BASEMODE_NAND),
BCM6362_PIN(16, "gpio16", BASEMODE_NAND),
BCM6362_PIN(17, "gpio17", BASEMODE_NAND),
BCM6362_PIN(18, "gpio18", BASEMODE_NAND),
BCM6362_PIN(19, "gpio19", BASEMODE_NAND),
BCM6362_PIN(20, "gpio20", BASEMODE_NAND),
BCM6362_PIN(21, "gpio21", BASEMODE_NAND),
BCM6362_PIN(22, "gpio22", BASEMODE_NAND),
BCM6362_PIN(23, "gpio23", BASEMODE_NAND),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
BCM6362_PIN(27, "gpio27", BASEMODE_NAND),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned nand_grp_pins[] = {
8, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 27,
};
static struct pingroup bcm6362_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(nand_grp),
};
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
static const char * const usb_device_led_groups[] = {
"gpio0",
};
static const char * const sys_irq_groups[] = {
"gpio1",
};
static const char * const serial_led_clk_groups[] = {
"gpio2",
};
static const char * const serial_led_data_groups[] = {
"gpio3",
};
static const char * const robosw_led_data_groups[] = {
"gpio4",
};
static const char * const robosw_led_clk_groups[] = {
"gpio5",
};
static const char * const robosw_led0_groups[] = {
"gpio6",
};
static const char * const robosw_led1_groups[] = {
"gpio7",
};
static const char * const inet_led_groups[] = {
"gpio8",
};
static const char * const spi_cs2_groups[] = {
"gpio9",
};
static const char * const spi_cs3_groups[] = {
"gpio10",
};
static const char * const ntr_pulse_groups[] = {
"gpio11",
};
static const char * const uart1_scts_groups[] = {
"gpio12",
};
static const char * const uart1_srts_groups[] = {
"gpio13",
};
static const char * const uart1_sdin_groups[] = {
"gpio14",
};
static const char * const uart1_sdout_groups[] = {
"gpio15",
};
static const char * const adsl_spi_miso_groups[] = {
"gpio16",
};
static const char * const adsl_spi_mosi_groups[] = {
"gpio17",
};
static const char * const adsl_spi_clk_groups[] = {
"gpio18",
};
static const char * const adsl_spi_cs_groups[] = {
"gpio19",
};
static const char * const ephy0_led_groups[] = {
"gpio20",
};
static const char * const ephy1_led_groups[] = {
"gpio21",
};
static const char * const ephy2_led_groups[] = {
"gpio22",
};
static const char * const ephy3_led_groups[] = {
"gpio23",
};
static const char * const ext_irq0_groups[] = {
"gpio24",
};
static const char * const ext_irq1_groups[] = {
"gpio25",
};
static const char * const ext_irq2_groups[] = {
"gpio26",
};
static const char * const ext_irq3_groups[] = {
"gpio27",
};
static const char * const wifi_groups[] = {
"gpio32",
"gpio33",
"gpio34",
"gpio35",
"gpio36",
"gpio37",
"gpio38",
"gpio39",
"gpio40",
"gpio41",
"gpio42",
"gpio43",
"gpio44",
"gpio45",
"gpio46",
"gpio47",
};
static const char * const nand_groups[] = {
"nand_grp",
};
#define BCM6362_LED_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_LEDCTRL, \
}
#define BCM6362_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_MODE, \
}
#define BCM6362_CTRL_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_CTRL, \
}
#define BCM6362_BASEMODE_FUN(n, mask) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_BASEMODE, \
.basemode_mask = (mask), \
}
static const struct bcm6362_function bcm6362_funcs[] = {
BCM6362_LED_FUN(led),
BCM6362_MODE_FUN(usb_device_led),
BCM6362_MODE_FUN(sys_irq),
BCM6362_MODE_FUN(serial_led_clk),
BCM6362_MODE_FUN(serial_led_data),
BCM6362_MODE_FUN(robosw_led_data),
BCM6362_MODE_FUN(robosw_led_clk),
BCM6362_MODE_FUN(robosw_led0),
BCM6362_MODE_FUN(robosw_led1),
BCM6362_MODE_FUN(inet_led),
BCM6362_MODE_FUN(spi_cs2),
BCM6362_MODE_FUN(spi_cs3),
BCM6362_MODE_FUN(ntr_pulse),
BCM6362_MODE_FUN(uart1_scts),
BCM6362_MODE_FUN(uart1_srts),
BCM6362_MODE_FUN(uart1_sdin),
BCM6362_MODE_FUN(uart1_sdout),
BCM6362_MODE_FUN(adsl_spi_miso),
BCM6362_MODE_FUN(adsl_spi_mosi),
BCM6362_MODE_FUN(adsl_spi_clk),
BCM6362_MODE_FUN(adsl_spi_cs),
BCM6362_MODE_FUN(ephy0_led),
BCM6362_MODE_FUN(ephy1_led),
BCM6362_MODE_FUN(ephy2_led),
BCM6362_MODE_FUN(ephy3_led),
BCM6362_MODE_FUN(ext_irq0),
BCM6362_MODE_FUN(ext_irq1),
BCM6362_MODE_FUN(ext_irq2),
BCM6362_MODE_FUN(ext_irq3),
BCM6362_CTRL_FUN(wifi),
BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),
};
static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6362_groups);
}
static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6362_groups[group].name;
}
static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *npins)
{
*pins = bcm6362_groups[group].pins;
*npins = bcm6362_groups[group].npins;
return 0;
}
static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6362_funcs);
}
static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6362_funcs[selector].name;
}
static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6362_funcs[selector].groups;
*num_groups = bcm6362_funcs[selector].num_groups;
return 0;
}
static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
{
const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];
unsigned int basemode = (uintptr_t)desc->drv_data;
unsigned int mask = bcm63xx_bank_pin(pin);
if (basemode)
regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, basemode, 0);
if (pin < BCM63XX_BANK_GPIOS) {
/* base mode 0 => gpio 1 => mux function */
regmap_update_bits(pc->regs, BCM6362_MODE_REG, mask, 0);
/* pins 0-23 might be muxed to led */
if (pin < BCM6362_NUM_LEDS)
regmap_update_bits(pc->regs, BCM6362_LED_REG, mask, 0);
} else {
/* ctrl reg 0 => wifi function 1 => gpio */
regmap_update_bits(pc->regs, BCM6362_CTRL_REG, mask, mask);
}
}
static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct pingroup *pg = &bcm6362_groups[group];
const struct bcm6362_function *f = &bcm6362_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->npins; i++)
bcm6362_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
case BCM6362_LEDCTRL:
reg = BCM6362_LED_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM6362_MODE:
reg = BCM6362_MODE_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM6362_CTRL:
reg = BCM6362_CTRL_REG;
mask = BIT(pg->pins[0]);
val = 0;
break;
case BCM6362_BASEMODE:
reg = BCM6362_BASEMODE_REG;
mask = f->basemode_mask;
val = f->basemode_mask;
break;
default:
WARN_ON(1);
return -EINVAL;
}
regmap_update_bits(pc->regs, reg, mask, val);
return 0;
}
static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm6362_set_gpio(pc, offset);
return 0;
}
static const struct pinctrl_ops bcm6362_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6362_pinctrl_get_group_name,
.get_group_pins = bcm6362_pinctrl_get_group_pins,
.get_groups_count = bcm6362_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm6362_pmx_ops = {
.get_function_groups = bcm6362_pinctrl_get_groups,
.get_function_name = bcm6362_pinctrl_get_func_name,
.get_functions_count = bcm6362_pinctrl_get_func_count,
.gpio_request_enable = bcm6362_gpio_request_enable,
.set_mux = bcm6362_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6362_soc = {
.ngpios = BCM6362_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6362_pins),
.pctl_ops = &bcm6362_pctl_ops,
.pins = bcm6362_pins,
.pmx_ops = &bcm6362_pmx_ops,
};
static int bcm6362_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6362_soc, NULL);
}
static const struct of_device_id bcm6362_pinctrl_match[] = {
{ .compatible = "brcm,bcm6362-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6362_pinctrl_driver = {
.probe = bcm6362_pinctrl_probe,
.driver = {
.name = "bcm6362-pinctrl",
.of_match_table = bcm6362_pinctrl_match,
},
};
builtin_platform_driver(bcm6362_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm6362.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6328 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <[email protected]>
* Copyright (C) 2016 Jonas Gorski <[email protected]>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6328_NUM_GPIOS 32
#define BCM6328_MODE_REG 0x18
#define BCM6328_MUX_HI_REG 0x1c
#define BCM6328_MUX_LO_REG 0x20
#define BCM6328_MUX_OTHER_REG 0x24
#define BCM6328_MUX_MASK GENMASK(1, 0)
struct bcm6328_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned mode_val:1;
unsigned mux_val:2;
};
static const unsigned int bcm6328_mux[] = {
BCM6328_MUX_LO_REG,
BCM6328_MUX_HI_REG,
BCM6328_MUX_OTHER_REG
};
static const struct pinctrl_pin_desc bcm6328_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
/*
* No idea where they really are; so let's put them according
* to their mux offsets.
*/
PINCTRL_PIN(36, "hsspi_cs1"),
PINCTRL_PIN(38, "usb_p2"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned hsspi_cs1_pins[] = { 36 };
static unsigned usb_port1_pins[] = { 38 };
static struct pingroup bcm6328_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(hsspi_cs1),
BCM_PIN_GROUP(usb_port1),
};
/* GPIO_MODE */
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
/* PINMUX_SEL */
static const char * const serial_led_data_groups[] = {
"gpio6",
};
static const char * const serial_led_clk_groups[] = {
"gpio7",
};
static const char * const inet_act_led_groups[] = {
"gpio11",
};
static const char * const pcie_clkreq_groups[] = {
"gpio16",
};
static const char * const ephy0_act_led_groups[] = {
"gpio25",
};
static const char * const ephy1_act_led_groups[] = {
"gpio26",
};
static const char * const ephy2_act_led_groups[] = {
"gpio27",
};
static const char * const ephy3_act_led_groups[] = {
"gpio28",
};
static const char * const hsspi_cs1_groups[] = {
"hsspi_cs1"
};
static const char * const usb_host_port_groups[] = {
"usb_port1",
};
static const char * const usb_device_port_groups[] = {
"usb_port1",
};
#define BCM6328_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mode_val = 1, \
}
#define BCM6328_MUX_FUN(n, mux) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mux_val = mux, \
}
static const struct bcm6328_function bcm6328_funcs[] = {
BCM6328_MODE_FUN(led),
BCM6328_MUX_FUN(serial_led_data, 2),
BCM6328_MUX_FUN(serial_led_clk, 2),
BCM6328_MUX_FUN(inet_act_led, 1),
BCM6328_MUX_FUN(pcie_clkreq, 2),
BCM6328_MUX_FUN(ephy0_act_led, 1),
BCM6328_MUX_FUN(ephy1_act_led, 1),
BCM6328_MUX_FUN(ephy2_act_led, 1),
BCM6328_MUX_FUN(ephy3_act_led, 1),
BCM6328_MUX_FUN(hsspi_cs1, 2),
BCM6328_MUX_FUN(usb_host_port, 1),
BCM6328_MUX_FUN(usb_device_port, 2),
};
static inline unsigned int bcm6328_mux_off(unsigned int pin)
{
return bcm6328_mux[pin / 16];
}
static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6328_groups);
}
static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6328_groups[group].name;
}
static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *npins)
{
*pins = bcm6328_groups[group].pins;
*npins = bcm6328_groups[group].npins;
return 0;
}
static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6328_funcs);
}
static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6328_funcs[selector].name;
}
static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6328_funcs[selector].groups;
*num_groups = bcm6328_funcs[selector].num_groups;
return 0;
}
static void bcm6328_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,
unsigned int mode, unsigned int mux)
{
if (pin < BCM6328_NUM_GPIOS)
regmap_update_bits(pc->regs, BCM6328_MODE_REG, BIT(pin),
mode ? BIT(pin) : 0);
regmap_update_bits(pc->regs, bcm6328_mux_off(pin),
BCM6328_MUX_MASK << ((pin % 16) * 2),
mux << ((pin % 16) * 2));
}
static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct pingroup *pg = &bcm6328_groups[group];
const struct bcm6328_function *f = &bcm6328_funcs[selector];
bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
return 0;
}
static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm6328_rmw_mux(pc, offset, 0, 0);
return 0;
}
static const struct pinctrl_ops bcm6328_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6328_pinctrl_get_group_name,
.get_group_pins = bcm6328_pinctrl_get_group_pins,
.get_groups_count = bcm6328_pinctrl_get_group_count,
};
static const struct pinmux_ops bcm6328_pmx_ops = {
.get_function_groups = bcm6328_pinctrl_get_groups,
.get_function_name = bcm6328_pinctrl_get_func_name,
.get_functions_count = bcm6328_pinctrl_get_func_count,
.gpio_request_enable = bcm6328_gpio_request_enable,
.set_mux = bcm6328_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6328_soc = {
.ngpios = BCM6328_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6328_pins),
.pctl_ops = &bcm6328_pctl_ops,
.pins = bcm6328_pins,
.pmx_ops = &bcm6328_pmx_ops,
};
static int bcm6328_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6328_soc, NULL);
}
static const struct of_device_id bcm6328_pinctrl_match[] = {
{ .compatible = "brcm,bcm6328-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6328_pinctrl_driver = {
.probe = bcm6328_pinctrl_probe,
.driver = {
.name = "bcm6328-pinctrl",
.of_match_table = bcm6328_pinctrl_match,
},
};
builtin_platform_driver(bcm6328_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/bcm/pinctrl-bcm6328.c
|
/*
* Driver for the ST Microelectronics SPEAr pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* Inspired from:
* - U300 Pinctl drivers
* - Tegra Pinctl drivers
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear-pinmux"
static void muxregs_endisable(struct spear_pmx *pmx,
struct spear_muxreg *muxregs, u8 count, bool enable)
{
struct spear_muxreg *muxreg;
u32 val, temp, j;
for (j = 0; j < count; j++) {
muxreg = &muxregs[j];
val = pmx_readl(pmx, muxreg->reg);
val &= ~muxreg->mask;
if (enable)
temp = muxreg->val;
else
temp = ~muxreg->val;
val |= muxreg->mask & temp;
pmx_writel(pmx, val, muxreg->reg);
}
}
static int set_mode(struct spear_pmx *pmx, int mode)
{
struct spear_pmx_mode *pmx_mode = NULL;
int i;
u32 val;
if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
return -EINVAL;
for (i = 0; i < pmx->machdata->npmx_modes; i++) {
if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
pmx_mode = pmx->machdata->pmx_modes[i];
break;
}
}
if (!pmx_mode)
return -EINVAL;
val = pmx_readl(pmx, pmx_mode->reg);
val &= ~pmx_mode->mask;
val |= pmx_mode->val;
pmx_writel(pmx, val, pmx_mode->reg);
pmx->machdata->mode = pmx_mode->mode;
dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
pmx_mode->name ? pmx_mode->name : "no_name",
pmx_mode->reg);
return 0;
}
void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
unsigned count, u16 reg)
{
int i, j;
for (i = 0; i < count; i++)
for (j = 0; j < gpio_pingroup[i].nmuxregs; j++)
gpio_pingroup[i].muxregs[j].reg = reg;
}
void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
{
struct spear_pingroup *pgroup;
struct spear_modemux *modemux;
int i, j, group;
for (group = 0; group < machdata->ngroups; group++) {
pgroup = machdata->groups[group];
for (i = 0; i < pgroup->nmodemuxs; i++) {
modemux = &pgroup->modemuxs[i];
for (j = 0; j < modemux->nmuxregs; j++)
if (modemux->muxregs[j].reg == 0xFFFF)
modemux->muxregs[j].reg = reg;
}
}
}
static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->machdata->ngroups;
}
static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->machdata->groups[group]->name;
}
static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins, unsigned *num_pins)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
*pins = pmx->machdata->groups[group]->pins;
*num_pins = pmx->machdata->groups[group]->npins;
return 0;
}
static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned offset)
{
seq_printf(s, " " DRIVER_NAME);
}
static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
struct device_node *np;
struct property *prop;
const char *function, *group;
int ret, index = 0, count = 0;
/* calculate number of maps required */
for_each_child_of_node(np_config, np) {
ret = of_property_read_string(np, "st,function", &function);
if (ret < 0) {
of_node_put(np);
return ret;
}
ret = of_property_count_strings(np, "st,pins");
if (ret < 0) {
of_node_put(np);
return ret;
}
count += ret;
}
if (!count) {
dev_err(pmx->dev, "No child nodes passed via DT\n");
return -ENODEV;
}
*map = kcalloc(count, sizeof(**map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
for_each_child_of_node(np_config, np) {
of_property_read_string(np, "st,function", &function);
of_property_for_each_string(np, "st,pins", prop, group) {
(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[index].data.mux.group = group;
(*map)[index].data.mux.function = function;
index++;
}
}
*num_maps = count;
return 0;
}
static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops spear_pinctrl_ops = {
.get_groups_count = spear_pinctrl_get_groups_cnt,
.get_group_name = spear_pinctrl_get_group_name,
.get_group_pins = spear_pinctrl_get_group_pins,
.pin_dbg_show = spear_pinctrl_pin_dbg_show,
.dt_node_to_map = spear_pinctrl_dt_node_to_map,
.dt_free_map = spear_pinctrl_dt_free_map,
};
static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->machdata->nfunctions;
}
static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->machdata->functions[function]->name;
}
static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function, const char *const **groups,
unsigned * const ngroups)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
*groups = pmx->machdata->functions[function]->groups;
*ngroups = pmx->machdata->functions[function]->ngroups;
return 0;
}
static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
unsigned function, unsigned group, bool enable)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct spear_pingroup *pgroup;
const struct spear_modemux *modemux;
int i;
bool found = false;
pgroup = pmx->machdata->groups[group];
for (i = 0; i < pgroup->nmodemuxs; i++) {
modemux = &pgroup->modemuxs[i];
/* SoC have any modes */
if (pmx->machdata->modes_supported) {
if (!(pmx->machdata->mode & modemux->modes))
continue;
}
found = true;
muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,
enable);
}
if (!found) {
dev_err(pmx->dev, "pinmux group: %s not supported\n",
pgroup->name);
return -ENODEV;
}
return 0;
}
static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
return spear_pinctrl_endisable(pctldev, function, group, true);
}
/* gpio with pinmux */
static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
unsigned pin)
{
struct spear_gpio_pingroup *gpio_pingroup;
int i, j;
if (!pmx->machdata->gpio_pingroups)
return NULL;
for (i = 0; i < pmx->machdata->ngpio_pingroups; i++) {
gpio_pingroup = &pmx->machdata->gpio_pingroups[i];
for (j = 0; j < gpio_pingroup->npins; j++) {
if (gpio_pingroup->pins[j] == pin)
return gpio_pingroup;
}
}
return NULL;
}
static int gpio_request_endisable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool enable)
{
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
struct spear_pinctrl_machdata *machdata = pmx->machdata;
struct spear_gpio_pingroup *gpio_pingroup;
/*
* Some SoC have configuration options applicable to group of pins,
* rather than a single pin.
*/
gpio_pingroup = get_gpio_pingroup(pmx, offset);
if (gpio_pingroup)
muxregs_endisable(pmx, gpio_pingroup->muxregs,
gpio_pingroup->nmuxregs, enable);
/*
* SoC may need some extra configurations, or configurations for single
* pin
*/
if (machdata->gpio_request_endisable)
machdata->gpio_request_endisable(pmx, offset, enable);
return 0;
}
static int gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
return gpio_request_endisable(pctldev, range, offset, true);
}
static void gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
gpio_request_endisable(pctldev, range, offset, false);
}
static const struct pinmux_ops spear_pinmux_ops = {
.get_functions_count = spear_pinctrl_get_funcs_count,
.get_function_name = spear_pinctrl_get_func_name,
.get_function_groups = spear_pinctrl_get_func_groups,
.set_mux = spear_pinctrl_set_mux,
.gpio_request_enable = gpio_request_enable,
.gpio_disable_free = gpio_disable_free,
};
static struct pinctrl_desc spear_pinctrl_desc = {
.name = DRIVER_NAME,
.pctlops = &spear_pinctrl_ops,
.pmxops = &spear_pinmux_ops,
.owner = THIS_MODULE,
};
int spear_pinctrl_probe(struct platform_device *pdev,
struct spear_pinctrl_machdata *machdata)
{
struct device_node *np = pdev->dev.of_node;
struct spear_pmx *pmx;
if (!machdata)
return -ENODEV;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
pmx->regmap = device_node_to_regmap(np);
if (IS_ERR(pmx->regmap)) {
dev_err(&pdev->dev, "Init regmap failed (%pe).\n",
pmx->regmap);
return PTR_ERR(pmx->regmap);
}
pmx->dev = &pdev->dev;
pmx->machdata = machdata;
/* configure mode, if supported by SoC */
if (machdata->modes_supported) {
int mode = 0;
if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
return -EINVAL;
}
if (set_mode(pmx, mode)) {
dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
mode);
return -EINVAL;
}
}
platform_set_drvdata(pdev, pmx);
spear_pinctrl_desc.pins = machdata->pins;
spear_pinctrl_desc.npins = machdata->npins;
pmx->pctl = devm_pinctrl_register(&pdev->dev, &spear_pinctrl_desc, pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(pmx->pctl);
}
return 0;
}
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear.c
|
/*
* Driver for the ST Microelectronics SPEAr1340 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1340-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1340_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
PINCTRL_PIN(246, "PLGPIO246"),
PINCTRL_PIN(247, "PLGPIO247"),
PINCTRL_PIN(248, "PLGPIO248"),
PINCTRL_PIN(249, "PLGPIO249"),
PINCTRL_PIN(250, "PLGPIO250"),
PINCTRL_PIN(251, "PLGPIO251"),
};
/* In SPEAr1340 there are two levels of pad muxing */
/* - pads as gpio OR peripherals */
#define PAD_FUNCTION_EN_1 0x668
#define PAD_FUNCTION_EN_2 0x66C
#define PAD_FUNCTION_EN_3 0x670
#define PAD_FUNCTION_EN_4 0x674
#define PAD_FUNCTION_EN_5 0x690
#define PAD_FUNCTION_EN_6 0x694
#define PAD_FUNCTION_EN_7 0x698
#define PAD_FUNCTION_EN_8 0x69C
/* - If peripherals, then primary OR alternate peripheral */
#define PAD_SHARED_IP_EN_1 0x6A0
#define PAD_SHARED_IP_EN_2 0x6A4
/*
* Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
* registers with 32 bits each for handling gpio pads, register 8 has only 26
* relevant bits.
*/
/* macro's for making pads as gpio's */
#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE
#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF
#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF
/* macro's for making pads as peripherals */
#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE
#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000
#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000
#define I2C1_REG0_MASK 0x01080000
#define SPDIF_IN_REG0_MASK 0x00100000
#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000
#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000
#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000
#define VIP_AND_CAM3_REG0_MASK 0xFC200000
#define VIP_AND_CAM3_REG1_MASK 0x0000000F
#define VIP_REG1_MASK 0x00001EF0
#define VIP_AND_CAM2_REG1_MASK 0x007FE100
#define VIP_AND_CAM1_REG1_MASK 0xFF800000
#define VIP_AND_CAM1_REG2_MASK 0x00000003
#define VIP_AND_CAM0_REG2_MASK 0x00001FFC
#define SMI_REG2_MASK 0x0021E000
#define SSP0_REG2_MASK 0x001E0000
#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000
#define UART0_REG2_MASK 0x01800000
#define UART1_REG2_MASK 0x06000000
#define I2S_IN_REG2_MASK 0xF8000000
#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE
#define I2S_OUT_REG3_MASK 0x000001EF
#define I2S_IN_REG3_MASK 0x00000010
#define GMAC_REG3_MASK 0xFFFFFE00
#define GMAC_REG4_MASK 0x0000001F
#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20
#define SSP0_CS3_REG4_MASK 0x00000020
#define I2C0_REG4_MASK 0x000000C0
#define CEC0_REG4_MASK 0x00000100
#define CEC1_REG4_MASK 0x00000200
#define SPDIF_OUT_REG4_MASK 0x00000400
#define CLCD_REG4_MASK 0x7FFFF800
#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000
#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF
#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001
#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE
#define MCIF_REG6_MASK 0xF8C00000
#define MCIF_REG7_MASK 0x000043FF
#define FSMC_8BIT_REG7_MASK 0x07FFBC00
/* other registers */
#define PERIP_CFG 0x42C
/* PERIP_CFG register masks */
#define SSP_CS_CTL_HW 0
#define SSP_CS_CTL_SW 1
#define SSP_CS_CTL_MASK 1
#define SSP_CS_CTL_SHIFT 21
#define SSP_CS_VAL_MASK 1
#define SSP_CS_VAL_SHIFT 20
#define SSP_CS_SEL_CS0 0
#define SSP_CS_SEL_CS1 1
#define SSP_CS_SEL_CS2 2
#define SSP_CS_SEL_MASK 3
#define SSP_CS_SEL_SHIFT 18
#define I2S_CHNL_2_0 (0)
#define I2S_CHNL_3_1 (1)
#define I2S_CHNL_5_1 (2)
#define I2S_CHNL_7_1 (3)
#define I2S_CHNL_PLAY_SHIFT (4)
#define I2S_CHNL_PLAY_MASK (3 << 4)
#define I2S_CHNL_REC_SHIFT (6)
#define I2S_CHNL_REC_MASK (3 << 6)
#define SPDIF_OUT_ENB_MASK (1 << 2)
#define SPDIF_OUT_ENB_SHIFT 2
#define MCIF_SEL_SD 1
#define MCIF_SEL_CF 2
#define MCIF_SEL_XD 3
#define MCIF_SEL_MASK 3
#define MCIF_SEL_SHIFT 0
#define GMAC_CLK_CFG 0x248
#define GMAC_PHY_IF_GMII_VAL (0 << 3)
#define GMAC_PHY_IF_RGMII_VAL (1 << 3)
#define GMAC_PHY_IF_SGMII_VAL (2 << 3)
#define GMAC_PHY_IF_RMII_VAL (4 << 3)
#define GMAC_PHY_IF_SEL_MASK (7 << 3)
#define GMAC_PHY_INPUT_ENB_VAL 0
#define GMAC_PHY_SYNT_ENB_VAL 1
#define GMAC_PHY_CLK_MASK 1
#define GMAC_PHY_CLK_SHIFT 2
#define GMAC_PHY_125M_PAD_VAL 0
#define GMAC_PHY_PLL2_VAL 1
#define GMAC_PHY_OSC3_VAL 2
#define GMAC_PHY_INPUT_CLK_MASK 3
#define GMAC_PHY_INPUT_CLK_SHIFT 0
#define PCIE_SATA_CFG 0x424
/* PCIE CFG MASks */
#define PCIE_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE_CFG_POWERUP_RESET (1 << 10)
#define PCIE_CFG_CORE_CLK_EN (1 << 9)
#define PCIE_CFG_AUX_CLK_EN (1 << 8)
#define SATA_CFG_TX_CLK_EN (1 << 4)
#define SATA_CFG_RX_CLK_EN (1 << 3)
#define SATA_CFG_POWERUP_RESET (1 << 2)
#define SATA_CFG_PM_CLK_EN (1 << 1)
#define PCIE_SATA_SEL_PCIE (0)
#define PCIE_SATA_SEL_SATA (1)
#define SATA_PCIE_CFG_MASK 0xF1F
#define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
PCIE_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
SATA_CFG_TX_CLK_EN)
/* Macro's for second level of pmx - pads as primary OR alternate peripheral */
/* Write 0 to enable FSMC_16_BIT */
#define KBD_ROW_COL_MASK (1 << 0)
/* Write 0 to enable UART0_ENH */
#define GPT_MASK (1 << 1) /* Only clk & cpt */
/* Write 0 to enable PWM1 */
#define KBD_COL5_MASK (1 << 2)
/* Write 0 to enable PWM2 */
#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */
/* Write 0 to enable PWM3 */
#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */
/* Write 0 to enable PWM0 */
#define SSP0_CS1_MASK (1 << 5)
/* Write 0 to enable VIP */
#define CAM3_MASK (1 << 6)
/* Write 0 to enable VIP */
#define CAM2_MASK (1 << 7)
/* Write 0 to enable VIP */
#define CAM1_MASK (1 << 8)
/* Write 0 to enable VIP */
#define CAM0_MASK (1 << 9)
/* Write 0 to enable TS */
#define SSP0_CS2_MASK (1 << 10)
/* Write 0 to enable FSMC PNOR */
#define MCIF_MASK (1 << 11)
/* Write 0 to enable CLCD */
#define ARM_TRACE_MASK (1 << 12)
/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */
#define MIPHY_DBG_MASK (1 << 13)
/*
* Pad multiplexing for making all pads as gpio's. This is done to override the
* values passed from bootloader and start from scratch.
*/
static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };
static struct spear_muxreg pads_as_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PADS_AS_GPIO_REG0_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = PADS_AS_GPIO_REGS_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_8,
.mask = PADS_AS_GPIO_REG7_MASK,
.val = 0x0,
},
};
static struct spear_modemux pads_as_gpio_modemux[] = {
{
.muxregs = pads_as_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg),
},
};
static struct spear_pingroup pads_as_gpio_pingroup = {
.name = "pads_as_gpio_grp",
.pins = pads_as_gpio_pins,
.npins = ARRAY_SIZE(pads_as_gpio_pins),
.modemuxs = pads_as_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux),
};
static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" };
static struct spear_function pads_as_gpio_function = {
.name = "pads_as_gpio",
.groups = pads_as_gpio_grps,
.ngroups = ARRAY_SIZE(pads_as_gpio_grps),
};
/* Pad multiplexing for fsmc_8bit device */
static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240,
241, 242, 243, 244, 245, 246, 247, 248, 249 };
static struct spear_muxreg fsmc_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_8,
.mask = FSMC_8BIT_REG7_MASK,
.val = FSMC_8BIT_REG7_MASK,
}
};
static struct spear_modemux fsmc_8bit_modemux[] = {
{
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
},
};
static struct spear_pingroup fsmc_8bit_pingroup = {
.name = "fsmc_8bit_grp",
.pins = fsmc_8bit_pins,
.npins = ARRAY_SIZE(fsmc_8bit_pins),
.modemuxs = fsmc_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
};
/* Pad multiplexing for fsmc_16bit device */
static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
static struct spear_muxreg fsmc_16bit_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux fsmc_16bit_modemux[] = {
{
.muxregs = fsmc_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
},
};
static struct spear_pingroup fsmc_16bit_pingroup = {
.name = "fsmc_16bit_grp",
.pins = fsmc_16bit_pins,
.npins = ARRAY_SIZE(fsmc_16bit_pins),
.modemuxs = fsmc_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
};
/* pad multiplexing for fsmc_pnor device */
static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198,
199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
215, 216, 217 };
static struct spear_muxreg fsmc_pnor_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MCIF_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
.val = FSMC_PNOR_AND_MCIF_REG6_MASK,
},
};
static struct spear_modemux fsmc_pnor_modemux[] = {
{
.muxregs = fsmc_pnor_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg),
},
};
static struct spear_pingroup fsmc_pnor_pingroup = {
.name = "fsmc_pnor_grp",
.pins = fsmc_pnor_pins,
.npins = ARRAY_SIZE(fsmc_pnor_pins),
.modemuxs = fsmc_pnor_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp",
"fsmc_pnor_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* pad multiplexing for keyboard rows-cols device */
static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10 };
static struct spear_muxreg keyboard_row_col_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_ROW_COL_MASK,
.val = KBD_ROW_COL_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
.val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
},
};
static struct spear_modemux keyboard_row_col_modemux[] = {
{
.muxregs = keyboard_row_col_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg),
},
};
static struct spear_pingroup keyboard_row_col_pingroup = {
.name = "keyboard_row_col_grp",
.pins = keyboard_row_col_pins,
.npins = ARRAY_SIZE(keyboard_row_col_pins),
.modemuxs = keyboard_row_col_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux),
};
/* pad multiplexing for keyboard col5 device */
static const unsigned keyboard_col5_pins[] = { 17 };
static struct spear_muxreg keyboard_col5_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = KBD_COL5_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux keyboard_col5_modemux[] = {
{
.muxregs = keyboard_col5_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg),
},
};
static struct spear_pingroup keyboard_col5_pingroup = {
.name = "keyboard_col5_grp",
.pins = keyboard_col5_pins,
.npins = ARRAY_SIZE(keyboard_col5_pins),
.modemuxs = keyboard_col5_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_row_col_grp",
"keyboard_col5_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* pad multiplexing for spdif_in device */
static const unsigned spdif_in_pins[] = { 19 };
static struct spear_muxreg spdif_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = SPDIF_IN_REG0_MASK,
.val = SPDIF_IN_REG0_MASK,
},
};
static struct spear_modemux spdif_in_modemux[] = {
{
.muxregs = spdif_in_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_in_muxreg),
},
};
static struct spear_pingroup spdif_in_pingroup = {
.name = "spdif_in_grp",
.pins = spdif_in_pins,
.npins = ARRAY_SIZE(spdif_in_pins),
.modemuxs = spdif_in_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_in_modemux),
};
static const char *const spdif_in_grps[] = { "spdif_in_grp" };
static struct spear_function spdif_in_function = {
.name = "spdif_in",
.groups = spdif_in_grps,
.ngroups = ARRAY_SIZE(spdif_in_grps),
};
/* pad multiplexing for spdif_out device */
static const unsigned spdif_out_pins[] = { 137 };
static struct spear_muxreg spdif_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SPDIF_OUT_REG4_MASK,
.val = SPDIF_OUT_REG4_MASK,
}, {
.reg = PERIP_CFG,
.mask = SPDIF_OUT_ENB_MASK,
.val = SPDIF_OUT_ENB_MASK,
}
};
static struct spear_modemux spdif_out_modemux[] = {
{
.muxregs = spdif_out_muxreg,
.nmuxregs = ARRAY_SIZE(spdif_out_muxreg),
},
};
static struct spear_pingroup spdif_out_pingroup = {
.name = "spdif_out_grp",
.pins = spdif_out_pins,
.npins = ARRAY_SIZE(spdif_out_pins),
.modemuxs = spdif_out_modemux,
.nmodemuxs = ARRAY_SIZE(spdif_out_modemux),
};
static const char *const spdif_out_grps[] = { "spdif_out_grp" };
static struct spear_function spdif_out_function = {
.name = "spdif_out",
.groups = spdif_out_grps,
.ngroups = ARRAY_SIZE(spdif_out_grps),
};
/* pad multiplexing for gpt_0_1 device */
static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 };
static struct spear_muxreg gpt_0_1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
.val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK |
PWM2_AND_GPT0_TMR0_CPT_REG0_MASK |
PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux gpt_0_1_modemux[] = {
{
.muxregs = gpt_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg),
},
};
static struct spear_pingroup gpt_0_1_pingroup = {
.name = "gpt_0_1_grp",
.pins = gpt_0_1_pins,
.npins = ARRAY_SIZE(gpt_0_1_pins),
.modemuxs = gpt_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux),
};
static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" };
static struct spear_function gpt_0_1_function = {
.name = "gpt_0_1",
.groups = gpt_0_1_grps,
.ngroups = ARRAY_SIZE(gpt_0_1_grps),
};
/* pad multiplexing for pwm0 device */
static const unsigned pwm0_pins[] = { 24 };
static struct spear_muxreg pwm0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux pwm0_modemux[] = {
{
.muxregs = pwm0_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_muxreg),
},
};
static struct spear_pingroup pwm0_pingroup = {
.name = "pwm0_grp",
.pins = pwm0_pins,
.npins = ARRAY_SIZE(pwm0_pins),
.modemuxs = pwm0_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_modemux),
};
/* pad multiplexing for pwm1 device */
static const unsigned pwm1_pins[] = { 17 };
static struct spear_muxreg pwm1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = KBD_COL5_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM1_AND_KBD_COL5_REG0_MASK,
.val = PWM1_AND_KBD_COL5_REG0_MASK,
},
};
static struct spear_modemux pwm1_modemux[] = {
{
.muxregs = pwm1_muxreg,
.nmuxregs = ARRAY_SIZE(pwm1_muxreg),
},
};
static struct spear_pingroup pwm1_pingroup = {
.name = "pwm1_grp",
.pins = pwm1_pins,
.npins = ARRAY_SIZE(pwm1_pins),
.modemuxs = pwm1_modemux,
.nmodemuxs = ARRAY_SIZE(pwm1_modemux),
};
/* pad multiplexing for pwm2 device */
static const unsigned pwm2_pins[] = { 21 };
static struct spear_muxreg pwm2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR0_CPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
.val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
},
};
static struct spear_modemux pwm2_modemux[] = {
{
.muxregs = pwm2_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_muxreg),
},
};
static struct spear_pingroup pwm2_pingroup = {
.name = "pwm2_grp",
.pins = pwm2_pins,
.npins = ARRAY_SIZE(pwm2_pins),
.modemuxs = pwm2_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_modemux),
};
/* pad multiplexing for pwm3 device */
static const unsigned pwm3_pins[] = { 22 };
static struct spear_muxreg pwm3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT0_TMR1_CLK_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
.val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
},
};
static struct spear_modemux pwm3_modemux[] = {
{
.muxregs = pwm3_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
},
};
static struct spear_pingroup pwm3_pingroup = {
.name = "pwm3_grp",
.pins = pwm3_pins,
.npins = ARRAY_SIZE(pwm3_pins),
.modemuxs = pwm3_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_modemux),
};
static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
"pwm3_grp" };
static struct spear_function pwm_function = {
.name = "pwm",
.groups = pwm_grps,
.ngroups = ARRAY_SIZE(pwm_grps),
};
/* pad multiplexing for vip_mux device */
static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 };
static struct spear_muxreg vip_mux_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_REG1_MASK,
.val = VIP_REG1_MASK,
},
};
static struct spear_modemux vip_mux_modemux[] = {
{
.muxregs = vip_mux_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_muxreg),
},
};
static struct spear_pingroup vip_mux_pingroup = {
.name = "vip_mux_grp",
.pins = vip_mux_pins,
.npins = ARRAY_SIZE(vip_mux_pins),
.modemuxs = vip_mux_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_modemux),
};
/* pad multiplexing for vip_mux_cam0 (disables cam0) device */
static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72,
73, 74, 75 };
static struct spear_muxreg vip_mux_cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam0_modemux[] = {
{
.muxregs = vip_mux_cam0_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg),
},
};
static struct spear_pingroup vip_mux_cam0_pingroup = {
.name = "vip_mux_cam0_grp",
.pins = vip_mux_cam0_pins,
.npins = ARRAY_SIZE(vip_mux_cam0_pins),
.modemuxs = vip_mux_cam0_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux),
};
/* pad multiplexing for vip_mux_cam1 (disables cam1) device */
static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64 };
static struct spear_muxreg vip_mux_cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux vip_mux_cam1_modemux[] = {
{
.muxregs = vip_mux_cam1_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg),
},
};
static struct spear_pingroup vip_mux_cam1_pingroup = {
.name = "vip_mux_cam1_grp",
.pins = vip_mux_cam1_pins,
.npins = ARRAY_SIZE(vip_mux_cam1_pins),
.modemuxs = vip_mux_cam1_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux),
};
/* pad multiplexing for vip_mux_cam2 (disables cam2) device */
static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53 };
static struct spear_muxreg vip_mux_cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam2_modemux[] = {
{
.muxregs = vip_mux_cam2_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg),
},
};
static struct spear_pingroup vip_mux_cam2_pingroup = {
.name = "vip_mux_cam2_grp",
.pins = vip_mux_cam2_pins,
.npins = ARRAY_SIZE(vip_mux_cam2_pins),
.modemuxs = vip_mux_cam2_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux),
};
/* pad multiplexing for vip_mux_cam3 (disables cam3) device */
static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34 };
static struct spear_muxreg vip_mux_cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux vip_mux_cam3_modemux[] = {
{
.muxregs = vip_mux_cam3_muxreg,
.nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg),
},
};
static struct spear_pingroup vip_mux_cam3_pingroup = {
.name = "vip_mux_cam3_grp",
.pins = vip_mux_cam3_pins,
.npins = ARRAY_SIZE(vip_mux_cam3_pins),
.modemuxs = vip_mux_cam3_modemux,
.nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux),
};
static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" ,
"vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" };
static struct spear_function vip_function = {
.name = "vip",
.groups = vip_grps,
.ngroups = ARRAY_SIZE(vip_grps),
};
/* pad multiplexing for cam0 device */
static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75
};
static struct spear_muxreg cam0_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM0_MASK,
.val = CAM0_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM0_REG2_MASK,
.val = VIP_AND_CAM0_REG2_MASK,
},
};
static struct spear_modemux cam0_modemux[] = {
{
.muxregs = cam0_muxreg,
.nmuxregs = ARRAY_SIZE(cam0_muxreg),
},
};
static struct spear_pingroup cam0_pingroup = {
.name = "cam0_grp",
.pins = cam0_pins,
.npins = ARRAY_SIZE(cam0_pins),
.modemuxs = cam0_modemux,
.nmodemuxs = ARRAY_SIZE(cam0_modemux),
};
static const char *const cam0_grps[] = { "cam0_grp" };
static struct spear_function cam0_function = {
.name = "cam0",
.groups = cam0_grps,
.ngroups = ARRAY_SIZE(cam0_grps),
};
/* pad multiplexing for cam1 device */
static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
};
static struct spear_muxreg cam1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM1_MASK,
.val = CAM1_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM1_REG1_MASK,
.val = VIP_AND_CAM1_REG1_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = VIP_AND_CAM1_REG2_MASK,
.val = VIP_AND_CAM1_REG2_MASK,
},
};
static struct spear_modemux cam1_modemux[] = {
{
.muxregs = cam1_muxreg,
.nmuxregs = ARRAY_SIZE(cam1_muxreg),
},
};
static struct spear_pingroup cam1_pingroup = {
.name = "cam1_grp",
.pins = cam1_pins,
.npins = ARRAY_SIZE(cam1_pins),
.modemuxs = cam1_modemux,
.nmodemuxs = ARRAY_SIZE(cam1_modemux),
};
static const char *const cam1_grps[] = { "cam1_grp" };
static struct spear_function cam1_function = {
.name = "cam1",
.groups = cam1_grps,
.ngroups = ARRAY_SIZE(cam1_grps),
};
/* pad multiplexing for cam2 device */
static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53
};
static struct spear_muxreg cam2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM2_MASK,
.val = CAM2_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM2_REG1_MASK,
.val = VIP_AND_CAM2_REG1_MASK,
},
};
static struct spear_modemux cam2_modemux[] = {
{
.muxregs = cam2_muxreg,
.nmuxregs = ARRAY_SIZE(cam2_muxreg),
},
};
static struct spear_pingroup cam2_pingroup = {
.name = "cam2_grp",
.pins = cam2_pins,
.npins = ARRAY_SIZE(cam2_pins),
.modemuxs = cam2_modemux,
.nmodemuxs = ARRAY_SIZE(cam2_modemux),
};
static const char *const cam2_grps[] = { "cam2_grp" };
static struct spear_function cam2_function = {
.name = "cam2",
.groups = cam2_grps,
.ngroups = ARRAY_SIZE(cam2_grps),
};
/* pad multiplexing for cam3 device */
static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
};
static struct spear_muxreg cam3_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = CAM3_MASK,
.val = CAM3_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = VIP_AND_CAM3_REG0_MASK,
.val = VIP_AND_CAM3_REG0_MASK,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = VIP_AND_CAM3_REG1_MASK,
.val = VIP_AND_CAM3_REG1_MASK,
},
};
static struct spear_modemux cam3_modemux[] = {
{
.muxregs = cam3_muxreg,
.nmuxregs = ARRAY_SIZE(cam3_muxreg),
},
};
static struct spear_pingroup cam3_pingroup = {
.name = "cam3_grp",
.pins = cam3_pins,
.npins = ARRAY_SIZE(cam3_pins),
.modemuxs = cam3_modemux,
.nmodemuxs = ARRAY_SIZE(cam3_modemux),
};
static const char *const cam3_grps[] = { "cam3_grp" };
static struct spear_function cam3_function = {
.name = "cam3",
.groups = cam3_grps,
.ngroups = ARRAY_SIZE(cam3_grps),
};
/* pad multiplexing for smi device */
static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 };
static struct spear_muxreg smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SMI_REG2_MASK,
.val = SMI_REG2_MASK,
},
};
static struct spear_modemux smi_modemux[] = {
{
.muxregs = smi_muxreg,
.nmuxregs = ARRAY_SIZE(smi_muxreg),
},
};
static struct spear_pingroup smi_pingroup = {
.name = "smi_grp",
.pins = smi_pins,
.npins = ARRAY_SIZE(smi_pins),
.modemuxs = smi_modemux,
.nmodemuxs = ARRAY_SIZE(smi_modemux),
};
static const char *const smi_grps[] = { "smi_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 80, 81, 82, 83 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = SSP0_REG2_MASK,
.val = SSP0_REG2_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* pad multiplexing for ssp0_cs1 device */
static const unsigned ssp0_cs1_pins[] = { 24 };
static struct spear_muxreg ssp0_cs1_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS1_MASK,
.val = SSP0_CS1_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PWM0_AND_SSP0_CS1_REG0_MASK,
.val = PWM0_AND_SSP0_CS1_REG0_MASK,
},
};
static struct spear_modemux ssp0_cs1_modemux[] = {
{
.muxregs = ssp0_cs1_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_pingroup = {
.name = "ssp0_cs1_grp",
.pins = ssp0_cs1_pins,
.npins = ARRAY_SIZE(ssp0_cs1_pins),
.modemuxs = ssp0_cs1_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux),
};
/* pad multiplexing for ssp0_cs2 device */
static const unsigned ssp0_cs2_pins[] = { 85 };
static struct spear_muxreg ssp0_cs2_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = SSP0_CS2_MASK,
.val = SSP0_CS2_MASK,
}, {
.reg = PAD_FUNCTION_EN_3,
.mask = TS_AND_SSP0_CS2_REG2_MASK,
.val = TS_AND_SSP0_CS2_REG2_MASK,
},
};
static struct spear_modemux ssp0_cs2_modemux[] = {
{
.muxregs = ssp0_cs2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg),
},
};
static struct spear_pingroup ssp0_cs2_pingroup = {
.name = "ssp0_cs2_grp",
.pins = ssp0_cs2_pins,
.npins = ARRAY_SIZE(ssp0_cs2_pins),
.modemuxs = ssp0_cs2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux),
};
/* pad multiplexing for ssp0_cs3 device */
static const unsigned ssp0_cs3_pins[] = { 132 };
static struct spear_muxreg ssp0_cs3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = SSP0_CS3_REG4_MASK,
.val = SSP0_CS3_REG4_MASK,
},
};
static struct spear_modemux ssp0_cs3_modemux[] = {
{
.muxregs = ssp0_cs3_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg),
},
};
static struct spear_pingroup ssp0_cs3_pingroup = {
.name = "ssp0_cs3_grp",
.pins = ssp0_cs3_pins,
.npins = ARRAY_SIZE(ssp0_cs3_pins),
.modemuxs = ssp0_cs3_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs2_grp", "ssp0_cs3_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 86, 87 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART0_REG2_MASK,
.val = UART0_REG2_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* pad multiplexing for uart0_enh device */
static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 };
static struct spear_muxreg uart0_enh_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = GPT_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = UART0_ENH_AND_GPT_REG0_MASK,
.val = UART0_ENH_AND_GPT_REG0_MASK,
},
};
static struct spear_modemux uart0_enh_modemux[] = {
{
.muxregs = uart0_enh_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_enh_muxreg),
},
};
static struct spear_pingroup uart0_enh_pingroup = {
.name = "uart0_enh_grp",
.pins = uart0_enh_pins,
.npins = ARRAY_SIZE(uart0_enh_pins),
.modemuxs = uart0_enh_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_enh_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* pad multiplexing for uart1 device */
static const unsigned uart1_pins[] = { 88, 89 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = UART1_REG2_MASK,
.val = UART1_REG2_MASK,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* pad multiplexing for i2s_in device */
static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 };
static struct spear_muxreg i2s_in_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_3,
.mask = I2S_IN_REG2_MASK,
.val = I2S_IN_REG2_MASK,
}, {
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_IN_REG3_MASK,
.val = I2S_IN_REG3_MASK,
},
};
static struct spear_modemux i2s_in_modemux[] = {
{
.muxregs = i2s_in_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_in_muxreg),
},
};
static struct spear_pingroup i2s_in_pingroup = {
.name = "i2s_in_grp",
.pins = i2s_in_pins,
.npins = ARRAY_SIZE(i2s_in_pins),
.modemuxs = i2s_in_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_in_modemux),
};
/* pad multiplexing for i2s_out device */
static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 };
static struct spear_muxreg i2s_out_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_4,
.mask = I2S_OUT_REG3_MASK,
.val = I2S_OUT_REG3_MASK,
},
};
static struct spear_modemux i2s_out_modemux[] = {
{
.muxregs = i2s_out_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_out_muxreg),
},
};
static struct spear_pingroup i2s_out_pingroup = {
.name = "i2s_out_grp",
.pins = i2s_out_pins,
.npins = ARRAY_SIZE(i2s_out_pins),
.modemuxs = i2s_out_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_out_modemux),
};
static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* pad multiplexing for gmac device */
static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
126, 127, 128, 129, 130, 131 };
#define GMAC_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_4, \
.mask = GMAC_REG3_MASK, \
.val = GMAC_REG3_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_5, \
.mask = GMAC_REG4_MASK, \
.val = GMAC_REG4_MASK, \
}
/* pad multiplexing for gmii device */
static struct spear_muxreg gmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_GMII_VAL,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
/* pad multiplexing for rgmii device */
static struct spear_muxreg rgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RGMII_VAL,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
/* pad multiplexing for rmii device */
static struct spear_muxreg rmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_RMII_VAL,
},
};
static struct spear_modemux rmii_modemux[] = {
{
.muxregs = rmii_muxreg,
.nmuxregs = ARRAY_SIZE(rmii_muxreg),
},
};
static struct spear_pingroup rmii_pingroup = {
.name = "rmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = rmii_modemux,
.nmodemuxs = ARRAY_SIZE(rmii_modemux),
};
/* pad multiplexing for sgmii device */
static struct spear_muxreg sgmii_muxreg[] = {
GMAC_MUXREG,
{
.reg = GMAC_CLK_CFG,
.mask = GMAC_PHY_IF_SEL_MASK,
.val = GMAC_PHY_IF_SGMII_VAL,
},
};
static struct spear_modemux sgmii_modemux[] = {
{
.muxregs = sgmii_muxreg,
.nmuxregs = ARRAY_SIZE(sgmii_muxreg),
},
};
static struct spear_pingroup sgmii_pingroup = {
.name = "sgmii_grp",
.pins = gmac_pins,
.npins = ARRAY_SIZE(gmac_pins),
.modemuxs = sgmii_modemux,
.nmodemuxs = ARRAY_SIZE(sgmii_modemux),
};
static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp",
"sgmii_grp" };
static struct spear_function gmac_function = {
.name = "gmac",
.groups = gmac_grps,
.ngroups = ARRAY_SIZE(gmac_grps),
};
/* pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 133, 134 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = I2C0_REG4_MASK,
.val = I2C0_REG4_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* pad multiplexing for i2c1 device */
static const unsigned i2c1_pins[] = { 18, 23 };
static struct spear_muxreg i2c1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = I2C1_REG0_MASK,
.val = I2C1_REG0_MASK,
},
};
static struct spear_modemux i2c1_modemux[] = {
{
.muxregs = i2c1_muxreg,
.nmuxregs = ARRAY_SIZE(i2c1_muxreg),
},
};
static struct spear_pingroup i2c1_pingroup = {
.name = "i2c1_grp",
.pins = i2c1_pins,
.npins = ARRAY_SIZE(i2c1_pins),
.modemuxs = i2c1_modemux,
.nmodemuxs = ARRAY_SIZE(i2c1_modemux),
};
static const char *const i2c1_grps[] = { "i2c1_grp" };
static struct spear_function i2c1_function = {
.name = "i2c1",
.groups = i2c1_grps,
.ngroups = ARRAY_SIZE(i2c1_grps),
};
/* pad multiplexing for cec0 device */
static const unsigned cec0_pins[] = { 135 };
static struct spear_muxreg cec0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC0_REG4_MASK,
.val = CEC0_REG4_MASK,
},
};
static struct spear_modemux cec0_modemux[] = {
{
.muxregs = cec0_muxreg,
.nmuxregs = ARRAY_SIZE(cec0_muxreg),
},
};
static struct spear_pingroup cec0_pingroup = {
.name = "cec0_grp",
.pins = cec0_pins,
.npins = ARRAY_SIZE(cec0_pins),
.modemuxs = cec0_modemux,
.nmodemuxs = ARRAY_SIZE(cec0_modemux),
};
static const char *const cec0_grps[] = { "cec0_grp" };
static struct spear_function cec0_function = {
.name = "cec0",
.groups = cec0_grps,
.ngroups = ARRAY_SIZE(cec0_grps),
};
/* pad multiplexing for cec1 device */
static const unsigned cec1_pins[] = { 136 };
static struct spear_muxreg cec1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_5,
.mask = CEC1_REG4_MASK,
.val = CEC1_REG4_MASK,
},
};
static struct spear_modemux cec1_modemux[] = {
{
.muxregs = cec1_muxreg,
.nmuxregs = ARRAY_SIZE(cec1_muxreg),
},
};
static struct spear_pingroup cec1_pingroup = {
.name = "cec1_grp",
.pins = cec1_pins,
.npins = ARRAY_SIZE(cec1_pins),
.modemuxs = cec1_modemux,
.nmodemuxs = ARRAY_SIZE(cec1_modemux),
};
static const char *const cec1_grps[] = { "cec1_grp" };
static struct spear_function cec1_function = {
.name = "cec1",
.groups = cec1_grps,
.ngroups = ARRAY_SIZE(cec1_grps),
};
/* pad multiplexing for mcif devices */
static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200,
201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 237 };
#define MCIF_MUXREG \
{ \
.reg = PAD_SHARED_IP_EN_1, \
.mask = MCIF_MASK, \
.val = MCIF_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_7, \
.mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
.val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_8, \
.mask = MCIF_REG7_MASK, \
.val = MCIF_REG7_MASK, \
}
/* Pad multiplexing for sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* Pad multiplexing for cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* Pad multiplexing for xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159,
160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187,
188, 189, 190, 191 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
/* Disable cld runtime to save panel damage */
static struct spear_muxreg clcd_sleep_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = 0x0,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = 0x0,
},
};
static struct spear_modemux clcd_sleep_modemux[] = {
{
.muxregs = clcd_sleep_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),
},
};
static struct spear_pingroup clcd_sleep_pingroup = {
.name = "clcd_sleep_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_sleep_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* pad multiplexing for arm_trace device */
static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164,
165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178,
179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192,
193, 194, 195, 196, 197, 198, 199, 200 };
static struct spear_muxreg arm_trace_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = ARM_TRACE_MASK,
.val = ARM_TRACE_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = CLCD_AND_ARM_TRACE_REG4_MASK,
.val = CLCD_AND_ARM_TRACE_REG4_MASK,
}, {
.reg = PAD_FUNCTION_EN_6,
.mask = CLCD_AND_ARM_TRACE_REG5_MASK,
.val = CLCD_AND_ARM_TRACE_REG5_MASK,
}, {
.reg = PAD_FUNCTION_EN_7,
.mask = CLCD_AND_ARM_TRACE_REG6_MASK,
.val = CLCD_AND_ARM_TRACE_REG6_MASK,
},
};
static struct spear_modemux arm_trace_modemux[] = {
{
.muxregs = arm_trace_muxreg,
.nmuxregs = ARRAY_SIZE(arm_trace_muxreg),
},
};
static struct spear_pingroup arm_trace_pingroup = {
.name = "arm_trace_grp",
.pins = arm_trace_pins,
.npins = ARRAY_SIZE(arm_trace_pins),
.modemuxs = arm_trace_modemux,
.nmodemuxs = ARRAY_SIZE(arm_trace_modemux),
};
static const char *const arm_trace_grps[] = { "arm_trace_grp" };
static struct spear_function arm_trace_function = {
.name = "arm_trace",
.groups = arm_trace_grps,
.ngroups = ARRAY_SIZE(arm_trace_grps),
};
/* pad multiplexing for miphy_dbg device */
static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103,
132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
148, 149, 150, 151, 152, 153, 154, 155, 156, 157 };
static struct spear_muxreg miphy_dbg_muxreg[] = {
{
.reg = PAD_SHARED_IP_EN_1,
.mask = MIPHY_DBG_MASK,
.val = MIPHY_DBG_MASK,
}, {
.reg = PAD_FUNCTION_EN_5,
.mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
.val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
},
};
static struct spear_modemux miphy_dbg_modemux[] = {
{
.muxregs = miphy_dbg_muxreg,
.nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg),
},
};
static struct spear_pingroup miphy_dbg_pingroup = {
.name = "miphy_dbg_grp",
.pins = miphy_dbg_pins,
.npins = ARRAY_SIZE(miphy_dbg_pins),
.modemuxs = miphy_dbg_modemux,
.nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux),
};
static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" };
static struct spear_function miphy_dbg_function = {
.name = "miphy_dbg",
.groups = miphy_dbg_grps,
.ngroups = ARRAY_SIZE(miphy_dbg_grps),
};
/* pad multiplexing for pcie device */
static const unsigned pcie_pins[] = { 250 };
static struct spear_muxreg pcie_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = PCIE_CFG_VAL,
},
};
static struct spear_modemux pcie_modemux[] = {
{
.muxregs = pcie_muxreg,
.nmuxregs = ARRAY_SIZE(pcie_muxreg),
},
};
static struct spear_pingroup pcie_pingroup = {
.name = "pcie_grp",
.pins = pcie_pins,
.npins = ARRAY_SIZE(pcie_pins),
.modemuxs = pcie_modemux,
.nmodemuxs = ARRAY_SIZE(pcie_modemux),
};
static const char *const pcie_grps[] = { "pcie_grp" };
static struct spear_function pcie_function = {
.name = "pcie",
.groups = pcie_grps,
.ngroups = ARRAY_SIZE(pcie_grps),
};
/* pad multiplexing for sata device */
static const unsigned sata_pins[] = { 250 };
static struct spear_muxreg sata_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_PCIE_CFG_MASK,
.val = SATA_CFG_VAL,
},
};
static struct spear_modemux sata_modemux[] = {
{
.muxregs = sata_muxreg,
.nmuxregs = ARRAY_SIZE(sata_muxreg),
},
};
static struct spear_pingroup sata_pingroup = {
.name = "sata_grp",
.pins = sata_pins,
.npins = ARRAY_SIZE(sata_pins),
.modemuxs = sata_modemux,
.nmodemuxs = ARRAY_SIZE(sata_modemux),
};
static const char *const sata_grps[] = { "sata_grp" };
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* pingroups */
static struct spear_pingroup *spear1340_pingroups[] = {
&pads_as_gpio_pingroup,
&fsmc_8bit_pingroup,
&fsmc_16bit_pingroup,
&fsmc_pnor_pingroup,
&keyboard_row_col_pingroup,
&keyboard_col5_pingroup,
&spdif_in_pingroup,
&spdif_out_pingroup,
&gpt_0_1_pingroup,
&pwm0_pingroup,
&pwm1_pingroup,
&pwm2_pingroup,
&pwm3_pingroup,
&vip_mux_pingroup,
&vip_mux_cam0_pingroup,
&vip_mux_cam1_pingroup,
&vip_mux_cam2_pingroup,
&vip_mux_cam3_pingroup,
&cam0_pingroup,
&cam1_pingroup,
&cam2_pingroup,
&cam3_pingroup,
&smi_pingroup,
&ssp0_pingroup,
&ssp0_cs1_pingroup,
&ssp0_cs2_pingroup,
&ssp0_cs3_pingroup,
&uart0_pingroup,
&uart0_enh_pingroup,
&uart1_pingroup,
&i2s_in_pingroup,
&i2s_out_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&rmii_pingroup,
&sgmii_pingroup,
&i2c0_pingroup,
&i2c1_pingroup,
&cec0_pingroup,
&cec1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&clcd_sleep_pingroup,
&clcd_pingroup,
&arm_trace_pingroup,
&miphy_dbg_pingroup,
&pcie_pingroup,
&sata_pingroup,
};
/* functions */
static struct spear_function *spear1340_functions[] = {
&pads_as_gpio_function,
&fsmc_function,
&keyboard_function,
&spdif_in_function,
&spdif_out_function,
&gpt_0_1_function,
&pwm_function,
&vip_function,
&cam0_function,
&cam1_function,
&cam2_function,
&cam3_function,
&smi_function,
&ssp0_function,
&uart0_function,
&uart1_function,
&i2s_function,
&gmac_function,
&i2c0_function,
&i2c1_function,
&cec0_function,
&cec1_function,
&sdhci_function,
&cf_function,
&xd_function,
&clcd_function,
&arm_trace_function,
&miphy_dbg_function,
&pcie_function,
&sata_function,
};
static void gpio_request_endisable(struct spear_pmx *pmx, int pin,
bool enable)
{
unsigned int regoffset, regindex, bitoffset;
unsigned int val;
/* pin++ as gpio configuration starts from 2nd bit of base register */
pin++;
regindex = pin / 32;
bitoffset = pin % 32;
if (regindex <= 3)
regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *);
else
regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *);
val = pmx_readl(pmx, regoffset);
if (enable)
val &= ~(0x1 << bitoffset);
else
val |= 0x1 << bitoffset;
pmx_writel(pmx, val, regoffset);
}
static struct spear_pinctrl_machdata spear1340_machdata = {
.pins = spear1340_pins,
.npins = ARRAY_SIZE(spear1340_pins),
.groups = spear1340_pingroups,
.ngroups = ARRAY_SIZE(spear1340_pingroups),
.functions = spear1340_functions,
.nfunctions = ARRAY_SIZE(spear1340_functions),
.gpio_request_endisable = gpio_request_endisable,
.modes_supported = false,
};
static const struct of_device_id spear1340_pinctrl_of_match[] = {
{
.compatible = "st,spear1340-pinmux",
},
{},
};
static int spear1340_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1340_machdata);
}
static struct platform_driver spear1340_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = spear1340_pinctrl_of_match,
},
.probe = spear1340_pinctrl_probe,
};
static int __init spear1340_pinctrl_init(void)
{
return platform_driver_register(&spear1340_pinctrl_driver);
}
arch_initcall(spear1340_pinctrl_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear1340.c
|
/*
* Driver for the ST Microelectronics SPEAr320 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear3xx.h"
#define DRIVER_NAME "spear320-pinmux"
/* addresses */
#define PMX_CONFIG_REG 0x0C
#define MODE_CONFIG_REG 0x10
#define MODE_EXT_CONFIG_REG 0x18
/* modes */
#define AUTO_NET_SMII_MODE (1 << 0)
#define AUTO_NET_MII_MODE (1 << 1)
#define AUTO_EXP_MODE (1 << 2)
#define SMALL_PRINTERS_MODE (1 << 3)
#define EXTENDED_MODE (1 << 4)
static struct spear_pmx_mode pmx_mode_auto_net_smii = {
.name = "Automation Networking SMII mode",
.mode = AUTO_NET_SMII_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x0,
};
static struct spear_pmx_mode pmx_mode_auto_net_mii = {
.name = "Automation Networking MII mode",
.mode = AUTO_NET_MII_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x1,
};
static struct spear_pmx_mode pmx_mode_auto_exp = {
.name = "Automation Expanded mode",
.mode = AUTO_EXP_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x2,
};
static struct spear_pmx_mode pmx_mode_small_printers = {
.name = "Small Printers mode",
.mode = SMALL_PRINTERS_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x3,
};
static struct spear_pmx_mode pmx_mode_extended = {
.name = "extended mode",
.mode = EXTENDED_MODE,
.reg = MODE_EXT_CONFIG_REG,
.mask = 0x00000001,
.val = 0x1,
};
static struct spear_pmx_mode *spear320_pmx_modes[] = {
&pmx_mode_auto_net_smii,
&pmx_mode_auto_net_mii,
&pmx_mode_auto_exp,
&pmx_mode_small_printers,
&pmx_mode_extended,
};
/* Extended mode registers and their offsets */
#define EXT_CTRL_REG 0x0018
#define MII_MDIO_MASK (1 << 4)
#define MII_MDIO_10_11_VAL 0
#define MII_MDIO_81_VAL (1 << 4)
#define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
#define MAC_MODE_MII 0
#define MAC_MODE_RMII 1
#define MAC_MODE_SMII 2
#define MAC_MODE_SS_SMII 3
#define MAC_MODE_MASK 0x3
#define MAC1_MODE_SHIFT 16
#define MAC2_MODE_SHIFT 18
#define IP_SEL_PAD_0_9_REG 0x00A4
#define PMX_PL_0_1_MASK (0x3F << 0)
#define PMX_UART2_PL_0_1_VAL 0x0
#define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
#define PMX_PL_2_3_MASK (0x3F << 6)
#define PMX_I2C2_PL_2_3_VAL 0x0
#define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
#define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_4_5_MASK (0x3F << 12)
#define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
#define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_5_MASK (0x7 << 15)
#define PMX_TOUCH_Y_PL_5_VAL 0x0
#define PMX_PL_6_7_MASK (0x3F << 18)
#define PMX_PL_6_MASK (0x7 << 18)
#define PMX_PL_7_MASK (0x7 << 21)
#define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_PWM_3_PL_6_VAL (0x2 << 18)
#define PMX_PWM_2_PL_7_VAL (0x2 << 21)
#define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_8_9_MASK (0x3F << 24)
#define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
#define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_10_19_REG 0x00A8
#define PMX_PL_10_11_MASK (0x3F << 0)
#define PMX_SMII_PL_10_11_VAL 0
#define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_12_MASK (0x7 << 6)
#define PMX_PWM3_PL_12_VAL 0
#define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
#define PMX_PL_13_14_MASK (0x3F << 9)
#define PMX_PL_13_MASK (0x7 << 9)
#define PMX_PL_14_MASK (0x7 << 12)
#define PMX_SSP2_PL_13_14_15_16_VAL 0
#define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
#define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
#define PMX_PWM2_PL_13_VAL (0x2 << 9)
#define PMX_PWM1_PL_14_VAL (0x2 << 12)
#define PMX_PL_15_MASK (0x7 << 15)
#define PMX_PWM0_PL_15_VAL (0x2 << 15)
#define PMX_PL_15_16_MASK (0x3F << 15)
#define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
#define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
#define PMX_PL_17_18_MASK (0x3F << 21)
#define PMX_SSP1_PL_17_18_19_20_VAL 0
#define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
#define PMX_PL_19_MASK (0x7 << 27)
#define PMX_I2C2_PL_19_VAL (0x1 << 27)
#define PMX_RMII_PL_19_VAL (0x4 << 27)
#define IP_SEL_PAD_20_29_REG 0x00AC
#define PMX_PL_20_MASK (0x7 << 0)
#define PMX_I2C2_PL_20_VAL (0x1 << 0)
#define PMX_RMII_PL_20_VAL (0x4 << 0)
#define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
#define PMX_SMII_PL_21_TO_27_VAL 0
#define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
#define PMX_PL_28_29_MASK (0x3F << 24)
#define PMX_PL_28_MASK (0x7 << 24)
#define PMX_PL_29_MASK (0x7 << 27)
#define PMX_UART1_PL_28_29_VAL 0
#define PMX_PWM_3_PL_28_VAL (0x4 << 24)
#define PMX_PWM_2_PL_29_VAL (0x4 << 27)
#define IP_SEL_PAD_30_39_REG 0x00B0
#define PMX_PL_30_31_MASK (0x3F << 0)
#define PMX_CAN1_PL_30_31_VAL (0)
#define PMX_PL_30_MASK (0x7 << 0)
#define PMX_PL_31_MASK (0x7 << 3)
#define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
#define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
#define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
#define PMX_PL_32_33_MASK (0x3F << 6)
#define PMX_CAN0_PL_32_33_VAL 0
#define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
#define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_34_MASK (0x7 << 12)
#define PMX_PWM2_PL_34_VAL 0
#define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
#define PMX_SSP2_PL_34_VAL (0x4 << 12)
#define PMX_PL_35_MASK (0x7 << 15)
#define PMX_I2S_REF_CLK_PL_35_VAL 0
#define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
#define PMX_SSP2_PL_35_VAL (0x4 << 15)
#define PMX_PL_36_MASK (0x7 << 18)
#define PMX_TOUCH_X_PL_36_VAL 0
#define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
#define PMX_SSP1_PL_36_VAL (0x4 << 18)
#define PMX_PL_37_38_MASK (0x3F << 21)
#define PMX_PWM0_1_PL_37_38_VAL 0
#define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
#define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
#define PMX_PL_39_MASK (0x7 << 27)
#define PMX_I2S_PL_39_VAL 0
#define PMX_UART4_PL_39_VAL (0x2 << 27)
#define PMX_SSP1_PL_39_VAL (0x4 << 27)
#define IP_SEL_PAD_40_49_REG 0x00B4
#define PMX_PL_40_MASK (0x7 << 0)
#define PMX_I2S_PL_40_VAL 0
#define PMX_UART4_PL_40_VAL (0x2 << 0)
#define PMX_PWM3_PL_40_VAL (0x4 << 0)
#define PMX_PL_41_42_MASK (0x3F << 3)
#define PMX_PL_41_MASK (0x7 << 3)
#define PMX_PL_42_MASK (0x7 << 6)
#define PMX_I2S_PL_41_42_VAL 0
#define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
#define PMX_PWM2_PL_41_VAL (0x4 << 3)
#define PMX_PWM1_PL_42_VAL (0x4 << 6)
#define PMX_PL_43_MASK (0x7 << 9)
#define PMX_SDHCI_PL_43_VAL 0
#define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
#define PMX_PWM0_PL_43_VAL (0x4 << 9)
#define PMX_PL_44_45_MASK (0x3F << 12)
#define PMX_SDHCI_PL_44_45_VAL 0
#define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
#define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_46_47_MASK (0x3F << 18)
#define PMX_SDHCI_PL_46_47_VAL 0
#define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_48_49_MASK (0x3F << 24)
#define PMX_SDHCI_PL_48_49_VAL 0
#define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_50_59_REG 0x00B8
#define PMX_PL_50_51_MASK (0x3F << 0)
#define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
#define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_50_MASK (0x7 << 0)
#define PMX_PL_51_MASK (0x7 << 3)
#define PMX_SDHCI_PL_50_VAL 0
#define PMX_SDHCI_CD_PL_51_VAL 0
#define PMX_PL_52_53_MASK (0x3F << 6)
#define PMX_FSMC_PL_52_53_VAL 0
#define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
#define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_54_55_56_MASK (0x1FF << 12)
#define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
#define PMX_PL_57_MASK (0x7 << 21)
#define PMX_FSMC_PL_57_VAL 0
#define PMX_PWM3_PL_57_VAL (0x4 << 21)
#define PMX_PL_58_59_MASK (0x3F << 24)
#define PMX_PL_58_MASK (0x7 << 24)
#define PMX_PL_59_MASK (0x7 << 27)
#define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_PWM2_PL_58_VAL (0x4 << 24)
#define PMX_PWM1_PL_59_VAL (0x4 << 27)
#define IP_SEL_PAD_60_69_REG 0x00BC
#define PMX_PL_60_MASK (0x7 << 0)
#define PMX_FSMC_PL_60_VAL 0
#define PMX_PWM0_PL_60_VAL (0x4 << 0)
#define PMX_PL_61_TO_64_MASK (0xFFF << 3)
#define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
#define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
#define PMX_PL_65_TO_68_MASK (0xFFF << 15)
#define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
#define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
#define PMX_PL_69_MASK (0x7 << 27)
#define PMX_CLCD_PL_69_VAL (0)
#define PMX_EMI_PL_69_VAL (0x2 << 27)
#define PMX_SPP_PL_69_VAL (0x3 << 27)
#define PMX_UART5_PL_69_VAL (0x4 << 27)
#define IP_SEL_PAD_70_79_REG 0x00C0
#define PMX_PL_70_MASK (0x7 << 0)
#define PMX_CLCD_PL_70_VAL (0)
#define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
#define PMX_SPP_PL_70_VAL (0x3 << 0)
#define PMX_UART5_PL_70_VAL (0x4 << 0)
#define PMX_PL_71_72_MASK (0x3F << 3)
#define PMX_CLCD_PL_71_72_VAL (0)
#define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
#define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
#define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
#define PMX_PL_73_MASK (0x7 << 9)
#define PMX_CLCD_PL_73_VAL (0)
#define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
#define PMX_SPP_PL_73_VAL (0x3 << 9)
#define PMX_UART3_PL_73_VAL (0x4 << 9)
#define PMX_PL_74_MASK (0x7 << 12)
#define PMX_CLCD_PL_74_VAL (0)
#define PMX_EMI_PL_74_VAL (0x2 << 12)
#define PMX_SPP_PL_74_VAL (0x3 << 12)
#define PMX_UART3_PL_74_VAL (0x4 << 12)
#define PMX_PL_75_76_MASK (0x3F << 15)
#define PMX_CLCD_PL_75_76_VAL (0)
#define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
#define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
#define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
#define PMX_PL_77_78_79_MASK (0x1FF << 21)
#define PMX_CLCD_PL_77_78_79_VAL (0)
#define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
#define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
#define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_80_89_REG 0x00C4
#define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
#define PMX_CLCD_PL_80_TO_85_VAL 0
#define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
#define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
#define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
#define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
#define PMX_PL_86_87_MASK (0x3F << 18)
#define PMX_PL_86_MASK (0x7 << 18)
#define PMX_PL_87_MASK (0x7 << 21)
#define PMX_CLCD_PL_86_87_VAL 0
#define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_PWM3_PL_86_VAL (0x4 << 18)
#define PMX_PWM2_PL_87_VAL (0x4 << 21)
#define PMX_PL_88_89_MASK (0x3F << 24)
#define PMX_CLCD_PL_88_89_VAL 0
#define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
#define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
#define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_90_99_REG 0x00C8
#define PMX_PL_90_91_MASK (0x3F << 0)
#define PMX_CLCD_PL_90_91_VAL 0
#define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
#define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
#define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
#define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_92_93_MASK (0x3F << 6)
#define PMX_CLCD_PL_92_93_VAL 0
#define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
#define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
#define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
#define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_94_95_MASK (0x3F << 12)
#define PMX_CLCD_PL_94_95_VAL 0
#define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
#define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
#define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
#define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_96_97_MASK (0x3F << 18)
#define PMX_CLCD_PL_96_97_VAL 0
#define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
#define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_98_MASK (0x7 << 24)
#define PMX_CLCD_PL_98_VAL 0
#define PMX_I2C1_PL_98_VAL (0x2 << 24)
#define PMX_UART3_PL_98_VAL (0x4 << 24)
#define PMX_PL_99_MASK (0x7 << 27)
#define PMX_SDHCI_PL_99_VAL 0
#define PMX_I2C1_PL_99_VAL (0x2 << 27)
#define PMX_UART3_PL_99_VAL (0x4 << 27)
#define IP_SEL_MIX_PAD_REG 0x00CC
#define PMX_PL_100_101_MASK (0x3F << 0)
#define PMX_SDHCI_PL_100_101_VAL 0
#define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
#define PMX_SSP1_PORT_94_TO_97_VAL 0
#define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
#define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
#define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
#define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
#define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
#define PMX_SSP2_PORT_90_TO_93_VAL 0
#define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
#define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
#define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
#define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
#define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
#define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
#define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
#define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
#define PMX_UART3_PORT_94_VAL 0
#define PMX_UART3_PORT_73_VAL (0x1 << 16)
#define PMX_UART3_PORT_52_VAL (0x2 << 16)
#define PMX_UART3_PORT_41_VAL (0x3 << 16)
#define PMX_UART3_PORT_15_VAL (0x4 << 16)
#define PMX_UART3_PORT_8_VAL (0x5 << 16)
#define PMX_UART3_PORT_99_VAL (0x6 << 16)
#define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
#define PMX_UART4_PORT_92_VAL 0
#define PMX_UART4_PORT_71_VAL (0x1 << 19)
#define PMX_UART4_PORT_39_VAL (0x2 << 19)
#define PMX_UART4_PORT_13_VAL (0x3 << 19)
#define PMX_UART4_PORT_6_VAL (0x4 << 19)
#define PMX_UART4_PORT_101_VAL (0x5 << 19)
#define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
#define PMX_UART5_PORT_90_VAL 0
#define PMX_UART5_PORT_69_VAL (0x1 << 22)
#define PMX_UART5_PORT_37_VAL (0x2 << 22)
#define PMX_UART5_PORT_4_VAL (0x3 << 22)
#define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
#define PMX_UART6_PORT_88_VAL 0
#define PMX_UART6_PORT_2_VAL (0x1 << 24)
#define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
#define PMX_I2C1_PORT_8_9_VAL 0
#define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
#define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
#define PMX_I2C2_PORT_96_97_VAL 0
#define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
#define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
#define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
#define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
#define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
#define PMX_SDHCI_CD_PORT_12_VAL 0
#define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
/* Pad multiplexing for CLCD device */
static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
97 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_CLCD_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
PMX_PL_88_89_MASK,
.val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
PMX_CLCD_PL_88_89_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
.val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
PMX_CLCD_PL_98_VAL,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* Pad multiplexing for EMI (Parallel NOR flash) device */
static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
93, 94, 95, 96, 97 };
static struct spear_muxreg emi_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg emi_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
.val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
PMX_FSMC_EMI_PL_54_55_56_VAL |
PMX_FSMC_EMI_PL_58_59_VAL,
}, {
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_EMI_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
PMX_PL_88_89_MASK,
.val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
PMX_EMI_PL_88_89_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
.val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
},
};
static struct spear_modemux emi_modemux[] = {
{
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
.muxregs = emi_muxreg,
.nmuxregs = ARRAY_SIZE(emi_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = emi_ext_muxreg,
.nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
},
};
static struct spear_pingroup emi_pingroup = {
.name = "emi_grp",
.pins = emi_pins,
.npins = ARRAY_SIZE(emi_pins),
.modemuxs = emi_modemux,
.nmodemuxs = ARRAY_SIZE(emi_modemux),
};
static const char *const emi_grps[] = { "emi_grp" };
static struct spear_function emi_function = {
.name = "emi",
.groups = emi_grps,
.ngroups = ARRAY_SIZE(emi_grps),
};
/* Pad multiplexing for FSMC (NAND flash) device */
static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66, 67, 68 };
static struct spear_muxreg fsmc_8bit_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
PMX_PL_57_MASK | PMX_PL_58_59_MASK,
.val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
}, {
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
PMX_PL_65_TO_68_MASK,
.val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
PMX_FSMC_PL_65_TO_68_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
},
};
static struct spear_modemux fsmc_8bit_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
},
};
static struct spear_pingroup fsmc_8bit_pingroup = {
.name = "fsmc_8bit_grp",
.pins = fsmc_8bit_pins,
.npins = ARRAY_SIZE(fsmc_8bit_pins),
.modemuxs = fsmc_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
};
static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg fsmc_16bit_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
PMX_FSMC_EMI_PL_73_VAL,
}
};
static struct spear_modemux fsmc_16bit_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
}, {
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
.muxregs = fsmc_16bit_autoexp_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = fsmc_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
},
};
static struct spear_pingroup fsmc_16bit_pingroup = {
.name = "fsmc_16bit_grp",
.pins = fsmc_16bit_pins,
.npins = ARRAY_SIZE(fsmc_16bit_pins),
.modemuxs = fsmc_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* Pad multiplexing for SPP device */
static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80, 81, 82, 83, 84, 85 };
static struct spear_muxreg spp_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_SPP_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK,
.val = PMX_SPP_PL_80_TO_85_VAL,
},
};
static struct spear_modemux spp_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = spp_muxreg,
.nmuxregs = ARRAY_SIZE(spp_muxreg),
},
};
static struct spear_pingroup spp_pingroup = {
.name = "spp_grp",
.pins = spp_pins,
.npins = ARRAY_SIZE(spp_pins),
.modemuxs = spp_modemux,
.nmodemuxs = ARRAY_SIZE(spp_modemux),
};
static const char *const spp_grps[] = { "spp_grp" };
static struct spear_function spp_function = {
.name = "spp",
.groups = spp_grps,
.ngroups = ARRAY_SIZE(spp_grps),
};
/* Pad multiplexing for SDHCI device */
static const unsigned sdhci_led_pins[] = { 34 };
static struct spear_muxreg sdhci_led_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg sdhci_led_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_34_MASK,
.val = PMX_PWM2_PL_34_VAL,
},
};
static struct spear_modemux sdhci_led_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = sdhci_led_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = sdhci_led_ext_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
},
};
static struct spear_pingroup sdhci_led_pingroup = {
.name = "sdhci_led_grp",
.pins = sdhci_led_pins,
.npins = ARRAY_SIZE(sdhci_led_pins),
.modemuxs = sdhci_led_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
};
static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
50};
static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
};
static struct spear_muxreg sdhci_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg sdhci_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
PMX_PL_48_49_MASK,
.val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_50_MASK,
.val = PMX_SDHCI_PL_50_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_99_MASK,
.val = PMX_SDHCI_PL_99_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_PL_100_101_MASK,
.val = PMX_SDHCI_PL_100_101_VAL,
},
};
static struct spear_muxreg sdhci_cd_12_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_12_MASK,
.val = PMX_SDHCI_CD_PL_12_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
.val = PMX_SDHCI_CD_PORT_12_VAL,
},
};
static struct spear_muxreg sdhci_cd_51_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_51_MASK,
.val = PMX_SDHCI_CD_PL_51_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
.val = PMX_SDHCI_CD_PORT_51_VAL,
},
};
#define pmx_sdhci_common_modemux \
{ \
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
SMALL_PRINTERS_MODE | EXTENDED_MODE, \
.muxregs = sdhci_muxreg, \
.nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
}, { \
.modes = EXTENDED_MODE, \
.muxregs = sdhci_ext_muxreg, \
.nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
}
static struct spear_modemux sdhci_modemux[][3] = {
{
/* select pin 12 for cd */
pmx_sdhci_common_modemux,
{
.modes = EXTENDED_MODE,
.muxregs = sdhci_cd_12_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
},
}, {
/* select pin 51 for cd */
pmx_sdhci_common_modemux,
{
.modes = EXTENDED_MODE,
.muxregs = sdhci_cd_51_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
},
}
};
static struct spear_pingroup sdhci_pingroup[] = {
{
.name = "sdhci_cd_12_grp",
.pins = sdhci_cd_12_pins,
.npins = ARRAY_SIZE(sdhci_cd_12_pins),
.modemuxs = sdhci_modemux[0],
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
}, {
.name = "sdhci_cd_51_grp",
.pins = sdhci_cd_51_pins,
.npins = ARRAY_SIZE(sdhci_cd_51_pins),
.modemuxs = sdhci_modemux[1],
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
},
};
static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
"sdhci_led_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* Pad multiplexing for I2S device */
static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
static struct spear_muxreg i2s_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
}, {
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_muxreg i2s_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
.val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
.val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
},
};
static struct spear_modemux i2s_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = i2s_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = i2s_ext_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
},
};
static struct spear_pingroup i2s_pingroup = {
.name = "i2s_grp",
.pins = i2s_pins,
.npins = ARRAY_SIZE(i2s_pins),
.modemuxs = i2s_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_modemux),
};
static const char *const i2s_grps[] = { "i2s_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* Pad multiplexing for UART1 device */
static const unsigned uart1_pins[] = { 28, 29 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_28_29_MASK,
.val = PMX_UART1_PL_28_29_VAL,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
| SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart1_ext_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* Pad multiplexing for UART1 Modem device */
static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
.val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
PMX_UART1_ENH_PL_6_7_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
},
};
static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
PMX_PL_35_MASK | PMX_PL_36_MASK,
.val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
PMX_UART1_ENH_PL_36_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
},
};
static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
.val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
PMX_UART1_ENH_PL_36_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
},
};
static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK,
.val = PMX_UART1_ENH_PL_80_TO_85_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
},
};
static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_2_to_7_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
},
};
static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
{
.modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = uart1_modem_31_to_36_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_31_to_36_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
},
};
static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
{
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
.muxregs = uart1_modem_34_to_45_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_34_to_45_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
},
};
static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_80_to_85_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
},
};
static struct spear_pingroup uart1_modem_pingroup[] = {
{
.name = "uart1_modem_2_to_7_grp",
.pins = uart1_modem_2_to_7_pins,
.npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
.modemuxs = uart1_modem_2_to_7_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
}, {
.name = "uart1_modem_31_to_36_grp",
.pins = uart1_modem_31_to_36_pins,
.npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
.modemuxs = uart1_modem_31_to_36_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
}, {
.name = "uart1_modem_34_to_45_grp",
.pins = uart1_modem_34_to_45_pins,
.npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
.modemuxs = uart1_modem_34_to_45_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
}, {
.name = "uart1_modem_80_to_85_grp",
.pins = uart1_modem_80_to_85_pins,
.npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
.modemuxs = uart1_modem_80_to_85_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
},
};
static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
"uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
"uart1_modem_80_to_85_grp" };
static struct spear_function uart1_modem_function = {
.name = "uart1_modem",
.groups = uart1_modem_grps,
.ngroups = ARRAY_SIZE(uart1_modem_grps),
};
/* Pad multiplexing for UART2 device */
static const unsigned uart2_pins[] = { 0, 1 };
static struct spear_muxreg uart2_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.val = 0,
},
};
static struct spear_muxreg uart2_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_0_1_MASK,
.val = PMX_UART2_PL_0_1_VAL,
},
};
static struct spear_modemux uart2_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
| SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = uart2_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart2_ext_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
},
};
static struct spear_pingroup uart2_pingroup = {
.name = "uart2_grp",
.pins = uart2_pins,
.npins = ARRAY_SIZE(uart2_pins),
.modemuxs = uart2_modemux,
.nmodemuxs = ARRAY_SIZE(uart2_modemux),
};
static const char *const uart2_grps[] = { "uart2_grp" };
static struct spear_function uart2_function = {
.name = "uart2",
.groups = uart2_grps,
.ngroups = ARRAY_SIZE(uart2_grps),
};
/* Pad multiplexing for uart3 device */
static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
{ 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_8_9_MASK,
.val = PMX_UART3_PL_8_9_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_8_VAL,
},
};
static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_15_16_MASK,
.val = PMX_UART3_PL_15_16_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_15_VAL,
},
};
static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_41_42_MASK,
.val = PMX_UART3_PL_41_42_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_41_VAL,
},
};
static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_52_53_MASK,
.val = PMX_UART3_PL_52_53_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_52_VAL,
},
};
static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
{
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
.val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_73_VAL,
},
};
static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_94_95_MASK,
.val = PMX_UART3_PL_94_95_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_94_VAL,
},
};
static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
.val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART3_PORT_SEL_MASK,
.val = PMX_UART3_PORT_99_VAL,
},
};
static struct spear_modemux uart3_modemux[][1] = {
{
/* Select signals on pins 8_9 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_8_9_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
},
}, {
/* Select signals on pins 15_16 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_15_16_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
},
}, {
/* Select signals on pins 41_42 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_41_42_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
},
}, {
/* Select signals on pins 52_53 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_52_53_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
},
}, {
/* Select signals on pins 73_74 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_73_74_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
},
}, {
/* Select signals on pins 94_95 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_94_95_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
},
}, {
/* Select signals on pins 98_99 */
{
.modes = EXTENDED_MODE,
.muxregs = uart3_ext_98_99_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
},
},
};
static struct spear_pingroup uart3_pingroup[] = {
{
.name = "uart3_8_9_grp",
.pins = uart3_pins[0],
.npins = ARRAY_SIZE(uart3_pins[0]),
.modemuxs = uart3_modemux[0],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
}, {
.name = "uart3_15_16_grp",
.pins = uart3_pins[1],
.npins = ARRAY_SIZE(uart3_pins[1]),
.modemuxs = uart3_modemux[1],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
}, {
.name = "uart3_41_42_grp",
.pins = uart3_pins[2],
.npins = ARRAY_SIZE(uart3_pins[2]),
.modemuxs = uart3_modemux[2],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
}, {
.name = "uart3_52_53_grp",
.pins = uart3_pins[3],
.npins = ARRAY_SIZE(uart3_pins[3]),
.modemuxs = uart3_modemux[3],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
}, {
.name = "uart3_73_74_grp",
.pins = uart3_pins[4],
.npins = ARRAY_SIZE(uart3_pins[4]),
.modemuxs = uart3_modemux[4],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
}, {
.name = "uart3_94_95_grp",
.pins = uart3_pins[5],
.npins = ARRAY_SIZE(uart3_pins[5]),
.modemuxs = uart3_modemux[5],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
}, {
.name = "uart3_98_99_grp",
.pins = uart3_pins[6],
.npins = ARRAY_SIZE(uart3_pins[6]),
.modemuxs = uart3_modemux[6],
.nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
},
};
static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
"uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
"uart3_94_95_grp", "uart3_98_99_grp" };
static struct spear_function uart3_function = {
.name = "uart3",
.groups = uart3_grps,
.ngroups = ARRAY_SIZE(uart3_grps),
};
/* Pad multiplexing for uart4 device */
static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
{ 71, 72 }, { 92, 93 }, { 100, 101 } };
static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_6_7_MASK,
.val = PMX_UART4_PL_6_7_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PORT_6_VAL,
},
};
static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_13_14_MASK,
.val = PMX_UART4_PL_13_14_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PORT_13_VAL,
},
};
static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_39_MASK,
.val = PMX_UART4_PL_39_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_40_MASK,
.val = PMX_UART4_PL_40_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PORT_39_VAL,
},
};
static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
{
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_71_72_MASK,
.val = PMX_UART4_PL_71_72_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PORT_71_VAL,
},
};
static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_92_93_MASK,
.val = PMX_UART4_PL_92_93_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PORT_92_VAL,
},
};
static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
{
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_PL_100_101_MASK |
PMX_UART4_PORT_SEL_MASK,
.val = PMX_UART4_PL_100_101_VAL |
PMX_UART4_PORT_101_VAL,
},
};
static struct spear_modemux uart4_modemux[][1] = {
{
/* Select signals on pins 6_7 */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_6_7_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
},
}, {
/* Select signals on pins 13_14 */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_13_14_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
},
}, {
/* Select signals on pins 39_40 */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_39_40_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
},
}, {
/* Select signals on pins 71_72 */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_71_72_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
},
}, {
/* Select signals on pins 92_93 */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_92_93_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
},
}, {
/* Select signals on pins 100_101_ */
{
.modes = EXTENDED_MODE,
.muxregs = uart4_ext_100_101_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
},
},
};
static struct spear_pingroup uart4_pingroup[] = {
{
.name = "uart4_6_7_grp",
.pins = uart4_pins[0],
.npins = ARRAY_SIZE(uart4_pins[0]),
.modemuxs = uart4_modemux[0],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
}, {
.name = "uart4_13_14_grp",
.pins = uart4_pins[1],
.npins = ARRAY_SIZE(uart4_pins[1]),
.modemuxs = uart4_modemux[1],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
}, {
.name = "uart4_39_40_grp",
.pins = uart4_pins[2],
.npins = ARRAY_SIZE(uart4_pins[2]),
.modemuxs = uart4_modemux[2],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
}, {
.name = "uart4_71_72_grp",
.pins = uart4_pins[3],
.npins = ARRAY_SIZE(uart4_pins[3]),
.modemuxs = uart4_modemux[3],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
}, {
.name = "uart4_92_93_grp",
.pins = uart4_pins[4],
.npins = ARRAY_SIZE(uart4_pins[4]),
.modemuxs = uart4_modemux[4],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
}, {
.name = "uart4_100_101_grp",
.pins = uart4_pins[5],
.npins = ARRAY_SIZE(uart4_pins[5]),
.modemuxs = uart4_modemux[5],
.nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
},
};
static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
"uart4_100_101_grp" };
static struct spear_function uart4_function = {
.name = "uart4",
.groups = uart4_grps,
.ngroups = ARRAY_SIZE(uart4_grps),
};
/* Pad multiplexing for uart5 device */
static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
{ 90, 91 } };
static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_I2C_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_4_5_MASK,
.val = PMX_UART5_PL_4_5_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART5_PORT_SEL_MASK,
.val = PMX_UART5_PORT_4_VAL,
},
};
static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_37_38_MASK,
.val = PMX_UART5_PL_37_38_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART5_PORT_SEL_MASK,
.val = PMX_UART5_PORT_37_VAL,
},
};
static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_UART5_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK,
.val = PMX_UART5_PL_70_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART5_PORT_SEL_MASK,
.val = PMX_UART5_PORT_69_VAL,
},
};
static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK,
.val = PMX_UART5_PL_90_91_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART5_PORT_SEL_MASK,
.val = PMX_UART5_PORT_90_VAL,
},
};
static struct spear_modemux uart5_modemux[][1] = {
{
/* Select signals on pins 4_5 */
{
.modes = EXTENDED_MODE,
.muxregs = uart5_ext_4_5_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
},
}, {
/* Select signals on pins 37_38 */
{
.modes = EXTENDED_MODE,
.muxregs = uart5_ext_37_38_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
},
}, {
/* Select signals on pins 69_70 */
{
.modes = EXTENDED_MODE,
.muxregs = uart5_ext_69_70_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
},
}, {
/* Select signals on pins 90_91 */
{
.modes = EXTENDED_MODE,
.muxregs = uart5_ext_90_91_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
},
},
};
static struct spear_pingroup uart5_pingroup[] = {
{
.name = "uart5_4_5_grp",
.pins = uart5_pins[0],
.npins = ARRAY_SIZE(uart5_pins[0]),
.modemuxs = uart5_modemux[0],
.nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
}, {
.name = "uart5_37_38_grp",
.pins = uart5_pins[1],
.npins = ARRAY_SIZE(uart5_pins[1]),
.modemuxs = uart5_modemux[1],
.nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
}, {
.name = "uart5_69_70_grp",
.pins = uart5_pins[2],
.npins = ARRAY_SIZE(uart5_pins[2]),
.modemuxs = uart5_modemux[2],
.nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
}, {
.name = "uart5_90_91_grp",
.pins = uart5_pins[3],
.npins = ARRAY_SIZE(uart5_pins[3]),
.modemuxs = uart5_modemux[3],
.nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
},
};
static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
"uart5_69_70_grp", "uart5_90_91_grp" };
static struct spear_function uart5_function = {
.name = "uart5",
.groups = uart5_grps,
.ngroups = ARRAY_SIZE(uart5_grps),
};
/* Pad multiplexing for uart6 device */
static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_2_3_MASK,
.val = PMX_UART6_PL_2_3_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART6_PORT_SEL_MASK,
.val = PMX_UART6_PORT_2_VAL,
},
};
static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_88_89_MASK,
.val = PMX_UART6_PL_88_89_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART6_PORT_SEL_MASK,
.val = PMX_UART6_PORT_88_VAL,
},
};
static struct spear_modemux uart6_modemux[][1] = {
{
/* Select signals on pins 2_3 */
{
.modes = EXTENDED_MODE,
.muxregs = uart6_ext_2_3_muxreg,
.nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
},
}, {
/* Select signals on pins 88_89 */
{
.modes = EXTENDED_MODE,
.muxregs = uart6_ext_88_89_muxreg,
.nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
},
},
};
static struct spear_pingroup uart6_pingroup[] = {
{
.name = "uart6_2_3_grp",
.pins = uart6_pins[0],
.npins = ARRAY_SIZE(uart6_pins[0]),
.modemuxs = uart6_modemux[0],
.nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
}, {
.name = "uart6_88_89_grp",
.pins = uart6_pins[1],
.npins = ARRAY_SIZE(uart6_pins[1]),
.modemuxs = uart6_modemux[1],
.nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
},
};
static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
static struct spear_function uart6_function = {
.name = "uart6",
.groups = uart6_grps,
.ngroups = ARRAY_SIZE(uart6_grps),
};
/* UART - RS485 pmx */
static const unsigned rs485_pins[] = { 77, 78, 79 };
static struct spear_muxreg rs485_muxreg[] = {
{
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_77_78_79_MASK,
.val = PMX_RS485_PL_77_78_79_VAL,
},
};
static struct spear_modemux rs485_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = rs485_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_muxreg),
},
};
static struct spear_pingroup rs485_pingroup = {
.name = "rs485_grp",
.pins = rs485_pins,
.npins = ARRAY_SIZE(rs485_pins),
.modemuxs = rs485_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_modemux),
};
static const char *const rs485_grps[] = { "rs485_grp" };
static struct spear_function rs485_function = {
.name = "rs485",
.groups = rs485_grps,
.ngroups = ARRAY_SIZE(rs485_grps),
};
/* Pad multiplexing for Touchscreen device */
static const unsigned touchscreen_pins[] = { 5, 36 };
static struct spear_muxreg touchscreen_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg touchscreen_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_5_MASK,
.val = PMX_TOUCH_Y_PL_5_VAL,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_36_MASK,
.val = PMX_TOUCH_X_PL_36_VAL,
},
};
static struct spear_modemux touchscreen_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
.muxregs = touchscreen_muxreg,
.nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = touchscreen_ext_muxreg,
.nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
},
};
static struct spear_pingroup touchscreen_pingroup = {
.name = "touchscreen_grp",
.pins = touchscreen_pins,
.npins = ARRAY_SIZE(touchscreen_pins),
.modemuxs = touchscreen_modemux,
.nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
};
static const char *const touchscreen_grps[] = { "touchscreen_grp" };
static struct spear_function touchscreen_function = {
.name = "touchscreen",
.groups = touchscreen_grps,
.ngroups = ARRAY_SIZE(touchscreen_grps),
};
/* Pad multiplexing for CAN device */
static const unsigned can0_pins[] = { 32, 33 };
static struct spear_muxreg can0_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
.val = 0,
},
};
static struct spear_muxreg can0_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_32_33_MASK,
.val = PMX_CAN0_PL_32_33_VAL,
},
};
static struct spear_modemux can0_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
| EXTENDED_MODE,
.muxregs = can0_muxreg,
.nmuxregs = ARRAY_SIZE(can0_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = can0_ext_muxreg,
.nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
},
};
static struct spear_pingroup can0_pingroup = {
.name = "can0_grp",
.pins = can0_pins,
.npins = ARRAY_SIZE(can0_pins),
.modemuxs = can0_modemux,
.nmodemuxs = ARRAY_SIZE(can0_modemux),
};
static const char *const can0_grps[] = { "can0_grp" };
static struct spear_function can0_function = {
.name = "can0",
.groups = can0_grps,
.ngroups = ARRAY_SIZE(can0_grps),
};
static const unsigned can1_pins[] = { 30, 31 };
static struct spear_muxreg can1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
.val = 0,
},
};
static struct spear_muxreg can1_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_30_31_MASK,
.val = PMX_CAN1_PL_30_31_VAL,
},
};
static struct spear_modemux can1_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
| EXTENDED_MODE,
.muxregs = can1_muxreg,
.nmuxregs = ARRAY_SIZE(can1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = can1_ext_muxreg,
.nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
},
};
static struct spear_pingroup can1_pingroup = {
.name = "can1_grp",
.pins = can1_pins,
.npins = ARRAY_SIZE(can1_pins),
.modemuxs = can1_modemux,
.nmodemuxs = ARRAY_SIZE(can1_modemux),
};
static const char *const can1_grps[] = { "can1_grp" };
static struct spear_function can1_function = {
.name = "can1",
.groups = can1_grps,
.ngroups = ARRAY_SIZE(can1_grps),
};
/* Pad multiplexing for PWM0_1 device */
static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
{ 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_8_9_MASK,
.val = PMX_PWM_0_1_PL_8_9_VAL,
},
};
static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
.val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
},
};
static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
.val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
},
};
static struct spear_muxreg pwm0_1_net_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_37_38_MASK,
.val = PMX_PWM0_1_PL_37_38_VAL,
},
};
static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
.val = PMX_PWM1_PL_42_VAL |
PMX_PWM0_PL_43_VAL,
},
};
static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_59_MASK,
.val = PMX_PWM1_PL_59_VAL,
}, {
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_60_MASK,
.val = PMX_PWM0_PL_60_VAL,
},
};
static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_88_89_MASK,
.val = PMX_PWM0_1_PL_88_89_VAL,
},
};
static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_8_9_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
{
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = pwm0_1_autoexpsmallpri_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_14_15_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_30_31_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = pwm0_1_net_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_37_38_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_42_43_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_59_60_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
},
};
static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm0_1_pin_88_89_muxreg,
.nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
},
};
static struct spear_pingroup pwm0_1_pingroup[] = {
{
.name = "pwm0_1_pin_8_9_grp",
.pins = pwm0_1_pins[0],
.npins = ARRAY_SIZE(pwm0_1_pins[0]),
.modemuxs = pwm0_1_pin_8_9_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
}, {
.name = "pwm0_1_pin_14_15_grp",
.pins = pwm0_1_pins[1],
.npins = ARRAY_SIZE(pwm0_1_pins[1]),
.modemuxs = pwm0_1_pin_14_15_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
}, {
.name = "pwm0_1_pin_30_31_grp",
.pins = pwm0_1_pins[2],
.npins = ARRAY_SIZE(pwm0_1_pins[2]),
.modemuxs = pwm0_1_pin_30_31_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
}, {
.name = "pwm0_1_pin_37_38_grp",
.pins = pwm0_1_pins[3],
.npins = ARRAY_SIZE(pwm0_1_pins[3]),
.modemuxs = pwm0_1_pin_37_38_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
}, {
.name = "pwm0_1_pin_42_43_grp",
.pins = pwm0_1_pins[4],
.npins = ARRAY_SIZE(pwm0_1_pins[4]),
.modemuxs = pwm0_1_pin_42_43_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
}, {
.name = "pwm0_1_pin_59_60_grp",
.pins = pwm0_1_pins[5],
.npins = ARRAY_SIZE(pwm0_1_pins[5]),
.modemuxs = pwm0_1_pin_59_60_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
}, {
.name = "pwm0_1_pin_88_89_grp",
.pins = pwm0_1_pins[6],
.npins = ARRAY_SIZE(pwm0_1_pins[6]),
.modemuxs = pwm0_1_pin_88_89_modemux,
.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
},
};
static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
"pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
"pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
};
static struct spear_function pwm0_1_function = {
.name = "pwm0_1",
.groups = pwm0_1_grps,
.ngroups = ARRAY_SIZE(pwm0_1_grps),
};
/* Pad multiplexing for PWM2 device */
static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
{ 58 }, { 87 } };
static struct spear_muxreg pwm2_net_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg pwm2_pin_7_muxreg[] = {
{
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_7_MASK,
.val = PMX_PWM_2_PL_7_VAL,
},
};
static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg pwm2_pin_13_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_13_MASK,
.val = PMX_PWM2_PL_13_VAL,
},
};
static struct spear_muxreg pwm2_pin_29_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN1_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_29_MASK,
.val = PMX_PWM_2_PL_29_VAL,
},
};
static struct spear_muxreg pwm2_pin_34_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
}, {
.reg = MODE_CONFIG_REG,
.mask = PMX_PWM_MASK,
.val = PMX_PWM_MASK,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_34_MASK,
.val = PMX_PWM2_PL_34_VAL,
},
};
static struct spear_muxreg pwm2_pin_41_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_41_MASK,
.val = PMX_PWM2_PL_41_VAL,
},
};
static struct spear_muxreg pwm2_pin_58_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_58_MASK,
.val = PMX_PWM2_PL_58_VAL,
},
};
static struct spear_muxreg pwm2_pin_87_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_87_MASK,
.val = PMX_PWM2_PL_87_VAL,
},
};
static struct spear_modemux pwm2_pin_7_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = pwm2_net_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_7_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
},
};
static struct spear_modemux pwm2_pin_13_modemux[] = {
{
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = pwm2_autoexpsmallpri_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_13_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
},
};
static struct spear_modemux pwm2_pin_29_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_29_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
},
};
static struct spear_modemux pwm2_pin_34_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_34_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
},
};
static struct spear_modemux pwm2_pin_41_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_41_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
},
};
static struct spear_modemux pwm2_pin_58_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_58_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
},
};
static struct spear_modemux pwm2_pin_87_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm2_pin_87_muxreg,
.nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
},
};
static struct spear_pingroup pwm2_pingroup[] = {
{
.name = "pwm2_pin_7_grp",
.pins = pwm2_pins[0],
.npins = ARRAY_SIZE(pwm2_pins[0]),
.modemuxs = pwm2_pin_7_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
}, {
.name = "pwm2_pin_13_grp",
.pins = pwm2_pins[1],
.npins = ARRAY_SIZE(pwm2_pins[1]),
.modemuxs = pwm2_pin_13_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
}, {
.name = "pwm2_pin_29_grp",
.pins = pwm2_pins[2],
.npins = ARRAY_SIZE(pwm2_pins[2]),
.modemuxs = pwm2_pin_29_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
}, {
.name = "pwm2_pin_34_grp",
.pins = pwm2_pins[3],
.npins = ARRAY_SIZE(pwm2_pins[3]),
.modemuxs = pwm2_pin_34_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
}, {
.name = "pwm2_pin_41_grp",
.pins = pwm2_pins[4],
.npins = ARRAY_SIZE(pwm2_pins[4]),
.modemuxs = pwm2_pin_41_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
}, {
.name = "pwm2_pin_58_grp",
.pins = pwm2_pins[5],
.npins = ARRAY_SIZE(pwm2_pins[5]),
.modemuxs = pwm2_pin_58_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
}, {
.name = "pwm2_pin_87_grp",
.pins = pwm2_pins[6],
.npins = ARRAY_SIZE(pwm2_pins[6]),
.modemuxs = pwm2_pin_87_modemux,
.nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
},
};
static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
"pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
"pwm2_pin_58_grp", "pwm2_pin_87_grp" };
static struct spear_function pwm2_function = {
.name = "pwm2",
.groups = pwm2_grps,
.ngroups = ARRAY_SIZE(pwm2_grps),
};
/* Pad multiplexing for PWM3 device */
static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
{ 86 } };
static struct spear_muxreg pwm3_pin_6_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_6_MASK,
.val = PMX_PWM_3_PL_6_VAL,
},
};
static struct spear_muxreg pwm3_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg pwm3_pin_12_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_12_MASK,
.val = PMX_PWM3_PL_12_VAL,
},
};
static struct spear_muxreg pwm3_pin_28_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_28_MASK,
.val = PMX_PWM_3_PL_28_VAL,
},
};
static struct spear_muxreg pwm3_pin_40_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_40_MASK,
.val = PMX_PWM3_PL_40_VAL,
},
};
static struct spear_muxreg pwm3_pin_57_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_57_MASK,
.val = PMX_PWM3_PL_57_VAL,
},
};
static struct spear_muxreg pwm3_pin_86_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_86_MASK,
.val = PMX_PWM3_PL_86_VAL,
},
};
static struct spear_modemux pwm3_pin_6_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_6_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
},
};
static struct spear_modemux pwm3_pin_12_modemux[] = {
{
.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
AUTO_NET_SMII_MODE | EXTENDED_MODE,
.muxregs = pwm3_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_12_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
},
};
static struct spear_modemux pwm3_pin_28_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_28_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
},
};
static struct spear_modemux pwm3_pin_40_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_40_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
},
};
static struct spear_modemux pwm3_pin_57_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_57_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
},
};
static struct spear_modemux pwm3_pin_86_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = pwm3_pin_86_muxreg,
.nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
},
};
static struct spear_pingroup pwm3_pingroup[] = {
{
.name = "pwm3_pin_6_grp",
.pins = pwm3_pins[0],
.npins = ARRAY_SIZE(pwm3_pins[0]),
.modemuxs = pwm3_pin_6_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
}, {
.name = "pwm3_pin_12_grp",
.pins = pwm3_pins[1],
.npins = ARRAY_SIZE(pwm3_pins[1]),
.modemuxs = pwm3_pin_12_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
}, {
.name = "pwm3_pin_28_grp",
.pins = pwm3_pins[2],
.npins = ARRAY_SIZE(pwm3_pins[2]),
.modemuxs = pwm3_pin_28_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
}, {
.name = "pwm3_pin_40_grp",
.pins = pwm3_pins[3],
.npins = ARRAY_SIZE(pwm3_pins[3]),
.modemuxs = pwm3_pin_40_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
}, {
.name = "pwm3_pin_57_grp",
.pins = pwm3_pins[4],
.npins = ARRAY_SIZE(pwm3_pins[4]),
.modemuxs = pwm3_pin_57_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
}, {
.name = "pwm3_pin_86_grp",
.pins = pwm3_pins[5],
.npins = ARRAY_SIZE(pwm3_pins[5]),
.modemuxs = pwm3_pin_86_modemux,
.nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
},
};
static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
"pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
"pwm3_pin_86_grp" };
static struct spear_function pwm3_function = {
.name = "pwm3",
.groups = pwm3_grps,
.ngroups = ARRAY_SIZE(pwm3_grps),
};
/* Pad multiplexing for SSP1 device */
static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
{ 65, 68 }, { 94, 97 } };
static struct spear_muxreg ssp1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
.val = PMX_SSP1_PL_17_18_19_20_VAL,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_20_MASK,
.val = PMX_SSP1_PL_17_18_19_20_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP1_PORT_SEL_MASK,
.val = PMX_SSP1_PORT_17_TO_20_VAL,
},
};
static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
.val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
PMX_SSP1_PL_39_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP1_PORT_SEL_MASK,
.val = PMX_SSP1_PORT_36_TO_39_VAL,
},
};
static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_48_49_MASK,
.val = PMX_SSP1_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_50_51_MASK,
.val = PMX_SSP1_PL_50_51_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP1_PORT_SEL_MASK,
.val = PMX_SSP1_PORT_48_TO_51_VAL,
},
};
static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_65_TO_68_MASK,
.val = PMX_SSP1_PL_65_TO_68_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP1_PORT_SEL_MASK,
.val = PMX_SSP1_PORT_65_TO_68_VAL,
},
};
static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
.val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP1_PORT_SEL_MASK,
.val = PMX_SSP1_PORT_94_TO_97_VAL,
},
};
static struct spear_modemux ssp1_17_20_modemux[] = {
{
.modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
EXTENDED_MODE,
.muxregs = ssp1_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = ssp1_ext_17_20_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
},
};
static struct spear_modemux ssp1_36_39_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp1_ext_36_39_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
},
};
static struct spear_modemux ssp1_48_51_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp1_ext_48_51_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
},
};
static struct spear_modemux ssp1_65_68_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp1_ext_65_68_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
},
};
static struct spear_modemux ssp1_94_97_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp1_ext_94_97_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
},
};
static struct spear_pingroup ssp1_pingroup[] = {
{
.name = "ssp1_17_20_grp",
.pins = ssp1_pins[0],
.npins = ARRAY_SIZE(ssp1_pins[0]),
.modemuxs = ssp1_17_20_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
}, {
.name = "ssp1_36_39_grp",
.pins = ssp1_pins[1],
.npins = ARRAY_SIZE(ssp1_pins[1]),
.modemuxs = ssp1_36_39_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
}, {
.name = "ssp1_48_51_grp",
.pins = ssp1_pins[2],
.npins = ARRAY_SIZE(ssp1_pins[2]),
.modemuxs = ssp1_48_51_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
}, {
.name = "ssp1_65_68_grp",
.pins = ssp1_pins[3],
.npins = ARRAY_SIZE(ssp1_pins[3]),
.modemuxs = ssp1_65_68_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
}, {
.name = "ssp1_94_97_grp",
.pins = ssp1_pins[4],
.npins = ARRAY_SIZE(ssp1_pins[4]),
.modemuxs = ssp1_94_97_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
},
};
static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
"ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
};
static struct spear_function ssp1_function = {
.name = "ssp1",
.groups = ssp1_grps,
.ngroups = ARRAY_SIZE(ssp1_grps),
};
/* Pad multiplexing for SSP2 device */
static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
{ 61, 64 }, { 90, 93 } };
static struct spear_muxreg ssp2_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
.val = PMX_SSP2_PL_13_14_15_16_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP2_PORT_SEL_MASK,
.val = PMX_SSP2_PORT_13_TO_16_VAL,
},
};
static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
.val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
PMX_SSP2_PL_35_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP2_PORT_SEL_MASK,
.val = PMX_SSP2_PORT_32_TO_35_VAL,
},
};
static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
.val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP2_PORT_SEL_MASK,
.val = PMX_SSP2_PORT_44_TO_47_VAL,
},
};
static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_61_TO_64_MASK,
.val = PMX_SSP2_PL_61_TO_64_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP2_PORT_SEL_MASK,
.val = PMX_SSP2_PORT_61_TO_64_VAL,
},
};
static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
.val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SSP2_PORT_SEL_MASK,
.val = PMX_SSP2_PORT_90_TO_93_VAL,
},
};
static struct spear_modemux ssp2_13_16_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
.muxregs = ssp2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = ssp2_ext_13_16_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
},
};
static struct spear_modemux ssp2_32_35_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp2_ext_32_35_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
},
};
static struct spear_modemux ssp2_44_47_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp2_ext_44_47_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
},
};
static struct spear_modemux ssp2_61_64_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp2_ext_61_64_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
},
};
static struct spear_modemux ssp2_90_93_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = ssp2_ext_90_93_muxreg,
.nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
},
};
static struct spear_pingroup ssp2_pingroup[] = {
{
.name = "ssp2_13_16_grp",
.pins = ssp2_pins[0],
.npins = ARRAY_SIZE(ssp2_pins[0]),
.modemuxs = ssp2_13_16_modemux,
.nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
}, {
.name = "ssp2_32_35_grp",
.pins = ssp2_pins[1],
.npins = ARRAY_SIZE(ssp2_pins[1]),
.modemuxs = ssp2_32_35_modemux,
.nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
}, {
.name = "ssp2_44_47_grp",
.pins = ssp2_pins[2],
.npins = ARRAY_SIZE(ssp2_pins[2]),
.modemuxs = ssp2_44_47_modemux,
.nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
}, {
.name = "ssp2_61_64_grp",
.pins = ssp2_pins[3],
.npins = ARRAY_SIZE(ssp2_pins[3]),
.modemuxs = ssp2_61_64_modemux,
.nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
}, {
.name = "ssp2_90_93_grp",
.pins = ssp2_pins[4],
.npins = ARRAY_SIZE(ssp2_pins[4]),
.modemuxs = ssp2_90_93_modemux,
.nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
},
};
static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
"ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
static struct spear_function ssp2_function = {
.name = "ssp2",
.groups = ssp2_grps,
.ngroups = ARRAY_SIZE(ssp2_grps),
};
/* Pad multiplexing for cadence mii2 as mii device */
static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
90, 91, 92, 93, 94, 95, 96, 97 };
static struct spear_muxreg mii2_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
PMX_PL_88_89_MASK,
.val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
PMX_MII2_PL_88_89_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
.val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
MII_MDIO_MASK,
.val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
(MAC_MODE_MII << MAC1_MODE_SHIFT) |
MII_MDIO_81_VAL,
},
};
static struct spear_modemux mii2_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = mii2_muxreg,
.nmuxregs = ARRAY_SIZE(mii2_muxreg),
},
};
static struct spear_pingroup mii2_pingroup = {
.name = "mii2_grp",
.pins = mii2_pins,
.npins = ARRAY_SIZE(mii2_pins),
.modemuxs = mii2_modemux,
.nmodemuxs = ARRAY_SIZE(mii2_modemux),
};
static const char *const mii2_grps[] = { "mii2_grp" };
static struct spear_function mii2_function = {
.name = "mii2",
.groups = mii2_grps,
.ngroups = ARRAY_SIZE(mii2_grps),
};
/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
21, 22, 23, 24, 25, 26, 27 };
static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
static struct spear_muxreg mii0_1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_muxreg smii0_1_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_10_11_MASK,
.val = PMX_SMII_PL_10_11_VAL,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_21_TO_27_MASK,
.val = PMX_SMII_PL_21_TO_27_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
MII_MDIO_MASK,
.val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
| (MAC_MODE_SMII << MAC1_MODE_SHIFT)
| MII_MDIO_10_11_VAL,
},
};
static struct spear_muxreg rmii0_1_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
.val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
PMX_RMII_PL_19_VAL,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
.val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
MII_MDIO_MASK,
.val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
| (MAC_MODE_RMII << MAC1_MODE_SHIFT)
| MII_MDIO_10_11_VAL,
},
};
static struct spear_modemux mii0_1_modemux[][2] = {
{
/* configure as smii */
{
.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = mii0_1_muxreg,
.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = smii0_1_ext_muxreg,
.nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
},
}, {
/* configure as rmii */
{
.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = mii0_1_muxreg,
.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = rmii0_1_ext_muxreg,
.nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
},
},
};
static struct spear_pingroup mii0_1_pingroup[] = {
{
.name = "smii0_1_grp",
.pins = smii0_1_pins,
.npins = ARRAY_SIZE(smii0_1_pins),
.modemuxs = mii0_1_modemux[0],
.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
}, {
.name = "rmii0_1_grp",
.pins = rmii0_1_pins,
.npins = ARRAY_SIZE(rmii0_1_pins),
.modemuxs = mii0_1_modemux[1],
.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
},
};
static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
static struct spear_function mii0_1_function = {
.name = "mii0_1",
.groups = mii0_1_grps,
.ngroups = ARRAY_SIZE(mii0_1_grps),
};
/* Pad multiplexing for i2c1 device */
static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_8_9_MASK,
.val = PMX_I2C1_PL_8_9_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C1_PORT_SEL_MASK,
.val = PMX_I2C1_PORT_8_9_VAL,
},
};
static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
.val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C1_PORT_SEL_MASK,
.val = PMX_I2C1_PORT_98_99_VAL,
},
};
static struct spear_modemux i2c1_modemux[][1] = {
{
/* Select signals on pins 8-9 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c1_ext_8_9_muxreg,
.nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
},
}, {
/* Select signals on pins 98-99 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c1_ext_98_99_muxreg,
.nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
},
},
};
static struct spear_pingroup i2c1_pingroup[] = {
{
.name = "i2c1_8_9_grp",
.pins = i2c1_pins[0],
.npins = ARRAY_SIZE(i2c1_pins[0]),
.modemuxs = i2c1_modemux[0],
.nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
}, {
.name = "i2c1_98_99_grp",
.pins = i2c1_pins[1],
.npins = ARRAY_SIZE(i2c1_pins[1]),
.modemuxs = i2c1_modemux[1],
.nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
},
};
static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
static struct spear_function i2c1_function = {
.name = "i2c1",
.groups = i2c1_grps,
.ngroups = ARRAY_SIZE(i2c1_grps),
};
/* Pad multiplexing for i2c2 device */
static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
{ 75, 76 }, { 96, 97 } };
static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_0_1_MASK,
.val = PMX_I2C2_PL_0_1_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C2_PORT_SEL_MASK,
.val = PMX_I2C2_PORT_0_1_VAL,
},
};
static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_2_3_MASK,
.val = PMX_I2C2_PL_2_3_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C2_PORT_SEL_MASK,
.val = PMX_I2C2_PORT_2_3_VAL,
},
};
static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_19_MASK,
.val = PMX_I2C2_PL_19_VAL,
}, {
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_20_MASK,
.val = PMX_I2C2_PL_20_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C2_PORT_SEL_MASK,
.val = PMX_I2C2_PORT_19_20_VAL,
},
};
static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
{
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_75_76_MASK,
.val = PMX_I2C2_PL_75_76_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C2_PORT_SEL_MASK,
.val = PMX_I2C2_PORT_75_76_VAL,
},
};
static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
{
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_96_97_MASK,
.val = PMX_I2C2_PL_96_97_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_I2C2_PORT_SEL_MASK,
.val = PMX_I2C2_PORT_96_97_VAL,
},
};
static struct spear_modemux i2c2_modemux[][1] = {
{
/* Select signals on pins 0_1 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c2_ext_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
},
}, {
/* Select signals on pins 2_3 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c2_ext_2_3_muxreg,
.nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
},
}, {
/* Select signals on pins 19_20 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c2_ext_19_20_muxreg,
.nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
},
}, {
/* Select signals on pins 75_76 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c2_ext_75_76_muxreg,
.nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
},
}, {
/* Select signals on pins 96_97 */
{
.modes = EXTENDED_MODE,
.muxregs = i2c2_ext_96_97_muxreg,
.nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
},
},
};
static struct spear_pingroup i2c2_pingroup[] = {
{
.name = "i2c2_0_1_grp",
.pins = i2c2_pins[0],
.npins = ARRAY_SIZE(i2c2_pins[0]),
.modemuxs = i2c2_modemux[0],
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
}, {
.name = "i2c2_2_3_grp",
.pins = i2c2_pins[1],
.npins = ARRAY_SIZE(i2c2_pins[1]),
.modemuxs = i2c2_modemux[1],
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
}, {
.name = "i2c2_19_20_grp",
.pins = i2c2_pins[2],
.npins = ARRAY_SIZE(i2c2_pins[2]),
.modemuxs = i2c2_modemux[2],
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
}, {
.name = "i2c2_75_76_grp",
.pins = i2c2_pins[3],
.npins = ARRAY_SIZE(i2c2_pins[3]),
.modemuxs = i2c2_modemux[3],
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
}, {
.name = "i2c2_96_97_grp",
.pins = i2c2_pins[4],
.npins = ARRAY_SIZE(i2c2_pins[4]),
.modemuxs = i2c2_modemux[4],
.nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
},
};
static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
"i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
static struct spear_function i2c2_function = {
.name = "i2c2",
.groups = i2c2_grps,
.ngroups = ARRAY_SIZE(i2c2_grps),
};
/* pingroups */
static struct spear_pingroup *spear320_pingroups[] = {
SPEAR3XX_COMMON_PINGROUPS,
&clcd_pingroup,
&emi_pingroup,
&fsmc_8bit_pingroup,
&fsmc_16bit_pingroup,
&spp_pingroup,
&sdhci_led_pingroup,
&sdhci_pingroup[0],
&sdhci_pingroup[1],
&i2s_pingroup,
&uart1_pingroup,
&uart1_modem_pingroup[0],
&uart1_modem_pingroup[1],
&uart1_modem_pingroup[2],
&uart1_modem_pingroup[3],
&uart2_pingroup,
&uart3_pingroup[0],
&uart3_pingroup[1],
&uart3_pingroup[2],
&uart3_pingroup[3],
&uart3_pingroup[4],
&uart3_pingroup[5],
&uart3_pingroup[6],
&uart4_pingroup[0],
&uart4_pingroup[1],
&uart4_pingroup[2],
&uart4_pingroup[3],
&uart4_pingroup[4],
&uart4_pingroup[5],
&uart5_pingroup[0],
&uart5_pingroup[1],
&uart5_pingroup[2],
&uart5_pingroup[3],
&uart6_pingroup[0],
&uart6_pingroup[1],
&rs485_pingroup,
&touchscreen_pingroup,
&can0_pingroup,
&can1_pingroup,
&pwm0_1_pingroup[0],
&pwm0_1_pingroup[1],
&pwm0_1_pingroup[2],
&pwm0_1_pingroup[3],
&pwm0_1_pingroup[4],
&pwm0_1_pingroup[5],
&pwm0_1_pingroup[6],
&pwm2_pingroup[0],
&pwm2_pingroup[1],
&pwm2_pingroup[2],
&pwm2_pingroup[3],
&pwm2_pingroup[4],
&pwm2_pingroup[5],
&pwm2_pingroup[6],
&pwm3_pingroup[0],
&pwm3_pingroup[1],
&pwm3_pingroup[2],
&pwm3_pingroup[3],
&pwm3_pingroup[4],
&pwm3_pingroup[5],
&ssp1_pingroup[0],
&ssp1_pingroup[1],
&ssp1_pingroup[2],
&ssp1_pingroup[3],
&ssp1_pingroup[4],
&ssp2_pingroup[0],
&ssp2_pingroup[1],
&ssp2_pingroup[2],
&ssp2_pingroup[3],
&ssp2_pingroup[4],
&mii2_pingroup,
&mii0_1_pingroup[0],
&mii0_1_pingroup[1],
&i2c1_pingroup[0],
&i2c1_pingroup[1],
&i2c2_pingroup[0],
&i2c2_pingroup[1],
&i2c2_pingroup[2],
&i2c2_pingroup[3],
&i2c2_pingroup[4],
};
/* functions */
static struct spear_function *spear320_functions[] = {
SPEAR3XX_COMMON_FUNCTIONS,
&clcd_function,
&emi_function,
&fsmc_function,
&spp_function,
&sdhci_function,
&i2s_function,
&uart1_function,
&uart1_modem_function,
&uart2_function,
&uart3_function,
&uart4_function,
&uart5_function,
&uart6_function,
&rs485_function,
&touchscreen_function,
&can0_function,
&can1_function,
&pwm0_1_function,
&pwm2_function,
&pwm3_function,
&ssp1_function,
&ssp2_function,
&mii2_function,
&mii0_1_function,
&i2c1_function,
&i2c2_function,
};
static const struct of_device_id spear320_pinctrl_of_match[] = {
{
.compatible = "st,spear320-pinmux",
},
{},
};
static int spear320_pinctrl_probe(struct platform_device *pdev)
{
spear3xx_machdata.groups = spear320_pingroups;
spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
spear3xx_machdata.functions = spear320_functions;
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
spear3xx_machdata.modes_supported = true;
spear3xx_machdata.pmx_modes = spear320_pmx_modes;
spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
return spear_pinctrl_probe(pdev, &spear3xx_machdata);
}
static struct platform_driver spear320_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = spear320_pinctrl_of_match,
},
.probe = spear320_pinctrl_probe,
};
static int __init spear320_pinctrl_init(void)
{
return platform_driver_register(&spear320_pinctrl_driver);
}
arch_initcall(spear320_pinctrl_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear320.c
|
/*
* Driver for the ST Microelectronics SPEAr3xx pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-spear3xx.h"
/* pins */
static const struct pinctrl_pin_desc spear3xx_pins[] = {
SPEAR_PIN_0_TO_101,
};
/* firda_pins */
static const unsigned firda_pins[] = { 0, 1 };
static struct spear_muxreg firda_muxreg[] = {
{
.reg = -1,
.mask = PMX_FIRDA_MASK,
.val = PMX_FIRDA_MASK,
},
};
static struct spear_modemux firda_modemux[] = {
{
.modes = ~0,
.muxregs = firda_muxreg,
.nmuxregs = ARRAY_SIZE(firda_muxreg),
},
};
struct spear_pingroup spear3xx_firda_pingroup = {
.name = "firda_grp",
.pins = firda_pins,
.npins = ARRAY_SIZE(firda_pins),
.modemuxs = firda_modemux,
.nmodemuxs = ARRAY_SIZE(firda_modemux),
};
static const char *const firda_grps[] = { "firda_grp" };
struct spear_function spear3xx_firda_function = {
.name = "firda",
.groups = firda_grps,
.ngroups = ARRAY_SIZE(firda_grps),
};
/* i2c_pins */
static const unsigned i2c_pins[] = { 4, 5 };
static struct spear_muxreg i2c_muxreg[] = {
{
.reg = -1,
.mask = PMX_I2C_MASK,
.val = PMX_I2C_MASK,
},
};
static struct spear_modemux i2c_modemux[] = {
{
.modes = ~0,
.muxregs = i2c_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_muxreg),
},
};
struct spear_pingroup spear3xx_i2c_pingroup = {
.name = "i2c0_grp",
.pins = i2c_pins,
.npins = ARRAY_SIZE(i2c_pins),
.modemuxs = i2c_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_modemux),
};
static const char *const i2c_grps[] = { "i2c0_grp" };
struct spear_function spear3xx_i2c_function = {
.name = "i2c0",
.groups = i2c_grps,
.ngroups = ARRAY_SIZE(i2c_grps),
};
/* ssp_cs_pins */
static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
static struct spear_muxreg ssp_cs_muxreg[] = {
{
.reg = -1,
.mask = PMX_SSP_CS_MASK,
.val = PMX_SSP_CS_MASK,
},
};
static struct spear_modemux ssp_cs_modemux[] = {
{
.modes = ~0,
.muxregs = ssp_cs_muxreg,
.nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
},
};
struct spear_pingroup spear3xx_ssp_cs_pingroup = {
.name = "ssp_cs_grp",
.pins = ssp_cs_pins,
.npins = ARRAY_SIZE(ssp_cs_pins),
.modemuxs = ssp_cs_modemux,
.nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
};
static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
struct spear_function spear3xx_ssp_cs_function = {
.name = "ssp_cs",
.groups = ssp_cs_grps,
.ngroups = ARRAY_SIZE(ssp_cs_grps),
};
/* ssp_pins */
static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
static struct spear_muxreg ssp_muxreg[] = {
{
.reg = -1,
.mask = PMX_SSP_MASK,
.val = PMX_SSP_MASK,
},
};
static struct spear_modemux ssp_modemux[] = {
{
.modes = ~0,
.muxregs = ssp_muxreg,
.nmuxregs = ARRAY_SIZE(ssp_muxreg),
},
};
struct spear_pingroup spear3xx_ssp_pingroup = {
.name = "ssp0_grp",
.pins = ssp_pins,
.npins = ARRAY_SIZE(ssp_pins),
.modemuxs = ssp_modemux,
.nmodemuxs = ARRAY_SIZE(ssp_modemux),
};
static const char *const ssp_grps[] = { "ssp0_grp" };
struct spear_function spear3xx_ssp_function = {
.name = "ssp0",
.groups = ssp_grps,
.ngroups = ARRAY_SIZE(ssp_grps),
};
/* mii_pins */
static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
21, 22, 23, 24, 25, 26, 27 };
static struct spear_muxreg mii_muxreg[] = {
{
.reg = -1,
.mask = PMX_MII_MASK,
.val = PMX_MII_MASK,
},
};
static struct spear_modemux mii_modemux[] = {
{
.modes = ~0,
.muxregs = mii_muxreg,
.nmuxregs = ARRAY_SIZE(mii_muxreg),
},
};
struct spear_pingroup spear3xx_mii_pingroup = {
.name = "mii0_grp",
.pins = mii_pins,
.npins = ARRAY_SIZE(mii_pins),
.modemuxs = mii_modemux,
.nmodemuxs = ARRAY_SIZE(mii_modemux),
};
static const char *const mii_grps[] = { "mii0_grp" };
struct spear_function spear3xx_mii_function = {
.name = "mii0",
.groups = mii_grps,
.ngroups = ARRAY_SIZE(mii_grps),
};
/* gpio0_pin0_pins */
static const unsigned gpio0_pin0_pins[] = { 28 };
static struct spear_muxreg gpio0_pin0_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN0_MASK,
.val = PMX_GPIO_PIN0_MASK,
},
};
static struct spear_modemux gpio0_pin0_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin0_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
.name = "gpio0_pin0_grp",
.pins = gpio0_pin0_pins,
.npins = ARRAY_SIZE(gpio0_pin0_pins),
.modemuxs = gpio0_pin0_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
};
/* gpio0_pin1_pins */
static const unsigned gpio0_pin1_pins[] = { 29 };
static struct spear_muxreg gpio0_pin1_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN1_MASK,
.val = PMX_GPIO_PIN1_MASK,
},
};
static struct spear_modemux gpio0_pin1_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin1_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
.name = "gpio0_pin1_grp",
.pins = gpio0_pin1_pins,
.npins = ARRAY_SIZE(gpio0_pin1_pins),
.modemuxs = gpio0_pin1_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
};
/* gpio0_pin2_pins */
static const unsigned gpio0_pin2_pins[] = { 30 };
static struct spear_muxreg gpio0_pin2_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN2_MASK,
.val = PMX_GPIO_PIN2_MASK,
},
};
static struct spear_modemux gpio0_pin2_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin2_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
.name = "gpio0_pin2_grp",
.pins = gpio0_pin2_pins,
.npins = ARRAY_SIZE(gpio0_pin2_pins),
.modemuxs = gpio0_pin2_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
};
/* gpio0_pin3_pins */
static const unsigned gpio0_pin3_pins[] = { 31 };
static struct spear_muxreg gpio0_pin3_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN3_MASK,
.val = PMX_GPIO_PIN3_MASK,
},
};
static struct spear_modemux gpio0_pin3_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin3_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
.name = "gpio0_pin3_grp",
.pins = gpio0_pin3_pins,
.npins = ARRAY_SIZE(gpio0_pin3_pins),
.modemuxs = gpio0_pin3_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
};
/* gpio0_pin4_pins */
static const unsigned gpio0_pin4_pins[] = { 32 };
static struct spear_muxreg gpio0_pin4_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN4_MASK,
.val = PMX_GPIO_PIN4_MASK,
},
};
static struct spear_modemux gpio0_pin4_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin4_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
.name = "gpio0_pin4_grp",
.pins = gpio0_pin4_pins,
.npins = ARRAY_SIZE(gpio0_pin4_pins),
.modemuxs = gpio0_pin4_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
};
/* gpio0_pin5_pins */
static const unsigned gpio0_pin5_pins[] = { 33 };
static struct spear_muxreg gpio0_pin5_muxreg[] = {
{
.reg = -1,
.mask = PMX_GPIO_PIN5_MASK,
.val = PMX_GPIO_PIN5_MASK,
},
};
static struct spear_modemux gpio0_pin5_modemux[] = {
{
.modes = ~0,
.muxregs = gpio0_pin5_muxreg,
.nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
},
};
struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
.name = "gpio0_pin5_grp",
.pins = gpio0_pin5_pins,
.npins = ARRAY_SIZE(gpio0_pin5_pins),
.modemuxs = gpio0_pin5_modemux,
.nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
};
static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
"gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
};
struct spear_function spear3xx_gpio0_function = {
.name = "gpio0",
.groups = gpio0_grps,
.ngroups = ARRAY_SIZE(gpio0_grps),
};
/* uart0_ext_pins */
static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
static struct spear_muxreg uart0_ext_muxreg[] = {
{
.reg = -1,
.mask = PMX_UART0_MODEM_MASK,
.val = PMX_UART0_MODEM_MASK,
},
};
static struct spear_modemux uart0_ext_modemux[] = {
{
.modes = ~0,
.muxregs = uart0_ext_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
},
};
struct spear_pingroup spear3xx_uart0_ext_pingroup = {
.name = "uart0_ext_grp",
.pins = uart0_ext_pins,
.npins = ARRAY_SIZE(uart0_ext_pins),
.modemuxs = uart0_ext_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
};
static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
struct spear_function spear3xx_uart0_ext_function = {
.name = "uart0_ext",
.groups = uart0_ext_grps,
.ngroups = ARRAY_SIZE(uart0_ext_grps),
};
/* uart0_pins */
static const unsigned uart0_pins[] = { 2, 3 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = -1,
.mask = PMX_UART0_MASK,
.val = PMX_UART0_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.modes = ~0,
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
struct spear_pingroup spear3xx_uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp" };
struct spear_function spear3xx_uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* timer_0_1_pins */
static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
static struct spear_muxreg timer_0_1_muxreg[] = {
{
.reg = -1,
.mask = PMX_TIMER_0_1_MASK,
.val = PMX_TIMER_0_1_MASK,
},
};
static struct spear_modemux timer_0_1_modemux[] = {
{
.modes = ~0,
.muxregs = timer_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
},
};
struct spear_pingroup spear3xx_timer_0_1_pingroup = {
.name = "timer_0_1_grp",
.pins = timer_0_1_pins,
.npins = ARRAY_SIZE(timer_0_1_pins),
.modemuxs = timer_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
};
static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
struct spear_function spear3xx_timer_0_1_function = {
.name = "timer_0_1",
.groups = timer_0_1_grps,
.ngroups = ARRAY_SIZE(timer_0_1_grps),
};
/* timer_2_3_pins */
static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
static struct spear_muxreg timer_2_3_muxreg[] = {
{
.reg = -1,
.mask = PMX_TIMER_2_3_MASK,
.val = PMX_TIMER_2_3_MASK,
},
};
static struct spear_modemux timer_2_3_modemux[] = {
{
.modes = ~0,
.muxregs = timer_2_3_muxreg,
.nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
},
};
struct spear_pingroup spear3xx_timer_2_3_pingroup = {
.name = "timer_2_3_grp",
.pins = timer_2_3_pins,
.npins = ARRAY_SIZE(timer_2_3_pins),
.modemuxs = timer_2_3_modemux,
.nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
};
static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
struct spear_function spear3xx_timer_2_3_function = {
.name = "timer_2_3",
.groups = timer_2_3_grps,
.ngroups = ARRAY_SIZE(timer_2_3_grps),
};
/* Define muxreg arrays */
DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
GPIO_PINGROUP(firda_pins),
GPIO_PINGROUP(i2c_pins),
GPIO_PINGROUP(ssp_cs_pins),
GPIO_PINGROUP(ssp_pins),
GPIO_PINGROUP(mii_pins),
GPIO_PINGROUP(gpio0_pin0_pins),
GPIO_PINGROUP(gpio0_pin1_pins),
GPIO_PINGROUP(gpio0_pin2_pins),
GPIO_PINGROUP(gpio0_pin3_pins),
GPIO_PINGROUP(gpio0_pin4_pins),
GPIO_PINGROUP(gpio0_pin5_pins),
GPIO_PINGROUP(uart0_ext_pins),
GPIO_PINGROUP(uart0_pins),
GPIO_PINGROUP(timer_0_1_pins),
GPIO_PINGROUP(timer_2_3_pins),
};
struct spear_pinctrl_machdata spear3xx_machdata = {
.pins = spear3xx_pins,
.npins = ARRAY_SIZE(spear3xx_pins),
.gpio_pingroups = spear3xx_gpio_pingroup,
.ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
};
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear3xx.c
|
/*
* Driver for the ST Microelectronics SPEAr1310 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"
#define DRIVER_NAME "spear1310-pinmux"
/* pins */
static const struct pinctrl_pin_desc spear1310_pins[] = {
SPEAR_PIN_0_TO_101,
SPEAR_PIN_102_TO_245,
};
/* registers */
#define PERIP_CFG 0x3B0
#define MCIF_SEL_SHIFT 5
#define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
#define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
#define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
#define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
#define PCIE_SATA_CFG 0x3A4
#define PCIE_SATA2_SEL_PCIE (0 << 31)
#define PCIE_SATA1_SEL_PCIE (0 << 30)
#define PCIE_SATA0_SEL_PCIE (0 << 29)
#define PCIE_SATA2_SEL_SATA (1 << 31)
#define PCIE_SATA1_SEL_SATA (1 << 30)
#define PCIE_SATA0_SEL_SATA (1 << 29)
#define SATA2_CFG_TX_CLK_EN (1 << 27)
#define SATA2_CFG_RX_CLK_EN (1 << 26)
#define SATA2_CFG_POWERUP_RESET (1 << 25)
#define SATA2_CFG_PM_CLK_EN (1 << 24)
#define SATA1_CFG_TX_CLK_EN (1 << 23)
#define SATA1_CFG_RX_CLK_EN (1 << 22)
#define SATA1_CFG_POWERUP_RESET (1 << 21)
#define SATA1_CFG_PM_CLK_EN (1 << 20)
#define SATA0_CFG_TX_CLK_EN (1 << 19)
#define SATA0_CFG_RX_CLK_EN (1 << 18)
#define SATA0_CFG_POWERUP_RESET (1 << 17)
#define SATA0_CFG_PM_CLK_EN (1 << 16)
#define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
#define PCIE2_CFG_POWERUP_RESET (1 << 10)
#define PCIE2_CFG_CORE_CLK_EN (1 << 9)
#define PCIE2_CFG_AUX_CLK_EN (1 << 8)
#define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
#define PCIE1_CFG_POWERUP_RESET (1 << 6)
#define PCIE1_CFG_CORE_CLK_EN (1 << 5)
#define PCIE1_CFG_AUX_CLK_EN (1 << 4)
#define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
#define PCIE0_CFG_POWERUP_RESET (1 << 2)
#define PCIE0_CFG_CORE_CLK_EN (1 << 1)
#define PCIE0_CFG_AUX_CLK_EN (1 << 0)
#define PAD_FUNCTION_EN_0 0x650
#define PMX_UART0_MASK (1 << 1)
#define PMX_I2C0_MASK (1 << 2)
#define PMX_I2S0_MASK (1 << 3)
#define PMX_SSP0_MASK (1 << 4)
#define PMX_CLCD1_MASK (1 << 5)
#define PMX_EGPIO00_MASK (1 << 6)
#define PMX_EGPIO01_MASK (1 << 7)
#define PMX_EGPIO02_MASK (1 << 8)
#define PMX_EGPIO03_MASK (1 << 9)
#define PMX_EGPIO04_MASK (1 << 10)
#define PMX_EGPIO05_MASK (1 << 11)
#define PMX_EGPIO06_MASK (1 << 12)
#define PMX_EGPIO07_MASK (1 << 13)
#define PMX_EGPIO08_MASK (1 << 14)
#define PMX_EGPIO09_MASK (1 << 15)
#define PMX_SMI_MASK (1 << 16)
#define PMX_NAND8_MASK (1 << 17)
#define PMX_GMIICLK_MASK (1 << 18)
#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
#define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
#define PMX_GMIID47_MASK (1 << 21)
#define PMX_MDC_MDIO_MASK (1 << 22)
#define PMX_MCI_DATA8_15_MASK (1 << 23)
#define PMX_NFAD23_MASK (1 << 24)
#define PMX_NFAD24_MASK (1 << 25)
#define PMX_NFAD25_MASK (1 << 26)
#define PMX_NFCE3_MASK (1 << 27)
#define PMX_NFWPRT3_MASK (1 << 28)
#define PMX_NFRSTPWDWN0_MASK (1 << 29)
#define PMX_NFRSTPWDWN1_MASK (1 << 30)
#define PMX_NFRSTPWDWN2_MASK (1 << 31)
#define PAD_FUNCTION_EN_1 0x654
#define PMX_NFRSTPWDWN3_MASK (1 << 0)
#define PMX_SMINCS2_MASK (1 << 1)
#define PMX_SMINCS3_MASK (1 << 2)
#define PMX_CLCD2_MASK (1 << 3)
#define PMX_KBD_ROWCOL68_MASK (1 << 4)
#define PMX_EGPIO10_MASK (1 << 5)
#define PMX_EGPIO11_MASK (1 << 6)
#define PMX_EGPIO12_MASK (1 << 7)
#define PMX_EGPIO13_MASK (1 << 8)
#define PMX_EGPIO14_MASK (1 << 9)
#define PMX_EGPIO15_MASK (1 << 10)
#define PMX_UART0_MODEM_MASK (1 << 11)
#define PMX_GPT0_TMR0_MASK (1 << 12)
#define PMX_GPT0_TMR1_MASK (1 << 13)
#define PMX_GPT1_TMR0_MASK (1 << 14)
#define PMX_GPT1_TMR1_MASK (1 << 15)
#define PMX_I2S1_MASK (1 << 16)
#define PMX_KBD_ROWCOL25_MASK (1 << 17)
#define PMX_NFIO8_15_MASK (1 << 18)
#define PMX_KBD_COL1_MASK (1 << 19)
#define PMX_NFCE1_MASK (1 << 20)
#define PMX_KBD_COL0_MASK (1 << 21)
#define PMX_NFCE2_MASK (1 << 22)
#define PMX_KBD_ROW1_MASK (1 << 23)
#define PMX_NFWPRT1_MASK (1 << 24)
#define PMX_KBD_ROW0_MASK (1 << 25)
#define PMX_NFWPRT2_MASK (1 << 26)
#define PMX_MCIDATA0_MASK (1 << 27)
#define PMX_MCIDATA1_MASK (1 << 28)
#define PMX_MCIDATA2_MASK (1 << 29)
#define PMX_MCIDATA3_MASK (1 << 30)
#define PMX_MCIDATA4_MASK (1 << 31)
#define PAD_FUNCTION_EN_2 0x658
#define PMX_MCIDATA5_MASK (1 << 0)
#define PMX_MCIDATA6_MASK (1 << 1)
#define PMX_MCIDATA7_MASK (1 << 2)
#define PMX_MCIDATA1SD_MASK (1 << 3)
#define PMX_MCIDATA2SD_MASK (1 << 4)
#define PMX_MCIDATA3SD_MASK (1 << 5)
#define PMX_MCIADDR0ALE_MASK (1 << 6)
#define PMX_MCIADDR1CLECLK_MASK (1 << 7)
#define PMX_MCIADDR2_MASK (1 << 8)
#define PMX_MCICECF_MASK (1 << 9)
#define PMX_MCICEXD_MASK (1 << 10)
#define PMX_MCICESDMMC_MASK (1 << 11)
#define PMX_MCICDCF1_MASK (1 << 12)
#define PMX_MCICDCF2_MASK (1 << 13)
#define PMX_MCICDXD_MASK (1 << 14)
#define PMX_MCICDSDMMC_MASK (1 << 15)
#define PMX_MCIDATADIR_MASK (1 << 16)
#define PMX_MCIDMARQWP_MASK (1 << 17)
#define PMX_MCIIORDRE_MASK (1 << 18)
#define PMX_MCIIOWRWE_MASK (1 << 19)
#define PMX_MCIRESETCF_MASK (1 << 20)
#define PMX_MCICS0CE_MASK (1 << 21)
#define PMX_MCICFINTR_MASK (1 << 22)
#define PMX_MCIIORDY_MASK (1 << 23)
#define PMX_MCICS1_MASK (1 << 24)
#define PMX_MCIDMAACK_MASK (1 << 25)
#define PMX_MCISDCMD_MASK (1 << 26)
#define PMX_MCILEDS_MASK (1 << 27)
#define PMX_TOUCH_XY_MASK (1 << 28)
#define PMX_SSP0_CS0_MASK (1 << 29)
#define PMX_SSP0_CS1_2_MASK (1 << 30)
#define PAD_DIRECTION_SEL_0 0x65C
#define PAD_DIRECTION_SEL_1 0x660
#define PAD_DIRECTION_SEL_2 0x664
/* combined macros */
#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_RXCLK_RDV_TXEN_D03_MASK | \
PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
PMX_EGPIO02_MASK | \
PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
PMX_EGPIO09_MASK)
#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
PMX_KBD_COL1_MASK)
#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
PMX_NFCE3_MASK)
#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
#define PMX_MCIFALL_1_MASK 0xF8000000
#define PMX_MCIFALL_2_MASK 0x0FFFFFFF
#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
PMX_NFCE2_MASK)
#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
PMX_GMIID47_MASK)
#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
PMX_SSP0_CS1_2_MASK)
#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
PCIE##x##_CFG_AUX_CLK_EN | \
PCIE##x##_CFG_CORE_CLK_EN | \
PCIE##x##_CFG_POWERUP_RESET | \
PCIE##x##_CFG_DEVICE_PRESENT)
#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
SATA##x##_CFG_PM_CLK_EN | \
SATA##x##_CFG_POWERUP_RESET | \
SATA##x##_CFG_RX_CLK_EN | \
SATA##x##_CFG_TX_CLK_EN)
/* Pad multiplexing for i2c0 device */
static const unsigned i2c0_pins[] = { 102, 103 };
static struct spear_muxreg i2c0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = PMX_I2C0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_I2C0_MASK,
.val = PMX_I2C0_MASK,
},
};
static struct spear_modemux i2c0_modemux[] = {
{
.muxregs = i2c0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c0_muxreg),
},
};
static struct spear_pingroup i2c0_pingroup = {
.name = "i2c0_grp",
.pins = i2c0_pins,
.npins = ARRAY_SIZE(i2c0_pins),
.modemuxs = i2c0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c0_modemux),
};
static const char *const i2c0_grps[] = { "i2c0_grp" };
static struct spear_function i2c0_function = {
.name = "i2c0",
.groups = i2c0_grps,
.ngroups = ARRAY_SIZE(i2c0_grps),
};
/* Pad multiplexing for ssp0 device */
static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
static struct spear_muxreg ssp0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SSP0_MASK,
.val = PMX_SSP0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_SSP0_MASK,
.val = PMX_SSP0_MASK,
},
};
static struct spear_modemux ssp0_modemux[] = {
{
.muxregs = ssp0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_muxreg),
},
};
static struct spear_pingroup ssp0_pingroup = {
.name = "ssp0_grp",
.pins = ssp0_pins,
.npins = ARRAY_SIZE(ssp0_pins),
.modemuxs = ssp0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_modemux),
};
/* Pad multiplexing for ssp0_cs0 device */
static const unsigned ssp0_cs0_pins[] = { 96 };
static struct spear_muxreg ssp0_cs0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS0_MASK,
.val = PMX_SSP0_CS0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_SSP0_CS0_MASK,
.val = PMX_SSP0_CS0_MASK,
},
};
static struct spear_modemux ssp0_cs0_modemux[] = {
{
.muxregs = ssp0_cs0_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
},
};
static struct spear_pingroup ssp0_cs0_pingroup = {
.name = "ssp0_cs0_grp",
.pins = ssp0_cs0_pins,
.npins = ARRAY_SIZE(ssp0_cs0_pins),
.modemuxs = ssp0_cs0_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
};
/* ssp0_cs1_2 device */
static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_SSP0_CS1_2_MASK,
.val = PMX_SSP0_CS1_2_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_SSP0_CS1_2_MASK,
.val = PMX_SSP0_CS1_2_MASK,
},
};
static struct spear_modemux ssp0_cs1_2_modemux[] = {
{
.muxregs = ssp0_cs1_2_muxreg,
.nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
},
};
static struct spear_pingroup ssp0_cs1_2_pingroup = {
.name = "ssp0_cs1_2_grp",
.pins = ssp0_cs1_2_pins,
.npins = ARRAY_SIZE(ssp0_cs1_2_pins),
.modemuxs = ssp0_cs1_2_modemux,
.nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
};
static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
"ssp0_cs1_2_grp" };
static struct spear_function ssp0_function = {
.name = "ssp0",
.groups = ssp0_grps,
.ngroups = ARRAY_SIZE(ssp0_grps),
};
/* Pad multiplexing for i2s0 device */
static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
static struct spear_muxreg i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = PMX_I2S0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_I2S0_MASK,
.val = PMX_I2S0_MASK,
},
};
static struct spear_modemux i2s0_modemux[] = {
{
.muxregs = i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2s0_muxreg),
},
};
static struct spear_pingroup i2s0_pingroup = {
.name = "i2s0_grp",
.pins = i2s0_pins,
.npins = ARRAY_SIZE(i2s0_pins),
.modemuxs = i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2s0_modemux),
};
static const char *const i2s0_grps[] = { "i2s0_grp" };
static struct spear_function i2s0_function = {
.name = "i2s0",
.groups = i2s0_grps,
.ngroups = ARRAY_SIZE(i2s0_grps),
};
/* Pad multiplexing for i2s1 device */
static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
static struct spear_muxreg i2s1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK,
.val = PMX_I2S1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_I2S1_MASK,
.val = PMX_I2S1_MASK,
},
};
static struct spear_modemux i2s1_modemux[] = {
{
.muxregs = i2s1_muxreg,
.nmuxregs = ARRAY_SIZE(i2s1_muxreg),
},
};
static struct spear_pingroup i2s1_pingroup = {
.name = "i2s1_grp",
.pins = i2s1_pins,
.npins = ARRAY_SIZE(i2s1_pins),
.modemuxs = i2s1_modemux,
.nmodemuxs = ARRAY_SIZE(i2s1_modemux),
};
static const char *const i2s1_grps[] = { "i2s1_grp" };
static struct spear_function i2s1_function = {
.name = "i2s1",
.groups = i2s1_grps,
.ngroups = ARRAY_SIZE(i2s1_grps),
};
/* Pad multiplexing for clcd device */
static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
135, 136, 137, 138, 139, 140, 141, 142 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
static struct spear_muxreg clcd_high_res_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_CLCD2_MASK,
.val = PMX_CLCD2_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_CLCD2_MASK,
.val = PMX_CLCD2_MASK,
},
};
static struct spear_modemux clcd_high_res_modemux[] = {
{
.muxregs = clcd_high_res_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
},
};
static struct spear_pingroup clcd_high_res_pingroup = {
.name = "clcd_high_res_grp",
.pins = clcd_high_res_pins,
.npins = ARRAY_SIZE(clcd_high_res_pins),
.modemuxs = clcd_high_res_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
146, 147, 148, 149, 150, 151, 152 };
static struct spear_muxreg arm_gpio_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_EGPIO_0_GRP_MASK,
.val = PMX_EGPIO_0_GRP_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_EGPIO_1_GRP_MASK,
.val = PMX_EGPIO_1_GRP_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_EGPIO_0_GRP_MASK,
.val = PMX_EGPIO_0_GRP_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_EGPIO_1_GRP_MASK,
.val = PMX_EGPIO_1_GRP_MASK,
},
};
static struct spear_modemux arm_gpio_modemux[] = {
{
.muxregs = arm_gpio_muxreg,
.nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
},
};
static struct spear_pingroup arm_gpio_pingroup = {
.name = "arm_gpio_grp",
.pins = arm_gpio_pins,
.npins = ARRAY_SIZE(arm_gpio_pins),
.modemuxs = arm_gpio_modemux,
.nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
};
static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
static struct spear_function arm_gpio_function = {
.name = "arm_gpio",
.groups = arm_gpio_grps,
.ngroups = ARRAY_SIZE(arm_gpio_grps),
};
/* Pad multiplexing for smi 2 chips device */
static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
static struct spear_muxreg smi_2_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
},
};
static struct spear_modemux smi_2_chips_modemux[] = {
{
.muxregs = smi_2_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
},
};
static struct spear_pingroup smi_2_chips_pingroup = {
.name = "smi_2_chips_grp",
.pins = smi_2_chips_pins,
.npins = ARRAY_SIZE(smi_2_chips_pins),
.modemuxs = smi_2_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
};
static const unsigned smi_4_chips_pins[] = { 54, 55 };
static struct spear_muxreg smi_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
.val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
},
};
static struct spear_modemux smi_4_chips_modemux[] = {
{
.muxregs = smi_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
},
};
static struct spear_pingroup smi_4_chips_pingroup = {
.name = "smi_4_chips_grp",
.pins = smi_4_chips_pins,
.npins = ARRAY_SIZE(smi_4_chips_pins),
.modemuxs = smi_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
};
static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
static struct spear_function smi_function = {
.name = "smi",
.groups = smi_grps,
.ngroups = ARRAY_SIZE(smi_grps),
};
/* Pad multiplexing for gmii device */
static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
195, 196, 197, 198, 199, 200 };
static struct spear_muxreg gmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_GMII_MASK,
.val = PMX_GMII_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_GMII_MASK,
.val = PMX_GMII_MASK,
},
};
static struct spear_modemux gmii_modemux[] = {
{
.muxregs = gmii_muxreg,
.nmuxregs = ARRAY_SIZE(gmii_muxreg),
},
};
static struct spear_pingroup gmii_pingroup = {
.name = "gmii_grp",
.pins = gmii_pins,
.npins = ARRAY_SIZE(gmii_pins),
.modemuxs = gmii_modemux,
.nmodemuxs = ARRAY_SIZE(gmii_modemux),
};
static const char *const gmii_grps[] = { "gmii_grp" };
static struct spear_function gmii_function = {
.name = "gmii",
.groups = gmii_grps,
.ngroups = ARRAY_SIZE(gmii_grps),
};
/* Pad multiplexing for rgmii device */
static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
static struct spear_muxreg rgmii_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_RGMII_REG0_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_RGMII_REG1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_RGMII_REG2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_RGMII_REG0_MASK,
.val = PMX_RGMII_REG0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_RGMII_REG1_MASK,
.val = PMX_RGMII_REG1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_RGMII_REG2_MASK,
.val = PMX_RGMII_REG2_MASK,
},
};
static struct spear_modemux rgmii_modemux[] = {
{
.muxregs = rgmii_muxreg,
.nmuxregs = ARRAY_SIZE(rgmii_muxreg),
},
};
static struct spear_pingroup rgmii_pingroup = {
.name = "rgmii_grp",
.pins = rgmii_pins,
.npins = ARRAY_SIZE(rgmii_pins),
.modemuxs = rgmii_modemux,
.nmodemuxs = ARRAY_SIZE(rgmii_modemux),
};
static const char *const rgmii_grps[] = { "rgmii_grp" };
static struct spear_function rgmii_function = {
.name = "rgmii",
.groups = rgmii_grps,
.ngroups = ARRAY_SIZE(rgmii_grps),
};
/* Pad multiplexing for smii_0_1_2 device */
static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53, 54, 55 };
static struct spear_muxreg smii_0_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_SMII_0_1_2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_SMII_0_1_2_MASK,
.val = PMX_SMII_0_1_2_MASK,
},
};
static struct spear_modemux smii_0_1_2_modemux[] = {
{
.muxregs = smii_0_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
},
};
static struct spear_pingroup smii_0_1_2_pingroup = {
.name = "smii_0_1_2_grp",
.pins = smii_0_1_2_pins,
.npins = ARRAY_SIZE(smii_0_1_2_pins),
.modemuxs = smii_0_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
};
static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
static struct spear_function smii_0_1_2_function = {
.name = "smii_0_1_2",
.groups = smii_0_1_2_grps,
.ngroups = ARRAY_SIZE(smii_0_1_2_grps),
};
/* Pad multiplexing for ras_mii_txclk device */
static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
static struct spear_muxreg ras_mii_txclk_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFCE2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_NFCE2_MASK,
.val = PMX_NFCE2_MASK,
},
};
static struct spear_modemux ras_mii_txclk_modemux[] = {
{
.muxregs = ras_mii_txclk_muxreg,
.nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
},
};
static struct spear_pingroup ras_mii_txclk_pingroup = {
.name = "ras_mii_txclk_grp",
.pins = ras_mii_txclk_pins,
.npins = ARRAY_SIZE(ras_mii_txclk_pins),
.modemuxs = ras_mii_txclk_modemux,
.nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
};
static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
static struct spear_function ras_mii_txclk_function = {
.name = "ras_mii_txclk",
.groups = ras_mii_txclk_grps,
.ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
};
/* Pad multiplexing for nand 8bit device (cs0 only) */
static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
212 };
static struct spear_muxreg nand_8bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NAND8BIT_0_MASK,
.val = PMX_NAND8BIT_0_MASK,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND8BIT_1_MASK,
.val = PMX_NAND8BIT_1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_NAND8BIT_0_MASK,
.val = PMX_NAND8BIT_0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_NAND8BIT_1_MASK,
.val = PMX_NAND8BIT_1_MASK,
},
};
static struct spear_modemux nand_8bit_modemux[] = {
{
.muxregs = nand_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
},
};
static struct spear_pingroup nand_8bit_pingroup = {
.name = "nand_8bit_grp",
.pins = nand_8bit_pins,
.npins = ARRAY_SIZE(nand_8bit_pins),
.modemuxs = nand_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
};
/* Pad multiplexing for nand 16bit device */
static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
210 };
static struct spear_muxreg nand_16bit_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND16BIT_1_MASK,
.val = PMX_NAND16BIT_1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_NAND16BIT_1_MASK,
.val = PMX_NAND16BIT_1_MASK,
},
};
static struct spear_modemux nand_16bit_modemux[] = {
{
.muxregs = nand_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
},
};
static struct spear_pingroup nand_16bit_pingroup = {
.name = "nand_16bit_grp",
.pins = nand_16bit_pins,
.npins = ARRAY_SIZE(nand_16bit_pins),
.modemuxs = nand_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
};
/* Pad multiplexing for nand 4 chips */
static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
static struct spear_muxreg nand_4_chips_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NAND_4CHIPS_MASK,
.val = PMX_NAND_4CHIPS_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_NAND_4CHIPS_MASK,
.val = PMX_NAND_4CHIPS_MASK,
},
};
static struct spear_modemux nand_4_chips_modemux[] = {
{
.muxregs = nand_4_chips_muxreg,
.nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
},
};
static struct spear_pingroup nand_4_chips_pingroup = {
.name = "nand_4_chips_grp",
.pins = nand_4_chips_pins,
.npins = ARRAY_SIZE(nand_4_chips_pins),
.modemuxs = nand_4_chips_modemux,
.nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
};
static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
"nand_4_chips_grp" };
static struct spear_function nand_function = {
.name = "nand",
.groups = nand_grps,
.ngroups = ARRAY_SIZE(nand_grps),
};
/* Pad multiplexing for keyboard_6x6 device */
static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212 };
static struct spear_muxreg keyboard_6x6_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
PMX_NFWPRT2_MASK,
.val = PMX_KEYBOARD_6X6_MASK,
},
};
static struct spear_modemux keyboard_6x6_modemux[] = {
{
.muxregs = keyboard_6x6_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
},
};
static struct spear_pingroup keyboard_6x6_pingroup = {
.name = "keyboard_6x6_grp",
.pins = keyboard_6x6_pins,
.npins = ARRAY_SIZE(keyboard_6x6_pins),
.modemuxs = keyboard_6x6_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
};
/* Pad multiplexing for keyboard_rowcol6_8 device */
static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL68_MASK,
.val = PMX_KBD_ROWCOL68_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_KBD_ROWCOL68_MASK,
.val = PMX_KBD_ROWCOL68_MASK,
},
};
static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
{
.muxregs = keyboard_rowcol6_8_muxreg,
.nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
},
};
static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
.name = "keyboard_rowcol6_8_grp",
.pins = keyboard_rowcol6_8_pins,
.npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
.modemuxs = keyboard_rowcol6_8_modemux,
.nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
};
static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
"keyboard_rowcol6_8_grp" };
static struct spear_function keyboard_function = {
.name = "keyboard",
.groups = keyboard_grps,
.ngroups = ARRAY_SIZE(keyboard_grps),
};
/* Pad multiplexing for uart0 device */
static const unsigned uart0_pins[] = { 100, 101 };
static struct spear_muxreg uart0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_UART0_MASK,
.val = PMX_UART0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_UART0_MASK,
.val = PMX_UART0_MASK,
},
};
static struct spear_modemux uart0_modemux[] = {
{
.muxregs = uart0_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
},
};
static struct spear_pingroup uart0_pingroup = {
.name = "uart0_grp",
.pins = uart0_pins,
.npins = ARRAY_SIZE(uart0_pins),
.modemuxs = uart0_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
};
/* Pad multiplexing for uart0_modem device */
static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
static struct spear_muxreg uart0_modem_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_UART0_MODEM_MASK,
.val = PMX_UART0_MODEM_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_UART0_MODEM_MASK,
.val = PMX_UART0_MODEM_MASK,
},
};
static struct spear_modemux uart0_modem_modemux[] = {
{
.muxregs = uart0_modem_muxreg,
.nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
},
};
static struct spear_pingroup uart0_modem_pingroup = {
.name = "uart0_modem_grp",
.pins = uart0_modem_pins,
.npins = ARRAY_SIZE(uart0_modem_pins),
.modemuxs = uart0_modem_modemux,
.nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
};
static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
static struct spear_function uart0_function = {
.name = "uart0",
.groups = uart0_grps,
.ngroups = ARRAY_SIZE(uart0_grps),
};
/* Pad multiplexing for gpt0_tmr0 device */
static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
static struct spear_muxreg gpt0_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR0_MASK,
.val = PMX_GPT0_TMR0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_GPT0_TMR0_MASK,
.val = PMX_GPT0_TMR0_MASK,
},
};
static struct spear_modemux gpt0_tmr0_modemux[] = {
{
.muxregs = gpt0_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
},
};
static struct spear_pingroup gpt0_tmr0_pingroup = {
.name = "gpt0_tmr0_grp",
.pins = gpt0_tmr0_pins,
.npins = ARRAY_SIZE(gpt0_tmr0_pins),
.modemuxs = gpt0_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
};
/* Pad multiplexing for gpt0_tmr1 device */
static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
static struct spear_muxreg gpt0_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT0_TMR1_MASK,
.val = PMX_GPT0_TMR1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_GPT0_TMR1_MASK,
.val = PMX_GPT0_TMR1_MASK,
},
};
static struct spear_modemux gpt0_tmr1_modemux[] = {
{
.muxregs = gpt0_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
},
};
static struct spear_pingroup gpt0_tmr1_pingroup = {
.name = "gpt0_tmr1_grp",
.pins = gpt0_tmr1_pins,
.npins = ARRAY_SIZE(gpt0_tmr1_pins),
.modemuxs = gpt0_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
};
static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
static struct spear_function gpt0_function = {
.name = "gpt0",
.groups = gpt0_grps,
.ngroups = ARRAY_SIZE(gpt0_grps),
};
/* Pad multiplexing for gpt1_tmr0 device */
static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
static struct spear_muxreg gpt1_tmr0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR0_MASK,
.val = PMX_GPT1_TMR0_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_GPT1_TMR0_MASK,
.val = PMX_GPT1_TMR0_MASK,
},
};
static struct spear_modemux gpt1_tmr0_modemux[] = {
{
.muxregs = gpt1_tmr0_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
},
};
static struct spear_pingroup gpt1_tmr0_pingroup = {
.name = "gpt1_tmr0_grp",
.pins = gpt1_tmr0_pins,
.npins = ARRAY_SIZE(gpt1_tmr0_pins),
.modemuxs = gpt1_tmr0_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
};
/* Pad multiplexing for gpt1_tmr1 device */
static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
static struct spear_muxreg gpt1_tmr1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_GPT1_TMR1_MASK,
.val = PMX_GPT1_TMR1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_GPT1_TMR1_MASK,
.val = PMX_GPT1_TMR1_MASK,
},
};
static struct spear_modemux gpt1_tmr1_modemux[] = {
{
.muxregs = gpt1_tmr1_muxreg,
.nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
},
};
static struct spear_pingroup gpt1_tmr1_pingroup = {
.name = "gpt1_tmr1_grp",
.pins = gpt1_tmr1_pins,
.npins = ARRAY_SIZE(gpt1_tmr1_pins),
.modemuxs = gpt1_tmr1_modemux,
.nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
};
static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
static struct spear_function gpt1_function = {
.name = "gpt1",
.groups = gpt1_grps,
.ngroups = ARRAY_SIZE(gpt1_grps),
};
/* Pad multiplexing for mcif device */
static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
243, 244, 245 };
#define MCIF_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = PMX_MCI_DATA8_15_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
PMX_NFWPRT2_MASK, \
.val = PMX_MCIFALL_1_MASK, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_MCIFALL_2_MASK, \
.val = PMX_MCIFALL_2_MASK, \
}, { \
.reg = PAD_DIRECTION_SEL_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = PMX_MCI_DATA8_15_MASK, \
}, { \
.reg = PAD_DIRECTION_SEL_1, \
.mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
PMX_NFWPRT2_MASK, \
.val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
PMX_NFWPRT2_MASK, \
}, { \
.reg = PAD_DIRECTION_SEL_2, \
.mask = PMX_MCIFALL_2_MASK, \
.val = PMX_MCIFALL_2_MASK, \
}
/* sdhci device */
static struct spear_muxreg sdhci_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_SD,
},
};
static struct spear_modemux sdhci_modemux[] = {
{
.muxregs = sdhci_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_muxreg),
},
};
static struct spear_pingroup sdhci_pingroup = {
.name = "sdhci_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = sdhci_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* cf device */
static struct spear_muxreg cf_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_CF,
},
};
static struct spear_modemux cf_modemux[] = {
{
.muxregs = cf_muxreg,
.nmuxregs = ARRAY_SIZE(cf_muxreg),
},
};
static struct spear_pingroup cf_pingroup = {
.name = "cf_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = cf_modemux,
.nmodemuxs = ARRAY_SIZE(cf_modemux),
};
static const char *const cf_grps[] = { "cf_grp" };
static struct spear_function cf_function = {
.name = "cf",
.groups = cf_grps,
.ngroups = ARRAY_SIZE(cf_grps),
};
/* xd device */
static struct spear_muxreg xd_muxreg[] = {
MCIF_MUXREG,
{
.reg = PERIP_CFG,
.mask = MCIF_SEL_MASK,
.val = MCIF_SEL_XD,
},
};
static struct spear_modemux xd_modemux[] = {
{
.muxregs = xd_muxreg,
.nmuxregs = ARRAY_SIZE(xd_muxreg),
},
};
static struct spear_pingroup xd_pingroup = {
.name = "xd_grp",
.pins = mcif_pins,
.npins = ARRAY_SIZE(mcif_pins),
.modemuxs = xd_modemux,
.nmodemuxs = ARRAY_SIZE(xd_modemux),
};
static const char *const xd_grps[] = { "xd_grp" };
static struct spear_function xd_function = {
.name = "xd",
.groups = xd_grps,
.ngroups = ARRAY_SIZE(xd_grps),
};
/* Pad multiplexing for touch_xy device */
static const unsigned touch_xy_pins[] = { 97 };
static struct spear_muxreg touch_xy_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_TOUCH_XY_MASK,
.val = PMX_TOUCH_XY_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_TOUCH_XY_MASK,
.val = PMX_TOUCH_XY_MASK,
},
};
static struct spear_modemux touch_xy_modemux[] = {
{
.muxregs = touch_xy_muxreg,
.nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
},
};
static struct spear_pingroup touch_xy_pingroup = {
.name = "touch_xy_grp",
.pins = touch_xy_pins,
.npins = ARRAY_SIZE(touch_xy_pins),
.modemuxs = touch_xy_modemux,
.nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
};
static const char *const touch_xy_grps[] = { "touch_xy_grp" };
static struct spear_function touch_xy_function = {
.name = "touchscreen",
.groups = touch_xy_grps,
.ngroups = ARRAY_SIZE(touch_xy_grps),
};
/* Pad multiplexing for uart1 device */
/* Muxed with I2C */
static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2C0_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_I2C0_MASK,
.val = PMX_I2C0_MASK,
},
};
static struct spear_modemux uart1_dis_i2c_modemux[] = {
{
.muxregs = uart1_dis_i2c_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
},
};
static struct spear_pingroup uart_1_dis_i2c_pingroup = {
.name = "uart1_disable_i2c_grp",
.pins = uart1_dis_i2c_pins,
.npins = ARRAY_SIZE(uart1_dis_i2c_pins),
.modemuxs = uart1_dis_i2c_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
};
/* Muxed with SD/MMC */
static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
static struct spear_muxreg uart1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA1_MASK |
PMX_MCIDATA2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_MCIDATA1_MASK |
PMX_MCIDATA2_MASK,
.val = PMX_MCIDATA1_MASK |
PMX_MCIDATA2_MASK,
},
};
static struct spear_modemux uart1_dis_sd_modemux[] = {
{
.muxregs = uart1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
},
};
static struct spear_pingroup uart_1_dis_sd_pingroup = {
.name = "uart1_disable_sd_grp",
.pins = uart1_dis_sd_pins,
.npins = ARRAY_SIZE(uart1_dis_sd_pins),
.modemuxs = uart1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
};
static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
"uart1_disable_sd_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* Pad multiplexing for uart2_3 device */
static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
static struct spear_muxreg uart2_3_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_I2S0_MASK,
.val = PMX_I2S0_MASK,
},
};
static struct spear_modemux uart2_3_modemux[] = {
{
.muxregs = uart2_3_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
},
};
static struct spear_pingroup uart_2_3_pingroup = {
.name = "uart2_3_grp",
.pins = uart2_3_pins,
.npins = ARRAY_SIZE(uart2_3_pins),
.modemuxs = uart2_3_modemux,
.nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
};
static const char *const uart2_3_grps[] = { "uart2_3_grp" };
static struct spear_function uart2_3_function = {
.name = "uart2_3",
.groups = uart2_3_grps,
.ngroups = ARRAY_SIZE(uart2_3_grps),
};
/* Pad multiplexing for uart4 device */
static const unsigned uart4_pins[] = { 108, 113 };
static struct spear_muxreg uart4_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
.val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
},
};
static struct spear_modemux uart4_modemux[] = {
{
.muxregs = uart4_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_muxreg),
},
};
static struct spear_pingroup uart_4_pingroup = {
.name = "uart4_grp",
.pins = uart4_pins,
.npins = ARRAY_SIZE(uart4_pins),
.modemuxs = uart4_modemux,
.nmodemuxs = ARRAY_SIZE(uart4_modemux),
};
static const char *const uart4_grps[] = { "uart4_grp" };
static struct spear_function uart4_function = {
.name = "uart4",
.groups = uart4_grps,
.ngroups = ARRAY_SIZE(uart4_grps),
};
/* Pad multiplexing for uart5 device */
static const unsigned uart5_pins[] = { 114, 115 };
static struct spear_muxreg uart5_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux uart5_modemux[] = {
{
.muxregs = uart5_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_muxreg),
},
};
static struct spear_pingroup uart_5_pingroup = {
.name = "uart5_grp",
.pins = uart5_pins,
.npins = ARRAY_SIZE(uart5_pins),
.modemuxs = uart5_modemux,
.nmodemuxs = ARRAY_SIZE(uart5_modemux),
};
static const char *const uart5_grps[] = { "uart5_grp" };
static struct spear_function uart5_function = {
.name = "uart5",
.groups = uart5_grps,
.ngroups = ARRAY_SIZE(uart5_grps),
};
/* Pad multiplexing for rs485_0_1_tdm_0_1 device */
static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
136, 137 };
static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
{
.muxregs = rs485_0_1_tdm_0_1_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
},
};
static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
.name = "rs485_0_1_tdm_0_1_grp",
.pins = rs485_0_1_tdm_0_1_pins,
.npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
.modemuxs = rs485_0_1_tdm_0_1_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
};
static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
static struct spear_function rs485_0_1_tdm_0_1_function = {
.name = "rs485_0_1_tdm_0_1",
.groups = rs485_0_1_tdm_0_1_grps,
.ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
};
/* Pad multiplexing for i2c_1_2 device */
static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
static struct spear_muxreg i2c_1_2_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_CLCD1_MASK,
.val = PMX_CLCD1_MASK,
},
};
static struct spear_modemux i2c_1_2_modemux[] = {
{
.muxregs = i2c_1_2_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
},
};
static struct spear_pingroup i2c_1_2_pingroup = {
.name = "i2c_1_2_grp",
.pins = i2c_1_2_pins,
.npins = ARRAY_SIZE(i2c_1_2_pins),
.modemuxs = i2c_1_2_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
};
static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
static struct spear_function i2c_1_2_function = {
.name = "i2c_1_2",
.groups = i2c_1_2_grps,
.ngroups = ARRAY_SIZE(i2c_1_2_grps),
};
/* Pad multiplexing for i2c3_dis_smi_clcd device */
/* Muxed with SMI & CLCD */
static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
.val = PMX_CLCD1_MASK | PMX_SMI_MASK,
},
};
static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
{
.muxregs = i2c3_dis_smi_clcd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
},
};
static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
.name = "i2c3_dis_smi_clcd_grp",
.pins = i2c3_dis_smi_clcd_pins,
.npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
.modemuxs = i2c3_dis_smi_clcd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
};
/* Pad multiplexing for i2c3_dis_sd_i2s0 device */
/* Muxed with SD/MMC & I2S1 */
static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
.val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
},
};
static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
{
.muxregs = i2c3_dis_sd_i2s0_muxreg,
.nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
},
};
static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
.name = "i2c3_dis_sd_i2s0_grp",
.pins = i2c3_dis_sd_i2s0_pins,
.npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
.modemuxs = i2c3_dis_sd_i2s0_modemux,
.nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
};
static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
"i2c3_dis_sd_i2s0_grp" };
static struct spear_function i2c3_unction = {
.name = "i2c3_i2s1",
.groups = i2c3_grps,
.ngroups = ARRAY_SIZE(i2c3_grps),
};
/* Pad multiplexing for i2c_4_5_dis_smi device */
/* Muxed with SMI */
static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_SMI_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_SMI_MASK,
.val = PMX_SMI_MASK,
},
};
static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
{
.muxregs = i2c_4_5_dis_smi_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
},
};
static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
.name = "i2c_4_5_dis_smi_grp",
.pins = i2c_4_5_dis_smi_pins,
.npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
.modemuxs = i2c_4_5_dis_smi_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
};
/* Pad multiplexing for i2c4_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_MCIDATA4_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA5_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_MCIDATA4_MASK,
.val = PMX_MCIDATA4_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCIDATA5_MASK,
.val = PMX_MCIDATA5_MASK,
},
};
static struct spear_modemux i2c4_dis_sd_modemux[] = {
{
.muxregs = i2c4_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c4_dis_sd_pingroup = {
.name = "i2c4_dis_sd_grp",
.pins = i2c4_dis_sd_pins,
.npins = ARRAY_SIZE(i2c4_dis_sd_pins),
.modemuxs = i2c4_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
};
/* Pad multiplexing for i2c5_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIDATA6_MASK |
PMX_MCIDATA7_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCIDATA6_MASK |
PMX_MCIDATA7_MASK,
.val = PMX_MCIDATA6_MASK |
PMX_MCIDATA7_MASK,
},
};
static struct spear_modemux i2c5_dis_sd_modemux[] = {
{
.muxregs = i2c5_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c5_dis_sd_pingroup = {
.name = "i2c5_dis_sd_grp",
.pins = i2c5_dis_sd_pins,
.npins = ARRAY_SIZE(i2c5_dis_sd_pins),
.modemuxs = i2c5_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
};
static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
"i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
static struct spear_function i2c_4_5_function = {
.name = "i2c_4_5",
.groups = i2c_4_5_grps,
.ngroups = ARRAY_SIZE(i2c_4_5_grps),
};
/* Pad multiplexing for i2c_6_7_dis_kbd device */
/* Muxed with KBD */
static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = PMX_KBD_ROWCOL25_MASK,
},
};
static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
{
.muxregs = i2c_6_7_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
},
};
static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
.name = "i2c_6_7_dis_kbd_grp",
.pins = i2c_6_7_dis_kbd_pins,
.npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
.modemuxs = i2c_6_7_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
};
/* Pad multiplexing for i2c6_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIIORDRE_MASK |
PMX_MCIIOWRWE_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCIIORDRE_MASK |
PMX_MCIIOWRWE_MASK,
.val = PMX_MCIIORDRE_MASK |
PMX_MCIIOWRWE_MASK,
},
};
static struct spear_modemux i2c6_dis_sd_modemux[] = {
{
.muxregs = i2c6_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c6_dis_sd_pingroup = {
.name = "i2c6_dis_sd_grp",
.pins = i2c6_dis_sd_pins,
.npins = ARRAY_SIZE(i2c6_dis_sd_pins),
.modemuxs = i2c6_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
};
/* Pad multiplexing for i2c7_dis_sd device */
static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIRESETCF_MASK |
PMX_MCICS0CE_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCIRESETCF_MASK |
PMX_MCICS0CE_MASK,
.val = PMX_MCIRESETCF_MASK |
PMX_MCICS0CE_MASK,
},
};
static struct spear_modemux i2c7_dis_sd_modemux[] = {
{
.muxregs = i2c7_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
},
};
static struct spear_pingroup i2c7_dis_sd_pingroup = {
.name = "i2c7_dis_sd_grp",
.pins = i2c7_dis_sd_pins,
.npins = ARRAY_SIZE(i2c7_dis_sd_pins),
.modemuxs = i2c7_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
};
static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
"i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
static struct spear_function i2c_6_7_function = {
.name = "i2c_6_7",
.groups = i2c_6_7_grps,
.ngroups = ARRAY_SIZE(i2c_6_7_grps),
};
/* Pad multiplexing for can0_dis_nor device */
/* Muxed with NOR */
static const unsigned can0_dis_nor_pins[] = { 56, 57 };
static struct spear_muxreg can0_dis_nor_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_NFRSTPWDWN2_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_NFRSTPWDWN3_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_NFRSTPWDWN2_MASK,
.val = PMX_NFRSTPWDWN2_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_NFRSTPWDWN3_MASK,
.val = PMX_NFRSTPWDWN3_MASK,
},
};
static struct spear_modemux can0_dis_nor_modemux[] = {
{
.muxregs = can0_dis_nor_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
},
};
static struct spear_pingroup can0_dis_nor_pingroup = {
.name = "can0_dis_nor_grp",
.pins = can0_dis_nor_pins,
.npins = ARRAY_SIZE(can0_dis_nor_pins),
.modemuxs = can0_dis_nor_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
};
/* Pad multiplexing for can0_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can0_dis_sd_pins[] = { 240, 241 };
static struct spear_muxreg can0_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
.val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
},
};
static struct spear_modemux can0_dis_sd_modemux[] = {
{
.muxregs = can0_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
},
};
static struct spear_pingroup can0_dis_sd_pingroup = {
.name = "can0_dis_sd_grp",
.pins = can0_dis_sd_pins,
.npins = ARRAY_SIZE(can0_dis_sd_pins),
.modemuxs = can0_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
};
static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
};
static struct spear_function can0_function = {
.name = "can0",
.groups = can0_grps,
.ngroups = ARRAY_SIZE(can0_grps),
};
/* Pad multiplexing for can1_dis_sd device */
/* Muxed with SD/MMC */
static const unsigned can1_dis_sd_pins[] = { 242, 243 };
static struct spear_muxreg can1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
.val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
},
};
static struct spear_modemux can1_dis_sd_modemux[] = {
{
.muxregs = can1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
},
};
static struct spear_pingroup can1_dis_sd_pingroup = {
.name = "can1_dis_sd_grp",
.pins = can1_dis_sd_pins,
.npins = ARRAY_SIZE(can1_dis_sd_pins),
.modemuxs = can1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
};
/* Pad multiplexing for can1_dis_kbd device */
/* Muxed with KBD */
static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
static struct spear_muxreg can1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_KBD_ROWCOL25_MASK,
.val = PMX_KBD_ROWCOL25_MASK,
},
};
static struct spear_modemux can1_dis_kbd_modemux[] = {
{
.muxregs = can1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
},
};
static struct spear_pingroup can1_dis_kbd_pingroup = {
.name = "can1_dis_kbd_grp",
.pins = can1_dis_kbd_pins,
.npins = ARRAY_SIZE(can1_dis_kbd_pins),
.modemuxs = can1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
};
static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
};
static struct spear_function can1_function = {
.name = "can1",
.groups = can1_grps,
.ngroups = ARRAY_SIZE(can1_grps),
};
/* Pad multiplexing for (ras-ip) pci device */
static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
static struct spear_muxreg pci_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_MCI_DATA8_15_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_PCI_REG1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_PCI_REG2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_0,
.mask = PMX_MCI_DATA8_15_MASK,
.val = PMX_MCI_DATA8_15_MASK,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_PCI_REG1_MASK,
.val = PMX_PCI_REG1_MASK,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_PCI_REG2_MASK,
.val = PMX_PCI_REG2_MASK,
},
};
static struct spear_modemux pci_modemux[] = {
{
.muxregs = pci_muxreg,
.nmuxregs = ARRAY_SIZE(pci_muxreg),
},
};
static struct spear_pingroup pci_pingroup = {
.name = "pci_grp",
.pins = pci_pins,
.npins = ARRAY_SIZE(pci_pins),
.modemuxs = pci_modemux,
.nmodemuxs = ARRAY_SIZE(pci_modemux),
};
static const char *const pci_grps[] = { "pci_grp" };
static struct spear_function pci_function = {
.name = "pci",
.groups = pci_grps,
.ngroups = ARRAY_SIZE(pci_grps),
};
/* pad multiplexing for (fix-part) pcie0 device */
static struct spear_muxreg pcie0_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(0),
.val = PCIE_CFG_VAL(0),
},
};
static struct spear_modemux pcie0_modemux[] = {
{
.muxregs = pcie0_muxreg,
.nmuxregs = ARRAY_SIZE(pcie0_muxreg),
},
};
static struct spear_pingroup pcie0_pingroup = {
.name = "pcie0_grp",
.modemuxs = pcie0_modemux,
.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
};
/* pad multiplexing for (fix-part) pcie1 device */
static struct spear_muxreg pcie1_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(1),
.val = PCIE_CFG_VAL(1),
},
};
static struct spear_modemux pcie1_modemux[] = {
{
.muxregs = pcie1_muxreg,
.nmuxregs = ARRAY_SIZE(pcie1_muxreg),
},
};
static struct spear_pingroup pcie1_pingroup = {
.name = "pcie1_grp",
.modemuxs = pcie1_modemux,
.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
};
/* pad multiplexing for (fix-part) pcie2 device */
static struct spear_muxreg pcie2_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(2),
.val = PCIE_CFG_VAL(2),
},
};
static struct spear_modemux pcie2_modemux[] = {
{
.muxregs = pcie2_muxreg,
.nmuxregs = ARRAY_SIZE(pcie2_muxreg),
},
};
static struct spear_pingroup pcie2_pingroup = {
.name = "pcie2_grp",
.modemuxs = pcie2_modemux,
.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
};
static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
};
static struct spear_function pcie_function = {
.name = "pci_express",
.groups = pcie_grps,
.ngroups = ARRAY_SIZE(pcie_grps),
};
/* pad multiplexing for sata0 device */
static struct spear_muxreg sata0_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(0),
.val = SATA_CFG_VAL(0),
},
};
static struct spear_modemux sata0_modemux[] = {
{
.muxregs = sata0_muxreg,
.nmuxregs = ARRAY_SIZE(sata0_muxreg),
},
};
static struct spear_pingroup sata0_pingroup = {
.name = "sata0_grp",
.modemuxs = sata0_modemux,
.nmodemuxs = ARRAY_SIZE(sata0_modemux),
};
/* pad multiplexing for sata1 device */
static struct spear_muxreg sata1_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(1),
.val = SATA_CFG_VAL(1),
},
};
static struct spear_modemux sata1_modemux[] = {
{
.muxregs = sata1_muxreg,
.nmuxregs = ARRAY_SIZE(sata1_muxreg),
},
};
static struct spear_pingroup sata1_pingroup = {
.name = "sata1_grp",
.modemuxs = sata1_modemux,
.nmodemuxs = ARRAY_SIZE(sata1_modemux),
};
/* pad multiplexing for sata2 device */
static struct spear_muxreg sata2_muxreg[] = {
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(2),
.val = SATA_CFG_VAL(2),
},
};
static struct spear_modemux sata2_modemux[] = {
{
.muxregs = sata2_muxreg,
.nmuxregs = ARRAY_SIZE(sata2_muxreg),
},
};
static struct spear_pingroup sata2_pingroup = {
.name = "sata2_grp",
.modemuxs = sata2_modemux,
.nmodemuxs = ARRAY_SIZE(sata2_modemux),
};
static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
};
static struct spear_function sata_function = {
.name = "sata",
.groups = sata_grps,
.ngroups = ARRAY_SIZE(sata_grps),
};
/* Pad multiplexing for ssp1_dis_kbd device */
static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
PMX_NFCE2_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_1,
.mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
PMX_NFCE2_MASK,
.val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
PMX_NFCE2_MASK,
},
};
static struct spear_modemux ssp1_dis_kbd_modemux[] = {
{
.muxregs = ssp1_dis_kbd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_kbd_pingroup = {
.name = "ssp1_dis_kbd_grp",
.pins = ssp1_dis_kbd_pins,
.npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
.modemuxs = ssp1_dis_kbd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
};
/* Pad multiplexing for ssp1_dis_sd device */
static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
.val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
},
};
static struct spear_modemux ssp1_dis_sd_modemux[] = {
{
.muxregs = ssp1_dis_sd_muxreg,
.nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
},
};
static struct spear_pingroup ssp1_dis_sd_pingroup = {
.name = "ssp1_dis_sd_grp",
.pins = ssp1_dis_sd_pins,
.npins = ARRAY_SIZE(ssp1_dis_sd_pins),
.modemuxs = ssp1_dis_sd_modemux,
.nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
};
static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
"ssp1_dis_sd_grp" };
static struct spear_function ssp1_function = {
.name = "ssp1",
.groups = ssp1_grps,
.ngroups = ARRAY_SIZE(ssp1_grps),
};
/* Pad multiplexing for gpt64 device */
static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
static struct spear_muxreg gpt64_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
| PMX_MCILEDS_MASK,
.val = 0,
}, {
.reg = PAD_DIRECTION_SEL_2,
.mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
| PMX_MCILEDS_MASK,
.val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
| PMX_MCILEDS_MASK,
},
};
static struct spear_modemux gpt64_modemux[] = {
{
.muxregs = gpt64_muxreg,
.nmuxregs = ARRAY_SIZE(gpt64_muxreg),
},
};
static struct spear_pingroup gpt64_pingroup = {
.name = "gpt64_grp",
.pins = gpt64_pins,
.npins = ARRAY_SIZE(gpt64_pins),
.modemuxs = gpt64_modemux,
.nmodemuxs = ARRAY_SIZE(gpt64_modemux),
};
static const char *const gpt64_grps[] = { "gpt64_grp" };
static struct spear_function gpt64_function = {
.name = "gpt64",
.groups = gpt64_grps,
.ngroups = ARRAY_SIZE(gpt64_grps),
};
/* pingroups */
static struct spear_pingroup *spear1310_pingroups[] = {
&i2c0_pingroup,
&ssp0_pingroup,
&i2s0_pingroup,
&i2s1_pingroup,
&clcd_pingroup,
&clcd_high_res_pingroup,
&arm_gpio_pingroup,
&smi_2_chips_pingroup,
&smi_4_chips_pingroup,
&gmii_pingroup,
&rgmii_pingroup,
&smii_0_1_2_pingroup,
&ras_mii_txclk_pingroup,
&nand_8bit_pingroup,
&nand_16bit_pingroup,
&nand_4_chips_pingroup,
&keyboard_6x6_pingroup,
&keyboard_rowcol6_8_pingroup,
&uart0_pingroup,
&uart0_modem_pingroup,
&gpt0_tmr0_pingroup,
&gpt0_tmr1_pingroup,
&gpt1_tmr0_pingroup,
&gpt1_tmr1_pingroup,
&sdhci_pingroup,
&cf_pingroup,
&xd_pingroup,
&touch_xy_pingroup,
&ssp0_cs0_pingroup,
&ssp0_cs1_2_pingroup,
&uart_1_dis_i2c_pingroup,
&uart_1_dis_sd_pingroup,
&uart_2_3_pingroup,
&uart_4_pingroup,
&uart_5_pingroup,
&rs485_0_1_tdm_0_1_pingroup,
&i2c_1_2_pingroup,
&i2c3_dis_smi_clcd_pingroup,
&i2c3_dis_sd_i2s0_pingroup,
&i2c_4_5_dis_smi_pingroup,
&i2c4_dis_sd_pingroup,
&i2c5_dis_sd_pingroup,
&i2c_6_7_dis_kbd_pingroup,
&i2c6_dis_sd_pingroup,
&i2c7_dis_sd_pingroup,
&can0_dis_nor_pingroup,
&can0_dis_sd_pingroup,
&can1_dis_sd_pingroup,
&can1_dis_kbd_pingroup,
&pci_pingroup,
&pcie0_pingroup,
&pcie1_pingroup,
&pcie2_pingroup,
&sata0_pingroup,
&sata1_pingroup,
&sata2_pingroup,
&ssp1_dis_kbd_pingroup,
&ssp1_dis_sd_pingroup,
&gpt64_pingroup,
};
/* functions */
static struct spear_function *spear1310_functions[] = {
&i2c0_function,
&ssp0_function,
&i2s0_function,
&i2s1_function,
&clcd_function,
&arm_gpio_function,
&smi_function,
&gmii_function,
&rgmii_function,
&smii_0_1_2_function,
&ras_mii_txclk_function,
&nand_function,
&keyboard_function,
&uart0_function,
&gpt0_function,
&gpt1_function,
&sdhci_function,
&cf_function,
&xd_function,
&touch_xy_function,
&uart1_function,
&uart2_3_function,
&uart4_function,
&uart5_function,
&rs485_0_1_tdm_0_1_function,
&i2c_1_2_function,
&i2c3_unction,
&i2c_4_5_function,
&i2c_6_7_function,
&can0_function,
&can1_function,
&pci_function,
&pcie_function,
&sata_function,
&ssp1_function,
&gpt64_function,
};
static const unsigned pin18[] = { 18, };
static const unsigned pin19[] = { 19, };
static const unsigned pin20[] = { 20, };
static const unsigned pin21[] = { 21, };
static const unsigned pin22[] = { 22, };
static const unsigned pin23[] = { 23, };
static const unsigned pin54[] = { 54, };
static const unsigned pin55[] = { 55, };
static const unsigned pin56[] = { 56, };
static const unsigned pin57[] = { 57, };
static const unsigned pin58[] = { 58, };
static const unsigned pin59[] = { 59, };
static const unsigned pin60[] = { 60, };
static const unsigned pin61[] = { 61, };
static const unsigned pin62[] = { 62, };
static const unsigned pin63[] = { 63, };
static const unsigned pin143[] = { 143, };
static const unsigned pin144[] = { 144, };
static const unsigned pin145[] = { 145, };
static const unsigned pin146[] = { 146, };
static const unsigned pin147[] = { 147, };
static const unsigned pin148[] = { 148, };
static const unsigned pin149[] = { 149, };
static const unsigned pin150[] = { 150, };
static const unsigned pin151[] = { 151, };
static const unsigned pin152[] = { 152, };
static const unsigned pin205[] = { 205, };
static const unsigned pin206[] = { 206, };
static const unsigned pin211[] = { 211, };
static const unsigned pin212[] = { 212, };
static const unsigned pin213[] = { 213, };
static const unsigned pin214[] = { 214, };
static const unsigned pin215[] = { 215, };
static const unsigned pin216[] = { 216, };
static const unsigned pin217[] = { 217, };
static const unsigned pin218[] = { 218, };
static const unsigned pin219[] = { 219, };
static const unsigned pin220[] = { 220, };
static const unsigned pin221[] = { 221, };
static const unsigned pin222[] = { 222, };
static const unsigned pin223[] = { 223, };
static const unsigned pin224[] = { 224, };
static const unsigned pin225[] = { 225, };
static const unsigned pin226[] = { 226, };
static const unsigned pin227[] = { 227, };
static const unsigned pin228[] = { 228, };
static const unsigned pin229[] = { 229, };
static const unsigned pin230[] = { 230, };
static const unsigned pin231[] = { 231, };
static const unsigned pin232[] = { 232, };
static const unsigned pin233[] = { 233, };
static const unsigned pin234[] = { 234, };
static const unsigned pin235[] = { 235, };
static const unsigned pin236[] = { 236, };
static const unsigned pin237[] = { 237, };
static const unsigned pin238[] = { 238, };
static const unsigned pin239[] = { 239, };
static const unsigned pin240[] = { 240, };
static const unsigned pin241[] = { 241, };
static const unsigned pin242[] = { 242, };
static const unsigned pin243[] = { 243, };
static const unsigned pin244[] = { 244, };
static const unsigned pin245[] = { 245, };
static const unsigned pin_grp0[] = { 173, 174, };
static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
190, 191, 192, };
static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
static const unsigned pin_grp4[] = { 199, 200, };
static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
static const unsigned pin_grp7[] = { 98, 99, };
static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
166, 167, 168, 169, 170, 171, 172, };
/* Define muxreg arrays */
DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
GPIO_PINGROUP(i2c0_pins),
GPIO_PINGROUP(ssp0_pins),
GPIO_PINGROUP(ssp0_cs0_pins),
GPIO_PINGROUP(ssp0_cs1_2_pins),
GPIO_PINGROUP(i2s0_pins),
GPIO_PINGROUP(i2s1_pins),
GPIO_PINGROUP(clcd_pins),
GPIO_PINGROUP(clcd_high_res_pins),
GPIO_PINGROUP(pin18),
GPIO_PINGROUP(pin19),
GPIO_PINGROUP(pin20),
GPIO_PINGROUP(pin21),
GPIO_PINGROUP(pin22),
GPIO_PINGROUP(pin23),
GPIO_PINGROUP(pin143),
GPIO_PINGROUP(pin144),
GPIO_PINGROUP(pin145),
GPIO_PINGROUP(pin146),
GPIO_PINGROUP(pin147),
GPIO_PINGROUP(pin148),
GPIO_PINGROUP(pin149),
GPIO_PINGROUP(pin150),
GPIO_PINGROUP(pin151),
GPIO_PINGROUP(pin152),
GPIO_PINGROUP(smi_2_chips_pins),
GPIO_PINGROUP(pin54),
GPIO_PINGROUP(pin55),
GPIO_PINGROUP(pin56),
GPIO_PINGROUP(pin57),
GPIO_PINGROUP(pin58),
GPIO_PINGROUP(pin59),
GPIO_PINGROUP(pin60),
GPIO_PINGROUP(pin61),
GPIO_PINGROUP(pin62),
GPIO_PINGROUP(pin63),
GPIO_PINGROUP(pin_grp0),
GPIO_PINGROUP(pin_grp1),
GPIO_PINGROUP(pin_grp2),
GPIO_PINGROUP(pin_grp3),
GPIO_PINGROUP(pin_grp4),
GPIO_PINGROUP(pin_grp5),
GPIO_PINGROUP(pin_grp6),
GPIO_PINGROUP(pin_grp7),
GPIO_PINGROUP(pin_grp8),
GPIO_PINGROUP(nand_16bit_pins),
GPIO_PINGROUP(pin205),
GPIO_PINGROUP(pin206),
GPIO_PINGROUP(pin211),
GPIO_PINGROUP(pin212),
GPIO_PINGROUP(pin213),
GPIO_PINGROUP(pin214),
GPIO_PINGROUP(pin215),
GPIO_PINGROUP(pin216),
GPIO_PINGROUP(pin217),
GPIO_PINGROUP(pin218),
GPIO_PINGROUP(pin219),
GPIO_PINGROUP(pin220),
GPIO_PINGROUP(pin221),
GPIO_PINGROUP(pin222),
GPIO_PINGROUP(pin223),
GPIO_PINGROUP(pin224),
GPIO_PINGROUP(pin225),
GPIO_PINGROUP(pin226),
GPIO_PINGROUP(pin227),
GPIO_PINGROUP(pin228),
GPIO_PINGROUP(pin229),
GPIO_PINGROUP(pin230),
GPIO_PINGROUP(pin231),
GPIO_PINGROUP(pin232),
GPIO_PINGROUP(pin233),
GPIO_PINGROUP(pin234),
GPIO_PINGROUP(pin235),
GPIO_PINGROUP(pin236),
GPIO_PINGROUP(pin237),
GPIO_PINGROUP(pin238),
GPIO_PINGROUP(pin239),
GPIO_PINGROUP(pin240),
GPIO_PINGROUP(pin241),
GPIO_PINGROUP(pin242),
GPIO_PINGROUP(pin243),
GPIO_PINGROUP(pin244),
GPIO_PINGROUP(pin245),
GPIO_PINGROUP(keyboard_rowcol6_8_pins),
GPIO_PINGROUP(uart0_pins),
GPIO_PINGROUP(uart0_modem_pins),
GPIO_PINGROUP(gpt0_tmr0_pins),
GPIO_PINGROUP(gpt0_tmr1_pins),
GPIO_PINGROUP(gpt1_tmr0_pins),
GPIO_PINGROUP(gpt1_tmr1_pins),
GPIO_PINGROUP(touch_xy_pins),
};
static struct spear_pinctrl_machdata spear1310_machdata = {
.pins = spear1310_pins,
.npins = ARRAY_SIZE(spear1310_pins),
.groups = spear1310_pingroups,
.ngroups = ARRAY_SIZE(spear1310_pingroups),
.functions = spear1310_functions,
.nfunctions = ARRAY_SIZE(spear1310_functions),
.gpio_pingroups = spear1310_gpio_pingroup,
.ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
.modes_supported = false,
};
static const struct of_device_id spear1310_pinctrl_of_match[] = {
{
.compatible = "st,spear1310-pinmux",
},
{},
};
static int spear1310_pinctrl_probe(struct platform_device *pdev)
{
return spear_pinctrl_probe(pdev, &spear1310_machdata);
}
static struct platform_driver spear1310_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = spear1310_pinctrl_of_match,
},
.probe = spear1310_pinctrl_probe,
};
static int __init spear1310_pinctrl_init(void)
{
return platform_driver_register(&spear1310_pinctrl_driver);
}
arch_initcall(spear1310_pinctrl_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear1310.c
|
/*
* SPEAr platform PLGPIO driver
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#define MAX_GPIO_PER_REG 32
#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
* sizeof(int *))
/*
* plgpio pins in all machines are not one to one mapped, bitwise with registers
* bits. These set of macros define register masks for which below functions
* (pin_to_offset and offset_to_pin) are required to be called.
*/
#define PTO_ENB_REG 0x001
#define PTO_WDATA_REG 0x002
#define PTO_DIR_REG 0x004
#define PTO_IE_REG 0x008
#define PTO_RDATA_REG 0x010
#define PTO_MIS_REG 0x020
struct plgpio_regs {
u32 enb; /* enable register */
u32 wdata; /* write data register */
u32 dir; /* direction set register */
u32 rdata; /* read data register */
u32 ie; /* interrupt enable register */
u32 mis; /* mask interrupt status register */
u32 eit; /* edge interrupt type */
};
/*
* struct plgpio: plgpio driver specific structure
*
* lock: lock for guarding gpio registers
* base: base address of plgpio block
* chip: gpio framework specific chip information structure
* p2o: function ptr for pin to offset conversion. This is required only for
* machines where mapping b/w pin and offset is not 1-to-1.
* o2p: function ptr for offset to pin conversion. This is required only for
* machines where mapping b/w pin and offset is not 1-to-1.
* p2o_regs: mask of registers for which p2o and o2p are applicable
* regs: register offsets
* csave_regs: context save registers for standby/sleep/hibernate cases
*/
struct plgpio {
spinlock_t lock;
struct regmap *regmap;
struct clk *clk;
struct gpio_chip chip;
int (*p2o)(int pin); /* pin_to_offset */
int (*o2p)(int offset); /* offset_to_pin */
u32 p2o_regs;
struct plgpio_regs regs;
#ifdef CONFIG_PM_SLEEP
struct plgpio_regs *csave_regs;
#endif
};
/* register manipulation inline functions */
static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg)
{
u32 offset = PIN_OFFSET(pin);
u32 reg_off = REG_OFFSET(0, reg, pin);
u32 val;
regmap_read(regmap, reg_off, &val);
return !!(val & (1 << offset));
}
static inline void plgpio_reg_set(struct regmap *regmap, u32 pin, u32 reg)
{
u32 offset = PIN_OFFSET(pin);
u32 reg_off = REG_OFFSET(0, reg, pin);
u32 mask;
mask = 1 << offset;
regmap_update_bits(regmap, reg_off, mask, mask);
}
static inline void plgpio_reg_reset(struct regmap *regmap, u32 pin, u32 reg)
{
u32 offset = PIN_OFFSET(pin);
u32 reg_off = REG_OFFSET(0, reg, pin);
u32 mask;
mask = 1 << offset;
regmap_update_bits(regmap, reg_off, mask, 0);
}
/* gpio framework specific routines */
static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
unsigned long flags;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return -EINVAL;
}
spin_lock_irqsave(&plgpio->lock, flags);
plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.dir);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
}
static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
unsigned long flags;
unsigned dir_offset = offset, wdata_offset = offset, tmp;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
tmp = plgpio->p2o(offset);
if (tmp == -1)
return -EINVAL;
if (plgpio->p2o_regs & PTO_DIR_REG)
dir_offset = tmp;
if (plgpio->p2o_regs & PTO_WDATA_REG)
wdata_offset = tmp;
}
spin_lock_irqsave(&plgpio->lock, flags);
if (value)
plgpio_reg_set(plgpio->regmap, wdata_offset,
plgpio->regs.wdata);
else
plgpio_reg_reset(plgpio->regmap, wdata_offset,
plgpio->regs.wdata);
plgpio_reg_reset(plgpio->regmap, dir_offset, plgpio->regs.dir);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
}
static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
if (offset >= chip->ngpio)
return -EINVAL;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return -EINVAL;
}
return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata);
}
static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
if (offset >= chip->ngpio)
return;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return;
}
if (value)
plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata);
else
plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata);
}
static int plgpio_request(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
int gpio = chip->base + offset;
unsigned long flags;
int ret = 0;
if (offset >= chip->ngpio)
return -EINVAL;
ret = pinctrl_gpio_request(gpio);
if (ret)
return ret;
if (!IS_ERR(plgpio->clk)) {
ret = clk_enable(plgpio->clk);
if (ret)
goto err0;
}
if (plgpio->regs.enb == -1)
return 0;
/*
* put gpio in IN mode before enabling it. This make enabling gpio safe
*/
ret = plgpio_direction_input(chip, offset);
if (ret)
goto err1;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1) {
ret = -EINVAL;
goto err1;
}
}
spin_lock_irqsave(&plgpio->lock, flags);
plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.enb);
spin_unlock_irqrestore(&plgpio->lock, flags);
return 0;
err1:
if (!IS_ERR(plgpio->clk))
clk_disable(plgpio->clk);
err0:
pinctrl_gpio_free(gpio);
return ret;
}
static void plgpio_free(struct gpio_chip *chip, unsigned offset)
{
struct plgpio *plgpio = gpiochip_get_data(chip);
int gpio = chip->base + offset;
unsigned long flags;
if (offset >= chip->ngpio)
return;
if (plgpio->regs.enb == -1)
goto disable_clk;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return;
}
spin_lock_irqsave(&plgpio->lock, flags);
plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.enb);
spin_unlock_irqrestore(&plgpio->lock, flags);
disable_clk:
if (!IS_ERR(plgpio->clk))
clk_disable(plgpio->clk);
pinctrl_gpio_free(gpio);
}
/* PLGPIO IRQ */
static void plgpio_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct plgpio *plgpio = gpiochip_get_data(gc);
int offset = d->hwirq;
unsigned long flags;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return;
}
spin_lock_irqsave(&plgpio->lock, flags);
plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie);
spin_unlock_irqrestore(&plgpio->lock, flags);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void plgpio_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct plgpio *plgpio = gpiochip_get_data(gc);
int offset = d->hwirq;
unsigned long flags;
/* get correct offset for "offset" pin */
if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
offset = plgpio->p2o(offset);
if (offset == -1)
return;
}
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
spin_lock_irqsave(&plgpio->lock, flags);
plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie);
spin_unlock_irqrestore(&plgpio->lock, flags);
}
static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct plgpio *plgpio = gpiochip_get_data(gc);
int offset = d->hwirq;
u32 reg_off;
unsigned int supported_type = 0, val;
if (offset >= plgpio->chip.ngpio)
return -EINVAL;
if (plgpio->regs.eit == -1)
supported_type = IRQ_TYPE_LEVEL_HIGH;
else
supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
if (!(trigger & supported_type))
return -EINVAL;
if (plgpio->regs.eit == -1)
return 0;
reg_off = REG_OFFSET(0, plgpio->regs.eit, offset);
regmap_read(plgpio->regmap, reg_off, &val);
offset = PIN_OFFSET(offset);
if (trigger & IRQ_TYPE_EDGE_RISING)
regmap_write(plgpio->regmap, reg_off, val | (1 << offset));
else
regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset));
return 0;
}
static const struct irq_chip plgpio_irqchip = {
.name = "PLGPIO",
.irq_enable = plgpio_irq_enable,
.irq_disable = plgpio_irq_disable,
.irq_set_type = plgpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void plgpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct plgpio *plgpio = gpiochip_get_data(gc);
struct irq_chip *irqchip = irq_desc_get_chip(desc);
int regs_count, count, pin, offset, i = 0;
u32 pending;
unsigned long pendingl;
count = plgpio->chip.ngpio;
regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
chained_irq_enter(irqchip, desc);
/* check all plgpio MIS registers for a possible interrupt */
for (; i < regs_count; i++) {
regmap_read(plgpio->regmap, plgpio->regs.mis +
i * sizeof(int *), &pending);
if (!pending)
continue;
/* clear interrupts */
regmap_write(plgpio->regmap, plgpio->regs.mis +
i * sizeof(int *), ~pending);
/*
* clear extra bits in last register having gpios < MAX/REG
* ex: Suppose there are max 102 plgpios. then last register
* must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
* so, we must not take other 28 bits into consideration for
* checking interrupt. so clear those bits.
*/
count = count - i * MAX_GPIO_PER_REG;
if (count < MAX_GPIO_PER_REG)
pending &= (1 << count) - 1;
pendingl = pending;
for_each_set_bit(offset, &pendingl, MAX_GPIO_PER_REG) {
/* get correct pin for "offset" */
if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
pin = plgpio->o2p(offset);
if (pin == -1)
continue;
} else
pin = offset;
/* get correct irq line number */
pin = i * MAX_GPIO_PER_REG + pin;
generic_handle_domain_irq(gc->irq.domain, pin);
}
}
chained_irq_exit(irqchip, desc);
}
/*
* pin to offset and offset to pin converter functions
*
* In spear310 there is inconsistency among bit positions in plgpio regiseters,
* for different plgpio pins. For example: for pin 27, bit offset is 23, pin
* 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
*/
static int spear310_p2o(int pin)
{
int offset = pin;
if (pin <= 27)
offset += 4;
else if (pin <= 33)
offset = -1;
else if (pin <= 97)
offset -= 2;
else if (pin <= 101)
offset = 101 - pin;
else
offset = -1;
return offset;
}
static int spear310_o2p(int offset)
{
if (offset <= 3)
return 101 - offset;
else if (offset <= 31)
return offset - 4;
else
return offset + 2;
}
static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
{
struct device_node *np = pdev->dev.of_node;
int ret = -EINVAL;
u32 val;
if (of_machine_is_compatible("st,spear310")) {
plgpio->p2o = spear310_p2o;
plgpio->o2p = spear310_o2p;
plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
PTO_RDATA_REG | PTO_MIS_REG;
}
if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
plgpio->chip.ngpio = val;
} else {
dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
plgpio->regs.enb = val;
else
plgpio->regs.enb = -1;
if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
plgpio->regs.wdata = val;
} else {
dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
plgpio->regs.dir = val;
} else {
dev_err(&pdev->dev, "DT: Invalid dir reg\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
plgpio->regs.ie = val;
} else {
dev_err(&pdev->dev, "DT: Invalid ie reg\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
plgpio->regs.rdata = val;
} else {
dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
plgpio->regs.mis = val;
} else {
dev_err(&pdev->dev, "DT: Invalid mis reg\n");
goto end;
}
if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
plgpio->regs.eit = val;
else
plgpio->regs.eit = -1;
return 0;
end:
return ret;
}
static int plgpio_probe(struct platform_device *pdev)
{
struct device_node *regmap_np;
struct plgpio *plgpio;
int ret, irq;
plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
if (!plgpio)
return -ENOMEM;
regmap_np = of_parse_phandle(pdev->dev.of_node, "regmap", 0);
if (regmap_np) {
plgpio->regmap = device_node_to_regmap(regmap_np);
of_node_put(regmap_np);
if (IS_ERR(plgpio->regmap)) {
dev_err(&pdev->dev, "Retrieve regmap failed (%pe)\n",
plgpio->regmap);
return PTR_ERR(plgpio->regmap);
}
} else {
plgpio->regmap = device_node_to_regmap(pdev->dev.of_node);
if (IS_ERR(plgpio->regmap)) {
dev_err(&pdev->dev, "Init regmap failed (%pe)\n",
plgpio->regmap);
return PTR_ERR(plgpio->regmap);
}
}
ret = plgpio_probe_dt(pdev, plgpio);
if (ret) {
dev_err(&pdev->dev, "DT probe failed\n");
return ret;
}
plgpio->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(plgpio->clk))
dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
#ifdef CONFIG_PM_SLEEP
plgpio->csave_regs = devm_kcalloc(&pdev->dev,
DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
sizeof(*plgpio->csave_regs),
GFP_KERNEL);
if (!plgpio->csave_regs)
return -ENOMEM;
#endif
platform_set_drvdata(pdev, plgpio);
spin_lock_init(&plgpio->lock);
plgpio->chip.base = -1;
plgpio->chip.request = plgpio_request;
plgpio->chip.free = plgpio_free;
plgpio->chip.direction_input = plgpio_direction_input;
plgpio->chip.direction_output = plgpio_direction_output;
plgpio->chip.get = plgpio_get_value;
plgpio->chip.set = plgpio_set_value;
plgpio->chip.label = dev_name(&pdev->dev);
plgpio->chip.parent = &pdev->dev;
plgpio->chip.owner = THIS_MODULE;
if (!IS_ERR(plgpio->clk)) {
ret = clk_prepare(plgpio->clk);
if (ret) {
dev_err(&pdev->dev, "clk prepare failed\n");
return ret;
}
}
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
struct gpio_irq_chip *girq;
girq = &plgpio->chip.irq;
gpio_irq_chip_set_chip(girq, &plgpio_irqchip);
girq->parent_handler = plgpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
dev_info(&pdev->dev, "PLGPIO registering with IRQs\n");
} else {
dev_info(&pdev->dev, "PLGPIO registering without IRQs\n");
}
ret = gpiochip_add_data(&plgpio->chip, plgpio);
if (ret) {
dev_err(&pdev->dev, "unable to add gpio chip\n");
goto unprepare_clk;
}
return 0;
unprepare_clk:
if (!IS_ERR(plgpio->clk))
clk_unprepare(plgpio->clk);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static int plgpio_suspend(struct device *dev)
{
struct plgpio *plgpio = dev_get_drvdata(dev);
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
u32 off;
for (i = 0; i < reg_count; i++) {
off = i * sizeof(int *);
if (plgpio->regs.enb != -1)
regmap_read(plgpio->regmap, plgpio->regs.enb + off,
&plgpio->csave_regs[i].enb);
if (plgpio->regs.eit != -1)
regmap_read(plgpio->regmap, plgpio->regs.eit + off,
&plgpio->csave_regs[i].eit);
regmap_read(plgpio->regmap, plgpio->regs.wdata + off,
&plgpio->csave_regs[i].wdata);
regmap_read(plgpio->regmap, plgpio->regs.dir + off,
&plgpio->csave_regs[i].dir);
regmap_read(plgpio->regmap, plgpio->regs.ie + off,
&plgpio->csave_regs[i].ie);
}
return 0;
}
/*
* This is used to correct the values in end registers. End registers contain
* extra bits that might be used for other purpose in platform. So, we shouldn't
* overwrite these bits. This macro, reads given register again, preserves other
* bit values (non-plgpio bits), and retain captured value (plgpio bits).
*/
#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
{ \
regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \
_tmp &= ~_mask; \
plgpio->csave_regs[i].__reg = \
_tmp | (plgpio->csave_regs[i].__reg & _mask); \
}
static int plgpio_resume(struct device *dev)
{
struct plgpio *plgpio = dev_get_drvdata(dev);
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
u32 off;
u32 mask, tmp;
for (i = 0; i < reg_count; i++) {
off = i * sizeof(int *);
if (i == reg_count - 1) {
mask = (1 << (plgpio->chip.ngpio - i *
MAX_GPIO_PER_REG)) - 1;
if (plgpio->regs.enb != -1)
plgpio_prepare_reg(enb, off, mask, tmp);
if (plgpio->regs.eit != -1)
plgpio_prepare_reg(eit, off, mask, tmp);
plgpio_prepare_reg(wdata, off, mask, tmp);
plgpio_prepare_reg(dir, off, mask, tmp);
plgpio_prepare_reg(ie, off, mask, tmp);
}
regmap_write(plgpio->regmap, plgpio->regs.wdata + off,
plgpio->csave_regs[i].wdata);
regmap_write(plgpio->regmap, plgpio->regs.dir + off,
plgpio->csave_regs[i].dir);
if (plgpio->regs.eit != -1)
regmap_write(plgpio->regmap, plgpio->regs.eit + off,
plgpio->csave_regs[i].eit);
regmap_write(plgpio->regmap, plgpio->regs.ie + off,
plgpio->csave_regs[i].ie);
if (plgpio->regs.enb != -1)
regmap_write(plgpio->regmap, plgpio->regs.enb + off,
plgpio->csave_regs[i].enb);
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
static const struct of_device_id plgpio_of_match[] = {
{ .compatible = "st,spear-plgpio" },
{}
};
static struct platform_driver plgpio_driver = {
.probe = plgpio_probe,
.driver = {
.name = "spear-plgpio",
.pm = &plgpio_dev_pm_ops,
.of_match_table = plgpio_of_match,
},
};
static int __init plgpio_init(void)
{
return platform_driver_register(&plgpio_driver);
}
subsys_initcall(plgpio_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-plgpio.c
|
/*
* Driver for the ST Microelectronics SPEAr300 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear3xx.h"
#define DRIVER_NAME "spear300-pinmux"
/* addresses */
#define PMX_CONFIG_REG 0x00
#define MODE_CONFIG_REG 0x04
/* modes */
#define NAND_MODE (1 << 0)
#define NOR_MODE (1 << 1)
#define PHOTO_FRAME_MODE (1 << 2)
#define LEND_IP_PHONE_MODE (1 << 3)
#define HEND_IP_PHONE_MODE (1 << 4)
#define LEND_WIFI_PHONE_MODE (1 << 5)
#define HEND_WIFI_PHONE_MODE (1 << 6)
#define ATA_PABX_WI2S_MODE (1 << 7)
#define ATA_PABX_I2S_MODE (1 << 8)
#define CAML_LCDW_MODE (1 << 9)
#define CAMU_LCD_MODE (1 << 10)
#define CAMU_WLCD_MODE (1 << 11)
#define CAML_LCD_MODE (1 << 12)
static struct spear_pmx_mode pmx_mode_nand = {
.name = "nand",
.mode = NAND_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x00,
};
static struct spear_pmx_mode pmx_mode_nor = {
.name = "nor",
.mode = NOR_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x01,
};
static struct spear_pmx_mode pmx_mode_photo_frame = {
.name = "photo frame mode",
.mode = PHOTO_FRAME_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x02,
};
static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
.name = "lend ip phone mode",
.mode = LEND_IP_PHONE_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x03,
};
static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
.name = "hend ip phone mode",
.mode = HEND_IP_PHONE_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x04,
};
static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
.name = "lend wifi phone mode",
.mode = LEND_WIFI_PHONE_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x05,
};
static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
.name = "hend wifi phone mode",
.mode = HEND_WIFI_PHONE_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x06,
};
static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
.name = "ata pabx wi2s mode",
.mode = ATA_PABX_WI2S_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x07,
};
static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
.name = "ata pabx i2s mode",
.mode = ATA_PABX_I2S_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x08,
};
static struct spear_pmx_mode pmx_mode_caml_lcdw = {
.name = "caml lcdw mode",
.mode = CAML_LCDW_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x0C,
};
static struct spear_pmx_mode pmx_mode_camu_lcd = {
.name = "camu lcd mode",
.mode = CAMU_LCD_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x0D,
};
static struct spear_pmx_mode pmx_mode_camu_wlcd = {
.name = "camu wlcd mode",
.mode = CAMU_WLCD_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0xE,
};
static struct spear_pmx_mode pmx_mode_caml_lcd = {
.name = "caml lcd mode",
.mode = CAML_LCD_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x0000000F,
.val = 0x0F,
};
static struct spear_pmx_mode *spear300_pmx_modes[] = {
&pmx_mode_nand,
&pmx_mode_nor,
&pmx_mode_photo_frame,
&pmx_mode_lend_ip_phone,
&pmx_mode_hend_ip_phone,
&pmx_mode_lend_wifi_phone,
&pmx_mode_hend_wifi_phone,
&pmx_mode_ata_pabx_wi2s,
&pmx_mode_ata_pabx_i2s,
&pmx_mode_caml_lcdw,
&pmx_mode_camu_lcd,
&pmx_mode_camu_wlcd,
&pmx_mode_caml_lcd,
};
/* fsmc_2chips_pins */
static const unsigned fsmc_2chips_pins[] = { 1, 97 };
static struct spear_muxreg fsmc_2chips_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.val = 0,
},
};
static struct spear_modemux fsmc_2chips_modemux[] = {
{
.modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
.muxregs = fsmc_2chips_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
},
};
static struct spear_pingroup fsmc_2chips_pingroup = {
.name = "fsmc_2chips_grp",
.pins = fsmc_2chips_pins,
.npins = ARRAY_SIZE(fsmc_2chips_pins),
.modemuxs = fsmc_2chips_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
};
/* fsmc_4chips_pins */
static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
static struct spear_muxreg fsmc_4chips_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
.val = 0,
},
};
static struct spear_modemux fsmc_4chips_modemux[] = {
{
.modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
.muxregs = fsmc_4chips_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
},
};
static struct spear_pingroup fsmc_4chips_pingroup = {
.name = "fsmc_4chips_grp",
.pins = fsmc_4chips_pins,
.npins = ARRAY_SIZE(fsmc_4chips_pins),
.modemuxs = fsmc_4chips_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
};
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* clcd_lcdmode_pins */
static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
static struct spear_muxreg clcd_lcdmode_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_modemux clcd_lcdmode_modemux[] = {
{
.modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
CAMU_LCD_MODE | CAML_LCD_MODE,
.muxregs = clcd_lcdmode_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
},
};
static struct spear_pingroup clcd_lcdmode_pingroup = {
.name = "clcd_lcdmode_grp",
.pins = clcd_lcdmode_pins,
.npins = ARRAY_SIZE(clcd_lcdmode_pins),
.modemuxs = clcd_lcdmode_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
};
/* clcd_pfmode_pins */
static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
static struct spear_muxreg clcd_pfmode_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_modemux clcd_pfmode_modemux[] = {
{
.modes = PHOTO_FRAME_MODE,
.muxregs = clcd_pfmode_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
},
};
static struct spear_pingroup clcd_pfmode_pingroup = {
.name = "clcd_pfmode_grp",
.pins = clcd_pfmode_pins,
.npins = ARRAY_SIZE(clcd_pfmode_pins),
.modemuxs = clcd_pfmode_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
};
static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
};
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* tdm_pins */
static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
static struct spear_muxreg tdm_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_modemux tdm_modemux[] = {
{
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
.muxregs = tdm_muxreg,
.nmuxregs = ARRAY_SIZE(tdm_muxreg),
},
};
static struct spear_pingroup tdm_pingroup = {
.name = "tdm_grp",
.pins = tdm_pins,
.npins = ARRAY_SIZE(tdm_pins),
.modemuxs = tdm_modemux,
.nmodemuxs = ARRAY_SIZE(tdm_modemux),
};
static const char *const tdm_grps[] = { "tdm_grp" };
static struct spear_function tdm_function = {
.name = "tdm",
.groups = tdm_grps,
.ngroups = ARRAY_SIZE(tdm_grps),
};
/* i2c_clk_pins */
static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
static struct spear_muxreg i2c_clk_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_modemux i2c_clk_modemux[] = {
{
.modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
| CAML_LCD_MODE,
.muxregs = i2c_clk_muxreg,
.nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
},
};
static struct spear_pingroup i2c_clk_pingroup = {
.name = "i2c_clk_grp_grp",
.pins = i2c_clk_pins,
.npins = ARRAY_SIZE(i2c_clk_pins),
.modemuxs = i2c_clk_modemux,
.nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
};
static const char *const i2c_grps[] = { "i2c_clk_grp" };
static struct spear_function i2c_function = {
.name = "i2c1",
.groups = i2c_grps,
.ngroups = ARRAY_SIZE(i2c_grps),
};
/* caml_pins */
static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
static struct spear_muxreg caml_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux caml_modemux[] = {
{
.modes = CAML_LCDW_MODE | CAML_LCD_MODE,
.muxregs = caml_muxreg,
.nmuxregs = ARRAY_SIZE(caml_muxreg),
},
};
static struct spear_pingroup caml_pingroup = {
.name = "caml_grp",
.pins = caml_pins,
.npins = ARRAY_SIZE(caml_pins),
.modemuxs = caml_modemux,
.nmodemuxs = ARRAY_SIZE(caml_modemux),
};
/* camu_pins */
static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
static struct spear_muxreg camu_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux camu_modemux[] = {
{
.modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
.muxregs = camu_muxreg,
.nmuxregs = ARRAY_SIZE(camu_muxreg),
},
};
static struct spear_pingroup camu_pingroup = {
.name = "camu_grp",
.pins = camu_pins,
.npins = ARRAY_SIZE(camu_pins),
.modemuxs = camu_modemux,
.nmodemuxs = ARRAY_SIZE(camu_modemux),
};
static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
static struct spear_function cam_function = {
.name = "cam",
.groups = cam_grps,
.ngroups = ARRAY_SIZE(cam_grps),
};
/* dac_pins */
static const unsigned dac_pins[] = { 43, 44 };
static struct spear_muxreg dac_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK,
.val = 0,
},
};
static struct spear_modemux dac_modemux[] = {
{
.modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
.muxregs = dac_muxreg,
.nmuxregs = ARRAY_SIZE(dac_muxreg),
},
};
static struct spear_pingroup dac_pingroup = {
.name = "dac_grp",
.pins = dac_pins,
.npins = ARRAY_SIZE(dac_pins),
.modemuxs = dac_modemux,
.nmodemuxs = ARRAY_SIZE(dac_modemux),
};
static const char *const dac_grps[] = { "dac_grp" };
static struct spear_function dac_function = {
.name = "dac",
.groups = dac_grps,
.ngroups = ARRAY_SIZE(dac_grps),
};
/* i2s_pins */
static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
static struct spear_muxreg i2s_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_modemux i2s_modemux[] = {
{
.modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
.muxregs = i2s_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_muxreg),
},
};
static struct spear_pingroup i2s_pingroup = {
.name = "i2s_grp",
.pins = i2s_pins,
.npins = ARRAY_SIZE(i2s_pins),
.modemuxs = i2s_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_modemux),
};
static const char *const i2s_grps[] = { "i2s_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* sdhci_4bit_pins */
static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
static struct spear_muxreg sdhci_4bit_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
.val = 0,
},
};
static struct spear_modemux sdhci_4bit_modemux[] = {
{
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
.muxregs = sdhci_4bit_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
},
};
static struct spear_pingroup sdhci_4bit_pingroup = {
.name = "sdhci_4bit_grp",
.pins = sdhci_4bit_pins,
.npins = ARRAY_SIZE(sdhci_4bit_pins),
.modemuxs = sdhci_4bit_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
};
/* sdhci_8bit_pins */
static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
33 };
static struct spear_muxreg sdhci_8bit_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux sdhci_8bit_modemux[] = {
{
.modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
CAMU_WLCD_MODE | CAML_LCD_MODE,
.muxregs = sdhci_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
},
};
static struct spear_pingroup sdhci_8bit_pingroup = {
.name = "sdhci_8bit_grp",
.pins = sdhci_8bit_pins,
.npins = ARRAY_SIZE(sdhci_8bit_pins),
.modemuxs = sdhci_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
};
static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* gpio1_0_to_3_pins */
static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_modemux gpio1_0_to_3_modemux[] = {
{
.modes = PHOTO_FRAME_MODE,
.muxregs = gpio1_0_to_3_muxreg,
.nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
},
};
static struct spear_pingroup gpio1_0_to_3_pingroup = {
.name = "gpio1_0_to_3_grp",
.pins = gpio1_0_to_3_pins,
.npins = ARRAY_SIZE(gpio1_0_to_3_pins),
.modemuxs = gpio1_0_to_3_modemux,
.nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
};
/* gpio1_4_to_7_pins */
static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_modemux gpio1_4_to_7_modemux[] = {
{
.modes = PHOTO_FRAME_MODE,
.muxregs = gpio1_4_to_7_muxreg,
.nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
},
};
static struct spear_pingroup gpio1_4_to_7_pingroup = {
.name = "gpio1_4_to_7_grp",
.pins = gpio1_4_to_7_pins,
.npins = ARRAY_SIZE(gpio1_4_to_7_pins),
.modemuxs = gpio1_4_to_7_modemux,
.nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
};
static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
};
static struct spear_function gpio1_function = {
.name = "gpio1",
.groups = gpio1_grps,
.ngroups = ARRAY_SIZE(gpio1_grps),
};
/* pingroups */
static struct spear_pingroup *spear300_pingroups[] = {
SPEAR3XX_COMMON_PINGROUPS,
&fsmc_2chips_pingroup,
&fsmc_4chips_pingroup,
&clcd_lcdmode_pingroup,
&clcd_pfmode_pingroup,
&tdm_pingroup,
&i2c_clk_pingroup,
&caml_pingroup,
&camu_pingroup,
&dac_pingroup,
&i2s_pingroup,
&sdhci_4bit_pingroup,
&sdhci_8bit_pingroup,
&gpio1_0_to_3_pingroup,
&gpio1_4_to_7_pingroup,
};
/* functions */
static struct spear_function *spear300_functions[] = {
SPEAR3XX_COMMON_FUNCTIONS,
&fsmc_function,
&clcd_function,
&tdm_function,
&i2c_function,
&cam_function,
&dac_function,
&i2s_function,
&sdhci_function,
&gpio1_function,
};
static const struct of_device_id spear300_pinctrl_of_match[] = {
{
.compatible = "st,spear300-pinmux",
},
{},
};
static int spear300_pinctrl_probe(struct platform_device *pdev)
{
spear3xx_machdata.groups = spear300_pingroups;
spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
spear3xx_machdata.functions = spear300_functions;
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
spear3xx_machdata.gpio_pingroups = NULL;
spear3xx_machdata.ngpio_pingroups = 0;
spear3xx_machdata.modes_supported = true;
spear3xx_machdata.pmx_modes = spear300_pmx_modes;
spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
return spear_pinctrl_probe(pdev, &spear3xx_machdata);
}
static struct platform_driver spear300_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = spear300_pinctrl_of_match,
},
.probe = spear300_pinctrl_probe,
};
static int __init spear300_pinctrl_init(void)
{
return platform_driver_register(&spear300_pinctrl_driver);
}
arch_initcall(spear300_pinctrl_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear300.c
|
/*
* Driver for the ST Microelectronics SPEAr310 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear3xx.h"
#define DRIVER_NAME "spear310-pinmux"
/* addresses */
#define PMX_CONFIG_REG 0x08
/* emi_cs_0_to_5_pins */
static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_modemux emi_cs_0_to_5_modemux[] = {
{
.muxregs = emi_cs_0_to_5_muxreg,
.nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
},
};
static struct spear_pingroup emi_cs_0_to_5_pingroup = {
.name = "emi_cs_0_to_5_grp",
.pins = emi_cs_0_to_5_pins,
.npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
.modemuxs = emi_cs_0_to_5_modemux,
.nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
};
static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
static struct spear_function emi_cs_0_to_5_function = {
.name = "emi",
.groups = emi_cs_0_to_5_grps,
.ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
};
/* uart1_pins */
static const unsigned uart1_pins[] = { 0, 1 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_FIRDA_MASK,
.val = 0,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* uart2_pins */
static const unsigned uart2_pins[] = { 43, 44 };
static struct spear_muxreg uart2_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK,
.val = 0,
},
};
static struct spear_modemux uart2_modemux[] = {
{
.muxregs = uart2_muxreg,
.nmuxregs = ARRAY_SIZE(uart2_muxreg),
},
};
static struct spear_pingroup uart2_pingroup = {
.name = "uart2_grp",
.pins = uart2_pins,
.npins = ARRAY_SIZE(uart2_pins),
.modemuxs = uart2_modemux,
.nmodemuxs = ARRAY_SIZE(uart2_modemux),
};
static const char *const uart2_grps[] = { "uart2_grp" };
static struct spear_function uart2_function = {
.name = "uart2",
.groups = uart2_grps,
.ngroups = ARRAY_SIZE(uart2_grps),
};
/* uart3_pins */
static const unsigned uart3_pins[] = { 37, 38 };
static struct spear_muxreg uart3_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_modemux uart3_modemux[] = {
{
.muxregs = uart3_muxreg,
.nmuxregs = ARRAY_SIZE(uart3_muxreg),
},
};
static struct spear_pingroup uart3_pingroup = {
.name = "uart3_grp",
.pins = uart3_pins,
.npins = ARRAY_SIZE(uart3_pins),
.modemuxs = uart3_modemux,
.nmodemuxs = ARRAY_SIZE(uart3_modemux),
};
static const char *const uart3_grps[] = { "uart3_grp" };
static struct spear_function uart3_function = {
.name = "uart3",
.groups = uart3_grps,
.ngroups = ARRAY_SIZE(uart3_grps),
};
/* uart4_pins */
static const unsigned uart4_pins[] = { 39, 40 };
static struct spear_muxreg uart4_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_modemux uart4_modemux[] = {
{
.muxregs = uart4_muxreg,
.nmuxregs = ARRAY_SIZE(uart4_muxreg),
},
};
static struct spear_pingroup uart4_pingroup = {
.name = "uart4_grp",
.pins = uart4_pins,
.npins = ARRAY_SIZE(uart4_pins),
.modemuxs = uart4_modemux,
.nmodemuxs = ARRAY_SIZE(uart4_modemux),
};
static const char *const uart4_grps[] = { "uart4_grp" };
static struct spear_function uart4_function = {
.name = "uart4",
.groups = uart4_grps,
.ngroups = ARRAY_SIZE(uart4_grps),
};
/* uart5_pins */
static const unsigned uart5_pins[] = { 41, 42 };
static struct spear_muxreg uart5_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_modemux uart5_modemux[] = {
{
.muxregs = uart5_muxreg,
.nmuxregs = ARRAY_SIZE(uart5_muxreg),
},
};
static struct spear_pingroup uart5_pingroup = {
.name = "uart5_grp",
.pins = uart5_pins,
.npins = ARRAY_SIZE(uart5_pins),
.modemuxs = uart5_modemux,
.nmodemuxs = ARRAY_SIZE(uart5_modemux),
};
static const char *const uart5_grps[] = { "uart5_grp" };
static struct spear_function uart5_function = {
.name = "uart5",
.groups = uart5_grps,
.ngroups = ARRAY_SIZE(uart5_grps),
};
/* fsmc_pins */
static const unsigned fsmc_pins[] = { 34, 35, 36 };
static struct spear_muxreg fsmc_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_modemux fsmc_modemux[] = {
{
.muxregs = fsmc_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_muxreg),
},
};
static struct spear_pingroup fsmc_pingroup = {
.name = "fsmc_grp",
.pins = fsmc_pins,
.npins = ARRAY_SIZE(fsmc_pins),
.modemuxs = fsmc_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* rs485_0_pins */
static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
static struct spear_muxreg rs485_0_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux rs485_0_modemux[] = {
{
.muxregs = rs485_0_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
},
};
static struct spear_pingroup rs485_0_pingroup = {
.name = "rs485_0_grp",
.pins = rs485_0_pins,
.npins = ARRAY_SIZE(rs485_0_pins),
.modemuxs = rs485_0_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
};
static const char *const rs485_0_grps[] = { "rs485_0" };
static struct spear_function rs485_0_function = {
.name = "rs485_0",
.groups = rs485_0_grps,
.ngroups = ARRAY_SIZE(rs485_0_grps),
};
/* rs485_1_pins */
static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
static struct spear_muxreg rs485_1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux rs485_1_modemux[] = {
{
.muxregs = rs485_1_muxreg,
.nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
},
};
static struct spear_pingroup rs485_1_pingroup = {
.name = "rs485_1_grp",
.pins = rs485_1_pins,
.npins = ARRAY_SIZE(rs485_1_pins),
.modemuxs = rs485_1_modemux,
.nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
};
static const char *const rs485_1_grps[] = { "rs485_1" };
static struct spear_function rs485_1_function = {
.name = "rs485_1",
.groups = rs485_1_grps,
.ngroups = ARRAY_SIZE(rs485_1_grps),
};
/* tdm_pins */
static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
static struct spear_muxreg tdm_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
},
};
static struct spear_modemux tdm_modemux[] = {
{
.muxregs = tdm_muxreg,
.nmuxregs = ARRAY_SIZE(tdm_muxreg),
},
};
static struct spear_pingroup tdm_pingroup = {
.name = "tdm_grp",
.pins = tdm_pins,
.npins = ARRAY_SIZE(tdm_pins),
.modemuxs = tdm_modemux,
.nmodemuxs = ARRAY_SIZE(tdm_modemux),
};
static const char *const tdm_grps[] = { "tdm_grp" };
static struct spear_function tdm_function = {
.name = "tdm",
.groups = tdm_grps,
.ngroups = ARRAY_SIZE(tdm_grps),
};
/* pingroups */
static struct spear_pingroup *spear310_pingroups[] = {
SPEAR3XX_COMMON_PINGROUPS,
&emi_cs_0_to_5_pingroup,
&uart1_pingroup,
&uart2_pingroup,
&uart3_pingroup,
&uart4_pingroup,
&uart5_pingroup,
&fsmc_pingroup,
&rs485_0_pingroup,
&rs485_1_pingroup,
&tdm_pingroup,
};
/* functions */
static struct spear_function *spear310_functions[] = {
SPEAR3XX_COMMON_FUNCTIONS,
&emi_cs_0_to_5_function,
&uart1_function,
&uart2_function,
&uart3_function,
&uart4_function,
&uart5_function,
&fsmc_function,
&rs485_0_function,
&rs485_1_function,
&tdm_function,
};
static const struct of_device_id spear310_pinctrl_of_match[] = {
{
.compatible = "st,spear310-pinmux",
},
{},
};
static int spear310_pinctrl_probe(struct platform_device *pdev)
{
spear3xx_machdata.groups = spear310_pingroups;
spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
spear3xx_machdata.functions = spear310_functions;
spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
spear3xx_machdata.modes_supported = false;
return spear_pinctrl_probe(pdev, &spear3xx_machdata);
}
static struct platform_driver spear310_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = spear310_pinctrl_of_match,
},
.probe = spear310_pinctrl_probe,
};
static int __init spear310_pinctrl_init(void)
{
return platform_driver_register(&spear310_pinctrl_driver);
}
arch_initcall(spear310_pinctrl_init);
|
linux-master
|
drivers/pinctrl/spear/pinctrl-spear310.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (C) 2019 IBM Corp. */
/* Pieces to enable drivers to implement the .set callback */
#include "pinmux-aspeed.h"
static const char *const aspeed_pinmux_ips[] = {
[ASPEED_IP_SCU] = "SCU",
[ASPEED_IP_GFX] = "GFX",
[ASPEED_IP_LPC] = "LPC",
};
static inline void aspeed_sig_desc_print_val(
const struct aspeed_sig_desc *desc, bool enable, u32 rv)
{
pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
aspeed_pinmux_ips[desc->ip], desc->reg,
desc->mask, enable ? desc->enable : desc->disable,
(rv & desc->mask) >> __ffs(desc->mask), rv);
}
/**
* aspeed_sig_desc_eval() - Query the enabled or disabled state of a signal
* descriptor.
*
* @desc: The signal descriptor of interest
* @enabled: True to query the enabled state, false to query disabled state
* @map: The IP block's regmap instance
*
* Return: 1 if the descriptor's bitfield is configured to the state
* selected by @enabled, 0 if not, and less than zero if an unrecoverable
* failure occurred
*
* Evaluation of descriptor state is non-trivial in that it is not a binary
* outcome: The bitfields can be greater than one bit in size and thus can take
* a value that is neither the enabled nor disabled state recorded in the
* descriptor (typically this means a different function to the one of interest
* is enabled). Thus we must explicitly test for either condition as required.
*/
int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
bool enabled, struct regmap *map)
{
int ret;
unsigned int raw;
u32 want;
if (!map)
return -ENODEV;
ret = regmap_read(map, desc->reg, &raw);
if (ret)
return ret;
aspeed_sig_desc_print_val(desc, enabled, raw);
want = enabled ? desc->enable : desc->disable;
return ((raw & desc->mask) >> __ffs(desc->mask)) == want;
}
/**
* aspeed_sig_expr_eval - Query the enabled or disabled state for a
* mux function's signal on a pin
*
* @ctx: The driver context for the pinctrl IP
* @expr: An expression controlling the signal for a mux function on a pin
* @enabled: True to query the enabled state, false to query disabled state
*
* Return: 1 if the expression composed by @enabled evaluates true, 0 if not,
* and less than zero if an unrecoverable failure occurred.
*
* A mux function is enabled or disabled if the function's signal expression
* for each pin in the function's pin group evaluates true for the desired
* state. An signal expression evaluates true if all of its associated signal
* descriptors evaluate true for the desired state.
*
* If an expression's state is described by more than one bit, either through
* multi-bit bitfields in a single signal descriptor or through multiple signal
* descriptors of a single bit then it is possible for the expression to be in
* neither the enabled nor disabled state. Thus we must explicitly test for
* either condition as required.
*/
int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled)
{
int ret;
int i;
if (ctx->ops->eval)
return ctx->ops->eval(ctx, expr, enabled);
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
if (ret <= 0)
return ret;
}
return 1;
}
|
linux-master
|
drivers/pinctrl/aspeed/pinmux-aspeed.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 IBM Corp.
*/
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/string.h>
#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinmux-aspeed.h"
#include "pinctrl-aspeed.h"
/* Wrap some of the common macros for clarity */
#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
/*
* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
* references registers by the device/offset mnemonic. The register macros
* below are named the same way to ease transcription and verification (as
* opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
* reference registers beyond those dedicated to pinmux, such as the system
* reset control and MAC clock configuration registers.
*/
#define SCU2C 0x2C /* Misc. Control Register */
#define SCU3C 0x3C /* System Reset Control/Status Register */
#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
#define SCU80 0x80 /* Multi-function Pin Control #1 */
#define SCU84 0x84 /* Multi-function Pin Control #2 */
#define SCU88 0x88 /* Multi-function Pin Control #3 */
#define SCU8C 0x8C /* Multi-function Pin Control #4 */
#define SCU90 0x90 /* Multi-function Pin Control #5 */
#define SCU94 0x94 /* Multi-function Pin Control #6 */
#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
#define SCUAC 0xAC /* Multi-function Pin Control #10 */
#define HW_STRAP2 0xD0 /* Strapping */
/*
* Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK,
* TIMER3 etc.
*
* Pins are defined in GPIO bank order:
*
* GPIOA0: 0
* ...
* GPIOA7: 7
* GPIOB0: 8
* ...
* GPIOZ7: 207
* GPIOAA0: 208
* ...
* GPIOAB3: 219
*
* Not all pins have their signals defined (yet).
*/
#define D6 0
SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
#define B5 1
SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
#define A4 2
SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
#define E6 3
SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
#define C5 4
SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
FUNC_GROUP_DECL(TIMER5, C5);
#define B4 5
SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6);
FUNC_GROUP_DECL(TIMER6, B4);
FUNC_GROUP_DECL(I2C9, C5, B4);
#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
#define A3 6
SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7);
FUNC_GROUP_DECL(TIMER7, A3);
#define D5 7
SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8);
FUNC_GROUP_DECL(TIMER8, D5);
FUNC_GROUP_DECL(MDIO2, A3, D5);
#define J21 8
SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8));
#define J20 9
SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9));
#define H18 10
SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
#define F18 11
SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
#define E19 12
SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS);
PIN_DECL_1(E19, GPIOB4, LPCRST);
FUNC_GROUP_DECL(LPCRST, E19);
#define H19 13
#define H19_DESC SIG_DESC_SET(SCU80, 13)
SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC);
SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC);
PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI);
FUNC_GROUP_DECL(LPCPD, H19);
FUNC_GROUP_DECL(LPCSMI, H19);
#define H20 14
SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
#define E18 15
SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST,
SIG_DESC_SET(SCU80, 15),
SIG_DESC_BIT(SCU90, 31, 0),
SIG_DESC_SET(SCU3C, 3));
SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1,
SIG_DESC_SET(SCU80, 15),
SIG_DESC_SET(SCU90, 31));
PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1);
FUNC_GROUP_DECL(EXTRST, E18);
FUNC_GROUP_DECL(SPICS1, E18);
#define SD1_DESC SIG_DESC_SET(SCU90, 0)
#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
#define C4 16
SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC);
PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10);
#define B3 17
SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC);
PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10);
FUNC_GROUP_DECL(I2C10, C4, B3);
#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
#define A2 18
SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC);
PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11);
#define E5 19
SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC);
PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11);
FUNC_GROUP_DECL(I2C11, A2, E5);
#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
#define D4 20
SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC);
PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12);
#define C3 21
SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC);
PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12);
FUNC_GROUP_DECL(I2C12, D4, C3);
#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
#define B2 22
SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC);
PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13);
#define A1 23
SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC);
PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13);
FUNC_GROUP_DECL(I2C13, B2, A1);
FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
#define SD2_DESC SIG_DESC_SET(SCU90, 1)
#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
#define A18 24
SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID);
PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN);
#define D16 25
SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID);
PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT);
FUNC_GROUP_DECL(GPID0, A18, D16);
#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
#define B17 26
SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID);
PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN);
#define A17 27
SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID);
PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT);
FUNC_GROUP_DECL(GPID2, B17, A17);
#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
#define C16 28
SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID);
PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN);
#define B16 29
SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID);
PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT);
FUNC_GROUP_DECL(GPID4, C16, B16);
#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
#define A16 30
SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID);
PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN);
#define E15 31
SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID);
PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT);
FUNC_GROUP_DECL(GPID6, A16, E15);
FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
#define D15 32
SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE);
PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN);
FUNC_GROUP_DECL(NCTS3, D15);
#define C15 33
SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE);
PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT);
FUNC_GROUP_DECL(NDCD3, C15);
FUNC_GROUP_DECL(GPIE0, D15, C15);
#define B15 34
SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE);
PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN);
FUNC_GROUP_DECL(NDSR3, B15);
#define A15 35
SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE);
PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT);
FUNC_GROUP_DECL(NRI3, A15);
FUNC_GROUP_DECL(GPIE2, B15, A15);
#define E14 36
SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE);
PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN);
FUNC_GROUP_DECL(NDTR3, E14);
#define D14 37
SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE);
PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT);
FUNC_GROUP_DECL(NRTS3, D14);
FUNC_GROUP_DECL(GPIE4, E14, D14);
#define C14 38
SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE);
PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN);
FUNC_GROUP_DECL(TXD3, C14);
#define B14 39
SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE);
PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT);
FUNC_GROUP_DECL(RXD3, B14);
FUNC_GROUP_DECL(GPIE6, C14, B14);
#define D18 40
SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24));
#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0)
#define B19 41
SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12));
SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI);
PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI);
FUNC_GROUP_DECL(NDCD4, B19);
FUNC_GROUP_DECL(SIOPBI, B19);
#define A20 42
SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12));
SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI);
PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD);
FUNC_GROUP_DECL(NDSR4, A20);
FUNC_GROUP_DECL(SIOPWRGD, A20);
#define D17 43
SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI);
PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO);
FUNC_GROUP_DECL(NRI4, D17);
FUNC_GROUP_DECL(SIOPBO, D17);
#define B18 44
SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28));
#define A19 45
SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29));
SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI);
PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI);
FUNC_GROUP_DECL(NDTS4, A19);
FUNC_GROUP_DECL(SIOSCI, A19);
#define E16 46
SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
#define C17 47
SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
#define A14 48
SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0));
#define E13 49
SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
#define D13 50
SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2));
#define C13 51
SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3));
#define B13 52
SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4));
PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1);
FUNC_GROUP_DECL(OSCCLK, B13);
FUNC_GROUP_DECL(WDTRST1, B13);
#define Y21 53
SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5));
PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2);
FUNC_GROUP_DECL(USBCKI, Y21);
FUNC_GROUP_DECL(WDTRST2, Y21);
#define AA22 54
SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
#define U18 55
SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
#define UART6_DESC SIG_DESC_SET(SCU90, 7)
#define ROM16_DESC SIG_DESC_SET(SCU90, 6)
#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
#define A8 56
SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC);
PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
#define C7 57
SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC);
PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6);
#define B7 58
SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC);
PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6);
#define A7 59
SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC);
PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6);
#define D7 60
SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC);
PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6);
#define B6 61
SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC);
PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6);
#define A6 62
SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC);
PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6);
#define E7 63
SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC);
SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S);
SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC);
PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6);
FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
#define SPI1_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
#define SPI1PASSTHRU_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define C22 64
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(C22, GPIOI0, SYSCS);
#define G18 65
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(G18, GPIOI1, SYSCK);
#define D19 66
SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(D19, GPIOI2, SYSDO);
#define C20 67
SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(C20, GPIOI3, SYSDI);
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
#define B22 68
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
SIG_EXPR_PTR(SPI1CS0, SPI1),
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC);
PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS);
#define G19 69
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
SIG_EXPR_PTR(SPI1CK, SPI1),
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC);
PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK);
#define C18 70
SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1DO, SPI1,
SIG_EXPR_PTR(SPI1DO, SPI1),
SIG_EXPR_PTR(SPI1DO, SPI1DEBUG),
SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC);
PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO);
#define E20 71
SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1DI, SPI1,
SIG_EXPR_PTR(SPI1DI, SPI1),
SIG_EXPR_PTR(SPI1DI, SPI1DEBUG),
SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC);
PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI);
FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20);
FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20);
FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20);
FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20);
#define J5 72
SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8));
#define J4 73
SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9));
#define K5 74
SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
#define J3 75
SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
#define T4 76
SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12));
#define U2 77
SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13));
#define T2 78
SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14));
#define T1 79
SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define E3 80
SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC);
PIN_DECL_1(E3, GPIOK0, SCL5);
#define D2 81
SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC);
PIN_DECL_1(D2, GPIOK1, SDA5);
FUNC_GROUP_DECL(I2C5, E3, D2);
#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
#define C1 82
SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC);
PIN_DECL_1(C1, GPIOK2, SCL6);
#define F4 83
SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC);
PIN_DECL_1(F4, GPIOK3, SDA6);
FUNC_GROUP_DECL(I2C6, C1, F4);
#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
#define E2 84
SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC);
PIN_DECL_1(E2, GPIOK4, SCL7);
#define D1 85
SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC);
PIN_DECL_1(D1, GPIOK5, SDA7);
FUNC_GROUP_DECL(I2C7, E2, D1);
#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
#define G5 86
SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC);
PIN_DECL_1(G5, GPIOK6, SCL8);
#define F3 87
SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC);
PIN_DECL_1(F3, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, G5, F3);
#define U1 88
SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
#define T5 89
#define T5_DESC SIG_DESC_SET(SCU84, 17)
SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC);
SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC);
SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC);
SIG_EXPR_LIST_DECL(VPIDE, VPI,
SIG_EXPR_PTR(VPIDE, VPI18),
SIG_EXPR_PTR(VPIDE, VPI24),
SIG_EXPR_PTR(VPIDE, VPI30));
SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI);
SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC);
PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1);
FUNC_GROUP_DECL(NDCD1, T5);
#define U3 90
#define U3_DESC SIG_DESC_SET(SCU84, 18)
SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC);
SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC);
SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC);
SIG_EXPR_LIST_DECL(VPIODD, VPI,
SIG_EXPR_PTR(VPIODD, VPI18),
SIG_EXPR_PTR(VPIODD, VPI24),
SIG_EXPR_PTR(VPIODD, VPI30));
SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI);
SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC);
PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1);
FUNC_GROUP_DECL(NDSR1, U3);
#define V1 91
#define V1_DESC SIG_DESC_SET(SCU84, 19)
SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC);
SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC);
SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC);
SIG_EXPR_LIST_DECL(VPIHS, VPI,
SIG_EXPR_PTR(VPIHS, VPI18),
SIG_EXPR_PTR(VPIHS, VPI24),
SIG_EXPR_PTR(VPIHS, VPI30));
SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI);
SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC);
PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1);
FUNC_GROUP_DECL(NRI1, V1);
#define U4 92
#define U4_DESC SIG_DESC_SET(SCU84, 20)
SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC);
SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC);
SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC);
SIG_EXPR_LIST_DECL(VPIVS, VPI,
SIG_EXPR_PTR(VPIVS, VPI18),
SIG_EXPR_PTR(VPIVS, VPI24),
SIG_EXPR_PTR(VPIVS, VPI30));
SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI);
SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC);
PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1);
FUNC_GROUP_DECL(NDTR1, U4);
#define V2 93
#define V2_DESC SIG_DESC_SET(SCU84, 21)
SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC);
SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC);
SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC);
SIG_EXPR_LIST_DECL(VPICLK, VPI,
SIG_EXPR_PTR(VPICLK, VPI18),
SIG_EXPR_PTR(VPICLK, VPI24),
SIG_EXPR_PTR(VPICLK, VPI30));
SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI);
SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC);
PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1);
FUNC_GROUP_DECL(NRTS1, V2);
#define W1 94
#define W1_DESC SIG_DESC_SET(SCU84, 22)
SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC);
PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1);
FUNC_GROUP_DECL(TXD1, W1);
#define U5 95
#define U5_DESC SIG_DESC_SET(SCU84, 23)
SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC);
PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1);
FUNC_GROUP_DECL(RXD1, U5);
#define V3 96
#define V3_DESC SIG_DESC_SET(SCU84, 24)
SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC);
SIG_EXPR_LIST_DECL(VPIOB2, VPI,
SIG_EXPR_PTR(VPIOB2, VPI18),
SIG_EXPR_PTR(VPIOB2, VPI24),
SIG_EXPR_PTR(VPIOB2, VPI30));
SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI);
SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC);
PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2);
FUNC_GROUP_DECL(NCTS2, V3);
#define W2 97
#define W2_DESC SIG_DESC_SET(SCU84, 25)
SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC);
SIG_EXPR_LIST_DECL(VPIOB3, VPI,
SIG_EXPR_PTR(VPIOB3, VPI18),
SIG_EXPR_PTR(VPIOB3, VPI24),
SIG_EXPR_PTR(VPIOB3, VPI30));
SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI);
SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC);
PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2);
FUNC_GROUP_DECL(NDCD2, W2);
#define Y1 98
#define Y1_DESC SIG_DESC_SET(SCU84, 26)
SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC);
SIG_EXPR_LIST_DECL(VPIOB4, VPI,
SIG_EXPR_PTR(VPIOB4, VPI18),
SIG_EXPR_PTR(VPIOB4, VPI24),
SIG_EXPR_PTR(VPIOB4, VPI30));
SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI);
SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC);
PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2);
FUNC_GROUP_DECL(NDSR2, Y1);
#define V4 99
#define V4_DESC SIG_DESC_SET(SCU84, 27)
SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC);
SIG_EXPR_LIST_DECL(VPIOB5, VPI,
SIG_EXPR_PTR(VPIOB5, VPI18),
SIG_EXPR_PTR(VPIOB5, VPI24),
SIG_EXPR_PTR(VPIOB5, VPI30));
SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI);
SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC);
PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2);
FUNC_GROUP_DECL(NRI2, V4);
#define W3 100
#define W3_DESC SIG_DESC_SET(SCU84, 28)
SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC);
SIG_EXPR_LIST_DECL(VPIOB6, VPI,
SIG_EXPR_PTR(VPIOB6, VPI18),
SIG_EXPR_PTR(VPIOB6, VPI24),
SIG_EXPR_PTR(VPIOB6, VPI30));
SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI);
SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC);
PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2);
FUNC_GROUP_DECL(NDTR2, W3);
#define Y2 101
#define Y2_DESC SIG_DESC_SET(SCU84, 29)
SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC);
SIG_EXPR_LIST_DECL(VPIOB7, VPI,
SIG_EXPR_PTR(VPIOB7, VPI18),
SIG_EXPR_PTR(VPIOB7, VPI24),
SIG_EXPR_PTR(VPIOB7, VPI30));
SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI);
SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC);
PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2);
FUNC_GROUP_DECL(NRTS2, Y2);
#define AA1 102
#define AA1_DESC SIG_DESC_SET(SCU84, 30)
SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC);
SIG_EXPR_LIST_DECL(VPIOB8, VPI,
SIG_EXPR_PTR(VPIOB8, VPI18),
SIG_EXPR_PTR(VPIOB8, VPI24),
SIG_EXPR_PTR(VPIOB8, VPI30));
SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI);
SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC);
PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2);
FUNC_GROUP_DECL(TXD2, AA1);
#define V5 103
#define V5_DESC SIG_DESC_SET(SCU84, 31)
SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC);
SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC);
SIG_EXPR_LIST_DECL(VPIOB9, VPI,
SIG_EXPR_PTR(VPIOB9, VPI18),
SIG_EXPR_PTR(VPIOB9, VPI24),
SIG_EXPR_PTR(VPIOB9, VPI30));
SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI);
SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC);
PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2);
FUNC_GROUP_DECL(RXD2, V5);
#define W4 104
#define W4_DESC SIG_DESC_SET(SCU88, 0)
SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC);
PIN_DECL_2(W4, GPION0, VPIG0, PWM0);
FUNC_GROUP_DECL(PWM0, W4);
#define Y3 105
#define Y3_DESC SIG_DESC_SET(SCU88, 1)
SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC);
PIN_DECL_2(Y3, GPION1, VPIG1, PWM1);
FUNC_GROUP_DECL(PWM1, Y3);
#define AA2 106
#define AA2_DESC SIG_DESC_SET(SCU88, 2)
SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC);
SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC);
SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC);
SIG_EXPR_LIST_DECL(VPIG2, VPI,
SIG_EXPR_PTR(VPIG2, VPI18),
SIG_EXPR_PTR(VPIG2, VPI24),
SIG_EXPR_PTR(VPIG2, VPI30));
SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI);
SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC);
PIN_DECL_2(AA2, GPION2, VPIG2, PWM2);
FUNC_GROUP_DECL(PWM2, AA2);
#define AB1 107
#define AB1_DESC SIG_DESC_SET(SCU88, 3)
SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC);
SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC);
SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC);
SIG_EXPR_LIST_DECL(VPIG3, VPI,
SIG_EXPR_PTR(VPIG3, VPI18),
SIG_EXPR_PTR(VPIG3, VPI24),
SIG_EXPR_PTR(VPIG3, VPI30));
SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI);
SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC);
PIN_DECL_2(AB1, GPION3, VPIG3, PWM3);
FUNC_GROUP_DECL(PWM3, AB1);
#define W5 108
#define W5_DESC SIG_DESC_SET(SCU88, 4)
SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC);
SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC);
SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC);
SIG_EXPR_LIST_DECL(VPIG4, VPI,
SIG_EXPR_PTR(VPIG4, VPI18),
SIG_EXPR_PTR(VPIG4, VPI24),
SIG_EXPR_PTR(VPIG4, VPI30));
SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI);
SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC);
PIN_DECL_2(W5, GPION4, VPIG4, PWM4);
FUNC_GROUP_DECL(PWM4, W5);
#define Y4 109
#define Y4_DESC SIG_DESC_SET(SCU88, 5)
SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC);
SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC);
SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC);
SIG_EXPR_LIST_DECL(VPIG5, VPI,
SIG_EXPR_PTR(VPIG5, VPI18),
SIG_EXPR_PTR(VPIG5, VPI24),
SIG_EXPR_PTR(VPIG5, VPI30));
SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI);
SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC);
PIN_DECL_2(Y4, GPION5, VPIG5, PWM5);
FUNC_GROUP_DECL(PWM5, Y4);
#define AA3 110
#define AA3_DESC SIG_DESC_SET(SCU88, 6)
SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC);
PIN_DECL_2(AA3, GPION6, VPIG6, PWM6);
FUNC_GROUP_DECL(PWM6, AA3);
#define AB2 111
#define AB2_DESC SIG_DESC_SET(SCU88, 7)
SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC);
PIN_DECL_2(AB2, GPION7, VPIG7, PWM7);
FUNC_GROUP_DECL(PWM7, AB2);
#define V6 112
SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8));
PIN_DECL_1(V6, GPIOO0, VPIG8);
#define Y5 113
SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
PIN_DECL_1(Y5, GPIOO1, VPIG9);
#define AA4 114
SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC,
SIG_DESC_SET(SCU88, 10));
PIN_DECL_1(AA4, GPIOO2, VPIR0);
#define AB3 115
SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC,
SIG_DESC_SET(SCU88, 11));
PIN_DECL_1(AB3, GPIOO3, VPIR1);
#define W6 116
SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 12));
PIN_DECL_1(W6, GPIOO4, VPIR2);
#define AA5 117
SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 13));
PIN_DECL_1(AA5, GPIOO5, VPIR3);
#define AB4 118
SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 14));
PIN_DECL_1(AB4, GPIOO6, VPIR4);
#define V7 119
SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 15));
PIN_DECL_1(V7, GPIOO7, VPIR5);
#define Y6 120
SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 16));
PIN_DECL_1(Y6, GPIOP0, VPIR6);
#define AB5 121
SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 17));
PIN_DECL_1(AB5, GPIOP1, VPIR7);
#define W7 122
SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 18));
PIN_DECL_1(W7, GPIOP2, VPIR8);
#define AA6 123
SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 19));
PIN_DECL_1(AA6, GPIOP3, VPIR9);
FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
AA22, W5, Y4, AA3, AB2);
FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7,
AA6);
FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3);
#define AB6 124
SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4);
PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4));
#define Y7 125
SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5);
PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5));
#define AA7 126
SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22));
#define AB7 127
SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23));
#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
#define D3 128
SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC);
PIN_DECL_1(D3, GPIOQ0, SCL3);
#define C2 129
SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC);
PIN_DECL_1(C2, GPIOQ1, SDA3);
FUNC_GROUP_DECL(I2C3, D3, C2);
#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
#define B1 130
SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC);
PIN_DECL_1(B1, GPIOQ2, SCL4);
#define F5 131
SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC);
PIN_DECL_1(F5, GPIOQ3, SDA4);
FUNC_GROUP_DECL(I2C4, B1, F5);
#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
#define H4 132
SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC);
PIN_DECL_1(H4, GPIOQ4, SCL14);
#define H3 133
SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC);
PIN_DECL_1(H3, GPIOQ5, SDA14);
FUNC_GROUP_DECL(I2C14, H4, H3);
/*
* There are several opportunities to document USB port 4 in the datasheet, but
* it is only mentioned in one location. Particularly, the Multi-function Pins
* Mapping and Control table in the datasheet elides the signal names,
* suggesting that port 4 may not actually be functional. As such we define the
* signal names and control bit, but don't export the capability's function or
* group.
*/
#define USB11H3_DESC SIG_DESC_SET(SCU90, 28)
#define H2 134
SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC);
PIN_DECL_1(H2, GPIOQ6, USB11HDP3);
#define H1 135
SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC);
PIN_DECL_1(H1, GPIOQ7, USB11HDN3);
#define V20 136
SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
#define W21 137
SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25));
#define Y22 138
SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26));
#define U19 139
SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27));
#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }
#define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
#define V21 140
#define V21_DESC SIG_DESC_SET(SCU88, 28)
SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL(ROMA24, ROM,
SIG_EXPR_PTR(ROMA24, ROM8),
SIG_EXPR_PTR(ROMA24, ROM16),
SIG_EXPR_PTR(ROMA24, ROM16S));
SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM);
SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF);
PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6);
#define W22 141
#define W22_DESC SIG_DESC_SET(SCU88, 29)
SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL(ROMA25, ROM,
SIG_EXPR_PTR(ROMA25, ROM8),
SIG_EXPR_PTR(ROMA25, ROM16),
SIG_EXPR_PTR(ROMA25, ROM16S));
SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM);
SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF);
PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7);
#define C6 142
SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
PIN_DECL_1(C6, GPIOR6, MDC1);
#define A5 143
SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
PIN_DECL_1(A5, GPIOR7, MDIO1);
FUNC_GROUP_DECL(MDIO1, C6, A5);
#define U21 144
#define U21_DESC SIG_DESC_SET(SCU8C, 0)
SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL(ROMD4, ROM,
SIG_EXPR_PTR(ROMD4, ROM8),
SIG_EXPR_PTR(ROMD4, ROM16),
SIG_EXPR_PTR(ROMD4, ROM16S));
SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM);
SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC);
SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24);
PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE);
#define T19 145
#define T19_DESC SIG_DESC_SET(SCU8C, 1)
SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL(ROMD5, ROM,
SIG_EXPR_PTR(ROMD5, ROM8),
SIG_EXPR_PTR(ROMD5, ROM16),
SIG_EXPR_PTR(ROMD5, ROM16S));
SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM);
SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC);
SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24);
PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS);
#define V22 146
#define V22_DESC SIG_DESC_SET(SCU8C, 2)
SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL(ROMD6, ROM,
SIG_EXPR_PTR(ROMD6, ROM8),
SIG_EXPR_PTR(ROMD6, ROM16),
SIG_EXPR_PTR(ROMD6, ROM16S));
SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM);
SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC);
SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24);
PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS);
#define U20 147
#define U20_DESC SIG_DESC_SET(SCU8C, 3)
SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL(ROMD7, ROM,
SIG_EXPR_PTR(ROMD7, ROM8),
SIG_EXPR_PTR(ROMD7, ROM16),
SIG_EXPR_PTR(ROMD7, ROM16S));
SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC);
SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24);
PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK);
#define R18 148
#define ROMOE_DESC SIG_DESC_SET(SCU8C, 4)
SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4);
SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC);
SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC);
SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC);
SIG_EXPR_LIST_DECL(ROMOE, ROM,
SIG_EXPR_PTR(ROMOE, ROM8),
SIG_EXPR_PTR(ROMOE, ROM16),
SIG_EXPR_PTR(ROMOE, ROM16S));
SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM);
PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4));
#define N21 149
#define ROMWE_DESC SIG_DESC_SET(SCU8C, 5)
SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5);
SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC);
SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC);
SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC);
SIG_EXPR_LIST_DECL(ROMWE, ROM,
SIG_EXPR_PTR(ROMWE, ROM8),
SIG_EXPR_PTR(ROMWE, ROM16),
SIG_EXPR_PTR(ROMWE, ROM16S));
SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM);
PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5));
#define L22 150
#define L22_DESC SIG_DESC_SET(SCU8C, 6)
SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL(ROMA22, ROM,
SIG_EXPR_PTR(ROMA22, ROM8),
SIG_EXPR_PTR(ROMA22, ROM16),
SIG_EXPR_PTR(ROMA22, ROM16S));
SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM);
SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF);
PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4);
#define K18 151
#define K18_DESC SIG_DESC_SET(SCU8C, 7)
SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL(ROMA23, ROM,
SIG_EXPR_PTR(ROMA23, ROM8),
SIG_EXPR_PTR(ROMA23, ROM16),
SIG_EXPR_PTR(ROMA23, ROM16S));
SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM);
SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF);
PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5);
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define A12 152
SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1);
PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0),
SIG_EXPR_LIST_PTR(A12, RMII1TXEN),
SIG_EXPR_LIST_PTR(A12, RGMII1TXCK));
#define B12 153
SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1);
PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12),
SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL));
#define C12 154
SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1);
PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2),
SIG_EXPR_LIST_PTR(C12, RMII1TXD0),
SIG_EXPR_LIST_PTR(C12, RGMII1TXD0));
#define D12 155
SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1);
PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3),
SIG_EXPR_LIST_PTR(D12, RMII1TXD1),
SIG_EXPR_LIST_PTR(D12, RGMII1TXD1));
#define E12 156
SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1);
PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12),
SIG_EXPR_LIST_PTR(E12, RGMII1TXD2));
#define A13 157
SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1);
PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13),
SIG_EXPR_LIST_PTR(A13, RGMII1TXD3));
#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
#define D9 158
SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2);
PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN),
SIG_EXPR_LIST_PTR(D9, RGMII2TXCK));
#define E9 159
SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2);
PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9),
SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL));
#define A10 160
SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2);
PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0),
SIG_EXPR_LIST_PTR(A10, RMII2TXD0),
SIG_EXPR_LIST_PTR(A10, RGMII2TXD0));
#define B10 161
SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2);
PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1),
SIG_EXPR_LIST_PTR(B10, RMII2TXD1),
SIG_EXPR_LIST_PTR(B10, RGMII2TXD1));
#define C10 162
SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2);
PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10),
SIG_EXPR_LIST_PTR(C10, RGMII2TXD2));
#define D10 163
SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2);
PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10),
SIG_EXPR_LIST_PTR(D10, RGMII2TXD3));
#define E11 164
SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1);
PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4),
SIG_EXPR_LIST_PTR(E11, RMII1RCLK),
SIG_EXPR_LIST_PTR(E11, RGMII1RXCK));
#define D11 165
SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1);
PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11),
SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL));
#define C11 166
SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1);
PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6),
SIG_EXPR_LIST_PTR(C11, RMII1RXD0),
SIG_EXPR_LIST_PTR(C11, RGMII1RXD0));
#define B11 167
SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1);
PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7),
SIG_EXPR_LIST_PTR(B11, RMII1RXD1),
SIG_EXPR_LIST_PTR(B11, RGMII1RXD1));
#define A11 168
SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1);
PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0),
SIG_EXPR_LIST_PTR(A11, RMII1CRSDV),
SIG_EXPR_LIST_PTR(A11, RGMII1RXD2));
#define E10 169
SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1);
PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1),
SIG_EXPR_LIST_PTR(E10, RMII1RXER),
SIG_EXPR_LIST_PTR(E10, RGMII1RXD3));
#define C9 170
SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2);
PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK),
SIG_EXPR_LIST_PTR(C9, RGMII2RXCK));
#define B9 171
SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2);
PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9),
SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL));
#define A9 172
SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2);
PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0),
SIG_EXPR_LIST_PTR(A9, RGMII2RXD0));
#define E8 173
SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2);
PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1),
SIG_EXPR_LIST_PTR(E8, RGMII2RXD1));
#define D8 174
SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2);
PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV),
SIG_EXPR_LIST_PTR(D8, RGMII2RXD2));
#define C8 175
SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2);
PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER),
SIG_EXPR_LIST_PTR(C8, RGMII2RXD3));
FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
#define L5 176
SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0);
PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0));
FUNC_GROUP_DECL(ADC0, L5);
#define L4 177
SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1);
PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1));
FUNC_GROUP_DECL(ADC1, L4);
#define L3 178
SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2);
PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2));
FUNC_GROUP_DECL(ADC2, L3);
#define L2 179
SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3);
PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3));
FUNC_GROUP_DECL(ADC3, L2);
#define L1 180
SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
FUNC_GROUP_DECL(ADC4, L1);
#define M5 181
SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5);
PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5));
FUNC_GROUP_DECL(ADC5, M5);
#define M4 182
SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6);
PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6));
FUNC_GROUP_DECL(ADC6, M4);
#define M3 183
SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7);
PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7));
FUNC_GROUP_DECL(ADC7, M3);
#define M2 184
SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8);
PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8));
FUNC_GROUP_DECL(ADC8, M2);
#define M1 185
SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);
PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));
FUNC_GROUP_DECL(ADC9, M1);
#define N5 186
SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10);
PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10));
FUNC_GROUP_DECL(ADC10, N5);
#define N4 187
SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11);
PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11));
FUNC_GROUP_DECL(ADC11, N4);
#define N3 188
SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12);
PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12));
FUNC_GROUP_DECL(ADC12, N3);
#define N2 189
SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13);
PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13));
FUNC_GROUP_DECL(ADC13, N2);
#define N1 190
SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14);
PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14));
FUNC_GROUP_DECL(ADC14, N1);
#define P5 191
SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15);
PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15));
FUNC_GROUP_DECL(ADC15, P5);
#define C21 192
SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI);
PIN_DECL_1(C21, GPIOY0, SIOS3);
FUNC_GROUP_DECL(SIOS3, C21);
#define F20 193
SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI);
PIN_DECL_1(F20, GPIOY1, SIOS5);
FUNC_GROUP_DECL(SIOS5, F20);
#define G20 194
SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI);
PIN_DECL_1(G20, GPIOY2, SIOPWREQ);
FUNC_GROUP_DECL(SIOPWREQ, G20);
#define K20 195
SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI);
PIN_DECL_1(K20, GPIOY3, SIOONCTRL);
FUNC_GROUP_DECL(SIOONCTRL, K20);
FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20);
#define R22 200
#define R22_DESC SIG_DESC_SET(SCUA4, 16)
SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB0, VPO,
SIG_EXPR_PTR(VPOB0, VPO12),
SIG_EXPR_PTR(VPOB0, VPO24),
SIG_EXPR_PTR(VPOB0, VPOOFF1));
SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO);
PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0);
#define P18 201
#define P18_DESC SIG_DESC_SET(SCUA4, 17)
SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB1, VPO,
SIG_EXPR_PTR(VPOB1, VPO12),
SIG_EXPR_PTR(VPOB1, VPO24),
SIG_EXPR_PTR(VPOB1, VPOOFF1));
SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO);
PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1);
#define P19 202
#define P19_DESC SIG_DESC_SET(SCUA4, 18)
SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB2, VPO,
SIG_EXPR_PTR(VPOB2, VPO12),
SIG_EXPR_PTR(VPOB2, VPO24),
SIG_EXPR_PTR(VPOB2, VPOOFF1));
SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO);
PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2);
#define P20 203
#define P20_DESC SIG_DESC_SET(SCUA4, 19)
SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB3, VPO,
SIG_EXPR_PTR(VPOB3, VPO12),
SIG_EXPR_PTR(VPOB3, VPO24),
SIG_EXPR_PTR(VPOB3, VPOOFF1));
SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO);
PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3);
#define P21 204
#define P21_DESC SIG_DESC_SET(SCUA4, 20)
SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB4, VPO,
SIG_EXPR_PTR(VPOB4, VPO12),
SIG_EXPR_PTR(VPOB4, VPO24),
SIG_EXPR_PTR(VPOB4, VPOOFF1));
SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO);
PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4);
#define P22 205
#define P22_DESC SIG_DESC_SET(SCUA4, 21)
SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB5, VPO,
SIG_EXPR_PTR(VPOB5, VPO12),
SIG_EXPR_PTR(VPOB5, VPO24),
SIG_EXPR_PTR(VPOB5, VPOOFF1));
SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO);
PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5);
#define M19 206
#define M19_DESC SIG_DESC_SET(SCUA4, 22)
SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB6, VPO,
SIG_EXPR_PTR(VPOB6, VPO12),
SIG_EXPR_PTR(VPOB6, VPO24),
SIG_EXPR_PTR(VPOB6, VPOOFF1));
SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO);
PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6);
#define M20 207
#define M20_DESC SIG_DESC_SET(SCUA4, 23)
SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOB7, VPO,
SIG_EXPR_PTR(VPOB7, VPO12),
SIG_EXPR_PTR(VPOB7, VPO24),
SIG_EXPR_PTR(VPOB7, VPOOFF1));
SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO);
PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7);
#define M21 208
#define M21_DESC SIG_DESC_SET(SCUA4, 24)
SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOG0, VPO,
SIG_EXPR_PTR(VPOG0, VPO12),
SIG_EXPR_PTR(VPOG0, VPO24),
SIG_EXPR_PTR(VPOG0, VPOOFF1));
SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO);
PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0);
#define M22 209
#define M22_DESC SIG_DESC_SET(SCUA4, 25)
SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOG1, VPO,
SIG_EXPR_PTR(VPOG1, VPO12),
SIG_EXPR_PTR(VPOG1, VPO24),
SIG_EXPR_PTR(VPOG1, VPOOFF1));
SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO);
PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1);
#define L18 210
#define L18_DESC SIG_DESC_SET(SCUA4, 26)
SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOG2, VPO,
SIG_EXPR_PTR(VPOG2, VPO12),
SIG_EXPR_PTR(VPOG2, VPO24),
SIG_EXPR_PTR(VPOG2, VPOOFF1));
SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO);
PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2);
#define L19 211
#define L19_DESC SIG_DESC_SET(SCUA4, 27)
SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC);
SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC);
SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL(VPOG3, VPO,
SIG_EXPR_PTR(VPOG3, VPO12),
SIG_EXPR_PTR(VPOG3, VPO24),
SIG_EXPR_PTR(VPOG3, VPOOFF1));
SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO);
PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3);
#define L20 212
#define L20_DESC SIG_DESC_SET(SCUA4, 28)
SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1);
PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4);
#define L21 213
#define L21_DESC SIG_DESC_SET(SCUA4, 29)
SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1);
PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5);
#define T18 214
#define T18_DESC SIG_DESC_SET(SCUA4, 30)
SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1);
PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6);
#define N18 215
#define N18_DESC SIG_DESC_SET(SCUA4, 31)
SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1);
PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7);
#define N19 216
#define N19_DESC SIG_DESC_SET(SCUA8, 0)
SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1);
PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0);
#define M18 217
#define M18_DESC SIG_DESC_SET(SCUA8, 1)
SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1);
PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1);
#define N22 218
#define N22_DESC SIG_DESC_SET(SCUA8, 2)
SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1);
PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2);
#define N20 219
#define N20_DESC SIG_DESC_SET(SCUA8, 3)
SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12);
SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12);
SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16);
SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC);
SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);
SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1);
PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3);
FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18,
L19, L20, L21, T18, N18, N19, M18, N22, N20);
FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18,
N18, N19, M18, N22, N20);
FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22,
N20);
FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
P20, P21, P22, M19, M20, M21, M22, L18, L19);
#define USB11H2_DESC SIG_DESC_SET(SCU90, 3)
#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0)
#define K4 220
SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC);
PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2),
SIG_EXPR_LIST_PTR(K4, USB11DP1));
#define K3 221
SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC);
PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1),
SIG_EXPR_LIST_PTR(K3, USB11DDN1));
FUNC_GROUP_DECL(USB11H2, K4, K3);
FUNC_GROUP_DECL(USB11D1, K4, K3);
#define USB2H1_DESC SIG_DESC_SET(SCU90, 29)
#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0)
#define AB21 222
SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC);
PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1),
SIG_EXPR_LIST_PTR(AB21, USB2DDP1));
#define AB20 223
SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC);
PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1),
SIG_EXPR_LIST_PTR(AB20, USB2DDN1));
FUNC_GROUP_DECL(USB2H1, AB21, AB20);
FUNC_GROUP_DECL(USB2D1, AB21, AB20);
/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
* pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
*/
#define ASPEED_G4_NR_PINS 224
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(A1),
ASPEED_PINCTRL_PIN(A10),
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
ASPEED_PINCTRL_PIN(A16),
ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
ASPEED_PINCTRL_PIN(A9),
ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA2),
ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
ASPEED_PINCTRL_PIN(AA4),
ASPEED_PINCTRL_PIN(AA5),
ASPEED_PINCTRL_PIN(AA6),
ASPEED_PINCTRL_PIN(AA7),
ASPEED_PINCTRL_PIN(AB1),
ASPEED_PINCTRL_PIN(AB2),
ASPEED_PINCTRL_PIN(AB3),
ASPEED_PINCTRL_PIN(AB4),
ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(AB20),
ASPEED_PINCTRL_PIN(AB21),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
ASPEED_PINCTRL_PIN(B17),
ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B7),
ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C10),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C17),
ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
ASPEED_PINCTRL_PIN(C21),
ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(C6),
ASPEED_PINCTRL_PIN(C7),
ASPEED_PINCTRL_PIN(C8),
ASPEED_PINCTRL_PIN(C9),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D10),
ASPEED_PINCTRL_PIN(D11),
ASPEED_PINCTRL_PIN(D12),
ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D3),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(D8),
ASPEED_PINCTRL_PIN(D9),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E11),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
ASPEED_PINCTRL_PIN(E14),
ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E16),
ASPEED_PINCTRL_PIN(E18),
ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E5),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
ASPEED_PINCTRL_PIN(E8),
ASPEED_PINCTRL_PIN(E9),
ASPEED_PINCTRL_PIN(F18),
ASPEED_PINCTRL_PIN(F20),
ASPEED_PINCTRL_PIN(F3),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
ASPEED_PINCTRL_PIN(G18),
ASPEED_PINCTRL_PIN(G19),
ASPEED_PINCTRL_PIN(G20),
ASPEED_PINCTRL_PIN(G5),
ASPEED_PINCTRL_PIN(H1),
ASPEED_PINCTRL_PIN(H18),
ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H2),
ASPEED_PINCTRL_PIN(H20),
ASPEED_PINCTRL_PIN(H3),
ASPEED_PINCTRL_PIN(H4),
ASPEED_PINCTRL_PIN(J20),
ASPEED_PINCTRL_PIN(J21),
ASPEED_PINCTRL_PIN(J3),
ASPEED_PINCTRL_PIN(J4),
ASPEED_PINCTRL_PIN(J5),
ASPEED_PINCTRL_PIN(K18),
ASPEED_PINCTRL_PIN(K20),
ASPEED_PINCTRL_PIN(K3),
ASPEED_PINCTRL_PIN(K4),
ASPEED_PINCTRL_PIN(K5),
ASPEED_PINCTRL_PIN(L1),
ASPEED_PINCTRL_PIN(L18),
ASPEED_PINCTRL_PIN(L19),
ASPEED_PINCTRL_PIN(L2),
ASPEED_PINCTRL_PIN(L20),
ASPEED_PINCTRL_PIN(L21),
ASPEED_PINCTRL_PIN(L22),
ASPEED_PINCTRL_PIN(L3),
ASPEED_PINCTRL_PIN(L4),
ASPEED_PINCTRL_PIN(L5),
ASPEED_PINCTRL_PIN(M1),
ASPEED_PINCTRL_PIN(M18),
ASPEED_PINCTRL_PIN(M19),
ASPEED_PINCTRL_PIN(M2),
ASPEED_PINCTRL_PIN(M20),
ASPEED_PINCTRL_PIN(M21),
ASPEED_PINCTRL_PIN(M22),
ASPEED_PINCTRL_PIN(M3),
ASPEED_PINCTRL_PIN(M4),
ASPEED_PINCTRL_PIN(M5),
ASPEED_PINCTRL_PIN(N1),
ASPEED_PINCTRL_PIN(N18),
ASPEED_PINCTRL_PIN(N19),
ASPEED_PINCTRL_PIN(N2),
ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
ASPEED_PINCTRL_PIN(N22),
ASPEED_PINCTRL_PIN(N3),
ASPEED_PINCTRL_PIN(N4),
ASPEED_PINCTRL_PIN(N5),
ASPEED_PINCTRL_PIN(P18),
ASPEED_PINCTRL_PIN(P19),
ASPEED_PINCTRL_PIN(P20),
ASPEED_PINCTRL_PIN(P21),
ASPEED_PINCTRL_PIN(P22),
ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R18),
ASPEED_PINCTRL_PIN(R22),
ASPEED_PINCTRL_PIN(T1),
ASPEED_PINCTRL_PIN(T18),
ASPEED_PINCTRL_PIN(T19),
ASPEED_PINCTRL_PIN(T2),
ASPEED_PINCTRL_PIN(T4),
ASPEED_PINCTRL_PIN(T5),
ASPEED_PINCTRL_PIN(U1),
ASPEED_PINCTRL_PIN(U18),
ASPEED_PINCTRL_PIN(U19),
ASPEED_PINCTRL_PIN(U2),
ASPEED_PINCTRL_PIN(U20),
ASPEED_PINCTRL_PIN(U21),
ASPEED_PINCTRL_PIN(U3),
ASPEED_PINCTRL_PIN(U4),
ASPEED_PINCTRL_PIN(U5),
ASPEED_PINCTRL_PIN(V1),
ASPEED_PINCTRL_PIN(V2),
ASPEED_PINCTRL_PIN(V20),
ASPEED_PINCTRL_PIN(V21),
ASPEED_PINCTRL_PIN(V22),
ASPEED_PINCTRL_PIN(V3),
ASPEED_PINCTRL_PIN(V4),
ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
ASPEED_PINCTRL_PIN(V7),
ASPEED_PINCTRL_PIN(W1),
ASPEED_PINCTRL_PIN(W2),
ASPEED_PINCTRL_PIN(W21),
ASPEED_PINCTRL_PIN(W22),
ASPEED_PINCTRL_PIN(W3),
ASPEED_PINCTRL_PIN(W4),
ASPEED_PINCTRL_PIN(W5),
ASPEED_PINCTRL_PIN(W6),
ASPEED_PINCTRL_PIN(W7),
ASPEED_PINCTRL_PIN(Y1),
ASPEED_PINCTRL_PIN(Y2),
ASPEED_PINCTRL_PIN(Y21),
ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
ASPEED_PINCTRL_PIN(Y6),
ASPEED_PINCTRL_PIN(Y7),
};
static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(ACPI),
ASPEED_PINCTRL_GROUP(ADC0),
ASPEED_PINCTRL_GROUP(ADC1),
ASPEED_PINCTRL_GROUP(ADC10),
ASPEED_PINCTRL_GROUP(ADC11),
ASPEED_PINCTRL_GROUP(ADC12),
ASPEED_PINCTRL_GROUP(ADC13),
ASPEED_PINCTRL_GROUP(ADC14),
ASPEED_PINCTRL_GROUP(ADC15),
ASPEED_PINCTRL_GROUP(ADC2),
ASPEED_PINCTRL_GROUP(ADC3),
ASPEED_PINCTRL_GROUP(ADC4),
ASPEED_PINCTRL_GROUP(ADC5),
ASPEED_PINCTRL_GROUP(ADC6),
ASPEED_PINCTRL_GROUP(ADC7),
ASPEED_PINCTRL_GROUP(ADC8),
ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(DDCCLK),
ASPEED_PINCTRL_GROUP(DDCDAT),
ASPEED_PINCTRL_GROUP(EXTRST),
ASPEED_PINCTRL_GROUP(FLACK),
ASPEED_PINCTRL_GROUP(FLBUSY),
ASPEED_PINCTRL_GROUP(FLWP),
ASPEED_PINCTRL_GROUP(GPID),
ASPEED_PINCTRL_GROUP(GPID0),
ASPEED_PINCTRL_GROUP(GPID2),
ASPEED_PINCTRL_GROUP(GPID4),
ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
ASPEED_PINCTRL_GROUP(GPIE2),
ASPEED_PINCTRL_GROUP(GPIE4),
ASPEED_PINCTRL_GROUP(GPIE6),
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
ASPEED_PINCTRL_GROUP(I2C6),
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPME),
ASPEED_PINCTRL_GROUP(LPCRST),
ASPEED_PINCTRL_GROUP(LPCSMI),
ASPEED_PINCTRL_GROUP(MAC1LINK),
ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
ASPEED_PINCTRL_GROUP(NCTS1),
ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
ASPEED_PINCTRL_GROUP(NDTR4),
ASPEED_PINCTRL_GROUP(NDTS4),
ASPEED_PINCTRL_GROUP(NRI1),
ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
ASPEED_PINCTRL_GROUP(PWM3),
ASPEED_PINCTRL_GROUP(PWM4),
ASPEED_PINCTRL_GROUP(PWM5),
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(RGMII1),
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(ROM16),
ASPEED_PINCTRL_GROUP(ROM8),
ASPEED_PINCTRL_GROUP(ROMCS1),
ASPEED_PINCTRL_GROUP(ROMCS2),
ASPEED_PINCTRL_GROUP(ROMCS3),
ASPEED_PINCTRL_GROUP(ROMCS4),
ASPEED_PINCTRL_GROUP(RXD1),
ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
ASPEED_PINCTRL_GROUP(SALT1),
ASPEED_PINCTRL_GROUP(SALT2),
ASPEED_PINCTRL_GROUP(SALT3),
ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(SGPMCK),
ASPEED_PINCTRL_GROUP(SGPMI),
ASPEED_PINCTRL_GROUP(SGPMLD),
ASPEED_PINCTRL_GROUP(SGPMO),
ASPEED_PINCTRL_GROUP(SGPSCK),
ASPEED_PINCTRL_GROUP(SGPSI0),
ASPEED_PINCTRL_GROUP(SGPSI1),
ASPEED_PINCTRL_GROUP(SGPSLD),
ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
ASPEED_PINCTRL_GROUP(SIOPWREQ),
ASPEED_PINCTRL_GROUP(SIOPWRGD),
ASPEED_PINCTRL_GROUP(SIOS3),
ASPEED_PINCTRL_GROUP(SIOS5),
ASPEED_PINCTRL_GROUP(SIOSCI),
ASPEED_PINCTRL_GROUP(SPI1),
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
ASPEED_PINCTRL_GROUP(SPICS1),
ASPEED_PINCTRL_GROUP(TIMER3),
ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
ASPEED_PINCTRL_GROUP(TXD1),
ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11D1),
ASPEED_PINCTRL_GROUP(USB11H2),
ASPEED_PINCTRL_GROUP(USB2D1),
ASPEED_PINCTRL_GROUP(USB2H1),
ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(VPI18),
ASPEED_PINCTRL_GROUP(VPI24),
ASPEED_PINCTRL_GROUP(VPI30),
ASPEED_PINCTRL_GROUP(VPO12),
ASPEED_PINCTRL_GROUP(VPO24),
ASPEED_PINCTRL_GROUP(WDTRST1),
ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(ACPI),
ASPEED_PINCTRL_FUNC(ADC0),
ASPEED_PINCTRL_FUNC(ADC1),
ASPEED_PINCTRL_FUNC(ADC10),
ASPEED_PINCTRL_FUNC(ADC11),
ASPEED_PINCTRL_FUNC(ADC12),
ASPEED_PINCTRL_FUNC(ADC13),
ASPEED_PINCTRL_FUNC(ADC14),
ASPEED_PINCTRL_FUNC(ADC15),
ASPEED_PINCTRL_FUNC(ADC2),
ASPEED_PINCTRL_FUNC(ADC3),
ASPEED_PINCTRL_FUNC(ADC4),
ASPEED_PINCTRL_FUNC(ADC5),
ASPEED_PINCTRL_FUNC(ADC6),
ASPEED_PINCTRL_FUNC(ADC7),
ASPEED_PINCTRL_FUNC(ADC8),
ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(DDCCLK),
ASPEED_PINCTRL_FUNC(DDCDAT),
ASPEED_PINCTRL_FUNC(EXTRST),
ASPEED_PINCTRL_FUNC(FLACK),
ASPEED_PINCTRL_FUNC(FLBUSY),
ASPEED_PINCTRL_FUNC(FLWP),
ASPEED_PINCTRL_FUNC(GPID),
ASPEED_PINCTRL_FUNC(GPID0),
ASPEED_PINCTRL_FUNC(GPID2),
ASPEED_PINCTRL_FUNC(GPID4),
ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
ASPEED_PINCTRL_FUNC(GPIE2),
ASPEED_PINCTRL_FUNC(GPIE4),
ASPEED_PINCTRL_FUNC(GPIE6),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
ASPEED_PINCTRL_FUNC(I2C6),
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPME),
ASPEED_PINCTRL_FUNC(LPCRST),
ASPEED_PINCTRL_FUNC(LPCSMI),
ASPEED_PINCTRL_FUNC(MAC1LINK),
ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
ASPEED_PINCTRL_FUNC(NCTS1),
ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
ASPEED_PINCTRL_FUNC(NDTR4),
ASPEED_PINCTRL_FUNC(NDTS4),
ASPEED_PINCTRL_FUNC(NRI1),
ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
ASPEED_PINCTRL_FUNC(PWM3),
ASPEED_PINCTRL_FUNC(PWM4),
ASPEED_PINCTRL_FUNC(PWM5),
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(RGMII1),
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(ROM16),
ASPEED_PINCTRL_FUNC(ROM8),
ASPEED_PINCTRL_FUNC(ROMCS1),
ASPEED_PINCTRL_FUNC(ROMCS2),
ASPEED_PINCTRL_FUNC(ROMCS3),
ASPEED_PINCTRL_FUNC(ROMCS4),
ASPEED_PINCTRL_FUNC(RXD1),
ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
ASPEED_PINCTRL_FUNC(SALT1),
ASPEED_PINCTRL_FUNC(SALT2),
ASPEED_PINCTRL_FUNC(SALT3),
ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SD1),
ASPEED_PINCTRL_FUNC(SD2),
ASPEED_PINCTRL_FUNC(SGPMCK),
ASPEED_PINCTRL_FUNC(SGPMI),
ASPEED_PINCTRL_FUNC(SGPMLD),
ASPEED_PINCTRL_FUNC(SGPMO),
ASPEED_PINCTRL_FUNC(SGPSCK),
ASPEED_PINCTRL_FUNC(SGPSI0),
ASPEED_PINCTRL_FUNC(SGPSI1),
ASPEED_PINCTRL_FUNC(SGPSLD),
ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
ASPEED_PINCTRL_FUNC(SIOPWREQ),
ASPEED_PINCTRL_FUNC(SIOPWRGD),
ASPEED_PINCTRL_FUNC(SIOS3),
ASPEED_PINCTRL_FUNC(SIOS5),
ASPEED_PINCTRL_FUNC(SIOSCI),
ASPEED_PINCTRL_FUNC(SPI1),
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
ASPEED_PINCTRL_FUNC(SPICS1),
ASPEED_PINCTRL_FUNC(TIMER3),
ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
ASPEED_PINCTRL_FUNC(TXD1),
ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(USB11D1),
ASPEED_PINCTRL_FUNC(USB11H2),
ASPEED_PINCTRL_FUNC(USB2D1),
ASPEED_PINCTRL_FUNC(USB2H1),
ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(VPI18),
ASPEED_PINCTRL_FUNC(VPI24),
ASPEED_PINCTRL_FUNC(VPI30),
ASPEED_PINCTRL_FUNC(VPO12),
ASPEED_PINCTRL_FUNC(VPO24),
ASPEED_PINCTRL_FUNC(WDTRST1),
ASPEED_PINCTRL_FUNC(WDTRST2),
};
static const struct aspeed_pin_config aspeed_g4_configs[] = {
/* GPIO banks ranges [A, B], [D, J], [M, R] */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
/* GPIOs T[0-5] (RGMII1 Tx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
/* GPIOs V[2-7] (RGMII2 Rx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
/* ADC pull-downs (SCUA8[19:4]) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
/*
* Debounce settings for GPIOs D and E passthrough mode are in
* SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
* banks D and E is handled by the GPIO driver - GPIO passthrough is
* treated like any other non-GPIO mux function. There is a catch
* however, in that the debounce period is configured in the GPIO
* controller. Due to this tangle between GPIO and pinctrl we don't yet
* fully support pass-through debounce.
*/
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
};
static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
if (!ctx->maps[desc->ip])
return -ENODEV;
/*
* Strap registers are configured in hardware or by early-boot
* firmware. Treat them as read-only despite that we can write
* them. This may mean that certain functions cannot be
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*
* Port D and port E GPIO loopback modes are the only exception
* as those are commonly used with front-panel buttons to allow
* normal operation of the host when the BMC is powered off or
* fails to boot. Once the BMC has booted, the loopback mode
* must be disabled for the BMC to control host power-on and
* reset.
*/
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
!(desc->mask & (BIT(21) | BIT(22))))
continue;
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
continue;
ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
desc->mask, val);
if (ret)
return ret;
}
ret = aspeed_sig_expr_eval(ctx, expr, enable);
if (ret < 0)
return ret;
if (!ret)
return -EPERM;
return 0;
}
static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
};
static const struct aspeed_pinmux_ops aspeed_g4_ops = {
.set = aspeed_g4_sig_expr_set,
};
static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
.pins = aspeed_g4_pins,
.npins = ARRAY_SIZE(aspeed_g4_pins),
.pinmux = {
.ops = &aspeed_g4_ops,
.groups = aspeed_g4_groups,
.ngroups = ARRAY_SIZE(aspeed_g4_groups),
.functions = aspeed_g4_functions,
.nfunctions = ARRAY_SIZE(aspeed_g4_functions),
},
.configs = aspeed_g4_configs,
.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
.confmaps = aspeed_g4_pin_config_map,
.nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
};
static const struct pinmux_ops aspeed_g4_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
.set_mux = aspeed_pinmux_set_mux,
.gpio_request_enable = aspeed_gpio_request_enable,
.strict = true,
};
static const struct pinctrl_ops aspeed_g4_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static const struct pinconf_ops aspeed_g4_conf_ops = {
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,
.pin_config_group_get = aspeed_pin_config_group_get,
.pin_config_group_set = aspeed_pin_config_group_set,
};
static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
.name = "aspeed-g4-pinctrl",
.pins = aspeed_g4_pins,
.npins = ARRAY_SIZE(aspeed_g4_pins),
.pctlops = &aspeed_g4_pinctrl_ops,
.pmxops = &aspeed_g4_pinmux_ops,
.confops = &aspeed_g4_conf_ops,
};
static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
{
int i;
for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++)
aspeed_g4_pins[i].number = i;
return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc,
&aspeed_g4_pinctrl_data);
}
static const struct of_device_id aspeed_g4_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2400-pinctrl", },
/*
* The aspeed,g4-pinctrl compatible has been removed the from the
* bindings, but keep the match in case of old devicetrees.
*/
{ .compatible = "aspeed,g4-pinctrl", },
{ },
};
static struct platform_driver aspeed_g4_pinctrl_driver = {
.probe = aspeed_g4_pinctrl_probe,
.driver = {
.name = "aspeed-g4-pinctrl",
.of_match_table = aspeed_g4_pinctrl_of_match,
},
};
static int aspeed_g4_pinctrl_init(void)
{
return platform_driver_register(&aspeed_g4_pinctrl_driver);
}
arch_initcall(aspeed_g4_pinctrl_init);
|
linux-master
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drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 IBM Corp.
*/
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/string.h>
#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
/* Wrap some of the common macros for clarity */
#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
/*
* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
* references registers by the device/offset mnemonic. The register macros
* below are named the same way to ease transcription and verification (as
* opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
* reference registers beyond those dedicated to pinmux, such as the system
* reset control and MAC clock configuration registers. The AST2500 goes a step
* further and references registers in the graphics IP block.
*/
#define SCU2C 0x2C /* Misc. Control Register */
#define SCU3C 0x3C /* System Reset Control/Status Register */
#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
#define SCU80 0x80 /* Multi-function Pin Control #1 */
#define SCU84 0x84 /* Multi-function Pin Control #2 */
#define SCU88 0x88 /* Multi-function Pin Control #3 */
#define SCU8C 0x8C /* Multi-function Pin Control #4 */
#define SCU90 0x90 /* Multi-function Pin Control #5 */
#define SCU94 0x94 /* Multi-function Pin Control #6 */
#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
#define SCUAC 0xAC /* Multi-function Pin Control #10 */
#define HW_STRAP2 0xD0 /* Strapping */
#define ASPEED_G5_NR_PINS 236
#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
/* LHCR0 is offset from the end of the H8S/2168-compatible registers */
#define LHCR0 0xa0
#define GFX064 0x64
#define B14 0
SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
#define D14 1
SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
#define D13 2
SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3);
FUNC_GROUP_DECL(SPI1CS1, D13);
FUNC_GROUP_DECL(TIMER3, D13);
#define E13 3
SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
#define C14 4
SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5);
FUNC_GROUP_DECL(TIMER5, C14);
#define A13 5
SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6);
FUNC_GROUP_DECL(TIMER6, A13);
FUNC_GROUP_DECL(I2C9, C14, A13);
#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
#define C13 6
SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7);
FUNC_GROUP_DECL(TIMER7, C13);
#define B13 7
SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1);
SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8);
FUNC_GROUP_DECL(TIMER8, B13);
FUNC_GROUP_DECL(MDIO2, C13, B13);
#define K19 8
GPIO_PIN_DECL(K19, GPIOB0);
#define L19 9
GPIO_PIN_DECL(L19, GPIOB1);
#define L18 10
GPIO_PIN_DECL(L18, GPIOB2);
#define K18 11
GPIO_PIN_DECL(K18, GPIOB3);
#define J20 12
SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
#define H21 13
#define H21_DESC SIG_DESC_SET(SCU80, 13)
SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC);
PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI);
FUNC_GROUP_DECL(LPCPD, H21);
FUNC_GROUP_DECL(LPCSMI, H21);
#define H22 14
SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
#define H20 15
GPIO_PIN_DECL(H20, GPIOB7);
#define SD1_DESC SIG_DESC_SET(SCU90, 0)
#define C12 16
#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
#define A12 17
SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
FUNC_GROUP_DECL(I2C10, C12, A12);
#define B12 18
#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC);
PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11);
#define D9 19
SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC);
PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11);
FUNC_GROUP_DECL(I2C11, B12, D9);
#define D10 20
#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC);
PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12);
#define E12 21
SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC);
PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12);
FUNC_GROUP_DECL(I2C12, D10, E12);
#define C11 22
#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC);
PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13);
#define B11 23
SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC);
PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13);
FUNC_GROUP_DECL(I2C13, C11, B11);
FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
#define SD2_DESC SIG_DESC_SET(SCU90, 1)
#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
#define F19 24
SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID);
PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN);
#define E21 25
SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID);
PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT);
FUNC_GROUP_DECL(GPID0, F19, E21);
#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
#define F20 26
SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID);
PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN);
#define D20 27
SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID);
PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT);
FUNC_GROUP_DECL(GPID2, F20, D20);
#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
#define D21 28
SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID);
PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN);
#define E20 29
SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID);
PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT);
FUNC_GROUP_DECL(GPID4, D21, E20);
#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
#define G18 30
SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID);
PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN);
#define C21 31
SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID);
PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT);
FUNC_GROUP_DECL(GPID6, G18, C21);
FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define B20 32
SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE);
PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN);
FUNC_GROUP_DECL(NCTS3, B20);
#define C20 33
SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE);
PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT);
FUNC_GROUP_DECL(NDCD3, C20);
FUNC_GROUP_DECL(GPIE0, B20, C20);
#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
#define F18 34
SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE);
PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN);
FUNC_GROUP_DECL(NDSR3, F18);
#define F17 35
SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE);
PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT);
FUNC_GROUP_DECL(NRI3, F17);
FUNC_GROUP_DECL(GPIE2, F18, F17);
#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
#define E18 36
SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE);
PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN);
FUNC_GROUP_DECL(NDTR3, E18);
#define D19 37
SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE);
PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT);
FUNC_GROUP_DECL(NRTS3, D19);
FUNC_GROUP_DECL(GPIE4, E18, D19);
#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
#define A20 38
SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE);
PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN);
FUNC_GROUP_DECL(TXD3, A20);
#define B19 39
SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE);
PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT);
FUNC_GROUP_DECL(RXD3, B19);
FUNC_GROUP_DECL(GPIE6, A20, B19);
#define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
#define J19 40
SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4);
FUNC_GROUP_DECL(NCTS4, J19);
#define J18 41
SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4);
FUNC_GROUP_DECL(NDCD4, J18);
#define B22 42
SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4);
FUNC_GROUP_DECL(NDSR4, B22);
#define B21 43
SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4);
FUNC_GROUP_DECL(NRI4, B21);
#define A21 44
SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4);
FUNC_GROUP_DECL(NDTR4, A21);
#define H19 45
SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4);
FUNC_GROUP_DECL(NRTS4, H19);
#define G17 46
SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4);
FUNC_GROUP_DECL(TXD4, G17);
#define H18 47
SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC);
SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC);
SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS);
SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
PIN_DECL_2(H18, GPIOF7, LHRST, RXD4);
FUNC_GROUP_DECL(RXD4, H18);
FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
#define A19 48
SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
PIN_DECL_1(A19, GPIOG0, SGPS1CK);
#define E19 49
SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
PIN_DECL_1(E19, GPIOG1, SGPS1LD);
#define C19 50
SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
PIN_DECL_1(C19, GPIOG2, SGPS1I0);
#define E16 51
SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
PIN_DECL_1(E16, GPIOG3, SGPS1I1);
FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
#define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
#define E17 52
SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1);
FUNC_GROUP_DECL(SALT1, E17);
#define D16 53
SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2);
FUNC_GROUP_DECL(SALT2, D16);
#define D15 54
SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
FUNC_GROUP_DECL(SALT3, D15);
#define E14 55
SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4);
FUNC_GROUP_DECL(SALT4, E14);
FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
#define UART6_DESC SIG_DESC_SET(SCU90, 7)
#define A18 56
SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC);
PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6);
#define B18 57
SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC);
PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6);
#define D17 58
SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC);
PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6);
#define C17 59
SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC);
PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6);
#define A17 60
SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC);
PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6);
#define B17 61
SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC);
PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6);
#define A16 62
SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC);
PIN_DECL_1(A16, GPIOH6, TXD6);
#define D18 63
SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC);
PIN_DECL_1(D18, GPIOH7, RXD6);
FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
#define SPI1_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
#define SPI1PASSTHRU_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define C18 64
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(C18, GPIOI0, SYSCS);
#define E15 65
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(E15, GPIOI1, SYSCK);
#define B16 66
SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(B16, GPIOI2, SYSMOSI);
#define C16 67
SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
PIN_DECL_1(C16, GPIOI3, SYSMISO);
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
#define B15 68
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
SIG_EXPR_PTR(SPI1CS0, SPI1),
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC);
PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS);
#define C15 69
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
SIG_EXPR_PTR(SPI1CK, SPI1),
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC);
PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK);
#define A14 70
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1,
SIG_EXPR_PTR(SPI1MOSI, SPI1),
SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC);
PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI);
#define A15 71
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MISO, SPI1,
SIG_EXPR_PTR(SPI1MISO, SPI1),
SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
#define R2 72
SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
PIN_DECL_1(R2, GPIOJ0, SGPMCK);
#define L2 73
SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
PIN_DECL_1(L2, GPIOJ1, SGPMLD);
#define N3 74
SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
PIN_DECL_1(N3, GPIOJ2, SGPMO);
#define N4 75
SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
PIN_DECL_1(N4, GPIOJ3, SGPMI);
FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
#define N5 76
SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5);
FUNC_GROUP_DECL(VGAHS, N5);
#define R4 77
SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4);
FUNC_GROUP_DECL(VGAVS, R4);
#define R3 78
SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3);
FUNC_GROUP_DECL(DDCCLK, R3);
#define T3 79
SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3);
FUNC_GROUP_DECL(DDCDAT, T3);
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define L3 80
SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC);
PIN_DECL_1(L3, GPIOK0, SCL5);
#define L4 81
SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC);
PIN_DECL_1(L4, GPIOK1, SDA5);
FUNC_GROUP_DECL(I2C5, L3, L4);
#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
#define L1 82
SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
PIN_DECL_1(L1, GPIOK2, SCL6);
#define N2 83
SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
PIN_DECL_1(N2, GPIOK3, SDA6);
FUNC_GROUP_DECL(I2C6, L1, N2);
#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
#define N1 84
SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
PIN_DECL_1(N1, GPIOK4, SCL7);
#define P1 85
SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC);
PIN_DECL_1(P1, GPIOK5, SDA7);
FUNC_GROUP_DECL(I2C7, N1, P1);
#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
#define P2 86
SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC);
PIN_DECL_1(P2, GPIOK6, SCL8);
#define R1 87
SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC);
PIN_DECL_1(R1, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, P2, R1);
#define T2 88
SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
#define T1 89
#define T1_DESC SIG_DESC_SET(SCU84, 17)
SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
FUNC_GROUP_DECL(NDCD1, T1);
#define U1 90
#define U1_DESC SIG_DESC_SET(SCU84, 18)
SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC);
PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1);
FUNC_GROUP_DECL(NDSR1, U1);
#define U2 91
#define U2_DESC SIG_DESC_SET(SCU84, 19)
SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2);
PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1);
FUNC_GROUP_DECL(NRI1, U2);
#define P4 92
#define P4_DESC SIG_DESC_SET(SCU84, 20)
SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
FUNC_GROUP_DECL(NDTR1, P4);
#define P3 93
#define P3_DESC SIG_DESC_SET(SCU84, 21)
SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2);
PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1);
FUNC_GROUP_DECL(NRTS1, P3);
#define V1 94
#define V1_DESC SIG_DESC_SET(SCU84, 22)
SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2);
PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1);
FUNC_GROUP_DECL(TXD1, V1);
#define W1 95
#define W1_DESC SIG_DESC_SET(SCU84, 23)
SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2);
PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1);
FUNC_GROUP_DECL(RXD1, W1);
#define Y1 96
#define Y1_DESC SIG_DESC_SET(SCU84, 24)
SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
FUNC_GROUP_DECL(NCTS2, Y1);
#define AB2 97
#define AB2_DESC SIG_DESC_SET(SCU84, 25)
SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2);
PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2);
FUNC_GROUP_DECL(NDCD2, AB2);
#define AA1 98
#define AA1_DESC SIG_DESC_SET(SCU84, 26)
SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2);
PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2);
FUNC_GROUP_DECL(NDSR2, AA1);
#define Y2 99
#define Y2_DESC SIG_DESC_SET(SCU84, 27)
SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2);
PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2);
FUNC_GROUP_DECL(NRI2, Y2);
#define AA2 100
#define AA2_DESC SIG_DESC_SET(SCU84, 28)
SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2);
PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2);
FUNC_GROUP_DECL(NDTR2, AA2);
#define P5 101
#define P5_DESC SIG_DESC_SET(SCU84, 29)
SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2);
PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2);
FUNC_GROUP_DECL(NRTS2, P5);
#define R5 102
#define R5_DESC SIG_DESC_SET(SCU84, 30)
SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2);
PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2);
FUNC_GROUP_DECL(TXD2, R5);
#define T5 103
#define T5_DESC SIG_DESC_SET(SCU84, 31)
SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
FUNC_GROUP_DECL(RXD2, T5);
#define V2 104
#define V2_DESC SIG_DESC_SET(SCU88, 0)
SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2);
PIN_DECL_2(V2, GPION0, DASHN0, PWM0);
FUNC_GROUP_DECL(PWM0, V2);
#define W2 105
#define W2_DESC SIG_DESC_SET(SCU88, 1)
SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2);
PIN_DECL_2(W2, GPION1, DASHN1, PWM1);
FUNC_GROUP_DECL(PWM1, W2);
#define V3 106
#define V3_DESC SIG_DESC_SET(SCU88, 2)
SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2);
PIN_DECL_2(V3, GPION2, VPIG2, PWM2);
FUNC_GROUP_DECL(PWM2, V3);
#define U3 107
#define U3_DESC SIG_DESC_SET(SCU88, 3)
SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2);
PIN_DECL_2(U3, GPION3, VPIG3, PWM3);
FUNC_GROUP_DECL(PWM3, U3);
#define W3 108
#define W3_DESC SIG_DESC_SET(SCU88, 4)
SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2);
PIN_DECL_2(W3, GPION4, VPIG4, PWM4);
FUNC_GROUP_DECL(PWM4, W3);
#define AA3 109
#define AA3_DESC SIG_DESC_SET(SCU88, 5)
SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD);
SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2);
PIN_DECL_2(AA3, GPION5, VPIG5, PWM5);
FUNC_GROUP_DECL(PWM5, AA3);
#define Y3 110
#define Y3_DESC SIG_DESC_SET(SCU88, 6)
SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2);
PIN_DECL_2(Y3, GPION6, VPIG6, PWM6);
FUNC_GROUP_DECL(PWM6, Y3);
#define T4 111
#define T4_DESC SIG_DESC_SET(SCU88, 7)
SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
FUNC_GROUP_DECL(PWM7, T4);
#define U5 112
SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
COND2);
PIN_DECL_1(U5, GPIOO0, VPIG8);
#define U4 113
SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
COND2);
PIN_DECL_1(U4, GPIOO1, VPIG9);
#define V5 114
SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC,
SIG_DESC_SET(SCU88, 10));
PIN_DECL_1(V5, GPIOO2, DASHV5);
#define AB4 115
SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
SIG_DESC_SET(SCU88, 11));
PIN_DECL_1(AB4, GPIOO3, DASHAB4);
#define AB3 116
SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 12), COND2);
PIN_DECL_1(AB3, GPIOO4, VPIR2);
#define Y4 117
SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 13), COND2);
PIN_DECL_1(Y4, GPIOO5, VPIR3);
#define AA4 118
SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 14), COND2);
PIN_DECL_1(AA4, GPIOO6, VPIR4);
#define W4 119
SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 15), COND2);
PIN_DECL_1(W4, GPIOO7, VPIR5);
#define V4 120
SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 16), COND2);
PIN_DECL_1(V4, GPIOP0, VPIR6);
#define W5 121
SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 17), COND2);
PIN_DECL_1(W5, GPIOP1, VPIR7);
#define AA5 122
SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 18), COND2);
PIN_DECL_1(AA5, GPIOP2, VPIR8);
#define AB5 123
SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC,
SIG_DESC_SET(SCU88, 19), COND2);
PIN_DECL_1(AB5, GPIOP3, VPIR9);
FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
AB5);
#define Y6 124
SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
SIG_DESC_SET(SCU88, 20));
PIN_DECL_1(Y6, GPIOP4, DASHY6);
#define Y5 125
SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
SIG_DESC_SET(SCU88, 21));
PIN_DECL_1(Y5, GPIOP5, DASHY5);
#define W6 126
SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
SIG_DESC_SET(SCU88, 22));
PIN_DECL_1(W6, GPIOP6, DASHW6);
#define V6 127
SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
SIG_DESC_SET(SCU88, 23));
PIN_DECL_1(V6, GPIOP7, DASHV6);
#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
#define A11 128
SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC);
PIN_DECL_1(A11, GPIOQ0, SCL3);
#define A10 129
SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC);
PIN_DECL_1(A10, GPIOQ1, SDA3);
FUNC_GROUP_DECL(I2C3, A11, A10);
#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
#define A9 130
SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
PIN_DECL_1(A9, GPIOQ2, SCL4);
#define B9 131
SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC);
PIN_DECL_1(B9, GPIOQ3, SDA4);
FUNC_GROUP_DECL(I2C4, A9, B9);
#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
#define N21 132
SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC);
PIN_DECL_1(N21, GPIOQ4, SCL14);
#define N22 133
SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC);
PIN_DECL_1(N22, GPIOQ5, SDA14);
FUNC_GROUP_DECL(I2C14, N21, N22);
#define B10 134
SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
#define N20 135
SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
#define AA19 136
SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
#define T19 137
SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
#define T17 138
SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
#define Y19 139
SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
#define W19 140
SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
#define V19 141
SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
#define D8 142
SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
PIN_DECL_1(D8, GPIOR6, MDC1);
#define E10 143
SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
PIN_DECL_1(E10, GPIOR7, MDIO1);
FUNC_GROUP_DECL(MDIO1, D8, E10);
#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
#define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
#define V20 144
#define V20_DESC SIG_DESC_SET(SCU8C, 0)
SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB2, VPO,
SIG_EXPR_PTR(VPOB2, VPO),
SIG_EXPR_PTR(VPOB2, VPOOFF1),
SIG_EXPR_PTR(VPOB2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC);
PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1);
FUNC_GROUP_DECL(SPI2CS1, V20);
#define U19 145
#define U19_DESC SIG_DESC_SET(SCU8C, 1)
SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB3, VPO,
SIG_EXPR_PTR(VPOB3, VPO),
SIG_EXPR_PTR(VPOB3, VPOOFF1),
SIG_EXPR_PTR(VPOB3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC);
PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT);
FUNC_GROUP_DECL(BMCINT, U19);
#define R18 146
#define R18_DESC SIG_DESC_SET(SCU8C, 2)
SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB4, VPO,
SIG_EXPR_PTR(VPOB4, VPO),
SIG_EXPR_PTR(VPOB4, VPOOFF1),
SIG_EXPR_PTR(VPOB4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO);
SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC);
PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5);
FUNC_GROUP_DECL(SALT5, R18);
#define P18 147
#define P18_DESC SIG_DESC_SET(SCU8C, 3)
SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB5, VPO,
SIG_EXPR_PTR(VPOB5, VPO),
SIG_EXPR_PTR(VPOB5, VPOOFF1),
SIG_EXPR_PTR(VPOB5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO);
SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC);
PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6);
FUNC_GROUP_DECL(SALT6, P18);
#define R19 148
#define R19_DESC SIG_DESC_SET(SCU8C, 4)
SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB6, VPO,
SIG_EXPR_PTR(VPOB6, VPO),
SIG_EXPR_PTR(VPOB6, VPOOFF1),
SIG_EXPR_PTR(VPOB6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO);
PIN_DECL_1(R19, GPIOS4, VPOB6);
#define W20 149
#define W20_DESC SIG_DESC_SET(SCU8C, 5)
SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB7, VPO,
SIG_EXPR_PTR(VPOB7, VPO),
SIG_EXPR_PTR(VPOB7, VPOOFF1),
SIG_EXPR_PTR(VPOB7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO);
PIN_DECL_1(W20, GPIOS5, VPOB7);
#define U20 150
#define U20_DESC SIG_DESC_SET(SCU8C, 6)
SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB8, VPO,
SIG_EXPR_PTR(VPOB8, VPO),
SIG_EXPR_PTR(VPOB8, VPOOFF1),
SIG_EXPR_PTR(VPOB8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO);
PIN_DECL_1(U20, GPIOS6, VPOB8);
#define AA20 151
#define AA20_DESC SIG_DESC_SET(SCU8C, 7)
SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOB9, VPO,
SIG_EXPR_PTR(VPOB9, VPO),
SIG_EXPR_PTR(VPOB9, VPOOFF1),
SIG_EXPR_PTR(VPOB9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO);
PIN_DECL_1(AA20, GPIOS7, VPOB9);
/* RGMII1/RMII1 */
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
#define B5 152
SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC,
SIG_DESC_SET(SCU48, 29));
SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1);
PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO),
SIG_EXPR_LIST_PTR(B5, RGMII1TXCK));
#define E9 153
SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1);
PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN),
SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL));
#define F9 154
SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1);
PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0),
SIG_EXPR_LIST_PTR(F9, RGMII1TXD0));
#define A5 155
SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1);
PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1),
SIG_EXPR_LIST_PTR(A5, RGMII1TXD1));
#define E7 156
SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1);
PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0),
SIG_EXPR_LIST_PTR(E7, RGMII1TXD2));
#define D7 157
SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1);
PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1),
SIG_EXPR_LIST_PTR(D7, RGMII1TXD3));
#define B2 158
SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
SIG_DESC_SET(SCU48, 30));
SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
#define B1 159
SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2);
PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN),
SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL));
#define A2 160
SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
#define B3 161
SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2);
PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1),
SIG_EXPR_LIST_PTR(B3, RGMII2TXD1));
#define D5 162
SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
#define D4 163
SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2);
PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1),
SIG_EXPR_LIST_PTR(D4, RGMII2TXD3));
#define B4 164
SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1);
PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI),
SIG_EXPR_LIST_PTR(B4, RGMII1RXCK));
#define A4 165
SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1);
PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2),
SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL));
#define A3 166
SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
#define D6 167
SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1);
PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1),
SIG_EXPR_LIST_PTR(D6, RGMII1RXD1));
#define C5 168
SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
#define C4 169
SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1);
PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER),
SIG_EXPR_LIST_PTR(C4, RGMII1RXD3));
FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
#define C2 170
SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
#define C1 171
SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
#define C3 172
SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2);
PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0),
SIG_EXPR_LIST_PTR(C3, RGMII2RXD0));
#define D1 173
SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2);
PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1),
SIG_EXPR_LIST_PTR(D1, RGMII2RXD1));
#define D2 174
SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
#define E6 175
SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2);
PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER),
SIG_EXPR_LIST_PTR(E6, RGMII2RXD3));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
#define F4 176
SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);
PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));
FUNC_GROUP_DECL(ADC0, F4);
#define F5 177
SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1);
PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1));
FUNC_GROUP_DECL(ADC1, F5);
#define E2 178
SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2);
PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2));
FUNC_GROUP_DECL(ADC2, E2);
#define E1 179
SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
FUNC_GROUP_DECL(ADC3, E1);
#define F3 180
SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);
PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));
FUNC_GROUP_DECL(ADC4, F3);
#define E3 181
SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
FUNC_GROUP_DECL(ADC5, E3);
#define G5 182
SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6);
PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6));
FUNC_GROUP_DECL(ADC6, G5);
#define G4 183
SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7);
PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7));
FUNC_GROUP_DECL(ADC7, G4);
#define F2 184
SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8);
PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8));
FUNC_GROUP_DECL(ADC8, F2);
#define G3 185
SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9);
PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9));
FUNC_GROUP_DECL(ADC9, G3);
#define G2 186
SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10);
PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10));
FUNC_GROUP_DECL(ADC10, G2);
#define F1 187
SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11);
PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11));
FUNC_GROUP_DECL(ADC11, F1);
#define H5 188
SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12);
PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12));
FUNC_GROUP_DECL(ADC12, H5);
#define G1 189
SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13);
PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13));
FUNC_GROUP_DECL(ADC13, G1);
#define H3 190
SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14);
PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14));
FUNC_GROUP_DECL(ADC14, H3);
#define H4 191
SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15);
PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15));
FUNC_GROUP_DECL(ADC15, H4);
#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
#define R22 192
SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22);
FUNC_GROUP_DECL(SIOS3, R22);
#define R21 193
SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21);
FUNC_GROUP_DECL(SIOS5, R21);
#define P22 194
SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22);
FUNC_GROUP_DECL(SIOPWREQ, P22);
#define P21 195
SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21);
FUNC_GROUP_DECL(SIOONCTRL, P21);
#define M18 196
SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
#define M19 197
SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
#define M20 198
SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
#define P20 199
SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
#define PNOR_DESC SIG_DESC_SET(SCU90, 31)
#define Y20 200
#define Y20_DESC SIG_DESC_SET(SCUA4, 16)
SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG2, VPO,
SIG_EXPR_PTR(VPOG2, VPO),
SIG_EXPR_PTR(VPOG2, VPOOFF1),
SIG_EXPR_PTR(VPOG2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO);
SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC);
SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC);
SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0);
PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI),
SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0));
FUNC_GROUP_DECL(SIOPBI, Y20);
#define AB20 201
#define AB20_DESC SIG_DESC_SET(SCUA4, 17)
SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG3, VPO,
SIG_EXPR_PTR(VPOG3, VPO),
SIG_EXPR_PTR(VPOG3, VPOOFF1),
SIG_EXPR_PTR(VPOG3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO);
SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC);
SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC);
SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1);
PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3),
SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1),
SIG_EXPR_LIST_PTR(AB20, GPIOZ1));
FUNC_GROUP_DECL(SIOPWRGD, AB20);
#define AB21 202
#define AB21_DESC SIG_DESC_SET(SCUA4, 18)
SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG4, VPO,
SIG_EXPR_PTR(VPOG4, VPO),
SIG_EXPR_PTR(VPOG4, VPOOFF1),
SIG_EXPR_PTR(VPOG4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO);
SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC);
SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC);
SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2);
PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4),
SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2),
SIG_EXPR_LIST_PTR(AB21, GPIOZ2));
FUNC_GROUP_DECL(SIOPBO, AB21);
#define AA21 203
#define AA21_DESC SIG_DESC_SET(SCUA4, 19)
SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOG5, VPO,
SIG_EXPR_PTR(VPOG5, VPO),
SIG_EXPR_PTR(VPOG5, VPOOFF1),
SIG_EXPR_PTR(VPOG5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO);
SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC);
SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC);
SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI);
SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3);
PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5),
SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3),
SIG_EXPR_LIST_PTR(AA21, GPIOZ3));
FUNC_GROUP_DECL(SIOSCI, AA21);
FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
/* CRT DVO disabled, configured for single-edge mode */
#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
/* CRT DVO disabled, configured for dual-edge mode */
#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
/* CRT DVO enabled, configured for single-edge mode */
#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
/* CRT DVO enabled, configured for dual-edge mode */
#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
#define U21 204
#define U21_DESC SIG_DESC_SET(SCUA4, 20)
SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG6, VPO,
SIG_EXPR_PTR(VPOG6, VPO),
SIG_EXPR_PTR(VPOG6, VPOOFF1),
SIG_EXPR_PTR(VPOG6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC);
PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4);
#define W22 205
#define W22_DESC SIG_DESC_SET(SCUA4, 21)
SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG7, VPO,
SIG_EXPR_PTR(VPOG7, VPO),
SIG_EXPR_PTR(VPOG7, VPOOFF1),
SIG_EXPR_PTR(VPOG7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO);
SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC);
PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5);
#define V22 206
#define V22_DESC SIG_DESC_SET(SCUA4, 22)
SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG8, VPO,
SIG_EXPR_PTR(VPOG8, VPO),
SIG_EXPR_PTR(VPOG8, VPOOFF1),
SIG_EXPR_PTR(VPOG8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC);
PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6);
#define W21 207
#define W21_DESC SIG_DESC_SET(SCUA4, 23)
SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOG9, VPO,
SIG_EXPR_PTR(VPOG9, VPO),
SIG_EXPR_PTR(VPOG9, VPOOFF1),
SIG_EXPR_PTR(VPOG9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO);
SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC);
PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7);
#define Y21 208
#define Y21_DESC SIG_DESC_SET(SCUA4, 24)
SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR2, VPO,
SIG_EXPR_PTR(VPOR2, VPO),
SIG_EXPR_PTR(VPOR2, VPOOFF1),
SIG_EXPR_PTR(VPOR2, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO);
SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0);
PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7),
SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0));
FUNC_GROUP_DECL(SALT7, Y21);
#define V21 209
#define V21_DESC SIG_DESC_SET(SCUA4, 25)
SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR3, VPO,
SIG_EXPR_PTR(VPOR3, VPO),
SIG_EXPR_PTR(VPOR3, VPOOFF1),
SIG_EXPR_PTR(VPOR3, VPOOFF2));
SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO);
SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1);
PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8),
SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1));
FUNC_GROUP_DECL(SALT8, V21);
#define Y22 210
#define Y22_DESC SIG_DESC_SET(SCUA4, 26)
SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR4, VPO,
SIG_EXPR_PTR(VPOR4, VPO),
SIG_EXPR_PTR(VPOR4, VPOOFF1),
SIG_EXPR_PTR(VPOR4, VPOOFF2));
SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO);
SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2);
PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9),
SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2));
FUNC_GROUP_DECL(SALT9, Y22);
#define AA22 211
#define AA22_DESC SIG_DESC_SET(SCUA4, 27)
SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR5, VPO,
SIG_EXPR_PTR(VPOR5, VPO),
SIG_EXPR_PTR(VPOR5, VPOOFF1),
SIG_EXPR_PTR(VPOR5, VPOOFF2));
SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO);
SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3);
PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5),
SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3),
SIG_EXPR_LIST_PTR(AA22, GPIOAA3));
FUNC_GROUP_DECL(SALT10, AA22);
#define U22 212
#define U22_DESC SIG_DESC_SET(SCUA4, 28)
SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR6, VPO,
SIG_EXPR_PTR(VPOR6, VPO),
SIG_EXPR_PTR(VPOR6, VPOOFF1),
SIG_EXPR_PTR(VPOR6, VPOOFF2));
SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO);
SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4);
PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11),
SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4));
FUNC_GROUP_DECL(SALT11, U22);
#define T20 213
#define T20_DESC SIG_DESC_SET(SCUA4, 29)
SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR7, VPO,
SIG_EXPR_PTR(VPOR7, VPO),
SIG_EXPR_PTR(VPOR7, VPOOFF1),
SIG_EXPR_PTR(VPOR7, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5);
PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12),
SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5));
FUNC_GROUP_DECL(SALT12, T20);
#define N18 214
#define N18_DESC SIG_DESC_SET(SCUA4, 30)
SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR8, VPO,
SIG_EXPR_PTR(VPOR8, VPO),
SIG_EXPR_PTR(VPOR8, VPOOFF1),
SIG_EXPR_PTR(VPOR8, VPOOFF2));
SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO);
SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC);
SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6);
PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13),
SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6));
FUNC_GROUP_DECL(SALT13, N18);
#define P19 215
#define P19_DESC SIG_DESC_SET(SCUA4, 31)
SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
SIG_EXPR_LIST_DECL(VPOR9, VPO,
SIG_EXPR_PTR(VPOR9, VPO),
SIG_EXPR_PTR(VPOR9, VPOOFF1),
SIG_EXPR_PTR(VPOR9, VPOOFF2));
SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO);
SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC);
SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC);
SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7);
PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14),
SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7));
FUNC_GROUP_DECL(SALT14, P19);
#define N19 216
#define N19_DESC SIG_DESC_SET(SCUA8, 0)
SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPODE, VPO,
SIG_EXPR_PTR(VPODE, VPO),
SIG_EXPR_PTR(VPODE, VPOOFF1),
SIG_EXPR_PTR(VPODE, VPOOFF2));
SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO);
SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC);
PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE);
#define T21 217
#define T21_DESC SIG_DESC_SET(SCUA8, 1)
SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOHS, VPO,
SIG_EXPR_PTR(VPOHS, VPO),
SIG_EXPR_PTR(VPOHS, VPOOFF1),
SIG_EXPR_PTR(VPOHS, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC);
PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE);
FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
AA22, U22, T20, N18, P19, N19, T21);
#define T22 218
#define T22_DESC SIG_DESC_SET(SCUA8, 2)
SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOVS, VPO,
SIG_EXPR_PTR(VPOVS, VPO),
SIG_EXPR_PTR(VPOVS, VPOOFF1),
SIG_EXPR_PTR(VPOVS, VPOOFF2));
SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO);
SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC);
PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1);
FUNC_GROUP_DECL(WDTRST1, T22);
#define R20 219
#define R20_DESC SIG_DESC_SET(SCUA8, 3)
SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
SIG_EXPR_LIST_DECL(VPOCLK, VPO,
SIG_EXPR_PTR(VPOCLK, VPO),
SIG_EXPR_PTR(VPOCLK, VPOOFF1),
SIG_EXPR_PTR(VPOCLK, VPOOFF2));
SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO);
SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC);
PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2);
FUNC_GROUP_DECL(WDTRST2, R20);
FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
N18, P19, N19, T21, T22, R20);
#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
#define G21 224
SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0);
FUNC_GROUP_DECL(LAD0, G21);
#define G20 225
SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1);
FUNC_GROUP_DECL(LAD1, G20);
#define D22 226
SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2);
FUNC_GROUP_DECL(LAD2, D22);
#define E22 227
SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3);
FUNC_GROUP_DECL(LAD3, E22);
#define C22 228
SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK);
FUNC_GROUP_DECL(LCLK, C22);
#define F21 229
SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME);
FUNC_GROUP_DECL(LFRAME, F21);
#define F22 230
SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ);
FUNC_GROUP_DECL(LSIRQ, F22);
#define G22 231
SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC);
SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST);
FUNC_GROUP_DECL(LPCRST, G22);
FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
#define A7 232
SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP));
#define A8 233
SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
FUNC_GROUP_DECL(USB2AH, A7, A8);
FUNC_GROUP_DECL(USB2AD, A7, A8);
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
#define B6 234
SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH,
SIG_EXPR_PTR(USB2BHDP1, USB2BH),
SIG_EXPR_PTR(USB2BHDP2, USB2BH));
SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH);
PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP),
SIG_EXPR_LIST_PTR(B6, USB2BHDP));
#define A6 235
SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH,
SIG_EXPR_PTR(USB2BHDN1, USB2BH),
SIG_EXPR_PTR(USB2BHDN2, USB2BH));
SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH);
PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN),
SIG_EXPR_LIST_PTR(A6, USB2BHDN));
FUNC_GROUP_DECL(USB11BHID, B6, A6);
FUNC_GROUP_DECL(USB2BD, B6, A6);
FUNC_GROUP_DECL(USB2BH, B6, A6);
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A10),
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
ASPEED_PINCTRL_PIN(A16),
ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A21),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
ASPEED_PINCTRL_PIN(A9),
ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA19),
ASPEED_PINCTRL_PIN(AA2),
ASPEED_PINCTRL_PIN(AA20),
ASPEED_PINCTRL_PIN(AA21),
ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
ASPEED_PINCTRL_PIN(AA4),
ASPEED_PINCTRL_PIN(AA5),
ASPEED_PINCTRL_PIN(AB2),
ASPEED_PINCTRL_PIN(AB20),
ASPEED_PINCTRL_PIN(AB21),
ASPEED_PINCTRL_PIN(AB3),
ASPEED_PINCTRL_PIN(AB4),
ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
ASPEED_PINCTRL_PIN(B17),
ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20),
ASPEED_PINCTRL_PIN(B21),
ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C17),
ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C19),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
ASPEED_PINCTRL_PIN(C21),
ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D10),
ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D20),
ASPEED_PINCTRL_PIN(D21),
ASPEED_PINCTRL_PIN(D22),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(D8),
ASPEED_PINCTRL_PIN(D9),
ASPEED_PINCTRL_PIN(E1),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
ASPEED_PINCTRL_PIN(E14),
ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E16),
ASPEED_PINCTRL_PIN(E17),
ASPEED_PINCTRL_PIN(E18),
ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E21),
ASPEED_PINCTRL_PIN(E22),
ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
ASPEED_PINCTRL_PIN(E9),
ASPEED_PINCTRL_PIN(F1),
ASPEED_PINCTRL_PIN(F17),
ASPEED_PINCTRL_PIN(F18),
ASPEED_PINCTRL_PIN(F19),
ASPEED_PINCTRL_PIN(F2),
ASPEED_PINCTRL_PIN(F20),
ASPEED_PINCTRL_PIN(F21),
ASPEED_PINCTRL_PIN(F22),
ASPEED_PINCTRL_PIN(F3),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
ASPEED_PINCTRL_PIN(F9),
ASPEED_PINCTRL_PIN(G1),
ASPEED_PINCTRL_PIN(G17),
ASPEED_PINCTRL_PIN(G18),
ASPEED_PINCTRL_PIN(G2),
ASPEED_PINCTRL_PIN(G20),
ASPEED_PINCTRL_PIN(G21),
ASPEED_PINCTRL_PIN(G22),
ASPEED_PINCTRL_PIN(G3),
ASPEED_PINCTRL_PIN(G4),
ASPEED_PINCTRL_PIN(G5),
ASPEED_PINCTRL_PIN(H18),
ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H20),
ASPEED_PINCTRL_PIN(H21),
ASPEED_PINCTRL_PIN(H22),
ASPEED_PINCTRL_PIN(H3),
ASPEED_PINCTRL_PIN(H4),
ASPEED_PINCTRL_PIN(H5),
ASPEED_PINCTRL_PIN(J18),
ASPEED_PINCTRL_PIN(J19),
ASPEED_PINCTRL_PIN(J20),
ASPEED_PINCTRL_PIN(K18),
ASPEED_PINCTRL_PIN(K19),
ASPEED_PINCTRL_PIN(L1),
ASPEED_PINCTRL_PIN(L18),
ASPEED_PINCTRL_PIN(L19),
ASPEED_PINCTRL_PIN(L2),
ASPEED_PINCTRL_PIN(L3),
ASPEED_PINCTRL_PIN(L4),
ASPEED_PINCTRL_PIN(M18),
ASPEED_PINCTRL_PIN(M19),
ASPEED_PINCTRL_PIN(M20),
ASPEED_PINCTRL_PIN(N1),
ASPEED_PINCTRL_PIN(N18),
ASPEED_PINCTRL_PIN(N19),
ASPEED_PINCTRL_PIN(N2),
ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
ASPEED_PINCTRL_PIN(N22),
ASPEED_PINCTRL_PIN(N3),
ASPEED_PINCTRL_PIN(N4),
ASPEED_PINCTRL_PIN(N5),
ASPEED_PINCTRL_PIN(P1),
ASPEED_PINCTRL_PIN(P18),
ASPEED_PINCTRL_PIN(P19),
ASPEED_PINCTRL_PIN(P2),
ASPEED_PINCTRL_PIN(P20),
ASPEED_PINCTRL_PIN(P21),
ASPEED_PINCTRL_PIN(P22),
ASPEED_PINCTRL_PIN(P3),
ASPEED_PINCTRL_PIN(P4),
ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R1),
ASPEED_PINCTRL_PIN(R18),
ASPEED_PINCTRL_PIN(R19),
ASPEED_PINCTRL_PIN(R2),
ASPEED_PINCTRL_PIN(R20),
ASPEED_PINCTRL_PIN(R21),
ASPEED_PINCTRL_PIN(R22),
ASPEED_PINCTRL_PIN(R3),
ASPEED_PINCTRL_PIN(R4),
ASPEED_PINCTRL_PIN(R5),
ASPEED_PINCTRL_PIN(T1),
ASPEED_PINCTRL_PIN(T17),
ASPEED_PINCTRL_PIN(T19),
ASPEED_PINCTRL_PIN(T2),
ASPEED_PINCTRL_PIN(T20),
ASPEED_PINCTRL_PIN(T21),
ASPEED_PINCTRL_PIN(T22),
ASPEED_PINCTRL_PIN(T3),
ASPEED_PINCTRL_PIN(T4),
ASPEED_PINCTRL_PIN(T5),
ASPEED_PINCTRL_PIN(U1),
ASPEED_PINCTRL_PIN(U19),
ASPEED_PINCTRL_PIN(U2),
ASPEED_PINCTRL_PIN(U20),
ASPEED_PINCTRL_PIN(U21),
ASPEED_PINCTRL_PIN(U22),
ASPEED_PINCTRL_PIN(U3),
ASPEED_PINCTRL_PIN(U4),
ASPEED_PINCTRL_PIN(U5),
ASPEED_PINCTRL_PIN(V1),
ASPEED_PINCTRL_PIN(V19),
ASPEED_PINCTRL_PIN(V2),
ASPEED_PINCTRL_PIN(V20),
ASPEED_PINCTRL_PIN(V21),
ASPEED_PINCTRL_PIN(V22),
ASPEED_PINCTRL_PIN(V3),
ASPEED_PINCTRL_PIN(V4),
ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
ASPEED_PINCTRL_PIN(W1),
ASPEED_PINCTRL_PIN(W19),
ASPEED_PINCTRL_PIN(W2),
ASPEED_PINCTRL_PIN(W20),
ASPEED_PINCTRL_PIN(W21),
ASPEED_PINCTRL_PIN(W22),
ASPEED_PINCTRL_PIN(W3),
ASPEED_PINCTRL_PIN(W4),
ASPEED_PINCTRL_PIN(W5),
ASPEED_PINCTRL_PIN(W6),
ASPEED_PINCTRL_PIN(Y1),
ASPEED_PINCTRL_PIN(Y19),
ASPEED_PINCTRL_PIN(Y2),
ASPEED_PINCTRL_PIN(Y20),
ASPEED_PINCTRL_PIN(Y21),
ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
ASPEED_PINCTRL_PIN(Y6),
};
static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(ACPI),
ASPEED_PINCTRL_GROUP(ADC0),
ASPEED_PINCTRL_GROUP(ADC1),
ASPEED_PINCTRL_GROUP(ADC10),
ASPEED_PINCTRL_GROUP(ADC11),
ASPEED_PINCTRL_GROUP(ADC12),
ASPEED_PINCTRL_GROUP(ADC13),
ASPEED_PINCTRL_GROUP(ADC14),
ASPEED_PINCTRL_GROUP(ADC15),
ASPEED_PINCTRL_GROUP(ADC2),
ASPEED_PINCTRL_GROUP(ADC3),
ASPEED_PINCTRL_GROUP(ADC4),
ASPEED_PINCTRL_GROUP(ADC5),
ASPEED_PINCTRL_GROUP(ADC6),
ASPEED_PINCTRL_GROUP(ADC7),
ASPEED_PINCTRL_GROUP(ADC8),
ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(DDCCLK),
ASPEED_PINCTRL_GROUP(DDCDAT),
ASPEED_PINCTRL_GROUP(ESPI),
ASPEED_PINCTRL_GROUP(FWSPICS1),
ASPEED_PINCTRL_GROUP(FWSPICS2),
ASPEED_PINCTRL_GROUP(GPID0),
ASPEED_PINCTRL_GROUP(GPID2),
ASPEED_PINCTRL_GROUP(GPID4),
ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
ASPEED_PINCTRL_GROUP(GPIE2),
ASPEED_PINCTRL_GROUP(GPIE4),
ASPEED_PINCTRL_GROUP(GPIE6),
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
ASPEED_PINCTRL_GROUP(I2C6),
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
ASPEED_PINCTRL_GROUP(LAD0),
ASPEED_PINCTRL_GROUP(LAD1),
ASPEED_PINCTRL_GROUP(LAD2),
ASPEED_PINCTRL_GROUP(LAD3),
ASPEED_PINCTRL_GROUP(LCLK),
ASPEED_PINCTRL_GROUP(LFRAME),
ASPEED_PINCTRL_GROUP(LPCHC),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPLUS),
ASPEED_PINCTRL_GROUP(LPCPME),
ASPEED_PINCTRL_GROUP(LPCRST),
ASPEED_PINCTRL_GROUP(LPCSMI),
ASPEED_PINCTRL_GROUP(LSIRQ),
ASPEED_PINCTRL_GROUP(MAC1LINK),
ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
ASPEED_PINCTRL_GROUP(NCTS1),
ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
ASPEED_PINCTRL_GROUP(NDTR4),
ASPEED_PINCTRL_GROUP(NRI1),
ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
ASPEED_PINCTRL_GROUP(NRTS4),
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PEWAKE),
ASPEED_PINCTRL_GROUP(PNOR),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
ASPEED_PINCTRL_GROUP(PWM3),
ASPEED_PINCTRL_GROUP(PWM4),
ASPEED_PINCTRL_GROUP(PWM5),
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(RGMII1),
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(RXD1),
ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
ASPEED_PINCTRL_GROUP(SALT1),
ASPEED_PINCTRL_GROUP(SALT10),
ASPEED_PINCTRL_GROUP(SALT11),
ASPEED_PINCTRL_GROUP(SALT12),
ASPEED_PINCTRL_GROUP(SALT13),
ASPEED_PINCTRL_GROUP(SALT14),
ASPEED_PINCTRL_GROUP(SALT2),
ASPEED_PINCTRL_GROUP(SALT3),
ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SALT5),
ASPEED_PINCTRL_GROUP(SALT6),
ASPEED_PINCTRL_GROUP(SALT7),
ASPEED_PINCTRL_GROUP(SALT8),
ASPEED_PINCTRL_GROUP(SALT9),
ASPEED_PINCTRL_GROUP(SCL1),
ASPEED_PINCTRL_GROUP(SCL2),
ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(SDA1),
ASPEED_PINCTRL_GROUP(SDA2),
ASPEED_PINCTRL_GROUP(SGPM),
ASPEED_PINCTRL_GROUP(SGPS1),
ASPEED_PINCTRL_GROUP(SGPS2),
ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
ASPEED_PINCTRL_GROUP(SIOPWREQ),
ASPEED_PINCTRL_GROUP(SIOPWRGD),
ASPEED_PINCTRL_GROUP(SIOS3),
ASPEED_PINCTRL_GROUP(SIOS5),
ASPEED_PINCTRL_GROUP(SIOSCI),
ASPEED_PINCTRL_GROUP(SPI1),
ASPEED_PINCTRL_GROUP(SPI1CS1),
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
ASPEED_PINCTRL_GROUP(SPI2CK),
ASPEED_PINCTRL_GROUP(SPI2CS0),
ASPEED_PINCTRL_GROUP(SPI2CS1),
ASPEED_PINCTRL_GROUP(SPI2MISO),
ASPEED_PINCTRL_GROUP(SPI2MOSI),
ASPEED_PINCTRL_GROUP(TIMER3),
ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
ASPEED_PINCTRL_GROUP(TXD1),
ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11BHID),
ASPEED_PINCTRL_GROUP(USB2AD),
ASPEED_PINCTRL_GROUP(USB2AH),
ASPEED_PINCTRL_GROUP(USB2BD),
ASPEED_PINCTRL_GROUP(USB2BH),
ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOSROM),
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(VPI24),
ASPEED_PINCTRL_GROUP(VPO),
ASPEED_PINCTRL_GROUP(WDTRST1),
ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(ACPI),
ASPEED_PINCTRL_FUNC(ADC0),
ASPEED_PINCTRL_FUNC(ADC1),
ASPEED_PINCTRL_FUNC(ADC10),
ASPEED_PINCTRL_FUNC(ADC11),
ASPEED_PINCTRL_FUNC(ADC12),
ASPEED_PINCTRL_FUNC(ADC13),
ASPEED_PINCTRL_FUNC(ADC14),
ASPEED_PINCTRL_FUNC(ADC15),
ASPEED_PINCTRL_FUNC(ADC2),
ASPEED_PINCTRL_FUNC(ADC3),
ASPEED_PINCTRL_FUNC(ADC4),
ASPEED_PINCTRL_FUNC(ADC5),
ASPEED_PINCTRL_FUNC(ADC6),
ASPEED_PINCTRL_FUNC(ADC7),
ASPEED_PINCTRL_FUNC(ADC8),
ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(DDCCLK),
ASPEED_PINCTRL_FUNC(DDCDAT),
ASPEED_PINCTRL_FUNC(ESPI),
ASPEED_PINCTRL_FUNC(FWSPICS1),
ASPEED_PINCTRL_FUNC(FWSPICS2),
ASPEED_PINCTRL_FUNC(GPID0),
ASPEED_PINCTRL_FUNC(GPID2),
ASPEED_PINCTRL_FUNC(GPID4),
ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
ASPEED_PINCTRL_FUNC(GPIE2),
ASPEED_PINCTRL_FUNC(GPIE4),
ASPEED_PINCTRL_FUNC(GPIE6),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
ASPEED_PINCTRL_FUNC(I2C6),
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
ASPEED_PINCTRL_FUNC(LAD0),
ASPEED_PINCTRL_FUNC(LAD1),
ASPEED_PINCTRL_FUNC(LAD2),
ASPEED_PINCTRL_FUNC(LAD3),
ASPEED_PINCTRL_FUNC(LCLK),
ASPEED_PINCTRL_FUNC(LFRAME),
ASPEED_PINCTRL_FUNC(LPCHC),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPLUS),
ASPEED_PINCTRL_FUNC(LPCPME),
ASPEED_PINCTRL_FUNC(LPCRST),
ASPEED_PINCTRL_FUNC(LPCSMI),
ASPEED_PINCTRL_FUNC(LSIRQ),
ASPEED_PINCTRL_FUNC(MAC1LINK),
ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
ASPEED_PINCTRL_FUNC(NCTS1),
ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
ASPEED_PINCTRL_FUNC(NDTR4),
ASPEED_PINCTRL_FUNC(NRI1),
ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
ASPEED_PINCTRL_FUNC(NRTS4),
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PEWAKE),
ASPEED_PINCTRL_FUNC(PNOR),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
ASPEED_PINCTRL_FUNC(PWM3),
ASPEED_PINCTRL_FUNC(PWM4),
ASPEED_PINCTRL_FUNC(PWM5),
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(RGMII1),
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(RXD1),
ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
ASPEED_PINCTRL_FUNC(SALT1),
ASPEED_PINCTRL_FUNC(SALT10),
ASPEED_PINCTRL_FUNC(SALT11),
ASPEED_PINCTRL_FUNC(SALT12),
ASPEED_PINCTRL_FUNC(SALT13),
ASPEED_PINCTRL_FUNC(SALT14),
ASPEED_PINCTRL_FUNC(SALT2),
ASPEED_PINCTRL_FUNC(SALT3),
ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SALT5),
ASPEED_PINCTRL_FUNC(SALT6),
ASPEED_PINCTRL_FUNC(SALT7),
ASPEED_PINCTRL_FUNC(SALT8),
ASPEED_PINCTRL_FUNC(SALT9),
ASPEED_PINCTRL_FUNC(SCL1),
ASPEED_PINCTRL_FUNC(SCL2),
ASPEED_PINCTRL_FUNC(SD1),
ASPEED_PINCTRL_FUNC(SD2),
ASPEED_PINCTRL_FUNC(SDA1),
ASPEED_PINCTRL_FUNC(SDA2),
ASPEED_PINCTRL_FUNC(SGPM),
ASPEED_PINCTRL_FUNC(SGPS1),
ASPEED_PINCTRL_FUNC(SGPS2),
ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
ASPEED_PINCTRL_FUNC(SIOPWREQ),
ASPEED_PINCTRL_FUNC(SIOPWRGD),
ASPEED_PINCTRL_FUNC(SIOS3),
ASPEED_PINCTRL_FUNC(SIOS5),
ASPEED_PINCTRL_FUNC(SIOSCI),
ASPEED_PINCTRL_FUNC(SPI1),
ASPEED_PINCTRL_FUNC(SPI1CS1),
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
ASPEED_PINCTRL_FUNC(SPI2CK),
ASPEED_PINCTRL_FUNC(SPI2CS0),
ASPEED_PINCTRL_FUNC(SPI2CS1),
ASPEED_PINCTRL_FUNC(SPI2MISO),
ASPEED_PINCTRL_FUNC(SPI2MOSI),
ASPEED_PINCTRL_FUNC(TIMER3),
ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
ASPEED_PINCTRL_FUNC(TXD1),
ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(USB11BHID),
ASPEED_PINCTRL_FUNC(USB2AD),
ASPEED_PINCTRL_FUNC(USB2AH),
ASPEED_PINCTRL_FUNC(USB2BD),
ASPEED_PINCTRL_FUNC(USB2BH),
ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOSROM),
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(VPI24),
ASPEED_PINCTRL_FUNC(VPO),
ASPEED_PINCTRL_FUNC(WDTRST1),
ASPEED_PINCTRL_FUNC(WDTRST2),
};
static struct aspeed_pin_config aspeed_g5_configs[] = {
/* GPIOA, GPIOQ */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
/* GPIOB, GPIOR */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
/* GPIOC, GPIOS*/
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
/* GPIOD, GPIOY */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
/* GPIOE, GPIOZ */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
/* GPIOF, GPIOAA */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
/* GPIOG, GPIOAB */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
/* GPIOH, GPIOAC */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
/* GPIOs [I, P] */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
/* GPIOs T[0-5] (RGMII1 Tx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
/* GPIOs V[2-7] (RGMII2 Rx pins) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
/* ADC pull-downs (SCUA8[19:4]) */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
/*
* Debounce settings for GPIOs D and E passthrough mode are in
* SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
* banks D and E is handled by the GPIO driver - GPIO passthrough is
* treated like any other non-GPIO mux function. There is a catch
* however, in that the debounce period is configured in the GPIO
* controller. Due to this tangle between GPIO and pinctrl we don't yet
* fully support pass-through debounce.
*/
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
};
static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
int ip)
{
if (ip == ASPEED_IP_SCU) {
WARN(!ctx->maps[ip], "Missing SCU syscon!");
return ctx->maps[ip];
}
if (ip >= ASPEED_NR_PINMUX_IPS)
return ERR_PTR(-EINVAL);
if (likely(ctx->maps[ip]))
return ctx->maps[ip];
if (ip == ASPEED_IP_GFX) {
struct device_node *node;
struct regmap *map;
node = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 0);
if (node) {
map = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(map))
return map;
} else
return ERR_PTR(-ENODEV);
ctx->maps[ASPEED_IP_GFX] = map;
dev_dbg(ctx->dev, "Acquired GFX regmap");
return map;
}
if (ip == ASPEED_IP_LPC) {
struct device_node *np;
struct regmap *map;
np = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 1);
if (np) {
if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
!of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
!of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
return ERR_PTR(-ENODEV);
map = syscon_node_to_regmap(np->parent);
of_node_put(np);
if (IS_ERR(map))
return map;
} else
return ERR_PTR(-ENODEV);
ctx->maps[ASPEED_IP_LPC] = map;
dev_dbg(ctx->dev, "Acquired LPC regmap");
return map;
}
return ERR_PTR(-EINVAL);
}
static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enabled)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
struct regmap *map;
map = aspeed_g5_acquire_regmap(ctx, desc->ip);
if (IS_ERR(map)) {
dev_err(ctx->dev,
"Failed to acquire regmap for IP block %d\n",
desc->ip);
return PTR_ERR(map);
}
ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
if (ret <= 0)
return ret;
}
return 1;
}
/**
* aspeed_g5_sig_expr_set() - Configure a pin's signal by applying an
* expression's descriptor state for all descriptors in the expression.
*
* @ctx: The pinmux context
* @expr: The expression associated with the function whose signal is to be
* configured
* @enable: true to enable an function's signal through a pin's signal
* expression, false to disable the function's signal
*
* Return: 0 if the expression is configured as requested and a negative error
* code otherwise
*/
static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
struct regmap *map;
map = aspeed_g5_acquire_regmap(ctx, desc->ip);
if (IS_ERR(map)) {
dev_err(ctx->dev,
"Failed to acquire regmap for IP block %d\n",
desc->ip);
return PTR_ERR(map);
}
/*
* Strap registers are configured in hardware or by early-boot
* firmware. Treat them as read-only despite that we can write
* them. This may mean that certain functions cannot be
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*
* Port D and port E GPIO loopback modes are the only exception
* as those are commonly used with front-panel buttons to allow
* normal operation of the host when the BMC is powered off or
* fails to boot. Once the BMC has booted, the loopback mode
* must be disabled for the BMC to control host power-on and
* reset.
*/
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
!(desc->mask & (BIT(21) | BIT(22))))
continue;
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
continue;
/* On AST2500, Set bits in SCU70 are cleared from SCU7C */
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
u32 value = ~val & desc->mask;
if (value) {
ret = regmap_write(ctx->maps[desc->ip],
HW_REVISION_ID, value);
if (ret < 0)
return ret;
}
}
ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
desc->mask, val);
if (ret)
return ret;
}
ret = aspeed_sig_expr_eval(ctx, expr, enable);
if (ret < 0)
return ret;
if (!ret)
return -EPERM;
return 0;
}
static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
};
static const struct aspeed_pinmux_ops aspeed_g5_ops = {
.eval = aspeed_g5_sig_expr_eval,
.set = aspeed_g5_sig_expr_set,
};
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
.pinmux = {
.ops = &aspeed_g5_ops,
.groups = aspeed_g5_groups,
.ngroups = ARRAY_SIZE(aspeed_g5_groups),
.functions = aspeed_g5_functions,
.nfunctions = ARRAY_SIZE(aspeed_g5_functions),
},
.configs = aspeed_g5_configs,
.nconfigs = ARRAY_SIZE(aspeed_g5_configs),
.confmaps = aspeed_g5_pin_config_map,
.nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
};
static const struct pinmux_ops aspeed_g5_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
.set_mux = aspeed_pinmux_set_mux,
.gpio_request_enable = aspeed_gpio_request_enable,
.strict = true,
};
static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static const struct pinconf_ops aspeed_g5_conf_ops = {
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,
.pin_config_group_get = aspeed_pin_config_group_get,
.pin_config_group_set = aspeed_pin_config_group_set,
};
static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
.name = "aspeed-g5-pinctrl",
.pins = aspeed_g5_pins,
.npins = ARRAY_SIZE(aspeed_g5_pins),
.pctlops = &aspeed_g5_pinctrl_ops,
.pmxops = &aspeed_g5_pinmux_ops,
.confops = &aspeed_g5_conf_ops,
};
static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
{
int i;
for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
aspeed_g5_pins[i].number = i;
aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
&aspeed_g5_pinctrl_data);
}
static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2500-pinctrl", },
/*
* The aspeed,g5-pinctrl compatible has been removed the from the
* bindings, but keep the match in case of old devicetrees.
*/
{ .compatible = "aspeed,g5-pinctrl", },
{ },
};
static struct platform_driver aspeed_g5_pinctrl_driver = {
.probe = aspeed_g5_pinctrl_probe,
.driver = {
.name = "aspeed-g5-pinctrl",
.of_match_table = aspeed_g5_pinctrl_of_match,
},
};
static int aspeed_g5_pinctrl_init(void)
{
return platform_driver_register(&aspeed_g5_pinctrl_driver);
}
arch_initcall(aspeed_g5_pinctrl_init);
|
linux-master
|
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (C) 2019 IBM Corp. */
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/string.h>
#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
#define SCU400 0x400 /* Multi-function Pin Control #1 */
#define SCU404 0x404 /* Multi-function Pin Control #2 */
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
#define SCU410 0x410 /* Multi-function Pin Control #4 */
#define SCU414 0x414 /* Multi-function Pin Control #5 */
#define SCU418 0x418 /* Multi-function Pin Control #6 */
#define SCU41C 0x41C /* Multi-function Pin Control #7 */
#define SCU430 0x430 /* Multi-function Pin Control #8 */
#define SCU434 0x434 /* Multi-function Pin Control #9 */
#define SCU438 0x438 /* Multi-function Pin Control #10 */
#define SCU440 0x440 /* USB Multi-function Pin Control #12 */
#define SCU450 0x450 /* Multi-function Pin Control #14 */
#define SCU454 0x454 /* Multi-function Pin Control #15 */
#define SCU458 0x458 /* Multi-function Pin Control #16 */
#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
#define SCU4BC 0x4BC /* Multi-function Pin Control #20 */
#define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */
#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
#define SCU500 0x500 /* Hardware Strap 1 */
#define SCU510 0x510 /* Hardware Strap 2 */
#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */
#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
#define SCU690 0x690 /* Multi-function Pin Control #24 */
#define SCU694 0x694 /* Multi-function Pin Control #25 */
#define SCU69C 0x69C /* Multi-function Pin Control #27 */
#define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */
#define SCUC20 0xC20 /* PCIE configuration Setting Control */
#define ASPEED_G6_NR_PINS 256
#define M24 0
SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0));
PIN_DECL_2(M24, GPIOA0, MDC3, SCL11);
#define M25 1
SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1));
SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1));
PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11);
FUNC_GROUP_DECL(MDIO3, M24, M25);
FUNC_GROUP_DECL(I2C11, M24, M25);
#define L26 2
SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2));
SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2));
PIN_DECL_2(L26, GPIOA2, MDC4, SCL12);
#define K24 3
SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3));
SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3));
PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12);
FUNC_GROUP_DECL(MDIO4, L26, K24);
FUNC_GROUP_DECL(I2C12, L26, K24);
#define K26 4
SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4));
SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4));
SIG_EXPR_LIST_DECL_SESG(K26, SGPS2CK, SGPS2, SIG_DESC_SET(SCU690, 4));
SIG_EXPR_LIST_DECL_SESG(K26, SGPM2CLK, SGPM2, SIG_DESC_SET(SCU6D0, 4));
PIN_DECL_4(K26, GPIOA4, MACLINK1, SCL13, SGPS2CK, SGPM2CLK);
FUNC_GROUP_DECL(MACLINK1, K26);
#define L24 5
SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5));
SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5));
SIG_EXPR_LIST_DECL_SESG(L24, SGPS2LD, SGPS2, SIG_DESC_SET(SCU690, 5));
SIG_EXPR_LIST_DECL_SESG(L24, SGPM2LD, SGPM2, SIG_DESC_SET(SCU6D0, 5));
PIN_DECL_4(L24, GPIOA5, MACLINK2, SDA13, SGPS2LD, SGPM2LD);
FUNC_GROUP_DECL(MACLINK2, L24);
FUNC_GROUP_DECL(I2C13, K26, L24);
#define L23 6
SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6));
SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6));
SIG_EXPR_LIST_DECL_SESG(L23, SGPS2O, SGPS2, SIG_DESC_SET(SCU690, 6));
SIG_EXPR_LIST_DECL_SESG(L23, SGPM2O, SGPM2, SIG_DESC_SET(SCU6D0, 6));
PIN_DECL_4(L23, GPIOA6, MACLINK3, SCL14, SGPS2O, SGPM2O);
FUNC_GROUP_DECL(MACLINK3, L23);
#define K25 7
SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7));
SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7));
SIG_EXPR_LIST_DECL_SESG(K25, SGPS2I, SGPS2, SIG_DESC_SET(SCU690, 7));
SIG_EXPR_LIST_DECL_SESG(K25, SGPM2I, SGPM2, SIG_DESC_SET(SCU6D0, 7));
PIN_DECL_4(K25, GPIOA7, MACLINK4, SDA14, SGPS2I, SGPM2I);
FUNC_GROUP_DECL(MACLINK4, K25);
FUNC_GROUP_DECL(I2C14, L23, K25);
FUNC_GROUP_DECL(SGPM2, K26, L24, L23, K25);
FUNC_GROUP_DECL(SGPS2, K26, L24, L23, K25);
#define J26 8
SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8));
SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8));
PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0);
FUNC_GROUP_DECL(SALT1, J26);
#define K23 9
SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9));
PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1);
FUNC_GROUP_DECL(SALT2, K23);
#define H26 10
SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10));
PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2);
FUNC_GROUP_DECL(SALT3, H26);
#define J25 11
SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11));
SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11));
PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3);
FUNC_GROUP_DECL(SALT4, J25);
#define J23 12
SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12));
SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12));
PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK);
#define G26 13
SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13));
SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13));
PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME);
FUNC_GROUP_DECL(MDIO2, J23, G26);
#define H25 14
SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14));
SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14));
PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ);
FUNC_GROUP_DECL(TXD4, H25);
FUNC_GROUP_DECL(LHSIRQ, H25);
#define J24 15
SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15));
SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15));
PIN_DECL_2(J24, GPIOB7, RXD4, LHRST);
FUNC_GROUP_DECL(RXD4, J24);
FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24);
#define H24 16
SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO);
#define J22 17
SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN);
#define H22 18
SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0);
#define H23 19
SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1);
#define G22 20
SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20),
SIG_DESC_SET(SCU510, 0));
PIN_DECL_1(G22, GPIOC4, RGMII3TXD2);
#define F22 21
SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21),
SIG_DESC_SET(SCU510, 0));
PIN_DECL_1(F22, GPIOC5, RGMII3TXD3);
#define G23 22
SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI);
#define G24 23
SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23),
SIG_DESC_SET(SCU510, 0));
PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL);
#define F23 24
SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0);
#define F26 25
SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1);
#define F25 26
SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV);
#define E26 27
SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27),
SIG_DESC_SET(SCU510, 0));
SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27),
SIG_DESC_CLEAR(SCU510, 0));
PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER);
FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25,
E26);
FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
#define F24 28
SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28));
SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO);
FUNC_GROUP_DECL(NCTS3, F24);
#define E23 29
SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29));
SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN);
FUNC_GROUP_DECL(NDCD3, E23);
#define E24 30
SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30));
SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0);
FUNC_GROUP_DECL(NDSR3, E24);
#define E25 31
SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31));
SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1);
FUNC_GROUP_DECL(NRI3, E25);
#define D26 32
SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0));
SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0),
SIG_DESC_SET(SCU510, 1));
PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2);
FUNC_GROUP_DECL(NDTR3, D26);
#define D24 33
SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1));
SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1),
SIG_DESC_SET(SCU510, 1));
PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3);
FUNC_GROUP_DECL(NRTS3, D24);
#define C25 34
SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2));
SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI);
FUNC_GROUP_DECL(NCTS4, C25);
#define C26 35
SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3));
SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3),
SIG_DESC_SET(SCU510, 1));
PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL);
FUNC_GROUP_DECL(NDCD4, C26);
#define C24 36
SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4));
SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0);
FUNC_GROUP_DECL(NDSR4, C24);
#define B26 37
SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5));
SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1);
FUNC_GROUP_DECL(NRI4, B26);
#define B25 38
SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6));
SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV);
FUNC_GROUP_DECL(NDTR4, B25);
#define B24 39
SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7));
SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7),
SIG_DESC_SET(SCU510, 1));
SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7),
SIG_DESC_CLEAR(SCU510, 1));
PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER);
FUNC_GROUP_DECL(NRTS4, B24);
FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25,
B24);
FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
#define D22 40
SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8));
SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8));
PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8);
GROUP_DECL(PWM8G0, D22);
#define E22 41
SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9));
SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9));
PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9);
GROUP_DECL(PWM9G0, E22);
#define D23 42
SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10));
SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10));
PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10);
GROUP_DECL(PWM10G0, D23);
#define C23 43
SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11));
SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11));
PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11);
GROUP_DECL(PWM11G0, C23);
#define C22 44
SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12));
SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12));
PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12);
GROUP_DECL(PWM12G0, C22);
#define A25 45
SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13));
SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13));
PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13);
GROUP_DECL(PWM13G0, A25);
#define A24 46
SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14));
SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14));
PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14);
GROUP_DECL(PWM14G0, A24);
#define A23 47
SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15));
SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15));
PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15);
GROUP_DECL(PWM15G0, A23);
FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23);
#define E21 48
SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16));
SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16));
PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9);
GROUP_DECL(SALT9G0, E21);
#define B22 49
SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17));
SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10,
SIG_DESC_SET(SCU694, 17));
PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10);
GROUP_DECL(SALT10G0, B22);
FUNC_GROUP_DECL(UART6, E21, B22);
#define C21 50
SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18));
SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11,
SIG_DESC_SET(SCU694, 18));
PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11);
GROUP_DECL(SALT11G0, C21);
#define A22 51
SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19));
SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12,
SIG_DESC_SET(SCU694, 19));
PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12);
GROUP_DECL(SALT12G0, A22);
FUNC_GROUP_DECL(UART7, C21, A22);
#define A21 52
SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20));
SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13,
SIG_DESC_SET(SCU694, 20));
PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13);
GROUP_DECL(SALT13G0, A21);
#define E20 53
SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21));
SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14,
SIG_DESC_SET(SCU694, 21));
PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14);
GROUP_DECL(SALT14G0, E20);
FUNC_GROUP_DECL(UART8, A21, E20);
#define D21 54
SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22));
SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15,
SIG_DESC_SET(SCU694, 22));
PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15);
GROUP_DECL(SALT15G0, D21);
#define B21 55
SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23));
SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23),
SIG_DESC_SET(SCU450, 1));
SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16,
SIG_DESC_SET(SCU694, 23));
PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16);
GROUP_DECL(SALT16G0, B21);
FUNC_GROUP_DECL(UART9, D21, B21);
FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21);
#define A18 56
SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24));
PIN_DECL_1(A18, GPIOH0, SGPM1CLK);
#define B18 57
SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25));
PIN_DECL_1(B18, GPIOH1, SGPM1LD);
#define C18 58
SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26));
PIN_DECL_1(C18, GPIOH2, SGPM1O);
#define A17 59
SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27));
PIN_DECL_1(A17, GPIOH3, SGPM1I);
FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17);
#define D18 60
SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28));
SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28));
PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15);
#define B17 61
SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29));
SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29));
PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15);
FUNC_GROUP_DECL(I2C15, D18, B17);
#define C17 62
SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30));
SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30));
PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16);
#define E18 63
SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31));
SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31));
PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16);
FUNC_GROUP_DECL(I2C16, C17, E18);
FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18);
#define D17 64
SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0));
SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0));
PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12);
#define A16 65
SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1));
SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1));
PIN_DECL_2(A16, GPIOI1, MTDI, RXD12);
GROUP_DECL(UART12G0, D17, A16);
#define E17 66
SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2));
SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2));
PIN_DECL_2(E17, GPIOI2, MTCK, TXD13);
#define D16 67
SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3));
SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3));
PIN_DECL_2(D16, GPIOI3, MTMS, RXD13);
GROUP_DECL(UART13G0, E17, D16);
#define C16 68
SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4));
PIN_DECL_1(C16, GPIOI4, MTDO);
FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16);
#define E16 69
SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5));
PIN_DECL_1(E16, GPIOI5, SIOPBO);
FUNC_GROUP_DECL(SIOPBO, E16);
#define B16 70
SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6));
PIN_DECL_1(B16, GPIOI6, SIOPBI);
FUNC_GROUP_DECL(SIOPBI, B16);
#define A15 71
SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7));
SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7));
PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI);
FUNC_GROUP_DECL(BMCINT, A15);
FUNC_GROUP_DECL(SIOSCI, A15);
#define B20 72
SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8));
SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8));
PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1);
#define A20 73
SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9));
SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9));
PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1);
GROUP_DECL(HVI3C3, B20, A20);
FUNC_GROUP_DECL(I2C1, B20, A20);
#define E19 74
SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10));
SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10));
PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2);
#define D20 75
SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11));
SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11));
PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2);
GROUP_DECL(HVI3C4, E19, D20);
FUNC_GROUP_DECL(I2C2, E19, D20);
#define C19 76
SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12));
SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12));
PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3);
#define A19 77
SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13));
SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13));
PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3);
FUNC_GROUP_DECL(I3C5, C19, A19);
FUNC_GROUP_DECL(I2C3, C19, A19);
#define C20 78
SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14));
SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14));
PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4);
#define D19 79
SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15));
SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15));
PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4);
FUNC_GROUP_DECL(I3C6, C20, D19);
FUNC_GROUP_DECL(I2C4, C20, D19);
#define A11 80
SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16));
PIN_DECL_1(A11, GPIOK0, SCL5);
#define C11 81
SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17));
PIN_DECL_1(C11, GPIOK1, SDA5);
FUNC_GROUP_DECL(I2C5, A11, C11);
#define D12 82
SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18));
PIN_DECL_1(D12, GPIOK2, SCL6);
#define E13 83
SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19));
PIN_DECL_1(E13, GPIOK3, SDA6);
FUNC_GROUP_DECL(I2C6, D12, E13);
#define D11 84
SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20));
PIN_DECL_1(D11, GPIOK4, SCL7);
#define E11 85
SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21));
PIN_DECL_1(E11, GPIOK5, SDA7);
FUNC_GROUP_DECL(I2C7, D11, E11);
#define F13 86
SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22));
PIN_DECL_1(F13, GPIOK6, SCL8);
#define E12 87
SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23));
PIN_DECL_1(E12, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, F13, E12);
#define D15 88
SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24));
PIN_DECL_1(D15, GPIOL0, SCL9);
#define A14 89
SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25));
PIN_DECL_1(A14, GPIOL1, SDA9);
FUNC_GROUP_DECL(I2C9, D15, A14);
#define E15 90
SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26));
PIN_DECL_1(E15, GPIOL2, SCL10);
#define A13 91
SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27));
PIN_DECL_1(A13, GPIOL3, SDA10);
FUNC_GROUP_DECL(I2C10, E15, A13);
#define C15 92
SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28));
#define F15 93
SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29));
#define B14 94
SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30));
#define C14 95
SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31));
#define D14 96
SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0));
#define B13 97
SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1));
#define A12 98
SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2));
#define E14 99
SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3));
#define B12 100
SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4));
#define C12 101
SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5));
#define C13 102
SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6));
#define D13 103
SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7));
#define P25 104
SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8));
#define N23 105
SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9));
#define N25 106
SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10));
#define N24 107
SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11));
#define P26 108
SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12));
#define M23 109
SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13));
#define N26 110
SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14));
#define M26 111
SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15));
#define AD26 112
SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16));
#define AD22 113
SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17));
#define AD23 114
SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18));
#define AD24 115
SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19));
#define AD25 116
SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20));
#define AC22 117
SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21));
#define AC24 118
SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22));
#define AC23 119
SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23));
#define AB22 120
SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24));
SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24));
PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0);
GROUP_DECL(PWM8G1, AB22);
FUNC_DECL_2(PWM8, PWM8G0, PWM8G1);
#define W24 121
SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25));
SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25));
PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0);
FUNC_GROUP_DECL(THRU0, AB22, W24);
GROUP_DECL(PWM9G1, W24);
FUNC_DECL_2(PWM9, PWM9G0, PWM9G1);
#define AA23 122
SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26));
SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26));
PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1);
GROUP_DECL(PWM10G1, AA23);
FUNC_DECL_2(PWM10, PWM10G0, PWM10G1);
#define AA24 123
SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27));
SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27));
PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1);
GROUP_DECL(PWM11G1, AA24);
FUNC_DECL_2(PWM11, PWM11G0, PWM11G1);
FUNC_GROUP_DECL(THRU1, AA23, AA24);
#define W23 124
SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28));
SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28));
PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2);
GROUP_DECL(PWM12G1, W23);
FUNC_DECL_2(PWM12, PWM12G0, PWM12G1);
#define AB23 125
SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29));
SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29));
PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2);
GROUP_DECL(PWM13G1, AB23);
FUNC_DECL_2(PWM13, PWM13G0, PWM13G1);
FUNC_GROUP_DECL(THRU2, W23, AB23);
#define AB24 126
SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30));
SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30));
PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3);
GROUP_DECL(PWM14G1, AB24);
FUNC_DECL_2(PWM14, PWM14G0, PWM14G1);
#define Y23 127
SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31));
SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31));
SIG_EXPR_LIST_DECL_SESG(Y23, HEARTBEAT, HEARTBEAT, SIG_DESC_SET(SCU69C, 31));
PIN_DECL_3(Y23, GPIOP7, PWM15, THRUOUT3, HEARTBEAT);
GROUP_DECL(PWM15G1, Y23);
FUNC_DECL_2(PWM15, PWM15G0, PWM15G1);
FUNC_GROUP_DECL(THRU3, AB24, Y23);
FUNC_GROUP_DECL(HEARTBEAT, Y23);
#define AA25 128
SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0));
#define AB25 129
SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1));
#define Y24 130
SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2));
#define AB26 131
SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3));
#define Y26 132
SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4));
#define AC26 133
SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5));
#define Y25 134
SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6));
#define AA26 135
SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7));
#define V25 136
SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8));
#define U24 137
SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9));
#define V24 138
SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10));
#define V26 139
SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11));
#define U25 140
SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12));
#define T23 141
SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13));
#define W26 142
SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14));
#define U26 143
SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15));
#define R23 144
SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16));
PIN_DECL_1(R23, GPIOS0, MDC1);
#define T25 145
SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17));
PIN_DECL_1(T25, GPIOS1, MDIO1);
FUNC_GROUP_DECL(MDIO1, R23, T25);
#define T26 146
SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18));
#define R24 147
SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19));
#define R26 148
SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20));
PIN_DECL_1(R26, GPIOS4, TXD10);
#define P24 149
SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21));
PIN_DECL_1(P24, GPIOS5, RXD10);
FUNC_GROUP_DECL(UART10, R26, P24);
#define P23 150
SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22));
PIN_DECL_1(P23, GPIOS6, TXD11);
#define T24 151
SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23));
PIN_DECL_1(T24, GPIOS7, RXD11);
FUNC_GROUP_DECL(UART11, P23, T24);
#define AD20 152
SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24));
SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0);
PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0));
FUNC_GROUP_DECL(GPIT0, AD20);
FUNC_GROUP_DECL(ADC0, AD20);
#define AC18 153
SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25));
SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1);
PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1));
FUNC_GROUP_DECL(GPIT1, AC18);
FUNC_GROUP_DECL(ADC1, AC18);
#define AE19 154
SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26));
SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2);
PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2));
FUNC_GROUP_DECL(GPIT2, AE19);
FUNC_GROUP_DECL(ADC2, AE19);
#define AD19 155
SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27));
SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3);
PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3));
FUNC_GROUP_DECL(GPIT3, AD19);
FUNC_GROUP_DECL(ADC3, AD19);
#define AC19 156
SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28));
SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4);
PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4));
FUNC_GROUP_DECL(GPIT4, AC19);
FUNC_GROUP_DECL(ADC4, AC19);
#define AB19 157
SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29));
SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5);
PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5));
FUNC_GROUP_DECL(GPIT5, AB19);
FUNC_GROUP_DECL(ADC5, AB19);
#define AB18 158
SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30));
SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6);
PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6));
FUNC_GROUP_DECL(GPIT6, AB18);
FUNC_GROUP_DECL(ADC6, AB18);
#define AE18 159
SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31));
SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7);
PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7));
FUNC_GROUP_DECL(GPIT7, AE18);
FUNC_GROUP_DECL(ADC7, AE18);
#define AB16 160
SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0),
SIG_DESC_CLEAR(SCU694, 16));
SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0),
SIG_DESC_SET(SCU694, 16));
SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8);
PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0),
SIG_EXPR_LIST_PTR(AB16, ADC8));
GROUP_DECL(SALT9G1, AB16);
FUNC_DECL_2(SALT9, SALT9G0, SALT9G1);
FUNC_GROUP_DECL(GPIU0, AB16);
FUNC_GROUP_DECL(ADC8, AB16);
#define AA17 161
SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1),
SIG_DESC_CLEAR(SCU694, 17));
SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1),
SIG_DESC_SET(SCU694, 17));
SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9);
PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1),
SIG_EXPR_LIST_PTR(AA17, ADC9));
GROUP_DECL(SALT10G1, AA17);
FUNC_DECL_2(SALT10, SALT10G0, SALT10G1);
FUNC_GROUP_DECL(GPIU1, AA17);
FUNC_GROUP_DECL(ADC9, AA17);
#define AB17 162
SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2),
SIG_DESC_CLEAR(SCU694, 18));
SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2),
SIG_DESC_SET(SCU694, 18));
SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10);
PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2),
SIG_EXPR_LIST_PTR(AB17, ADC10));
GROUP_DECL(SALT11G1, AB17);
FUNC_DECL_2(SALT11, SALT11G0, SALT11G1);
FUNC_GROUP_DECL(GPIU2, AB17);
FUNC_GROUP_DECL(ADC10, AB17);
#define AE16 163
SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3),
SIG_DESC_CLEAR(SCU694, 19));
SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3),
SIG_DESC_SET(SCU694, 19));
SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11);
PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3),
SIG_EXPR_LIST_PTR(AE16, ADC11));
GROUP_DECL(SALT12G1, AE16);
FUNC_DECL_2(SALT12, SALT12G0, SALT12G1);
FUNC_GROUP_DECL(GPIU3, AE16);
FUNC_GROUP_DECL(ADC11, AE16);
#define AC16 164
SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4),
SIG_DESC_CLEAR(SCU694, 20));
SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4),
SIG_DESC_SET(SCU694, 20));
SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12);
PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4),
SIG_EXPR_LIST_PTR(AC16, ADC12));
GROUP_DECL(SALT13G1, AC16);
FUNC_DECL_2(SALT13, SALT13G0, SALT13G1);
FUNC_GROUP_DECL(GPIU4, AC16);
FUNC_GROUP_DECL(ADC12, AC16);
#define AA16 165
SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5),
SIG_DESC_CLEAR(SCU694, 21));
SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5),
SIG_DESC_SET(SCU694, 21));
SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13);
PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5),
SIG_EXPR_LIST_PTR(AA16, ADC13));
GROUP_DECL(SALT14G1, AA16);
FUNC_DECL_2(SALT14, SALT14G0, SALT14G1);
FUNC_GROUP_DECL(GPIU5, AA16);
FUNC_GROUP_DECL(ADC13, AA16);
#define AD16 166
SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6),
SIG_DESC_CLEAR(SCU694, 22));
SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6),
SIG_DESC_SET(SCU694, 22));
SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14);
PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6),
SIG_EXPR_LIST_PTR(AD16, ADC14));
GROUP_DECL(SALT15G1, AD16);
FUNC_DECL_2(SALT15, SALT15G0, SALT15G1);
FUNC_GROUP_DECL(GPIU6, AD16);
FUNC_GROUP_DECL(ADC14, AD16);
#define AC17 167
SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7),
SIG_DESC_CLEAR(SCU694, 23));
SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7),
SIG_DESC_SET(SCU694, 23));
SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15);
PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7),
SIG_EXPR_LIST_PTR(AC17, ADC15));
GROUP_DECL(SALT16G1, AC17);
FUNC_DECL_2(SALT16, SALT16G0, SALT16G1);
FUNC_GROUP_DECL(GPIU7, AC17);
FUNC_GROUP_DECL(ADC15, AC17);
#define AB15 168
SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8));
#define AF14 169
SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9));
#define AD14 170
SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10));
#define AC15 171
SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11));
#define AE15 172
SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12));
#define AE14 173
SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13));
SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13));
PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD);
FUNC_GROUP_DECL(LPCPD, AE14);
FUNC_GROUP_DECL(LHPD, AE14);
#define AD15 174
SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14));
#define AF15 175
SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15));
#define AB7 176
SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16));
PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0);
#define AB8 177
SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17));
PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1);
#define AC8 178
SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18));
PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2);
#define AC7 179
SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19));
PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3);
#define AE7 180
SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20));
PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK);
#define AF7 181
SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21));
PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS);
#define AD7 182
SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22));
PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT);
FUNC_GROUP_DECL(LSIRQ, AD7);
FUNC_GROUP_DECL(ESPIALT, AD7);
#define AD8 183
SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23));
PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST);
FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
#define AE8 184
SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24));
PIN_DECL_1(AE8, GPIOX0, SPI2CS0);
#define AA9 185
SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25));
#define AC9 186
SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26));
#define AF8 187
SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27));
PIN_DECL_1(AF8, GPIOX3, SPI2CK);
#define AB9 188
SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28));
PIN_DECL_1(AB9, GPIOX4, SPI2MOSI);
#define AD9 189
SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29));
PIN_DECL_1(AD9, GPIOX5, SPI2MISO);
GROUP_DECL(SPI2, AE8, AF8, AB9, AD9);
#define AF9 190
SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30));
SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30));
PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12);
#define AB10 191
SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31));
SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12,
SIG_DESC_SET(SCU4D4, 31));
PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12);
GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10);
FUNC_DECL_2(SPI2, SPI2, QSPI2);
GROUP_DECL(UART12G1, AF9, AB10);
FUNC_DECL_2(UART12, UART12G0, UART12G1);
#define AF11 192
SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0));
SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0));
PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1);
FUNC_GROUP_DECL(SALT5, AF11);
FUNC_GROUP_DECL(WDTRST1, AF11);
#define AD12 193
SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1));
SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1));
PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2);
FUNC_GROUP_DECL(SALT6, AD12);
FUNC_GROUP_DECL(WDTRST2, AD12);
#define AE11 194
SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2));
SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2));
PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3);
FUNC_GROUP_DECL(SALT7, AE11);
FUNC_GROUP_DECL(WDTRST3, AE11);
#define AA12 195
SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3));
SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3));
PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4);
FUNC_GROUP_DECL(SALT8, AA12);
FUNC_GROUP_DECL(WDTRST4, AA12);
#define AE12 196
SIG_EXPR_LIST_DECL_SESG(AE12, FWSPIQ2, FWQSPI, SIG_DESC_SET(SCU438, 4));
SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIQ2),
SIG_EXPR_LIST_PTR(AE12, GPIOY4));
#define AF12 197
SIG_EXPR_LIST_DECL_SESG(AF12, FWSPIQ3, FWQSPI, SIG_DESC_SET(SCU438, 5));
SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIQ3),
SIG_EXPR_LIST_PTR(AF12, GPIOY5));
FUNC_GROUP_DECL(FWQSPI, AE12, AF12);
#define AC12 198
SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
#define AB12 199
SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7));
#define AC10 200
SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8));
#define AD10 201
SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9));
#define AE10 202
SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10));
#define AB11 203
SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11));
PIN_DECL_1(AB11, GPIOZ3, SPI1CK);
#define AC11 204
SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12));
PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI);
#define AA11 205
SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13));
PIN_DECL_1(AA11, GPIOZ5, SPI1MISO);
GROUP_DECL(SPI1, AB11, AC11, AA11);
#define AD11 206
SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14));
SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13,
SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14));
PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13);
#define AF10 207
SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15));
SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13,
SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15));
PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13);
GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10);
FUNC_DECL_2(SPI1, SPI1, QSPI1);
GROUP_DECL(UART13G1, AD11, AF10);
FUNC_DECL_2(UART13, UART13G0, UART13G1);
#define C6 208
SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO);
#define D6 209
SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN);
#define D5 210
SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0);
#define A3 211
SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1);
#define C5 212
SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4),
SIG_DESC_SET(SCU500, 6));
PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2);
#define E6 213
SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5),
SIG_DESC_SET(SCU500, 6));
PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3);
#define B3 214
SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI);
#define A2 215
SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7),
SIG_DESC_SET(SCU500, 6));
PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL);
#define B2 216
SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0);
#define B1 217
SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1);
#define C4 218
SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV);
#define E5 219
SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11),
SIG_DESC_SET(SCU500, 6));
SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11),
SIG_DESC_CLEAR(SCU500, 6));
PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER);
FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
#define D4 220
SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO);
#define C2 221
SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN);
#define C1 222
SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0);
#define D3 223
SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1);
#define E4 224
SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16),
SIG_DESC_SET(SCU500, 7));
PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2);
#define F5 225
SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17),
SIG_DESC_SET(SCU500, 7));
PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3);
#define D2 226
SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI);
#define E3 227
SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19),
SIG_DESC_SET(SCU500, 7));
PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL);
#define D1 228
SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0);
#define F4 229
SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1);
#define E2 230
SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV);
#define E1 231
SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23),
SIG_DESC_SET(SCU500, 7));
SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23),
SIG_DESC_CLEAR(SCU500, 7));
PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER);
FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
#define AB4 232
SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
#define AA4 233
SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
#define AC4 234
SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
#define AA5 235
SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
#define Y5 236
SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
#define AB5 237
SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
#define AB6 238
SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
#define AC5 239
SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
#define Y1 240
SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
#define Y2 241
SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
#define Y3 242
SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
#define Y4 243
SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
SIG_DESC_SET(SCU500, 3));
SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
FUNC_DECL_1(FWSPID, FWSPID);
FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
/*
* FIXME: Confirm bits and priorities are the right way around for the
* following 4 pins
*/
#define AF25 244
SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20));
SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20));
PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL),
SIG_EXPR_LIST_PTR(AF25, FSI1CLK));
#define AE26 245
SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21));
SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21));
PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA),
SIG_EXPR_LIST_PTR(AE26, FSI1DATA));
GROUP_DECL(I3C3, AF25, AE26);
FUNC_DECL_2(I3C3, HVI3C3, I3C3);
FUNC_GROUP_DECL(FSI1, AF25, AE26);
#define AE25 246
SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22));
SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22));
PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL),
SIG_EXPR_LIST_PTR(AE25, FSI2CLK));
#define AF24 247
SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23));
SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23));
PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA),
SIG_EXPR_LIST_PTR(AF24, FSI2DATA));
GROUP_DECL(I3C4, AE25, AF24);
FUNC_DECL_2(I3C4, HVI3C4, I3C4);
FUNC_GROUP_DECL(FSI2, AE25, AF24);
#define AF23 248
SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16));
PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL));
#define AE24 249
SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17));
PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA));
FUNC_GROUP_DECL(I3C1, AF23, AE24);
#define AF22 250
SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18));
PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL));
#define AE22 251
SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19));
PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA));
FUNC_GROUP_DECL(I3C2, AF22, AE22);
#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }
#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }
#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }
#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }
#define A4 252
SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
SIG_DESC_SET(SCUC20, 16));
SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC);
PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
SIG_EXPR_LIST_PTR(A4, USB2AHDP));
#define B4 253
SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
SIG_EXPR_LIST_PTR(B4, USB2AHDN));
GROUP_DECL(USBA, A4, B4);
FUNC_DECL_1(USB2ADP, USBA);
FUNC_DECL_1(USB2AD, USBA);
FUNC_DECL_1(USB2AH, USBA);
FUNC_DECL_1(USB2AHP, USBA);
#define A6 254
SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC);
SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC);
PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP),
SIG_EXPR_LIST_PTR(A6, USB2BHDP));
#define B6 255
SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC);
SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC);
PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN),
SIG_EXPR_LIST_PTR(B6, USB2BHDN));
GROUP_DECL(USBB, A6, B6);
FUNC_DECL_1(USB11BHID, USBB);
FUNC_DECL_1(USB2BD, USBB);
FUNC_DECL_1(USB2BH, USBB);
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
ASPEED_PINCTRL_PIN(A16),
ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A21),
ASPEED_PINCTRL_PIN(A22),
ASPEED_PINCTRL_PIN(A23),
ASPEED_PINCTRL_PIN(A24),
ASPEED_PINCTRL_PIN(A25),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(AA11),
ASPEED_PINCTRL_PIN(AA12),
ASPEED_PINCTRL_PIN(AA16),
ASPEED_PINCTRL_PIN(AA17),
ASPEED_PINCTRL_PIN(AA23),
ASPEED_PINCTRL_PIN(AA24),
ASPEED_PINCTRL_PIN(AA25),
ASPEED_PINCTRL_PIN(AA26),
ASPEED_PINCTRL_PIN(AA4),
ASPEED_PINCTRL_PIN(AA5),
ASPEED_PINCTRL_PIN(AA9),
ASPEED_PINCTRL_PIN(AB10),
ASPEED_PINCTRL_PIN(AB11),
ASPEED_PINCTRL_PIN(AB12),
ASPEED_PINCTRL_PIN(AB15),
ASPEED_PINCTRL_PIN(AB16),
ASPEED_PINCTRL_PIN(AB17),
ASPEED_PINCTRL_PIN(AB18),
ASPEED_PINCTRL_PIN(AB19),
ASPEED_PINCTRL_PIN(AB22),
ASPEED_PINCTRL_PIN(AB23),
ASPEED_PINCTRL_PIN(AB24),
ASPEED_PINCTRL_PIN(AB25),
ASPEED_PINCTRL_PIN(AB26),
ASPEED_PINCTRL_PIN(AB4),
ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(AB8),
ASPEED_PINCTRL_PIN(AB9),
ASPEED_PINCTRL_PIN(AC10),
ASPEED_PINCTRL_PIN(AC11),
ASPEED_PINCTRL_PIN(AC12),
ASPEED_PINCTRL_PIN(AC15),
ASPEED_PINCTRL_PIN(AC16),
ASPEED_PINCTRL_PIN(AC17),
ASPEED_PINCTRL_PIN(AC18),
ASPEED_PINCTRL_PIN(AC19),
ASPEED_PINCTRL_PIN(AC22),
ASPEED_PINCTRL_PIN(AC23),
ASPEED_PINCTRL_PIN(AC24),
ASPEED_PINCTRL_PIN(AC26),
ASPEED_PINCTRL_PIN(AC4),
ASPEED_PINCTRL_PIN(AC5),
ASPEED_PINCTRL_PIN(AC7),
ASPEED_PINCTRL_PIN(AC8),
ASPEED_PINCTRL_PIN(AC9),
ASPEED_PINCTRL_PIN(AD10),
ASPEED_PINCTRL_PIN(AD11),
ASPEED_PINCTRL_PIN(AD12),
ASPEED_PINCTRL_PIN(AD14),
ASPEED_PINCTRL_PIN(AD15),
ASPEED_PINCTRL_PIN(AD16),
ASPEED_PINCTRL_PIN(AD19),
ASPEED_PINCTRL_PIN(AD20),
ASPEED_PINCTRL_PIN(AD22),
ASPEED_PINCTRL_PIN(AD23),
ASPEED_PINCTRL_PIN(AD24),
ASPEED_PINCTRL_PIN(AD25),
ASPEED_PINCTRL_PIN(AD26),
ASPEED_PINCTRL_PIN(AD7),
ASPEED_PINCTRL_PIN(AD8),
ASPEED_PINCTRL_PIN(AD9),
ASPEED_PINCTRL_PIN(AE10),
ASPEED_PINCTRL_PIN(AE11),
ASPEED_PINCTRL_PIN(AE12),
ASPEED_PINCTRL_PIN(AE14),
ASPEED_PINCTRL_PIN(AE15),
ASPEED_PINCTRL_PIN(AE16),
ASPEED_PINCTRL_PIN(AE18),
ASPEED_PINCTRL_PIN(AE19),
ASPEED_PINCTRL_PIN(AE22),
ASPEED_PINCTRL_PIN(AE24),
ASPEED_PINCTRL_PIN(AE25),
ASPEED_PINCTRL_PIN(AE26),
ASPEED_PINCTRL_PIN(AE7),
ASPEED_PINCTRL_PIN(AE8),
ASPEED_PINCTRL_PIN(AF10),
ASPEED_PINCTRL_PIN(AF11),
ASPEED_PINCTRL_PIN(AF12),
ASPEED_PINCTRL_PIN(AF14),
ASPEED_PINCTRL_PIN(AF15),
ASPEED_PINCTRL_PIN(AF22),
ASPEED_PINCTRL_PIN(AF23),
ASPEED_PINCTRL_PIN(AF24),
ASPEED_PINCTRL_PIN(AF25),
ASPEED_PINCTRL_PIN(AF7),
ASPEED_PINCTRL_PIN(AF8),
ASPEED_PINCTRL_PIN(AF9),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B12),
ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B16),
ASPEED_PINCTRL_PIN(B17),
ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20),
ASPEED_PINCTRL_PIN(B21),
ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B24),
ASPEED_PINCTRL_PIN(B25),
ASPEED_PINCTRL_PIN(B26),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C17),
ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C19),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
ASPEED_PINCTRL_PIN(C21),
ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C23),
ASPEED_PINCTRL_PIN(C24),
ASPEED_PINCTRL_PIN(C25),
ASPEED_PINCTRL_PIN(C26),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(C6),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D11),
ASPEED_PINCTRL_PIN(D12),
ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D20),
ASPEED_PINCTRL_PIN(D21),
ASPEED_PINCTRL_PIN(D22),
ASPEED_PINCTRL_PIN(D23),
ASPEED_PINCTRL_PIN(D24),
ASPEED_PINCTRL_PIN(D26),
ASPEED_PINCTRL_PIN(D3),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(E1),
ASPEED_PINCTRL_PIN(E11),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
ASPEED_PINCTRL_PIN(E14),
ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E16),
ASPEED_PINCTRL_PIN(E17),
ASPEED_PINCTRL_PIN(E18),
ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E21),
ASPEED_PINCTRL_PIN(E22),
ASPEED_PINCTRL_PIN(E23),
ASPEED_PINCTRL_PIN(E24),
ASPEED_PINCTRL_PIN(E25),
ASPEED_PINCTRL_PIN(E26),
ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E4),
ASPEED_PINCTRL_PIN(E5),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(F13),
ASPEED_PINCTRL_PIN(F15),
ASPEED_PINCTRL_PIN(F22),
ASPEED_PINCTRL_PIN(F23),
ASPEED_PINCTRL_PIN(F24),
ASPEED_PINCTRL_PIN(F25),
ASPEED_PINCTRL_PIN(F26),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
ASPEED_PINCTRL_PIN(G22),
ASPEED_PINCTRL_PIN(G23),
ASPEED_PINCTRL_PIN(G24),
ASPEED_PINCTRL_PIN(G26),
ASPEED_PINCTRL_PIN(H22),
ASPEED_PINCTRL_PIN(H23),
ASPEED_PINCTRL_PIN(H24),
ASPEED_PINCTRL_PIN(H25),
ASPEED_PINCTRL_PIN(H26),
ASPEED_PINCTRL_PIN(J22),
ASPEED_PINCTRL_PIN(J23),
ASPEED_PINCTRL_PIN(J24),
ASPEED_PINCTRL_PIN(J25),
ASPEED_PINCTRL_PIN(J26),
ASPEED_PINCTRL_PIN(K23),
ASPEED_PINCTRL_PIN(K24),
ASPEED_PINCTRL_PIN(K25),
ASPEED_PINCTRL_PIN(K26),
ASPEED_PINCTRL_PIN(L23),
ASPEED_PINCTRL_PIN(L24),
ASPEED_PINCTRL_PIN(L26),
ASPEED_PINCTRL_PIN(M23),
ASPEED_PINCTRL_PIN(M24),
ASPEED_PINCTRL_PIN(M25),
ASPEED_PINCTRL_PIN(M26),
ASPEED_PINCTRL_PIN(N23),
ASPEED_PINCTRL_PIN(N24),
ASPEED_PINCTRL_PIN(N25),
ASPEED_PINCTRL_PIN(N26),
ASPEED_PINCTRL_PIN(P23),
ASPEED_PINCTRL_PIN(P24),
ASPEED_PINCTRL_PIN(P25),
ASPEED_PINCTRL_PIN(P26),
ASPEED_PINCTRL_PIN(R23),
ASPEED_PINCTRL_PIN(R24),
ASPEED_PINCTRL_PIN(R26),
ASPEED_PINCTRL_PIN(T23),
ASPEED_PINCTRL_PIN(T24),
ASPEED_PINCTRL_PIN(T25),
ASPEED_PINCTRL_PIN(T26),
ASPEED_PINCTRL_PIN(U24),
ASPEED_PINCTRL_PIN(U25),
ASPEED_PINCTRL_PIN(U26),
ASPEED_PINCTRL_PIN(V24),
ASPEED_PINCTRL_PIN(V25),
ASPEED_PINCTRL_PIN(V26),
ASPEED_PINCTRL_PIN(W23),
ASPEED_PINCTRL_PIN(W24),
ASPEED_PINCTRL_PIN(W26),
ASPEED_PINCTRL_PIN(Y1),
ASPEED_PINCTRL_PIN(Y2),
ASPEED_PINCTRL_PIN(Y23),
ASPEED_PINCTRL_PIN(Y24),
ASPEED_PINCTRL_PIN(Y25),
ASPEED_PINCTRL_PIN(Y26),
ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
};
static const struct aspeed_pin_group aspeed_g6_groups[] = {
ASPEED_PINCTRL_GROUP(ADC0),
ASPEED_PINCTRL_GROUP(ADC1),
ASPEED_PINCTRL_GROUP(ADC10),
ASPEED_PINCTRL_GROUP(ADC11),
ASPEED_PINCTRL_GROUP(ADC12),
ASPEED_PINCTRL_GROUP(ADC13),
ASPEED_PINCTRL_GROUP(ADC14),
ASPEED_PINCTRL_GROUP(ADC15),
ASPEED_PINCTRL_GROUP(ADC2),
ASPEED_PINCTRL_GROUP(ADC3),
ASPEED_PINCTRL_GROUP(ADC4),
ASPEED_PINCTRL_GROUP(ADC5),
ASPEED_PINCTRL_GROUP(ADC6),
ASPEED_PINCTRL_GROUP(ADC7),
ASPEED_PINCTRL_GROUP(ADC8),
ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(ESPI),
ASPEED_PINCTRL_GROUP(ESPIALT),
ASPEED_PINCTRL_GROUP(FSI1),
ASPEED_PINCTRL_GROUP(FSI2),
ASPEED_PINCTRL_GROUP(FWSPIABR),
ASPEED_PINCTRL_GROUP(FWSPID),
ASPEED_PINCTRL_GROUP(FWQSPI),
ASPEED_PINCTRL_GROUP(FWSPIWP),
ASPEED_PINCTRL_GROUP(GPIT0),
ASPEED_PINCTRL_GROUP(GPIT1),
ASPEED_PINCTRL_GROUP(GPIT2),
ASPEED_PINCTRL_GROUP(GPIT3),
ASPEED_PINCTRL_GROUP(GPIT4),
ASPEED_PINCTRL_GROUP(GPIT5),
ASPEED_PINCTRL_GROUP(GPIT6),
ASPEED_PINCTRL_GROUP(GPIT7),
ASPEED_PINCTRL_GROUP(GPIU0),
ASPEED_PINCTRL_GROUP(GPIU1),
ASPEED_PINCTRL_GROUP(GPIU2),
ASPEED_PINCTRL_GROUP(GPIU3),
ASPEED_PINCTRL_GROUP(GPIU4),
ASPEED_PINCTRL_GROUP(GPIU5),
ASPEED_PINCTRL_GROUP(GPIU6),
ASPEED_PINCTRL_GROUP(GPIU7),
ASPEED_PINCTRL_GROUP(HEARTBEAT),
ASPEED_PINCTRL_GROUP(HVI3C3),
ASPEED_PINCTRL_GROUP(HVI3C4),
ASPEED_PINCTRL_GROUP(I2C1),
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C15),
ASPEED_PINCTRL_GROUP(I2C16),
ASPEED_PINCTRL_GROUP(I2C2),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
ASPEED_PINCTRL_GROUP(I2C6),
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
ASPEED_PINCTRL_GROUP(I3C1),
ASPEED_PINCTRL_GROUP(I3C2),
ASPEED_PINCTRL_GROUP(I3C3),
ASPEED_PINCTRL_GROUP(I3C4),
ASPEED_PINCTRL_GROUP(I3C5),
ASPEED_PINCTRL_GROUP(I3C6),
ASPEED_PINCTRL_GROUP(JTAGM),
ASPEED_PINCTRL_GROUP(LHPD),
ASPEED_PINCTRL_GROUP(LHSIRQ),
ASPEED_PINCTRL_GROUP(LPC),
ASPEED_PINCTRL_GROUP(LPCHC),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPME),
ASPEED_PINCTRL_GROUP(LPCSMI),
ASPEED_PINCTRL_GROUP(LSIRQ),
ASPEED_PINCTRL_GROUP(MACLINK1),
ASPEED_PINCTRL_GROUP(MACLINK2),
ASPEED_PINCTRL_GROUP(MACLINK3),
ASPEED_PINCTRL_GROUP(MACLINK4),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
ASPEED_PINCTRL_GROUP(MDIO3),
ASPEED_PINCTRL_GROUP(MDIO4),
ASPEED_PINCTRL_GROUP(NCTS1),
ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
ASPEED_PINCTRL_GROUP(NDTR4),
ASPEED_PINCTRL_GROUP(NRI1),
ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
ASPEED_PINCTRL_GROUP(NRTS4),
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PEWAKE),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM10G0),
ASPEED_PINCTRL_GROUP(PWM10G1),
ASPEED_PINCTRL_GROUP(PWM11G0),
ASPEED_PINCTRL_GROUP(PWM11G1),
ASPEED_PINCTRL_GROUP(PWM12G0),
ASPEED_PINCTRL_GROUP(PWM12G1),
ASPEED_PINCTRL_GROUP(PWM13G0),
ASPEED_PINCTRL_GROUP(PWM13G1),
ASPEED_PINCTRL_GROUP(PWM14G0),
ASPEED_PINCTRL_GROUP(PWM14G1),
ASPEED_PINCTRL_GROUP(PWM15G0),
ASPEED_PINCTRL_GROUP(PWM15G1),
ASPEED_PINCTRL_GROUP(PWM2),
ASPEED_PINCTRL_GROUP(PWM3),
ASPEED_PINCTRL_GROUP(PWM4),
ASPEED_PINCTRL_GROUP(PWM5),
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(PWM8G0),
ASPEED_PINCTRL_GROUP(PWM8G1),
ASPEED_PINCTRL_GROUP(PWM9G0),
ASPEED_PINCTRL_GROUP(PWM9G1),
ASPEED_PINCTRL_GROUP(QSPI1),
ASPEED_PINCTRL_GROUP(QSPI2),
ASPEED_PINCTRL_GROUP(RGMII1),
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RGMII3),
ASPEED_PINCTRL_GROUP(RGMII4),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(RMII3),
ASPEED_PINCTRL_GROUP(RMII4),
ASPEED_PINCTRL_GROUP(RXD1),
ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
ASPEED_PINCTRL_GROUP(SALT1),
ASPEED_PINCTRL_GROUP(SALT10G0),
ASPEED_PINCTRL_GROUP(SALT10G1),
ASPEED_PINCTRL_GROUP(SALT11G0),
ASPEED_PINCTRL_GROUP(SALT11G1),
ASPEED_PINCTRL_GROUP(SALT12G0),
ASPEED_PINCTRL_GROUP(SALT12G1),
ASPEED_PINCTRL_GROUP(SALT13G0),
ASPEED_PINCTRL_GROUP(SALT13G1),
ASPEED_PINCTRL_GROUP(SALT14G0),
ASPEED_PINCTRL_GROUP(SALT14G1),
ASPEED_PINCTRL_GROUP(SALT15G0),
ASPEED_PINCTRL_GROUP(SALT15G1),
ASPEED_PINCTRL_GROUP(SALT16G0),
ASPEED_PINCTRL_GROUP(SALT16G1),
ASPEED_PINCTRL_GROUP(SALT2),
ASPEED_PINCTRL_GROUP(SALT3),
ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SALT5),
ASPEED_PINCTRL_GROUP(SALT6),
ASPEED_PINCTRL_GROUP(SALT7),
ASPEED_PINCTRL_GROUP(SALT8),
ASPEED_PINCTRL_GROUP(SALT9G0),
ASPEED_PINCTRL_GROUP(SALT9G1),
ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SD2),
ASPEED_PINCTRL_GROUP(EMMCG1),
ASPEED_PINCTRL_GROUP(EMMCG4),
ASPEED_PINCTRL_GROUP(EMMCG8),
ASPEED_PINCTRL_GROUP(SGPM1),
ASPEED_PINCTRL_GROUP(SGPM2),
ASPEED_PINCTRL_GROUP(SGPS1),
ASPEED_PINCTRL_GROUP(SGPS2),
ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
ASPEED_PINCTRL_GROUP(SIOPWREQ),
ASPEED_PINCTRL_GROUP(SIOPWRGD),
ASPEED_PINCTRL_GROUP(SIOS3),
ASPEED_PINCTRL_GROUP(SIOS5),
ASPEED_PINCTRL_GROUP(SIOSCI),
ASPEED_PINCTRL_GROUP(SPI1),
ASPEED_PINCTRL_GROUP(SPI1ABR),
ASPEED_PINCTRL_GROUP(SPI1CS1),
ASPEED_PINCTRL_GROUP(SPI1WP),
ASPEED_PINCTRL_GROUP(SPI2),
ASPEED_PINCTRL_GROUP(SPI2CS1),
ASPEED_PINCTRL_GROUP(SPI2CS2),
ASPEED_PINCTRL_GROUP(TACH0),
ASPEED_PINCTRL_GROUP(TACH1),
ASPEED_PINCTRL_GROUP(TACH10),
ASPEED_PINCTRL_GROUP(TACH11),
ASPEED_PINCTRL_GROUP(TACH12),
ASPEED_PINCTRL_GROUP(TACH13),
ASPEED_PINCTRL_GROUP(TACH14),
ASPEED_PINCTRL_GROUP(TACH15),
ASPEED_PINCTRL_GROUP(TACH2),
ASPEED_PINCTRL_GROUP(TACH3),
ASPEED_PINCTRL_GROUP(TACH4),
ASPEED_PINCTRL_GROUP(TACH5),
ASPEED_PINCTRL_GROUP(TACH6),
ASPEED_PINCTRL_GROUP(TACH7),
ASPEED_PINCTRL_GROUP(TACH8),
ASPEED_PINCTRL_GROUP(TACH9),
ASPEED_PINCTRL_GROUP(THRU0),
ASPEED_PINCTRL_GROUP(THRU1),
ASPEED_PINCTRL_GROUP(THRU2),
ASPEED_PINCTRL_GROUP(THRU3),
ASPEED_PINCTRL_GROUP(TXD1),
ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART10),
ASPEED_PINCTRL_GROUP(UART11),
ASPEED_PINCTRL_GROUP(UART12G0),
ASPEED_PINCTRL_GROUP(UART12G1),
ASPEED_PINCTRL_GROUP(UART13G0),
ASPEED_PINCTRL_GROUP(UART13G1),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(UART7),
ASPEED_PINCTRL_GROUP(UART8),
ASPEED_PINCTRL_GROUP(UART9),
ASPEED_PINCTRL_GROUP(USBA),
ASPEED_PINCTRL_GROUP(USBB),
ASPEED_PINCTRL_GROUP(VB),
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(WDTRST1),
ASPEED_PINCTRL_GROUP(WDTRST2),
ASPEED_PINCTRL_GROUP(WDTRST3),
ASPEED_PINCTRL_GROUP(WDTRST4),
};
static const struct aspeed_pin_function aspeed_g6_functions[] = {
ASPEED_PINCTRL_FUNC(ADC0),
ASPEED_PINCTRL_FUNC(ADC1),
ASPEED_PINCTRL_FUNC(ADC10),
ASPEED_PINCTRL_FUNC(ADC11),
ASPEED_PINCTRL_FUNC(ADC12),
ASPEED_PINCTRL_FUNC(ADC13),
ASPEED_PINCTRL_FUNC(ADC14),
ASPEED_PINCTRL_FUNC(ADC15),
ASPEED_PINCTRL_FUNC(ADC2),
ASPEED_PINCTRL_FUNC(ADC3),
ASPEED_PINCTRL_FUNC(ADC4),
ASPEED_PINCTRL_FUNC(ADC5),
ASPEED_PINCTRL_FUNC(ADC6),
ASPEED_PINCTRL_FUNC(ADC7),
ASPEED_PINCTRL_FUNC(ADC8),
ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(EMMC),
ASPEED_PINCTRL_FUNC(ESPI),
ASPEED_PINCTRL_FUNC(ESPIALT),
ASPEED_PINCTRL_FUNC(FSI1),
ASPEED_PINCTRL_FUNC(FSI2),
ASPEED_PINCTRL_FUNC(FWSPIABR),
ASPEED_PINCTRL_FUNC(FWSPID),
ASPEED_PINCTRL_FUNC(FWQSPI),
ASPEED_PINCTRL_FUNC(FWSPIWP),
ASPEED_PINCTRL_FUNC(GPIT0),
ASPEED_PINCTRL_FUNC(GPIT1),
ASPEED_PINCTRL_FUNC(GPIT2),
ASPEED_PINCTRL_FUNC(GPIT3),
ASPEED_PINCTRL_FUNC(GPIT4),
ASPEED_PINCTRL_FUNC(GPIT5),
ASPEED_PINCTRL_FUNC(GPIT6),
ASPEED_PINCTRL_FUNC(GPIT7),
ASPEED_PINCTRL_FUNC(GPIU0),
ASPEED_PINCTRL_FUNC(GPIU1),
ASPEED_PINCTRL_FUNC(GPIU2),
ASPEED_PINCTRL_FUNC(GPIU3),
ASPEED_PINCTRL_FUNC(GPIU4),
ASPEED_PINCTRL_FUNC(GPIU5),
ASPEED_PINCTRL_FUNC(GPIU6),
ASPEED_PINCTRL_FUNC(GPIU7),
ASPEED_PINCTRL_FUNC(HEARTBEAT),
ASPEED_PINCTRL_FUNC(I2C1),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C15),
ASPEED_PINCTRL_FUNC(I2C16),
ASPEED_PINCTRL_FUNC(I2C2),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
ASPEED_PINCTRL_FUNC(I2C6),
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
ASPEED_PINCTRL_FUNC(I3C1),
ASPEED_PINCTRL_FUNC(I3C2),
ASPEED_PINCTRL_FUNC(I3C3),
ASPEED_PINCTRL_FUNC(I3C4),
ASPEED_PINCTRL_FUNC(I3C5),
ASPEED_PINCTRL_FUNC(I3C6),
ASPEED_PINCTRL_FUNC(JTAGM),
ASPEED_PINCTRL_FUNC(LHPD),
ASPEED_PINCTRL_FUNC(LHSIRQ),
ASPEED_PINCTRL_FUNC(LPC),
ASPEED_PINCTRL_FUNC(LPCHC),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPME),
ASPEED_PINCTRL_FUNC(LPCSMI),
ASPEED_PINCTRL_FUNC(LSIRQ),
ASPEED_PINCTRL_FUNC(MACLINK1),
ASPEED_PINCTRL_FUNC(MACLINK2),
ASPEED_PINCTRL_FUNC(MACLINK3),
ASPEED_PINCTRL_FUNC(MACLINK4),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
ASPEED_PINCTRL_FUNC(MDIO3),
ASPEED_PINCTRL_FUNC(MDIO4),
ASPEED_PINCTRL_FUNC(NCTS1),
ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
ASPEED_PINCTRL_FUNC(NDTR4),
ASPEED_PINCTRL_FUNC(NRI1),
ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
ASPEED_PINCTRL_FUNC(NRTS4),
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PEWAKE),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM10),
ASPEED_PINCTRL_FUNC(PWM11),
ASPEED_PINCTRL_FUNC(PWM12),
ASPEED_PINCTRL_FUNC(PWM13),
ASPEED_PINCTRL_FUNC(PWM14),
ASPEED_PINCTRL_FUNC(PWM15),
ASPEED_PINCTRL_FUNC(PWM2),
ASPEED_PINCTRL_FUNC(PWM3),
ASPEED_PINCTRL_FUNC(PWM4),
ASPEED_PINCTRL_FUNC(PWM5),
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(PWM8),
ASPEED_PINCTRL_FUNC(PWM9),
ASPEED_PINCTRL_FUNC(RGMII1),
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RGMII3),
ASPEED_PINCTRL_FUNC(RGMII4),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(RMII3),
ASPEED_PINCTRL_FUNC(RMII4),
ASPEED_PINCTRL_FUNC(RXD1),
ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
ASPEED_PINCTRL_FUNC(SALT1),
ASPEED_PINCTRL_FUNC(SALT10),
ASPEED_PINCTRL_FUNC(SALT11),
ASPEED_PINCTRL_FUNC(SALT12),
ASPEED_PINCTRL_FUNC(SALT13),
ASPEED_PINCTRL_FUNC(SALT14),
ASPEED_PINCTRL_FUNC(SALT15),
ASPEED_PINCTRL_FUNC(SALT16),
ASPEED_PINCTRL_FUNC(SALT2),
ASPEED_PINCTRL_FUNC(SALT3),
ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SALT5),
ASPEED_PINCTRL_FUNC(SALT6),
ASPEED_PINCTRL_FUNC(SALT7),
ASPEED_PINCTRL_FUNC(SALT8),
ASPEED_PINCTRL_FUNC(SALT9),
ASPEED_PINCTRL_FUNC(SD1),
ASPEED_PINCTRL_FUNC(SD2),
ASPEED_PINCTRL_FUNC(SGPM1),
ASPEED_PINCTRL_FUNC(SGPM2),
ASPEED_PINCTRL_FUNC(SGPS1),
ASPEED_PINCTRL_FUNC(SGPS2),
ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
ASPEED_PINCTRL_FUNC(SIOPWREQ),
ASPEED_PINCTRL_FUNC(SIOPWRGD),
ASPEED_PINCTRL_FUNC(SIOS3),
ASPEED_PINCTRL_FUNC(SIOS5),
ASPEED_PINCTRL_FUNC(SIOSCI),
ASPEED_PINCTRL_FUNC(SPI1),
ASPEED_PINCTRL_FUNC(SPI1ABR),
ASPEED_PINCTRL_FUNC(SPI1CS1),
ASPEED_PINCTRL_FUNC(SPI1WP),
ASPEED_PINCTRL_FUNC(SPI2),
ASPEED_PINCTRL_FUNC(SPI2CS1),
ASPEED_PINCTRL_FUNC(SPI2CS2),
ASPEED_PINCTRL_FUNC(TACH0),
ASPEED_PINCTRL_FUNC(TACH1),
ASPEED_PINCTRL_FUNC(TACH10),
ASPEED_PINCTRL_FUNC(TACH11),
ASPEED_PINCTRL_FUNC(TACH12),
ASPEED_PINCTRL_FUNC(TACH13),
ASPEED_PINCTRL_FUNC(TACH14),
ASPEED_PINCTRL_FUNC(TACH15),
ASPEED_PINCTRL_FUNC(TACH2),
ASPEED_PINCTRL_FUNC(TACH3),
ASPEED_PINCTRL_FUNC(TACH4),
ASPEED_PINCTRL_FUNC(TACH5),
ASPEED_PINCTRL_FUNC(TACH6),
ASPEED_PINCTRL_FUNC(TACH7),
ASPEED_PINCTRL_FUNC(TACH8),
ASPEED_PINCTRL_FUNC(TACH9),
ASPEED_PINCTRL_FUNC(THRU0),
ASPEED_PINCTRL_FUNC(THRU1),
ASPEED_PINCTRL_FUNC(THRU2),
ASPEED_PINCTRL_FUNC(THRU3),
ASPEED_PINCTRL_FUNC(TXD1),
ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART10),
ASPEED_PINCTRL_FUNC(UART11),
ASPEED_PINCTRL_FUNC(UART12),
ASPEED_PINCTRL_FUNC(UART13),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(UART7),
ASPEED_PINCTRL_FUNC(UART8),
ASPEED_PINCTRL_FUNC(UART9),
ASPEED_PINCTRL_FUNC(USB11BHID),
ASPEED_PINCTRL_FUNC(USB2AD),
ASPEED_PINCTRL_FUNC(USB2ADP),
ASPEED_PINCTRL_FUNC(USB2AH),
ASPEED_PINCTRL_FUNC(USB2AHP),
ASPEED_PINCTRL_FUNC(USB2BD),
ASPEED_PINCTRL_FUNC(USB2BH),
ASPEED_PINCTRL_FUNC(VB),
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(WDTRST1),
ASPEED_PINCTRL_FUNC(WDTRST2),
ASPEED_PINCTRL_FUNC(WDTRST3),
ASPEED_PINCTRL_FUNC(WDTRST4),
};
static struct aspeed_pin_config aspeed_g6_configs[] = {
/* GPIOB7 */
ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
/* GPIOB6 */
ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
/* GPIOB5 */
ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
/* GPIOB4 */
ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
/* GPIOB3 */
ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
/* GPIOB2 */
ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
/* GPIOB1 */
ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
/* GPIOB0 */
ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
/* GPIOH3 */
ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
/* GPIOH2 */
ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
/* GPIOH1 */
ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
/* GPIOH0 */
ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
/* GPIOL7 */
ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
/* GPIOL6 */
ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
/* GPIOL5 */
ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
/* GPIOL4 */
ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
/* GPIOJ7 */
ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
/* GPIOJ6 */
ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
/* GPIOJ5 */
ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
/* GPIOJ4 */
ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
/* GPIOJ3 */
ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
/* GPIOJ2 */
ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
/* GPIOJ1 */
ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
/* GPIOJ0 */
ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
/* GPIOI7 */
ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
/* GPIOI6 */
ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
/* GPIOI5 */
ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
/* GPIOI4 */
ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
/* GPIOI3 */
ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
/* GPIOI2 */
ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
/* GPIOI1 */
ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
/* GPIOI0 */
ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
/* GPIOP7 */
ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
/* GPIOP6 */
ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
/* GPIOP5 */
ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
/* GPIOP4 */
ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
/* GPIOP3 */
ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
/* GPIOP2 */
ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
/* GPIOP1 */
ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
/* GPIOP0 */
ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
/* GPIOO7 */
ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
/* GPIOO6 */
ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
/* GPIOO5 */
ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
/* GPIOO4 */
ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
/* GPIOO3 */
ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
/* GPIOO2 */
ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
/* GPIOO1 */
ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
/* GPIOO0 */
ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
/* GPION7 */
ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
/* GPION6 */
ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
/* GPION5 */
ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
/* GPION4 */
ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
/* GPION3 */
ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
/* GPION2 */
ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
/* GPION1 */
ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
/* GPION0 */
ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
/* GPIOM7 */
ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
/* GPIOM6 */
ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
/* GPIOM5 */
ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
/* GPIOM4 */
ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
/* GPIOM3 */
ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
/* GPIOM2 */
ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
/* GPIOM1 */
ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
/* GPIOM0 */
ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
/* GPIOS7 */
ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23),
/* GPIOS6 */
ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22),
/* GPIOS5 */
ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21),
/* GPIOS4 */
ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20),
/* GPIOS3*/
ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19),
/* GPIOS2 */
ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18),
/* GPIOS1 */
ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17),
/* GPIOS0 */
ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16),
/* GPIOR7 */
ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15),
/* GPIOR6 */
ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14),
/* GPIOR5 */
ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13),
/* GPIOR4 */
ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12),
/* GPIOR3*/
ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11),
/* GPIOR2 */
ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10),
/* GPIOR1 */
ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9),
/* GPIOR0 */
ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8),
/* GPIOX7 */
ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
/* GPIOX6 */
ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
/* GPIOX5 */
ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
/* GPIOX4 */
ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
/* GPIOX3*/
ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
/* GPIOX2 */
ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
/* GPIOX1 */
ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
/* GPIOX0 */
ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
/* GPIOV7 */
ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
/* GPIOV6 */
ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
/* GPIOV5 */
ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
/* GPIOV4 */
ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
/* GPIOV3*/
ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
/* GPIOV2 */
ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
/* GPIOV1 */
ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
/* GPIOV0 */
ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
/* GPIOZ7 */
ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
/* GPIOZ6 */
ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
/* GPIOZ5 */
ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
/* GPIOZ4 */
ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
/* GPIOZ3*/
ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
/* GPIOZ1 */
ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
/* GPIOZ0 */
ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
/* GPIOY6 */
ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
/* GPIOY5 */
ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
/* GPIOY4 */
ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
/* GPIOY3 */
ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
/* GPIOY2 */
ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
/* GPIOY1 */
ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
/* GPIOY0 */
ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
/* LAD3 */
{ PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
/* LAD2 */
{ PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
/* LAD1 */
{ PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
/* LAD0 */
{ PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
/* MAC3 */
{ PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
{ PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
/* MAC4 */
{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
/* GPIO18E */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
/* GPIO18D */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3),
/* GPIO18C */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
/* GPIO18B */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
/* GPIO18A */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
};
/**
* aspeed_g6_sig_expr_set() - Configure a pin's signal by applying an
* expression's descriptor state for all descriptors in the expression.
*
* @ctx: The pinmux context
* @expr: The expression associated with the function whose signal is to be
* configured
* @enable: true to enable an function's signal through a pin's signal
* expression, false to disable the function's signal
*
* Return: 0 if the expression is configured as requested and a negative error
* code otherwise
*/
static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
bool is_strap;
if (!ctx->maps[desc->ip])
return -ENODEV;
WARN_ON(desc->ip != ASPEED_IP_SCU);
is_strap = desc->reg == SCU500 || desc->reg == SCU510;
if (is_strap) {
/*
* The AST2600 has write protection mask registers for
* the hardware strapping in SCU508 and SCU518. Assume
* that if the platform doesn't want the strapping
* values changed that it has set the write mask.
*
* The strapping registers implement write-1-clear
* behaviour. SCU500 is paired with clear writes on
* SCU504, likewise SCU510 is paired with SCU514.
*/
u32 clear = ~val & desc->mask;
u32 w1c = desc->reg + 4;
if (clear)
ret = regmap_update_bits(ctx->maps[desc->ip],
w1c, desc->mask,
clear);
}
ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
desc->mask, val);
if (ret)
return ret;
}
ret = aspeed_sig_expr_eval(ctx, expr, enable);
if (ret < 0)
return ret;
if (!ret)
return -EPERM;
return 0;
}
static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
{ PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
{ PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
{ PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
{ PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
};
static const struct aspeed_pinmux_ops aspeed_g5_ops = {
.set = aspeed_g6_sig_expr_set,
};
static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
.pins = aspeed_g6_pins,
.npins = ARRAY_SIZE(aspeed_g6_pins),
.pinmux = {
.ops = &aspeed_g5_ops,
.groups = aspeed_g6_groups,
.ngroups = ARRAY_SIZE(aspeed_g6_groups),
.functions = aspeed_g6_functions,
.nfunctions = ARRAY_SIZE(aspeed_g6_functions),
},
.configs = aspeed_g6_configs,
.nconfigs = ARRAY_SIZE(aspeed_g6_configs),
.confmaps = aspeed_g6_pin_config_map,
.nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
};
static const struct pinmux_ops aspeed_g6_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
.set_mux = aspeed_pinmux_set_mux,
.gpio_request_enable = aspeed_gpio_request_enable,
.strict = true,
};
static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static const struct pinconf_ops aspeed_g6_conf_ops = {
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,
.pin_config_group_get = aspeed_pin_config_group_get,
.pin_config_group_set = aspeed_pin_config_group_set,
};
static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
.name = "aspeed-g6-pinctrl",
.pins = aspeed_g6_pins,
.npins = ARRAY_SIZE(aspeed_g6_pins),
.pctlops = &aspeed_g6_pinctrl_ops,
.pmxops = &aspeed_g6_pinmux_ops,
.confops = &aspeed_g6_conf_ops,
};
static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
{
int i;
for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++)
aspeed_g6_pins[i].number = i;
return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc,
&aspeed_g6_pinctrl_data);
}
static const struct of_device_id aspeed_g6_pinctrl_of_match[] = {
{ .compatible = "aspeed,ast2600-pinctrl", },
{ },
};
static struct platform_driver aspeed_g6_pinctrl_driver = {
.probe = aspeed_g6_pinctrl_probe,
.driver = {
.name = "aspeed-g6-pinctrl",
.of_match_table = aspeed_g6_pinctrl_of_match,
},
};
static int aspeed_g6_pinctrl_init(void)
{
return platform_driver_register(&aspeed_g6_pinctrl_driver);
}
arch_initcall(aspeed_g6_pinctrl_init);
|
linux-master
|
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 IBM Corp.
*/
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string.h>
#include "../core.h"
#include "pinctrl-aspeed.h"
int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.ngroups;
}
const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.groups[group].name;
}
int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group, const unsigned int **pins,
unsigned int *npins)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*pins = &pdata->pinmux.groups[group].pins[0];
*npins = pdata->pinmux.groups[group].npins;
return 0;
}
void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.nfunctions;
}
const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.functions[function].name;
}
int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*groups = pdata->pinmux.functions[function].groups;
*num_groups = pdata->pinmux.functions[function].ngroups;
return 0;
}
static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Enabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (!ret)
return aspeed_sig_expr_set(ctx, expr, true);
return 0;
}
static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Disabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (ret)
return aspeed_sig_expr_set(ctx, expr, false);
return 0;
}
/**
* aspeed_disable_sig() - Disable a signal on a pin by disabling all provided
* signal expressions.
*
* @ctx: The pinmux context
* @exprs: The list of signal expressions (from a priority level on a pin)
*
* Return: 0 if all expressions are disabled, otherwise a negative error code
*/
static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr **exprs)
{
int ret = 0;
if (!exprs)
return -EINVAL;
while (*exprs && !ret) {
ret = aspeed_sig_expr_disable(ctx, *exprs);
exprs++;
}
return ret;
}
/**
* aspeed_find_expr_by_name - Search for the signal expression needed to
* enable the pin's signal for the requested function.
*
* @exprs: List of signal expressions (haystack)
* @name: The name of the requested function (needle)
*
* Return: A pointer to the signal expression whose function tag matches the
* provided name, otherwise NULL.
*
*/
static const struct aspeed_sig_expr *aspeed_find_expr_by_name(
const struct aspeed_sig_expr **exprs, const char *name)
{
while (*exprs) {
if (strcmp((*exprs)->function, name) == 0)
return *exprs;
exprs++;
}
return NULL;
}
static char *get_defined_attribute(const struct aspeed_pin_desc *pdesc,
const char *(*get)(
const struct aspeed_sig_expr *))
{
char *found = NULL;
size_t len = 0;
const struct aspeed_sig_expr ***prios, **funcs, *expr;
prios = pdesc->prios;
while ((funcs = *prios)) {
while ((expr = *funcs)) {
const char *str = get(expr);
size_t delta = strlen(str) + 2;
char *expanded;
expanded = krealloc(found, len + delta + 1, GFP_KERNEL);
if (!expanded) {
kfree(found);
return expanded;
}
found = expanded;
found[len] = '\0';
len += delta;
strcat(found, str);
strcat(found, ", ");
funcs++;
}
prios++;
}
if (len < 2) {
kfree(found);
return NULL;
}
found[len - 2] = '\0';
return found;
}
static const char *aspeed_sig_expr_function(const struct aspeed_sig_expr *expr)
{
return expr->function;
}
static char *get_defined_functions(const struct aspeed_pin_desc *pdesc)
{
return get_defined_attribute(pdesc, aspeed_sig_expr_function);
}
static const char *aspeed_sig_expr_signal(const struct aspeed_sig_expr *expr)
{
return expr->signal;
}
static char *get_defined_signals(const struct aspeed_pin_desc *pdesc)
{
return get_defined_attribute(pdesc, aspeed_sig_expr_signal);
}
int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
unsigned int group)
{
int i;
int ret;
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
const struct aspeed_pin_function *pfunc =
&pdata->pinmux.functions[function];
for (i = 0; i < pgroup->npins; i++) {
int pin = pgroup->pins[i];
const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data;
const struct aspeed_sig_expr *expr = NULL;
const struct aspeed_sig_expr **funcs;
const struct aspeed_sig_expr ***prios;
if (!pdesc)
return -EINVAL;
pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
prios = pdesc->prios;
if (!prios)
continue;
/* Disable functions at a higher priority than that requested */
while ((funcs = *prios)) {
expr = aspeed_find_expr_by_name(funcs, pfunc->name);
if (expr)
break;
ret = aspeed_disable_sig(&pdata->pinmux, funcs);
if (ret)
return ret;
prios++;
}
if (!expr) {
char *functions = get_defined_functions(pdesc);
char *signals = get_defined_signals(pdesc);
pr_warn("No function %s found on pin %s (%d). Found signal(s) %s for function(s) %s\n",
pfunc->name, pdesc->name, pin, signals,
functions);
kfree(signals);
kfree(functions);
return -ENXIO;
}
ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
if (ret)
return ret;
pr_debug("Muxed pin %s as %s for %s\n", pdesc->name, expr->signal,
expr->function);
}
return 0;
}
static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
{
/*
* We need to differentiate between GPIO and non-GPIO signals to
* implement the gpio_request_enable() interface. For better or worse
* the ASPEED pinctrl driver uses the expression names to determine
* whether an expression will mux a pin for GPIO.
*
* Generally we have the following - A GPIO such as B1 has:
*
* - expr->signal set to "GPIOB1"
* - expr->function set to "GPIOB1"
*
* Using this fact we can determine whether the provided expression is
* a GPIO expression by testing the signal name for the string prefix
* "GPIO".
*
* However, some GPIOs are input-only, and the ASPEED datasheets name
* them differently. An input-only GPIO such as T0 has:
*
* - expr->signal set to "GPIT0"
* - expr->function set to "GPIT0"
*
* It's tempting to generalise the prefix test from "GPIO" to "GPI" to
* account for both GPIOs and GPIs, but in doing so we run aground on
* another feature:
*
* Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
* function where the input state of one pin is replicated as the
* output state of another (as if they were shorted together - a mux
* configuration that is typically enabled by hardware strapping).
* This feature allows the BMC to pass e.g. power button state through
* to the host while the BMC is yet to boot, but take control of the
* button state once the BMC has booted by muxing each pin as a
* separate, pin-specific GPIO.
*
* Conceptually this pass-through mode is a form of GPIO and is named
* as such in the datasheets, e.g. "GPID0". This naming similarity
* trips us up with the simple GPI-prefixed-signal-name scheme
* discussed above, as the pass-through configuration is not what we
* want when muxing a pin as GPIO for the GPIO subsystem.
*
* On e.g. the AST2400, a pass-through function "GPID0" is grouped on
* balls A18 and D16, where we have:
*
* For ball A18:
* - expr->signal set to "GPID0IN"
* - expr->function set to "GPID0"
*
* For ball D16:
* - expr->signal set to "GPID0OUT"
* - expr->function set to "GPID0"
*
* By contrast, the pin-specific GPIO expressions for the same pins are
* as follows:
*
* For ball A18:
* - expr->signal looks like "GPIOD0"
* - expr->function looks like "GPIOD0"
*
* For ball D16:
* - expr->signal looks like "GPIOD1"
* - expr->function looks like "GPIOD1"
*
* Testing both the signal _and_ function names gives us the means
* differentiate the pass-through GPIO pinmux configuration from the
* pin-specific configuration that the GPIO subsystem is after: An
* expression is a pin-specific (non-pass-through) GPIO configuration
* if the signal prefix is "GPI" and the signal name matches the
* function name.
*/
return !strncmp(expr->signal, "GPI", 3) &&
!strcmp(expr->signal, expr->function);
}
static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
{
if (!exprs)
return false;
while (*exprs) {
if (aspeed_expr_is_gpio(*exprs))
return true;
exprs++;
}
return false;
}
int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
int ret;
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
const struct aspeed_sig_expr ***prios, **funcs, *expr;
if (!pdesc)
return -EINVAL;
prios = pdesc->prios;
if (!prios)
return -ENXIO;
pr_debug("Muxing pin %s for GPIO\n", pdesc->name);
/* Disable any functions of higher priority than GPIO */
while ((funcs = *prios)) {
if (aspeed_gpio_in_exprs(funcs))
break;
ret = aspeed_disable_sig(&pdata->pinmux, funcs);
if (ret)
return ret;
prios++;
}
if (!funcs) {
char *signals = get_defined_signals(pdesc);
pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n",
pdesc->name, offset, signals);
kfree(signals);
return -ENXIO;
}
expr = *funcs;
/*
* Disabling all higher-priority expressions is enough to enable the
* lowest-priority signal type. As such it has no associated
* expression.
*/
if (!expr) {
pr_debug("Muxed pin %s as GPIO\n", pdesc->name);
return 0;
}
/*
* If GPIO is not the lowest priority signal type, assume there is only
* one expression defined to enable the GPIO function
*/
ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
if (ret)
return ret;
pr_debug("Muxed pin %s as %s\n", pdesc->name, expr->signal);
return 0;
}
int aspeed_pinctrl_probe(struct platform_device *pdev,
struct pinctrl_desc *pdesc,
struct aspeed_pinctrl_data *pdata)
{
struct device *parent;
struct pinctrl_dev *pctl;
parent = pdev->dev.parent;
if (!parent) {
dev_err(&pdev->dev, "No parent for syscon pincontroller\n");
return -ENODEV;
}
pdata->scu = syscon_node_to_regmap(parent->of_node);
if (IS_ERR(pdata->scu)) {
dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
return PTR_ERR(pdata->scu);
}
pdata->pinmux.maps[ASPEED_IP_SCU] = pdata->scu;
pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
if (IS_ERR(pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(pctl);
}
platform_set_drvdata(pdev, pdata);
return 0;
}
static inline bool pin_in_config_range(unsigned int offset,
const struct aspeed_pin_config *config)
{
return offset >= config->pins[0] && offset <= config->pins[1];
}
static inline const struct aspeed_pin_config *find_pinconf_config(
const struct aspeed_pinctrl_data *pdata,
unsigned int offset,
enum pin_config_param param)
{
unsigned int i;
for (i = 0; i < pdata->nconfigs; i++) {
if (param == pdata->configs[i].param &&
pin_in_config_range(offset, &pdata->configs[i]))
return &pdata->configs[i];
}
return NULL;
}
enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
static const struct aspeed_pin_config_map *find_pinconf_map(
const struct aspeed_pinctrl_data *pdata,
enum pin_config_param param,
enum aspeed_pin_config_map_type type,
s64 value)
{
int i;
for (i = 0; i < pdata->nconfmaps; i++) {
const struct aspeed_pin_config_map *elem;
bool match;
elem = &pdata->confmaps[i];
switch (type) {
case MAP_TYPE_ARG:
match = (elem->arg == -1 || elem->arg == value);
break;
case MAP_TYPE_VAL:
match = (elem->val == value);
break;
}
if (param == elem->param && match)
return elem;
}
return NULL;
}
int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *config)
{
const enum pin_config_param param = pinconf_to_config_param(*config);
const struct aspeed_pin_config_map *pmap;
const struct aspeed_pinctrl_data *pdata;
const struct aspeed_pin_config *pconf;
unsigned int val;
int rc = 0;
u32 arg;
pdata = pinctrl_dev_get_drvdata(pctldev);
pconf = find_pinconf_config(pdata, offset, param);
if (!pconf)
return -ENOTSUPP;
rc = regmap_read(pdata->scu, pconf->reg, &val);
if (rc < 0)
return rc;
pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL,
(val & pconf->mask) >> __ffs(pconf->mask));
if (!pmap)
return -EINVAL;
if (param == PIN_CONFIG_DRIVE_STRENGTH)
arg = (u32) pmap->arg;
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
arg = !!pmap->arg;
else
arg = 1;
if (!arg)
return -EINVAL;
*config = pinconf_to_config_packed(param, arg);
return 0;
}
int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *configs, unsigned int num_configs)
{
const struct aspeed_pinctrl_data *pdata;
unsigned int i;
int rc = 0;
pdata = pinctrl_dev_get_drvdata(pctldev);
for (i = 0; i < num_configs; i++) {
const struct aspeed_pin_config_map *pmap;
const struct aspeed_pin_config *pconf;
enum pin_config_param param;
unsigned int val;
u32 arg;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
pconf = find_pinconf_config(pdata, offset, param);
if (!pconf)
return -ENOTSUPP;
pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg);
if (WARN_ON(!pmap))
return -EINVAL;
val = pmap->val << __ffs(pconf->mask);
rc = regmap_update_bits(pdata->scu, pconf->reg,
pconf->mask, val);
if (rc < 0)
return rc;
pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
__func__, pconf->reg, pconf->mask,
val, param, arg, offset);
}
return 0;
}
int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *config)
{
const unsigned int *pins;
unsigned int npins;
int rc;
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
if (rc < 0)
return rc;
if (!npins)
return -ENODEV;
rc = aspeed_pin_config_get(pctldev, pins[0], config);
return rc;
}
int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int npins;
int rc;
int i;
pr_debug("%s: Fetching pins for group selector %d\n",
__func__, selector);
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
if (rc < 0)
return rc;
for (i = 0; i < npins; i++) {
rc = aspeed_pin_config_set(pctldev, pins[i], configs,
num_configs);
if (rc < 0)
return rc;
}
return 0;
}
|
linux-master
|
drivers/pinctrl/aspeed/pinctrl-aspeed.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell Berlin BG2 pinctrl driver.
*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <[email protected]>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group berlin2_soc_pinctrl_groups[] = {
/* G */
BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "usb1")),
BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0")),
BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s1")),
BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "pwm")),
BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x2, "et"),
/*
* Mode 0x3 mux i2s2 mclk *and* i2s3 mclk:
* add two functions so it can be used with other groups
* within the same subnode in the device tree
*/
BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s3")),
BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
BERLIN_PINCTRL_FUNCTION(0x2, "et")),
BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
BERLIN_PINCTRL_FUNCTION(0x2, "et"),
BERLIN_PINCTRL_FUNCTION(0x3, "vdac")),
BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "et"),
BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "et"),
BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "sata_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16,
BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "ptp")),
BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "soc"),
BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "eddc")),
BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a,
BERLIN_PINCTRL_FUNCTION(0x0, "sts2"),
BERLIN_PINCTRL_FUNCTION(0x1, "sata"),
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sata"),
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"),
BERLIN_PINCTRL_FUNCTION(0x3, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "et"),
BERLIN_PINCTRL_FUNCTION(0x3, "osco")),
BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp")),
BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "pll"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s0")),
BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d,
BERLIN_PINCTRL_FUNCTION(0x0, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")),
BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e,
BERLIN_PINCTRL_FUNCTION(0x0, "spdif"),
BERLIN_PINCTRL_FUNCTION(0x1, "arc")),
BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "adac_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "pdm_a"), /* gpio17..19,pdm */
BERLIN_PINCTRL_FUNCTION(0x7, "pdm_b")), /* gpio12..14,pdm */
BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "twsi0"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "vclki"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x7, "pdm")),
BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1")),
BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "nand"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s2")),
BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")),
BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "nand")),
BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e,
BERLIN_PINCTRL_FUNCTION(0x0, "dvo"),
BERLIN_PINCTRL_FUNCTION(0x2, "sp")),
};
static const struct berlin_desc_group berlin2_sysmgr_pinctrl_groups[] = {
/* GSM */
BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "twsi2"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS2n/SS3n */
BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */
BERLIN_PINCTRL_FUNCTION(0x2, "uart2"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")),
BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x1, "irda0")),
BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")),
BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "clki")),
BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "led")),
BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "led")),
BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "led")),
};
static const struct berlin_pinctrl_desc berlin2_soc_pinctrl_data = {
.groups = berlin2_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2_soc_pinctrl_groups),
};
static const struct berlin_pinctrl_desc berlin2_sysmgr_pinctrl_data = {
.groups = berlin2_sysmgr_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2_sysmgr_pinctrl_groups),
};
static const struct of_device_id berlin2_pinctrl_match[] = {
{
.compatible = "marvell,berlin2-soc-pinctrl",
.data = &berlin2_soc_pinctrl_data
},
{
.compatible = "marvell,berlin2-system-pinctrl",
.data = &berlin2_sysmgr_pinctrl_data
},
{}
};
static int berlin2_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(berlin2_pinctrl_match, &pdev->dev);
return berlin_pinctrl_probe(pdev, match->data);
}
static struct platform_driver berlin2_pinctrl_driver = {
.probe = berlin2_pinctrl_probe,
.driver = {
.name = "berlin-bg2-pinctrl",
.of_match_table = berlin2_pinctrl_match,
},
};
builtin_platform_driver(berlin2_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/berlin/berlin-bg2.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Synaptics AS370 pinctrl driver
*
* Copyright (C) 2018 Synaptics Incorporated
*
* Author: Jisheng Zhang <[email protected]>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 1P8V RSTB*/
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO0 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO2 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG2 */
BERLIN_PINCTRL_GROUP("I2S1_DO1", 0x0, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 3P3V RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO1 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO3 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG3 */
BERLIN_PINCTRL_GROUP("I2S1_DO2", 0x0, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* CORE RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM4 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO4 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG4 */
BERLIN_PINCTRL_GROUP("I2S1_DO3", 0x0, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */
BERLIN_PINCTRL_FUNCTION(0x3, "spdifib"), /* SPDIFIB */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */
BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG6 */
BERLIN_PINCTRL_GROUP("I2S2_BCLKIO", 0x0, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG7 */
BERLIN_PINCTRL_GROUP("I2S2_LRCKIO", 0x0, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO8 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG8 */
BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x0, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO9 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM2 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG9 */
BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO10 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM3 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG10 */
BERLIN_PINCTRL_GROUP("I2S2_DI2", 0x4, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO11 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
BERLIN_PINCTRL_FUNCTION(0x3, "spdific"), /* SPDIFIC */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG11 */
BERLIN_PINCTRL_GROUP("I2S2_DI3", 0x4, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO12 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
BERLIN_PINCTRL_FUNCTION(0x3, "spdifia"), /* SPDIFIA */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG12 */
BERLIN_PINCTRL_GROUP("PDM_CLKO", 0x4, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO13 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG13 */
BERLIN_PINCTRL_GROUP("PDM_DI0", 0x4, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO14 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG14 */
BERLIN_PINCTRL_GROUP("PDM_DI1", 0x4, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG15 */
BERLIN_PINCTRL_GROUP("PDM_DI2", 0x4, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM4 */
BERLIN_PINCTRL_FUNCTION(0x3, "spdifid"), /* SPDIFID */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG16 */
BERLIN_PINCTRL_GROUP("PDM_DI3", 0x4, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM5 */
BERLIN_PINCTRL_FUNCTION(0x3, "spdifi"), /* SPDIFI */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG17 */
BERLIN_PINCTRL_GROUP("NAND_IO0", 0x4, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA0 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie0")), /* MDIO */
BERLIN_PINCTRL_GROUP("NAND_IO1", 0x4, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA1 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie0")), /* MDC */
BERLIN_PINCTRL_GROUP("NAND_IO2", 0x8, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA2 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie1")), /* MDIO */
BERLIN_PINCTRL_GROUP("NAND_IO3", 0x8, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA3 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie1")), /* MDC */
BERLIN_PINCTRL_GROUP("NAND_IO4", 0x8, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA4 */
BERLIN_PINCTRL_GROUP("NAND_IO5", 0x8, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA5 */
BERLIN_PINCTRL_GROUP("NAND_IO6", 0x8, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA6 */
BERLIN_PINCTRL_GROUP("NAND_IO7", 0x8, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA7 */
BERLIN_PINCTRL_GROUP("NAND_ALE", 0x8, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO18 */
BERLIN_PINCTRL_GROUP("NAND_CLE", 0x8, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO19 */
BERLIN_PINCTRL_GROUP("NAND_WEn", 0x8, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO20 */
BERLIN_PINCTRL_GROUP("NAND_REn", 0x8, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO21 */
BERLIN_PINCTRL_GROUP("NAND_WPn", 0xc, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO22 */
BERLIN_PINCTRL_GROUP("NAND_CEn", 0xc, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* RSTn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO23 */
BERLIN_PINCTRL_GROUP("NAND_RDY", 0xc, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO24 */
BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO25 */
BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO26 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM2 */
BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0xc, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO27 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM3 */
BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0xc, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO28 */
BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0xc, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO29 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM4 */
BERLIN_PINCTRL_GROUP("SPI1_SDO", 0xc, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO30 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM5 */
BERLIN_PINCTRL_GROUP("SPI1_SDI", 0xc, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO31 */
BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "usb0"), /* VBUS */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO32 */
BERLIN_PINCTRL_FUNCTION(0x3, "refclko")), /* 25M */
BERLIN_PINCTRL_GROUP("TW1_SCL", 0x10, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw1")), /* SCL */
BERLIN_PINCTRL_GROUP("TW1_SDA", 0x10, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw1")), /* SDA */
BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */
BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */
BERLIN_PINCTRL_GROUP("TMS", 0x10, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM0 */
BERLIN_PINCTRL_GROUP("TDI", 0x10, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM1 */
BERLIN_PINCTRL_GROUP("TDO", 0x10, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")), /* PWM0 */
BERLIN_PINCTRL_GROUP("PWM6", 0x10, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO40 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM6 */
BERLIN_PINCTRL_GROUP("PWM7", 0x10, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO41 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM7 */
BERLIN_PINCTRL_GROUP("PWM0", 0x14, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* VDDCPUSOC RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm"), /* PWM0 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO42 */
BERLIN_PINCTRL_GROUP("PWM1", 0x14, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO43 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM1 */
BERLIN_PINCTRL_GROUP("PWM2", 0x14, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM2 */
BERLIN_PINCTRL_GROUP("PWM3", 0x14, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM3 */
BERLIN_PINCTRL_GROUP("PWM4", 0x14, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM4 */
BERLIN_PINCTRL_GROUP("PWM5", 0x14, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO47 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm")), /* PWM5 */
BERLIN_PINCTRL_GROUP("URT1_RTSn", 0x14, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO48 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RTSn */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM6 */
BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SCL */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG0 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG18 */
BERLIN_PINCTRL_GROUP("URT1_CTSn", 0x14, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO49 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* CTSn */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm"), /* PWM7 */
BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SDA */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG1 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG19 */
BERLIN_PINCTRL_GROUP("URT1_RXD", 0x14, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO50 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG2 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG20 */
BERLIN_PINCTRL_GROUP("URT1_TXD", 0x14, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO51 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG3 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG21 */
BERLIN_PINCTRL_GROUP("I2S3_DI", 0x18, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO52 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DI */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG22 */
BERLIN_PINCTRL_GROUP("I2S3_DO", 0x18, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO53 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG23 */
BERLIN_PINCTRL_GROUP("I2S3_BCLKIO", 0x18, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO54 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "clk")), /* DBG */
BERLIN_PINCTRL_GROUP("I2S3_LRCKIO", 0x18, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO55 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3")), /* LRCKIO */
BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x18, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "cpupll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO56 */
BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x18, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "syspll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO57 */
BERLIN_PINCTRL_GROUP("SD0_CLK", 0x18, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO58 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0")), /* CLK */
BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x18, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "mempll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO59 */
BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x18, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "apll0"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO60 */
BERLIN_PINCTRL_GROUP("SD0_CMD", 0x18, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "apll1"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO61 */
BERLIN_PINCTRL_GROUP("SD0_CDn", 0x1c, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO62 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM2 */
BERLIN_PINCTRL_GROUP("SD0_WP", 0x1c, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO63 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), /* PWM3 */
};
static const struct berlin_pinctrl_desc as370_soc_pinctrl_data = {
.groups = as370_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(as370_soc_pinctrl_groups),
};
static const struct of_device_id as370_pinctrl_match[] = {
{
.compatible = "syna,as370-soc-pinctrl",
.data = &as370_soc_pinctrl_data,
},
{}
};
static int as370_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(as370_pinctrl_match, &pdev->dev);
struct regmap_config *rmconfig;
struct regmap *regmap;
struct resource *res;
void __iomem *base;
rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
if (!rmconfig)
return -ENOMEM;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
rmconfig->reg_bits = 32,
rmconfig->val_bits = 32,
rmconfig->reg_stride = 4,
rmconfig->max_register = resource_size(res);
regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
}
static struct platform_driver as370_pinctrl_driver = {
.probe = as370_pinctrl_probe,
.driver = {
.name = "as370-pinctrl",
.of_match_table = as370_pinctrl_match,
},
};
builtin_platform_driver(as370_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/berlin/pinctrl-as370.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell berlin4ct pinctrl driver
*
* Copyright (C) 2015 Marvell Technology Group Ltd.
*
* Author: Jisheng Zhang <[email protected]>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */
BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD1 */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CDn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */
BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD2 */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT0 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */
BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD3 */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT1 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */
BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXC */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT2 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO4 */
BERLIN_PINCTRL_GROUP("NAND_IO5", 0x0, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXCTL */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT3 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO5 */
BERLIN_PINCTRL_GROUP("NAND_IO6", 0x0, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDC */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO6 */
BERLIN_PINCTRL_GROUP("NAND_IO7", 0x0, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDIO */
BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* WP */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO7 */
BERLIN_PINCTRL_GROUP("NAND_ALE", 0x0, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD0 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO8 */
BERLIN_PINCTRL_GROUP("NAND_CLE", 0x4, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD1 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO9 */
BERLIN_PINCTRL_GROUP("NAND_WEn", 0x4, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD2 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO10 */
BERLIN_PINCTRL_GROUP("NAND_REn", 0x4, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD3 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO11 */
BERLIN_PINCTRL_GROUP("NAND_WPn", 0x4, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO12 */
BERLIN_PINCTRL_GROUP("NAND_CEn", 0x4, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXC */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO13 */
BERLIN_PINCTRL_GROUP("NAND_RDY", 0x4, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */
BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXCTL */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO14 */
BERLIN_PINCTRL_GROUP("SD0_CLK", 0x4, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO29 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CLK*/
BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG8 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG8 */
BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x4, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO30 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG9 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG9 */
BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x4, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO31 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG10 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG10 */
BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x4, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO32 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG11 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG11 */
BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x8, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG12 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG12 */
BERLIN_PINCTRL_GROUP("SD0_CDn", 0x8, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */
BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG13 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG13 */
BERLIN_PINCTRL_GROUP("SD0_CMD", 0x8, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG14 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG14 */
BERLIN_PINCTRL_GROUP("SD0_WP", 0x8, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */
BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG15 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG15 */
BERLIN_PINCTRL_GROUP("STS0_CLK", 0x8, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO21 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x2, "cpupll"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG0 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG0 */
BERLIN_PINCTRL_GROUP("STS0_SOP", 0x8, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO22 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x2, "syspll"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG1 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG1 */
BERLIN_PINCTRL_GROUP("STS0_SD", 0x8, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO23 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x2, "mempll"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG2 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG2 */
BERLIN_PINCTRL_GROUP("STS0_VALD", 0x8, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO24 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG3 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG3 */
BERLIN_PINCTRL_GROUP("STS1_CLK", 0x8, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO25 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG4 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG4 */
BERLIN_PINCTRL_GROUP("STS1_SOP", 0x8, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO26 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG5 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG5 */
BERLIN_PINCTRL_GROUP("STS1_SD", 0xc, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO27 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG6 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG6 */
BERLIN_PINCTRL_GROUP("STS1_VALD", 0xc, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO28 */
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG7 */
BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG7 */
BERLIN_PINCTRL_GROUP("SCRD0_RST", 0xc, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* RST */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CLK */
BERLIN_PINCTRL_GROUP("SCRD0_DCLK", 0xc, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DCLK */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CMD */
BERLIN_PINCTRL_GROUP("SCRD0_GPIO0", 0xc, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO0 */
BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DIO */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT0 */
BERLIN_PINCTRL_GROUP("SCRD0_GPIO1", 0xc, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO18 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO1 */
BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT1 */
BERLIN_PINCTRL_GROUP("SCRD0_DIO", 0xc, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO19 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DIO */
BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DEN */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT2 */
BERLIN_PINCTRL_GROUP("SCRD0_CRD_PRES", 0xc, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* crd pres */
BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT3 */
BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* CLK */
BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")),
BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0x10, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0x10, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO40 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* VALD */
BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0x10, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO41 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* CLK */
BERLIN_PINCTRL_GROUP("SPI1_SDO", 0x10, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO42 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SOP */
BERLIN_PINCTRL_GROUP("SPI1_SDI", 0x10, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO43 */
BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SD */
BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
BERLIN_PINCTRL_FUNCTION(0x1, "usb0"), /* VBUS */
BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* VALD */
BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */
BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */
};
static const struct berlin_desc_group berlin4ct_avio_pinctrl_groups[] = {
BERLIN_PINCTRL_GROUP("TX_EDDC_SCL", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SCL */
BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SCL */
BERLIN_PINCTRL_GROUP("TX_EDDC_SDA", 0x0, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SDA */
BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SDA */
BERLIN_PINCTRL_GROUP("I2S1_LRCKO", 0x0, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO2 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKO */
BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG0 */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG0 */
BERLIN_PINCTRL_GROUP("I2S1_BCLKO", 0x0, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO3 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKO */
BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG1 */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG1 */
BERLIN_PINCTRL_GROUP("I2S1_DO", 0x0, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO4 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO */
BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG2 */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT0 */
BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG2 */
BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT1 */
BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG3 */
BERLIN_PINCTRL_GROUP("SPDIFO", 0x0, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "spdifo"),
BERLIN_PINCTRL_FUNCTION(0x2, "avpll"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x4, "adac")), /* DBG3 */
BERLIN_PINCTRL_GROUP("I2S2_MCLK", 0x0, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x4, "hdmi"), /* FBCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* CLKO */
BERLIN_PINCTRL_GROUP("I2S2_LRCKI", 0x0, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO8 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKI */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* LRCK */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT2 */
BERLIN_PINCTRL_GROUP("I2S2_BCLKI", 0x0, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO9 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKI */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SOP */
BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* BCLK */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT3 */
BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x4, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO10 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SD */
BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* SDIN */
BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* CDn */
BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO11 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* VALD */
BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* PWMCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* WP */
};
static const struct berlin_desc_group berlin4ct_sysmgr_pinctrl_groups[] = {
BERLIN_PINCTRL_GROUP("SM_TW2_SCL", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO19 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SCL */
BERLIN_PINCTRL_GROUP("SM_TW2_SDA", 0x0, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO20 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SDA */
BERLIN_PINCTRL_GROUP("SM_TW3_SCL", 0x0, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO21 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SCL */
BERLIN_PINCTRL_GROUP("SM_TW3_SDA", 0x0, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO22 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SDA */
BERLIN_PINCTRL_GROUP("SM_TMS", 0x0, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO0 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm0")),
BERLIN_PINCTRL_GROUP("SM_TDI", 0x0, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO1 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm1")),
BERLIN_PINCTRL_GROUP("SM_TDO", 0x0, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO2 */
BERLIN_PINCTRL_GROUP("SM_URT0_TXD", 0x0, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO3 */
BERLIN_PINCTRL_GROUP("SM_URT0_RXD", 0x0, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO4 */
BERLIN_PINCTRL_GROUP("SM_URT1_TXD", 0x0, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* RXCLK */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm2"),
BERLIN_PINCTRL_FUNCTION(0x4, "timer0"),
BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")),
BERLIN_PINCTRL_GROUP("SM_URT1_RXD", 0x4, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm3"),
BERLIN_PINCTRL_FUNCTION(0x4, "timer1")),
BERLIN_PINCTRL_GROUP("SM_SPI2_SS0n", 0x4, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SS0 n*/
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO7 */
BERLIN_PINCTRL_GROUP("SM_SPI2_SS1n", 0x4, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO8 */
BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS1n */
BERLIN_PINCTRL_GROUP("SM_SPI2_SS2n", 0x4, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO9 */
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDC */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm0"),
BERLIN_PINCTRL_FUNCTION(0x4, "timer0"),
BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")),
BERLIN_PINCTRL_GROUP("SM_SPI2_SS3n", 0x4, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO10 */
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDIO */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm1"),
BERLIN_PINCTRL_FUNCTION(0x4, "timer1")),
BERLIN_PINCTRL_GROUP("SM_SPI2_SDO", 0x4, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO11 */
BERLIN_PINCTRL_GROUP("SM_SPI2_SDI", 0x4, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO12 */
BERLIN_PINCTRL_GROUP("SM_SPI2_SCLK", 0x4, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SCLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO13 */
BERLIN_PINCTRL_GROUP("SM_FE_LED0", 0x4, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO14 */
BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED0 */
BERLIN_PINCTRL_GROUP("SM_FE_LED1", 0x4, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "pwr"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO 15 */
BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED1 */
BERLIN_PINCTRL_GROUP("SM_FE_LED2", 0x8, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO16 */
BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED2 */
BERLIN_PINCTRL_GROUP("SM_HDMI_HPD", 0x8, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO17 */
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* HPD */
BERLIN_PINCTRL_GROUP("SM_HDMI_CEC", 0x8, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO18 */
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* CEC */
};
static const struct berlin_pinctrl_desc berlin4ct_soc_pinctrl_data = {
.groups = berlin4ct_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin4ct_soc_pinctrl_groups),
};
static const struct berlin_pinctrl_desc berlin4ct_avio_pinctrl_data = {
.groups = berlin4ct_avio_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin4ct_avio_pinctrl_groups),
};
static const struct berlin_pinctrl_desc berlin4ct_sysmgr_pinctrl_data = {
.groups = berlin4ct_sysmgr_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin4ct_sysmgr_pinctrl_groups),
};
static const struct of_device_id berlin4ct_pinctrl_match[] = {
{
.compatible = "marvell,berlin4ct-soc-pinctrl",
.data = &berlin4ct_soc_pinctrl_data,
},
{
.compatible = "marvell,berlin4ct-avio-pinctrl",
.data = &berlin4ct_avio_pinctrl_data,
},
{
.compatible = "marvell,berlin4ct-system-pinctrl",
.data = &berlin4ct_sysmgr_pinctrl_data,
},
{}
};
static int berlin4ct_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(berlin4ct_pinctrl_match, &pdev->dev);
struct regmap_config *rmconfig;
struct regmap *regmap;
struct resource *res;
void __iomem *base;
rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
if (!rmconfig)
return -ENOMEM;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
rmconfig->reg_bits = 32,
rmconfig->val_bits = 32,
rmconfig->reg_stride = 4,
rmconfig->max_register = resource_size(res);
regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
}
static struct platform_driver berlin4ct_pinctrl_driver = {
.probe = berlin4ct_pinctrl_probe,
.driver = {
.name = "berlin4ct-pinctrl",
.of_match_table = berlin4ct_pinctrl_match,
},
};
builtin_platform_driver(berlin4ct_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/berlin/berlin-bg4ct.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell Berlin BG2Q pinctrl driver
*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <[email protected]>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group berlin2q_soc_pinctrl_groups[] = {
/* G */
BERLIN_PINCTRL_GROUP("G0", 0x18, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G1", 0x18, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G2", 0x18, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "arc"),
BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
BERLIN_PINCTRL_GROUP("G3", 0x18, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
BERLIN_PINCTRL_GROUP("G4", 0x18, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "pll"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G5", 0x18, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata_dbg"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G6", 0x18, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G7", 0x18, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "eddc")),
BERLIN_PINCTRL_GROUP("G8", 0x18, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK/SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G9", 0x18, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n/SS1n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
BERLIN_PINCTRL_GROUP("G10", 0x1c, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
BERLIN_PINCTRL_GROUP("G11", 0x1c, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x5, "sata")),
BERLIN_PINCTRL_GROUP("G12", 0x1c, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "agc"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G13", 0x1c, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G14", 0x1c, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G15", 0x1c, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x5, "vdac"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G16", 0x1c, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts0"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x5, "osco"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G17", 0x1c, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x3, "spdif"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G18", 0x1c, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1")),
BERLIN_PINCTRL_GROUP("G19", 0x1c, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "rgmii"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x4, "sts1"),
BERLIN_PINCTRL_FUNCTION(0x5, "osco")),
BERLIN_PINCTRL_GROUP("G20", 0x20, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "demod"),
/*
* Mode 0x4 mux usb2_dbg *and* usb3_dbg:
* add two functions so it can be used with other groups
* within the same subnode in the device tree
*/
BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg"),
BERLIN_PINCTRL_FUNCTION(0x4, "usb3_dbg")),
BERLIN_PINCTRL_GROUP("G21", 0x20, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "sts2"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "demod")),
BERLIN_PINCTRL_GROUP("G22", 0x20, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G23", 0x20, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
BERLIN_PINCTRL_GROUP("G24", 0x20, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "demod"),
BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
BERLIN_PINCTRL_GROUP("G25", 0x20, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "vga"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
BERLIN_PINCTRL_GROUP("G26", 0x20, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "lvds"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G27", 0x20, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "agc"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G28", 0x20, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x3, "avif"),
BERLIN_PINCTRL_FUNCTION(0x4, "usb2_dbg")),
BERLIN_PINCTRL_GROUP("G29", 0x20, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G30", 0x24, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "scrd1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G31", 0x24, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G32", 0x24, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "cam"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
/* GAV */
BERLIN_PINCTRL_GROUP("GAV0", 0x24, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "lvds")),
BERLIN_PINCTRL_GROUP("GAV1", 0x24, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "vga")),
BERLIN_PINCTRL_GROUP("GAV2", 0x24, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x4, "pdm"),
BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
BERLIN_PINCTRL_GROUP("GAV3", 0x24, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
BERLIN_PINCTRL_GROUP("GAV4", 0x24, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x6, "adac")),
BERLIN_PINCTRL_GROUP("GAV5", 0x24, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "spdif")),
BERLIN_PINCTRL_GROUP("GAV6", 0x24, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s2")),
BERLIN_PINCTRL_GROUP("GAV7", 0x28, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dvio"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s3")),
BERLIN_PINCTRL_GROUP("GAV8", 0x28, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
BERLIN_PINCTRL_GROUP("GAV9", 0x28, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm")),
BERLIN_PINCTRL_GROUP("GAV10", 0x28, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x4, "agc")),
BERLIN_PINCTRL_GROUP("GAV11", 0x28, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "dv0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fp"),
BERLIN_PINCTRL_FUNCTION(0x3, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x5, "vclki")),
BERLIN_PINCTRL_GROUP("GAV12", 0x28, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
BERLIN_PINCTRL_GROUP("GAV13", 0x28, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2")),
BERLIN_PINCTRL_GROUP("GAV14", 0x28, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s1")),
BERLIN_PINCTRL_GROUP("GAV15", 0x28, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
BERLIN_PINCTRL_GROUP("GAV16", 0x28, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x5, "pdm"),
BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
BERLIN_PINCTRL_GROUP("GAV17", 0x2c, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "i2s0"),
BERLIN_PINCTRL_FUNCTION(0x2, "i2s1"),
BERLIN_PINCTRL_FUNCTION(0x3, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x5, "pdm"),
BERLIN_PINCTRL_FUNCTION(0x6, "dac_dbg")),
BERLIN_PINCTRL_GROUP("GAV18", 0x2c, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spdif"),
BERLIN_PINCTRL_FUNCTION(0x2, "arc")),
BERLIN_PINCTRL_GROUP("GAV19", 0x2c, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "avio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spdif"),
BERLIN_PINCTRL_FUNCTION(0x4, "i2s3"),
BERLIN_PINCTRL_FUNCTION(0x5, "pdm")),
};
static const struct berlin_desc_group berlin2q_sysmgr_pinctrl_groups[] = {
/* GSM */
BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "eth1")),
BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n/SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* CLK/SDO */
BERLIN_PINCTRL_FUNCTION(0x2, "eddc")),
BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x1, 0x08,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x1, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x1, 0x0a,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x0d,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")),
BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x0e,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "led")),
BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "led")),
BERLIN_PINCTRL_GROUP("GSM12", 0x40, 0x2, 0x10,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x1, "irda0"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("GSM13", 0x40, 0x2, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "uart0"), /* CTS/RTS */
BERLIN_PINCTRL_FUNCTION(0x2, "uart1"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x3, "twsi2")),
BERLIN_PINCTRL_GROUP("GSM14", 0x40, 0x2, 0x14,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x2, "irda1"),
BERLIN_PINCTRL_FUNCTION(0x3, "twsi3")),
BERLIN_PINCTRL_GROUP("GSM15", 0x40, 0x2, 0x16,
BERLIN_PINCTRL_FUNCTION(0x0, "pwr"),
BERLIN_PINCTRL_FUNCTION(0x1, "led"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("GSM16", 0x40, 0x1, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
BERLIN_PINCTRL_GROUP("GSM17", 0x40, 0x1, 0x19,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
BERLIN_PINCTRL_GROUP("GSM18", 0x40, 0x1, 0x1a,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "eddc")),
};
static const struct berlin_pinctrl_desc berlin2q_soc_pinctrl_data = {
.groups = berlin2q_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2q_soc_pinctrl_groups),
};
static const struct berlin_pinctrl_desc berlin2q_sysmgr_pinctrl_data = {
.groups = berlin2q_sysmgr_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2q_sysmgr_pinctrl_groups),
};
static const struct of_device_id berlin2q_pinctrl_match[] = {
{
.compatible = "marvell,berlin2q-soc-pinctrl",
.data = &berlin2q_soc_pinctrl_data,
},
{
.compatible = "marvell,berlin2q-system-pinctrl",
.data = &berlin2q_sysmgr_pinctrl_data,
},
{}
};
static int berlin2q_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(berlin2q_pinctrl_match, &pdev->dev);
return berlin_pinctrl_probe(pdev, match->data);
}
static struct platform_driver berlin2q_pinctrl_driver = {
.probe = berlin2q_pinctrl_probe,
.driver = {
.name = "berlin-bg2q-pinctrl",
.of_match_table = berlin2q_pinctrl_match,
},
};
builtin_platform_driver(berlin2q_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/berlin/berlin-bg2q.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell Berlin BG2CD pinctrl driver.
*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <[email protected]>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
/* G */
BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x2, "led"),
BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G2", 0x00, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "fe"),
BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G3", 0x00, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"),
BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
BERLIN_PINCTRL_FUNCTION(0x4, "fe"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G4", 0x00, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
BERLIN_PINCTRL_FUNCTION(0x3, "arc"),
BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G6", 0x00, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "eddc"),
BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */
BERLIN_PINCTRL_FUNCTION(0x3, "twsi0")),
BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x1e,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G11", 0x04, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G12", 0x04, 0x3, 0x02,
BERLIN_PINCTRL_FUNCTION(0x0, "usb1"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x05,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"),
BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")),
BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x08,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G15", 0x04, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G18", 0x04, 0x2, 0x12,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G19", 0x04, 0x2, 0x14,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G20", 0x04, 0x2, 0x16,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G23", 0x08, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G24", 0x08, 0x2, 0x03,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G25", 0x08, 0x2, 0x05,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G26", 0x08, 0x1, 0x07,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G27", 0x08, 0x2, 0x08,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G28", 0x08, 0x3, 0x0a,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("G29", 0x08, 0x3, 0x0d,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
};
static const struct berlin_desc_group berlin2cd_sysmgr_pinctrl_groups[] = {
/* GSM */
BERLIN_PINCTRL_GROUP("GSM0", 0x40, 0x2, 0x00,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM1", 0x40, 0x2, 0x02,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM2", 0x40, 0x2, 0x04,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM3", 0x40, 0x2, 0x06,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM4", 0x40, 0x2, 0x08,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM5", 0x40, 0x2, 0x0a,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM6", 0x40, 0x2, 0x0c,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM7", 0x40, 0x1, 0x0e,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM8", 0x40, 0x1, 0x0f,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM9", 0x40, 0x1, 0x10,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM10", 0x40, 0x1, 0x11,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
BERLIN_PINCTRL_GROUP("GSM11", 0x40, 0x1, 0x12,
BERLIN_PINCTRL_FUNCTION_UNKNOWN),
};
static const struct berlin_pinctrl_desc berlin2cd_soc_pinctrl_data = {
.groups = berlin2cd_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2cd_soc_pinctrl_groups),
};
static const struct berlin_pinctrl_desc berlin2cd_sysmgr_pinctrl_data = {
.groups = berlin2cd_sysmgr_pinctrl_groups,
.ngroups = ARRAY_SIZE(berlin2cd_sysmgr_pinctrl_groups),
};
static const struct of_device_id berlin2cd_pinctrl_match[] = {
{
.compatible = "marvell,berlin2cd-soc-pinctrl",
.data = &berlin2cd_soc_pinctrl_data
},
{
.compatible = "marvell,berlin2cd-system-pinctrl",
.data = &berlin2cd_sysmgr_pinctrl_data
},
{}
};
static int berlin2cd_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(berlin2cd_pinctrl_match, &pdev->dev);
return berlin_pinctrl_probe(pdev, match->data);
}
static struct platform_driver berlin2cd_pinctrl_driver = {
.probe = berlin2cd_pinctrl_probe,
.driver = {
.name = "berlin-bg2cd-pinctrl",
.of_match_table = berlin2cd_pinctrl_match,
},
};
builtin_platform_driver(berlin2cd_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/berlin/berlin-bg2cd.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Marvell Berlin SoC pinctrl core driver
*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <[email protected]>
*/
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "berlin.h"
struct berlin_pinctrl {
struct regmap *regmap;
struct device *dev;
const struct berlin_pinctrl_desc *desc;
struct berlin_pinctrl_function *functions;
unsigned nfunctions;
struct pinctrl_dev *pctrl_dev;
};
static int berlin_pinctrl_get_group_count(struct pinctrl_dev *pctrl_dev)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pctrl->desc->ngroups;
}
static const char *berlin_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev,
unsigned group)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pctrl->desc->groups[group].name;
}
static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
struct property *prop;
const char *function_name, *group_name;
unsigned reserved_maps = 0;
int ret, ngroups;
*map = NULL;
*num_maps = 0;
ret = of_property_read_string(node, "function", &function_name);
if (ret) {
dev_err(pctrl->dev,
"missing function property in node %pOFn\n", node);
return -EINVAL;
}
ngroups = of_property_count_strings(node, "groups");
if (ngroups < 0) {
dev_err(pctrl->dev,
"missing groups property in node %pOFn\n", node);
return -EINVAL;
}
ret = pinctrl_utils_reserve_map(pctrl_dev, map, &reserved_maps,
num_maps, ngroups);
if (ret) {
dev_err(pctrl->dev, "can't reserve map: %d\n", ret);
return ret;
}
of_property_for_each_string(node, "groups", prop, group_name) {
ret = pinctrl_utils_add_map_mux(pctrl_dev, map, &reserved_maps,
num_maps, group_name,
function_name);
if (ret) {
dev_err(pctrl->dev, "can't add map: %d\n", ret);
return ret;
}
}
return 0;
}
static const struct pinctrl_ops berlin_pinctrl_ops = {
.get_groups_count = &berlin_pinctrl_get_group_count,
.get_group_name = &berlin_pinctrl_get_group_name,
.dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
.dt_free_map = &pinctrl_utils_free_map,
};
static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pctrl->nfunctions;
}
static const char *berlin_pinmux_get_function_name(struct pinctrl_dev *pctrl_dev,
unsigned function)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
return pctrl->functions[function].name;
}
static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
*groups = pctrl->functions[function].groups;
*num_groups = pctrl->functions[function].ngroups;
return 0;
}
static struct berlin_desc_function *
berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl,
const struct berlin_desc_group *group,
const char *fname)
{
struct berlin_desc_function *function = group->functions;
while (function->name) {
if (!strcmp(function->name, fname))
return function;
function++;
}
return NULL;
}
static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
unsigned function,
unsigned group)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
struct berlin_pinctrl_function *func = pctrl->functions + function;
struct berlin_desc_function *function_desc =
berlin_pinctrl_find_function_by_name(pctrl, group_desc,
func->name);
u32 mask, val;
if (!function_desc)
return -EINVAL;
mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1,
group_desc->lsb);
val = function_desc->muxval << group_desc->lsb;
regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val);
return 0;
}
static const struct pinmux_ops berlin_pinmux_ops = {
.get_functions_count = &berlin_pinmux_get_functions_count,
.get_function_name = &berlin_pinmux_get_function_name,
.get_function_groups = &berlin_pinmux_get_function_groups,
.set_mux = &berlin_pinmux_set,
};
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
const char *name)
{
struct berlin_pinctrl_function *function = pctrl->functions;
while (function->name) {
if (!strcmp(function->name, name)) {
function->ngroups++;
return -EEXIST;
}
function++;
}
function->name = name;
function->ngroups = 1;
pctrl->nfunctions++;
return 0;
}
static int berlin_pinctrl_build_state(struct platform_device *pdev)
{
struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev);
const struct berlin_desc_group *desc_group;
const struct berlin_desc_function *desc_function;
int i, max_functions = 0;
pctrl->nfunctions = 0;
for (i = 0; i < pctrl->desc->ngroups; i++) {
desc_group = pctrl->desc->groups + i;
/* compute the maximum number of functions a group can have */
max_functions += 1 << (desc_group->bit_width + 1);
}
/* we will reallocate later */
pctrl->functions = kcalloc(max_functions,
sizeof(*pctrl->functions), GFP_KERNEL);
if (!pctrl->functions)
return -ENOMEM;
/* register all functions */
for (i = 0; i < pctrl->desc->ngroups; i++) {
desc_group = pctrl->desc->groups + i;
desc_function = desc_group->functions;
while (desc_function->name) {
berlin_pinctrl_add_function(pctrl, desc_function->name);
desc_function++;
}
}
pctrl->functions = krealloc(pctrl->functions,
pctrl->nfunctions * sizeof(*pctrl->functions),
GFP_KERNEL);
if (!pctrl->functions)
return -ENOMEM;
/* map functions to theirs groups */
for (i = 0; i < pctrl->desc->ngroups; i++) {
desc_group = pctrl->desc->groups + i;
desc_function = desc_group->functions;
while (desc_function->name) {
struct berlin_pinctrl_function
*function = pctrl->functions;
const char **groups;
bool found = false;
while (function->name) {
if (!strcmp(desc_function->name, function->name)) {
found = true;
break;
}
function++;
}
if (!found) {
kfree(pctrl->functions);
return -EINVAL;
}
if (!function->groups) {
function->groups =
devm_kcalloc(&pdev->dev,
function->ngroups,
sizeof(char *),
GFP_KERNEL);
if (!function->groups) {
kfree(pctrl->functions);
return -ENOMEM;
}
}
groups = function->groups;
while (*groups)
groups++;
*groups = desc_group->name;
desc_function++;
}
}
return 0;
}
static struct pinctrl_desc berlin_pctrl_desc = {
.name = "berlin-pinctrl",
.pctlops = &berlin_pinctrl_ops,
.pmxops = &berlin_pinmux_ops,
.owner = THIS_MODULE,
};
int berlin_pinctrl_probe_regmap(struct platform_device *pdev,
const struct berlin_pinctrl_desc *desc,
struct regmap *regmap)
{
struct device *dev = &pdev->dev;
struct berlin_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
platform_set_drvdata(pdev, pctrl);
pctrl->regmap = regmap;
pctrl->dev = &pdev->dev;
pctrl->desc = desc;
ret = berlin_pinctrl_build_state(pdev);
if (ret) {
dev_err(dev, "cannot build driver state: %d\n", ret);
return ret;
}
pctrl->pctrl_dev = devm_pinctrl_register(dev, &berlin_pctrl_desc,
pctrl);
if (IS_ERR(pctrl->pctrl_dev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(pctrl->pctrl_dev);
}
return 0;
}
int berlin_pinctrl_probe(struct platform_device *pdev,
const struct berlin_pinctrl_desc *desc)
{
struct device *dev = &pdev->dev;
struct device_node *parent_np = of_get_parent(dev->of_node);
struct regmap *regmap = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return berlin_pinctrl_probe_regmap(pdev, desc, regmap);
}
|
linux-master
|
drivers/pinctrl/berlin/berlin.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Spreadtrum pin controller driver
* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
*/
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinmux.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "pinctrl-sprd.h"
#define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
#define PINCTRL_REG_OFFSET 0x20
#define PINCTRL_REG_MISC_OFFSET 0x4020
#define PINCTRL_REG_LEN 0x4
#define PIN_FUNC_MASK (BIT(4) | BIT(5))
#define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK
#define PIN_FUNC_SEL_2 BIT(4)
#define PIN_FUNC_SEL_3 BIT(5)
#define PIN_FUNC_SEL_4 PIN_FUNC_MASK
#define AP_SLEEP_MODE BIT(13)
#define PUBCP_SLEEP_MODE BIT(14)
#define TGLDSP_SLEEP_MODE BIT(15)
#define AGDSP_SLEEP_MODE BIT(16)
#define CM4_SLEEP_MODE BIT(17)
#define SLEEP_MODE_MASK GENMASK(5, 0)
#define SLEEP_MODE_SHIFT 13
#define SLEEP_INPUT BIT(1)
#define SLEEP_INPUT_MASK 0x1
#define SLEEP_INPUT_SHIFT 1
#define SLEEP_OUTPUT BIT(0)
#define SLEEP_OUTPUT_MASK 0x1
#define SLEEP_OUTPUT_SHIFT 0
#define DRIVE_STRENGTH_MASK GENMASK(3, 0)
#define DRIVE_STRENGTH_SHIFT 19
#define SLEEP_PULL_DOWN BIT(2)
#define SLEEP_PULL_DOWN_MASK 0x1
#define SLEEP_PULL_DOWN_SHIFT 2
#define PULL_DOWN BIT(6)
#define PULL_DOWN_MASK 0x1
#define PULL_DOWN_SHIFT 6
#define SLEEP_PULL_UP BIT(3)
#define SLEEP_PULL_UP_MASK 0x1
#define SLEEP_PULL_UP_SHIFT 3
#define PULL_UP_4_7K (BIT(12) | BIT(7))
#define PULL_UP_20K BIT(7)
#define PULL_UP_MASK 0x21
#define PULL_UP_SHIFT 7
#define INPUT_SCHMITT BIT(11)
#define INPUT_SCHMITT_MASK 0x1
#define INPUT_SCHMITT_SHIFT 11
enum pin_sleep_mode {
AP_SLEEP = BIT(0),
PUBCP_SLEEP = BIT(1),
TGLDSP_SLEEP = BIT(2),
AGDSP_SLEEP = BIT(3),
CM4_SLEEP = BIT(4),
};
enum pin_func_sel {
PIN_FUNC_1,
PIN_FUNC_2,
PIN_FUNC_3,
PIN_FUNC_4,
PIN_FUNC_MAX,
};
/**
* struct sprd_pin: represent one pin's description
* @name: pin name
* @number: pin number
* @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
* @reg: pin register address
* @bit_offset: bit offset in pin register
* @bit_width: bit width in pin register
*/
struct sprd_pin {
const char *name;
unsigned int number;
enum pin_type type;
unsigned long reg;
unsigned long bit_offset;
unsigned long bit_width;
};
/**
* struct sprd_pin_group: represent one group's description
* @name: group name
* @npins: pin numbers of this group
* @pins: pointer to pins array
*/
struct sprd_pin_group {
const char *name;
unsigned int npins;
unsigned int *pins;
};
/**
* struct sprd_pinctrl_soc_info: represent the SoC's pins description
* @groups: pointer to groups of pins
* @ngroups: group numbers of the whole SoC
* @pins: pointer to pins description
* @npins: pin numbers of the whole SoC
* @grp_names: pointer to group names array
*/
struct sprd_pinctrl_soc_info {
struct sprd_pin_group *groups;
unsigned int ngroups;
struct sprd_pin *pins;
unsigned int npins;
const char **grp_names;
};
/**
* struct sprd_pinctrl: represent the pin controller device
* @dev: pointer to the device structure
* @pctl: pointer to the pinctrl handle
* @base: base address of the controller
* @info: pointer to SoC's pins description information
*/
struct sprd_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct sprd_pinctrl_soc_info *info;
};
#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
#define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
const char *name)
{
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
int i;
for (i = 0; i < info->npins; i++) {
if (!strcmp(info->pins[i].name, name))
return info->pins[i].number;
}
return -ENODEV;
}
static struct sprd_pin *
sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
{
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
struct sprd_pin *pin = NULL;
int i;
for (i = 0; i < info->npins; i++) {
if (info->pins[i].number == id) {
pin = &info->pins[i];
break;
}
}
return pin;
}
static const struct sprd_pin_group *
sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
const char *name)
{
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
const struct sprd_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name)) {
grp = &info->groups[i];
break;
}
}
return grp;
}
static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
return info->ngroups;
}
static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
return info->groups[selector].name;
}
static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*npins = info->groups[selector].npins;
return 0;
}
static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct sprd_pin_group *grp;
unsigned long *configs = NULL;
unsigned int num_configs = 0;
unsigned int reserved_maps = 0;
unsigned int reserve = 0;
const char *function;
enum pinctrl_map_type type;
int ret;
grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
if (!grp) {
dev_err(pctl->dev, "unable to find group for node %s\n",
of_node_full_name(np));
return -EINVAL;
}
ret = of_property_count_strings(np, "pins");
if (ret < 0)
return ret;
if (ret == 1)
type = PIN_MAP_TYPE_CONFIGS_PIN;
else
type = PIN_MAP_TYPE_CONFIGS_GROUP;
ret = of_property_read_string(np, "function", &function);
if (ret < 0) {
if (ret != -EINVAL)
dev_err(pctl->dev,
"%s: could not parse property function\n",
of_node_full_name(np));
function = NULL;
}
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(pctl->dev, "%s: could not parse node property\n",
of_node_full_name(np));
return ret;
}
*map = NULL;
*num_maps = 0;
if (function != NULL)
reserve++;
if (num_configs)
reserve++;
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
num_maps, reserve);
if (ret < 0)
goto out;
if (function) {
ret = pinctrl_utils_add_map_mux(pctldev, map,
&reserved_maps, num_maps,
grp->name, function);
if (ret < 0)
goto out;
}
if (num_configs) {
const char *group_or_pin;
unsigned int pin_id;
if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
pin_id = grp->pins[0];
group_or_pin = pin_get_name(pctldev, pin_id);
} else {
group_or_pin = grp->name;
}
ret = pinctrl_utils_add_map_configs(pctldev, map,
&reserved_maps, num_maps,
group_or_pin, configs,
num_configs, type);
}
out:
kfree(configs);
return ret;
}
static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static const struct pinctrl_ops sprd_pctrl_ops = {
.get_groups_count = sprd_pctrl_group_count,
.get_group_name = sprd_pctrl_group_name,
.get_group_pins = sprd_pctrl_group_pins,
.pin_dbg_show = sprd_pctrl_dbg_show,
.dt_node_to_map = sprd_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
{
return PIN_FUNC_MAX;
}
static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
switch (selector) {
case PIN_FUNC_1:
return "func1";
case PIN_FUNC_2:
return "func2";
case PIN_FUNC_3:
return "func3";
case PIN_FUNC_4:
return "func4";
default:
return "null";
}
}
static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
*groups = info->grp_names;
*num_groups = info->ngroups;
return 0;
}
static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int func_selector,
unsigned int group_selector)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
struct sprd_pin_group *grp = &info->groups[group_selector];
unsigned int i, grp_pins = grp->npins;
unsigned long reg;
unsigned int val = 0;
if (group_selector >= info->ngroups)
return -EINVAL;
switch (func_selector) {
case PIN_FUNC_1:
val &= PIN_FUNC_SEL_1;
break;
case PIN_FUNC_2:
val |= PIN_FUNC_SEL_2;
break;
case PIN_FUNC_3:
val |= PIN_FUNC_SEL_3;
break;
case PIN_FUNC_4:
val |= PIN_FUNC_SEL_4;
break;
default:
break;
}
for (i = 0; i < grp_pins; i++) {
unsigned int pin_id = grp->pins[i];
struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
if (!pin || pin->type != COMMON_PIN)
continue;
reg = readl((void __iomem *)pin->reg);
reg &= ~PIN_FUNC_MASK;
reg |= val;
writel(reg, (void __iomem *)pin->reg);
}
return 0;
}
static const struct pinmux_ops sprd_pmx_ops = {
.get_functions_count = sprd_pmx_get_function_count,
.get_function_name = sprd_pmx_get_function_name,
.get_function_groups = sprd_pmx_get_function_groups,
.set_mux = sprd_pmx_set_mux,
};
static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *config)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
unsigned int param = pinconf_to_config_param(*config);
unsigned int reg, arg;
if (!pin)
return -EINVAL;
if (pin->type == GLOBAL_CTRL_PIN) {
reg = (readl((void __iomem *)pin->reg) >>
pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
} else {
reg = readl((void __iomem *)pin->reg);
}
if (pin->type == GLOBAL_CTRL_PIN &&
param == SPRD_PIN_CONFIG_CONTROL) {
arg = reg;
} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
switch (param) {
case SPRD_PIN_CONFIG_SLEEP_MODE:
arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
break;
case PIN_CONFIG_INPUT_ENABLE:
arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
arg = reg & SLEEP_OUTPUT_MASK;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = (reg >> DRIVE_STRENGTH_SHIFT) &
DRIVE_STRENGTH_MASK;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
/* combine sleep pull down and pull down config */
arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
SLEEP_PULL_DOWN_MASK) << 16;
arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
break;
case PIN_CONFIG_BIAS_PULL_UP:
/* combine sleep pull up and pull up config */
arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
SLEEP_PULL_UP_MASK) << 16;
arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
break;
case PIN_CONFIG_BIAS_DISABLE:
if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
(reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
arg = 0;
break;
default:
return -ENOTSUPP;
}
} else {
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static unsigned int sprd_pinconf_drive(unsigned int mA)
{
unsigned int val = 0;
switch (mA) {
case 2:
break;
case 4:
val |= BIT(19);
break;
case 6:
val |= BIT(20);
break;
case 8:
val |= BIT(19) | BIT(20);
break;
case 10:
val |= BIT(21);
break;
case 12:
val |= BIT(21) | BIT(19);
break;
case 14:
val |= BIT(21) | BIT(20);
break;
case 16:
val |= BIT(19) | BIT(20) | BIT(21);
break;
case 20:
val |= BIT(22);
break;
case 21:
val |= BIT(22) | BIT(19);
break;
case 24:
val |= BIT(22) | BIT(20);
break;
case 25:
val |= BIT(22) | BIT(20) | BIT(19);
break;
case 27:
val |= BIT(22) | BIT(21);
break;
case 29:
val |= BIT(22) | BIT(21) | BIT(19);
break;
case 31:
val |= BIT(22) | BIT(21) | BIT(20);
break;
case 33:
val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
break;
default:
break;
}
return val;
}
static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
unsigned int num_configs)
{
unsigned int param;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
return true;
}
return false;
}
static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *configs, unsigned int num_configs)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
bool is_sleep_config;
unsigned long reg;
int i;
if (!pin)
return -EINVAL;
is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
for (i = 0; i < num_configs; i++) {
unsigned int param, arg, shift, mask, val;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
val = 0;
shift = 0;
mask = 0;
if (pin->type == GLOBAL_CTRL_PIN &&
param == SPRD_PIN_CONFIG_CONTROL) {
val = arg;
} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
switch (param) {
case SPRD_PIN_CONFIG_SLEEP_MODE:
if (arg & AP_SLEEP)
val |= AP_SLEEP_MODE;
if (arg & PUBCP_SLEEP)
val |= PUBCP_SLEEP_MODE;
if (arg & TGLDSP_SLEEP)
val |= TGLDSP_SLEEP_MODE;
if (arg & AGDSP_SLEEP)
val |= AGDSP_SLEEP_MODE;
if (arg & CM4_SLEEP)
val |= CM4_SLEEP_MODE;
mask = SLEEP_MODE_MASK;
shift = SLEEP_MODE_SHIFT;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (is_sleep_config == true) {
if (arg > 0)
val |= SLEEP_INPUT;
else
val &= ~SLEEP_INPUT;
mask = SLEEP_INPUT_MASK;
shift = SLEEP_INPUT_SHIFT;
}
break;
case PIN_CONFIG_OUTPUT_ENABLE:
if (is_sleep_config == true) {
if (arg > 0)
val |= SLEEP_OUTPUT;
else
val &= ~SLEEP_OUTPUT;
mask = SLEEP_OUTPUT_MASK;
shift = SLEEP_OUTPUT_SHIFT;
}
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
if (is_sleep_config == true) {
val = shift = 0;
mask = SLEEP_OUTPUT | SLEEP_INPUT;
}
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (arg < 2 || arg > 60)
return -EINVAL;
val = sprd_pinconf_drive(arg);
mask = DRIVE_STRENGTH_MASK;
shift = DRIVE_STRENGTH_SHIFT;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (is_sleep_config == true) {
val |= SLEEP_PULL_DOWN;
mask = SLEEP_PULL_DOWN_MASK;
shift = SLEEP_PULL_DOWN_SHIFT;
} else {
val |= PULL_DOWN;
mask = PULL_DOWN_MASK;
shift = PULL_DOWN_SHIFT;
}
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (arg > 0)
val |= INPUT_SCHMITT;
else
val &= ~INPUT_SCHMITT;
mask = INPUT_SCHMITT_MASK;
shift = INPUT_SCHMITT_SHIFT;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (is_sleep_config) {
val |= SLEEP_PULL_UP;
mask = SLEEP_PULL_UP_MASK;
shift = SLEEP_PULL_UP_SHIFT;
} else {
if (arg == 20000)
val |= PULL_UP_20K;
else if (arg == 4700)
val |= PULL_UP_4_7K;
mask = PULL_UP_MASK;
shift = PULL_UP_SHIFT;
}
break;
case PIN_CONFIG_BIAS_DISABLE:
if (is_sleep_config == true) {
val = shift = 0;
mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
} else {
val = shift = 0;
mask = PULL_DOWN | PULL_UP_20K |
PULL_UP_4_7K;
}
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
continue;
default:
return -ENOTSUPP;
}
} else {
return -ENOTSUPP;
}
if (pin->type == GLOBAL_CTRL_PIN) {
reg = readl((void __iomem *)pin->reg);
reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
<< pin->bit_offset);
reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
<< pin->bit_offset;
writel(reg, (void __iomem *)pin->reg);
} else {
reg = readl((void __iomem *)pin->reg);
reg &= ~(mask << shift);
reg |= val;
writel(reg, (void __iomem *)pin->reg);
}
}
return 0;
}
static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned long *config)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
struct sprd_pin_group *grp;
unsigned int pin_id;
if (selector >= info->ngroups)
return -EINVAL;
grp = &info->groups[selector];
pin_id = grp->pins[0];
return sprd_pinconf_get(pctldev, pin_id, config);
}
static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
struct sprd_pin_group *grp;
int ret, i;
if (selector >= info->ngroups)
return -EINVAL;
grp = &info->groups[selector];
for (i = 0; i < grp->npins; i++) {
unsigned int pin_id = grp->pins[i];
ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
unsigned int pin_id,
unsigned long *config)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
if (!pin)
return -EINVAL;
if (pin->type == GLOBAL_CTRL_PIN) {
*config = (readl((void __iomem *)pin->reg) >>
pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
} else {
*config = readl((void __iomem *)pin->reg);
}
return 0;
}
static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int pin_id)
{
unsigned long config;
int ret;
ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
if (ret)
return;
seq_printf(s, "0x%lx", config);
}
static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int selector)
{
struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sprd_pinctrl_soc_info *info = pctl->info;
struct sprd_pin_group *grp;
unsigned long config;
const char *name;
int i, ret;
if (selector >= info->ngroups)
return;
grp = &info->groups[selector];
seq_putc(s, '\n');
for (i = 0; i < grp->npins; i++, config++) {
unsigned int pin_id = grp->pins[i];
name = pin_get_name(pctldev, pin_id);
ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
if (ret)
return;
seq_printf(s, "%s: 0x%lx ", name, config);
}
}
static const struct pinconf_ops sprd_pinconf_ops = {
.is_generic = true,
.pin_config_get = sprd_pinconf_get,
.pin_config_set = sprd_pinconf_set,
.pin_config_group_get = sprd_pinconf_group_get,
.pin_config_group_set = sprd_pinconf_group_set,
.pin_config_dbg_show = sprd_pinconf_dbg_show,
.pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
};
static const struct pinconf_generic_params sprd_dt_params[] = {
{"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
{"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item sprd_conf_items[] = {
PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
};
#endif
static struct pinctrl_desc sprd_pinctrl_desc = {
.pctlops = &sprd_pctrl_ops,
.pmxops = &sprd_pmx_ops,
.confops = &sprd_pinconf_ops,
.num_custom_params = ARRAY_SIZE(sprd_dt_params),
.custom_params = sprd_dt_params,
#ifdef CONFIG_DEBUG_FS
.custom_conf_items = sprd_conf_items,
#endif
.owner = THIS_MODULE,
};
static int sprd_pinctrl_parse_groups(struct device_node *np,
struct sprd_pinctrl *sprd_pctl,
struct sprd_pin_group *grp)
{
struct property *prop;
const char *pin_name;
int ret, i = 0;
ret = of_property_count_strings(np, "pins");
if (ret < 0)
return ret;
grp->name = np->name;
grp->npins = ret;
grp->pins = devm_kcalloc(sprd_pctl->dev,
grp->npins, sizeof(unsigned int),
GFP_KERNEL);
if (!grp->pins)
return -ENOMEM;
of_property_for_each_string(np, "pins", prop, pin_name) {
ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
if (ret >= 0)
grp->pins[i++] = ret;
}
for (i = 0; i < grp->npins; i++) {
dev_dbg(sprd_pctl->dev,
"Group[%s] contains [%d] pins: id = %d\n",
grp->name, grp->npins, grp->pins[i]);
}
return 0;
}
static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
{
struct device_node *child;
unsigned int group_cnt, cnt;
group_cnt = of_get_child_count(np);
for_each_child_of_node(np, child) {
cnt = of_get_child_count(child);
if (cnt > 0)
group_cnt += cnt;
}
return group_cnt;
}
static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
{
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
struct device_node *np = sprd_pctl->dev->of_node;
struct device_node *child, *sub_child;
struct sprd_pin_group *grp;
const char **temp;
int ret;
if (!np)
return -ENODEV;
info->ngroups = sprd_pinctrl_get_groups(np);
if (!info->ngroups)
return 0;
info->groups = devm_kcalloc(sprd_pctl->dev,
info->ngroups,
sizeof(struct sprd_pin_group),
GFP_KERNEL);
if (!info->groups)
return -ENOMEM;
info->grp_names = devm_kcalloc(sprd_pctl->dev,
info->ngroups, sizeof(char *),
GFP_KERNEL);
if (!info->grp_names)
return -ENOMEM;
temp = info->grp_names;
grp = info->groups;
for_each_child_of_node(np, child) {
ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
if (ret) {
of_node_put(child);
return ret;
}
*temp++ = grp->name;
grp++;
if (of_get_child_count(child) > 0) {
for_each_child_of_node(child, sub_child) {
ret = sprd_pinctrl_parse_groups(sub_child,
sprd_pctl, grp);
if (ret) {
of_node_put(sub_child);
of_node_put(child);
return ret;
}
*temp++ = grp->name;
grp++;
}
}
}
return 0;
}
static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
struct sprd_pins_info *sprd_soc_pin_info,
int pins_cnt)
{
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
unsigned int ctrl_pin = 0, com_pin = 0;
struct sprd_pin *pin;
int i;
info->npins = pins_cnt;
info->pins = devm_kcalloc(sprd_pctl->dev,
info->npins, sizeof(struct sprd_pin),
GFP_KERNEL);
if (!info->pins)
return -ENOMEM;
for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
unsigned int reg;
pin->name = sprd_soc_pin_info[i].name;
pin->type = sprd_soc_pin_info[i].type;
pin->number = sprd_soc_pin_info[i].num;
reg = sprd_soc_pin_info[i].reg;
if (pin->type == GLOBAL_CTRL_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
PINCTRL_REG_LEN * reg;
pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
pin->bit_width = sprd_soc_pin_info[i].bit_width;
ctrl_pin++;
} else if (pin->type == COMMON_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
(i - ctrl_pin);
com_pin++;
} else if (pin->type == MISC_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
(i - ctrl_pin - com_pin);
}
}
for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
"bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
pin->name, pin->number, pin->type,
pin->bit_offset, pin->bit_width, pin->reg);
}
return 0;
}
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
int pins_cnt)
{
struct sprd_pinctrl *sprd_pctl;
struct sprd_pinctrl_soc_info *pinctrl_info;
struct pinctrl_pin_desc *pin_desc;
int ret, i;
sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
GFP_KERNEL);
if (!sprd_pctl)
return -ENOMEM;
sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sprd_pctl->base))
return PTR_ERR(sprd_pctl->base);
pinctrl_info = devm_kzalloc(&pdev->dev,
sizeof(struct sprd_pinctrl_soc_info),
GFP_KERNEL);
if (!pinctrl_info)
return -ENOMEM;
sprd_pctl->info = pinctrl_info;
sprd_pctl->dev = &pdev->dev;
platform_set_drvdata(pdev, sprd_pctl);
ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
if (ret) {
dev_err(&pdev->dev, "fail to add pins information\n");
return ret;
}
ret = sprd_pinctrl_parse_dt(sprd_pctl);
if (ret) {
dev_err(&pdev->dev, "fail to parse dt properties\n");
return ret;
}
pin_desc = devm_kcalloc(&pdev->dev,
pinctrl_info->npins,
sizeof(struct pinctrl_pin_desc),
GFP_KERNEL);
if (!pin_desc)
return -ENOMEM;
for (i = 0; i < pinctrl_info->npins; i++) {
pin_desc[i].number = pinctrl_info->pins[i].number;
pin_desc[i].name = pinctrl_info->pins[i].name;
pin_desc[i].drv_data = pinctrl_info;
}
sprd_pinctrl_desc.pins = pin_desc;
sprd_pinctrl_desc.name = dev_name(&pdev->dev);
sprd_pinctrl_desc.npins = pinctrl_info->npins;
sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
&pdev->dev, (void *)sprd_pctl);
if (IS_ERR(sprd_pctl->pctl)) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
return PTR_ERR(sprd_pctl->pctl);
}
return 0;
}
EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
int sprd_pinctrl_remove(struct platform_device *pdev)
{
struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
pinctrl_unregister(sprd_pctl->pctl);
return 0;
}
EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
void sprd_pinctrl_shutdown(struct platform_device *pdev)
{
struct pinctrl *pinctl;
struct pinctrl_state *state;
pinctl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(pinctl))
return;
state = pinctrl_lookup_state(pinctl, "shutdown");
if (IS_ERR(state))
return;
pinctrl_select_state(pinctl, state);
}
EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
MODULE_AUTHOR("Baolin Wang <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/sprd/pinctrl-sprd.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Spreadtrum pin controller driver
* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-sprd.h"
enum sprd_sc9860_pins {
/* pin global control register 0 */
SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0),
SC9860_VIO_SD2_IRTE = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 10, 1, 0),
SC9860_VIO_SD0_IRTE = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 9, 1, 0),
SC9860_VIO_SIM2_IRTE = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 8, 1, 0),
SC9860_VIO_SIM1_IRTE = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 7, 1, 0),
SC9860_VIO_SIM0_IRTE = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 6, 1, 0),
SC9860_VIO28_0_MS = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 5, 1, 0),
SC9860_VIO_SD2_MS = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 4, 1, 0),
SC9860_VIO_SD0_MS = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 3, 1, 0),
SC9860_VIO_SIM2_MS = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 2, 1, 0),
SC9860_VIO_SIM1_MS = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 1, 1, 0),
SC9860_VIO_SIM0_MS = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 0, 1, 0),
/* pin global control register 2 */
SC9860_SPSPI_PIN_IN_SEL = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 31, 1, 2),
SC9860_UART1_USB30_PHY_SEL = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 30, 1, 2),
SC9860_USB30_PHY_DM_OE = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 29, 1, 2),
SC9860_USB30_PHY_DP_OE = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 28, 1, 2),
SC9860_UART5_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 25, 3, 2),
SC9860_ORP_URXD_PIN_IN_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 24, 1, 2),
SC9860_SIM2_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 23, 1, 2),
SC9860_SIM1_SYS_SEL = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 22, 1, 2),
SC9860_SIM0_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 21, 1, 2),
SC9860_CLK26MHZ_BUF_OUT_SEL = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 20, 1, 2),
SC9860_UART4_SYS_SEL = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 16, 3, 2),
SC9860_UART3_SYS_SEL = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 13, 3, 2),
SC9860_UART2_SYS_SEL = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 10, 3, 2),
SC9860_UART1_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 7, 3, 2),
SC9860_UART0_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 4, 3, 2),
SC9860_UART24_LOOP_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 3, 1, 2),
SC9860_UART23_LOOP_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 2, 1, 2),
SC9860_UART14_LOOP_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 1, 1, 2),
SC9860_UART13_LOOP_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 0, 1, 2),
/* pin global control register 3 */
SC9860_IIS3_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 18, 4, 3),
SC9860_IIS2_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 14, 4, 3),
SC9860_IIS1_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 10, 4, 3),
SC9860_IIS0_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 6, 4, 3),
SC9860_IIS23_LOOP_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 5, 1, 3),
SC9860_IIS13_LOOP_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 4, 1, 3),
SC9860_IIS12_LOOP_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 3, 1, 3),
SC9860_IIS03_LOOP_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 2, 1, 3),
SC9860_IIS02_LOOP_SEL = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 1, 1, 3),
SC9860_IIS01_LOOP_SEL = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 0, 1, 3),
/* pin global control register 4 */
SC9860_IIS6_SYS_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 27, 4, 4),
SC9860_IIS5_SYS_SEL = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 23, 4, 4),
SC9860_IIS4_SYS_SEL = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 19, 4, 4),
SC9860_I2C_INF6_SYS_SEL = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 8, 2, 4),
SC9860_I2C_INF4_SYS_SEL = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 6, 2, 4),
SC9860_I2C_INF2_SYS_SEL = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 4, 2, 4),
SC9860_I2C_INF1_SYS_SEL = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 2, 2, 4),
SC9860_I2C_INF0_SYS_SEL = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 0, 2, 4),
/* pin global control register 5 */
SC9860_GPIO_INF7_SYS_SEL = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 27, 1, 5),
SC9860_GPIO_INF6_SYS_SEL = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 26, 1, 5),
SC9860_GPIO_INF5_SYS_SEL = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 25, 1, 5),
SC9860_GPIO_INF4_SYS_SEL = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 24, 1, 5),
SC9860_GPIO_INF3_SYS_SEL = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 23, 1, 5),
SC9860_GPIO_INF2_SYS_SEL = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 22, 1, 5),
SC9860_GPIO_INF1_SYS_SEL = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 21, 1, 5),
SC9860_GPIO_INF0_SYS_SEL = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 20, 1, 5),
SC9860_WDRST_OUT_SEL = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 16, 3, 5),
SC9860_ADI_SYNC_PIN_OUT_SEL = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 14, 1, 5),
SC9860_CMRST_SEL = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 13, 1, 5),
SC9860_CMPD_SEL = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 12, 1, 5),
SC9860_TEST_DBG_MODE11 = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 11, 1, 5),
SC9860_TEST_DBG_MODE10 = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 10, 1, 5),
SC9860_TEST_DBG_MODE9 = SPRD_PIN_INFO(63, GLOBAL_CTRL_PIN, 9, 1, 5),
SC9860_TEST_DBG_MODE8 = SPRD_PIN_INFO(64, GLOBAL_CTRL_PIN, 8, 1, 5),
SC9860_TEST_DBG_MODE7 = SPRD_PIN_INFO(65, GLOBAL_CTRL_PIN, 7, 1, 5),
SC9860_TEST_DBG_MODE6 = SPRD_PIN_INFO(66, GLOBAL_CTRL_PIN, 6, 1, 5),
SC9860_TEST_DBG_MODE5 = SPRD_PIN_INFO(67, GLOBAL_CTRL_PIN, 5, 1, 5),
SC9860_TEST_DBG_MODE4 = SPRD_PIN_INFO(68, GLOBAL_CTRL_PIN, 4, 1, 5),
SC9860_TEST_DBG_MODE3 = SPRD_PIN_INFO(69, GLOBAL_CTRL_PIN, 3, 1, 5),
SC9860_TEST_DBG_MODE2 = SPRD_PIN_INFO(70, GLOBAL_CTRL_PIN, 2, 1, 5),
SC9860_TEST_DBG_MODE1 = SPRD_PIN_INFO(71, GLOBAL_CTRL_PIN, 1, 1, 5),
SC9860_TEST_DBG_MODE0 = SPRD_PIN_INFO(72, GLOBAL_CTRL_PIN, 0, 1, 5),
/* pin global control register 6 */
SC9860_SP_EIC_DPAD3_SEL = SPRD_PIN_INFO(73, GLOBAL_CTRL_PIN, 24, 8, 6),
SC9860_SP_EIC_DPAD2_SEL = SPRD_PIN_INFO(74, GLOBAL_CTRL_PIN, 16, 8, 6),
SC9860_SP_EIC_DPAD1_SEL = SPRD_PIN_INFO(75, GLOBAL_CTRL_PIN, 8, 8, 6),
SC9860_SP_EIC_DPAD0_SEL = SPRD_PIN_INFO(76, GLOBAL_CTRL_PIN, 0, 8, 6),
/* pin global control register 7 */
SC9860_SP_EIC_DPAD7_SEL = SPRD_PIN_INFO(77, GLOBAL_CTRL_PIN, 24, 8, 7),
SC9860_SP_EIC_DPAD6_SEL = SPRD_PIN_INFO(78, GLOBAL_CTRL_PIN, 16, 8, 7),
SC9860_SP_EIC_DPAD5_SEL = SPRD_PIN_INFO(79, GLOBAL_CTRL_PIN, 8, 8, 7),
SC9860_SP_EIC_DPAD4_SEL = SPRD_PIN_INFO(80, GLOBAL_CTRL_PIN, 0, 8, 7),
/* common pin registers definitions */
SC9860_RFCTL20 = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL21 = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL30 = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL31 = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL32 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL33 = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL34 = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL35 = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL36 = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL37 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL22 = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL23 = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL24 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL25 = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL26 = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL27 = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL28 = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL29 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
SC9860_SCL2 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
SC9860_SDA2 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
SC9860_MTCK_ARM = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
SC9860_MTMS_ARM = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
SC9860_XTL_EN0 = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
SC9860_PTEST = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DAD1 = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
SC9860_AUD_ADD0 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
SC9860_AUD_ADSYNC = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
SC9860_AUD_SCLK = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
SC9860_CHIP_SLEEP = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
SC9860_CLK_32K = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
SC9860_DCDC_ARM_EN = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
SC9860_EXT_RST_B = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
SC9860_ADI_D = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
SC9860_ADI_SCLK = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
SC9860_XTL_EN1 = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
SC9860_ANA_INT = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DAD0 = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DASYNC = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
SC9860_LCM_RSTN = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
SC9860_DSI_TE = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
SC9860_PWMA = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT0 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT1 = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
SC9860_SDA1 = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
SC9860_SCL1 = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK2 = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA2 = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST2 = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK1 = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA1 = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST1 = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK0 = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA0 = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST0 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
SC9860_SD2_CMD = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D0 = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D1 = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
SC9860_SD2_CLK = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D2 = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D3 = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D3 = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D2 = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
SC9860_SD0_CMD = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D0 = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D1 = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
SC9860_SD0_CLK = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CMD_reserved = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CMD = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D6 = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D7 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CLK = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D5 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D4 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_DS = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D3_reserved = SPRD_PIN_INFO(229, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D3 = SPRD_PIN_INFO(231, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_RST = SPRD_PIN_INFO(233, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D1 = SPRD_PIN_INFO(235, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D2 = SPRD_PIN_INFO(237, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D0 = SPRD_PIN_INFO(239, COMMON_PIN, 0, 0, 0),
SC9860_IIS0DI = SPRD_PIN_INFO(241, COMMON_PIN, 0, 0, 0),
SC9860_IIS0DO = SPRD_PIN_INFO(243, COMMON_PIN, 0, 0, 0),
SC9860_IIS0CLK = SPRD_PIN_INFO(245, COMMON_PIN, 0, 0, 0),
SC9860_IIS0LRCK = SPRD_PIN_INFO(247, COMMON_PIN, 0, 0, 0),
SC9860_SD1_CLK = SPRD_PIN_INFO(249, COMMON_PIN, 0, 0, 0),
SC9860_SD1_CMD = SPRD_PIN_INFO(251, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D0 = SPRD_PIN_INFO(253, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D1 = SPRD_PIN_INFO(255, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D2 = SPRD_PIN_INFO(257, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D3 = SPRD_PIN_INFO(259, COMMON_PIN, 0, 0, 0),
SC9860_CLK_AUX0 = SPRD_PIN_INFO(261, COMMON_PIN, 0, 0, 0),
SC9860_WIFI_COEXIST = SPRD_PIN_INFO(263, COMMON_PIN, 0, 0, 0),
SC9860_BEIDOU_COEXIST = SPRD_PIN_INFO(265, COMMON_PIN, 0, 0, 0),
SC9860_U3TXD = SPRD_PIN_INFO(267, COMMON_PIN, 0, 0, 0),
SC9860_U3RXD = SPRD_PIN_INFO(269, COMMON_PIN, 0, 0, 0),
SC9860_U3CTS = SPRD_PIN_INFO(271, COMMON_PIN, 0, 0, 0),
SC9860_U3RTS = SPRD_PIN_INFO(273, COMMON_PIN, 0, 0, 0),
SC9860_U0TXD = SPRD_PIN_INFO(275, COMMON_PIN, 0, 0, 0),
SC9860_U0RXD = SPRD_PIN_INFO(277, COMMON_PIN, 0, 0, 0),
SC9860_U0CTS = SPRD_PIN_INFO(279, COMMON_PIN, 0, 0, 0),
SC9860_U0RTS = SPRD_PIN_INFO(281, COMMON_PIN, 0, 0, 0),
SC9860_IIS1DI = SPRD_PIN_INFO(283, COMMON_PIN, 0, 0, 0),
SC9860_IIS1DO = SPRD_PIN_INFO(285, COMMON_PIN, 0, 0, 0),
SC9860_IIS1CLK = SPRD_PIN_INFO(287, COMMON_PIN, 0, 0, 0),
SC9860_IIS1LRCK = SPRD_PIN_INFO(289, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_CSN = SPRD_PIN_INFO(291, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_DO = SPRD_PIN_INFO(293, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_DI = SPRD_PIN_INFO(295, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_CLK = SPRD_PIN_INFO(297, COMMON_PIN, 0, 0, 0),
SC9860_U2TXD = SPRD_PIN_INFO(299, COMMON_PIN, 0, 0, 0),
SC9860_U2RXD = SPRD_PIN_INFO(301, COMMON_PIN, 0, 0, 0),
SC9860_U4TXD = SPRD_PIN_INFO(303, COMMON_PIN, 0, 0, 0),
SC9860_U4RXD = SPRD_PIN_INFO(305, COMMON_PIN, 0, 0, 0),
SC9860_CMMCLK1 = SPRD_PIN_INFO(307, COMMON_PIN, 0, 0, 0),
SC9860_CMRST1 = SPRD_PIN_INFO(309, COMMON_PIN, 0, 0, 0),
SC9860_CMMCLK0 = SPRD_PIN_INFO(311, COMMON_PIN, 0, 0, 0),
SC9860_CMRST0 = SPRD_PIN_INFO(313, COMMON_PIN, 0, 0, 0),
SC9860_CMPD0 = SPRD_PIN_INFO(315, COMMON_PIN, 0, 0, 0),
SC9860_CMPD1 = SPRD_PIN_INFO(317, COMMON_PIN, 0, 0, 0),
SC9860_SCL0 = SPRD_PIN_INFO(319, COMMON_PIN, 0, 0, 0),
SC9860_SDA0 = SPRD_PIN_INFO(321, COMMON_PIN, 0, 0, 0),
SC9860_SDA6 = SPRD_PIN_INFO(323, COMMON_PIN, 0, 0, 0),
SC9860_SCL6 = SPRD_PIN_INFO(325, COMMON_PIN, 0, 0, 0),
SC9860_U1TXD = SPRD_PIN_INFO(327, COMMON_PIN, 0, 0, 0),
SC9860_U1RXD = SPRD_PIN_INFO(329, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT0 = SPRD_PIN_INFO(331, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT1 = SPRD_PIN_INFO(333, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT2 = SPRD_PIN_INFO(335, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN0 = SPRD_PIN_INFO(337, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN1 = SPRD_PIN_INFO(339, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN2 = SPRD_PIN_INFO(341, COMMON_PIN, 0, 0, 0),
SC9860_IIS3DI = SPRD_PIN_INFO(343, COMMON_PIN, 0, 0, 0),
SC9860_IIS3DO = SPRD_PIN_INFO(345, COMMON_PIN, 0, 0, 0),
SC9860_IIS3CLK = SPRD_PIN_INFO(347, COMMON_PIN, 0, 0, 0),
SC9860_IIS3LRCK = SPRD_PIN_INFO(349, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL0 = SPRD_PIN_INFO(351, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL1 = SPRD_PIN_INFO(353, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL10 = SPRD_PIN_INFO(355, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL11 = SPRD_PIN_INFO(357, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL12 = SPRD_PIN_INFO(359, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL13 = SPRD_PIN_INFO(361, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL14 = SPRD_PIN_INFO(363, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL15 = SPRD_PIN_INFO(365, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL16 = SPRD_PIN_INFO(367, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL17 = SPRD_PIN_INFO(369, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL18 = SPRD_PIN_INFO(371, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL19 = SPRD_PIN_INFO(373, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL2 = SPRD_PIN_INFO(375, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT5 = SPRD_PIN_INFO(377, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT6 = SPRD_PIN_INFO(379, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT7 = SPRD_PIN_INFO(381, COMMON_PIN, 0, 0, 0),
SC9860_GPIO30 = SPRD_PIN_INFO(383, COMMON_PIN, 0, 0, 0),
SC9860_GPIO31 = SPRD_PIN_INFO(385, COMMON_PIN, 0, 0, 0),
SC9860_GPIO32 = SPRD_PIN_INFO(387, COMMON_PIN, 0, 0, 0),
SC9860_GPIO33 = SPRD_PIN_INFO(389, COMMON_PIN, 0, 0, 0),
SC9860_GPIO34 = SPRD_PIN_INFO(391, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL3 = SPRD_PIN_INFO(393, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL4 = SPRD_PIN_INFO(395, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL5 = SPRD_PIN_INFO(397, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL6 = SPRD_PIN_INFO(399, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL7 = SPRD_PIN_INFO(401, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL8 = SPRD_PIN_INFO(403, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL9 = SPRD_PIN_INFO(405, COMMON_PIN, 0, 0, 0),
SC9860_RFFE0_SCK0 = SPRD_PIN_INFO(407, COMMON_PIN, 0, 0, 0),
SC9860_GPIO38 = SPRD_PIN_INFO(409, COMMON_PIN, 0, 0, 0),
SC9860_RFFE0_SDA0 = SPRD_PIN_INFO(411, COMMON_PIN, 0, 0, 0),
SC9860_GPIO39 = SPRD_PIN_INFO(413, COMMON_PIN, 0, 0, 0),
SC9860_RFFE1_SCK0 = SPRD_PIN_INFO(415, COMMON_PIN, 0, 0, 0),
SC9860_GPIO181 = SPRD_PIN_INFO(417, COMMON_PIN, 0, 0, 0),
SC9860_RFFE1_SDA0 = SPRD_PIN_INFO(419, COMMON_PIN, 0, 0, 0),
SC9860_GPIO182 = SPRD_PIN_INFO(421, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS0_ADC_ON = SPRD_PIN_INFO(423, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS0_DAC_ON = SPRD_PIN_INFO(425, COMMON_PIN, 0, 0, 0),
SC9860_RFSCK0 = SPRD_PIN_INFO(427, COMMON_PIN, 0, 0, 0),
SC9860_RFSDA0 = SPRD_PIN_INFO(429, COMMON_PIN, 0, 0, 0),
SC9860_RFSEN0 = SPRD_PIN_INFO(431, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS1_ADC_ON = SPRD_PIN_INFO(433, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS1_DAC_ON = SPRD_PIN_INFO(435, COMMON_PIN, 0, 0, 0),
SC9860_RFSCK1 = SPRD_PIN_INFO(437, COMMON_PIN, 0, 0, 0),
SC9860_RFSDA1 = SPRD_PIN_INFO(439, COMMON_PIN, 0, 0, 0),
SC9860_RFSEN1 = SPRD_PIN_INFO(441, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL38 = SPRD_PIN_INFO(443, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL39 = SPRD_PIN_INFO(445, COMMON_PIN, 0, 0, 0),
/* MSIC pin registers definitions */
SC9860_RFCTL20_MISC = SPRD_PIN_INFO(82, MISC_PIN, 0, 0, 0),
SC9860_RFCTL21_MISC = SPRD_PIN_INFO(84, MISC_PIN, 0, 0, 0),
SC9860_RFCTL30_MISC = SPRD_PIN_INFO(86, MISC_PIN, 0, 0, 0),
SC9860_RFCTL31_MISC = SPRD_PIN_INFO(88, MISC_PIN, 0, 0, 0),
SC9860_RFCTL32_MISC = SPRD_PIN_INFO(90, MISC_PIN, 0, 0, 0),
SC9860_RFCTL33_MISC = SPRD_PIN_INFO(92, MISC_PIN, 0, 0, 0),
SC9860_RFCTL34_MISC = SPRD_PIN_INFO(94, MISC_PIN, 0, 0, 0),
SC9860_RFCTL35_MISC = SPRD_PIN_INFO(96, MISC_PIN, 0, 0, 0),
SC9860_RFCTL36_MISC = SPRD_PIN_INFO(98, MISC_PIN, 0, 0, 0),
SC9860_RFCTL37_MISC = SPRD_PIN_INFO(100, MISC_PIN, 0, 0, 0),
SC9860_RFCTL22_MISC = SPRD_PIN_INFO(102, MISC_PIN, 0, 0, 0),
SC9860_RFCTL23_MISC = SPRD_PIN_INFO(104, MISC_PIN, 0, 0, 0),
SC9860_RFCTL24_MISC = SPRD_PIN_INFO(106, MISC_PIN, 0, 0, 0),
SC9860_RFCTL25_MISC = SPRD_PIN_INFO(108, MISC_PIN, 0, 0, 0),
SC9860_RFCTL26_MISC = SPRD_PIN_INFO(110, MISC_PIN, 0, 0, 0),
SC9860_RFCTL27_MISC = SPRD_PIN_INFO(112, MISC_PIN, 0, 0, 0),
SC9860_RFCTL28_MISC = SPRD_PIN_INFO(114, MISC_PIN, 0, 0, 0),
SC9860_RFCTL29_MISC = SPRD_PIN_INFO(116, MISC_PIN, 0, 0, 0),
SC9860_SCL2_MISC = SPRD_PIN_INFO(118, MISC_PIN, 0, 0, 0),
SC9860_SDA2_MISC = SPRD_PIN_INFO(120, MISC_PIN, 0, 0, 0),
SC9860_MTCK_ARM_MISC = SPRD_PIN_INFO(122, MISC_PIN, 0, 0, 0),
SC9860_MTMS_ARM_MISC = SPRD_PIN_INFO(124, MISC_PIN, 0, 0, 0),
SC9860_XTL_EN0_MISC = SPRD_PIN_INFO(126, MISC_PIN, 0, 0, 0),
SC9860_PTEST_MISC = SPRD_PIN_INFO(128, MISC_PIN, 0, 0, 0),
SC9860_AUD_DAD1_MISC = SPRD_PIN_INFO(130, MISC_PIN, 0, 0, 0),
SC9860_AUD_ADD0_MISC = SPRD_PIN_INFO(132, MISC_PIN, 0, 0, 0),
SC9860_AUD_ADSYNC_MISC = SPRD_PIN_INFO(134, MISC_PIN, 0, 0, 0),
SC9860_AUD_SCLK_MISC = SPRD_PIN_INFO(136, MISC_PIN, 0, 0, 0),
SC9860_CHIP_SLEEP_MISC = SPRD_PIN_INFO(138, MISC_PIN, 0, 0, 0),
SC9860_CLK_32K_MISC = SPRD_PIN_INFO(140, MISC_PIN, 0, 0, 0),
SC9860_DCDC_ARM_EN_MISC = SPRD_PIN_INFO(142, MISC_PIN, 0, 0, 0),
SC9860_EXT_RST_B_MISC = SPRD_PIN_INFO(144, MISC_PIN, 0, 0, 0),
SC9860_ADI_D_MISC = SPRD_PIN_INFO(146, MISC_PIN, 0, 0, 0),
SC9860_ADI_SCLK_MISC = SPRD_PIN_INFO(148, MISC_PIN, 0, 0, 0),
SC9860_XTL_EN1_MISC = SPRD_PIN_INFO(150, MISC_PIN, 0, 0, 0),
SC9860_ANA_INT_MISC = SPRD_PIN_INFO(152, MISC_PIN, 0, 0, 0),
SC9860_AUD_DAD0_MISC = SPRD_PIN_INFO(154, MISC_PIN, 0, 0, 0),
SC9860_AUD_DASYNC_MISC = SPRD_PIN_INFO(156, MISC_PIN, 0, 0, 0),
SC9860_LCM_RSTN_MISC = SPRD_PIN_INFO(158, MISC_PIN, 0, 0, 0),
SC9860_DSI_TE_MISC = SPRD_PIN_INFO(160, MISC_PIN, 0, 0, 0),
SC9860_PWMA_MISC = SPRD_PIN_INFO(162, MISC_PIN, 0, 0, 0),
SC9860_EXTINT0_MISC = SPRD_PIN_INFO(164, MISC_PIN, 0, 0, 0),
SC9860_EXTINT1_MISC = SPRD_PIN_INFO(166, MISC_PIN, 0, 0, 0),
SC9860_SDA1_MISC = SPRD_PIN_INFO(168, MISC_PIN, 0, 0, 0),
SC9860_SCL1_MISC = SPRD_PIN_INFO(170, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK2_MISC = SPRD_PIN_INFO(172, MISC_PIN, 0, 0, 0),
SC9860_SIMDA2_MISC = SPRD_PIN_INFO(174, MISC_PIN, 0, 0, 0),
SC9860_SIMRST2_MISC = SPRD_PIN_INFO(176, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK1_MISC = SPRD_PIN_INFO(178, MISC_PIN, 0, 0, 0),
SC9860_SIMDA1_MISC = SPRD_PIN_INFO(180, MISC_PIN, 0, 0, 0),
SC9860_SIMRST1_MISC = SPRD_PIN_INFO(182, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK0_MISC = SPRD_PIN_INFO(184, MISC_PIN, 0, 0, 0),
SC9860_SIMDA0_MISC = SPRD_PIN_INFO(186, MISC_PIN, 0, 0, 0),
SC9860_SIMRST0_MISC = SPRD_PIN_INFO(188, MISC_PIN, 0, 0, 0),
SC9860_SD2_CMD_MISC = SPRD_PIN_INFO(190, MISC_PIN, 0, 0, 0),
SC9860_SD2_D0_MISC = SPRD_PIN_INFO(192, MISC_PIN, 0, 0, 0),
SC9860_SD2_D1_MISC = SPRD_PIN_INFO(194, MISC_PIN, 0, 0, 0),
SC9860_SD2_CLK_MISC = SPRD_PIN_INFO(196, MISC_PIN, 0, 0, 0),
SC9860_SD2_D2_MISC = SPRD_PIN_INFO(198, MISC_PIN, 0, 0, 0),
SC9860_SD2_D3_MISC = SPRD_PIN_INFO(200, MISC_PIN, 0, 0, 0),
SC9860_SD0_D3_MISC = SPRD_PIN_INFO(202, MISC_PIN, 0, 0, 0),
SC9860_SD0_D2_MISC = SPRD_PIN_INFO(204, MISC_PIN, 0, 0, 0),
SC9860_SD0_CMD_MISC = SPRD_PIN_INFO(206, MISC_PIN, 0, 0, 0),
SC9860_SD0_D0_MISC = SPRD_PIN_INFO(208, MISC_PIN, 0, 0, 0),
SC9860_SD0_D1_MISC = SPRD_PIN_INFO(210, MISC_PIN, 0, 0, 0),
SC9860_SD0_CLK_MISC = SPRD_PIN_INFO(212, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CMD_reserved_MISC = SPRD_PIN_INFO(214, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CMD_MISC = SPRD_PIN_INFO(216, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D6_MISC = SPRD_PIN_INFO(218, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D7_MISC = SPRD_PIN_INFO(220, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CLK_MISC = SPRD_PIN_INFO(222, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D5_MISC = SPRD_PIN_INFO(224, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D4_MISC = SPRD_PIN_INFO(226, MISC_PIN, 0, 0, 0),
SC9860_EMMC_DS_MISC = SPRD_PIN_INFO(228, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D3_reserved_MISC = SPRD_PIN_INFO(230, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D3_MISC = SPRD_PIN_INFO(232, MISC_PIN, 0, 0, 0),
SC9860_EMMC_RST_MISC = SPRD_PIN_INFO(234, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D1_MISC = SPRD_PIN_INFO(236, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D2_MISC = SPRD_PIN_INFO(238, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D0_MISC = SPRD_PIN_INFO(240, MISC_PIN, 0, 0, 0),
SC9860_IIS0DI_MISC = SPRD_PIN_INFO(242, MISC_PIN, 0, 0, 0),
SC9860_IIS0DO_MISC = SPRD_PIN_INFO(244, MISC_PIN, 0, 0, 0),
SC9860_IIS0CLK_MISC = SPRD_PIN_INFO(246, MISC_PIN, 0, 0, 0),
SC9860_IIS0LRCK_MISC = SPRD_PIN_INFO(248, MISC_PIN, 0, 0, 0),
SC9860_SD1_CLK_MISC = SPRD_PIN_INFO(250, MISC_PIN, 0, 0, 0),
SC9860_SD1_CMD_MISC = SPRD_PIN_INFO(252, MISC_PIN, 0, 0, 0),
SC9860_SD1_D0_MISC = SPRD_PIN_INFO(254, MISC_PIN, 0, 0, 0),
SC9860_SD1_D1_MISC = SPRD_PIN_INFO(256, MISC_PIN, 0, 0, 0),
SC9860_SD1_D2_MISC = SPRD_PIN_INFO(258, MISC_PIN, 0, 0, 0),
SC9860_SD1_D3_MISC = SPRD_PIN_INFO(260, MISC_PIN, 0, 0, 0),
SC9860_CLK_AUX0_MISC = SPRD_PIN_INFO(262, MISC_PIN, 0, 0, 0),
SC9860_WIFI_COEXIST_MISC = SPRD_PIN_INFO(264, MISC_PIN, 0, 0, 0),
SC9860_BEIDOU_COEXIST_MISC = SPRD_PIN_INFO(266, MISC_PIN, 0, 0, 0),
SC9860_U3TXD_MISC = SPRD_PIN_INFO(268, MISC_PIN, 0, 0, 0),
SC9860_U3RXD_MISC = SPRD_PIN_INFO(270, MISC_PIN, 0, 0, 0),
SC9860_U3CTS_MISC = SPRD_PIN_INFO(272, MISC_PIN, 0, 0, 0),
SC9860_U3RTS_MISC = SPRD_PIN_INFO(274, MISC_PIN, 0, 0, 0),
SC9860_U0TXD_MISC = SPRD_PIN_INFO(276, MISC_PIN, 0, 0, 0),
SC9860_U0RXD_MISC = SPRD_PIN_INFO(278, MISC_PIN, 0, 0, 0),
SC9860_U0CTS_MISC = SPRD_PIN_INFO(280, MISC_PIN, 0, 0, 0),
SC9860_U0RTS_MISC = SPRD_PIN_INFO(282, MISC_PIN, 0, 0, 0),
SC9860_IIS1DI_MISC = SPRD_PIN_INFO(284, MISC_PIN, 0, 0, 0),
SC9860_IIS1DO_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
SC9860_IIS1CLK_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
SC9860_IIS1LRCK_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
SC9860_SPI0_CSN_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
SC9860_SPI0_DO_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
SC9860_SPI0_DI_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
SC9860_SPI0_CLK_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
SC9860_U2TXD_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
SC9860_U2RXD_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
SC9860_U4TXD_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
SC9860_U4RXD_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
SC9860_CMMCLK1_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
SC9860_CMRST1_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
SC9860_CMMCLK0_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
SC9860_CMRST0_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
SC9860_CMPD0_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
SC9860_CMPD1_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
SC9860_SCL0_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
SC9860_SDA0_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
SC9860_SDA6_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
SC9860_SCL6_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
SC9860_U1TXD_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
SC9860_U1RXD_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT0_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT1_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT2_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
SC9860_KEYIN0_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
SC9860_KEYIN1_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
SC9860_KEYIN2_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
SC9860_IIS3DI_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
SC9860_IIS3DO_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
SC9860_IIS3CLK_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
SC9860_IIS3LRCK_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
SC9860_RFCTL0_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
SC9860_RFCTL1_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
SC9860_RFCTL10_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
SC9860_RFCTL11_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
SC9860_RFCTL12_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
SC9860_RFCTL13_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
SC9860_RFCTL14_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
SC9860_RFCTL15_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
SC9860_RFCTL16_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
SC9860_RFCTL17_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
SC9860_RFCTL18_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
SC9860_RFCTL19_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
SC9860_RFCTL2_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
SC9860_EXTINT5_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
SC9860_EXTINT6_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
SC9860_EXTINT7_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
SC9860_GPIO30_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
SC9860_GPIO31_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
SC9860_GPIO32_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
SC9860_GPIO33_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
SC9860_GPIO34_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
SC9860_RFCTL3_MISC = SPRD_PIN_INFO(394, MISC_PIN, 0, 0, 0),
SC9860_RFCTL4_MISC = SPRD_PIN_INFO(396, MISC_PIN, 0, 0, 0),
SC9860_RFCTL5_MISC = SPRD_PIN_INFO(398, MISC_PIN, 0, 0, 0),
SC9860_RFCTL6_MISC = SPRD_PIN_INFO(400, MISC_PIN, 0, 0, 0),
SC9860_RFCTL7_MISC = SPRD_PIN_INFO(402, MISC_PIN, 0, 0, 0),
SC9860_RFCTL8_MISC = SPRD_PIN_INFO(404, MISC_PIN, 0, 0, 0),
SC9860_RFCTL9_MISC = SPRD_PIN_INFO(406, MISC_PIN, 0, 0, 0),
SC9860_RFFE0_SCK0_MISC = SPRD_PIN_INFO(408, MISC_PIN, 0, 0, 0),
SC9860_GPIO38_MISC = SPRD_PIN_INFO(410, MISC_PIN, 0, 0, 0),
SC9860_RFFE0_SDA0_MISC = SPRD_PIN_INFO(412, MISC_PIN, 0, 0, 0),
SC9860_GPIO39_MISC = SPRD_PIN_INFO(414, MISC_PIN, 0, 0, 0),
SC9860_RFFE1_SCK0_MISC = SPRD_PIN_INFO(416, MISC_PIN, 0, 0, 0),
SC9860_GPIO181_MISC = SPRD_PIN_INFO(418, MISC_PIN, 0, 0, 0),
SC9860_RFFE1_SDA0_MISC = SPRD_PIN_INFO(420, MISC_PIN, 0, 0, 0),
SC9860_GPIO182_MISC = SPRD_PIN_INFO(422, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS0_ADC_ON_MISC = SPRD_PIN_INFO(424, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS0_DAC_ON_MISC = SPRD_PIN_INFO(426, MISC_PIN, 0, 0, 0),
SC9860_RFSCK0_MISC = SPRD_PIN_INFO(428, MISC_PIN, 0, 0, 0),
SC9860_RFSDA0_MISC = SPRD_PIN_INFO(430, MISC_PIN, 0, 0, 0),
SC9860_RFSEN0_MISC = SPRD_PIN_INFO(432, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS1_ADC_ON_MISC = SPRD_PIN_INFO(434, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS1_DAC_ON_MISC = SPRD_PIN_INFO(436, MISC_PIN, 0, 0, 0),
SC9860_RFSCK1_MISC = SPRD_PIN_INFO(438, MISC_PIN, 0, 0, 0),
SC9860_RFSDA1_MISC = SPRD_PIN_INFO(440, MISC_PIN, 0, 0, 0),
SC9860_RFSEN1_MISC = SPRD_PIN_INFO(442, MISC_PIN, 0, 0, 0),
SC9860_RFCTL38_MISC = SPRD_PIN_INFO(444, MISC_PIN, 0, 0, 0),
SC9860_RFCTL39_MISC = SPRD_PIN_INFO(446, MISC_PIN, 0, 0, 0),
};
static struct sprd_pins_info sprd_sc9860_pins_info[] = {
SPRD_PINCTRL_PIN(SC9860_VIO28_0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SD2_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SD0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO28_0_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SD2_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SD0_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_MS),
SPRD_PINCTRL_PIN(SC9860_SPSPI_PIN_IN_SEL),
SPRD_PINCTRL_PIN(SC9860_UART1_USB30_PHY_SEL),
SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DM_OE),
SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DP_OE),
SPRD_PINCTRL_PIN(SC9860_UART5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_ORP_URXD_PIN_IN_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_CLK26MHZ_BUF_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_UART4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART24_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART23_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART14_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART13_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS23_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS13_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS12_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS03_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS02_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS01_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF7_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_WDRST_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_ADI_SYNC_PIN_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_CMRST_SEL),
SPRD_PINCTRL_PIN(SC9860_CMPD_SEL),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE11),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE10),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE9),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE8),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE7),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE6),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE5),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE4),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE3),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE2),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE1),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE0),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD3_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD2_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD1_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD0_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD7_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD6_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD5_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD4_SEL),
SPRD_PINCTRL_PIN(SC9860_RFCTL20),
SPRD_PINCTRL_PIN(SC9860_RFCTL21),
SPRD_PINCTRL_PIN(SC9860_RFCTL30),
SPRD_PINCTRL_PIN(SC9860_RFCTL31),
SPRD_PINCTRL_PIN(SC9860_RFCTL32),
SPRD_PINCTRL_PIN(SC9860_RFCTL33),
SPRD_PINCTRL_PIN(SC9860_RFCTL34),
SPRD_PINCTRL_PIN(SC9860_RFCTL35),
SPRD_PINCTRL_PIN(SC9860_RFCTL36),
SPRD_PINCTRL_PIN(SC9860_RFCTL37),
SPRD_PINCTRL_PIN(SC9860_RFCTL22),
SPRD_PINCTRL_PIN(SC9860_RFCTL23),
SPRD_PINCTRL_PIN(SC9860_RFCTL24),
SPRD_PINCTRL_PIN(SC9860_RFCTL25),
SPRD_PINCTRL_PIN(SC9860_RFCTL26),
SPRD_PINCTRL_PIN(SC9860_RFCTL27),
SPRD_PINCTRL_PIN(SC9860_RFCTL28),
SPRD_PINCTRL_PIN(SC9860_RFCTL29),
SPRD_PINCTRL_PIN(SC9860_SCL2),
SPRD_PINCTRL_PIN(SC9860_SDA2),
SPRD_PINCTRL_PIN(SC9860_MTCK_ARM),
SPRD_PINCTRL_PIN(SC9860_MTMS_ARM),
SPRD_PINCTRL_PIN(SC9860_XTL_EN0),
SPRD_PINCTRL_PIN(SC9860_PTEST),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD1),
SPRD_PINCTRL_PIN(SC9860_AUD_ADD0),
SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC),
SPRD_PINCTRL_PIN(SC9860_AUD_SCLK),
SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP),
SPRD_PINCTRL_PIN(SC9860_CLK_32K),
SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN),
SPRD_PINCTRL_PIN(SC9860_EXT_RST_B),
SPRD_PINCTRL_PIN(SC9860_ADI_D),
SPRD_PINCTRL_PIN(SC9860_ADI_SCLK),
SPRD_PINCTRL_PIN(SC9860_XTL_EN1),
SPRD_PINCTRL_PIN(SC9860_ANA_INT),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD0),
SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC),
SPRD_PINCTRL_PIN(SC9860_LCM_RSTN),
SPRD_PINCTRL_PIN(SC9860_DSI_TE),
SPRD_PINCTRL_PIN(SC9860_PWMA),
SPRD_PINCTRL_PIN(SC9860_EXTINT0),
SPRD_PINCTRL_PIN(SC9860_EXTINT1),
SPRD_PINCTRL_PIN(SC9860_SDA1),
SPRD_PINCTRL_PIN(SC9860_SCL1),
SPRD_PINCTRL_PIN(SC9860_SIMCLK2),
SPRD_PINCTRL_PIN(SC9860_SIMDA2),
SPRD_PINCTRL_PIN(SC9860_SIMRST2),
SPRD_PINCTRL_PIN(SC9860_SIMCLK1),
SPRD_PINCTRL_PIN(SC9860_SIMDA1),
SPRD_PINCTRL_PIN(SC9860_SIMRST1),
SPRD_PINCTRL_PIN(SC9860_SIMCLK0),
SPRD_PINCTRL_PIN(SC9860_SIMDA0),
SPRD_PINCTRL_PIN(SC9860_SIMRST0),
SPRD_PINCTRL_PIN(SC9860_SD2_CMD),
SPRD_PINCTRL_PIN(SC9860_SD2_D0),
SPRD_PINCTRL_PIN(SC9860_SD2_D1),
SPRD_PINCTRL_PIN(SC9860_SD2_CLK),
SPRD_PINCTRL_PIN(SC9860_SD2_D2),
SPRD_PINCTRL_PIN(SC9860_SD2_D3),
SPRD_PINCTRL_PIN(SC9860_SD0_D3),
SPRD_PINCTRL_PIN(SC9860_SD0_D2),
SPRD_PINCTRL_PIN(SC9860_SD0_CMD),
SPRD_PINCTRL_PIN(SC9860_SD0_D0),
SPRD_PINCTRL_PIN(SC9860_SD0_D1),
SPRD_PINCTRL_PIN(SC9860_SD0_CLK),
SPRD_PINCTRL_PIN(SC9860_EMMC_CMD),
SPRD_PINCTRL_PIN(SC9860_EMMC_D6),
SPRD_PINCTRL_PIN(SC9860_EMMC_D7),
SPRD_PINCTRL_PIN(SC9860_EMMC_CLK),
SPRD_PINCTRL_PIN(SC9860_EMMC_D5),
SPRD_PINCTRL_PIN(SC9860_EMMC_D4),
SPRD_PINCTRL_PIN(SC9860_EMMC_DS),
SPRD_PINCTRL_PIN(SC9860_EMMC_D3),
SPRD_PINCTRL_PIN(SC9860_EMMC_RST),
SPRD_PINCTRL_PIN(SC9860_EMMC_D1),
SPRD_PINCTRL_PIN(SC9860_EMMC_D2),
SPRD_PINCTRL_PIN(SC9860_EMMC_D0),
SPRD_PINCTRL_PIN(SC9860_IIS0DI),
SPRD_PINCTRL_PIN(SC9860_IIS0DO),
SPRD_PINCTRL_PIN(SC9860_IIS0CLK),
SPRD_PINCTRL_PIN(SC9860_IIS0LRCK),
SPRD_PINCTRL_PIN(SC9860_SD1_CLK),
SPRD_PINCTRL_PIN(SC9860_SD1_CMD),
SPRD_PINCTRL_PIN(SC9860_SD1_D0),
SPRD_PINCTRL_PIN(SC9860_SD1_D1),
SPRD_PINCTRL_PIN(SC9860_SD1_D2),
SPRD_PINCTRL_PIN(SC9860_SD1_D3),
SPRD_PINCTRL_PIN(SC9860_CLK_AUX0),
SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST),
SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST),
SPRD_PINCTRL_PIN(SC9860_U3TXD),
SPRD_PINCTRL_PIN(SC9860_U3RXD),
SPRD_PINCTRL_PIN(SC9860_U3CTS),
SPRD_PINCTRL_PIN(SC9860_U3RTS),
SPRD_PINCTRL_PIN(SC9860_U0TXD),
SPRD_PINCTRL_PIN(SC9860_U0RXD),
SPRD_PINCTRL_PIN(SC9860_U0CTS),
SPRD_PINCTRL_PIN(SC9860_U0RTS),
SPRD_PINCTRL_PIN(SC9860_IIS1DI),
SPRD_PINCTRL_PIN(SC9860_IIS1DO),
SPRD_PINCTRL_PIN(SC9860_IIS1CLK),
SPRD_PINCTRL_PIN(SC9860_IIS1LRCK),
SPRD_PINCTRL_PIN(SC9860_SPI0_CSN),
SPRD_PINCTRL_PIN(SC9860_SPI0_DO),
SPRD_PINCTRL_PIN(SC9860_SPI0_DI),
SPRD_PINCTRL_PIN(SC9860_SPI0_CLK),
SPRD_PINCTRL_PIN(SC9860_U2TXD),
SPRD_PINCTRL_PIN(SC9860_U2RXD),
SPRD_PINCTRL_PIN(SC9860_U4TXD),
SPRD_PINCTRL_PIN(SC9860_U4RXD),
SPRD_PINCTRL_PIN(SC9860_CMMCLK1),
SPRD_PINCTRL_PIN(SC9860_CMRST1),
SPRD_PINCTRL_PIN(SC9860_CMMCLK0),
SPRD_PINCTRL_PIN(SC9860_CMRST0),
SPRD_PINCTRL_PIN(SC9860_CMPD0),
SPRD_PINCTRL_PIN(SC9860_CMPD1),
SPRD_PINCTRL_PIN(SC9860_SCL0),
SPRD_PINCTRL_PIN(SC9860_SDA0),
SPRD_PINCTRL_PIN(SC9860_SDA6),
SPRD_PINCTRL_PIN(SC9860_SCL6),
SPRD_PINCTRL_PIN(SC9860_U1TXD),
SPRD_PINCTRL_PIN(SC9860_U1RXD),
SPRD_PINCTRL_PIN(SC9860_KEYOUT0),
SPRD_PINCTRL_PIN(SC9860_KEYOUT1),
SPRD_PINCTRL_PIN(SC9860_KEYOUT2),
SPRD_PINCTRL_PIN(SC9860_KEYIN0),
SPRD_PINCTRL_PIN(SC9860_KEYIN1),
SPRD_PINCTRL_PIN(SC9860_KEYIN2),
SPRD_PINCTRL_PIN(SC9860_IIS3DI),
SPRD_PINCTRL_PIN(SC9860_IIS3DO),
SPRD_PINCTRL_PIN(SC9860_IIS3CLK),
SPRD_PINCTRL_PIN(SC9860_IIS3LRCK),
SPRD_PINCTRL_PIN(SC9860_RFCTL0),
SPRD_PINCTRL_PIN(SC9860_RFCTL1),
SPRD_PINCTRL_PIN(SC9860_RFCTL10),
SPRD_PINCTRL_PIN(SC9860_RFCTL11),
SPRD_PINCTRL_PIN(SC9860_RFCTL12),
SPRD_PINCTRL_PIN(SC9860_RFCTL13),
SPRD_PINCTRL_PIN(SC9860_RFCTL14),
SPRD_PINCTRL_PIN(SC9860_RFCTL15),
SPRD_PINCTRL_PIN(SC9860_RFCTL16),
SPRD_PINCTRL_PIN(SC9860_RFCTL17),
SPRD_PINCTRL_PIN(SC9860_RFCTL18),
SPRD_PINCTRL_PIN(SC9860_RFCTL19),
SPRD_PINCTRL_PIN(SC9860_RFCTL2),
SPRD_PINCTRL_PIN(SC9860_EXTINT5),
SPRD_PINCTRL_PIN(SC9860_EXTINT6),
SPRD_PINCTRL_PIN(SC9860_EXTINT7),
SPRD_PINCTRL_PIN(SC9860_GPIO30),
SPRD_PINCTRL_PIN(SC9860_GPIO31),
SPRD_PINCTRL_PIN(SC9860_GPIO32),
SPRD_PINCTRL_PIN(SC9860_GPIO33),
SPRD_PINCTRL_PIN(SC9860_GPIO34),
SPRD_PINCTRL_PIN(SC9860_RFCTL3),
SPRD_PINCTRL_PIN(SC9860_RFCTL4),
SPRD_PINCTRL_PIN(SC9860_RFCTL5),
SPRD_PINCTRL_PIN(SC9860_RFCTL6),
SPRD_PINCTRL_PIN(SC9860_RFCTL7),
SPRD_PINCTRL_PIN(SC9860_RFCTL8),
SPRD_PINCTRL_PIN(SC9860_RFCTL9),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0),
SPRD_PINCTRL_PIN(SC9860_GPIO38),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0),
SPRD_PINCTRL_PIN(SC9860_GPIO39),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0),
SPRD_PINCTRL_PIN(SC9860_GPIO181),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0),
SPRD_PINCTRL_PIN(SC9860_GPIO182),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON),
SPRD_PINCTRL_PIN(SC9860_RFSCK0),
SPRD_PINCTRL_PIN(SC9860_RFSDA0),
SPRD_PINCTRL_PIN(SC9860_RFSEN0),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON),
SPRD_PINCTRL_PIN(SC9860_RFSCK1),
SPRD_PINCTRL_PIN(SC9860_RFSDA1),
SPRD_PINCTRL_PIN(SC9860_RFSEN1),
SPRD_PINCTRL_PIN(SC9860_RFCTL38),
SPRD_PINCTRL_PIN(SC9860_RFCTL39),
SPRD_PINCTRL_PIN(SC9860_RFCTL20_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL21_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL30_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL31_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL32_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL33_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL34_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL35_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL36_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL37_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL22_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL23_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL24_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL25_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL26_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL27_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL28_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL29_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL2_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA2_MISC),
SPRD_PINCTRL_PIN(SC9860_MTCK_ARM_MISC),
SPRD_PINCTRL_PIN(SC9860_MTMS_ARM_MISC),
SPRD_PINCTRL_PIN(SC9860_XTL_EN0_MISC),
SPRD_PINCTRL_PIN(SC9860_PTEST_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD1_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_ADD0_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_SCLK_MISC),
SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP_MISC),
SPRD_PINCTRL_PIN(SC9860_CLK_32K_MISC),
SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN_MISC),
SPRD_PINCTRL_PIN(SC9860_EXT_RST_B_MISC),
SPRD_PINCTRL_PIN(SC9860_ADI_D_MISC),
SPRD_PINCTRL_PIN(SC9860_ADI_SCLK_MISC),
SPRD_PINCTRL_PIN(SC9860_XTL_EN1_MISC),
SPRD_PINCTRL_PIN(SC9860_ANA_INT_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD0_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC_MISC),
SPRD_PINCTRL_PIN(SC9860_LCM_RSTN_MISC),
SPRD_PINCTRL_PIN(SC9860_DSI_TE_MISC),
SPRD_PINCTRL_PIN(SC9860_PWMA_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT0_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT1_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK0_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D6_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D7_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D5_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D4_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_DS_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_RST_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_CLK_AUX0_MISC),
SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST_MISC),
SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST_MISC),
SPRD_PINCTRL_PIN(SC9860_U3TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U3RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U3CTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U3RTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U0TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U0RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U0CTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U0RTS_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_CSN_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_DO_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_DI_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_U2TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U2RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U4TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U4RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_CMMCLK1_MISC),
SPRD_PINCTRL_PIN(SC9860_CMRST1_MISC),
SPRD_PINCTRL_PIN(SC9860_CMMCLK0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMRST0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMPD0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMPD1_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL0_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA6_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL6_MISC),
SPRD_PINCTRL_PIN(SC9860_U1TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U1RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT0_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT1_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT2_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN0_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN1_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN2_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL10_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL11_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL12_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL13_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL14_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL15_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL16_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL17_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL18_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL19_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL2_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT5_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT6_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT7_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO30_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO31_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO32_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO33_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO34_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL3_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL4_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL5_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL6_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL7_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL8_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL9_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO38_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO39_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO181_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO182_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSEN0_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSCK1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSEN1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL38_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL39_MISC),
};
static int sprd_pinctrl_probe(struct platform_device *pdev)
{
return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info,
ARRAY_SIZE(sprd_sc9860_pins_info));
}
static const struct of_device_id sprd_pinctrl_of_match[] = {
{
.compatible = "sprd,sc9860-pinctrl",
},
{ },
};
MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
static struct platform_driver sprd_pinctrl_driver = {
.driver = {
.name = "sprd-pinctrl",
.of_match_table = sprd_pinctrl_of_match,
},
.probe = sprd_pinctrl_probe,
.remove = sprd_pinctrl_remove,
.shutdown = sprd_pinctrl_shutdown,
};
module_platform_driver(sprd_pinctrl_driver);
MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
MODULE_AUTHOR("Baolin Wang <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L92
*
* Copyright (C) 2018-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l92_spk1_pins[] = { 2, 3 };
static const unsigned int cs47l92_aif1_pins[] = { 4, 5, 6, 7 };
static const unsigned int cs47l92_aif2_pins[] = { 8, 9, 10, 11 };
static const unsigned int cs47l92_aif3_pins[] = { 12, 13, 14, 15 };
static const struct madera_pin_groups cs47l92_pin_groups[] = {
{ "aif1", cs47l92_aif1_pins, ARRAY_SIZE(cs47l92_aif1_pins) },
{ "aif2", cs47l92_aif2_pins, ARRAY_SIZE(cs47l92_aif2_pins) },
{ "aif3", cs47l92_aif3_pins, ARRAY_SIZE(cs47l92_aif3_pins) },
{ "pdmspk1", cs47l92_spk1_pins, ARRAY_SIZE(cs47l92_spk1_pins) },
};
const struct madera_pin_chip cs47l92_pin_chip = {
.n_pins = CS47L92_NUM_GPIOS,
.pin_groups = cs47l92_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l92_pin_groups),
};
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs47l92.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L35
*
* Copyright (C) 2016-2017 Cirrus Logic
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l35_aif3_pins[] = { 0, 1, 2, 3 };
static const unsigned int cs47l35_spk_pins[] = { 4, 5 };
static const unsigned int cs47l35_aif1_pins[] = { 7, 8, 9, 10 };
static const unsigned int cs47l35_aif2_pins[] = { 11, 12, 13, 14 };
static const unsigned int cs47l35_mif1_pins[] = { 6, 15 };
static const struct madera_pin_groups cs47l35_pin_groups[] = {
{ "aif1", cs47l35_aif1_pins, ARRAY_SIZE(cs47l35_aif1_pins) },
{ "aif2", cs47l35_aif2_pins, ARRAY_SIZE(cs47l35_aif2_pins) },
{ "aif3", cs47l35_aif3_pins, ARRAY_SIZE(cs47l35_aif3_pins) },
{ "mif1", cs47l35_mif1_pins, ARRAY_SIZE(cs47l35_mif1_pins) },
{ "pdmspk1", cs47l35_spk_pins, ARRAY_SIZE(cs47l35_spk_pins) },
};
const struct madera_pin_chip cs47l35_pin_chip = {
.n_pins = CS47L35_NUM_GPIOS,
.pin_groups = cs47l35_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l35_pin_groups),
};
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs47l35.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic Madera codecs
*
* Copyright (C) 2016-2018 Cirrus Logic
*/
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "../pinctrl-utils.h"
#include "pinctrl-madera.h"
/*
* Use pin GPIO names for consistency
* NOTE: IDs are zero-indexed for coding convenience
*/
static const struct pinctrl_pin_desc madera_pins[] = {
PINCTRL_PIN(0, "gpio1"),
PINCTRL_PIN(1, "gpio2"),
PINCTRL_PIN(2, "gpio3"),
PINCTRL_PIN(3, "gpio4"),
PINCTRL_PIN(4, "gpio5"),
PINCTRL_PIN(5, "gpio6"),
PINCTRL_PIN(6, "gpio7"),
PINCTRL_PIN(7, "gpio8"),
PINCTRL_PIN(8, "gpio9"),
PINCTRL_PIN(9, "gpio10"),
PINCTRL_PIN(10, "gpio11"),
PINCTRL_PIN(11, "gpio12"),
PINCTRL_PIN(12, "gpio13"),
PINCTRL_PIN(13, "gpio14"),
PINCTRL_PIN(14, "gpio15"),
PINCTRL_PIN(15, "gpio16"),
PINCTRL_PIN(16, "gpio17"),
PINCTRL_PIN(17, "gpio18"),
PINCTRL_PIN(18, "gpio19"),
PINCTRL_PIN(19, "gpio20"),
PINCTRL_PIN(20, "gpio21"),
PINCTRL_PIN(21, "gpio22"),
PINCTRL_PIN(22, "gpio23"),
PINCTRL_PIN(23, "gpio24"),
PINCTRL_PIN(24, "gpio25"),
PINCTRL_PIN(25, "gpio26"),
PINCTRL_PIN(26, "gpio27"),
PINCTRL_PIN(27, "gpio28"),
PINCTRL_PIN(28, "gpio29"),
PINCTRL_PIN(29, "gpio30"),
PINCTRL_PIN(30, "gpio31"),
PINCTRL_PIN(31, "gpio32"),
PINCTRL_PIN(32, "gpio33"),
PINCTRL_PIN(33, "gpio34"),
PINCTRL_PIN(34, "gpio35"),
PINCTRL_PIN(35, "gpio36"),
PINCTRL_PIN(36, "gpio37"),
PINCTRL_PIN(37, "gpio38"),
PINCTRL_PIN(38, "gpio39"),
PINCTRL_PIN(39, "gpio40"),
};
/*
* All single-pin functions can be mapped to any GPIO, however pinmux applies
* functions to pin groups and only those groups declared as supporting that
* function. To make this work we must put each pin in its own dummy group so
* that the functions can be described as applying to all pins.
* Since these do not correspond to anything in the actual hardware - they are
* merely an adaptation to pinctrl's view of the world - we use the same name
* as the pin to avoid confusion when comparing with datasheet instructions
*/
static const char * const madera_pin_single_group_names[] = {
"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
};
/* set of pin numbers for single-pin groups, zero-indexed */
static const unsigned int madera_pin_single_group_pins[] = {
0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17, 18, 19, 20,
21, 22, 23, 24, 25, 26, 27,
28, 29, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39,
};
static const char * const madera_aif1_group_names[] = { "aif1" };
static const char * const madera_aif2_group_names[] = { "aif2" };
static const char * const madera_aif3_group_names[] = { "aif3" };
static const char * const madera_aif4_group_names[] = { "aif4" };
static const char * const madera_mif1_group_names[] = { "mif1" };
static const char * const madera_mif2_group_names[] = { "mif2" };
static const char * const madera_mif3_group_names[] = { "mif3" };
static const char * const madera_dmic3_group_names[] = { "dmic3" };
static const char * const madera_dmic4_group_names[] = { "dmic4" };
static const char * const madera_dmic5_group_names[] = { "dmic5" };
static const char * const madera_dmic6_group_names[] = { "dmic6" };
static const char * const madera_spk1_group_names[] = { "pdmspk1" };
static const char * const madera_spk2_group_names[] = { "pdmspk2" };
/*
* alt-functions always apply to a single pin group, other functions always
* apply to all pins
*/
static const struct {
const char *name;
const char * const *group_names;
u32 func;
} madera_mux_funcs[] = {
{
.name = "aif1",
.group_names = madera_aif1_group_names,
.func = 0x000
},
{
.name = "aif2",
.group_names = madera_aif2_group_names,
.func = 0x000
},
{
.name = "aif3",
.group_names = madera_aif3_group_names,
.func = 0x000
},
{
.name = "aif4",
.group_names = madera_aif4_group_names,
.func = 0x000
},
{
.name = "mif1",
.group_names = madera_mif1_group_names,
.func = 0x000
},
{
.name = "mif2",
.group_names = madera_mif2_group_names,
.func = 0x000
},
{
.name = "mif3",
.group_names = madera_mif3_group_names,
.func = 0x000
},
{
.name = "dmic3",
.group_names = madera_dmic3_group_names,
.func = 0x000
},
{
.name = "dmic4",
.group_names = madera_dmic4_group_names,
.func = 0x000
},
{
.name = "dmic5",
.group_names = madera_dmic5_group_names,
.func = 0x000
},
{
.name = "dmic6",
.group_names = madera_dmic6_group_names,
.func = 0x000
},
{
.name = "pdmspk1",
.group_names = madera_spk1_group_names,
.func = 0x000
},
{
.name = "pdmspk2",
.group_names = madera_spk2_group_names,
.func = 0x000
},
{
.name = "io",
.group_names = madera_pin_single_group_names,
.func = 0x001
},
{
.name = "dsp-gpio",
.group_names = madera_pin_single_group_names,
.func = 0x002
},
{
.name = "irq1",
.group_names = madera_pin_single_group_names,
.func = 0x003
},
{
.name = "irq2",
.group_names = madera_pin_single_group_names,
.func = 0x004
},
{
.name = "fll1-clk",
.group_names = madera_pin_single_group_names,
.func = 0x010
},
{
.name = "fll2-clk",
.group_names = madera_pin_single_group_names,
.func = 0x011
},
{
.name = "fll3-clk",
.group_names = madera_pin_single_group_names,
.func = 0x012
},
{
.name = "fllao-clk",
.group_names = madera_pin_single_group_names,
.func = 0x013
},
{
.name = "fll1-lock",
.group_names = madera_pin_single_group_names,
.func = 0x018
},
{
.name = "fll2-lock",
.group_names = madera_pin_single_group_names,
.func = 0x019
},
{
.name = "fll3-lock",
.group_names = madera_pin_single_group_names,
.func = 0x01a
},
{
.name = "fllao-lock",
.group_names = madera_pin_single_group_names,
.func = 0x01b
},
{
.name = "opclk",
.group_names = madera_pin_single_group_names,
.func = 0x040
},
{
.name = "opclk-async",
.group_names = madera_pin_single_group_names,
.func = 0x041
},
{
.name = "pwm1",
.group_names = madera_pin_single_group_names,
.func = 0x048
},
{
.name = "pwm2",
.group_names = madera_pin_single_group_names,
.func = 0x049
},
{
.name = "spdif",
.group_names = madera_pin_single_group_names,
.func = 0x04c
},
{
.name = "asrc1-in1-lock",
.group_names = madera_pin_single_group_names,
.func = 0x088
},
{
.name = "asrc1-in2-lock",
.group_names = madera_pin_single_group_names,
.func = 0x089
},
{
.name = "asrc2-in1-lock",
.group_names = madera_pin_single_group_names,
.func = 0x08a
},
{
.name = "asrc2-in2-lock",
.group_names = madera_pin_single_group_names,
.func = 0x08b
},
{
.name = "spkl-short-circuit",
.group_names = madera_pin_single_group_names,
.func = 0x0b6
},
{
.name = "spkr-short-circuit",
.group_names = madera_pin_single_group_names,
.func = 0x0b7
},
{
.name = "spk-shutdown",
.group_names = madera_pin_single_group_names,
.func = 0x0e0
},
{
.name = "spk-overheat-shutdown",
.group_names = madera_pin_single_group_names,
.func = 0x0e1
},
{
.name = "spk-overheat-warn",
.group_names = madera_pin_single_group_names,
.func = 0x0e2
},
{
.name = "timer1-sts",
.group_names = madera_pin_single_group_names,
.func = 0x140
},
{
.name = "timer2-sts",
.group_names = madera_pin_single_group_names,
.func = 0x141
},
{
.name = "timer3-sts",
.group_names = madera_pin_single_group_names,
.func = 0x142
},
{
.name = "timer4-sts",
.group_names = madera_pin_single_group_names,
.func = 0x143
},
{
.name = "timer5-sts",
.group_names = madera_pin_single_group_names,
.func = 0x144
},
{
.name = "timer6-sts",
.group_names = madera_pin_single_group_names,
.func = 0x145
},
{
.name = "timer7-sts",
.group_names = madera_pin_single_group_names,
.func = 0x146
},
{
.name = "timer8-sts",
.group_names = madera_pin_single_group_names,
.func = 0x147
},
{
.name = "log1-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x150
},
{
.name = "log2-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x151
},
{
.name = "log3-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x152
},
{
.name = "log4-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x153
},
{
.name = "log5-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x154
},
{
.name = "log6-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x155
},
{
.name = "log7-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x156
},
{
.name = "log8-fifo-ne",
.group_names = madera_pin_single_group_names,
.func = 0x157
},
{
.name = "aux-pdm-clk",
.group_names = madera_pin_single_group_names,
.func = 0x280
},
{
.name = "aux-pdm-dat",
.group_names = madera_pin_single_group_names,
.func = 0x281
},
};
static u16 madera_pin_make_drv_str(struct madera_pin_private *priv,
unsigned int milliamps)
{
switch (milliamps) {
case 4:
return 0;
case 8:
return 2 << MADERA_GP1_DRV_STR_SHIFT;
default:
break;
}
dev_warn(priv->dev, "%u mA not a valid drive strength", milliamps);
return 0;
}
static unsigned int madera_pin_unmake_drv_str(struct madera_pin_private *priv,
u16 regval)
{
regval = (regval & MADERA_GP1_DRV_STR_MASK) >> MADERA_GP1_DRV_STR_SHIFT;
switch (regval) {
case 0:
return 4;
case 2:
return 8;
default:
return 0;
}
}
static int madera_get_groups_count(struct pinctrl_dev *pctldev)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
/* Number of alt function groups plus number of single-pin groups */
return priv->chip->n_pin_groups + priv->chip->n_pins;
}
static const char *madera_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
if (selector < priv->chip->n_pin_groups)
return priv->chip->pin_groups[selector].name;
selector -= priv->chip->n_pin_groups;
return madera_pin_single_group_names[selector];
}
static int madera_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
if (selector < priv->chip->n_pin_groups) {
*pins = priv->chip->pin_groups[selector].pins;
*num_pins = priv->chip->pin_groups[selector].n_pins;
} else {
/* return the dummy group for a single pin */
selector -= priv->chip->n_pin_groups;
*pins = &madera_pin_single_group_pins[selector];
*num_pins = 1;
}
return 0;
}
static void madera_pin_dbg_show_fn(struct madera_pin_private *priv,
struct seq_file *s,
unsigned int pin, unsigned int fn)
{
const struct madera_pin_chip *chip = priv->chip;
int i, g_pin;
if (fn != 0) {
for (i = 0; i < ARRAY_SIZE(madera_mux_funcs); ++i) {
if (madera_mux_funcs[i].func == fn) {
seq_printf(s, " FN=%s",
madera_mux_funcs[i].name);
return;
}
}
return; /* ignore unknown function values */
}
/* alt function */
for (i = 0; i < chip->n_pin_groups; ++i) {
for (g_pin = 0; g_pin < chip->pin_groups[i].n_pins; ++g_pin) {
if (chip->pin_groups[i].pins[g_pin] == pin) {
seq_printf(s, " FN=%s",
chip->pin_groups[i].name);
return;
}
}
}
}
static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int conf[2];
unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
unsigned int fn;
int ret;
ret = regmap_read(priv->madera->regmap, reg, &conf[0]);
if (ret)
return;
ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]);
if (ret)
return;
seq_printf(s, "%04x:%04x", conf[0], conf[1]);
fn = (conf[0] & MADERA_GP1_FN_MASK) >> MADERA_GP1_FN_SHIFT;
madera_pin_dbg_show_fn(priv, s, pin, fn);
/* State of direction bit is only relevant if function==1 */
if (fn == 1) {
if (conf[1] & MADERA_GP1_DIR_MASK)
seq_puts(s, " IN");
else
seq_puts(s, " OUT");
}
if (conf[1] & MADERA_GP1_PU_MASK)
seq_puts(s, " PU");
if (conf[1] & MADERA_GP1_PD_MASK)
seq_puts(s, " PD");
if (conf[0] & MADERA_GP1_DB_MASK)
seq_puts(s, " DB");
if (conf[0] & MADERA_GP1_OP_CFG_MASK)
seq_puts(s, " OD");
else
seq_puts(s, " CMOS");
seq_printf(s, " DRV=%umA", madera_pin_unmake_drv_str(priv, conf[1]));
if (conf[0] & MADERA_GP1_IP_CFG_MASK)
seq_puts(s, " SCHMITT");
}
static const struct pinctrl_ops madera_pin_group_ops = {
.get_groups_count = madera_get_groups_count,
.get_group_name = madera_get_group_name,
.get_group_pins = madera_get_group_pins,
#if IS_ENABLED(CONFIG_OF)
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
#endif
#if IS_ENABLED(CONFIG_DEBUG_FS)
.pin_dbg_show = madera_pin_dbg_show,
#endif
};
static int madera_mux_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(madera_mux_funcs);
}
static const char *madera_mux_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return madera_mux_funcs[selector].name;
}
static int madera_mux_get_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
*groups = madera_mux_funcs[selector].group_names;
if (madera_mux_funcs[selector].func == 0) {
/* alt func always maps to a single group */
*num_groups = 1;
} else {
/* other funcs map to all available gpio pins */
*num_groups = priv->chip->n_pins;
}
return 0;
}
static int madera_mux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned int group)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
struct madera *madera = priv->madera;
const struct madera_pin_groups *pin_group = priv->chip->pin_groups;
unsigned int n_chip_groups = priv->chip->n_pin_groups;
const char *func_name = madera_mux_funcs[selector].name;
unsigned int reg;
int i, ret = 0;
dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n",
__func__, selector, func_name, group,
madera_get_group_name(pctldev, group));
if (madera_mux_funcs[selector].func == 0) {
/* alt func pin assignments are codec-specific */
for (i = 0; i < n_chip_groups; ++i) {
if (strcmp(func_name, pin_group->name) == 0)
break;
++pin_group;
}
if (i == n_chip_groups)
return -EINVAL;
for (i = 0; i < pin_group->n_pins; ++i) {
reg = MADERA_GPIO1_CTRL_1 + (2 * pin_group->pins[i]);
dev_dbg(priv->dev, "%s setting 0x%x func bits to 0\n",
__func__, reg);
ret = regmap_update_bits(madera->regmap, reg,
MADERA_GP1_FN_MASK, 0);
if (ret)
break;
}
} else {
/*
* for other funcs the group will be the gpio number and will
* be offset by the number of chip-specific functions at the
* start of the group list
*/
group -= n_chip_groups;
reg = MADERA_GPIO1_CTRL_1 + (2 * group);
dev_dbg(priv->dev, "%s setting 0x%x func bits to 0x%x\n",
__func__, reg, madera_mux_funcs[selector].func);
ret = regmap_update_bits(madera->regmap,
reg,
MADERA_GP1_FN_MASK,
madera_mux_funcs[selector].func);
}
if (ret)
dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
return ret;
}
static int madera_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset,
bool input)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
struct madera *madera = priv->madera;
unsigned int reg = MADERA_GPIO1_CTRL_2 + (2 * offset);
unsigned int val;
int ret;
if (input)
val = MADERA_GP1_DIR;
else
val = 0;
ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_DIR_MASK, val);
if (ret)
dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
return ret;
}
static int madera_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
struct madera *madera = priv->madera;
unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset);
int ret;
/* put the pin into GPIO mode */
ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1);
if (ret)
dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
return ret;
}
static void madera_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
struct madera *madera = priv->madera;
unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset);
int ret;
/* disable GPIO by setting to GPIO IN */
madera_gpio_set_direction(pctldev, range, offset, true);
ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1);
if (ret)
dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
}
static const struct pinmux_ops madera_pin_mux_ops = {
.get_functions_count = madera_mux_get_funcs_count,
.get_function_name = madera_mux_get_func_name,
.get_function_groups = madera_mux_get_groups,
.set_mux = madera_mux_set_mux,
.gpio_request_enable = madera_gpio_request_enable,
.gpio_disable_free = madera_gpio_disable_free,
.gpio_set_direction = madera_gpio_set_direction,
.strict = true, /* GPIO and other functions are exclusive */
};
static int madera_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
unsigned int result = 0;
unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
unsigned int conf[2];
int ret;
ret = regmap_read(priv->madera->regmap, reg, &conf[0]);
if (!ret)
ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]);
if (ret) {
dev_err(priv->dev, "Failed to read GP%d conf (%d)\n",
pin + 1, ret);
return ret;
}
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
if (conf[1] == (MADERA_GP1_PU | MADERA_GP1_PD))
result = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
if (!conf[1])
result = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
if (conf[1] == MADERA_GP1_PD_MASK)
result = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
if (conf[1] == MADERA_GP1_PU_MASK)
result = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (conf[0] & MADERA_GP1_OP_CFG_MASK)
result = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (!(conf[0] & MADERA_GP1_OP_CFG_MASK))
result = 1;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
result = madera_pin_unmake_drv_str(priv, conf[1]);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
if (conf[0] & MADERA_GP1_DB_MASK)
result = 1;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (conf[0] & MADERA_GP1_DIR_MASK)
result = 1;
break;
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (conf[0] & MADERA_GP1_IP_CFG_MASK)
result = 1;
break;
case PIN_CONFIG_OUTPUT:
if ((conf[1] & MADERA_GP1_DIR_MASK) &&
(conf[0] & MADERA_GP1_LVL_MASK))
result = 1;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, result);
return 0;
}
static int madera_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
u16 conf[2] = {0, 0};
u16 mask[2] = {0, 0};
unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
unsigned int val;
int ret;
while (num_configs) {
dev_dbg(priv->dev, "%s config 0x%lx\n", __func__, *configs);
switch (pinconf_to_config_param(*configs)) {
case PIN_CONFIG_BIAS_BUS_HOLD:
mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
conf[1] |= MADERA_GP1_PU | MADERA_GP1_PD;
break;
case PIN_CONFIG_BIAS_DISABLE:
mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
conf[1] &= ~(MADERA_GP1_PU | MADERA_GP1_PD);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
conf[1] |= MADERA_GP1_PD;
conf[1] &= ~MADERA_GP1_PU;
break;
case PIN_CONFIG_BIAS_PULL_UP:
mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
conf[1] |= MADERA_GP1_PU;
conf[1] &= ~MADERA_GP1_PD;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
mask[0] |= MADERA_GP1_OP_CFG_MASK;
conf[0] |= MADERA_GP1_OP_CFG;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
mask[0] |= MADERA_GP1_OP_CFG_MASK;
conf[0] &= ~MADERA_GP1_OP_CFG;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
val = pinconf_to_config_argument(*configs);
mask[1] |= MADERA_GP1_DRV_STR_MASK;
conf[1] &= ~MADERA_GP1_DRV_STR_MASK;
conf[1] |= madera_pin_make_drv_str(priv, val);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
mask[0] |= MADERA_GP1_DB_MASK;
/*
* we can't configure debounce time per-pin so value
* is just a flag
*/
val = pinconf_to_config_argument(*configs);
if (val)
conf[0] |= MADERA_GP1_DB;
else
conf[0] &= ~MADERA_GP1_DB;
break;
case PIN_CONFIG_INPUT_ENABLE:
val = pinconf_to_config_argument(*configs);
mask[1] |= MADERA_GP1_DIR_MASK;
if (val)
conf[1] |= MADERA_GP1_DIR;
else
conf[1] &= ~MADERA_GP1_DIR;
break;
case PIN_CONFIG_INPUT_SCHMITT:
val = pinconf_to_config_argument(*configs);
mask[0] |= MADERA_GP1_IP_CFG;
if (val)
conf[0] |= MADERA_GP1_IP_CFG;
else
conf[0] &= ~MADERA_GP1_IP_CFG;
mask[1] |= MADERA_GP1_DIR_MASK;
conf[1] |= MADERA_GP1_DIR;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
mask[0] |= MADERA_GP1_IP_CFG;
conf[0] |= MADERA_GP1_IP_CFG;
mask[1] |= MADERA_GP1_DIR_MASK;
conf[1] |= MADERA_GP1_DIR;
break;
case PIN_CONFIG_OUTPUT:
val = pinconf_to_config_argument(*configs);
mask[0] |= MADERA_GP1_LVL_MASK;
if (val)
conf[0] |= MADERA_GP1_LVL;
else
conf[0] &= ~MADERA_GP1_LVL;
mask[1] |= MADERA_GP1_DIR_MASK;
conf[1] &= ~MADERA_GP1_DIR;
break;
default:
return -ENOTSUPP;
}
++configs;
--num_configs;
}
dev_dbg(priv->dev,
"%s gpio%d 0x%x:0x%x 0x%x:0x%x\n",
__func__, pin + 1, reg, conf[0], reg + 1, conf[1]);
ret = regmap_update_bits(priv->madera->regmap, reg, mask[0], conf[0]);
if (ret)
goto err;
++reg;
ret = regmap_update_bits(priv->madera->regmap, reg, mask[1], conf[1]);
if (ret)
goto err;
return 0;
err:
dev_err(priv->dev,
"Failed to write GPIO%d conf (%d) reg 0x%x\n",
pin + 1, ret, reg);
return ret;
}
static int madera_pin_conf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
const struct madera_pin_groups *pin_group;
unsigned int n_groups = priv->chip->n_pin_groups;
int i, ret;
dev_dbg(priv->dev, "%s setting group %s\n", __func__,
madera_get_group_name(pctldev, selector));
if (selector >= n_groups) {
/* group is a single pin, convert to pin number and set */
return madera_pin_conf_set(pctldev,
selector - n_groups,
configs,
num_configs);
} else {
pin_group = &priv->chip->pin_groups[selector];
for (i = 0; i < pin_group->n_pins; ++i) {
ret = madera_pin_conf_set(pctldev,
pin_group->pins[i],
configs,
num_configs);
if (ret)
return ret;
}
}
return 0;
}
static const struct pinconf_ops madera_pin_conf_ops = {
.is_generic = true,
.pin_config_get = madera_pin_conf_get,
.pin_config_set = madera_pin_conf_set,
.pin_config_group_set = madera_pin_conf_group_set,
};
static struct pinctrl_desc madera_pin_desc = {
.name = "madera-pinctrl",
.pins = madera_pins,
.pctlops = &madera_pin_group_ops,
.pmxops = &madera_pin_mux_ops,
.confops = &madera_pin_conf_ops,
.owner = THIS_MODULE,
};
static int madera_pin_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
const struct madera_pdata *pdata = &madera->pdata;
struct madera_pin_private *priv;
int ret;
BUILD_BUG_ON(ARRAY_SIZE(madera_pin_single_group_names) !=
ARRAY_SIZE(madera_pin_single_group_pins));
dev_dbg(&pdev->dev, "%s\n", __func__);
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->madera = madera;
switch (madera->type) {
case CS47L15:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L15))
priv->chip = &cs47l15_pin_chip;
break;
case CS47L35:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L35))
priv->chip = &cs47l35_pin_chip;
break;
case CS47L85:
case WM1840:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L85))
priv->chip = &cs47l85_pin_chip;
break;
case CS47L90:
case CS47L91:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L90))
priv->chip = &cs47l90_pin_chip;
break;
case CS42L92:
case CS47L92:
case CS47L93:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L92))
priv->chip = &cs47l92_pin_chip;
break;
default:
break;
}
if (!priv->chip)
return -ENODEV;
madera_pin_desc.npins = priv->chip->n_pins;
ret = devm_pinctrl_register_and_init(&pdev->dev,
&madera_pin_desc,
priv,
&priv->pctl);
if (ret) {
dev_err(priv->dev, "Failed pinctrl register (%d)\n", ret);
return ret;
}
/* if the configuration is provided through pdata, apply it */
if (pdata->gpio_configs) {
ret = pinctrl_register_mappings(pdata->gpio_configs,
pdata->n_gpio_configs);
if (ret) {
dev_err(priv->dev,
"Failed to register pdata mappings (%d)\n",
ret);
return ret;
}
}
ret = pinctrl_enable(priv->pctl);
if (ret) {
dev_err(priv->dev, "Failed to enable pinctrl (%d)\n", ret);
return ret;
}
platform_set_drvdata(pdev, priv);
dev_dbg(priv->dev, "pinctrl probed ok\n");
return 0;
}
static int madera_pin_remove(struct platform_device *pdev)
{
struct madera_pin_private *priv = platform_get_drvdata(pdev);
if (priv->madera->pdata.gpio_configs)
pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs);
return 0;
}
static struct platform_driver madera_pin_driver = {
.probe = madera_pin_probe,
.remove = madera_pin_remove,
.driver = {
.name = "madera-pinctrl",
},
};
module_platform_driver(madera_pin_driver);
MODULE_DESCRIPTION("Madera pinctrl driver");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-madera-core.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L85
*
* Copyright (C) 2016-2017 Cirrus Logic
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l85_mif1_pins[] = { 8, 9 };
static const unsigned int cs47l85_mif2_pins[] = { 10, 11 };
static const unsigned int cs47l85_mif3_pins[] = { 12, 13 };
static const unsigned int cs47l85_aif1_pins[] = { 14, 15, 16, 17 };
static const unsigned int cs47l85_aif2_pins[] = { 18, 19, 20, 21 };
static const unsigned int cs47l85_aif3_pins[] = { 22, 23, 24, 25 };
static const unsigned int cs47l85_aif4_pins[] = { 26, 27, 28, 29 };
static const unsigned int cs47l85_dmic4_pins[] = { 30, 31 };
static const unsigned int cs47l85_dmic5_pins[] = { 32, 33 };
static const unsigned int cs47l85_dmic6_pins[] = { 34, 35 };
static const unsigned int cs47l85_spk1_pins[] = { 36, 38 };
static const unsigned int cs47l85_spk2_pins[] = { 37, 39 };
static const struct madera_pin_groups cs47l85_pin_groups[] = {
{ "aif1", cs47l85_aif1_pins, ARRAY_SIZE(cs47l85_aif1_pins) },
{ "aif2", cs47l85_aif2_pins, ARRAY_SIZE(cs47l85_aif2_pins) },
{ "aif3", cs47l85_aif3_pins, ARRAY_SIZE(cs47l85_aif3_pins) },
{ "aif4", cs47l85_aif4_pins, ARRAY_SIZE(cs47l85_aif4_pins) },
{ "mif1", cs47l85_mif1_pins, ARRAY_SIZE(cs47l85_mif1_pins) },
{ "mif2", cs47l85_mif2_pins, ARRAY_SIZE(cs47l85_mif2_pins) },
{ "mif3", cs47l85_mif3_pins, ARRAY_SIZE(cs47l85_mif3_pins) },
{ "dmic4", cs47l85_dmic4_pins, ARRAY_SIZE(cs47l85_dmic4_pins) },
{ "dmic5", cs47l85_dmic5_pins, ARRAY_SIZE(cs47l85_dmic5_pins) },
{ "dmic6", cs47l85_dmic6_pins, ARRAY_SIZE(cs47l85_dmic6_pins) },
{ "pdmspk1", cs47l85_spk1_pins, ARRAY_SIZE(cs47l85_spk1_pins) },
{ "pdmspk2", cs47l85_spk2_pins, ARRAY_SIZE(cs47l85_spk2_pins) },
};
const struct madera_pin_chip cs47l85_pin_chip = {
.n_pins = CS47L85_NUM_GPIOS,
.pin_groups = cs47l85_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l85_pin_groups),
};
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs47l85.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L90
*
* Copyright (C) 2016-2017 Cirrus Logic
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l90_mif1_pins[] = { 8, 9 };
static const unsigned int cs47l90_mif2_pins[] = { 10, 11 };
static const unsigned int cs47l90_mif3_pins[] = { 12, 13 };
static const unsigned int cs47l90_aif1_pins[] = { 14, 15, 16, 17 };
static const unsigned int cs47l90_aif2_pins[] = { 18, 19, 20, 21 };
static const unsigned int cs47l90_aif3_pins[] = { 22, 23, 24, 25 };
static const unsigned int cs47l90_aif4_pins[] = { 26, 27, 28, 29 };
static const unsigned int cs47l90_dmic4_pins[] = { 30, 31 };
static const unsigned int cs47l90_dmic5_pins[] = { 32, 33 };
static const unsigned int cs47l90_dmic3_pins[] = { 34, 35 };
static const unsigned int cs47l90_spk1_pins[] = { 36, 37 };
static const struct madera_pin_groups cs47l90_pin_groups[] = {
{ "aif1", cs47l90_aif1_pins, ARRAY_SIZE(cs47l90_aif1_pins) },
{ "aif2", cs47l90_aif2_pins, ARRAY_SIZE(cs47l90_aif2_pins) },
{ "aif3", cs47l90_aif3_pins, ARRAY_SIZE(cs47l90_aif3_pins) },
{ "aif4", cs47l90_aif4_pins, ARRAY_SIZE(cs47l90_aif4_pins) },
{ "mif1", cs47l90_mif1_pins, ARRAY_SIZE(cs47l90_mif1_pins) },
{ "mif2", cs47l90_mif2_pins, ARRAY_SIZE(cs47l90_mif2_pins) },
{ "mif3", cs47l90_mif3_pins, ARRAY_SIZE(cs47l90_mif3_pins) },
{ "dmic3", cs47l90_dmic3_pins, ARRAY_SIZE(cs47l90_dmic3_pins) },
{ "dmic4", cs47l90_dmic4_pins, ARRAY_SIZE(cs47l90_dmic4_pins) },
{ "dmic5", cs47l90_dmic5_pins, ARRAY_SIZE(cs47l90_dmic5_pins) },
{ "pdmspk1", cs47l90_spk1_pins, ARRAY_SIZE(cs47l90_spk1_pins) },
};
const struct madera_pin_chip cs47l90_pin_chip = {
.n_pins = CS47L90_NUM_GPIOS,
.pin_groups = cs47l90_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l90_pin_groups),
};
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs47l90.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L15
*
* Copyright (C) 2018-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l15_aif1_pins[] = { 0, 1, 2, 3 };
static const unsigned int cs47l15_aif2_pins[] = { 4, 5, 6, 7 };
static const unsigned int cs47l15_aif3_pins[] = { 8, 9, 10, 11 };
static const unsigned int cs47l15_spk1_pins[] = { 12, 13, 14 };
static const struct madera_pin_groups cs47l15_pin_groups[] = {
{ "aif1", cs47l15_aif1_pins, ARRAY_SIZE(cs47l15_aif1_pins) },
{ "aif2", cs47l15_aif2_pins, ARRAY_SIZE(cs47l15_aif2_pins) },
{ "aif3", cs47l15_aif3_pins, ARRAY_SIZE(cs47l15_aif3_pins) },
{ "pdmspk1", cs47l15_spk1_pins, ARRAY_SIZE(cs47l15_spk1_pins) },
};
const struct madera_pin_chip cs47l15_pin_chip = {
.n_pins = CS47L15_NUM_GPIOS,
.pin_groups = cs47l15_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l15_pin_groups),
};
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs47l15.c
|
// SPDX-License-Identifier: GPL-2.0
//
// CS42L43 Pinctrl and GPIO driver
//
// Copyright (c) 2023 Cirrus Logic, Inc. and
// Cirrus Logic International Semiconductor Ltd.
#include <linux/bits.h>
#include <linux/build_bug.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/cs42l43.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/string_helpers.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include "../pinctrl-utils.h"
#define CS42L43_NUM_GPIOS 3
struct cs42l43_pin {
struct gpio_chip gpio_chip;
struct device *dev;
struct regmap *regmap;
bool shutters_locked;
};
struct cs42l43_pin_data {
unsigned int reg;
unsigned int shift;
unsigned int mask;
};
#define CS42L43_PIN(_number, _name, _reg, _field) { \
.number = _number, .name = _name, \
.drv_data = &((struct cs42l43_pin_data){ \
.reg = CS42L43_##_reg, \
.shift = CS42L43_##_field##_DRV_SHIFT, \
.mask = CS42L43_##_field##_DRV_MASK, \
}), \
}
static const struct pinctrl_pin_desc cs42l43_pin_pins[] = {
CS42L43_PIN(0, "gpio1", DRV_CTRL4, GPIO1),
CS42L43_PIN(1, "gpio2", DRV_CTRL4, GPIO2),
CS42L43_PIN(2, "gpio3", DRV_CTRL4, GPIO3),
CS42L43_PIN(3, "asp_dout", DRV_CTRL1, ASP_DOUT),
CS42L43_PIN(4, "asp_fsync", DRV_CTRL1, ASP_FSYNC),
CS42L43_PIN(5, "asp_bclk", DRV_CTRL1, ASP_BCLK),
CS42L43_PIN(6, "pdmout2_clk", DRV_CTRL3, PDMOUT2_CLK),
CS42L43_PIN(7, "pdmout2_data", DRV_CTRL3, PDMOUT2_DATA),
CS42L43_PIN(8, "pdmout1_clk", DRV_CTRL3, PDMOUT1_CLK),
CS42L43_PIN(9, "pdmout1_data", DRV_CTRL3, PDMOUT1_DATA),
CS42L43_PIN(10, "i2c_sda", DRV_CTRL3, I2C_SDA),
CS42L43_PIN(11, "i2c_scl", DRV_CTRL_5, I2C_SCL),
CS42L43_PIN(12, "spi_miso", DRV_CTRL3, SPI_MISO),
CS42L43_PIN(13, "spi_sck", DRV_CTRL_5, SPI_SCK),
CS42L43_PIN(14, "spi_ssb", DRV_CTRL_5, SPI_SSB),
};
static const unsigned int cs42l43_pin_gpio1_pins[] = { 0 };
static const unsigned int cs42l43_pin_gpio2_pins[] = { 1 };
static const unsigned int cs42l43_pin_gpio3_pins[] = { 2 };
static const unsigned int cs42l43_pin_asp_pins[] = { 3, 4, 5 };
static const unsigned int cs42l43_pin_pdmout2_pins[] = { 6, 7 };
static const unsigned int cs42l43_pin_pdmout1_pins[] = { 8, 9 };
static const unsigned int cs42l43_pin_i2c_pins[] = { 10, 11 };
static const unsigned int cs42l43_pin_spi_pins[] = { 12, 13, 14 };
#define CS42L43_PINGROUP(_name) \
PINCTRL_PINGROUP(#_name, cs42l43_pin_##_name##_pins, \
ARRAY_SIZE(cs42l43_pin_##_name##_pins))
static const struct pingroup cs42l43_pin_groups[] = {
CS42L43_PINGROUP(gpio1),
CS42L43_PINGROUP(gpio2),
CS42L43_PINGROUP(gpio3),
CS42L43_PINGROUP(asp),
CS42L43_PINGROUP(pdmout2),
CS42L43_PINGROUP(pdmout1),
CS42L43_PINGROUP(i2c),
CS42L43_PINGROUP(spi),
};
static int cs42l43_pin_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(cs42l43_pin_groups);
}
static const char *cs42l43_pin_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group_idx)
{
return cs42l43_pin_groups[group_idx].name;
}
static int cs42l43_pin_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group_idx,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = cs42l43_pin_groups[group_idx].pins;
*num_pins = cs42l43_pin_groups[group_idx].npins;
return 0;
}
static const struct pinctrl_ops cs42l43_pin_group_ops = {
.get_groups_count = cs42l43_pin_get_groups_count,
.get_group_name = cs42l43_pin_get_group_name,
.get_group_pins = cs42l43_pin_get_group_pins,
#if IS_ENABLED(CONFIG_OF)
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
#endif
};
enum cs42l43_pin_funcs {
CS42L43_FUNC_GPIO,
CS42L43_FUNC_SPDIF,
CS42L43_FUNC_IRQ,
CS42L43_FUNC_MIC_SHT,
CS42L43_FUNC_SPK_SHT,
CS42L43_FUNC_MAX
};
static const char * const cs42l43_pin_funcs[] = {
"gpio", "spdif", "irq", "mic-shutter", "spk-shutter",
};
static const char * const cs42l43_pin_gpio_groups[] = { "gpio1", "gpio3" };
static const char * const cs42l43_pin_spdif_groups[] = { "gpio3" };
static const char * const cs42l43_pin_irq_groups[] = { "gpio1" };
static const char * const cs42l43_pin_shutter_groups[] = { "gpio1", "gpio2", "gpio3" };
static const struct pinfunction cs42l43_pin_func_groups[] = {
PINCTRL_PINFUNCTION("gpio", cs42l43_pin_gpio_groups,
ARRAY_SIZE(cs42l43_pin_gpio_groups)),
PINCTRL_PINFUNCTION("spdif", cs42l43_pin_spdif_groups,
ARRAY_SIZE(cs42l43_pin_spdif_groups)),
PINCTRL_PINFUNCTION("irq", cs42l43_pin_irq_groups,
ARRAY_SIZE(cs42l43_pin_irq_groups)),
PINCTRL_PINFUNCTION("mic-shutter", cs42l43_pin_shutter_groups,
ARRAY_SIZE(cs42l43_pin_shutter_groups)),
PINCTRL_PINFUNCTION("spk-shutter", cs42l43_pin_shutter_groups,
ARRAY_SIZE(cs42l43_pin_shutter_groups)),
};
static_assert(ARRAY_SIZE(cs42l43_pin_funcs) == CS42L43_FUNC_MAX);
static_assert(ARRAY_SIZE(cs42l43_pin_func_groups) == CS42L43_FUNC_MAX);
static int cs42l43_pin_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(cs42l43_pin_funcs);
}
static const char *cs42l43_pin_get_func_name(struct pinctrl_dev *pctldev,
unsigned int func_idx)
{
return cs42l43_pin_funcs[func_idx];
}
static int cs42l43_pin_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int func_idx,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = cs42l43_pin_func_groups[func_idx].groups;
*num_groups = cs42l43_pin_func_groups[func_idx].ngroups;
return 0;
}
static int cs42l43_pin_set_mux(struct pinctrl_dev *pctldev,
unsigned int func_idx, unsigned int group_idx)
{
struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int reg, mask, val;
dev_dbg(priv->dev, "Setting %s to %s\n",
cs42l43_pin_groups[group_idx].name, cs42l43_pin_funcs[func_idx]);
switch (func_idx) {
case CS42L43_FUNC_MIC_SHT:
reg = CS42L43_SHUTTER_CONTROL;
mask = CS42L43_MIC_SHUTTER_CFG_MASK;
val = 0x2 << (group_idx + CS42L43_MIC_SHUTTER_CFG_SHIFT);
break;
case CS42L43_FUNC_SPK_SHT:
reg = CS42L43_SHUTTER_CONTROL;
mask = CS42L43_SPK_SHUTTER_CFG_MASK;
val = 0x2 << (group_idx + CS42L43_SPK_SHUTTER_CFG_SHIFT);
break;
default:
reg = CS42L43_GPIO_FN_SEL;
mask = BIT(group_idx + CS42L43_GPIO1_FN_SEL_SHIFT);
val = (func_idx == CS42L43_FUNC_GPIO) ?
(0x1 << (group_idx + CS42L43_GPIO1_FN_SEL_SHIFT)) : 0;
break;
}
if (priv->shutters_locked && reg == CS42L43_SHUTTER_CONTROL) {
dev_err(priv->dev, "Shutter configuration not available\n");
return -EPERM;
}
return regmap_update_bits(priv->regmap, reg, mask, val);
}
static int cs42l43_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int shift = offset + CS42L43_GPIO1_DIR_SHIFT;
int ret;
dev_dbg(priv->dev, "Setting gpio%d to %s\n",
offset + 1, input ? "input" : "output");
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for direction: %d\n", ret);
return ret;
}
ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
BIT(shift), !!input << shift);
if (ret)
dev_err(priv->dev, "Failed to set gpio%d direction: %d\n",
offset + 1, ret);
pm_runtime_put(priv->dev);
return ret;
}
static int cs42l43_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
return cs42l43_pin_set_mux(pctldev, 0, offset);
}
static void cs42l43_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
cs42l43_gpio_set_direction(pctldev, range, offset, true);
}
static const struct pinmux_ops cs42l43_pin_mux_ops = {
.get_functions_count = cs42l43_pin_get_func_count,
.get_function_name = cs42l43_pin_get_func_name,
.get_function_groups = cs42l43_pin_get_func_groups,
.set_mux = cs42l43_pin_set_mux,
.gpio_request_enable = cs42l43_gpio_request_enable,
.gpio_disable_free = cs42l43_gpio_disable_free,
.gpio_set_direction = cs42l43_gpio_set_direction,
.strict = true,
};
static const unsigned int cs42l43_pin_drv_str_ma[] = { 1, 2, 4, 8, 9, 10, 12, 16 };
static inline int cs42l43_pin_get_drv_str(struct cs42l43_pin *priv, unsigned int pin)
{
const struct cs42l43_pin_data *pdat = cs42l43_pin_pins[pin].drv_data;
unsigned int val;
int ret;
ret = regmap_read(priv->regmap, pdat->reg, &val);
if (ret)
return ret;
return cs42l43_pin_drv_str_ma[(val & pdat->mask) >> pdat->shift];
}
static inline int cs42l43_pin_set_drv_str(struct cs42l43_pin *priv, unsigned int pin,
unsigned int ma)
{
const struct cs42l43_pin_data *pdat = cs42l43_pin_pins[pin].drv_data;
int i;
for (i = 0; i < ARRAY_SIZE(cs42l43_pin_drv_str_ma); i++) {
if (ma == cs42l43_pin_drv_str_ma[i]) {
if ((i << pdat->shift) > pdat->mask)
goto err;
dev_dbg(priv->dev, "Set drive strength for %s to %d mA\n",
cs42l43_pin_pins[pin].name, ma);
return regmap_update_bits(priv->regmap, pdat->reg,
pdat->mask, i << pdat->shift);
}
}
err:
dev_err(priv->dev, "Invalid drive strength for %s: %d mA\n",
cs42l43_pin_pins[pin].name, ma);
return -EINVAL;
}
static inline int cs42l43_pin_get_db(struct cs42l43_pin *priv, unsigned int pin)
{
unsigned int val;
int ret;
if (pin >= CS42L43_NUM_GPIOS)
return -ENOTSUPP;
ret = regmap_read(priv->regmap, CS42L43_GPIO_CTRL2, &val);
if (ret)
return ret;
if (val & (CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin))
return 0;
return 85; // Debounce is roughly 85uS
}
static inline int cs42l43_pin_set_db(struct cs42l43_pin *priv, unsigned int pin,
unsigned int us)
{
if (pin >= CS42L43_NUM_GPIOS)
return -ENOTSUPP;
dev_dbg(priv->dev, "Set debounce %s for %s\n",
str_on_off(us), cs42l43_pin_pins[pin].name);
return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2,
CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin,
!!us << pin);
}
static int cs42l43_pin_config_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
int ret;
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
ret = cs42l43_pin_get_drv_str(priv, pin);
if (ret < 0)
return ret;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
ret = cs42l43_pin_get_db(priv, pin);
if (ret < 0)
return ret;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, ret);
return 0;
}
static int cs42l43_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct cs42l43_pin *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int val;
int ret;
while (num_configs) {
val = pinconf_to_config_argument(*configs);
switch (pinconf_to_config_param(*configs)) {
case PIN_CONFIG_DRIVE_STRENGTH:
ret = cs42l43_pin_set_drv_str(priv, pin, val);
if (ret)
return ret;
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
ret = cs42l43_pin_set_db(priv, pin, val);
if (ret)
return ret;
break;
default:
return -ENOTSUPP;
}
configs++;
num_configs--;
}
return 0;
}
static int cs42l43_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned long *config)
{
int i, ret;
for (i = 0; i < cs42l43_pin_groups[selector].npins; ++i) {
ret = cs42l43_pin_config_get(pctldev,
cs42l43_pin_groups[selector].pins[i],
config);
if (ret)
return ret;
}
return 0;
}
static int cs42l43_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
for (i = 0; i < cs42l43_pin_groups[selector].npins; ++i) {
ret = cs42l43_pin_config_set(pctldev,
cs42l43_pin_groups[selector].pins[i],
configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops cs42l43_pin_conf_ops = {
.is_generic = true,
.pin_config_get = cs42l43_pin_config_get,
.pin_config_set = cs42l43_pin_config_set,
.pin_config_group_get = cs42l43_pin_config_group_get,
.pin_config_group_set = cs42l43_pin_config_group_set,
};
static struct pinctrl_desc cs42l43_pin_desc = {
.name = "cs42l43-pinctrl",
.owner = THIS_MODULE,
.pins = cs42l43_pin_pins,
.npins = ARRAY_SIZE(cs42l43_pin_pins),
.pctlops = &cs42l43_pin_group_ops,
.pmxops = &cs42l43_pin_mux_ops,
.confops = &cs42l43_pin_conf_ops,
};
static int cs42l43_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct cs42l43_pin *priv = gpiochip_get_data(chip);
unsigned int val;
int ret;
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for get: %d\n", ret);
return ret;
}
ret = regmap_read(priv->regmap, CS42L43_GPIO_STS, &val);
if (ret)
dev_err(priv->dev, "Failed to get gpio%d: %d\n", offset + 1, ret);
else
ret = !!(val & BIT(offset + CS42L43_GPIO1_STS_SHIFT));
pm_runtime_put(priv->dev);
return ret;
}
static void cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct cs42l43_pin *priv = gpiochip_get_data(chip);
unsigned int shift = offset + CS42L43_GPIO1_LVL_SHIFT;
int ret;
dev_dbg(priv->dev, "Setting gpio%d to %s\n",
offset + 1, value ? "high" : "low");
ret = pm_runtime_resume_and_get(priv->dev);
if (ret) {
dev_err(priv->dev, "Failed to resume for set: %d\n", ret);
return;
}
ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1,
BIT(shift), value << shift);
if (ret)
dev_err(priv->dev, "Failed to set gpio%d: %d\n", offset + 1, ret);
pm_runtime_put(priv->dev);
}
static int cs42l43_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int cs42l43_gpio_direction_out(struct gpio_chip *chip,
unsigned int offset, int value)
{
cs42l43_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int cs42l43_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct cs42l43_pin *priv = gpiochip_get_data(chip);
int ret;
ret = gpiochip_add_pin_range(&priv->gpio_chip, priv->gpio_chip.label,
0, 0, CS42L43_NUM_GPIOS);
if (ret)
dev_err(priv->dev, "Failed to add GPIO pin range: %d\n", ret);
return ret;
}
static int cs42l43_pin_probe(struct platform_device *pdev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
struct cs42l43_pin *priv;
struct pinctrl_dev *pctldev;
struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->regmap = cs42l43->regmap;
priv->shutters_locked = cs42l43->hw_lock;
priv->gpio_chip.request = gpiochip_generic_request;
priv->gpio_chip.free = gpiochip_generic_free;
priv->gpio_chip.direction_input = cs42l43_gpio_direction_in;
priv->gpio_chip.direction_output = cs42l43_gpio_direction_out;
priv->gpio_chip.add_pin_ranges = cs42l43_gpio_add_pin_ranges;
priv->gpio_chip.get = cs42l43_gpio_get;
priv->gpio_chip.set = cs42l43_gpio_set;
priv->gpio_chip.label = dev_name(priv->dev);
priv->gpio_chip.parent = priv->dev;
priv->gpio_chip.can_sleep = true;
priv->gpio_chip.base = -1;
priv->gpio_chip.ngpio = CS42L43_NUM_GPIOS;
if (is_of_node(fwnode)) {
fwnode = fwnode_get_named_child_node(fwnode, "pinctrl");
if (fwnode && !fwnode->dev)
fwnode->dev = priv->dev;
}
priv->gpio_chip.fwnode = fwnode;
device_set_node(priv->dev, fwnode);
devm_pm_runtime_enable(priv->dev);
pm_runtime_idle(priv->dev);
pctldev = devm_pinctrl_register(priv->dev, &cs42l43_pin_desc, priv);
if (IS_ERR(pctldev))
return dev_err_probe(priv->dev, PTR_ERR(pctldev),
"Failed to register pinctrl\n");
ret = devm_gpiochip_add_data(priv->dev, &priv->gpio_chip, priv);
if (ret)
return dev_err_probe(priv->dev, ret,
"Failed to register gpiochip\n");
return 0;
}
static const struct platform_device_id cs42l43_pin_id_table[] = {
{ "cs42l43-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(platform, cs42l43_pin_id_table);
static struct platform_driver cs42l43_pin_driver = {
.driver = {
.name = "cs42l43-pinctrl",
},
.probe = cs42l43_pin_probe,
.id_table = cs42l43_pin_id_table,
};
module_platform_driver(cs42l43_pin_driver);
MODULE_DESCRIPTION("CS42L43 Pinctrl Driver");
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Lochnagar pin and GPIO control
*
* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/mfd/lochnagar.h>
#include <linux/mfd/lochnagar1_regs.h>
#include <linux/mfd/lochnagar2_regs.h>
#include <dt-bindings/pinctrl/lochnagar.h>
#include "../pinctrl-utils.h"
#define LN2_NUM_GPIO_CHANNELS 16
#define LN_CDC_AIF1_STR "codec-aif1"
#define LN_CDC_AIF2_STR "codec-aif2"
#define LN_CDC_AIF3_STR "codec-aif3"
#define LN_DSP_AIF1_STR "dsp-aif1"
#define LN_DSP_AIF2_STR "dsp-aif2"
#define LN_PSIA1_STR "psia1"
#define LN_PSIA2_STR "psia2"
#define LN_GF_AIF1_STR "gf-aif1"
#define LN_GF_AIF2_STR "gf-aif2"
#define LN_GF_AIF3_STR "gf-aif3"
#define LN_GF_AIF4_STR "gf-aif4"
#define LN_SPDIF_AIF_STR "spdif-aif"
#define LN_USB_AIF1_STR "usb-aif1"
#define LN_USB_AIF2_STR "usb-aif2"
#define LN_ADAT_AIF_STR "adat-aif"
#define LN_SOUNDCARD_AIF_STR "soundcard-aif"
#define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
.name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
.shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
}
#define LN_PIN_SAIF(REV, ID, NAME) \
static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
{ .name = NAME, .type = LN_PTYPE_AIF, }
#define LN_PIN_AIF(REV, ID) \
LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
#define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
#define LN1_PIN_MUX(ID, NAME) \
static const struct lochnagar_pin lochnagar1_##ID##_pin = \
{ .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, }
#define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID)
#define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
#define LN2_PIN_MUX(ID, NAME) \
static const struct lochnagar_pin lochnagar2_##ID##_pin = \
{ .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, }
#define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID)
#define LN2_PIN_GAI(ID) \
LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
#define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \
.number = LOCHNAGAR##REV##_PIN_##ID, \
.name = lochnagar##REV##_##ID##_pin.name, \
.drv_data = (void *)&lochnagar##REV##_##ID##_pin, \
}
#define LN1_PIN(ID) LN_PIN(1, ID)
#define LN2_PIN(ID) LN_PIN(2, ID)
#define LN_PINS(REV, ID) \
LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \
LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
#define LN1_PINS(ID) LN_PINS(1, ID)
#define LN2_PINS(ID) LN_PINS(2, ID)
enum {
LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS,
LOCHNAGAR1_PIN_GF_GPIO3,
LOCHNAGAR1_PIN_GF_GPIO7,
LOCHNAGAR1_PIN_LED1,
LOCHNAGAR1_PIN_LED2,
LOCHNAGAR1_PIN_CDC_AIF1_BCLK,
LOCHNAGAR1_PIN_CDC_AIF1_LRCLK,
LOCHNAGAR1_PIN_CDC_AIF1_RXDAT,
LOCHNAGAR1_PIN_CDC_AIF1_TXDAT,
LOCHNAGAR1_PIN_CDC_AIF2_BCLK,
LOCHNAGAR1_PIN_CDC_AIF2_LRCLK,
LOCHNAGAR1_PIN_CDC_AIF2_RXDAT,
LOCHNAGAR1_PIN_CDC_AIF2_TXDAT,
LOCHNAGAR1_PIN_CDC_AIF3_BCLK,
LOCHNAGAR1_PIN_CDC_AIF3_LRCLK,
LOCHNAGAR1_PIN_CDC_AIF3_RXDAT,
LOCHNAGAR1_PIN_CDC_AIF3_TXDAT,
LOCHNAGAR1_PIN_DSP_AIF1_BCLK,
LOCHNAGAR1_PIN_DSP_AIF1_LRCLK,
LOCHNAGAR1_PIN_DSP_AIF1_RXDAT,
LOCHNAGAR1_PIN_DSP_AIF1_TXDAT,
LOCHNAGAR1_PIN_DSP_AIF2_BCLK,
LOCHNAGAR1_PIN_DSP_AIF2_LRCLK,
LOCHNAGAR1_PIN_DSP_AIF2_RXDAT,
LOCHNAGAR1_PIN_DSP_AIF2_TXDAT,
LOCHNAGAR1_PIN_PSIA1_BCLK,
LOCHNAGAR1_PIN_PSIA1_LRCLK,
LOCHNAGAR1_PIN_PSIA1_RXDAT,
LOCHNAGAR1_PIN_PSIA1_TXDAT,
LOCHNAGAR1_PIN_PSIA2_BCLK,
LOCHNAGAR1_PIN_PSIA2_LRCLK,
LOCHNAGAR1_PIN_PSIA2_RXDAT,
LOCHNAGAR1_PIN_PSIA2_TXDAT,
LOCHNAGAR1_PIN_SPDIF_AIF_BCLK,
LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK,
LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT,
LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT,
LOCHNAGAR1_PIN_GF_AIF3_BCLK,
LOCHNAGAR1_PIN_GF_AIF3_RXDAT,
LOCHNAGAR1_PIN_GF_AIF3_LRCLK,
LOCHNAGAR1_PIN_GF_AIF3_TXDAT,
LOCHNAGAR1_PIN_GF_AIF4_BCLK,
LOCHNAGAR1_PIN_GF_AIF4_RXDAT,
LOCHNAGAR1_PIN_GF_AIF4_LRCLK,
LOCHNAGAR1_PIN_GF_AIF4_TXDAT,
LOCHNAGAR1_PIN_GF_AIF1_BCLK,
LOCHNAGAR1_PIN_GF_AIF1_RXDAT,
LOCHNAGAR1_PIN_GF_AIF1_LRCLK,
LOCHNAGAR1_PIN_GF_AIF1_TXDAT,
LOCHNAGAR1_PIN_GF_AIF2_BCLK,
LOCHNAGAR1_PIN_GF_AIF2_RXDAT,
LOCHNAGAR1_PIN_GF_AIF2_LRCLK,
LOCHNAGAR1_PIN_GF_AIF2_TXDAT,
LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS,
LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK,
LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT,
LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT,
LOCHNAGAR2_PIN_USB_AIF1_BCLK,
LOCHNAGAR2_PIN_USB_AIF1_LRCLK,
LOCHNAGAR2_PIN_USB_AIF1_RXDAT,
LOCHNAGAR2_PIN_USB_AIF1_TXDAT,
LOCHNAGAR2_PIN_USB_AIF2_BCLK,
LOCHNAGAR2_PIN_USB_AIF2_LRCLK,
LOCHNAGAR2_PIN_USB_AIF2_RXDAT,
LOCHNAGAR2_PIN_USB_AIF2_TXDAT,
LOCHNAGAR2_PIN_ADAT_AIF_BCLK,
LOCHNAGAR2_PIN_ADAT_AIF_LRCLK,
LOCHNAGAR2_PIN_ADAT_AIF_RXDAT,
LOCHNAGAR2_PIN_ADAT_AIF_TXDAT,
LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK,
LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK,
LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT,
LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT,
};
enum lochnagar_pin_type {
LN_PTYPE_GPIO,
LN_PTYPE_MUX,
LN_PTYPE_AIF,
LN_PTYPE_COUNT,
};
struct lochnagar_pin {
const char name[20];
enum lochnagar_pin_type type;
unsigned int reg;
int shift;
bool invert;
};
LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1);
LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1);
LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
LN1_PIN_MUX(GF_GPIO2, "gf-gpio2");
LN1_PIN_MUX(GF_GPIO3, "gf-gpio3");
LN1_PIN_MUX(GF_GPIO7, "gf-gpio7");
LN1_PIN_MUX(LED1, "led1");
LN1_PIN_MUX(LED2, "led2");
LN1_PIN_AIF(CDC_AIF1);
LN1_PIN_AIF(CDC_AIF2);
LN1_PIN_AIF(CDC_AIF3);
LN1_PIN_AIF(DSP_AIF1);
LN1_PIN_AIF(DSP_AIF2);
LN1_PIN_AIF(PSIA1);
LN1_PIN_AIF(PSIA2);
LN1_PIN_AIF(SPDIF_AIF);
LN1_PIN_AIF(GF_AIF1);
LN1_PIN_AIF(GF_AIF2);
LN1_PIN_AIF(GF_AIF3);
LN1_PIN_AIF(GF_AIF4);
LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1);
LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1);
LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0);
LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0);
LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0);
LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1);
LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1");
LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2");
LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3");
LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4");
LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5");
LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6");
LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1");
LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2");
LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3");
LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4");
LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5");
LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6");
LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7");
LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8");
LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1");
LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2");
LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3");
LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4");
LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5");
LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6");
LN2_PIN_MUX(GF_GPIO2, "gf-gpio2");
LN2_PIN_MUX(GF_GPIO3, "gf-gpio3");
LN2_PIN_MUX(GF_GPIO7, "gf-gpio7");
LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx");
LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx");
LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx");
LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx");
LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx");
LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx");
LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx");
LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1");
LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1");
LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2");
LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2");
LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1");
LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1");
LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2");
LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2");
LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3");
LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3");
LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4");
LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4");
LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1");
LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1");
LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2");
LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2");
LN2_PIN_MUX(I2C2_SCL, "i2c2-scl");
LN2_PIN_MUX(I2C2_SDA, "i2c2-sda");
LN2_PIN_MUX(I2C3_SCL, "i2c3-scl");
LN2_PIN_MUX(I2C3_SDA, "i2c3-sda");
LN2_PIN_MUX(I2C4_SCL, "i2c4-scl");
LN2_PIN_MUX(I2C4_SDA, "i2c4-sda");
LN2_PIN_MUX(DSP_STANDBY, "dsp-standby");
LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1");
LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2");
LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin");
LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk");
LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk");
LN2_PIN_MUX(GF_GPIO1, "gf-gpio1");
LN2_PIN_MUX(GF_GPIO5, "gf-gpio5");
LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20");
LN2_PIN_GAI(CDC_AIF1);
LN2_PIN_GAI(CDC_AIF2);
LN2_PIN_GAI(CDC_AIF3);
LN2_PIN_GAI(DSP_AIF1);
LN2_PIN_GAI(DSP_AIF2);
LN2_PIN_GAI(PSIA1);
LN2_PIN_GAI(PSIA2);
LN2_PIN_GAI(GF_AIF1);
LN2_PIN_GAI(GF_AIF2);
LN2_PIN_GAI(GF_AIF3);
LN2_PIN_GAI(GF_AIF4);
LN2_PIN_AIF(SPDIF_AIF);
LN2_PIN_AIF(USB_AIF1);
LN2_PIN_AIF(USB_AIF2);
LN2_PIN_AIF(ADAT_AIF);
LN2_PIN_AIF(SOUNDCARD_AIF);
static const struct pinctrl_pin_desc lochnagar1_pins[] = {
LN1_PIN(CDC_RESET), LN1_PIN(DSP_RESET), LN1_PIN(CDC_CIF1MODE),
LN1_PIN(GF_GPIO2), LN1_PIN(GF_GPIO3), LN1_PIN(GF_GPIO7),
LN1_PIN(LED1), LN1_PIN(LED2),
LN1_PINS(CDC_AIF1), LN1_PINS(CDC_AIF2), LN1_PINS(CDC_AIF3),
LN1_PINS(DSP_AIF1), LN1_PINS(DSP_AIF2),
LN1_PINS(PSIA1), LN1_PINS(PSIA2),
LN1_PINS(SPDIF_AIF),
LN1_PINS(GF_AIF1), LN1_PINS(GF_AIF2),
LN1_PINS(GF_AIF3), LN1_PINS(GF_AIF4),
};
static const struct pinctrl_pin_desc lochnagar2_pins[] = {
LN2_PIN(CDC_RESET), LN2_PIN(DSP_RESET), LN2_PIN(CDC_CIF1MODE),
LN2_PIN(CDC_LDOENA),
LN2_PIN(SPDIF_HWMODE), LN2_PIN(SPDIF_RESET),
LN2_PIN(FPGA_GPIO1), LN2_PIN(FPGA_GPIO2), LN2_PIN(FPGA_GPIO3),
LN2_PIN(FPGA_GPIO4), LN2_PIN(FPGA_GPIO5), LN2_PIN(FPGA_GPIO6),
LN2_PIN(CDC_GPIO1), LN2_PIN(CDC_GPIO2), LN2_PIN(CDC_GPIO3),
LN2_PIN(CDC_GPIO4), LN2_PIN(CDC_GPIO5), LN2_PIN(CDC_GPIO6),
LN2_PIN(CDC_GPIO7), LN2_PIN(CDC_GPIO8),
LN2_PIN(DSP_GPIO1), LN2_PIN(DSP_GPIO2), LN2_PIN(DSP_GPIO3),
LN2_PIN(DSP_GPIO4), LN2_PIN(DSP_GPIO5), LN2_PIN(DSP_GPIO6),
LN2_PIN(DSP_GPIO20),
LN2_PIN(GF_GPIO1), LN2_PIN(GF_GPIO2), LN2_PIN(GF_GPIO3),
LN2_PIN(GF_GPIO5), LN2_PIN(GF_GPIO7),
LN2_PINS(CDC_AIF1), LN2_PINS(CDC_AIF2), LN2_PINS(CDC_AIF3),
LN2_PINS(DSP_AIF1), LN2_PINS(DSP_AIF2),
LN2_PINS(PSIA1), LN2_PINS(PSIA2),
LN2_PINS(GF_AIF1), LN2_PINS(GF_AIF2),
LN2_PINS(GF_AIF3), LN2_PINS(GF_AIF4),
LN2_PIN(DSP_UART1_RX), LN2_PIN(DSP_UART1_TX),
LN2_PIN(DSP_UART2_RX), LN2_PIN(DSP_UART2_TX),
LN2_PIN(GF_UART2_RX), LN2_PIN(GF_UART2_TX),
LN2_PIN(USB_UART_RX),
LN2_PIN(CDC_PDMCLK1), LN2_PIN(CDC_PDMDAT1),
LN2_PIN(CDC_PDMCLK2), LN2_PIN(CDC_PDMDAT2),
LN2_PIN(CDC_DMICCLK1), LN2_PIN(CDC_DMICDAT1),
LN2_PIN(CDC_DMICCLK2), LN2_PIN(CDC_DMICDAT2),
LN2_PIN(CDC_DMICCLK3), LN2_PIN(CDC_DMICDAT3),
LN2_PIN(CDC_DMICCLK4), LN2_PIN(CDC_DMICDAT4),
LN2_PIN(DSP_DMICCLK1), LN2_PIN(DSP_DMICDAT1),
LN2_PIN(DSP_DMICCLK2), LN2_PIN(DSP_DMICDAT2),
LN2_PIN(I2C2_SCL), LN2_PIN(I2C2_SDA),
LN2_PIN(I2C3_SCL), LN2_PIN(I2C3_SDA),
LN2_PIN(I2C4_SCL), LN2_PIN(I2C4_SDA),
LN2_PIN(DSP_STANDBY),
LN2_PIN(CDC_MCLK1), LN2_PIN(CDC_MCLK2),
LN2_PIN(DSP_CLKIN),
LN2_PIN(PSIA1_MCLK), LN2_PIN(PSIA2_MCLK),
LN2_PINS(SPDIF_AIF),
LN2_PINS(USB_AIF1), LN2_PINS(USB_AIF2),
LN2_PINS(ADAT_AIF),
LN2_PINS(SOUNDCARD_AIF),
};
#define LN_AIF_PINS(REV, ID) \
LOCHNAGAR##REV##_PIN_##ID##_BCLK, \
LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \
LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \
LOCHNAGAR##REV##_PIN_##ID##_RXDAT,
#define LN1_AIF(ID, CTRL) \
static const struct lochnagar_aif lochnagar1_##ID##_aif = { \
.name = LN_##ID##_STR, \
.pins = { LN_AIF_PINS(1, ID) }, \
.src_reg = LOCHNAGAR1_##ID##_SEL, \
.src_mask = LOCHNAGAR1_SRC_MASK, \
.ctrl_reg = LOCHNAGAR1_##CTRL, \
.ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
.master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \
LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \
}
#define LN2_AIF(ID) \
static const struct lochnagar_aif lochnagar2_##ID##_aif = { \
.name = LN_##ID##_STR, \
.pins = { LN_AIF_PINS(2, ID) }, \
.src_reg = LOCHNAGAR2_##ID##_CTRL, \
.src_mask = LOCHNAGAR2_AIF_SRC_MASK, \
.ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
.ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \
.master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \
LOCHNAGAR2_AIF_BCLK_DIR_MASK, \
}
struct lochnagar_aif {
const char name[16];
unsigned int pins[4];
u16 src_reg;
u16 src_mask;
u16 ctrl_reg;
u16 ena_mask;
u16 master_mask;
};
LN1_AIF(CDC_AIF1, CDC_AIF_CTRL1);
LN1_AIF(CDC_AIF2, CDC_AIF_CTRL1);
LN1_AIF(CDC_AIF3, CDC_AIF_CTRL2);
LN1_AIF(DSP_AIF1, DSP_AIF);
LN1_AIF(DSP_AIF2, DSP_AIF);
LN1_AIF(PSIA1, PSIA_AIF);
LN1_AIF(PSIA2, PSIA_AIF);
LN1_AIF(GF_AIF1, GF_AIF1);
LN1_AIF(GF_AIF2, GF_AIF2);
LN1_AIF(GF_AIF3, GF_AIF1);
LN1_AIF(GF_AIF4, GF_AIF2);
LN1_AIF(SPDIF_AIF, EXT_AIF_CTRL);
LN2_AIF(CDC_AIF1);
LN2_AIF(CDC_AIF2);
LN2_AIF(CDC_AIF3);
LN2_AIF(DSP_AIF1);
LN2_AIF(DSP_AIF2);
LN2_AIF(PSIA1);
LN2_AIF(PSIA2);
LN2_AIF(GF_AIF1);
LN2_AIF(GF_AIF2);
LN2_AIF(GF_AIF3);
LN2_AIF(GF_AIF4);
LN2_AIF(SPDIF_AIF);
LN2_AIF(USB_AIF1);
LN2_AIF(USB_AIF2);
LN2_AIF(ADAT_AIF);
LN2_AIF(SOUNDCARD_AIF);
#define LN2_OP_AIF 0x00
#define LN2_OP_GPIO 0xFE
#define LN_FUNC(NAME, TYPE, OP) \
{ .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
#define LN_FUNC_PIN(REV, ID, OP) \
LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
#define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP)
#define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP)
#define LN_FUNC_AIF(REV, ID, OP) \
LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
#define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP)
#define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP)
#define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \
LN2_FUNC_AIF(ID, OP), \
LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \
LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \
LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \
LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP)
enum lochnagar_func_type {
LN_FTYPE_PIN,
LN_FTYPE_AIF,
LN_FTYPE_COUNT,
};
struct lochnagar_func {
const char * const name;
enum lochnagar_func_type type;
u8 op;
};
static const struct lochnagar_func lochnagar1_funcs[] = {
LN_FUNC("dsp-gpio1", PIN, 0x01),
LN_FUNC("dsp-gpio2", PIN, 0x02),
LN_FUNC("dsp-gpio3", PIN, 0x03),
LN_FUNC("codec-gpio1", PIN, 0x04),
LN_FUNC("codec-gpio2", PIN, 0x05),
LN_FUNC("codec-gpio3", PIN, 0x06),
LN_FUNC("codec-gpio4", PIN, 0x07),
LN_FUNC("codec-gpio5", PIN, 0x08),
LN_FUNC("codec-gpio6", PIN, 0x09),
LN_FUNC("codec-gpio7", PIN, 0x0A),
LN_FUNC("codec-gpio8", PIN, 0x0B),
LN1_FUNC_PIN(GF_GPIO2, 0x0C),
LN1_FUNC_PIN(GF_GPIO3, 0x0D),
LN1_FUNC_PIN(GF_GPIO7, 0x0E),
LN1_FUNC_AIF(SPDIF_AIF, 0x01),
LN1_FUNC_AIF(PSIA1, 0x02),
LN1_FUNC_AIF(PSIA2, 0x03),
LN1_FUNC_AIF(CDC_AIF1, 0x04),
LN1_FUNC_AIF(CDC_AIF2, 0x05),
LN1_FUNC_AIF(CDC_AIF3, 0x06),
LN1_FUNC_AIF(DSP_AIF1, 0x07),
LN1_FUNC_AIF(DSP_AIF2, 0x08),
LN1_FUNC_AIF(GF_AIF3, 0x09),
LN1_FUNC_AIF(GF_AIF4, 0x0A),
LN1_FUNC_AIF(GF_AIF1, 0x0B),
LN1_FUNC_AIF(GF_AIF2, 0x0C),
};
static const struct lochnagar_func lochnagar2_funcs[] = {
LN_FUNC("aif", PIN, LN2_OP_AIF),
LN2_FUNC_PIN(FPGA_GPIO1, 0x01),
LN2_FUNC_PIN(FPGA_GPIO2, 0x02),
LN2_FUNC_PIN(FPGA_GPIO3, 0x03),
LN2_FUNC_PIN(FPGA_GPIO4, 0x04),
LN2_FUNC_PIN(FPGA_GPIO5, 0x05),
LN2_FUNC_PIN(FPGA_GPIO6, 0x06),
LN2_FUNC_PIN(CDC_GPIO1, 0x07),
LN2_FUNC_PIN(CDC_GPIO2, 0x08),
LN2_FUNC_PIN(CDC_GPIO3, 0x09),
LN2_FUNC_PIN(CDC_GPIO4, 0x0A),
LN2_FUNC_PIN(CDC_GPIO5, 0x0B),
LN2_FUNC_PIN(CDC_GPIO6, 0x0C),
LN2_FUNC_PIN(CDC_GPIO7, 0x0D),
LN2_FUNC_PIN(CDC_GPIO8, 0x0E),
LN2_FUNC_PIN(DSP_GPIO1, 0x0F),
LN2_FUNC_PIN(DSP_GPIO2, 0x10),
LN2_FUNC_PIN(DSP_GPIO3, 0x11),
LN2_FUNC_PIN(DSP_GPIO4, 0x12),
LN2_FUNC_PIN(DSP_GPIO5, 0x13),
LN2_FUNC_PIN(DSP_GPIO6, 0x14),
LN2_FUNC_PIN(GF_GPIO2, 0x15),
LN2_FUNC_PIN(GF_GPIO3, 0x16),
LN2_FUNC_PIN(GF_GPIO7, 0x17),
LN2_FUNC_PIN(GF_GPIO1, 0x18),
LN2_FUNC_PIN(GF_GPIO5, 0x19),
LN2_FUNC_PIN(DSP_GPIO20, 0x1A),
LN_FUNC("codec-clkout", PIN, 0x20),
LN_FUNC("dsp-clkout", PIN, 0x21),
LN_FUNC("pmic-32k", PIN, 0x22),
LN_FUNC("spdif-clkout", PIN, 0x23),
LN_FUNC("clk-12m288", PIN, 0x24),
LN_FUNC("clk-11m2986", PIN, 0x25),
LN_FUNC("clk-24m576", PIN, 0x26),
LN_FUNC("clk-22m5792", PIN, 0x27),
LN_FUNC("xmos-mclk", PIN, 0x29),
LN_FUNC("gf-clkout1", PIN, 0x2A),
LN_FUNC("gf-mclk1", PIN, 0x2B),
LN_FUNC("gf-mclk3", PIN, 0x2C),
LN_FUNC("gf-mclk2", PIN, 0x2D),
LN_FUNC("gf-clkout2", PIN, 0x2E),
LN2_FUNC_PIN(CDC_MCLK1, 0x2F),
LN2_FUNC_PIN(CDC_MCLK2, 0x30),
LN2_FUNC_PIN(DSP_CLKIN, 0x31),
LN2_FUNC_PIN(PSIA1_MCLK, 0x32),
LN2_FUNC_PIN(PSIA2_MCLK, 0x33),
LN_FUNC("spdif-mclk", PIN, 0x34),
LN_FUNC("codec-irq", PIN, 0x42),
LN2_FUNC_PIN(CDC_RESET, 0x43),
LN2_FUNC_PIN(DSP_RESET, 0x44),
LN_FUNC("dsp-irq", PIN, 0x45),
LN2_FUNC_PIN(DSP_STANDBY, 0x46),
LN2_FUNC_PIN(CDC_PDMCLK1, 0x90),
LN2_FUNC_PIN(CDC_PDMDAT1, 0x91),
LN2_FUNC_PIN(CDC_PDMCLK2, 0x92),
LN2_FUNC_PIN(CDC_PDMDAT2, 0x93),
LN2_FUNC_PIN(CDC_DMICCLK1, 0xA0),
LN2_FUNC_PIN(CDC_DMICDAT1, 0xA1),
LN2_FUNC_PIN(CDC_DMICCLK2, 0xA2),
LN2_FUNC_PIN(CDC_DMICDAT2, 0xA3),
LN2_FUNC_PIN(CDC_DMICCLK3, 0xA4),
LN2_FUNC_PIN(CDC_DMICDAT3, 0xA5),
LN2_FUNC_PIN(CDC_DMICCLK4, 0xA6),
LN2_FUNC_PIN(CDC_DMICDAT4, 0xA7),
LN2_FUNC_PIN(DSP_DMICCLK1, 0xA8),
LN2_FUNC_PIN(DSP_DMICDAT1, 0xA9),
LN2_FUNC_PIN(DSP_DMICCLK2, 0xAA),
LN2_FUNC_PIN(DSP_DMICDAT2, 0xAB),
LN2_FUNC_PIN(DSP_UART1_RX, 0xC0),
LN2_FUNC_PIN(DSP_UART1_TX, 0xC1),
LN2_FUNC_PIN(DSP_UART2_RX, 0xC2),
LN2_FUNC_PIN(DSP_UART2_TX, 0xC3),
LN2_FUNC_PIN(GF_UART2_RX, 0xC4),
LN2_FUNC_PIN(GF_UART2_TX, 0xC5),
LN2_FUNC_PIN(USB_UART_RX, 0xC6),
LN_FUNC("usb-uart-tx", PIN, 0xC7),
LN2_FUNC_PIN(I2C2_SCL, 0xE0),
LN2_FUNC_PIN(I2C2_SDA, 0xE1),
LN2_FUNC_PIN(I2C3_SCL, 0xE2),
LN2_FUNC_PIN(I2C3_SDA, 0xE3),
LN2_FUNC_PIN(I2C4_SCL, 0xE4),
LN2_FUNC_PIN(I2C4_SDA, 0xE5),
LN2_FUNC_AIF(SPDIF_AIF, 0x01),
LN2_FUNC_GAI(PSIA1, 0x02, 0x50, 0x51, 0x52, 0x53),
LN2_FUNC_GAI(PSIA2, 0x03, 0x54, 0x55, 0x56, 0x57),
LN2_FUNC_GAI(CDC_AIF1, 0x04, 0x59, 0x5B, 0x5A, 0x58),
LN2_FUNC_GAI(CDC_AIF2, 0x05, 0x5D, 0x5F, 0x5E, 0x5C),
LN2_FUNC_GAI(CDC_AIF3, 0x06, 0x61, 0x62, 0x63, 0x60),
LN2_FUNC_GAI(DSP_AIF1, 0x07, 0x65, 0x67, 0x66, 0x64),
LN2_FUNC_GAI(DSP_AIF2, 0x08, 0x69, 0x6B, 0x6A, 0x68),
LN2_FUNC_GAI(GF_AIF3, 0x09, 0x6D, 0x6F, 0x6C, 0x6E),
LN2_FUNC_GAI(GF_AIF4, 0x0A, 0x71, 0x73, 0x70, 0x72),
LN2_FUNC_GAI(GF_AIF1, 0x0B, 0x75, 0x77, 0x74, 0x76),
LN2_FUNC_GAI(GF_AIF2, 0x0C, 0x79, 0x7B, 0x78, 0x7A),
LN2_FUNC_AIF(USB_AIF1, 0x0D),
LN2_FUNC_AIF(USB_AIF2, 0x0E),
LN2_FUNC_AIF(ADAT_AIF, 0x0F),
LN2_FUNC_AIF(SOUNDCARD_AIF, 0x10),
};
#define LN_GROUP_PIN(REV, ID) { \
.name = lochnagar##REV##_##ID##_pin.name, \
.type = LN_FTYPE_PIN, \
.pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \
.npins = 1, \
.priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \
}
#define LN_GROUP_AIF(REV, ID) { \
.name = lochnagar##REV##_##ID##_aif.name, \
.type = LN_FTYPE_AIF, \
.pins = lochnagar##REV##_##ID##_aif.pins, \
.npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \
.priv = &lochnagar##REV##_##ID##_aif, \
}
#define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID)
#define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID)
#define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID)
#define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID)
#define LN2_GROUP_GAI(ID) \
LN2_GROUP_AIF(ID), \
LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \
LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT)
struct lochnagar_group {
const char * const name;
enum lochnagar_func_type type;
const unsigned int *pins;
unsigned int npins;
const void *priv;
};
static const struct lochnagar_group lochnagar1_groups[] = {
LN1_GROUP_PIN(GF_GPIO2), LN1_GROUP_PIN(GF_GPIO3),
LN1_GROUP_PIN(GF_GPIO7),
LN1_GROUP_PIN(LED1), LN1_GROUP_PIN(LED2),
LN1_GROUP_AIF(CDC_AIF1), LN1_GROUP_AIF(CDC_AIF2),
LN1_GROUP_AIF(CDC_AIF3),
LN1_GROUP_AIF(DSP_AIF1), LN1_GROUP_AIF(DSP_AIF2),
LN1_GROUP_AIF(PSIA1), LN1_GROUP_AIF(PSIA2),
LN1_GROUP_AIF(GF_AIF1), LN1_GROUP_AIF(GF_AIF2),
LN1_GROUP_AIF(GF_AIF3), LN1_GROUP_AIF(GF_AIF4),
LN1_GROUP_AIF(SPDIF_AIF),
};
static const struct lochnagar_group lochnagar2_groups[] = {
LN2_GROUP_PIN(FPGA_GPIO1), LN2_GROUP_PIN(FPGA_GPIO2),
LN2_GROUP_PIN(FPGA_GPIO3), LN2_GROUP_PIN(FPGA_GPIO4),
LN2_GROUP_PIN(FPGA_GPIO5), LN2_GROUP_PIN(FPGA_GPIO6),
LN2_GROUP_PIN(CDC_GPIO1), LN2_GROUP_PIN(CDC_GPIO2),
LN2_GROUP_PIN(CDC_GPIO3), LN2_GROUP_PIN(CDC_GPIO4),
LN2_GROUP_PIN(CDC_GPIO5), LN2_GROUP_PIN(CDC_GPIO6),
LN2_GROUP_PIN(CDC_GPIO7), LN2_GROUP_PIN(CDC_GPIO8),
LN2_GROUP_PIN(DSP_GPIO1), LN2_GROUP_PIN(DSP_GPIO2),
LN2_GROUP_PIN(DSP_GPIO3), LN2_GROUP_PIN(DSP_GPIO4),
LN2_GROUP_PIN(DSP_GPIO5), LN2_GROUP_PIN(DSP_GPIO6),
LN2_GROUP_PIN(DSP_GPIO20),
LN2_GROUP_PIN(GF_GPIO1),
LN2_GROUP_PIN(GF_GPIO2), LN2_GROUP_PIN(GF_GPIO5),
LN2_GROUP_PIN(GF_GPIO3), LN2_GROUP_PIN(GF_GPIO7),
LN2_GROUP_PIN(DSP_UART1_RX), LN2_GROUP_PIN(DSP_UART1_TX),
LN2_GROUP_PIN(DSP_UART2_RX), LN2_GROUP_PIN(DSP_UART2_TX),
LN2_GROUP_PIN(GF_UART2_RX), LN2_GROUP_PIN(GF_UART2_TX),
LN2_GROUP_PIN(USB_UART_RX),
LN2_GROUP_PIN(CDC_PDMCLK1), LN2_GROUP_PIN(CDC_PDMDAT1),
LN2_GROUP_PIN(CDC_PDMCLK2), LN2_GROUP_PIN(CDC_PDMDAT2),
LN2_GROUP_PIN(CDC_DMICCLK1), LN2_GROUP_PIN(CDC_DMICDAT1),
LN2_GROUP_PIN(CDC_DMICCLK2), LN2_GROUP_PIN(CDC_DMICDAT2),
LN2_GROUP_PIN(CDC_DMICCLK3), LN2_GROUP_PIN(CDC_DMICDAT3),
LN2_GROUP_PIN(CDC_DMICCLK4), LN2_GROUP_PIN(CDC_DMICDAT4),
LN2_GROUP_PIN(DSP_DMICCLK1), LN2_GROUP_PIN(DSP_DMICDAT1),
LN2_GROUP_PIN(DSP_DMICCLK2), LN2_GROUP_PIN(DSP_DMICDAT2),
LN2_GROUP_PIN(I2C2_SCL), LN2_GROUP_PIN(I2C2_SDA),
LN2_GROUP_PIN(I2C3_SCL), LN2_GROUP_PIN(I2C3_SDA),
LN2_GROUP_PIN(I2C4_SCL), LN2_GROUP_PIN(I2C4_SDA),
LN2_GROUP_PIN(DSP_STANDBY),
LN2_GROUP_PIN(CDC_MCLK1), LN2_GROUP_PIN(CDC_MCLK2),
LN2_GROUP_PIN(DSP_CLKIN),
LN2_GROUP_PIN(PSIA1_MCLK), LN2_GROUP_PIN(PSIA2_MCLK),
LN2_GROUP_GAI(CDC_AIF1), LN2_GROUP_GAI(CDC_AIF2),
LN2_GROUP_GAI(CDC_AIF3),
LN2_GROUP_GAI(DSP_AIF1), LN2_GROUP_GAI(DSP_AIF2),
LN2_GROUP_GAI(PSIA1), LN2_GROUP_GAI(PSIA2),
LN2_GROUP_GAI(GF_AIF1), LN2_GROUP_GAI(GF_AIF2),
LN2_GROUP_GAI(GF_AIF3), LN2_GROUP_GAI(GF_AIF4),
LN2_GROUP_AIF(SPDIF_AIF),
LN2_GROUP_AIF(USB_AIF1), LN2_GROUP_AIF(USB_AIF2),
LN2_GROUP_AIF(ADAT_AIF),
LN2_GROUP_AIF(SOUNDCARD_AIF),
};
struct lochnagar_func_groups {
const char **groups;
unsigned int ngroups;
};
struct lochnagar_pin_priv {
struct lochnagar *lochnagar;
struct device *dev;
const struct lochnagar_func *funcs;
unsigned int nfuncs;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
const struct lochnagar_group *groups;
unsigned int ngroups;
struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT];
struct gpio_chip gpio_chip;
};
static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->ngroups;
}
static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group_idx)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->groups[group_idx].name;
}
static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group_idx,
const unsigned int **pins,
unsigned int *num_pins)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
*pins = priv->groups[group_idx].pins;
*num_pins = priv->groups[group_idx].npins;
return 0;
}
static const struct pinctrl_ops lochnagar_pin_group_ops = {
.get_groups_count = lochnagar_get_groups_count,
.get_group_name = lochnagar_get_group_name,
.get_group_pins = lochnagar_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->nfuncs;
}
static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev,
unsigned int func_idx)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->funcs[func_idx].name;
}
static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int func_idx,
const char * const **groups,
unsigned int * const num_groups)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
int func_type;
func_type = priv->funcs[func_idx].type;
*groups = priv->func_groups[func_type].groups;
*num_groups = priv->func_groups[func_type].ngroups;
return 0;
}
static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv,
unsigned int op)
{
struct regmap *regmap = priv->lochnagar->regmap;
unsigned int val;
int free = -1;
int i, ret;
for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) {
ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val);
if (ret)
return ret;
val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK;
if (val == op)
return i + 1;
if (free < 0 && !val)
free = i;
}
if (free >= 0) {
ret = regmap_update_bits(regmap,
LOCHNAGAR2_GPIO_CHANNEL1 + free,
LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op);
if (ret)
return ret;
free++;
dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
return free;
}
return -ENOSPC;
}
static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv,
const struct lochnagar_pin *pin,
unsigned int op)
{
int ret;
switch (priv->lochnagar->type) {
case LOCHNAGAR1:
break;
default:
ret = lochnagar2_get_gpio_chan(priv, op);
if (ret < 0) {
dev_err(priv->dev, "Failed to get channel for %s: %d\n",
pin->name, ret);
return ret;
}
op = ret;
break;
}
dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
if (ret)
dev_err(priv->dev, "Failed to set %s mux: %d\n",
pin->name, ret);
return 0;
}
static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv,
const struct lochnagar_group *group,
unsigned int op)
{
struct regmap *regmap = priv->lochnagar->regmap;
const struct lochnagar_aif *aif = group->priv;
const struct lochnagar_pin *pin;
int i, ret;
ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
if (ret) {
dev_err(priv->dev, "Failed to set %s source: %d\n",
group->name, ret);
return ret;
}
ret = regmap_update_bits(regmap, aif->ctrl_reg,
aif->ena_mask, aif->ena_mask);
if (ret) {
dev_err(priv->dev, "Failed to set %s enable: %d\n",
group->name, ret);
return ret;
}
for (i = 0; i < group->npins; i++) {
pin = priv->pins[group->pins[i]].drv_data;
if (pin->type != LN_PTYPE_MUX)
continue;
dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
ret = regmap_update_bits(regmap, pin->reg,
LOCHNAGAR2_GPIO_SRC_MASK,
LN2_OP_AIF);
if (ret) {
dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
pin->name, ret);
return ret;
}
}
return 0;
}
static int lochnagar_set_mux(struct pinctrl_dev *pctldev,
unsigned int func_idx, unsigned int group_idx)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
const struct lochnagar_func *func = &priv->funcs[func_idx];
const struct lochnagar_group *group = &priv->groups[group_idx];
const struct lochnagar_pin *pin;
switch (func->type) {
case LN_FTYPE_AIF:
dev_dbg(priv->dev, "Set group %s to %s\n",
group->name, func->name);
return lochnagar_aif_set_mux(priv, group, func->op);
case LN_FTYPE_PIN:
pin = priv->pins[*group->pins].drv_data;
dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
return lochnagar_pin_set_mux(priv, pin, func->op);
default:
return -EINVAL;
}
}
static int lochnagar_gpio_request(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
struct lochnagar *lochnagar = priv->lochnagar;
const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
int ret;
dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
return 0;
ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO);
if (ret < 0) {
dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
return ret;
}
ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1);
if (ret < 0) {
dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
return ret;
}
return 0;
}
static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset,
bool input)
{
/* The GPIOs only support output */
if (input)
return -EINVAL;
return 0;
}
static const struct pinmux_ops lochnagar_pin_mux_ops = {
.get_functions_count = lochnagar_get_funcs_count,
.get_function_name = lochnagar_get_func_name,
.get_function_groups = lochnagar_get_func_groups,
.set_mux = lochnagar_set_mux,
.gpio_request_enable = lochnagar_gpio_request,
.gpio_set_direction = lochnagar_gpio_set_direction,
.strict = true,
};
static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv,
unsigned int group_idx, bool master)
{
struct regmap *regmap = priv->lochnagar->regmap;
const struct lochnagar_group *group = &priv->groups[group_idx];
const struct lochnagar_aif *aif = group->priv;
unsigned int val = 0;
int ret;
if (group->type != LN_FTYPE_AIF)
return -EINVAL;
if (!master)
val = aif->master_mask;
dev_dbg(priv->dev, "Set AIF %s to %s\n",
group->name, master ? "master" : "slave");
ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
if (ret) {
dev_err(priv->dev, "Failed to set %s mode: %d\n",
group->name, ret);
return ret;
}
return 0;
}
static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev,
unsigned int group_idx,
unsigned long *configs,
unsigned int num_configs)
{
struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
int i, ret;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(*configs);
switch (param) {
case PIN_CONFIG_OUTPUT_ENABLE:
ret = lochnagar_aif_set_master(priv, group_idx, true);
if (ret)
return ret;
break;
case PIN_CONFIG_INPUT_ENABLE:
ret = lochnagar_aif_set_master(priv, group_idx, false);
if (ret)
return ret;
break;
default:
return -ENOTSUPP;
}
configs++;
}
return 0;
}
static const struct pinconf_ops lochnagar_pin_conf_ops = {
.pin_config_group_set = lochnagar_conf_group_set,
};
static const struct pinctrl_desc lochnagar_pin_desc = {
.name = "lochnagar-pinctrl",
.owner = THIS_MODULE,
.pctlops = &lochnagar_pin_group_ops,
.pmxops = &lochnagar_pin_mux_ops,
.confops = &lochnagar_pin_conf_ops,
};
static void lochnagar_gpio_set(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
struct lochnagar *lochnagar = priv->lochnagar;
const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
int ret;
value = !!value;
dev_dbg(priv->dev, "Set GPIO %s to %s\n",
pin->name, value ? "high" : "low");
switch (pin->type) {
case LN_PTYPE_MUX:
value |= LN2_OP_GPIO;
ret = lochnagar_pin_set_mux(priv, pin, value);
break;
case LN_PTYPE_GPIO:
if (pin->invert)
value = !value;
ret = regmap_update_bits(lochnagar->regmap, pin->reg,
BIT(pin->shift), value << pin->shift);
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0)
dev_err(chip->parent, "Failed to set %s value: %d\n",
pin->name, ret);
}
static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
unsigned int offset, int value)
{
lochnagar_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
{
struct lochnagar_func_groups *funcs;
int i;
for (i = 0; i < priv->ngroups; i++)
priv->func_groups[priv->groups[i].type].ngroups++;
for (i = 0; i < LN_FTYPE_COUNT; i++) {
funcs = &priv->func_groups[i];
if (!funcs->ngroups)
continue;
funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
sizeof(*funcs->groups),
GFP_KERNEL);
if (!funcs->groups)
return -ENOMEM;
funcs->ngroups = 0;
}
for (i = 0; i < priv->ngroups; i++) {
funcs = &priv->func_groups[priv->groups[i].type];
funcs->groups[funcs->ngroups++] = priv->groups[i].name;
}
return 0;
}
static int lochnagar_pin_probe(struct platform_device *pdev)
{
struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
struct lochnagar_pin_priv *priv;
struct pinctrl_desc *desc;
struct pinctrl_dev *pctl;
struct device *dev = &pdev->dev;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->lochnagar = lochnagar;
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
if (!desc)
return -ENOMEM;
*desc = lochnagar_pin_desc;
priv->gpio_chip.label = dev_name(dev);
priv->gpio_chip.request = gpiochip_generic_request;
priv->gpio_chip.free = gpiochip_generic_free;
priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
priv->gpio_chip.set = lochnagar_gpio_set;
priv->gpio_chip.can_sleep = true;
priv->gpio_chip.parent = dev;
priv->gpio_chip.base = -1;
switch (lochnagar->type) {
case LOCHNAGAR1:
priv->funcs = lochnagar1_funcs;
priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
priv->pins = lochnagar1_pins;
priv->npins = ARRAY_SIZE(lochnagar1_pins);
priv->groups = lochnagar1_groups;
priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
break;
case LOCHNAGAR2:
priv->funcs = lochnagar2_funcs;
priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
priv->pins = lochnagar2_pins;
priv->npins = ARRAY_SIZE(lochnagar2_pins);
priv->groups = lochnagar2_groups;
priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
break;
default:
dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
return -EINVAL;
}
ret = lochnagar_fill_func_groups(priv);
if (ret < 0)
return ret;
desc->pins = priv->pins;
desc->npins = priv->npins;
pctl = devm_pinctrl_register(dev, desc, priv);
if (IS_ERR(pctl)) {
ret = PTR_ERR(pctl);
dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
return ret;
}
ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id lochnagar_of_match[] = {
{ .compatible = "cirrus,lochnagar-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, lochnagar_of_match);
static struct platform_driver lochnagar_pin_driver = {
.driver = {
.name = "lochnagar-pinctrl",
.of_match_table = of_match_ptr(lochnagar_of_match),
},
.probe = lochnagar_pin_probe,
};
module_platform_driver(lochnagar_pin_driver);
MODULE_AUTHOR("Charles Keepax <[email protected]>");
MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A779F0 processor support - PFC hardware block.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
*/
/* GPSR0 */
#define GPSR0_20 F_(IRQ3, IP2SR0_19_16)
#define GPSR0_19 F_(IRQ2, IP2SR0_15_12)
#define GPSR0_18 F_(IRQ1, IP2SR0_11_8)
#define GPSR0_17 F_(IRQ0, IP2SR0_7_4)
#define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0)
#define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28)
#define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24)
#define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20)
#define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16)
#define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12)
#define GPSR0_10 F_(CTS0_N, IP1SR0_11_8)
#define GPSR0_9 F_(RTS0_N, IP1SR0_7_4)
#define GPSR0_8 F_(SCK0, IP1SR0_3_0)
#define GPSR0_7 F_(TX0, IP0SR0_31_28)
#define GPSR0_6 F_(RX0, IP0SR0_27_24)
#define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20)
#define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16)
#define GPSR0_3 F_(HTX0, IP0SR0_15_12)
#define GPSR0_2 F_(HRX0, IP0SR0_11_8)
#define GPSR0_1 F_(HSCK0, IP0SR0_7_4)
#define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0)
/* GPSR1 */
#define GPSR1_24 FM(SD_WP)
#define GPSR1_23 FM(SD_CD)
#define GPSR1_22 FM(MMC_SD_CMD)
#define GPSR1_21 FM(MMC_D7)
#define GPSR1_20 FM(MMC_DS)
#define GPSR1_19 FM(MMC_D6)
#define GPSR1_18 FM(MMC_D4)
#define GPSR1_17 FM(MMC_D5)
#define GPSR1_16 FM(MMC_SD_D3)
#define GPSR1_15 FM(MMC_SD_D2)
#define GPSR1_14 FM(MMC_SD_D1)
#define GPSR1_13 FM(MMC_SD_D0)
#define GPSR1_12 FM(MMC_SD_CLK)
#define GPSR1_11 FM(GP1_11)
#define GPSR1_10 FM(GP1_10)
#define GPSR1_9 FM(GP1_09)
#define GPSR1_8 FM(GP1_08)
#define GPSR1_7 F_(GP1_07, IP0SR1_31_28)
#define GPSR1_6 F_(GP1_06, IP0SR1_27_24)
#define GPSR1_5 F_(GP1_05, IP0SR1_23_20)
#define GPSR1_4 F_(GP1_04, IP0SR1_19_16)
#define GPSR1_3 F_(GP1_03, IP0SR1_15_12)
#define GPSR1_2 F_(GP1_02, IP0SR1_11_8)
#define GPSR1_1 F_(GP1_01, IP0SR1_7_4)
#define GPSR1_0 F_(GP1_00, IP0SR1_3_0)
/* GPSR2 */
#define GPSR2_16 FM(PCIE1_CLKREQ_N)
#define GPSR2_15 FM(PCIE0_CLKREQ_N)
#define GPSR2_14 FM(QSPI0_IO3)
#define GPSR2_13 FM(QSPI0_SSL)
#define GPSR2_12 FM(QSPI0_MISO_IO1)
#define GPSR2_11 FM(QSPI0_IO2)
#define GPSR2_10 FM(QSPI0_SPCLK)
#define GPSR2_9 FM(QSPI0_MOSI_IO0)
#define GPSR2_8 FM(QSPI1_SPCLK)
#define GPSR2_7 FM(QSPI1_MOSI_IO0)
#define GPSR2_6 FM(QSPI1_IO2)
#define GPSR2_5 FM(QSPI1_MISO_IO1)
#define GPSR2_4 FM(QSPI1_IO3)
#define GPSR2_3 FM(QSPI1_SSL)
#define GPSR2_2 FM(RPC_RESET_N)
#define GPSR2_1 FM(RPC_WP_N)
#define GPSR2_0 FM(RPC_INT_N)
/* GPSR3 */
#define GPSR3_18 FM(TSN0_AVTP_CAPTURE_B)
#define GPSR3_17 FM(TSN0_AVTP_MATCH_B)
#define GPSR3_16 FM(TSN0_AVTP_PPS)
#define GPSR3_15 FM(TSN1_AVTP_CAPTURE_B)
#define GPSR3_14 FM(TSN1_AVTP_MATCH_B)
#define GPSR3_13 FM(TSN1_AVTP_PPS)
#define GPSR3_12 FM(TSN0_MAGIC_B)
#define GPSR3_11 FM(TSN1_PHY_INT_B)
#define GPSR3_10 FM(TSN0_PHY_INT_B)
#define GPSR3_9 FM(TSN2_PHY_INT_B)
#define GPSR3_8 FM(TSN0_LINK_B)
#define GPSR3_7 FM(TSN2_LINK_B)
#define GPSR3_6 FM(TSN1_LINK_B)
#define GPSR3_5 FM(TSN1_MDC_B)
#define GPSR3_4 FM(TSN0_MDC_B)
#define GPSR3_3 FM(TSN2_MDC_B)
#define GPSR3_2 FM(TSN0_MDIO_B)
#define GPSR3_1 FM(TSN2_MDIO_B)
#define GPSR3_0 FM(TSN1_MDIO_B)
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
#define IP0SR0_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 FM(HSCK0) FM(SCK3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 FM(HRX0) FM(RX3) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_15_12 FM(HTX0) FM(TX3) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_19_16 FM(HCTS0_N) FM(CTS3_N) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_23_20 FM(HRTS0_N) FM(RTS3_N) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_31_28 FM(TX0) FM(HTX1) F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
#define IP1SR0_3_0 FM(SCK0) FM(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_7_4 FM(RTS0_N) FM(HRTS1_N) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_11_8 FM(CTS0_N) FM(HCTS1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_15_12 FM(MSIOF0_SYNC) FM(HCTS3_N) FM(CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_19_16 FM(MSIOF0_RXD) FM(HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_23_20 FM(MSIOF0_TXD) FM(HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_27_24 FM(MSIOF0_SCK) FM(HSCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_31_28 FM(MSIOF0_SS1) FM(HRTS3_N) FM(RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
#define IP2SR0_3_0 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_7_4 FM(IRQ0) F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
#define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_7_4 FM(GP1_01) FM(TCLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_11_8 FM(GP1_02) F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_15_12 FM(GP1_03) FM(TCLK2) FM(HCTS2_N) FM(MSIOF2_SS2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_19_16 FM(GP1_04) FM(TCLK3) FM(HRTS2_N) FM(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(GP1_05) FM(MSIOF2_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(GP1_06) FM(MSIOF2_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(GP1_07) FM(MSIOF2_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
GPSR1_24 \
GPSR1_23 \
GPSR1_22 \
GPSR1_21 \
GPSR0_20 GPSR1_20 \
GPSR0_19 GPSR1_19 \
GPSR0_18 GPSR1_18 GPSR3_18 \
GPSR0_17 GPSR1_17 GPSR3_17 \
GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 \
GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 \
GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 \
GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 \
GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 \
GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0
#define PINMUX_IPSR \
\
FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \
FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \
FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
\
FM(IP0SR1_3_0) IP0SR1_3_0 \
FM(IP0SR1_7_4) IP0SR1_7_4 \
FM(IP0SR1_11_8) IP0SR1_11_8 \
FM(IP0SR1_15_12) IP0SR1_15_12 \
FM(IP0SR1_19_16) IP0SR1_19_16 \
FM(IP0SR1_23_20) IP0SR1_23_20 \
FM(IP0SR1_27_24) IP0SR1_27_24 \
FM(IP0SR1_31_28) IP0SR1_31_28
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
#define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
#define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
#define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
#define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
#define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
#define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
#define PINMUX_MOD_SELS \
\
MOD_SEL1_11_10 \
MOD_SEL1_9_8 \
MOD_SEL1_7_6 \
MOD_SEL1_5_4 \
MOD_SEL1_3_2 \
MOD_SEL1_1_0
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
/* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
#define GP_1_0_FN GP_1_0_FN, FN_SEL_I2C0_0
#define GP_1_1_FN GP_1_1_FN, FN_SEL_I2C0_0
#define GP_1_2_FN GP_1_2_FN, FN_SEL_I2C1_0
#define GP_1_3_FN GP_1_3_FN, FN_SEL_I2C1_0
#define GP_1_4_FN GP_1_4_FN, FN_SEL_I2C2_0
#define GP_1_5_FN GP_1_5_FN, FN_SEL_I2C2_0
#define GP_1_6_FN GP_1_6_FN, FN_SEL_I2C3_0
#define GP_1_7_FN GP_1_7_FN, FN_SEL_I2C3_0
#define GP_1_8_FN GP_1_8_FN, FN_SEL_I2C4_0
#define GP_1_9_FN GP_1_9_FN, FN_SEL_I2C4_0
PINMUX_DATA_GP_ALL(),
#undef GP_1_0_FN
#undef GP_1_1_FN
#undef GP_1_2_FN
#undef GP_1_3_FN
#undef GP_1_4_FN
#undef GP_1_5_FN
#undef GP_1_6_FN
#undef GP_1_7_FN
#undef GP_1_8_FN
#undef GP_1_9_FN
PINMUX_SINGLE(SD_WP),
PINMUX_SINGLE(SD_CD),
PINMUX_SINGLE(MMC_SD_CMD),
PINMUX_SINGLE(MMC_D7),
PINMUX_SINGLE(MMC_DS),
PINMUX_SINGLE(MMC_D6),
PINMUX_SINGLE(MMC_D4),
PINMUX_SINGLE(MMC_D5),
PINMUX_SINGLE(MMC_SD_D3),
PINMUX_SINGLE(MMC_SD_D2),
PINMUX_SINGLE(MMC_SD_D1),
PINMUX_SINGLE(MMC_SD_D0),
PINMUX_SINGLE(MMC_SD_CLK),
PINMUX_SINGLE(PCIE1_CLKREQ_N),
PINMUX_SINGLE(PCIE0_CLKREQ_N),
PINMUX_SINGLE(QSPI0_IO3),
PINMUX_SINGLE(QSPI0_SSL),
PINMUX_SINGLE(QSPI0_MISO_IO1),
PINMUX_SINGLE(QSPI0_IO2),
PINMUX_SINGLE(QSPI0_SPCLK),
PINMUX_SINGLE(QSPI0_MOSI_IO0),
PINMUX_SINGLE(QSPI1_SPCLK),
PINMUX_SINGLE(QSPI1_MOSI_IO0),
PINMUX_SINGLE(QSPI1_IO2),
PINMUX_SINGLE(QSPI1_MISO_IO1),
PINMUX_SINGLE(QSPI1_IO3),
PINMUX_SINGLE(QSPI1_SSL),
PINMUX_SINGLE(RPC_RESET_N),
PINMUX_SINGLE(RPC_WP_N),
PINMUX_SINGLE(RPC_INT_N),
PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B),
PINMUX_SINGLE(TSN0_AVTP_MATCH_B),
PINMUX_SINGLE(TSN0_AVTP_PPS),
PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B),
PINMUX_SINGLE(TSN1_AVTP_MATCH_B),
PINMUX_SINGLE(TSN1_AVTP_PPS),
PINMUX_SINGLE(TSN0_MAGIC_B),
PINMUX_SINGLE(TSN1_PHY_INT_B),
PINMUX_SINGLE(TSN0_PHY_INT_B),
PINMUX_SINGLE(TSN2_PHY_INT_B),
PINMUX_SINGLE(TSN0_LINK_B),
PINMUX_SINGLE(TSN2_LINK_B),
PINMUX_SINGLE(TSN1_LINK_B),
PINMUX_SINGLE(TSN1_MDC_B),
PINMUX_SINGLE(TSN0_MDC_B),
PINMUX_SINGLE(TSN2_MDC_B),
PINMUX_SINGLE(TSN0_MDIO_B),
PINMUX_SINGLE(TSN2_MDIO_B),
PINMUX_SINGLE(TSN1_MDIO_B),
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, SCIF_CLK),
PINMUX_IPSR_GPSR(IP0SR0_7_4, HSCK0),
PINMUX_IPSR_GPSR(IP0SR0_7_4, SCK3),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SCK),
PINMUX_IPSR_GPSR(IP0SR0_7_4, TSN0_AVTP_CAPTURE_A),
PINMUX_IPSR_GPSR(IP0SR0_11_8, HRX0),
PINMUX_IPSR_GPSR(IP0SR0_11_8, RX3),
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_RXD),
PINMUX_IPSR_GPSR(IP0SR0_11_8, TSN0_AVTP_MATCH_A),
PINMUX_IPSR_GPSR(IP0SR0_15_12, HTX0),
PINMUX_IPSR_GPSR(IP0SR0_15_12, TX3),
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_TXD),
PINMUX_IPSR_GPSR(IP0SR0_19_16, HCTS0_N),
PINMUX_IPSR_GPSR(IP0SR0_19_16, CTS3_N),
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_SS1),
PINMUX_IPSR_GPSR(IP0SR0_19_16, TSN0_MDC_A),
PINMUX_IPSR_GPSR(IP0SR0_23_20, HRTS0_N),
PINMUX_IPSR_GPSR(IP0SR0_23_20, RTS3_N),
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_SS2),
PINMUX_IPSR_GPSR(IP0SR0_23_20, TSN0_MDIO_A),
PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0),
PINMUX_IPSR_GPSR(IP0SR0_27_24, HRX1),
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP0SR0_27_24, TSN1_AVTP_MATCH_A),
PINMUX_IPSR_GPSR(IP0SR0_31_28, TX0),
PINMUX_IPSR_GPSR(IP0SR0_31_28, HTX1),
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP0SR0_31_28, TSN1_AVTP_CAPTURE_A),
/* IP1SR0 */
PINMUX_IPSR_GPSR(IP1SR0_3_0, SCK0),
PINMUX_IPSR_GPSR(IP1SR0_3_0, HSCK1),
PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP1SR0_7_4, RTS0_N),
PINMUX_IPSR_GPSR(IP1SR0_7_4, HRTS1_N),
PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP1SR0_7_4, TSN1_MDIO_A),
PINMUX_IPSR_GPSR(IP1SR0_11_8, CTS0_N),
PINMUX_IPSR_GPSR(IP1SR0_11_8, HCTS1_N),
PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP1SR0_11_8, TSN1_MDC_A),
PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP1SR0_15_12, HCTS3_N),
PINMUX_IPSR_GPSR(IP1SR0_15_12, CTS1_N),
PINMUX_IPSR_GPSR(IP1SR0_15_12, IRQ4),
PINMUX_IPSR_GPSR(IP1SR0_15_12, TSN0_LINK_A),
PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF0_RXD),
PINMUX_IPSR_GPSR(IP1SR0_19_16, HRX3),
PINMUX_IPSR_GPSR(IP1SR0_19_16, RX1),
PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP1SR0_23_20, HTX3),
PINMUX_IPSR_GPSR(IP1SR0_23_20, TX1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3),
PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1),
PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF0_SS1),
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRTS3_N),
PINMUX_IPSR_GPSR(IP1SR0_31_28, RTS1_N),
PINMUX_IPSR_GPSR(IP1SR0_31_28, IRQ5),
PINMUX_IPSR_GPSR(IP1SR0_31_28, TSN1_LINK_A),
/* IP2SR0 */
PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF0_SS2),
PINMUX_IPSR_GPSR(IP2SR0_3_0, TSN2_LINK_A),
PINMUX_IPSR_GPSR(IP2SR0_7_4, IRQ0),
PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP2SR0_7_4, TSN0_MAGIC_A),
PINMUX_IPSR_GPSR(IP2SR0_11_8, IRQ1),
PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP2SR0_11_8, TSN0_PHY_INT_A),
PINMUX_IPSR_GPSR(IP2SR0_15_12, IRQ2),
PINMUX_IPSR_GPSR(IP2SR0_15_12, TSN1_PHY_INT_A),
PINMUX_IPSR_GPSR(IP2SR0_19_16, IRQ3),
PINMUX_IPSR_GPSR(IP2SR0_19_16, TSN2_PHY_INT_A),
/* IP0SR1 */
/* GP1_00 = SCL0 */
PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0),
PINMUX_IPSR_PHYS(IP0SR1_3_0, SCL0, SEL_I2C0_3),
/* GP1_01 = SDA0 */
PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0),
PINMUX_IPSR_PHYS(IP0SR1_7_4, SDA0, SEL_I2C0_3),
/* GP1_02 = SCL1 */
PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0),
PINMUX_IPSR_PHYS(IP0SR1_11_8, SCL1, SEL_I2C1_3),
/* GP1_03 = SDA1 */
PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0),
PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3),
/* GP1_04 = SCL2 */
PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0),
PINMUX_IPSR_PHYS(IP0SR1_19_16, SCL2, SEL_I2C2_3),
/* GP1_05 = SDA2 */
PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0),
PINMUX_IPSR_PHYS(IP0SR1_23_20, SDA2, SEL_I2C2_3),
/* GP1_06 = SCL3 */
PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0),
PINMUX_IPSR_PHYS(IP0SR1_27_24, SCL3, SEL_I2C3_3),
/* GP1_07 = SDA3 */
PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0),
PINMUX_IPSR_PHYS(IP0SR1_31_28, SDA3, SEL_I2C3_3),
/* GP1_08 = SCL4 */
PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0),
PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3),
/* GP1_09 = SDA4 */
PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0),
PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3),
/* GP1_10 = SCL5 */
PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0),
PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3),
/* GP1_11 = SDA5 */
PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0),
PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* HRX0, HTX0 */
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
};
static const unsigned int hscif0_data_mux[] = {
HRX0_MARK, HTX0_MARK,
};
static const unsigned int hscif0_clk_pins[] = {
/* HSCK0 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK,
};
static const unsigned int hscif0_ctrl_pins[] = {
/* HRTS0#, HCTS0# */
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
};
static const unsigned int hscif0_ctrl_mux[] = {
HRTS0_N_MARK, HCTS0_N_MARK,
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_pins[] = {
/* HRX1, HTX1 */
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int hscif1_data_mux[] = {
HRX1_MARK, HTX1_MARK,
};
static const unsigned int hscif1_clk_pins[] = {
/* HSCK1 */
RCAR_GP_PIN(0, 8),
};
static const unsigned int hscif1_clk_mux[] = {
HSCK1_MARK,
};
static const unsigned int hscif1_ctrl_pins[] = {
/* HRTS1#, HCTS1# */
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int hscif1_ctrl_mux[] = {
HRTS1_N_MARK, HCTS1_N_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_pins[] = {
/* HRX2, HTX2 */
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
};
static const unsigned int hscif2_data_mux[] = {
HRX2_MARK, HTX2_MARK,
};
static const unsigned int hscif2_clk_pins[] = {
/* HSCK2 */
RCAR_GP_PIN(1, 0),
};
static const unsigned int hscif2_clk_mux[] = {
HSCK2_MARK,
};
static const unsigned int hscif2_ctrl_pins[] = {
/* HRTS2#, HCTS2# */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
};
static const unsigned int hscif2_ctrl_mux[] = {
HRTS2_N_MARK, HCTS2_N_MARK,
};
/* - HSCIF3 ----------------------------------------------------------------- */
static const unsigned int hscif3_data_pins[] = {
/* HRX3, HTX3 */
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
};
static const unsigned int hscif3_data_mux[] = {
HRX3_MARK, HTX3_MARK,
};
static const unsigned int hscif3_clk_pins[] = {
/* HSCK3 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int hscif3_clk_mux[] = {
HSCK3_MARK,
};
static const unsigned int hscif3_ctrl_pins[] = {
/* HRTS3#, HCTS3# */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
};
static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SDA0, SCL0 */
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int i2c0_mux[] = {
SDA0_MARK, SCL0_MARK,
};
/* - I2C1 ------------------------------------------------------------------- */
static const unsigned int i2c1_pins[] = {
/* SDA1, SCL1 */
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int i2c1_mux[] = {
SDA1_MARK, SCL1_MARK,
};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_pins[] = {
/* SDA2, SCL2 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
};
static const unsigned int i2c2_mux[] = {
SDA2_MARK, SCL2_MARK,
};
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_pins[] = {
/* SDA3, SCL3 */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
};
static const unsigned int i2c3_mux[] = {
SDA3_MARK, SCL3_MARK,
};
/* - I2C4 ------------------------------------------------------------------- */
static const unsigned int i2c4_pins[] = {
/* SDA4, SCL4 */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
};
static const unsigned int i2c4_mux[] = {
SDA4_MARK, SCL4_MARK,
};
/* - I2C5 ------------------------------------------------------------------- */
static const unsigned int i2c5_pins[] = {
/* SDA5, SCL5 */
RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
};
static const unsigned int i2c5_mux[] = {
SDA5_MARK, SCL5_MARK,
};
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
RCAR_GP_PIN(0, 17),
};
static const unsigned int intc_ex_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_ex_irq1_pins[] = {
/* IRQ1 */
RCAR_GP_PIN(0, 18),
};
static const unsigned int intc_ex_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_ex_irq2_pins[] = {
/* IRQ2 */
RCAR_GP_PIN(0, 19),
};
static const unsigned int intc_ex_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_ex_irq3_pins[] = {
/* IRQ3 */
RCAR_GP_PIN(0, 20),
};
static const unsigned int intc_ex_irq3_mux[] = {
IRQ3_MARK,
};
static const unsigned int intc_ex_irq4_pins[] = {
/* IRQ4 */
RCAR_GP_PIN(0, 11),
};
static const unsigned int intc_ex_irq4_mux[] = {
IRQ4_MARK,
};
static const unsigned int intc_ex_irq5_pins[] = {
/* IRQ5 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* MMC_SD_D[0:3], MMC_D[4:7] */
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
};
static const unsigned int mmc_data_mux[] = {
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
MMC_D6_MARK, MMC_D7_MARK,
};
static const unsigned int mmc_ctrl_pins[] = {
/* MMC_SD_CLK, MMC_SD_CMD */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
};
static const unsigned int mmc_ctrl_mux[] = {
MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
};
static const unsigned int mmc_cd_pins[] = {
/* SD_CD */
RCAR_GP_PIN(1, 23),
};
static const unsigned int mmc_cd_mux[] = {
SD_CD_MARK,
};
static const unsigned int mmc_wp_pins[] = {
/* SD_WP */
RCAR_GP_PIN(1, 24),
};
static const unsigned int mmc_wp_mux[] = {
SD_WP_MARK,
};
static const unsigned int mmc_ds_pins[] = {
/* MMC_DS */
RCAR_GP_PIN(1, 20),
};
static const unsigned int mmc_ds_mux[] = {
MMC_DS_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* MSIOF0_SCK */
RCAR_GP_PIN(0, 14),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* MSIOF0_SYNC */
RCAR_GP_PIN(0, 11),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* MSIOF0_SS1 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* MSIOF0_SS2 */
RCAR_GP_PIN(0, 16),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* MSIOF0_TXD */
RCAR_GP_PIN(0, 13),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* MSIOF0_RXD */
RCAR_GP_PIN(0, 12),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* MSIOF1_SCK */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* MSIOF1_SYNC */
RCAR_GP_PIN(0, 10),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* MSIOF1_SS1 */
RCAR_GP_PIN(0, 17),
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* MSIOF1_SS2 */
RCAR_GP_PIN(0, 18),
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* MSIOF1_TXD */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* MSIOF1_RXD */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_pins[] = {
/* MSIOF2_SCK */
RCAR_GP_PIN(1, 5),
};
static const unsigned int msiof2_clk_mux[] = {
MSIOF2_SCK_MARK,
};
static const unsigned int msiof2_sync_pins[] = {
/* MSIOF2_SYNC */
RCAR_GP_PIN(1, 4),
};
static const unsigned int msiof2_sync_mux[] = {
MSIOF2_SYNC_MARK,
};
static const unsigned int msiof2_ss1_pins[] = {
/* MSIOF2_SS1 */
RCAR_GP_PIN(1, 2),
};
static const unsigned int msiof2_ss1_mux[] = {
MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_pins[] = {
/* MSIOF2_SS2 */
RCAR_GP_PIN(1, 3),
};
static const unsigned int msiof2_ss2_mux[] = {
MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* MSIOF2_TXD */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_rxd_pins[] = {
/* MSIOF2_RXD */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof2_rxd_mux[] = {
MSIOF2_RXD_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_pins[] = {
/* MSIOF3_SCK */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof3_clk_mux[] = {
MSIOF3_SCK_MARK,
};
static const unsigned int msiof3_sync_pins[] = {
/* MSIOF3_SYNC */
RCAR_GP_PIN(0, 9),
};
static const unsigned int msiof3_sync_mux[] = {
MSIOF3_SYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* MSIOF3_SS1 */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof3_ss1_mux[] = {
MSIOF3_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* MSIOF3_SS2 */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof3_ss2_mux[] = {
MSIOF3_SS2_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* MSIOF3_TXD */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof3_txd_mux[] = {
MSIOF3_TXD_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* MSIOF3_RXD */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof3_rxd_mux[] = {
MSIOF3_RXD_MARK,
};
/* - PCIE ------------------------------------------------------------------- */
static const unsigned int pcie0_clkreq_n_pins[] = {
/* PCIE0_CLKREQ# */
RCAR_GP_PIN(2, 15),
};
static const unsigned int pcie0_clkreq_n_mux[] = {
PCIE0_CLKREQ_N_MARK,
};
static const unsigned int pcie1_clkreq_n_pins[] = {
/* PCIE1_CLKREQ# */
RCAR_GP_PIN(2, 16),
};
static const unsigned int pcie1_clkreq_n_mux[] = {
PCIE1_CLKREQ_N_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
};
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK0 */
RCAR_GP_PIN(0, 8),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS0#, CTS0# */
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_pins[] = {
/* RX1, TX1 */
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
};
static const unsigned int scif1_data_mux[] = {
RX1_MARK, TX1_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK1 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS1#, CTS1# */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_pins[] = {
/* RX3, TX3 */
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
};
static const unsigned int scif3_data_mux[] = {
RX3_MARK, TX3_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK3 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
static const unsigned int scif3_ctrl_pins[] = {
/* RTS3#, CTS3# */
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_pins[] = {
/* RX4, TX4 */
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int scif4_data_mux[] = {
RX4_MARK, TX4_MARK,
};
static const unsigned int scif4_clk_pins[] = {
/* SCK4 */
RCAR_GP_PIN(1, 5),
};
static const unsigned int scif4_clk_mux[] = {
SCK4_MARK,
};
static const unsigned int scif4_ctrl_pins[] = {
/* RTS4#, CTS4# */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
};
static const unsigned int scif4_ctrl_mux[] = {
RTS4_N_MARK, CTS4_N_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(0, 0),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
/* - TSN0 ------------------------------------------------ */
static const unsigned int tsn0_link_a_pins[] = {
/* TSN0_LINK_A */
RCAR_GP_PIN(0, 11),
};
static const unsigned int tsn0_link_a_mux[] = {
TSN0_LINK_A_MARK,
};
static const unsigned int tsn0_magic_a_pins[] = {
/* TSN0_MAGIC_A */
RCAR_GP_PIN(0, 17),
};
static const unsigned int tsn0_magic_a_mux[] = {
TSN0_MAGIC_A_MARK,
};
static const unsigned int tsn0_phy_int_a_pins[] = {
/* TSN0_PHY_INT_A */
RCAR_GP_PIN(0, 18),
};
static const unsigned int tsn0_phy_int_a_mux[] = {
TSN0_PHY_INT_A_MARK,
};
static const unsigned int tsn0_mdio_a_pins[] = {
/* TSN0_MDC_A, TSN0_MDIO_A */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
};
static const unsigned int tsn0_mdio_a_mux[] = {
TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
};
static const unsigned int tsn0_link_b_pins[] = {
/* TSN0_LINK_B */
RCAR_GP_PIN(3, 8),
};
static const unsigned int tsn0_link_b_mux[] = {
TSN0_LINK_B_MARK,
};
static const unsigned int tsn0_magic_b_pins[] = {
/* TSN0_MAGIC_B */
RCAR_GP_PIN(3, 12),
};
static const unsigned int tsn0_magic_b_mux[] = {
TSN0_MAGIC_B_MARK,
};
static const unsigned int tsn0_phy_int_b_pins[] = {
/* TSN0_PHY_INT_B */
RCAR_GP_PIN(3, 10),
};
static const unsigned int tsn0_phy_int_b_mux[] = {
TSN0_PHY_INT_B_MARK,
};
static const unsigned int tsn0_mdio_b_pins[] = {
/* TSN0_MDC_B, TSN0_MDIO_B */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
};
static const unsigned int tsn0_mdio_b_mux[] = {
TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
};
static const unsigned int tsn0_avtp_pps_pins[] = {
/* TSN0_AVTP_PPS */
RCAR_GP_PIN(3, 16),
};
static const unsigned int tsn0_avtp_pps_mux[] = {
TSN0_AVTP_PPS_MARK,
};
static const unsigned int tsn0_avtp_capture_a_pins[] = {
/* TSN0_AVTP_CAPTURE_A */
RCAR_GP_PIN(0, 1),
};
static const unsigned int tsn0_avtp_capture_a_mux[] = {
TSN0_AVTP_CAPTURE_A_MARK,
};
static const unsigned int tsn0_avtp_match_a_pins[] = {
/* TSN0_AVTP_MATCH_A */
RCAR_GP_PIN(0, 2),
};
static const unsigned int tsn0_avtp_match_a_mux[] = {
TSN0_AVTP_MATCH_A_MARK,
};
static const unsigned int tsn0_avtp_capture_b_pins[] = {
/* TSN0_AVTP_CAPTURE_B */
RCAR_GP_PIN(3, 18),
};
static const unsigned int tsn0_avtp_capture_b_mux[] = {
TSN0_AVTP_CAPTURE_B_MARK,
};
static const unsigned int tsn0_avtp_match_b_pins[] = {
/* TSN0_AVTP_MATCH_B */
RCAR_GP_PIN(3, 17),
};
static const unsigned int tsn0_avtp_match_b_mux[] = {
TSN0_AVTP_MATCH_B_MARK,
};
/* - TSN1 ------------------------------------------------ */
static const unsigned int tsn1_link_a_pins[] = {
/* TSN1_LINK_A */
RCAR_GP_PIN(0, 15),
};
static const unsigned int tsn1_link_a_mux[] = {
TSN1_LINK_A_MARK,
};
static const unsigned int tsn1_phy_int_a_pins[] = {
/* TSN1_PHY_INT_A */
RCAR_GP_PIN(0, 19),
};
static const unsigned int tsn1_phy_int_a_mux[] = {
TSN1_PHY_INT_A_MARK,
};
static const unsigned int tsn1_mdio_a_pins[] = {
/* TSN1_MDC_A, TSN1_MDIO_A */
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
};
static const unsigned int tsn1_mdio_a_mux[] = {
TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
};
static const unsigned int tsn1_link_b_pins[] = {
/* TSN1_LINK_B */
RCAR_GP_PIN(3, 6),
};
static const unsigned int tsn1_link_b_mux[] = {
TSN1_LINK_B_MARK,
};
static const unsigned int tsn1_phy_int_b_pins[] = {
/* TSN1_PHY_INT_B */
RCAR_GP_PIN(3, 11),
};
static const unsigned int tsn1_phy_int_b_mux[] = {
TSN1_PHY_INT_B_MARK,
};
static const unsigned int tsn1_mdio_b_pins[] = {
/* TSN1_MDC_B, TSN1_MDIO_B */
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
};
static const unsigned int tsn1_mdio_b_mux[] = {
TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
};
static const unsigned int tsn1_avtp_pps_pins[] = {
/* TSN1_AVTP_PPS */
RCAR_GP_PIN(3, 13),
};
static const unsigned int tsn1_avtp_pps_mux[] = {
TSN1_AVTP_PPS_MARK,
};
static const unsigned int tsn1_avtp_capture_a_pins[] = {
/* TSN1_AVTP_CAPTURE_A */
RCAR_GP_PIN(0, 7),
};
static const unsigned int tsn1_avtp_capture_a_mux[] = {
TSN1_AVTP_CAPTURE_A_MARK,
};
static const unsigned int tsn1_avtp_match_a_pins[] = {
/* TSN1_AVTP_MATCH_A */
RCAR_GP_PIN(0, 6),
};
static const unsigned int tsn1_avtp_match_a_mux[] = {
TSN1_AVTP_MATCH_A_MARK,
};
static const unsigned int tsn1_avtp_capture_b_pins[] = {
/* TSN1_AVTP_CAPTURE_B */
RCAR_GP_PIN(3, 15),
};
static const unsigned int tsn1_avtp_capture_b_mux[] = {
TSN1_AVTP_CAPTURE_B_MARK,
};
static const unsigned int tsn1_avtp_match_b_pins[] = {
/* TSN1_AVTP_MATCH_B */
RCAR_GP_PIN(3, 14),
};
static const unsigned int tsn1_avtp_match_b_mux[] = {
TSN1_AVTP_MATCH_B_MARK,
};
/* - TSN2 ------------------------------------------------ */
static const unsigned int tsn2_link_a_pins[] = {
/* TSN2_LINK_A */
RCAR_GP_PIN(0, 16),
};
static const unsigned int tsn2_link_a_mux[] = {
TSN2_LINK_A_MARK,
};
static const unsigned int tsn2_phy_int_a_pins[] = {
/* TSN2_PHY_INT_A */
RCAR_GP_PIN(0, 20),
};
static const unsigned int tsn2_phy_int_a_mux[] = {
TSN2_PHY_INT_A_MARK,
};
static const unsigned int tsn2_mdio_a_pins[] = {
/* TSN2_MDC_A, TSN2_MDIO_A */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
};
static const unsigned int tsn2_mdio_a_mux[] = {
TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
};
static const unsigned int tsn2_link_b_pins[] = {
/* TSN2_LINK_B */
RCAR_GP_PIN(3, 7),
};
static const unsigned int tsn2_link_b_mux[] = {
TSN2_LINK_B_MARK,
};
static const unsigned int tsn2_phy_int_b_pins[] = {
/* TSN2_PHY_INT_B */
RCAR_GP_PIN(3, 9),
};
static const unsigned int tsn2_phy_int_b_mux[] = {
TSN2_PHY_INT_B_MARK,
};
static const unsigned int tsn2_mdio_b_pins[] = {
/* TSN2_MDC_B, TSN2_MDIO_B */
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
};
static const unsigned int tsn2_mdio_b_mux[] = {
TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif1_data),
SH_PFC_PIN_GROUP(hscif1_clk),
SH_PFC_PIN_GROUP(hscif1_ctrl),
SH_PFC_PIN_GROUP(hscif2_data),
SH_PFC_PIN_GROUP(hscif2_clk),
SH_PFC_PIN_GROUP(hscif2_ctrl),
SH_PFC_PIN_GROUP(hscif3_data),
SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(hscif3_ctrl),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c4),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof2_clk),
SH_PFC_PIN_GROUP(msiof2_sync),
SH_PFC_PIN_GROUP(msiof2_ss1),
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_rxd),
SH_PFC_PIN_GROUP(msiof3_clk),
SH_PFC_PIN_GROUP(msiof3_sync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data),
SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(tsn0_link_a),
SH_PFC_PIN_GROUP(tsn0_magic_a),
SH_PFC_PIN_GROUP(tsn0_phy_int_a),
SH_PFC_PIN_GROUP(tsn0_mdio_a),
SH_PFC_PIN_GROUP(tsn0_link_b),
SH_PFC_PIN_GROUP(tsn0_magic_b),
SH_PFC_PIN_GROUP(tsn0_phy_int_b),
SH_PFC_PIN_GROUP(tsn0_mdio_b),
SH_PFC_PIN_GROUP(tsn0_avtp_pps),
SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
SH_PFC_PIN_GROUP(tsn1_link_a),
SH_PFC_PIN_GROUP(tsn1_phy_int_a),
SH_PFC_PIN_GROUP(tsn1_mdio_a),
SH_PFC_PIN_GROUP(tsn1_link_b),
SH_PFC_PIN_GROUP(tsn1_phy_int_b),
SH_PFC_PIN_GROUP(tsn1_mdio_b),
SH_PFC_PIN_GROUP(tsn1_avtp_pps),
SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
SH_PFC_PIN_GROUP(tsn2_link_a),
SH_PFC_PIN_GROUP(tsn2_phy_int_a),
SH_PFC_PIN_GROUP(tsn2_mdio_a),
SH_PFC_PIN_GROUP(tsn2_link_b),
SH_PFC_PIN_GROUP(tsn2_phy_int_b),
SH_PFC_PIN_GROUP(tsn2_mdio_b),
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
};
static const char * const hscif1_groups[] = {
"hscif1_data",
"hscif1_clk",
"hscif1_ctrl",
};
static const char * const hscif2_groups[] = {
"hscif2_data",
"hscif2_clk",
"hscif2_ctrl",
};
static const char * const hscif3_groups[] = {
"hscif3_data",
"hscif3_clk",
"hscif3_ctrl",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1",
};
static const char * const i2c2_groups[] = {
"i2c2",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c4_groups[] = {
"i2c4",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
"intc_ex_irq2",
"intc_ex_irq3",
"intc_ex_irq4",
"intc_ex_irq5",
};
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
"mmc_ctrl",
"mmc_cd",
"mmc_wp",
"mmc_ds",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_txd",
"msiof1_rxd",
};
static const char * const msiof2_groups[] = {
"msiof2_clk",
"msiof2_sync",
"msiof2_ss1",
"msiof2_ss2",
"msiof2_txd",
"msiof2_rxd",
};
static const char * const msiof3_groups[] = {
"msiof3_clk",
"msiof3_sync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_txd",
"msiof3_rxd",
};
static const char * const pcie_groups[] = {
"pcie0_clkreq_n",
"pcie1_clkreq_n",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
"scif1_data",
"scif1_clk",
"scif1_ctrl",
};
static const char * const scif3_groups[] = {
"scif3_data",
"scif3_clk",
"scif3_ctrl",
};
static const char * const scif4_groups[] = {
"scif4_data",
"scif4_clk",
"scif4_ctrl",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
};
static const char * const tsn0_groups[] = {
"tsn0_link_a",
"tsn0_magic_a",
"tsn0_phy_int_a",
"tsn0_mdio_a",
"tsn0_link_b",
"tsn0_magic_b",
"tsn0_phy_int_b",
"tsn0_mdio_b",
"tsn0_avtp_pps",
"tsn0_avtp_capture_a",
"tsn0_avtp_match_a",
"tsn0_avtp_capture_b",
"tsn0_avtp_match_b",
};
static const char * const tsn1_groups[] = {
"tsn1_link_a",
"tsn1_phy_int_a",
"tsn1_mdio_a",
"tsn1_link_b",
"tsn1_phy_int_b",
"tsn1_mdio_b",
"tsn1_avtp_pps",
"tsn1_avtp_capture_a",
"tsn1_avtp_match_a",
"tsn1_avtp_capture_b",
"tsn1_avtp_match_b",
};
static const char * const tsn2_groups[] = {
"tsn2_link_a",
"tsn2_phy_int_a",
"tsn2_mdio_a",
"tsn2_link_b",
"tsn2_phy_int_b",
"tsn2_mdio_b",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pcie),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(tsn0),
SH_PFC_FUNCTION(tsn1),
SH_PFC_FUNCTION(tsn2),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_21 RESERVED */
GP_0_20_FN, GPSR0_20,
GP_0_19_FN, GPSR0_19,
GP_0_18_FN, GPSR0_18,
GP_0_17_FN, GPSR0_17,
GP_0_16_FN, GPSR0_16,
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
GP_0_12_FN, GPSR0_12,
GP_0_11_FN, GPSR0_11,
GP_0_10_FN, GPSR0_10,
GP_0_9_FN, GPSR0_9,
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
GP_0_5_FN, GPSR0_5,
GP_0_4_FN, GPSR0_4,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP1_31_25 RESERVED */
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
GP_1_19_FN, GPSR1_19,
GP_1_18_FN, GPSR1_18,
GP_1_17_FN, GPSR1_17,
GP_1_16_FN, GPSR1_16,
GP_1_15_FN, GPSR1_15,
GP_1_14_FN, GPSR1_14,
GP_1_13_FN, GPSR1_13,
GP_1_12_FN, GPSR1_12,
GP_1_11_FN, GPSR1_11,
GP_1_10_FN, GPSR1_10,
GP_1_9_FN, GPSR1_9,
GP_1_8_FN, GPSR1_8,
GP_1_7_FN, GPSR1_7,
GP_1_6_FN, GPSR1_6,
GP_1_5_FN, GPSR1_5,
GP_1_4_FN, GPSR1_4,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP2_31_17 RESERVED */
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
GP_2_11_FN, GPSR2_11,
GP_2_10_FN, GPSR2_10,
GP_2_9_FN, GPSR2_9,
GP_2_8_FN, GPSR2_8,
GP_2_7_FN, GPSR2_7,
GP_2_6_FN, GPSR2_6,
GP_2_5_FN, GPSR2_5,
GP_2_4_FN, GPSR2_4,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP3_31_19 RESERVED */
GP_3_18_FN, GPSR3_18,
GP_3_17_FN, GPSR3_17,
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
GP_3_12_FN, GPSR3_12,
GP_3_11_FN, GPSR3_11,
GP_3_10_FN, GPSR3_10,
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
GP_3_6_FN, GPSR3_6,
GP_3_5_FN, GPSR3_5,
GP_3_4_FN, GPSR3_4,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
IP0SR0_31_28
IP0SR0_27_24
IP0SR0_23_20
IP0SR0_19_16
IP0SR0_15_12
IP0SR0_11_8
IP0SR0_7_4
IP0SR0_3_0))
},
{ PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
IP1SR0_31_28
IP1SR0_27_24
IP1SR0_23_20
IP1SR0_19_16
IP1SR0_15_12
IP1SR0_11_8
IP1SR0_7_4
IP1SR0_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
GROUP(-12, 4, 4, 4, 4, 4),
GROUP(
/* IP2SR0_31_20 RESERVED */
IP2SR0_19_16
IP2SR0_15_12
IP2SR0_11_8
IP2SR0_7_4
IP2SR0_3_0))
},
{ PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
IP0SR1_31_28
IP0SR1_27_24
IP0SR1_23_20
IP0SR1_19_16
IP0SR1_15_12
IP0SR1_11_8
IP0SR1_7_4
IP0SR1_3_0))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
GROUP(-20, 2, 2, 2, 2, 2, 2),
GROUP(
/* RESERVED 31-12 */
MOD_SEL1_11_10
MOD_SEL1_9_8
MOD_SEL1_7_6
MOD_SEL1_5_4
MOD_SEL1_3_2
MOD_SEL1_1_0))
},
{ /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
{ RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
{ RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
{ RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
{ RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
{ RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
{ RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
{ RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
{ RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
{ RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
{ RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
{ RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
{ RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
{ RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
{ RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */
{ RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */
{ RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */
{ RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */
{ RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */
{ RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */
{ RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
{ RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
{ RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */
{ RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */
{ RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */
{ RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */
{ RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */
{ RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
{ RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
{ RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
{ RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */
{ RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */
{ RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */
{ RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */
{ RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */
{ RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
} },
{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
{ RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
{ RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
{ RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */
{ RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */
{ RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */
{ RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */
{ RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */
{ RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */
{ RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
{ RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
{ RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */
{ RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */
{ RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */
{ RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */
{ RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */
{ RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
{ RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
{ RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
{ RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
{ RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */
{ RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */
{ RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */
{ RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */
{ RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */
{ RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */
{ RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
{ RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
{ RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
{ RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
} },
{ /* sentinel */ }
};
enum ioctrl_regs {
POC0,
POC1,
POC3,
TD0SEL1,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POC0] = { 0xe60500a0, },
[POC1] = { 0xe60508a0, },
[POC3] = { 0xe60518a0, },
[TD0SEL1] = { 0xe6050920, },
{ /* sentinel */ }
};
static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
*pocctrl = pinmux_ioctrl_regs[POC0].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20))
return bit;
*pocctrl = pinmux_ioctrl_regs[POC1].reg;
if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24))
return bit;
*pocctrl = pinmux_ioctrl_regs[POC3].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18))
return bit;
return -EINVAL;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
[ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
[ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
[ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */
[ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */
[ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
[ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
[ 6] = RCAR_GP_PIN(0, 6), /* RX0 */
[ 7] = RCAR_GP_PIN(0, 7), /* TX0 */
[ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */
[ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
[10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
[11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
[12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
[13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
[14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
[15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
[16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
[17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
[18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
[19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
[20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
[ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
[ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */
[ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */
[ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */
[ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */
[ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */
[ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */
[ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */
[ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */
[ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
[10] = RCAR_GP_PIN(1, 10), /* GP1_10 */
[11] = RCAR_GP_PIN(1, 11), /* GP1_11 */
[12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */
[13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */
[14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */
[15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */
[16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */
[17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */
[18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */
[19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */
[20] = RCAR_GP_PIN(1, 20), /* MMC_DS */
[21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */
[22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */
[23] = RCAR_GP_PIN(1, 23), /* SD_CD */
[24] = RCAR_GP_PIN(1, 24), /* SD_WP */
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
[ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
[ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */
[ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */
[ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */
[ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */
[ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */
[ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */
[ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */
[ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */
[ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
[10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */
[11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */
[12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */
[13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */
[14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */
[15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */
[16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
[ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
[ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */
[ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */
[ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */
[ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */
[ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */
[ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */
[ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */
[ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */
[ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
[10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */
[11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */
[12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */
[13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */
[14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */
[15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */
[16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */
[17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */
[18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
.pin_to_pocctrl = r8a779f0_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a779f0_pinmux_info = {
.name = "r8a779f0_pfc",
.ops = &r8a779f0_pfc_ops,
.unlock_reg = 0x1ff, /* PMMRn mask */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a779f0.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014-2018 Renesas Electronics Europe Limited
*
* Phil Edworthy <[email protected]>
* Based on a driver originally written by Michel Pollet at Renesas.
*/
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
/* Field positions and masks in the pinmux registers */
#define RZN1_L1_PIN_DRIVE_STRENGTH 10
#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
#define RZN1_L1_PIN_PULL 8
#define RZN1_L1_PIN_PULL_NONE 0
#define RZN1_L1_PIN_PULL_UP 1
#define RZN1_L1_PIN_PULL_DOWN 3
#define RZN1_L1_FUNCTION 0
#define RZN1_L1_FUNC_MASK 0xf
#define RZN1_L1_FUNCTION_L2 0xf
/*
* The hardware manual describes two levels of multiplexing, but it's more
* logical to think of the hardware as three levels, with level 3 consisting of
* the multiplexing for Ethernet MDIO signals.
*
* Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
* that level 2 functions are used instead. Level 2 has a lot more options,
* going from 0 to 61. Level 3 allows selection of MDIO functions which can be
* floating, or one of seven internal peripherals. Unfortunately, there are two
* level 2 functions that can select MDIO, and two MDIO channels so we have four
* sets of level 3 functions.
*
* For this driver, we've compounded the numbers together, so:
* 0 to 9 is level 1
* 10 to 71 is 10 + level 2 number
* 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
* 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
* 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
* 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
* Examples:
* Function 28 corresponds UART0
* Function 73 corresponds to MDIO0 to GMAC0
*
* There are 170 configurable pins (called PL_GPIO in the datasheet).
*/
/*
* Structure detailing the HW registers on the RZ/N1 devices.
* Both the Level 1 mux registers and Level 2 mux registers have the same
* structure. The only difference is that Level 2 has additional MDIO registers
* at the end.
*/
struct rzn1_pinctrl_regs {
u32 conf[170];
u32 pad0[86];
u32 status_protect; /* 0x400 */
/* MDIO mux registers, level2 only */
u32 l2_mdio[2];
};
/**
* struct rzn1_pmx_func - describes rzn1 pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
* @num_groups: the number of groups
*/
struct rzn1_pmx_func {
const char *name;
const char **groups;
unsigned int num_groups;
};
/**
* struct rzn1_pin_group - describes an rzn1 pin group
* @name: the name of this specific pin group
* @func: the name of the function selected by this group
* @npins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
* @pin_ids: array of pin_ids, i.e. the value used to select the mux
*/
struct rzn1_pin_group {
const char *name;
const char *func;
unsigned int npins;
unsigned int *pins;
u8 *pin_ids;
};
struct rzn1_pinctrl {
struct device *dev;
struct clk *clk;
struct pinctrl_dev *pctl;
struct rzn1_pinctrl_regs __iomem *lev1;
struct rzn1_pinctrl_regs __iomem *lev2;
u32 lev1_protect_phys;
u32 lev2_protect_phys;
int mdio_func[2];
struct rzn1_pin_group *groups;
unsigned int ngroups;
struct rzn1_pmx_func *functions;
unsigned int nfunctions;
};
#define RZN1_PINS_PROP "pinmux"
#define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
static const struct pinctrl_pin_desc rzn1_pins[] = {
RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
RZN1_PIN(168), RZN1_PIN(169),
};
enum {
LOCK_LEVEL1 = 0x1,
LOCK_LEVEL2 = 0x2,
LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
};
static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
{
/*
* The pinmux configuration is locked by writing the physical address of
* the status_protect register to itself. It is unlocked by writing the
* address | 1.
*/
if (lock & LOCK_LEVEL1) {
u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
writel(val, &ipctl->lev1->status_protect);
}
if (lock & LOCK_LEVEL2) {
u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
writel(val, &ipctl->lev2->status_protect);
}
}
static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
u32 func)
{
if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
ipctl->mdio_func[mdio] = func;
dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
writel(func, &ipctl->lev2->l2_mdio[mdio]);
}
/*
* Using a composite pin description, set the hardware pinmux registers
* with the corresponding values.
* Make sure to unlock write protection and reset it afterward.
*
* NOTE: There is no protection for potential concurrency, it is assumed these
* calls are serialized already.
*/
static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
u32 pin_config, u8 use_locks)
{
u32 l1_cache;
u32 l2_cache;
u32 l1;
u32 l2;
/* Level 3 MDIO multiplexing */
if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
int mdio_channel;
u32 mdio_func;
if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
mdio_channel = 0;
else
mdio_channel = 1;
/* Get MDIO func, and convert the func to the level 2 number */
if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
pin_config = RZN1_FUNC_ETH_MDIO;
} else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
pin_config = RZN1_FUNC_ETH_MDIO_E1;
} else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
pin_config = RZN1_FUNC_ETH_MDIO;
} else {
mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
pin_config = RZN1_FUNC_ETH_MDIO_E1;
}
rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
}
/* Note here, we do not allow anything past the MDIO Mux values */
if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
return -EINVAL;
l1 = readl(&ipctl->lev1->conf[pin]);
l1_cache = l1;
l2 = readl(&ipctl->lev2->conf[pin]);
l2_cache = l2;
dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
if (pin_config < RZN1_FUNC_L2_OFFSET) {
l1 |= (pin_config << RZN1_L1_FUNCTION);
} else {
l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
l2 = pin_config - RZN1_FUNC_L2_OFFSET;
}
/* If either configuration changes, we update both anyway */
if (l1 != l1_cache || l2 != l2_cache) {
writel(l1, &ipctl->lev1->conf[pin]);
writel(l2, &ipctl->lev2->conf[pin]);
}
return 0;
}
static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
const struct rzn1_pinctrl *ipctl, const char *name)
{
unsigned int i;
for (i = 0; i < ipctl->ngroups; i++) {
if (!strcmp(ipctl->groups[i].name, name))
return &ipctl->groups[i];
}
return NULL;
}
static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
return ipctl->ngroups;
}
static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
return ipctl->groups[selector].name;
}
static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector, const unsigned int **pins,
unsigned int *npins)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
if (selector >= ipctl->ngroups)
return -EINVAL;
*pins = ipctl->groups[selector].pins;
*npins = ipctl->groups[selector].npins;
return 0;
}
/*
* This function is called for each pinctl 'Function' node.
* Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
* If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
* Each 'Group' uses pinmux = <...> to detail the pins and data used to select
* the functionality. Each 'Group' has optional pin configurations that apply
* to all pins in the 'Group'.
*/
static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct rzn1_pin_group *grp;
unsigned long *configs = NULL;
unsigned int reserved_maps = *num_maps;
unsigned int num_configs = 0;
unsigned int reserve = 1;
int ret;
dev_dbg(ipctl->dev, "processing node %pOF\n", np);
grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
if (!grp) {
dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
return -EINVAL;
}
/* Get the group's pin configuration */
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
return ret;
}
if (num_configs)
reserve++;
/* Increase the number of maps to cover this group */
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
reserve);
if (ret < 0)
goto out;
/* Associate the group with the function */
ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
grp->name, grp->func);
if (ret < 0)
goto out;
if (num_configs) {
/* Associate the group's pin configuration with the group */
ret = pinctrl_utils_add_map_configs(pctldev, map,
&reserved_maps, num_maps, grp->name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
goto out;
}
dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
grp->func, grp->name, grp->npins);
out:
kfree(configs);
return ret;
}
static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct device_node *child;
int ret;
*map = NULL;
*num_maps = 0;
ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
if (ret < 0)
return ret;
for_each_child_of_node(np, child) {
ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
if (ret < 0) {
of_node_put(child);
return ret;
}
}
return 0;
}
static const struct pinctrl_ops rzn1_pctrl_ops = {
.get_groups_count = rzn1_get_groups_count,
.get_group_name = rzn1_get_group_name,
.get_group_pins = rzn1_get_group_pins,
.dt_node_to_map = rzn1_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
return ipctl->nfunctions;
}
static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
return ipctl->functions[selector].name;
}
static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
*groups = ipctl->functions[selector].groups;
*num_groups = ipctl->functions[selector].num_groups;
return 0;
}
static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
unsigned int group)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct rzn1_pin_group *grp = &ipctl->groups[group];
unsigned int i, grp_pins = grp->npins;
dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
ipctl->functions[selector].name, selector, grp->name, group);
rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
for (i = 0; i < grp_pins; i++)
rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
return 0;
}
static const struct pinmux_ops rzn1_pmx_ops = {
.get_functions_count = rzn1_pmx_get_funcs_count,
.get_function_name = rzn1_pmx_get_func_name,
.get_function_groups = rzn1_pmx_get_groups,
.set_mux = rzn1_set_mux,
};
static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
static const u32 reg_drive[4] = { 4, 6, 8, 12 };
u32 pull, drive, l1mux;
u32 l1, l2, arg = 0;
if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
return -EINVAL;
l1 = readl(&ipctl->lev1->conf[pin]);
l1mux = l1 & RZN1_L1_FUNC_MASK;
pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
if (pull != RZN1_L1_PIN_PULL_UP)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (pull != RZN1_L1_PIN_PULL_DOWN)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_DISABLE:
if (pull != RZN1_L1_PIN_PULL_NONE)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = reg_drive[drive];
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
l2 = readl(&ipctl->lev2->conf[pin]);
if (l1mux == RZN1_L1_FUNCTION_L2) {
if (l2 != 0)
return -EINVAL;
} else if (l1mux != RZN1_FUNC_HIGHZ) {
return -EINVAL;
}
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
unsigned int i;
u32 l1, l1_cache;
u32 drv;
u32 arg;
if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
return -EINVAL;
l1 = readl(&ipctl->lev1->conf[pin]);
l1_cache = l1;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
break;
case PIN_CONFIG_BIAS_DISABLE:
dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
switch (arg) {
case 4:
drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
break;
case 6:
drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
break;
case 8:
drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
break;
case 12:
drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
break;
default:
dev_err(ipctl->dev,
"Drive strength %umA not supported\n",
arg);
return -EINVAL;
}
l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
l1 &= ~RZN1_L1_FUNC_MASK;
l1 |= RZN1_FUNC_HIGHZ;
break;
default:
return -ENOTSUPP;
}
}
if (l1 != l1_cache) {
rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
writel(l1, &ipctl->lev1->conf[pin]);
rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
}
return 0;
}
static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *config)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct rzn1_pin_group *grp = &ipctl->groups[selector];
unsigned long old = 0;
unsigned int i;
dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
for (i = 0; i < grp->npins; i++) {
if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && (old != *config))
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct rzn1_pin_group *grp = &ipctl->groups[selector];
unsigned int i;
int ret;
dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
grp->name, selector, configs, num_configs);
for (i = 0; i < grp->npins; i++) {
unsigned int pin = grp->pins[i];
ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops rzn1_pinconf_ops = {
.is_generic = true,
.pin_config_get = rzn1_pinconf_get,
.pin_config_set = rzn1_pinconf_set,
.pin_config_group_get = rzn1_pinconf_group_get,
.pin_config_group_set = rzn1_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static struct pinctrl_desc rzn1_pinctrl_desc = {
.pctlops = &rzn1_pctrl_ops,
.pmxops = &rzn1_pmx_ops,
.confops = &rzn1_pinconf_ops,
.owner = THIS_MODULE,
};
static int rzn1_pinctrl_parse_groups(struct device_node *np,
struct rzn1_pin_group *grp,
struct rzn1_pinctrl *ipctl)
{
const __be32 *list;
unsigned int i;
int size;
dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
/* Initialise group */
grp->name = np->name;
/*
* The binding format is
* pinmux = <PIN_FUNC_ID CONFIG ...>,
* do sanity check and calculate pins number
*/
list = of_get_property(np, RZN1_PINS_PROP, &size);
if (!list) {
dev_err(ipctl->dev,
"no " RZN1_PINS_PROP " property in node %pOF\n", np);
return -EINVAL;
}
if (!size) {
dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
np);
return -EINVAL;
}
grp->npins = size / sizeof(list[0]);
grp->pin_ids = devm_kmalloc_array(ipctl->dev,
grp->npins, sizeof(grp->pin_ids[0]),
GFP_KERNEL);
grp->pins = devm_kmalloc_array(ipctl->dev,
grp->npins, sizeof(grp->pins[0]),
GFP_KERNEL);
if (!grp->pin_ids || !grp->pins)
return -ENOMEM;
for (i = 0; i < grp->npins; i++) {
u32 pin_id = be32_to_cpu(*list++);
grp->pins[i] = pin_id & 0xff;
grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
}
return grp->npins;
}
static int rzn1_pinctrl_count_function_groups(struct device_node *np)
{
struct device_node *child;
int count = 0;
if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
count++;
for_each_child_of_node(np, child) {
if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
count++;
}
return count;
}
static int rzn1_pinctrl_parse_functions(struct device_node *np,
struct rzn1_pinctrl *ipctl,
unsigned int index)
{
struct rzn1_pmx_func *func;
struct rzn1_pin_group *grp;
struct device_node *child;
unsigned int i = 0;
int ret;
func = &ipctl->functions[index];
/* Initialise function */
func->name = np->name;
func->num_groups = rzn1_pinctrl_count_function_groups(np);
if (func->num_groups == 0) {
dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
dev_dbg(ipctl->dev, "function %s has %d groups\n",
np->name, func->num_groups);
func->groups = devm_kmalloc_array(ipctl->dev,
func->num_groups, sizeof(char *),
GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
func->groups[i] = np->name;
grp = &ipctl->groups[ipctl->ngroups];
grp->func = func->name;
ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
if (ret < 0)
return ret;
i++;
ipctl->ngroups++;
}
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &ipctl->groups[ipctl->ngroups];
grp->func = func->name;
ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
if (ret < 0) {
of_node_put(child);
return ret;
}
i++;
ipctl->ngroups++;
}
dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
np->name, i, func->num_groups);
return 0;
}
static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
struct rzn1_pinctrl *ipctl)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
unsigned int maxgroups = 0;
unsigned int i = 0;
int nfuncs = 0;
int ret;
nfuncs = of_get_child_count(np);
if (nfuncs <= 0)
return 0;
ipctl->nfunctions = nfuncs;
ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
sizeof(*ipctl->functions),
GFP_KERNEL);
if (!ipctl->functions)
return -ENOMEM;
ipctl->ngroups = 0;
for_each_child_of_node(np, child)
maxgroups += rzn1_pinctrl_count_function_groups(child);
ipctl->groups = devm_kmalloc_array(&pdev->dev,
maxgroups,
sizeof(*ipctl->groups),
GFP_KERNEL);
if (!ipctl->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
if (ret < 0) {
of_node_put(child);
return ret;
}
}
return 0;
}
static int rzn1_pinctrl_probe(struct platform_device *pdev)
{
struct rzn1_pinctrl *ipctl;
struct resource *res;
int ret;
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)
return -ENOMEM;
ipctl->mdio_func[0] = -1;
ipctl->mdio_func[1] = -1;
ipctl->lev1 = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ipctl->lev1))
return PTR_ERR(ipctl->lev1);
ipctl->lev1_protect_phys = (u32)res->start + 0x400;
ipctl->lev2 = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
if (IS_ERR(ipctl->lev2))
return PTR_ERR(ipctl->lev2);
ipctl->lev2_protect_phys = (u32)res->start + 0x400;
ipctl->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ipctl->clk))
return PTR_ERR(ipctl->clk);
ret = clk_prepare_enable(ipctl->clk);
if (ret)
return ret;
ipctl->dev = &pdev->dev;
rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
rzn1_pinctrl_desc.pins = rzn1_pins;
rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
if (ret) {
dev_err(&pdev->dev, "fail to probe dt properties\n");
goto err_clk;
}
platform_set_drvdata(pdev, ipctl);
ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
ipctl, &ipctl->pctl);
if (ret) {
dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
goto err_clk;
}
ret = pinctrl_enable(ipctl->pctl);
if (ret)
goto err_clk;
dev_info(&pdev->dev, "probed\n");
return 0;
err_clk:
clk_disable_unprepare(ipctl->clk);
return ret;
}
static int rzn1_pinctrl_remove(struct platform_device *pdev)
{
struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
clk_disable_unprepare(ipctl->clk);
return 0;
}
static const struct of_device_id rzn1_pinctrl_match[] = {
{ .compatible = "renesas,rzn1-pinctrl", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
static struct platform_driver rzn1_pinctrl_driver = {
.probe = rzn1_pinctrl_probe,
.remove = rzn1_pinctrl_remove,
.driver = {
.name = "rzn1-pinctrl",
.of_match_table = rzn1_pinctrl_match,
},
};
static int __init _pinctrl_drv_register(void)
{
return platform_driver_register(&rzn1_pinctrl_driver);
}
subsys_initcall(_pinctrl_drv_register);
MODULE_AUTHOR("Phil Edworthy <[email protected]>");
MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
|
linux-master
|
drivers/pinctrl/renesas/pinctrl-rzn1.c
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// SPDX-License-Identifier: GPL-2.0
/*
* r8a7792 processor support - PFC hardware block.
*
* Copyright (C) 2013-2014 Renesas Electronics Corporation
* Copyright (C) 2016 Cogent Embedded, Inc., <[email protected]>
*/
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
/* GPSR0 */
FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
FN_IP1_3, FN_IP1_4,
/* GPSR1 */
FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
/* GPSR2 */
FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
/* GPSR3 */
FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
/* GPSR4 */
FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
FN_VI0_FIELD,
/* GPSR5 */
FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
FN_VI1_FIELD,
/* GPSR6 */
FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
/* GPSR7 */
FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
/* GPSR8 */
FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
/* GPSR9 */
FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
/* GPSR10 */
FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
FN_CAN1_TX, FN_CAN1_RX,
/* GPSR11 */
FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
FN_ADICHS2, FN_AVS1, FN_AVS2,
/* IPSR0 */
FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
FN_DU0_DB7_C5,
/* IPSR1 */
FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
/* IPSR2 */
FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
FN_VI2_FIELD, FN_AVB_TXD2,
/* IPSR3 */
FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
/* IPSR4 */
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
/* IPSR5 */
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
/* IPSR6 */
FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
/* IPSR7 */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
FN_AUDIO_CLKA, FN_AUDIO_CLKB,
/* MOD_SEL */
FN_SEL_VI1_0, FN_SEL_VI1_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
DU1_DISP_MARK, DU1_CDE_MARK,
D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
A12_MARK, A13_MARK, A14_MARK, A15_MARK,
A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
VI0_FIELD_MARK,
VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_FIELD_MARK,
VI3_D10_Y2_MARK, VI3_FIELD_MARK,
VI4_CLK_MARK,
VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
VI5_FIELD_MARK,
HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
/* IPSR0 */
DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
/* IPSR1 */
DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
/* IPSR2 */
VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
VI2_D10_Y2_MARK, AVB_TXD0_MARK,
VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
/* IPSR3 */
VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
/* IPSR4 */
VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
/* IPSR5 */
VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
/* IPSR6 */
MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
RX3_MARK,
/* IPSR7 */
PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
AUDIO_CLKB_MARK,
PINMUX_MARK_END,
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_SINGLE(DU1_DB2_C0_DATA12),
PINMUX_SINGLE(DU1_DB3_C1_DATA13),
PINMUX_SINGLE(DU1_DB4_C2_DATA14),
PINMUX_SINGLE(DU1_DB5_C3_DATA15),
PINMUX_SINGLE(DU1_DB6_C4),
PINMUX_SINGLE(DU1_DB7_C5),
PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
PINMUX_SINGLE(DU1_DISP),
PINMUX_SINGLE(DU1_CDE),
PINMUX_SINGLE(D0),
PINMUX_SINGLE(D1),
PINMUX_SINGLE(D2),
PINMUX_SINGLE(D3),
PINMUX_SINGLE(D4),
PINMUX_SINGLE(D5),
PINMUX_SINGLE(D6),
PINMUX_SINGLE(D7),
PINMUX_SINGLE(D8),
PINMUX_SINGLE(D9),
PINMUX_SINGLE(D10),
PINMUX_SINGLE(D11),
PINMUX_SINGLE(D12),
PINMUX_SINGLE(D13),
PINMUX_SINGLE(D14),
PINMUX_SINGLE(D15),
PINMUX_SINGLE(A0),
PINMUX_SINGLE(A1),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(A3),
PINMUX_SINGLE(A4),
PINMUX_SINGLE(A5),
PINMUX_SINGLE(A6),
PINMUX_SINGLE(A7),
PINMUX_SINGLE(A8),
PINMUX_SINGLE(A9),
PINMUX_SINGLE(A10),
PINMUX_SINGLE(A11),
PINMUX_SINGLE(A12),
PINMUX_SINGLE(A13),
PINMUX_SINGLE(A14),
PINMUX_SINGLE(A15),
PINMUX_SINGLE(A16),
PINMUX_SINGLE(A17),
PINMUX_SINGLE(A18),
PINMUX_SINGLE(A19),
PINMUX_SINGLE(CS1_N_A26),
PINMUX_SINGLE(EX_CS0_N),
PINMUX_SINGLE(EX_CS1_N),
PINMUX_SINGLE(EX_CS2_N),
PINMUX_SINGLE(EX_CS3_N),
PINMUX_SINGLE(EX_CS4_N),
PINMUX_SINGLE(EX_CS5_N),
PINMUX_SINGLE(BS_N),
PINMUX_SINGLE(RD_N),
PINMUX_SINGLE(RD_WR_N),
PINMUX_SINGLE(WE0_N),
PINMUX_SINGLE(WE1_N),
PINMUX_SINGLE(EX_WAIT0),
PINMUX_SINGLE(IRQ0),
PINMUX_SINGLE(IRQ1),
PINMUX_SINGLE(IRQ2),
PINMUX_SINGLE(IRQ3),
PINMUX_SINGLE(CS0_N),
PINMUX_SINGLE(VI0_CLK),
PINMUX_SINGLE(VI0_CLKENB),
PINMUX_SINGLE(VI0_HSYNC_N),
PINMUX_SINGLE(VI0_VSYNC_N),
PINMUX_SINGLE(VI0_D0_B0_C0),
PINMUX_SINGLE(VI0_D1_B1_C1),
PINMUX_SINGLE(VI0_D2_B2_C2),
PINMUX_SINGLE(VI0_D3_B3_C3),
PINMUX_SINGLE(VI0_D4_B4_C4),
PINMUX_SINGLE(VI0_D5_B5_C5),
PINMUX_SINGLE(VI0_D6_B6_C6),
PINMUX_SINGLE(VI0_D7_B7_C7),
PINMUX_SINGLE(VI0_D8_G0_Y0),
PINMUX_SINGLE(VI0_D9_G1_Y1),
PINMUX_SINGLE(VI0_D10_G2_Y2),
PINMUX_SINGLE(VI0_D11_G3_Y3),
PINMUX_SINGLE(VI0_FIELD),
PINMUX_SINGLE(VI1_CLK),
PINMUX_SINGLE(VI1_CLKENB),
PINMUX_SINGLE(VI1_HSYNC_N),
PINMUX_SINGLE(VI1_VSYNC_N),
PINMUX_SINGLE(VI1_D0_B0_C0),
PINMUX_SINGLE(VI1_D1_B1_C1),
PINMUX_SINGLE(VI1_D2_B2_C2),
PINMUX_SINGLE(VI1_D3_B3_C3),
PINMUX_SINGLE(VI1_D4_B4_C4),
PINMUX_SINGLE(VI1_D5_B5_C5),
PINMUX_SINGLE(VI1_D6_B6_C6),
PINMUX_SINGLE(VI1_D7_B7_C7),
PINMUX_SINGLE(VI1_D8_G0_Y0),
PINMUX_SINGLE(VI1_D9_G1_Y1),
PINMUX_SINGLE(VI1_D10_G2_Y2),
PINMUX_SINGLE(VI1_D11_G3_Y3),
PINMUX_SINGLE(VI1_FIELD),
PINMUX_SINGLE(VI3_D10_Y2),
PINMUX_SINGLE(VI3_FIELD),
PINMUX_SINGLE(VI4_CLK),
PINMUX_SINGLE(VI5_CLK),
PINMUX_SINGLE(VI5_D9_Y1),
PINMUX_SINGLE(VI5_D10_Y2),
PINMUX_SINGLE(VI5_D11_Y3),
PINMUX_SINGLE(VI5_FIELD),
PINMUX_SINGLE(HRTS0_N),
PINMUX_SINGLE(HCTS1_N),
PINMUX_SINGLE(SCK0),
PINMUX_SINGLE(CTS0_N),
PINMUX_SINGLE(RTS0_N),
PINMUX_SINGLE(TX0),
PINMUX_SINGLE(RX0),
PINMUX_SINGLE(SCK1),
PINMUX_SINGLE(CTS1_N),
PINMUX_SINGLE(RTS1_N),
PINMUX_SINGLE(TX1),
PINMUX_SINGLE(RX1),
PINMUX_SINGLE(SCIF_CLK),
PINMUX_SINGLE(CAN0_TX),
PINMUX_SINGLE(CAN0_RX),
PINMUX_SINGLE(CAN_CLK),
PINMUX_SINGLE(CAN1_TX),
PINMUX_SINGLE(CAN1_RX),
PINMUX_SINGLE(SD0_CLK),
PINMUX_SINGLE(SD0_CMD),
PINMUX_SINGLE(SD0_DAT0),
PINMUX_SINGLE(SD0_DAT1),
PINMUX_SINGLE(SD0_DAT2),
PINMUX_SINGLE(SD0_DAT3),
PINMUX_SINGLE(SD0_CD),
PINMUX_SINGLE(SD0_WP),
PINMUX_SINGLE(ADICLK),
PINMUX_SINGLE(ADICS_SAMP),
PINMUX_SINGLE(ADIDATA),
PINMUX_SINGLE(ADICHS0),
PINMUX_SINGLE(ADICHS1),
PINMUX_SINGLE(ADICHS2),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
PINMUX_IPSR_GPSR(IP1_17, A20),
PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
PINMUX_IPSR_GPSR(IP1_18, A21),
PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
PINMUX_IPSR_GPSR(IP1_19, A22),
PINMUX_IPSR_GPSR(IP1_19, IO2),
PINMUX_IPSR_GPSR(IP1_20, A23),
PINMUX_IPSR_GPSR(IP1_20, IO3),
PINMUX_IPSR_GPSR(IP1_21, A24),
PINMUX_IPSR_GPSR(IP1_21, SPCLK),
PINMUX_IPSR_GPSR(IP1_22, A25),
PINMUX_IPSR_GPSR(IP1_22, SSL),
/* IPSR2 */
PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
/* IPSR4 */
PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP6_0, HSCK0),
PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP6_2, HTX0),
PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
PINMUX_IPSR_GPSR(IP6_3, HRX0),
PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP6_4, HSCK1),
PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP6_6, HTX1),
PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP6_7, HRX1),
PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
PINMUX_IPSR_GPSR(IP6_11_10, TX2),
PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
PINMUX_IPSR_GPSR(IP6_13_12, RX2),
PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
PINMUX_IPSR_GPSR(IP6_16, TX3),
PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
PINMUX_IPSR_GPSR(IP6_18_17, RX3),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
PINMUX_IPSR_GPSR(IP7_6, PWM3),
PINMUX_IPSR_GPSR(IP7_7, PWM4),
PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB -------------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
RCAR_GP_PIN(7, 9),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
RCAR_GP_PIN(7, 10),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
RCAR_GP_PIN(7, 11),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdio_pins[] = {
RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
RCAR_GP_PIN(6, 12),
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK,
AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
RCAR_GP_PIN(6, 11),
};
static const unsigned int avb_gmii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
AVB_TXD6_MARK, AVB_TXD7_MARK,
AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
AVB_RXD6_MARK, AVB_RXD7_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
static const unsigned int avb_avtp_match_pins[] = {
RCAR_GP_PIN(7, 15),
};
static const unsigned int avb_avtp_match_mux[] = {
AVB_AVTP_MATCH_MARK,
};
/* - CAN -------------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
};
static const unsigned int can0_data_mux[] = {
CAN0_TX_MARK, CAN0_RX_MARK,
};
static const unsigned int can1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
};
static const unsigned int can1_data_mux[] = {
CAN1_TX_MARK, CAN1_RX_MARK,
};
static const unsigned int can_clk_pins[] = {
/* CAN_CLK */
RCAR_GP_PIN(10, 29),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du0_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
};
static const unsigned int du0_rgb666_mux[] = {
DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
};
static const unsigned int du0_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
};
static const unsigned int du0_rgb888_mux[] = {
DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
DU0_DB1_MARK, DU0_DB0_MARK,
};
static const unsigned int du0_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
};
static const unsigned int du0_sync_mux[] = {
DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
};
static const unsigned int du0_oddf_pins[] = {
/* EXODDF/ODDF/DISP/CDE */
RCAR_GP_PIN(0, 26),
};
static const unsigned int du0_oddf_mux[] = {
DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
};
static const unsigned int du0_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(0, 27),
};
static const unsigned int du0_disp_mux[] = {
DU0_DISP_MARK,
};
static const unsigned int du0_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(0, 28),
};
static const unsigned int du0_cde_mux[] = {
DU0_CDE_MARK,
};
static const unsigned int du1_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
};
static const unsigned int du1_rgb666_mux[] = {
DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
};
static const unsigned int du1_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
};
static const unsigned int du1_sync_mux[] = {
DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
};
static const unsigned int du1_oddf_pins[] = {
/* EXODDF/ODDF/DISP/CDE */
RCAR_GP_PIN(1, 20),
};
static const unsigned int du1_oddf_mux[] = {
DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
};
static const unsigned int du1_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(1, 21),
};
static const unsigned int du1_disp_mux[] = {
DU1_DISP_MARK,
};
static const unsigned int du1_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(1, 22),
};
static const unsigned int du1_cde_mux[] = {
DU1_CDE_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ0 */
RCAR_GP_PIN(3, 19),
};
static const unsigned int intc_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_irq1_pins[] = {
/* IRQ1 */
RCAR_GP_PIN(3, 20),
};
static const unsigned int intc_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_irq2_pins[] = {
/* IRQ2 */
RCAR_GP_PIN(3, 21),
};
static const unsigned int intc_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_irq3_pins[] = {
/* IRQ3 */
RCAR_GP_PIN(3, 22),
};
static const unsigned int intc_irq3_mux[] = {
IRQ3_MARK,
};
/* - LBSC ------------------------------------------------------------------- */
static const unsigned int lbsc_cs0_pins[] = {
/* CS0# */
RCAR_GP_PIN(3, 27),
};
static const unsigned int lbsc_cs0_mux[] = {
CS0_N_MARK,
};
static const unsigned int lbsc_cs1_pins[] = {
/* CS1#_A26 */
RCAR_GP_PIN(3, 6),
};
static const unsigned int lbsc_cs1_mux[] = {
CS1_N_A26_MARK,
};
static const unsigned int lbsc_ex_cs0_pins[] = {
/* EX_CS0# */
RCAR_GP_PIN(3, 7),
};
static const unsigned int lbsc_ex_cs0_mux[] = {
EX_CS0_N_MARK,
};
static const unsigned int lbsc_ex_cs1_pins[] = {
/* EX_CS1# */
RCAR_GP_PIN(3, 8),
};
static const unsigned int lbsc_ex_cs1_mux[] = {
EX_CS1_N_MARK,
};
static const unsigned int lbsc_ex_cs2_pins[] = {
/* EX_CS2# */
RCAR_GP_PIN(3, 9),
};
static const unsigned int lbsc_ex_cs2_mux[] = {
EX_CS2_N_MARK,
};
static const unsigned int lbsc_ex_cs3_pins[] = {
/* EX_CS3# */
RCAR_GP_PIN(3, 10),
};
static const unsigned int lbsc_ex_cs3_mux[] = {
EX_CS3_N_MARK,
};
static const unsigned int lbsc_ex_cs4_pins[] = {
/* EX_CS4# */
RCAR_GP_PIN(3, 11),
};
static const unsigned int lbsc_ex_cs4_mux[] = {
EX_CS4_N_MARK,
};
static const unsigned int lbsc_ex_cs5_pins[] = {
/* EX_CS5# */
RCAR_GP_PIN(3, 12),
};
static const unsigned int lbsc_ex_cs5_mux[] = {
EX_CS5_N_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 0),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(10, 1),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(10, 4),
};
static const unsigned int msiof0_rx_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(10, 3),
};
static const unsigned int msiof0_tx_mux[] = {
MSIOF0_TXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 5),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(10, 6),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_rx_pins[] = {
/* RXD */
RCAR_GP_PIN(10, 9),
};
static const unsigned int msiof1_rx_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_tx_pins[] = {
/* TXD */
RCAR_GP_PIN(10, 8),
};
static const unsigned int msiof1_tx_mux[] = {
MSIOF1_TXD_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
};
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24),
};
static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 10),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
};
static const unsigned int scif1_data_mux[] = {
RX1_MARK, TX1_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 15),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
};
static const unsigned int scif2_data_mux[] = {
RX2_MARK, TX2_MARK,
};
static const unsigned int scif2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 20),
};
static const unsigned int scif2_clk_mux[] = {
SCK2_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
};
static const unsigned int scif3_data_mux[] = {
RX3_MARK, TX3_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(10, 23),
};
static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data_pins[] = {
/* DAT[0-3] */
RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
};
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
};
static const unsigned int sdhi0_ctrl_mux[] = {
SD0_CLK_MARK, SD0_CMD_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
RCAR_GP_PIN(11, 11),
};
static const unsigned int sdhi0_cd_mux[] = {
SD0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
RCAR_GP_PIN(11, 12),
};
static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
/* G */
RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
/* R */
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
};
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
/* G */
VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
/* R */
VI0_D16_R0_MARK, VI0_D17_R1_MARK,
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
/* G */
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
/* R */
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
};
static const unsigned int vin0_data18_mux[] = {
/* B */
VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
/* G */
VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
/* R */
VI0_D18_R2_MARK, VI0_D19_R3_MARK,
VI0_D20_R4_MARK, VI0_D21_R5_MARK,
VI0_D22_R6_MARK, VI0_D23_R7_MARK,
};
static const unsigned int vin0_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
};
static const unsigned int vin0_sync_mux[] = {
VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
};
static const unsigned int vin0_field_pins[] = {
RCAR_GP_PIN(4, 16),
};
static const unsigned int vin0_field_mux[] = {
VI0_FIELD_MARK,
};
static const unsigned int vin0_clkenb_pins[] = {
RCAR_GP_PIN(4, 1),
};
static const unsigned int vin0_clkenb_mux[] = {
VI0_CLKENB_MARK,
};
static const unsigned int vin0_clk_pins[] = {
RCAR_GP_PIN(4, 0),
};
static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const unsigned int vin1_data_pins[] = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const unsigned int vin1_data_mux[] = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_data18_pins[] = {
/* B */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
/* R */
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const unsigned int vin1_data18_mux[] = {
/* B */
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
/* R */
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_data_b_pins[] = {
/* B */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
/* R */
RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const unsigned int vin1_data_b_mux[] = {
/* B */
VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
/* R */
VI1_D16_R0_MARK, VI1_D17_R1_MARK,
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_data18_b_pins[] = {
/* B */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
/* G */
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
/* R */
RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
};
static const unsigned int vin1_data18_b_mux[] = {
/* B */
VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
/* G */
VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
/* R */
VI1_D18_R2_MARK, VI1_D19_R3_MARK,
VI1_D20_R4_MARK, VI1_D21_R5_MARK,
VI1_D22_R6_MARK, VI1_D23_R7_MARK,
};
static const unsigned int vin1_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
};
static const unsigned int vin1_sync_mux[] = {
VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
};
static const unsigned int vin1_field_pins[] = {
RCAR_GP_PIN(5, 16),
};
static const unsigned int vin1_field_mux[] = {
VI1_FIELD_MARK,
};
static const unsigned int vin1_clkenb_pins[] = {
RCAR_GP_PIN(5, 1),
};
static const unsigned int vin1_clkenb_mux[] = {
VI1_CLKENB_MARK,
};
static const unsigned int vin1_clk_pins[] = {
RCAR_GP_PIN(5, 0),
};
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
/* - VIN2 ------------------------------------------------------------------- */
static const unsigned int vin2_data_pins[] = {
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
};
static const unsigned int vin2_data_mux[] = {
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
VI2_D4_C4_MARK, VI2_D5_C5_MARK,
VI2_D6_C6_MARK, VI2_D7_C7_MARK,
VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
};
static const unsigned int vin2_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
};
static const unsigned int vin2_sync_mux[] = {
VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
};
static const unsigned int vin2_field_pins[] = {
RCAR_GP_PIN(6, 16),
};
static const unsigned int vin2_field_mux[] = {
VI2_FIELD_MARK,
};
static const unsigned int vin2_clkenb_pins[] = {
RCAR_GP_PIN(6, 1),
};
static const unsigned int vin2_clkenb_mux[] = {
VI2_CLKENB_MARK,
};
static const unsigned int vin2_clk_pins[] = {
RCAR_GP_PIN(6, 0),
};
static const unsigned int vin2_clk_mux[] = {
VI2_CLK_MARK,
};
/* - VIN3 ------------------------------------------------------------------- */
static const unsigned int vin3_data_pins[] = {
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
};
static const unsigned int vin3_data_mux[] = {
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
VI3_D4_C4_MARK, VI3_D5_C5_MARK,
VI3_D6_C6_MARK, VI3_D7_C7_MARK,
VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
};
static const unsigned int vin3_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
};
static const unsigned int vin3_sync_mux[] = {
VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
};
static const unsigned int vin3_field_pins[] = {
RCAR_GP_PIN(7, 16),
};
static const unsigned int vin3_field_mux[] = {
VI3_FIELD_MARK,
};
static const unsigned int vin3_clkenb_pins[] = {
RCAR_GP_PIN(7, 1),
};
static const unsigned int vin3_clkenb_mux[] = {
VI3_CLKENB_MARK,
};
static const unsigned int vin3_clk_pins[] = {
RCAR_GP_PIN(7, 0),
};
static const unsigned int vin3_clk_mux[] = {
VI3_CLK_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data_pins[] = {
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
};
static const unsigned int vin4_data_mux[] = {
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
VI4_D4_C4_MARK, VI4_D5_C5_MARK,
VI4_D6_C6_MARK, VI4_D7_C7_MARK,
VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
RCAR_GP_PIN(8, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
RCAR_GP_PIN(8, 1),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
RCAR_GP_PIN(8, 0),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
};
static const unsigned int vin5_data_mux[] = {
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
VI5_D4_C4_MARK, VI5_D5_C5_MARK,
VI5_D6_C6_MARK, VI5_D7_C7_MARK,
VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(9, 16),
};
static const unsigned int vin5_field_mux[] = {
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(9, 1),
};
static const unsigned int vin5_clkenb_mux[] = {
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(9, 0),
};
static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
SH_PFC_PIN_GROUP(avb_avtp_match),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(du0_rgb666),
SH_PFC_PIN_GROUP(du0_rgb888),
SH_PFC_PIN_GROUP(du0_sync),
SH_PFC_PIN_GROUP(du0_oddf),
SH_PFC_PIN_GROUP(du0_disp),
SH_PFC_PIN_GROUP(du0_cde),
SH_PFC_PIN_GROUP(du1_rgb666),
SH_PFC_PIN_GROUP(du1_sync),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_disp),
SH_PFC_PIN_GROUP(du1_cde),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
SH_PFC_PIN_GROUP(intc_irq3),
SH_PFC_PIN_GROUP(lbsc_cs0),
SH_PFC_PIN_GROUP(lbsc_cs1),
SH_PFC_PIN_GROUP(lbsc_ex_cs0),
SH_PFC_PIN_GROUP(lbsc_ex_cs1),
SH_PFC_PIN_GROUP(lbsc_ex_cs2),
SH_PFC_PIN_GROUP(lbsc_ex_cs3),
SH_PFC_PIN_GROUP(lbsc_ex_cs4),
SH_PFC_PIN_GROUP(lbsc_ex_cs5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_rx),
SH_PFC_PIN_GROUP(msiof0_tx),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_rx),
SH_PFC_PIN_GROUP(msiof1_tx),
SH_PFC_PIN_GROUP(qspi_ctrl),
BUS_DATA_PIN_GROUP(qspi_data, 2),
BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data),
SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(scif2_data),
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
BUS_DATA_PIN_GROUP(vin1_data, 24),
BUS_DATA_PIN_GROUP(vin1_data, 20),
SH_PFC_PIN_GROUP(vin1_data18),
BUS_DATA_PIN_GROUP(vin1_data, 16),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
BUS_DATA_PIN_GROUP(vin2_data, 16),
BUS_DATA_PIN_GROUP(vin2_data, 12),
BUS_DATA_PIN_GROUP(vin2_data, 10),
BUS_DATA_PIN_GROUP(vin2_data, 8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
SH_PFC_PIN_GROUP(vin2_clkenb),
SH_PFC_PIN_GROUP(vin2_clk),
BUS_DATA_PIN_GROUP(vin3_data, 16),
BUS_DATA_PIN_GROUP(vin3_data, 12),
BUS_DATA_PIN_GROUP(vin3_data, 10),
BUS_DATA_PIN_GROUP(vin3_data, 8),
SH_PFC_PIN_GROUP(vin3_sync),
SH_PFC_PIN_GROUP(vin3_field),
SH_PFC_PIN_GROUP(vin3_clkenb),
SH_PFC_PIN_GROUP(vin3_clk),
BUS_DATA_PIN_GROUP(vin4_data, 12),
BUS_DATA_PIN_GROUP(vin4_data, 10),
BUS_DATA_PIN_GROUP(vin4_data, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdio",
"avb_mii",
"avb_gmii",
"avb_avtp_match",
};
static const char * const can0_groups[] = {
"can0_data",
"can_clk",
};
static const char * const can1_groups[] = {
"can1_data",
"can_clk",
};
static const char * const du0_groups[] = {
"du0_rgb666",
"du0_rgb888",
"du0_sync",
"du0_oddf",
"du0_disp",
"du0_cde",
};
static const char * const du1_groups[] = {
"du1_rgb666",
"du1_sync",
"du1_oddf",
"du1_disp",
"du1_cde",
};
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
"intc_irq2",
"intc_irq3",
};
static const char * const lbsc_groups[] = {
"lbsc_cs0",
"lbsc_cs1",
"lbsc_ex_cs0",
"lbsc_ex_cs1",
"lbsc_ex_cs2",
"lbsc_ex_cs3",
"lbsc_ex_cs4",
"lbsc_ex_cs5",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_rx",
"msiof0_tx",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_rx",
"msiof1_tx",
};
static const char * const qspi_groups[] = {
"qspi_ctrl",
"qspi_data2",
"qspi_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
"scif1_data",
"scif1_clk",
"scif1_ctrl",
};
static const char * const scif2_groups[] = {
"scif2_data",
"scif2_clk",
};
static const char * const scif3_groups[] = {
"scif3_data",
"scif3_clk",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const vin0_groups[] = {
"vin0_data24",
"vin0_data20",
"vin0_data18",
"vin0_data16",
"vin0_data12",
"vin0_data10",
"vin0_data8",
"vin0_sync",
"vin0_field",
"vin0_clkenb",
"vin0_clk",
};
static const char * const vin1_groups[] = {
"vin1_data24",
"vin1_data20",
"vin1_data18",
"vin1_data16",
"vin1_data12",
"vin1_data10",
"vin1_data8",
"vin1_data24_b",
"vin1_data20_b",
"vin1_data18_b",
"vin1_data16_b",
"vin1_sync",
"vin1_field",
"vin1_clkenb",
"vin1_clk",
};
static const char * const vin2_groups[] = {
"vin2_data16",
"vin2_data12",
"vin2_data10",
"vin2_data8",
"vin2_sync",
"vin2_field",
"vin2_clkenb",
"vin2_clk",
};
static const char * const vin3_groups[] = {
"vin3_data16",
"vin3_data12",
"vin3_data10",
"vin3_data8",
"vin3_sync",
"vin3_field",
"vin3_clkenb",
"vin3_clk",
};
static const char * const vin4_groups[] = {
"vin4_data12",
"vin4_data10",
"vin4_data8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data12",
"vin5_data10",
"vin5_data8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lbsc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(vin0),
SH_PFC_FUNCTION(vin1),
SH_PFC_FUNCTION(vin2),
SH_PFC_FUNCTION(vin3),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_0_28_FN, FN_IP1_4,
GP_0_27_FN, FN_IP1_3,
GP_0_26_FN, FN_IP1_2,
GP_0_25_FN, FN_IP1_1,
GP_0_24_FN, FN_IP1_0,
GP_0_23_FN, FN_IP0_23,
GP_0_22_FN, FN_IP0_22,
GP_0_21_FN, FN_IP0_21,
GP_0_20_FN, FN_IP0_20,
GP_0_19_FN, FN_IP0_19,
GP_0_18_FN, FN_IP0_18,
GP_0_17_FN, FN_IP0_17,
GP_0_16_FN, FN_IP0_16,
GP_0_15_FN, FN_IP0_15,
GP_0_14_FN, FN_IP0_14,
GP_0_13_FN, FN_IP0_13,
GP_0_12_FN, FN_IP0_12,
GP_0_11_FN, FN_IP0_11,
GP_0_10_FN, FN_IP0_10,
GP_0_9_FN, FN_IP0_9,
GP_0_8_FN, FN_IP0_8,
GP_0_7_FN, FN_IP0_7,
GP_0_6_FN, FN_IP0_6,
GP_0_5_FN, FN_IP0_5,
GP_0_4_FN, FN_IP0_4,
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0 ))
},
{ PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP1_31_23 RESERVED */
GP_1_22_FN, FN_DU1_CDE,
GP_1_21_FN, FN_DU1_DISP,
GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
GP_1_17_FN, FN_DU1_DB7_C5,
GP_1_16_FN, FN_DU1_DB6_C4,
GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
GP_1_11_FN, FN_IP1_16,
GP_1_10_FN, FN_IP1_15,
GP_1_9_FN, FN_IP1_14,
GP_1_8_FN, FN_IP1_13,
GP_1_7_FN, FN_IP1_12,
GP_1_6_FN, FN_IP1_11,
GP_1_5_FN, FN_IP1_10,
GP_1_4_FN, FN_IP1_9,
GP_1_3_FN, FN_IP1_8,
GP_1_2_FN, FN_IP1_7,
GP_1_1_FN, FN_IP1_6,
GP_1_0_FN, FN_IP1_5, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_A15,
GP_2_30_FN, FN_A14,
GP_2_29_FN, FN_A13,
GP_2_28_FN, FN_A12,
GP_2_27_FN, FN_A11,
GP_2_26_FN, FN_A10,
GP_2_25_FN, FN_A9,
GP_2_24_FN, FN_A8,
GP_2_23_FN, FN_A7,
GP_2_22_FN, FN_A6,
GP_2_21_FN, FN_A5,
GP_2_20_FN, FN_A4,
GP_2_19_FN, FN_A3,
GP_2_18_FN, FN_A2,
GP_2_17_FN, FN_A1,
GP_2_16_FN, FN_A0,
GP_2_15_FN, FN_D15,
GP_2_14_FN, FN_D14,
GP_2_13_FN, FN_D13,
GP_2_12_FN, FN_D12,
GP_2_11_FN, FN_D11,
GP_2_10_FN, FN_D10,
GP_2_9_FN, FN_D9,
GP_2_8_FN, FN_D8,
GP_2_7_FN, FN_D7,
GP_2_6_FN, FN_D6,
GP_2_5_FN, FN_D5,
GP_2_4_FN, FN_D4,
GP_2_3_FN, FN_D3,
GP_2_2_FN, FN_D2,
GP_2_1_FN, FN_D1,
GP_2_0_FN, FN_D0 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
GP_3_27_FN, FN_CS0_N,
GP_3_26_FN, FN_IP1_22,
GP_3_25_FN, FN_IP1_21,
GP_3_24_FN, FN_IP1_20,
GP_3_23_FN, FN_IP1_19,
GP_3_22_FN, FN_IRQ3,
GP_3_21_FN, FN_IRQ2,
GP_3_20_FN, FN_IRQ1,
GP_3_19_FN, FN_IRQ0,
GP_3_18_FN, FN_EX_WAIT0,
GP_3_17_FN, FN_WE1_N,
GP_3_16_FN, FN_WE0_N,
GP_3_15_FN, FN_RD_WR_N,
GP_3_14_FN, FN_RD_N,
GP_3_13_FN, FN_BS_N,
GP_3_12_FN, FN_EX_CS5_N,
GP_3_11_FN, FN_EX_CS4_N,
GP_3_10_FN, FN_EX_CS3_N,
GP_3_9_FN, FN_EX_CS2_N,
GP_3_8_FN, FN_EX_CS1_N,
GP_3_7_FN, FN_EX_CS0_N,
GP_3_6_FN, FN_CS1_N_A26,
GP_3_5_FN, FN_IP1_18,
GP_3_4_FN, FN_IP1_17,
GP_3_3_FN, FN_A19,
GP_3_2_FN, FN_A18,
GP_3_1_FN, FN_A17,
GP_3_0_FN, FN_A16 ))
},
{ PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_17 RESERVED */
GP_4_16_FN, FN_VI0_FIELD,
GP_4_15_FN, FN_VI0_D11_G3_Y3,
GP_4_14_FN, FN_VI0_D10_G2_Y2,
GP_4_13_FN, FN_VI0_D9_G1_Y1,
GP_4_12_FN, FN_VI0_D8_G0_Y0,
GP_4_11_FN, FN_VI0_D7_B7_C7,
GP_4_10_FN, FN_VI0_D6_B6_C6,
GP_4_9_FN, FN_VI0_D5_B5_C5,
GP_4_8_FN, FN_VI0_D4_B4_C4,
GP_4_7_FN, FN_VI0_D3_B3_C3,
GP_4_6_FN, FN_VI0_D2_B2_C2,
GP_4_5_FN, FN_VI0_D1_B1_C1,
GP_4_4_FN, FN_VI0_D0_B0_C0,
GP_4_3_FN, FN_VI0_VSYNC_N,
GP_4_2_FN, FN_VI0_HSYNC_N,
GP_4_1_FN, FN_VI0_CLKENB,
GP_4_0_FN, FN_VI0_CLK ))
},
{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP5_31_17 RESERVED */
GP_5_16_FN, FN_VI1_FIELD,
GP_5_15_FN, FN_VI1_D11_G3_Y3,
GP_5_14_FN, FN_VI1_D10_G2_Y2,
GP_5_13_FN, FN_VI1_D9_G1_Y1,
GP_5_12_FN, FN_VI1_D8_G0_Y0,
GP_5_11_FN, FN_VI1_D7_B7_C7,
GP_5_10_FN, FN_VI1_D6_B6_C6,
GP_5_9_FN, FN_VI1_D5_B5_C5,
GP_5_8_FN, FN_VI1_D4_B4_C4,
GP_5_7_FN, FN_VI1_D3_B3_C3,
GP_5_6_FN, FN_VI1_D2_B2_C2,
GP_5_5_FN, FN_VI1_D1_B1_C1,
GP_5_4_FN, FN_VI1_D0_B0_C0,
GP_5_3_FN, FN_VI1_VSYNC_N,
GP_5_2_FN, FN_VI1_HSYNC_N,
GP_5_1_FN, FN_VI1_CLKENB,
GP_5_0_FN, FN_VI1_CLK ))
},
{ PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP6_31_17 RESERVED */
GP_6_16_FN, FN_IP2_16,
GP_6_15_FN, FN_IP2_15,
GP_6_14_FN, FN_IP2_14,
GP_6_13_FN, FN_IP2_13,
GP_6_12_FN, FN_IP2_12,
GP_6_11_FN, FN_IP2_11,
GP_6_10_FN, FN_IP2_10,
GP_6_9_FN, FN_IP2_9,
GP_6_8_FN, FN_IP2_8,
GP_6_7_FN, FN_IP2_7,
GP_6_6_FN, FN_IP2_6,
GP_6_5_FN, FN_IP2_5,
GP_6_4_FN, FN_IP2_4,
GP_6_3_FN, FN_IP2_3,
GP_6_2_FN, FN_IP2_2,
GP_6_1_FN, FN_IP2_1,
GP_6_0_FN, FN_IP2_0 ))
},
{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP7_31_17 RESERVED */
GP_7_16_FN, FN_VI3_FIELD,
GP_7_15_FN, FN_IP3_14,
GP_7_14_FN, FN_VI3_D10_Y2,
GP_7_13_FN, FN_IP3_13,
GP_7_12_FN, FN_IP3_12,
GP_7_11_FN, FN_IP3_11,
GP_7_10_FN, FN_IP3_10,
GP_7_9_FN, FN_IP3_9,
GP_7_8_FN, FN_IP3_8,
GP_7_7_FN, FN_IP3_7,
GP_7_6_FN, FN_IP3_6,
GP_7_5_FN, FN_IP3_5,
GP_7_4_FN, FN_IP3_4,
GP_7_3_FN, FN_IP3_3,
GP_7_2_FN, FN_IP3_2,
GP_7_1_FN, FN_IP3_1,
GP_7_0_FN, FN_IP3_0 ))
},
{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP8_31_17 RESERVED */
GP_8_16_FN, FN_IP4_24,
GP_8_15_FN, FN_IP4_23,
GP_8_14_FN, FN_IP4_22,
GP_8_13_FN, FN_IP4_21,
GP_8_12_FN, FN_IP4_20_19,
GP_8_11_FN, FN_IP4_18_17,
GP_8_10_FN, FN_IP4_16_15,
GP_8_9_FN, FN_IP4_14_13,
GP_8_8_FN, FN_IP4_12_11,
GP_8_7_FN, FN_IP4_10_9,
GP_8_6_FN, FN_IP4_8_7,
GP_8_5_FN, FN_IP4_6_5,
GP_8_4_FN, FN_IP4_4,
GP_8_3_FN, FN_IP4_3_2,
GP_8_2_FN, FN_IP4_1,
GP_8_1_FN, FN_IP4_0,
GP_8_0_FN, FN_VI4_CLK ))
},
{ PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1),
GROUP(
/* GP9_31_17 RESERVED */
GP_9_16_FN, FN_VI5_FIELD,
GP_9_15_FN, FN_VI5_D11_Y3,
GP_9_14_FN, FN_VI5_D10_Y2,
GP_9_13_FN, FN_VI5_D9_Y1,
GP_9_12_FN, FN_IP5_11,
GP_9_11_FN, FN_IP5_10,
GP_9_10_FN, FN_IP5_9,
GP_9_9_FN, FN_IP5_8,
GP_9_8_FN, FN_IP5_7,
GP_9_7_FN, FN_IP5_6,
GP_9_6_FN, FN_IP5_5,
GP_9_5_FN, FN_IP5_4,
GP_9_4_FN, FN_IP5_3,
GP_9_3_FN, FN_IP5_2,
GP_9_2_FN, FN_IP5_1,
GP_9_1_FN, FN_IP5_0,
GP_9_0_FN, FN_VI5_CLK ))
},
{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
GP_10_31_FN, FN_CAN1_RX,
GP_10_30_FN, FN_CAN1_TX,
GP_10_29_FN, FN_CAN_CLK,
GP_10_28_FN, FN_CAN0_RX,
GP_10_27_FN, FN_CAN0_TX,
GP_10_26_FN, FN_SCIF_CLK,
GP_10_25_FN, FN_IP6_18_17,
GP_10_24_FN, FN_IP6_16,
GP_10_23_FN, FN_IP6_15_14,
GP_10_22_FN, FN_IP6_13_12,
GP_10_21_FN, FN_IP6_11_10,
GP_10_20_FN, FN_IP6_9_8,
GP_10_19_FN, FN_RX1,
GP_10_18_FN, FN_TX1,
GP_10_17_FN, FN_RTS1_N,
GP_10_16_FN, FN_CTS1_N,
GP_10_15_FN, FN_SCK1,
GP_10_14_FN, FN_RX0,
GP_10_13_FN, FN_TX0,
GP_10_12_FN, FN_RTS0_N,
GP_10_11_FN, FN_CTS0_N,
GP_10_10_FN, FN_SCK0,
GP_10_9_FN, FN_IP6_7,
GP_10_8_FN, FN_IP6_6,
GP_10_7_FN, FN_HCTS1_N,
GP_10_6_FN, FN_IP6_5,
GP_10_5_FN, FN_IP6_4,
GP_10_4_FN, FN_IP6_3,
GP_10_3_FN, FN_IP6_2,
GP_10_2_FN, FN_HRTS0_N,
GP_10_1_FN, FN_IP6_1,
GP_10_0_FN, FN_IP6_0 ))
},
{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
0, 0,
0, 0,
GP_11_29_FN, FN_AVS2,
GP_11_28_FN, FN_AVS1,
GP_11_27_FN, FN_ADICHS2,
GP_11_26_FN, FN_ADICHS1,
GP_11_25_FN, FN_ADICHS0,
GP_11_24_FN, FN_ADIDATA,
GP_11_23_FN, FN_ADICS_SAMP,
GP_11_22_FN, FN_ADICLK,
GP_11_21_FN, FN_IP7_20,
GP_11_20_FN, FN_IP7_19,
GP_11_19_FN, FN_IP7_18,
GP_11_18_FN, FN_IP7_17,
GP_11_17_FN, FN_IP7_16,
GP_11_16_FN, FN_IP7_15_14,
GP_11_15_FN, FN_IP7_13_12,
GP_11_14_FN, FN_IP7_11_10,
GP_11_13_FN, FN_IP7_9_8,
GP_11_12_FN, FN_SD0_WP,
GP_11_11_FN, FN_SD0_CD,
GP_11_10_FN, FN_SD0_DAT3,
GP_11_9_FN, FN_SD0_DAT2,
GP_11_8_FN, FN_SD0_DAT1,
GP_11_7_FN, FN_SD0_DAT0,
GP_11_6_FN, FN_SD0_CMD,
GP_11_5_FN, FN_SD0_CLK,
GP_11_4_FN, FN_IP7_7,
GP_11_3_FN, FN_IP7_6,
GP_11_2_FN, FN_IP7_5_4,
GP_11_1_FN, FN_IP7_3_2,
GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
GROUP(-8,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31_24 [8] RESERVED */
/* IP0_23 [1] */
FN_DU0_DB7_C5, 0,
/* IP0_22 [1] */
FN_DU0_DB6_C4, 0,
/* IP0_21 [1] */
FN_DU0_DB5_C3, 0,
/* IP0_20 [1] */
FN_DU0_DB4_C2, 0,
/* IP0_19 [1] */
FN_DU0_DB3_C1, 0,
/* IP0_18 [1] */
FN_DU0_DB2_C0, 0,
/* IP0_17 [1] */
FN_DU0_DB1, 0,
/* IP0_16 [1] */
FN_DU0_DB0, 0,
/* IP0_15 [1] */
FN_DU0_DG7_Y3_DATA15, 0,
/* IP0_14 [1] */
FN_DU0_DG6_Y2_DATA14, 0,
/* IP0_13 [1] */
FN_DU0_DG5_Y1_DATA13, 0,
/* IP0_12 [1] */
FN_DU0_DG4_Y0_DATA12, 0,
/* IP0_11 [1] */
FN_DU0_DG3_C7_DATA11, 0,
/* IP0_10 [1] */
FN_DU0_DG2_C6_DATA10, 0,
/* IP0_9 [1] */
FN_DU0_DG1_DATA9, 0,
/* IP0_8 [1] */
FN_DU0_DG0_DATA8, 0,
/* IP0_7 [1] */
FN_DU0_DR7_Y9_DATA7, 0,
/* IP0_6 [1] */
FN_DU0_DR6_Y8_DATA6, 0,
/* IP0_5 [1] */
FN_DU0_DR5_Y7_DATA5, 0,
/* IP0_4 [1] */
FN_DU0_DR4_Y6_DATA4, 0,
/* IP0_3 [1] */
FN_DU0_DR3_Y5_DATA3, 0,
/* IP0_2 [1] */
FN_DU0_DR2_Y4_DATA2, 0,
/* IP0_1 [1] */
FN_DU0_DR1_DATA1, 0,
/* IP0_0 [1] */
FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP1_31_23 [9] RESERVED */
/* IP1_22 [1] */
FN_A25, FN_SSL,
/* IP1_21 [1] */
FN_A24, FN_SPCLK,
/* IP1_20 [1] */
FN_A23, FN_IO3,
/* IP1_19 [1] */
FN_A22, FN_IO2,
/* IP1_18 [1] */
FN_A21, FN_MISO_IO1,
/* IP1_17 [1] */
FN_A20, FN_MOSI_IO0,
/* IP1_16 [1] */
FN_DU1_DG7_Y3_DATA11, 0,
/* IP1_15 [1] */
FN_DU1_DG6_Y2_DATA10, 0,
/* IP1_14 [1] */
FN_DU1_DG5_Y1_DATA9, 0,
/* IP1_13 [1] */
FN_DU1_DG4_Y0_DATA8, 0,
/* IP1_12 [1] */
FN_DU1_DG3_C7_DATA7, 0,
/* IP1_11 [1] */
FN_DU1_DG2_C6_DATA6, 0,
/* IP1_10 [1] */
FN_DU1_DR7_DATA5, 0,
/* IP1_9 [1] */
FN_DU1_DR6_DATA4, 0,
/* IP1_8 [1] */
FN_DU1_DR5_Y7_DATA3, 0,
/* IP1_7 [1] */
FN_DU1_DR4_Y6_DATA2, 0,
/* IP1_6 [1] */
FN_DU1_DR3_Y5_DATA1, 0,
/* IP1_5 [1] */
FN_DU1_DR2_Y4_DATA0, 0,
/* IP1_4 [1] */
FN_DU0_CDE, 0,
/* IP1_3 [1] */
FN_DU0_DISP, 0,
/* IP1_2 [1] */
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
/* IP1_1 [1] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0,
/* IP1_0 [1] */
FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
GROUP(-15, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP2_31_17 [15] RESERVED */
/* IP2_16 [1] */
FN_VI2_FIELD, FN_AVB_TXD2,
/* IP2_15 [1] */
FN_VI2_D11_Y3, FN_AVB_TXD1,
/* IP2_14 [1] */
FN_VI2_D10_Y2, FN_AVB_TXD0,
/* IP2_13 [1] */
FN_VI2_D9_Y1, FN_AVB_TX_EN,
/* IP2_12 [1] */
FN_VI2_D8_Y0, FN_AVB_TXD3,
/* IP2_11 [1] */
FN_VI2_D7_C7, FN_AVB_COL,
/* IP2_10 [1] */
FN_VI2_D6_C6, FN_AVB_RX_ER,
/* IP2_9 [1] */
FN_VI2_D5_C5, FN_AVB_RXD7,
/* IP2_8 [1] */
FN_VI2_D4_C4, FN_AVB_RXD6,
/* IP2_7 [1] */
FN_VI2_D3_C3, FN_AVB_RXD5,
/* IP2_6 [1] */
FN_VI2_D2_C2, FN_AVB_RXD4,
/* IP2_5 [1] */
FN_VI2_D1_C1, FN_AVB_RXD3,
/* IP2_4 [1] */
FN_VI2_D0_C0, FN_AVB_RXD2,
/* IP2_3 [1] */
FN_VI2_VSYNC_N, FN_AVB_RXD1,
/* IP2_2 [1] */
FN_VI2_HSYNC_N, FN_AVB_RXD0,
/* IP2_1 [1] */
FN_VI2_CLKENB, FN_AVB_RX_DV,
/* IP2_0 [1] */
FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP3_31_15 [17] RESERVED */
/* IP3_14 [1] */
FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
/* IP3_13 [1] */
FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
/* IP3_12 [1] */
FN_VI3_D8_Y0, FN_AVB_CRS,
/* IP3_11 [1] */
FN_VI3_D7_C7, FN_AVB_PHY_INT,
/* IP3_10 [1] */
FN_VI3_D6_C6, FN_AVB_MAGIC,
/* IP3_9 [1] */
FN_VI3_D5_C5, FN_AVB_LINK,
/* IP3_8 [1] */
FN_VI3_D4_C4, FN_AVB_MDIO,
/* IP3_7 [1] */
FN_VI3_D3_C3, FN_AVB_MDC,
/* IP3_6 [1] */
FN_VI3_D2_C2, FN_AVB_GTX_CLK,
/* IP3_5 [1] */
FN_VI3_D1_C1, FN_AVB_TX_ER,
/* IP3_4 [1] */
FN_VI3_D0_C0, FN_AVB_TXD7,
/* IP3_3 [1] */
FN_VI3_VSYNC_N, FN_AVB_TXD6,
/* IP3_2 [1] */
FN_VI3_HSYNC_N, FN_AVB_TXD5,
/* IP3_1 [1] */
FN_VI3_CLKENB, FN_AVB_TXD4,
/* IP3_0 [1] */
FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
GROUP(-7, 1, 1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1),
GROUP(
/* IP4_31_25 [7] RESERVED */
/* IP4_24 [1] */
FN_VI4_FIELD, FN_VI3_D15_Y7,
/* IP4_23 [1] */
FN_VI4_D11_Y3, FN_VI3_D14_Y6,
/* IP4_22 [1] */
FN_VI4_D10_Y2, FN_VI3_D13_Y5,
/* IP4_21 [1] */
FN_VI4_D9_Y1, FN_VI3_D12_Y4,
/* IP4_20_19 [2] */
FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
/* IP4_18_17 [2] */
FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
/* IP4_16_15 [2] */
FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
/* IP4_14_13 [2] */
FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
/* IP4_12_11 [2] */
FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
/* IP4_10_9 [2] */
FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
/* IP4_8_7 [2] */
FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
/* IP4_6_5 [2] */
FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
/* IP4_4 [1] */
FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
/* IP4_3_2 [2] */
FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
/* IP4_1 [1] */
FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
/* IP4_0 [1] */
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
GROUP(-20, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP5_31_12 [20] RESERVED */
/* IP5_11 [1] */
FN_VI5_D8_Y0, FN_VI1_D23_R7,
/* IP5_10 [1] */
FN_VI5_D7_C7, FN_VI1_D22_R6,
/* IP5_9 [1] */
FN_VI5_D6_C6, FN_VI1_D21_R5,
/* IP5_8 [1] */
FN_VI5_D5_C5, FN_VI1_D20_R4,
/* IP5_7 [1] */
FN_VI5_D4_C4, FN_VI1_D19_R3,
/* IP5_6 [1] */
FN_VI5_D3_C3, FN_VI1_D18_R2,
/* IP5_5 [1] */
FN_VI5_D2_C2, FN_VI1_D17_R1,
/* IP5_4 [1] */
FN_VI5_D1_C1, FN_VI1_D16_R0,
/* IP5_3 [1] */
FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
/* IP5_2 [1] */
FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
/* IP5_1 [1] */
FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
/* IP5_0 [1] */
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
GROUP(-13, 2, 1, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP6_31_19 [13] RESERVED */
/* IP6_18_17 [2] */
FN_DREQ1_N, FN_RX3, 0, 0,
/* IP6_16 [1] */
FN_TX3, 0,
/* IP6_15_14 [2] */
FN_DACK1, FN_SCK3, 0, 0,
/* IP6_13_12 [2] */
FN_DREQ0_N, FN_RX2, 0, 0,
/* IP6_11_10 [2] */
FN_DACK0, FN_TX2, 0, 0,
/* IP6_9_8 [2] */
FN_DRACK0, FN_SCK2, 0, 0,
/* IP6_7 [1] */
FN_MSIOF1_RXD, FN_HRX1,
/* IP6_6 [1] */
FN_MSIOF1_TXD, FN_HTX1,
/* IP6_5 [1] */
FN_MSIOF1_SYNC, FN_HRTS1_N,
/* IP6_4 [1] */
FN_MSIOF1_SCK, FN_HSCK1,
/* IP6_3 [1] */
FN_MSIOF0_RXD, FN_HRX0,
/* IP6_2 [1] */
FN_MSIOF0_TXD, FN_HTX0,
/* IP6_1 [1] */
FN_MSIOF0_SYNC, FN_HCTS0_N,
/* IP6_0 [1] */
FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
GROUP(-11, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2),
GROUP(
/* IP7_31_21 [11] RESERVED */
/* IP7_20 [1] */
FN_AUDIO_CLKB, 0,
/* IP7_19 [1] */
FN_AUDIO_CLKA, 0,
/* IP7_18 [1] */
FN_AUDIO_CLKOUT, 0,
/* IP7_17 [1] */
FN_SSI_SDATA4, 0,
/* IP7_16 [1] */
FN_SSI_WS4, 0,
/* IP7_15_14 [2] */
FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
/* IP7_13_12 [2] */
FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
/* IP7_11_10 [2] */
FN_SSI_WS34, FN_TPU0TO1, 0, 0,
/* IP7_9_8 [2] */
FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
/* IP7_7 [1] */
FN_PWM4, 0,
/* IP7_6 [1] */
FN_PWM3, 0,
/* IP7_5_4 [2] */
FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
/* IP7_3_2 [2] */
FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
{ /* sentinel */ }
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
[ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
[ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
[ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
[ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
[ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
[ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
[ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
[ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
[ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
[10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
[11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
[12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
[13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
[14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
[15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
[16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
[17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
[18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
[19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
[20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
[21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
[22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
[23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
[24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
[25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
[26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
[27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
[28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
[ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */
[ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */
[ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */
[ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */
[ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */
[ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */
[ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */
[ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */
[ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */
[10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */
[11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */
[12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */
[13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */
[14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */
[15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */
[16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */
[17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */
[18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */
[19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */
[20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
[21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */
[22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 0), /* D0 */
[ 1] = RCAR_GP_PIN(2, 1), /* D1 */
[ 2] = RCAR_GP_PIN(2, 2), /* D2 */
[ 3] = RCAR_GP_PIN(2, 3), /* D3 */
[ 4] = RCAR_GP_PIN(2, 4), /* D4 */
[ 5] = RCAR_GP_PIN(2, 5), /* D5 */
[ 6] = RCAR_GP_PIN(2, 6), /* D6 */
[ 7] = RCAR_GP_PIN(2, 7), /* D7 */
[ 8] = RCAR_GP_PIN(2, 8), /* D8 */
[ 9] = RCAR_GP_PIN(2, 9), /* D9 */
[10] = RCAR_GP_PIN(2, 10), /* D10 */
[11] = RCAR_GP_PIN(2, 11), /* D11 */
[12] = RCAR_GP_PIN(2, 12), /* D12 */
[13] = RCAR_GP_PIN(2, 13), /* D13 */
[14] = RCAR_GP_PIN(2, 14), /* D14 */
[15] = RCAR_GP_PIN(2, 15), /* D15 */
[16] = RCAR_GP_PIN(2, 16), /* A0 */
[17] = RCAR_GP_PIN(2, 17), /* A1 */
[18] = RCAR_GP_PIN(2, 18), /* A2 */
[19] = RCAR_GP_PIN(2, 19), /* A3 */
[20] = RCAR_GP_PIN(2, 20), /* A4 */
[21] = RCAR_GP_PIN(2, 21), /* A5 */
[22] = RCAR_GP_PIN(2, 22), /* A6 */
[23] = RCAR_GP_PIN(2, 23), /* A7 */
[24] = RCAR_GP_PIN(2, 24), /* A8 */
[25] = RCAR_GP_PIN(2, 25), /* A9 */
[26] = RCAR_GP_PIN(2, 26), /* A10 */
[27] = RCAR_GP_PIN(2, 27), /* A11 */
[28] = RCAR_GP_PIN(2, 28), /* A12 */
[29] = RCAR_GP_PIN(2, 29), /* A13 */
[30] = RCAR_GP_PIN(2, 30), /* A14 */
[31] = RCAR_GP_PIN(2, 31), /* A15 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 0), /* A16 */
[ 1] = RCAR_GP_PIN(3, 1), /* A17 */
[ 2] = RCAR_GP_PIN(3, 2), /* A18 */
[ 3] = RCAR_GP_PIN(3, 3), /* A19 */
[ 4] = RCAR_GP_PIN(3, 4), /* A20 */
[ 5] = RCAR_GP_PIN(3, 5), /* A21 */
[ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */
[ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */
[ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */
[ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */
[10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */
[11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */
[12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */
[13] = RCAR_GP_PIN(3, 13), /* BS# */
[14] = RCAR_GP_PIN(3, 14), /* RD# */
[15] = RCAR_GP_PIN(3, 15), /* RD/WR# */
[16] = RCAR_GP_PIN(3, 16), /* WE0# */
[17] = RCAR_GP_PIN(3, 17), /* WE1# */
[18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */
[19] = RCAR_GP_PIN(3, 19), /* IRQ0 */
[20] = RCAR_GP_PIN(3, 20), /* IRQ1 */
[21] = RCAR_GP_PIN(3, 21), /* IRQ2 */
[22] = RCAR_GP_PIN(3, 22), /* IRQ3 */
[23] = RCAR_GP_PIN(3, 23), /* A22 */
[24] = RCAR_GP_PIN(3, 24), /* A23 */
[25] = RCAR_GP_PIN(3, 25), /* A24 */
[26] = RCAR_GP_PIN(3, 26), /* A25 */
[27] = RCAR_GP_PIN(3, 27), /* CS0# */
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
[ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
[ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */
[ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */
[ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */
[ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */
[ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */
[ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */
[ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */
[ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */
[10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */
[11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */
[12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */
[13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */
[14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */
[15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */
[16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
[ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */
[ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */
[ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */
[ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */
[ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */
[ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */
[ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */
[ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */
[ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */
[10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */
[11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */
[12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */
[13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */
[14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */
[15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */
[16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
[ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
[ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */
[ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */
[ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */
[ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */
[ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */
[ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */
[ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */
[ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */
[ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */
[10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */
[11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */
[12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */
[13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */
[14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */
[15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */
[16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
[ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */
[ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */
[ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */
[ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */
[ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */
[ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */
[ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */
[ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */
[ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */
[10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */
[11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */
[12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */
[13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */
[14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */
[15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */
[16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
[ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
[ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */
[ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */
[ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */
[ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */
[ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */
[ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */
[ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */
[ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */
[ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */
[10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */
[11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */
[12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */
[13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */
[14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */
[15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */
[16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
[ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
[ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */
[ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */
[ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */
[ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */
[ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */
[ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */
[ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */
[ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */
[ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */
[10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */
[11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */
[12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */
[13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */
[14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */
[15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */
[16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
[ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
[ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */
[ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */
[ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */
[ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */
[ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */
[ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */
[ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */
[ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */
[ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */
[10] = RCAR_GP_PIN(10, 10), /* SCK0 */
[11] = RCAR_GP_PIN(10, 11), /* CTS0# */
[12] = RCAR_GP_PIN(10, 12), /* RTS0# */
[13] = RCAR_GP_PIN(10, 13), /* TX0 */
[14] = RCAR_GP_PIN(10, 14), /* RX0 */
[15] = RCAR_GP_PIN(10, 15), /* SCK1 */
[16] = RCAR_GP_PIN(10, 16), /* CTS1# */
[17] = RCAR_GP_PIN(10, 17), /* RTS1# */
[18] = RCAR_GP_PIN(10, 18), /* TX1 */
[19] = RCAR_GP_PIN(10, 19), /* RX1 */
[20] = RCAR_GP_PIN(10, 20), /* SCK2 */
[21] = RCAR_GP_PIN(10, 21), /* TX2 */
[22] = RCAR_GP_PIN(10, 22), /* RX2 */
[23] = RCAR_GP_PIN(10, 23), /* SCK3 */
[24] = RCAR_GP_PIN(10, 24), /* TX3 */
[25] = RCAR_GP_PIN(10, 25), /* RX3 */
[26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */
[27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */
[28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */
[29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */
[30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */
[31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */
} },
{ PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
[ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */
[ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */
[ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */
[ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */
[ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */
[ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */
[ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */
[ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */
[ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */
[10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */
[11] = RCAR_GP_PIN(11, 11), /* SD0_CD */
[12] = RCAR_GP_PIN(11, 12), /* SD0_WP */
[13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */
[14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */
[15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */
[16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */
[17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */
[18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */
[19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */
[20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */
[21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */
[22] = RCAR_GP_PIN(11, 22), /* ADICLK */
[23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */
[24] = RCAR_GP_PIN(11, 24), /* ADIDATA */
[25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */
[26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */
[27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */
[28] = RCAR_GP_PIN(11, 28), /* AVS1 */
[29] = RCAR_GP_PIN(11, 29), /* AVS2 */
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
/* PUPR12 pull-up pins */
[ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
[ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */
[ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */
[ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
/* PUPR12 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = PIN_EDBGREQ, /* EDBGREQ */
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7792_pfc_ops = {
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7792_pinmux_info = {
.name = "r8a77920_pfc",
.ops = &r8a7792_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a7792.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* SH7786 Pinmux
*
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
* Kuninori Morimoto <[email protected]>
*
* Based on SH7785 pinmux
*
* Copyright (C) 2008 Magnus Damm
*/
#include <linux/kernel.h>
#include <cpu/sh7786.h>
#include "sh_pfc.h"
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
PE7_DATA, PE6_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
PG7_DATA, PG6_DATA, PG5_DATA,
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA,
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
PE7_IN, PE6_IN,
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
PG7_IN, PG6_IN, PG5_IN,
PH7_IN, PH6_IN, PH5_IN, PH4_IN,
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
PJ3_IN, PJ2_IN, PJ1_IN,
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
PE7_OUT, PE6_OUT,
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
PG7_OUT, PG6_OUT, PG5_OUT,
PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
PJ3_OUT, PJ2_OUT, PJ1_OUT,
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
PE7_FN, PE6_FN,
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
PG7_FN, PG6_FN, PG5_FN,
PH7_FN, PH6_FN, PH5_FN, PH4_FN,
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
PJ3_FN, PJ2_FN, PJ1_FN,
P1MSEL14_0, P1MSEL14_1,
P1MSEL13_0, P1MSEL13_1,
P1MSEL12_0, P1MSEL12_1,
P1MSEL11_0, P1MSEL11_1,
P1MSEL10_0, P1MSEL10_1,
P1MSEL9_0, P1MSEL9_1,
P1MSEL8_0, P1MSEL8_1,
P1MSEL7_0, P1MSEL7_1,
P1MSEL6_0, P1MSEL6_1,
P1MSEL5_0, P1MSEL5_1,
P1MSEL4_0, P1MSEL4_1,
P1MSEL3_0, P1MSEL3_1,
P1MSEL2_0, P1MSEL2_1,
P1MSEL1_0, P1MSEL1_1,
P1MSEL0_0, P1MSEL0_1,
P2MSEL15_0, P2MSEL15_1,
P2MSEL14_0, P2MSEL14_1,
P2MSEL13_0, P2MSEL13_1,
P2MSEL12_0, P2MSEL12_1,
P2MSEL11_0, P2MSEL11_1,
P2MSEL10_0, P2MSEL10_1,
P2MSEL9_0, P2MSEL9_1,
P2MSEL8_0, P2MSEL8_1,
P2MSEL7_0, P2MSEL7_1,
P2MSEL6_0, P2MSEL6_1,
P2MSEL5_0, P2MSEL5_1,
P2MSEL4_0, P2MSEL4_1,
P2MSEL3_0, P2MSEL3_1,
P2MSEL2_0, P2MSEL2_1,
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
SCIF0_CTS_MARK, SCIF0_RTS_MARK,
SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
FALE_MARK, FRB_MARK, FSTATUS_MARK,
FSE_MARK, FCLE_MARK,
DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
USB_OVC1_MARK, USB_OVC0_MARK,
USB_PENC1_MARK, USB_PENC0_MARK,
HAC_RES_MARK,
HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
TCLK_MARK,
IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
PINMUX_MARK_END,
};
static const u16 pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
/* PB GPIO */
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
/* PC GPIO */
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
/* PD GPIO */
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
/* PE GPIO */
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
/* PF GPIO */
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
/* PG GPIO */
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
/* PH GPIO */
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
/* PJ GPIO */
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
/* PA FN */
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
/* PB FN */
PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
/* PC FN */
PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
/* PD FN */
PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN),
PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
/* PE FN */
PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
/* PF FN */
PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
/* PG FN */
PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
/* PH FN */
PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
/* PJ FN */
PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
};
static const struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
/* PF */
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* PG */
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
/* PH */
PINMUX_GPIO(PH7),
PINMUX_GPIO(PH6),
PINMUX_GPIO(PH5),
PINMUX_GPIO(PH4),
PINMUX_GPIO(PH3),
PINMUX_GPIO(PH2),
PINMUX_GPIO(PH1),
PINMUX_GPIO(PH0),
/* PJ */
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(CDE),
GPIO_FN(ETH_MAGIC),
GPIO_FN(DISP),
GPIO_FN(ETH_LINK),
GPIO_FN(DR5),
GPIO_FN(ETH_TX_ER),
GPIO_FN(DR4),
GPIO_FN(ETH_TX_EN),
GPIO_FN(DR3),
GPIO_FN(ETH_TXD3),
GPIO_FN(DR2),
GPIO_FN(ETH_TXD2),
GPIO_FN(DR1),
GPIO_FN(ETH_TXD1),
GPIO_FN(DR0),
GPIO_FN(ETH_TXD0),
GPIO_FN(VSYNC),
GPIO_FN(HSPI_CLK),
GPIO_FN(ODDF),
GPIO_FN(HSPI_CS),
GPIO_FN(DG5),
GPIO_FN(ETH_MDIO),
GPIO_FN(DG4),
GPIO_FN(ETH_RX_CLK),
GPIO_FN(DG3),
GPIO_FN(ETH_MDC),
GPIO_FN(DG2),
GPIO_FN(ETH_COL),
GPIO_FN(DG1),
GPIO_FN(ETH_TX_CLK),
GPIO_FN(DG0),
GPIO_FN(ETH_CRS),
GPIO_FN(DCLKIN),
GPIO_FN(HSPI_RX),
GPIO_FN(HSYNC),
GPIO_FN(HSPI_TX),
GPIO_FN(DB5),
GPIO_FN(ETH_RXD3),
GPIO_FN(DB4),
GPIO_FN(ETH_RXD2),
GPIO_FN(DB3),
GPIO_FN(ETH_RXD1),
GPIO_FN(DB2),
GPIO_FN(ETH_RXD0),
GPIO_FN(DB1),
GPIO_FN(ETH_RX_DV),
GPIO_FN(DB0),
GPIO_FN(ETH_RX_ER),
GPIO_FN(DCLKOUT),
GPIO_FN(SCIF1_SCK),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_TXD),
GPIO_FN(DACK1),
GPIO_FN(BACK),
GPIO_FN(FALE),
GPIO_FN(DACK0),
GPIO_FN(FCLE),
GPIO_FN(DREQ1),
GPIO_FN(BREQ),
GPIO_FN(USB_OVC1),
GPIO_FN(DREQ0),
GPIO_FN(USB_OVC0),
GPIO_FN(USB_PENC1),
GPIO_FN(USB_PENC0),
GPIO_FN(HAC1_SDOUT),
GPIO_FN(SSI1_SDATA),
GPIO_FN(SDIF1CMD),
GPIO_FN(HAC1_SDIN),
GPIO_FN(SSI1_SCK),
GPIO_FN(SDIF1CD),
GPIO_FN(HAC1_SYNC),
GPIO_FN(SSI1_WS),
GPIO_FN(SDIF1WP),
GPIO_FN(HAC1_BITCLK),
GPIO_FN(SSI1_CLK),
GPIO_FN(SDIF1CLK),
GPIO_FN(HAC0_SDOUT),
GPIO_FN(SSI0_SDATA),
GPIO_FN(SDIF1D3),
GPIO_FN(HAC0_SDIN),
GPIO_FN(SSI0_SCK),
GPIO_FN(SDIF1D2),
GPIO_FN(HAC0_SYNC),
GPIO_FN(SSI0_WS),
GPIO_FN(SDIF1D1),
GPIO_FN(HAC0_BITCLK),
GPIO_FN(SSI0_CLK),
GPIO_FN(SDIF1D0),
GPIO_FN(SCIF3_SCK),
GPIO_FN(SSI2_SDATA),
GPIO_FN(SCIF3_RXD),
GPIO_FN(TCLK),
GPIO_FN(SSI2_SCK),
GPIO_FN(SCIF3_TXD),
GPIO_FN(HAC_RES),
GPIO_FN(SSI2_WS),
GPIO_FN(DACK3),
GPIO_FN(SDIF0CMD),
GPIO_FN(DACK2),
GPIO_FN(SDIF0CD),
GPIO_FN(DREQ3),
GPIO_FN(SDIF0WP),
GPIO_FN(SCIF0_CTS),
GPIO_FN(DREQ2),
GPIO_FN(SDIF0CLK),
GPIO_FN(SCIF0_RTS),
GPIO_FN(IRL7),
GPIO_FN(SDIF0D3),
GPIO_FN(SCIF0_SCK),
GPIO_FN(IRL6),
GPIO_FN(SDIF0D2),
GPIO_FN(SCIF0_RXD),
GPIO_FN(IRL5),
GPIO_FN(SDIF0D1),
GPIO_FN(SCIF0_TXD),
GPIO_FN(IRL4),
GPIO_FN(SDIF0D0),
GPIO_FN(SCIF5_SCK),
GPIO_FN(FRB),
GPIO_FN(SCIF5_RXD),
GPIO_FN(IOIS16),
GPIO_FN(SCIF5_TXD),
GPIO_FN(CE2B),
GPIO_FN(DRAK3),
GPIO_FN(CE2A),
GPIO_FN(SCIF4_SCK),
GPIO_FN(DRAK2),
GPIO_FN(SSI3_WS),
GPIO_FN(SCIF4_RXD),
GPIO_FN(DRAK1),
GPIO_FN(SSI3_SDATA),
GPIO_FN(FSTATUS),
GPIO_FN(SCIF4_TXD),
GPIO_FN(DRAK0),
GPIO_FN(SSI3_SCK),
GPIO_FN(FSE),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
PA4_FN, PA4_OUT, PA4_IN, 0,
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 ))
},
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
PB4_FN, PB4_OUT, PB4_IN, 0,
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0 ))
},
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
PC4_FN, PC4_OUT, PC4_IN, 0,
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0 ))
},
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
PD4_FN, PD4_OUT, PD4_IN, 0,
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 ))
},
{ PINMUX_CFG_REG_VAR("PECR", 0xffcc0008, 16,
GROUP(2, 2, -12),
GROUP(
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
/* RESERVED [12] */ ))
},
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
PF4_FN, PF4_OUT, PF4_IN, 0,
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 ))
},
{ PINMUX_CFG_REG_VAR("PGCR", 0xffcc000c, 16,
GROUP(2, 2, 2, -10),
GROUP(
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
/* RESERVED [10] */ ))
},
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
PH7_FN, PH7_OUT, PH7_IN, 0,
PH6_FN, PH6_OUT, PH6_IN, 0,
PH5_FN, PH5_OUT, PH5_IN, 0,
PH4_FN, PH4_OUT, PH4_IN, 0,
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0 ))
},
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
PJ4_FN, PJ4_OUT, PJ4_IN, 0,
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
0, 0,
P1MSEL14_0, P1MSEL14_1,
P1MSEL13_0, P1MSEL13_1,
P1MSEL12_0, P1MSEL12_1,
P1MSEL11_0, P1MSEL11_1,
P1MSEL10_0, P1MSEL10_1,
P1MSEL9_0, P1MSEL9_1,
P1MSEL8_0, P1MSEL8_1,
P1MSEL7_0, P1MSEL7_1,
P1MSEL6_0, P1MSEL6_1,
P1MSEL5_0, P1MSEL5_1,
P1MSEL4_0, P1MSEL4_1,
P1MSEL3_0, P1MSEL3_1,
P1MSEL2_0, P1MSEL2_1,
P1MSEL1_0, P1MSEL1_1,
P1MSEL0_0, P1MSEL0_1 ))
},
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
P2MSEL15_0, P2MSEL15_1,
P2MSEL14_0, P2MSEL14_1,
P2MSEL13_0, P2MSEL13_1,
P2MSEL12_0, P2MSEL12_1,
P2MSEL11_0, P2MSEL11_1,
P2MSEL10_0, P2MSEL10_1,
P2MSEL9_0, P2MSEL9_1,
P2MSEL8_0, P2MSEL8_1,
P2MSEL7_0, P2MSEL7_1,
P2MSEL6_0, P2MSEL6_1,
P2MSEL5_0, P2MSEL5_1,
P2MSEL4_0, P2MSEL4_1,
P2MSEL3_0, P2MSEL3_1,
P2MSEL2_0, P2MSEL2_1,
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 ))
},
{ /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
PE7_DATA, PE6_DATA,
0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
PG7_DATA, PG6_DATA, PG5_DATA, 0,
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
},
{ /* sentinel */ }
};
const struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-sh7786.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
*
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
*/
/* GPSR0 */
#define GPSR0_15 F_(D15, IP7_11_8)
#define GPSR0_14 F_(D14, IP7_7_4)
#define GPSR0_13 F_(D13, IP7_3_0)
#define GPSR0_12 F_(D12, IP6_31_28)
#define GPSR0_11 F_(D11, IP6_27_24)
#define GPSR0_10 F_(D10, IP6_23_20)
#define GPSR0_9 F_(D9, IP6_19_16)
#define GPSR0_8 F_(D8, IP6_15_12)
#define GPSR0_7 F_(D7, IP6_11_8)
#define GPSR0_6 F_(D6, IP6_7_4)
#define GPSR0_5 F_(D5, IP6_3_0)
#define GPSR0_4 F_(D4, IP5_31_28)
#define GPSR0_3 F_(D3, IP5_27_24)
#define GPSR0_2 F_(D2, IP5_23_20)
#define GPSR0_1 F_(D1, IP5_19_16)
#define GPSR0_0 F_(D0, IP5_15_12)
/* GPSR1 */
#define GPSR1_28 FM(CLKOUT)
#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
#define GPSR1_26 F_(WE1_N, IP5_7_4)
#define GPSR1_25 F_(WE0_N, IP5_3_0)
#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
#define GPSR1_23 F_(RD_N, IP4_27_24)
#define GPSR1_22 F_(BS_N, IP4_23_20)
#define GPSR1_21 F_(CS1_N, IP4_19_16)
#define GPSR1_20 F_(CS0_N, IP4_15_12)
#define GPSR1_19 F_(A19, IP4_11_8)
#define GPSR1_18 F_(A18, IP4_7_4)
#define GPSR1_17 F_(A17, IP4_3_0)
#define GPSR1_16 F_(A16, IP3_31_28)
#define GPSR1_15 F_(A15, IP3_27_24)
#define GPSR1_14 F_(A14, IP3_23_20)
#define GPSR1_13 F_(A13, IP3_19_16)
#define GPSR1_12 F_(A12, IP3_15_12)
#define GPSR1_11 F_(A11, IP3_11_8)
#define GPSR1_10 F_(A10, IP3_7_4)
#define GPSR1_9 F_(A9, IP3_3_0)
#define GPSR1_8 F_(A8, IP2_31_28)
#define GPSR1_7 F_(A7, IP2_27_24)
#define GPSR1_6 F_(A6, IP2_23_20)
#define GPSR1_5 F_(A5, IP2_19_16)
#define GPSR1_4 F_(A4, IP2_15_12)
#define GPSR1_3 F_(A3, IP2_11_8)
#define GPSR1_2 F_(A2, IP2_7_4)
#define GPSR1_1 F_(A1, IP2_3_0)
#define GPSR1_0 F_(A0, IP1_31_28)
/* GPSR2 */
#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
#define GPSR2_8 F_(PWM2_A, IP1_27_24)
#define GPSR2_7 F_(PWM1_A, IP1_23_20)
#define GPSR2_6 F_(PWM0, IP1_19_16)
#define GPSR2_5 F_(IRQ5, IP1_15_12)
#define GPSR2_4 F_(IRQ4, IP1_11_8)
#define GPSR2_3 F_(IRQ3, IP1_7_4)
#define GPSR2_2 F_(IRQ2, IP1_3_0)
#define GPSR2_1 F_(IRQ1, IP0_31_28)
#define GPSR2_0 F_(IRQ0, IP0_27_24)
/* GPSR3 */
#define GPSR3_15 F_(SD1_WP, IP11_23_20)
#define GPSR3_14 F_(SD1_CD, IP11_19_16)
#define GPSR3_13 F_(SD0_WP, IP11_15_12)
#define GPSR3_12 F_(SD0_CD, IP11_11_8)
#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
/* GPSR4 */
#define GPSR4_17 F_(SD3_DS, IP11_7_4)
#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
#define GPSR4_6 F_(SD2_DS, IP9_27_24)
#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
/* GPSR5 */
#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
#define GPSR5_22 FM(MSIOF0_RXD)
#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
#define GPSR5_20 FM(MSIOF0_TXD)
#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
#define GPSR5_17 FM(MSIOF0_SCK)
#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
#define GPSR5_14 F_(HTX0, IP13_19_16)
#define GPSR5_13 F_(HRX0, IP13_15_12)
#define GPSR5_12 F_(HSCK0, IP13_11_8)
#define GPSR5_11 F_(RX2_A, IP13_7_4)
#define GPSR5_10 F_(TX2_A, IP13_3_0)
#define GPSR5_9 F_(SCK2, IP12_31_28)
#define GPSR5_8 F_(RTS1_N, IP12_27_24)
#define GPSR5_7 F_(CTS1_N, IP12_23_20)
#define GPSR5_6 F_(TX1_A, IP12_19_16)
#define GPSR5_5 F_(RX1_A, IP12_15_12)
#define GPSR5_4 F_(RTS0_N, IP12_11_8)
#define GPSR5_3 F_(CTS0_N, IP12_7_4)
#define GPSR5_2 F_(TX0, IP12_3_0)
#define GPSR5_1 F_(RX0, IP11_31_28)
#define GPSR5_0 F_(SCK0, IP11_27_24)
/* GPSR6 */
#define GPSR6_31 F_(GP6_31, IP18_7_4)
#define GPSR6_30 F_(GP6_30, IP18_3_0)
#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
#define GPSR6_13 FM(SSI_SDATA5)
#define GPSR6_12 FM(SSI_WS5)
#define GPSR6_11 FM(SSI_SCK5)
#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
GPSR6_31 \
GPSR6_30 \
GPSR6_29 \
GPSR1_28 GPSR6_28 \
GPSR1_27 GPSR6_27 \
GPSR1_26 GPSR6_26 \
GPSR1_25 GPSR5_25 GPSR6_25 \
GPSR1_24 GPSR5_24 GPSR6_24 \
GPSR1_23 GPSR5_23 GPSR6_23 \
GPSR1_22 GPSR5_22 GPSR6_22 \
GPSR1_21 GPSR5_21 GPSR6_21 \
GPSR1_20 GPSR5_20 GPSR6_20 \
GPSR1_19 GPSR5_19 GPSR6_19 \
GPSR1_18 GPSR5_18 GPSR6_18 \
GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
#define PINMUX_IPSR \
\
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
\
FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
\
FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
\
FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
\
FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
\
MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
MOD_SEL2_30 \
MOD_SEL1_29_28_27 MOD_SEL2_29 \
MOD_SEL0_28_27 MOD_SEL2_28_27 \
MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
MOD_SEL0_23 MOD_SEL1_23_22_21 \
MOD_SEL0_22 MOD_SEL2_22 \
MOD_SEL0_21 MOD_SEL2_21 \
MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
MOD_SEL2_17 \
MOD_SEL0_16 MOD_SEL1_16 \
MOD_SEL1_15_14 \
MOD_SEL0_14_13 \
MOD_SEL1_13 \
MOD_SEL0_12 MOD_SEL1_12 \
MOD_SEL0_11 MOD_SEL1_11 \
MOD_SEL0_10 MOD_SEL1_10 \
MOD_SEL0_9_8 MOD_SEL1_9 \
MOD_SEL0_7_6 \
MOD_SEL1_6 \
MOD_SEL0_5 MOD_SEL1_5 \
MOD_SEL0_4_3 MOD_SEL1_4 \
MOD_SEL1_3 \
MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0 MOD_SEL2_0
/*
* These pins are not able to be muxed but have other properties
* that can be set, such as drive-strength or pull-up/pull-down enable.
*/
#define PINMUX_STATIC \
FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
FM(QSPI0_IO2) FM(QSPI0_IO3) \
FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
FM(QSPI1_IO2) FM(QSPI1_IO3) \
FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
FM(PRESETOUT) \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_SINGLE(SSI_SCK5),
PINMUX_SINGLE(SSI_SDATA5),
PINMUX_SINGLE(SSI_WS5),
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
/* IPSR2 */
PINMUX_IPSR_GPSR(IP2_3_0, A1),
PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
PINMUX_IPSR_GPSR(IP2_7_4, A2),
PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
PINMUX_IPSR_GPSR(IP2_11_8, A3),
PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
PINMUX_IPSR_GPSR(IP2_15_12, A4),
PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
PINMUX_IPSR_GPSR(IP2_19_16, A5),
PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
PINMUX_IPSR_GPSR(IP2_23_20, A6),
PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
PINMUX_IPSR_GPSR(IP2_27_24, A7),
PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
PINMUX_IPSR_GPSR(IP2_31_28, A8),
PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
PINMUX_IPSR_GPSR(IP3_7_4, A10),
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
PINMUX_IPSR_GPSR(IP3_11_8, A11),
PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
PINMUX_IPSR_GPSR(IP3_15_12, A12),
PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
PINMUX_IPSR_GPSR(IP3_19_16, A13),
PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
PINMUX_IPSR_GPSR(IP3_23_20, A14),
PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
PINMUX_IPSR_GPSR(IP3_27_24, A15),
PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
PINMUX_IPSR_GPSR(IP3_31_28, A16),
PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
/* IPSR4 */
PINMUX_IPSR_GPSR(IP4_3_0, A17),
PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
PINMUX_IPSR_GPSR(IP4_7_4, A18),
PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
PINMUX_IPSR_GPSR(IP4_11_8, A19),
PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
PINMUX_IPSR_GPSR(IP5_15_12, D0),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
PINMUX_IPSR_GPSR(IP5_19_16, D1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
PINMUX_IPSR_GPSR(IP5_23_20, D2),
PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
PINMUX_IPSR_GPSR(IP5_27_24, D3),
PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
PINMUX_IPSR_GPSR(IP5_31_28, D4),
PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_3_0, D5),
PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
PINMUX_IPSR_GPSR(IP6_7_4, D6),
PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
PINMUX_IPSR_GPSR(IP6_11_8, D7),
PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
PINMUX_IPSR_GPSR(IP6_15_12, D8),
PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
PINMUX_IPSR_GPSR(IP6_19_16, D9),
PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
PINMUX_IPSR_GPSR(IP6_23_20, D10),
PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
PINMUX_IPSR_GPSR(IP6_27_24, D11),
PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
PINMUX_IPSR_GPSR(IP6_31_28, D12),
PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_3_0, D13),
PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
PINMUX_IPSR_GPSR(IP7_7_4, D14),
PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
PINMUX_IPSR_GPSR(IP7_11_8, D15),
PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
/* IPSR8 */
PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
/* IPSR10 */
PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP11_31_28, RX0),
PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
/* IPSR12 */
PINMUX_IPSR_GPSR(IP12_3_0, TX0),
PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
/* IPSR13 */
PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
/* IPSR16 */
PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
* pin to the list without an associated function. The sh-pfc
* core will do the right thing and skip trying to mux the pin
* while still applying configuration to it.
*/
#define FM(x) PINMUX_DATA(x##_MARK, 0),
PINMUX_STATIC
#undef FM
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
static const unsigned int audio_clk_a_a_pins[] = {
/* CLK A */
RCAR_GP_PIN(6, 22),
};
static const unsigned int audio_clk_a_a_mux[] = {
AUDIO_CLKA_A_MARK,
};
static const unsigned int audio_clk_a_b_pins[] = {
/* CLK A */
RCAR_GP_PIN(5, 4),
};
static const unsigned int audio_clk_a_b_mux[] = {
AUDIO_CLKA_B_MARK,
};
static const unsigned int audio_clk_a_c_pins[] = {
/* CLK A */
RCAR_GP_PIN(5, 19),
};
static const unsigned int audio_clk_a_c_mux[] = {
AUDIO_CLKA_C_MARK,
};
static const unsigned int audio_clk_b_a_pins[] = {
/* CLK B */
RCAR_GP_PIN(5, 12),
};
static const unsigned int audio_clk_b_a_mux[] = {
AUDIO_CLKB_A_MARK,
};
static const unsigned int audio_clk_b_b_pins[] = {
/* CLK B */
RCAR_GP_PIN(6, 23),
};
static const unsigned int audio_clk_b_b_mux[] = {
AUDIO_CLKB_B_MARK,
};
static const unsigned int audio_clk_c_a_pins[] = {
/* CLK C */
RCAR_GP_PIN(5, 21),
};
static const unsigned int audio_clk_c_a_mux[] = {
AUDIO_CLKC_A_MARK,
};
static const unsigned int audio_clk_c_b_pins[] = {
/* CLK C */
RCAR_GP_PIN(5, 0),
};
static const unsigned int audio_clk_c_b_mux[] = {
AUDIO_CLKC_B_MARK,
};
static const unsigned int audio_clkout_a_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 18),
};
static const unsigned int audio_clkout_a_mux[] = {
AUDIO_CLKOUT_A_MARK,
};
static const unsigned int audio_clkout_b_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(6, 28),
};
static const unsigned int audio_clkout_b_mux[] = {
AUDIO_CLKOUT_B_MARK,
};
static const unsigned int audio_clkout_c_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 3),
};
static const unsigned int audio_clkout_c_mux[] = {
AUDIO_CLKOUT_C_MARK,
};
static const unsigned int audio_clkout_d_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 21),
};
static const unsigned int audio_clkout_d_mux[] = {
AUDIO_CLKOUT_D_MARK,
};
static const unsigned int audio_clkout1_a_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(5, 15),
};
static const unsigned int audio_clkout1_a_mux[] = {
AUDIO_CLKOUT1_A_MARK,
};
static const unsigned int audio_clkout1_b_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int audio_clkout1_b_mux[] = {
AUDIO_CLKOUT1_B_MARK,
};
static const unsigned int audio_clkout2_a_pins[] = {
/* CLKOUT2 */
RCAR_GP_PIN(5, 16),
};
static const unsigned int audio_clkout2_a_mux[] = {
AUDIO_CLKOUT2_A_MARK,
};
static const unsigned int audio_clkout2_b_pins[] = {
/* CLKOUT2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int audio_clkout2_b_mux[] = {
AUDIO_CLKOUT2_B_MARK,
};
static const unsigned int audio_clkout3_a_pins[] = {
/* CLKOUT3 */
RCAR_GP_PIN(5, 19),
};
static const unsigned int audio_clkout3_a_mux[] = {
AUDIO_CLKOUT3_A_MARK,
};
static const unsigned int audio_clkout3_b_pins[] = {
/* CLKOUT3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int audio_clkout3_b_mux[] = {
AUDIO_CLKOUT3_B_MARK,
};
/* - EtherAVB --------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
/* AVB_LINK */
RCAR_GP_PIN(2, 12),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
/* AVB_MAGIC_ */
RCAR_GP_PIN(2, 10),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
/* AVB_PHY_INT */
RCAR_GP_PIN(2, 11),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
/*
* AVB_TX_CTL, AVB_TXC, AVB_TD0,
* AVB_TD1, AVB_TD2, AVB_TD3,
* AVB_RX_CTL, AVB_RXC, AVB_RD0,
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
AVB_TXCREFCLK_MARK,
};
static const unsigned int avb_avtp_pps_pins[] = {
/* AVB_AVTP_PPS */
RCAR_GP_PIN(2, 6),
};
static const unsigned int avb_avtp_pps_mux[] = {
AVB_AVTP_PPS_MARK,
};
static const unsigned int avb_avtp_match_a_pins[] = {
/* AVB_AVTP_MATCH_A */
RCAR_GP_PIN(2, 13),
};
static const unsigned int avb_avtp_match_a_mux[] = {
AVB_AVTP_MATCH_A_MARK,
};
static const unsigned int avb_avtp_capture_a_pins[] = {
/* AVB_AVTP_CAPTURE_A */
RCAR_GP_PIN(2, 14),
};
static const unsigned int avb_avtp_capture_a_mux[] = {
AVB_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb_avtp_match_b_pins[] = {
/* AVB_AVTP_MATCH_B */
RCAR_GP_PIN(1, 8),
};
static const unsigned int avb_avtp_match_b_mux[] = {
AVB_AVTP_MATCH_B_MARK,
};
static const unsigned int avb_avtp_capture_b_pins[] = {
/* AVB_AVTP_CAPTURE_B */
RCAR_GP_PIN(1, 11),
};
static const unsigned int avb_avtp_capture_b_mux[] = {
AVB_AVTP_CAPTURE_B_MARK,
};
/* - CAN ------------------------------------------------------------------ */
static const unsigned int can0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int can0_data_a_mux[] = {
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int can1_data_mux[] = {
CAN1_TX_MARK, CAN1_RX_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 25),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - CAN FD --------------------------------------------------------------- */
static const unsigned int canfd0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int canfd0_data_a_mux[] = {
CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
};
static const unsigned int canfd0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int canfd0_data_b_mux[] = {
CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
};
static const unsigned int canfd1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif0_ctrl_a_mux[] = {
RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
};
static const unsigned int drif0_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif0_data0_a_mux[] = {
RIF0_D0_A_MARK,
};
static const unsigned int drif0_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif0_data1_a_mux[] = {
RIF0_D1_A_MARK,
};
static const unsigned int drif0_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int drif0_ctrl_b_mux[] = {
RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
};
static const unsigned int drif0_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 1),
};
static const unsigned int drif0_data0_b_mux[] = {
RIF0_D0_B_MARK,
};
static const unsigned int drif0_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 2),
};
static const unsigned int drif0_data1_b_mux[] = {
RIF0_D1_B_MARK,
};
static const unsigned int drif0_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
};
static const unsigned int drif0_ctrl_c_mux[] = {
RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
};
static const unsigned int drif0_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 13),
};
static const unsigned int drif0_data0_c_mux[] = {
RIF0_D0_C_MARK,
};
static const unsigned int drif0_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 14),
};
static const unsigned int drif0_data1_c_mux[] = {
RIF0_D1_C_MARK,
};
/* - DRIF1 --------------------------------------------------------------- */
static const unsigned int drif1_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif1_ctrl_a_mux[] = {
RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
};
static const unsigned int drif1_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif1_data0_a_mux[] = {
RIF1_D0_A_MARK,
};
static const unsigned int drif1_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif1_data1_a_mux[] = {
RIF1_D1_A_MARK,
};
static const unsigned int drif1_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
};
static const unsigned int drif1_ctrl_b_mux[] = {
RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
};
static const unsigned int drif1_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 7),
};
static const unsigned int drif1_data0_b_mux[] = {
RIF1_D0_B_MARK,
};
static const unsigned int drif1_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 8),
};
static const unsigned int drif1_data1_b_mux[] = {
RIF1_D1_B_MARK,
};
static const unsigned int drif1_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
};
static const unsigned int drif1_ctrl_c_mux[] = {
RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
};
static const unsigned int drif1_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 6),
};
static const unsigned int drif1_data0_c_mux[] = {
RIF1_D0_C_MARK,
};
static const unsigned int drif1_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 10),
};
static const unsigned int drif1_data1_c_mux[] = {
RIF1_D1_C_MARK,
};
/* - DRIF2 --------------------------------------------------------------- */
static const unsigned int drif2_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif2_ctrl_a_mux[] = {
RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
};
static const unsigned int drif2_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif2_data0_a_mux[] = {
RIF2_D0_A_MARK,
};
static const unsigned int drif2_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif2_data1_a_mux[] = {
RIF2_D1_A_MARK,
};
static const unsigned int drif2_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int drif2_ctrl_b_mux[] = {
RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
};
static const unsigned int drif2_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int drif2_data0_b_mux[] = {
RIF2_D0_B_MARK,
};
static const unsigned int drif2_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int drif2_data1_b_mux[] = {
RIF2_D1_B_MARK,
};
/* - DRIF3 --------------------------------------------------------------- */
static const unsigned int drif3_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif3_ctrl_a_mux[] = {
RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
};
static const unsigned int drif3_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif3_data0_a_mux[] = {
RIF3_D0_A_MARK,
};
static const unsigned int drif3_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif3_data1_a_mux[] = {
RIF3_D1_A_MARK,
};
static const unsigned int drif3_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int drif3_ctrl_b_mux[] = {
RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
};
static const unsigned int drif3_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int drif3_data0_b_mux[] = {
RIF3_D0_B_MARK,
};
static const unsigned int drif3_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_clk_out_1_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(2, 3),
};
static const unsigned int du_clk_out_1_mux[] = {
DU_DOTCLKOUT1_MARK
};
static const unsigned int du_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
};
static const unsigned int du_sync_mux[] = {
DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
};
static const unsigned int du_oddf_pins[] = {
/* EXDISP/EXODDF/EXCDE */
RCAR_GP_PIN(2, 2),
};
static const unsigned int du_oddf_mux[] = {
DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(2, 0),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(2, 1),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
};
static const unsigned int hscif0_data_mux[] = {
HRX0_MARK, HTX0_MARK,
};
static const unsigned int hscif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK,
};
static const unsigned int hscif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
};
static const unsigned int hscif0_ctrl_mux[] = {
HRTS0_N_MARK, HCTS0_N_MARK,
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
};
static const unsigned int hscif1_data_a_mux[] = {
HRX1_A_MARK, HTX1_A_MARK,
};
static const unsigned int hscif1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif1_clk_a_mux[] = {
HSCK1_A_MARK,
};
static const unsigned int hscif1_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int hscif1_ctrl_a_mux[] = {
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
};
static const unsigned int hscif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int hscif1_data_b_mux[] = {
HRX1_B_MARK, HTX1_B_MARK,
};
static const unsigned int hscif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int hscif1_clk_b_mux[] = {
HSCK1_B_MARK,
};
static const unsigned int hscif1_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int hscif1_ctrl_b_mux[] = {
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int hscif2_data_a_mux[] = {
HRX2_A_MARK, HTX2_A_MARK,
};
static const unsigned int hscif2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 10),
};
static const unsigned int hscif2_clk_a_mux[] = {
HSCK2_A_MARK,
};
static const unsigned int hscif2_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
};
static const unsigned int hscif2_ctrl_a_mux[] = {
HRTS2_N_A_MARK, HCTS2_N_A_MARK,
};
static const unsigned int hscif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int hscif2_data_b_mux[] = {
HRX2_B_MARK, HTX2_B_MARK,
};
static const unsigned int hscif2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif2_clk_b_mux[] = {
HSCK2_B_MARK,
};
static const unsigned int hscif2_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
};
static const unsigned int hscif2_ctrl_b_mux[] = {
HRTS2_N_B_MARK, HCTS2_N_B_MARK,
};
static const unsigned int hscif2_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
};
static const unsigned int hscif2_data_c_mux[] = {
HRX2_C_MARK, HTX2_C_MARK,
};
static const unsigned int hscif2_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 24),
};
static const unsigned int hscif2_clk_c_mux[] = {
HSCK2_C_MARK,
};
static const unsigned int hscif2_ctrl_c_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
};
static const unsigned int hscif2_ctrl_c_mux[] = {
HRTS2_N_C_MARK, HCTS2_N_C_MARK,
};
/* - HSCIF3 ----------------------------------------------------------------- */
static const unsigned int hscif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int hscif3_data_a_mux[] = {
HRX3_A_MARK, HTX3_A_MARK,
};
static const unsigned int hscif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int hscif3_clk_mux[] = {
HSCK3_MARK,
};
static const unsigned int hscif3_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
static const unsigned int hscif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
};
static const unsigned int hscif3_data_b_mux[] = {
HRX3_B_MARK, HTX3_B_MARK,
};
static const unsigned int hscif3_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int hscif3_data_c_mux[] = {
HRX3_C_MARK, HTX3_C_MARK,
};
static const unsigned int hscif3_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int hscif3_data_d_mux[] = {
HRX3_D_MARK, HTX3_D_MARK,
};
/* - HSCIF4 ----------------------------------------------------------------- */
static const unsigned int hscif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const unsigned int hscif4_data_a_mux[] = {
HRX4_A_MARK, HTX4_A_MARK,
};
static const unsigned int hscif4_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_clk_mux[] = {
HSCK4_MARK,
};
static const unsigned int hscif4_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
};
static const unsigned int hscif4_ctrl_mux[] = {
HRTS4_N_MARK, HCTS4_N_MARK,
};
static const unsigned int hscif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_data_b_mux[] = {
HRX4_B_MARK, HTX4_B_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
static const unsigned int i2c1_a_mux[] = {
SDA1_A_MARK, SCL1_A_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
};
static const unsigned int i2c1_b_mux[] = {
SDA1_B_MARK, SCL1_B_MARK,
};
static const unsigned int i2c2_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int i2c2_a_mux[] = {
SDA2_A_MARK, SCL2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int i2c6_a_mux[] = {
SDA6_A_MARK, SCL6_A_MARK,
};
static const unsigned int i2c6_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int i2c6_b_mux[] = {
SDA6_B_MARK, SCL6_B_MARK,
};
static const unsigned int i2c6_c_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
RCAR_GP_PIN(2, 0),
};
static const unsigned int intc_ex_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_ex_irq1_pins[] = {
/* IRQ1 */
RCAR_GP_PIN(2, 1),
};
static const unsigned int intc_ex_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_ex_irq2_pins[] = {
/* IRQ2 */
RCAR_GP_PIN(2, 2),
};
static const unsigned int intc_ex_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_ex_irq3_pins[] = {
/* IRQ3 */
RCAR_GP_PIN(2, 3),
};
static const unsigned int intc_ex_irq3_mux[] = {
IRQ3_MARK,
};
static const unsigned int intc_ex_irq4_pins[] = {
/* IRQ4 */
RCAR_GP_PIN(2, 4),
};
static const unsigned int intc_ex_irq4_mux[] = {
IRQ4_MARK,
};
static const unsigned int intc_ex_irq5_pins[] = {
/* IRQ5 */
RCAR_GP_PIN(2, 5),
};
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
};
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 17),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 18),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 19),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 21),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 20),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 22),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 8),
};
static const unsigned int msiof1_clk_a_mux[] = {
MSIOF1_SCK_A_MARK,
};
static const unsigned int msiof1_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(6, 9),
};
static const unsigned int msiof1_sync_a_mux[] = {
MSIOF1_SYNC_A_MARK,
};
static const unsigned int msiof1_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 5),
};
static const unsigned int msiof1_ss1_a_mux[] = {
MSIOF1_SS1_A_MARK,
};
static const unsigned int msiof1_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 6),
};
static const unsigned int msiof1_ss2_a_mux[] = {
MSIOF1_SS2_A_MARK,
};
static const unsigned int msiof1_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 7),
};
static const unsigned int msiof1_txd_a_mux[] = {
MSIOF1_TXD_A_MARK,
};
static const unsigned int msiof1_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(6, 10),
};
static const unsigned int msiof1_rxd_a_mux[] = {
MSIOF1_RXD_A_MARK,
};
static const unsigned int msiof1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int msiof1_clk_b_mux[] = {
MSIOF1_SCK_B_MARK,
};
static const unsigned int msiof1_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 3),
};
static const unsigned int msiof1_sync_b_mux[] = {
MSIOF1_SYNC_B_MARK,
};
static const unsigned int msiof1_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 4),
};
static const unsigned int msiof1_ss1_b_mux[] = {
MSIOF1_SS1_B_MARK,
};
static const unsigned int msiof1_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 0),
};
static const unsigned int msiof1_ss2_b_mux[] = {
MSIOF1_SS2_B_MARK,
};
static const unsigned int msiof1_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 8),
};
static const unsigned int msiof1_txd_b_mux[] = {
MSIOF1_TXD_B_MARK,
};
static const unsigned int msiof1_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 7),
};
static const unsigned int msiof1_rxd_b_mux[] = {
MSIOF1_RXD_B_MARK,
};
static const unsigned int msiof1_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 17),
};
static const unsigned int msiof1_clk_c_mux[] = {
MSIOF1_SCK_C_MARK,
};
static const unsigned int msiof1_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(6, 18),
};
static const unsigned int msiof1_sync_c_mux[] = {
MSIOF1_SYNC_C_MARK,
};
static const unsigned int msiof1_ss1_c_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 21),
};
static const unsigned int msiof1_ss1_c_mux[] = {
MSIOF1_SS1_C_MARK,
};
static const unsigned int msiof1_ss2_c_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 27),
};
static const unsigned int msiof1_ss2_c_mux[] = {
MSIOF1_SS2_C_MARK,
};
static const unsigned int msiof1_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 20),
};
static const unsigned int msiof1_txd_c_mux[] = {
MSIOF1_TXD_C_MARK,
};
static const unsigned int msiof1_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(6, 19),
};
static const unsigned int msiof1_rxd_c_mux[] = {
MSIOF1_RXD_C_MARK,
};
static const unsigned int msiof1_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int msiof1_clk_d_mux[] = {
MSIOF1_SCK_D_MARK,
};
static const unsigned int msiof1_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 15),
};
static const unsigned int msiof1_sync_d_mux[] = {
MSIOF1_SYNC_D_MARK,
};
static const unsigned int msiof1_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 16),
};
static const unsigned int msiof1_ss1_d_mux[] = {
MSIOF1_SS1_D_MARK,
};
static const unsigned int msiof1_ss2_d_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 21),
};
static const unsigned int msiof1_ss2_d_mux[] = {
MSIOF1_SS2_D_MARK,
};
static const unsigned int msiof1_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 14),
};
static const unsigned int msiof1_txd_d_mux[] = {
MSIOF1_TXD_D_MARK,
};
static const unsigned int msiof1_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 13),
};
static const unsigned int msiof1_rxd_d_mux[] = {
MSIOF1_RXD_D_MARK,
};
static const unsigned int msiof1_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 0),
};
static const unsigned int msiof1_clk_e_mux[] = {
MSIOF1_SCK_E_MARK,
};
static const unsigned int msiof1_sync_e_pins[] = {
/* SYNC */
RCAR_GP_PIN(3, 1),
};
static const unsigned int msiof1_sync_e_mux[] = {
MSIOF1_SYNC_E_MARK,
};
static const unsigned int msiof1_ss1_e_pins[] = {
/* SS1 */
RCAR_GP_PIN(3, 4),
};
static const unsigned int msiof1_ss1_e_mux[] = {
MSIOF1_SS1_E_MARK,
};
static const unsigned int msiof1_ss2_e_pins[] = {
/* SS2 */
RCAR_GP_PIN(3, 5),
};
static const unsigned int msiof1_ss2_e_mux[] = {
MSIOF1_SS2_E_MARK,
};
static const unsigned int msiof1_txd_e_pins[] = {
/* TXD */
RCAR_GP_PIN(3, 3),
};
static const unsigned int msiof1_txd_e_mux[] = {
MSIOF1_TXD_E_MARK,
};
static const unsigned int msiof1_rxd_e_pins[] = {
/* RXD */
RCAR_GP_PIN(3, 2),
};
static const unsigned int msiof1_rxd_e_mux[] = {
MSIOF1_RXD_E_MARK,
};
static const unsigned int msiof1_clk_f_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 23),
};
static const unsigned int msiof1_clk_f_mux[] = {
MSIOF1_SCK_F_MARK,
};
static const unsigned int msiof1_sync_f_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 24),
};
static const unsigned int msiof1_sync_f_mux[] = {
MSIOF1_SYNC_F_MARK,
};
static const unsigned int msiof1_ss1_f_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 1),
};
static const unsigned int msiof1_ss1_f_mux[] = {
MSIOF1_SS1_F_MARK,
};
static const unsigned int msiof1_ss2_f_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 2),
};
static const unsigned int msiof1_ss2_f_mux[] = {
MSIOF1_SS2_F_MARK,
};
static const unsigned int msiof1_txd_f_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 0),
};
static const unsigned int msiof1_txd_f_mux[] = {
MSIOF1_TXD_F_MARK,
};
static const unsigned int msiof1_rxd_f_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 25),
};
static const unsigned int msiof1_rxd_f_mux[] = {
MSIOF1_RXD_F_MARK,
};
static const unsigned int msiof1_clk_g_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 6),
};
static const unsigned int msiof1_clk_g_mux[] = {
MSIOF1_SCK_G_MARK,
};
static const unsigned int msiof1_sync_g_pins[] = {
/* SYNC */
RCAR_GP_PIN(3, 7),
};
static const unsigned int msiof1_sync_g_mux[] = {
MSIOF1_SYNC_G_MARK,
};
static const unsigned int msiof1_ss1_g_pins[] = {
/* SS1 */
RCAR_GP_PIN(3, 10),
};
static const unsigned int msiof1_ss1_g_mux[] = {
MSIOF1_SS1_G_MARK,
};
static const unsigned int msiof1_ss2_g_pins[] = {
/* SS2 */
RCAR_GP_PIN(3, 11),
};
static const unsigned int msiof1_ss2_g_mux[] = {
MSIOF1_SS2_G_MARK,
};
static const unsigned int msiof1_txd_g_pins[] = {
/* TXD */
RCAR_GP_PIN(3, 9),
};
static const unsigned int msiof1_txd_g_mux[] = {
MSIOF1_TXD_G_MARK,
};
static const unsigned int msiof1_rxd_g_pins[] = {
/* RXD */
RCAR_GP_PIN(3, 8),
};
static const unsigned int msiof1_rxd_g_mux[] = {
MSIOF1_RXD_G_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 9),
};
static const unsigned int msiof2_clk_a_mux[] = {
MSIOF2_SCK_A_MARK,
};
static const unsigned int msiof2_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 8),
};
static const unsigned int msiof2_sync_a_mux[] = {
MSIOF2_SYNC_A_MARK,
};
static const unsigned int msiof2_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof2_ss1_a_mux[] = {
MSIOF2_SS1_A_MARK,
};
static const unsigned int msiof2_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof2_ss2_a_mux[] = {
MSIOF2_SS2_A_MARK,
};
static const unsigned int msiof2_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 11),
};
static const unsigned int msiof2_txd_a_mux[] = {
MSIOF2_TXD_A_MARK,
};
static const unsigned int msiof2_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 10),
};
static const unsigned int msiof2_rxd_a_mux[] = {
MSIOF2_RXD_A_MARK,
};
static const unsigned int msiof2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof2_clk_b_mux[] = {
MSIOF2_SCK_B_MARK,
};
static const unsigned int msiof2_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof2_sync_b_mux[] = {
MSIOF2_SYNC_B_MARK,
};
static const unsigned int msiof2_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 0),
};
static const unsigned int msiof2_ss1_b_mux[] = {
MSIOF2_SS1_B_MARK,
};
static const unsigned int msiof2_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof2_ss2_b_mux[] = {
MSIOF2_SS2_B_MARK,
};
static const unsigned int msiof2_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof2_txd_b_mux[] = {
MSIOF2_TXD_B_MARK,
};
static const unsigned int msiof2_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof2_rxd_b_mux[] = {
MSIOF2_RXD_B_MARK,
};
static const unsigned int msiof2_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 12),
};
static const unsigned int msiof2_clk_c_mux[] = {
MSIOF2_SCK_C_MARK,
};
static const unsigned int msiof2_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(2, 11),
};
static const unsigned int msiof2_sync_c_mux[] = {
MSIOF2_SYNC_C_MARK,
};
static const unsigned int msiof2_ss1_c_pins[] = {
/* SS1 */
RCAR_GP_PIN(2, 10),
};
static const unsigned int msiof2_ss1_c_mux[] = {
MSIOF2_SS1_C_MARK,
};
static const unsigned int msiof2_ss2_c_pins[] = {
/* SS2 */
RCAR_GP_PIN(2, 9),
};
static const unsigned int msiof2_ss2_c_mux[] = {
MSIOF2_SS2_C_MARK,
};
static const unsigned int msiof2_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(2, 14),
};
static const unsigned int msiof2_txd_c_mux[] = {
MSIOF2_TXD_C_MARK,
};
static const unsigned int msiof2_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(2, 13),
};
static const unsigned int msiof2_rxd_c_mux[] = {
MSIOF2_RXD_C_MARK,
};
static const unsigned int msiof2_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof2_clk_d_mux[] = {
MSIOF2_SCK_D_MARK,
};
static const unsigned int msiof2_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 9),
};
static const unsigned int msiof2_sync_d_mux[] = {
MSIOF2_SYNC_D_MARK,
};
static const unsigned int msiof2_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 12),
};
static const unsigned int msiof2_ss1_d_mux[] = {
MSIOF2_SS1_D_MARK,
};
static const unsigned int msiof2_ss2_d_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 13),
};
static const unsigned int msiof2_ss2_d_mux[] = {
MSIOF2_SS2_D_MARK,
};
static const unsigned int msiof2_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 11),
};
static const unsigned int msiof2_txd_d_mux[] = {
MSIOF2_TXD_D_MARK,
};
static const unsigned int msiof2_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 10),
};
static const unsigned int msiof2_rxd_d_mux[] = {
MSIOF2_RXD_D_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 0),
};
static const unsigned int msiof3_clk_a_mux[] = {
MSIOF3_SCK_A_MARK,
};
static const unsigned int msiof3_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof3_sync_a_mux[] = {
MSIOF3_SYNC_A_MARK,
};
static const unsigned int msiof3_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int msiof3_ss1_a_mux[] = {
MSIOF3_SS1_A_MARK,
};
static const unsigned int msiof3_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int msiof3_ss2_a_mux[] = {
MSIOF3_SS2_A_MARK,
};
static const unsigned int msiof3_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof3_txd_a_mux[] = {
MSIOF3_TXD_A_MARK,
};
static const unsigned int msiof3_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof3_rxd_a_mux[] = {
MSIOF3_RXD_A_MARK,
};
static const unsigned int msiof3_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 2),
};
static const unsigned int msiof3_clk_b_mux[] = {
MSIOF3_SCK_B_MARK,
};
static const unsigned int msiof3_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 0),
};
static const unsigned int msiof3_sync_b_mux[] = {
MSIOF3_SYNC_B_MARK,
};
static const unsigned int msiof3_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 4),
};
static const unsigned int msiof3_ss1_b_mux[] = {
MSIOF3_SS1_B_MARK,
};
static const unsigned int msiof3_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(1, 5),
};
static const unsigned int msiof3_ss2_b_mux[] = {
MSIOF3_SS2_B_MARK,
};
static const unsigned int msiof3_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 1),
};
static const unsigned int msiof3_txd_b_mux[] = {
MSIOF3_TXD_B_MARK,
};
static const unsigned int msiof3_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 3),
};
static const unsigned int msiof3_rxd_b_mux[] = {
MSIOF3_RXD_B_MARK,
};
static const unsigned int msiof3_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 12),
};
static const unsigned int msiof3_clk_c_mux[] = {
MSIOF3_SCK_C_MARK,
};
static const unsigned int msiof3_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 13),
};
static const unsigned int msiof3_sync_c_mux[] = {
MSIOF3_SYNC_C_MARK,
};
static const unsigned int msiof3_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 15),
};
static const unsigned int msiof3_txd_c_mux[] = {
MSIOF3_TXD_C_MARK,
};
static const unsigned int msiof3_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 14),
};
static const unsigned int msiof3_rxd_c_mux[] = {
MSIOF3_RXD_C_MARK,
};
static const unsigned int msiof3_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int msiof3_clk_d_mux[] = {
MSIOF3_SCK_D_MARK,
};
static const unsigned int msiof3_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 23),
};
static const unsigned int msiof3_sync_d_mux[] = {
MSIOF3_SYNC_D_MARK,
};
static const unsigned int msiof3_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 26),
};
static const unsigned int msiof3_ss1_d_mux[] = {
MSIOF3_SS1_D_MARK,
};
static const unsigned int msiof3_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 25),
};
static const unsigned int msiof3_txd_d_mux[] = {
MSIOF3_TXD_D_MARK,
};
static const unsigned int msiof3_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 24),
};
static const unsigned int msiof3_rxd_d_mux[] = {
MSIOF3_RXD_D_MARK,
};
static const unsigned int msiof3_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 3),
};
static const unsigned int msiof3_clk_e_mux[] = {
MSIOF3_SCK_E_MARK,
};
static const unsigned int msiof3_sync_e_pins[] = {
/* SYNC */
RCAR_GP_PIN(2, 2),
};
static const unsigned int msiof3_sync_e_mux[] = {
MSIOF3_SYNC_E_MARK,
};
static const unsigned int msiof3_ss1_e_pins[] = {
/* SS1 */
RCAR_GP_PIN(2, 1),
};
static const unsigned int msiof3_ss1_e_mux[] = {
MSIOF3_SS1_E_MARK,
};
static const unsigned int msiof3_ss2_e_pins[] = {
/* SS2 */
RCAR_GP_PIN(2, 0),
};
static const unsigned int msiof3_ss2_e_mux[] = {
MSIOF3_SS2_E_MARK,
};
static const unsigned int msiof3_txd_e_pins[] = {
/* TXD */
RCAR_GP_PIN(2, 5),
};
static const unsigned int msiof3_txd_e_mux[] = {
MSIOF3_TXD_E_MARK,
};
static const unsigned int msiof3_rxd_e_pins[] = {
/* RXD */
RCAR_GP_PIN(2, 4),
};
static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
};
/* - PWM0 --------------------------------------------------------------------*/
static const unsigned int pwm0_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 6),
};
static const unsigned int pwm0_mux[] = {
PWM0_MARK,
};
/* - PWM1 --------------------------------------------------------------------*/
static const unsigned int pwm1_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 7),
};
static const unsigned int pwm1_a_mux[] = {
PWM1_A_MARK,
};
static const unsigned int pwm1_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 8),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
/* - PWM2 --------------------------------------------------------------------*/
static const unsigned int pwm2_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 8),
};
static const unsigned int pwm2_a_mux[] = {
PWM2_A_MARK,
};
static const unsigned int pwm2_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 11),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
/* - PWM3 --------------------------------------------------------------------*/
static const unsigned int pwm3_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 0),
};
static const unsigned int pwm3_a_mux[] = {
PWM3_A_MARK,
};
static const unsigned int pwm3_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 2),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
/* - PWM4 --------------------------------------------------------------------*/
static const unsigned int pwm4_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 1),
};
static const unsigned int pwm4_a_mux[] = {
PWM4_A_MARK,
};
static const unsigned int pwm4_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 3),
};
static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
/* - PWM5 --------------------------------------------------------------------*/
static const unsigned int pwm5_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 2),
};
static const unsigned int pwm5_a_mux[] = {
PWM5_A_MARK,
};
static const unsigned int pwm5_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 4),
};
static const unsigned int pwm5_b_mux[] = {
PWM5_B_MARK,
};
/* - PWM6 --------------------------------------------------------------------*/
static const unsigned int pwm6_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 3),
};
static const unsigned int pwm6_a_mux[] = {
PWM6_A_MARK,
};
static const unsigned int pwm6_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 5),
};
static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
};
static const unsigned int scif1_data_a_mux[] = {
RX1_A_MARK, TX1_A_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
static const unsigned int scif2_data_a_mux[] = {
RX2_A_MARK, TX2_A_MARK,
};
static const unsigned int scif2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int scif2_clk_mux[] = {
SCK2_MARK,
};
static const unsigned int scif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
};
static const unsigned int scif2_data_b_mux[] = {
RX2_B_MARK, TX2_B_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int scif3_data_a_mux[] = {
RX3_A_MARK, TX3_A_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
static const unsigned int scif3_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int scif3_data_b_mux[] = {
RX3_B_MARK, TX3_B_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
};
static const unsigned int scif4_data_a_mux[] = {
RX4_A_MARK, TX4_A_MARK,
};
static const unsigned int scif4_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 10),
};
static const unsigned int scif4_clk_a_mux[] = {
SCK4_A_MARK,
};
static const unsigned int scif4_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
};
static const unsigned int scif4_ctrl_a_mux[] = {
RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int scif4_data_b_mux[] = {
RX4_B_MARK, TX4_B_MARK,
};
static const unsigned int scif4_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 5),
};
static const unsigned int scif4_clk_b_mux[] = {
SCK4_B_MARK,
};
static const unsigned int scif4_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int scif4_ctrl_b_mux[] = {
RTS4_N_B_MARK, CTS4_N_B_MARK,
};
static const unsigned int scif4_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
};
static const unsigned int scif4_data_c_mux[] = {
RX4_C_MARK, TX4_C_MARK,
};
static const unsigned int scif4_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 8),
};
static const unsigned int scif4_clk_c_mux[] = {
SCK4_C_MARK,
};
static const unsigned int scif4_ctrl_c_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
};
static const unsigned int scif4_ctrl_c_mux[] = {
RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
static const unsigned int scif5_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
};
static const unsigned int scif5_data_a_mux[] = {
RX5_A_MARK, TX5_A_MARK,
};
static const unsigned int scif5_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int scif5_clk_a_mux[] = {
SCK5_A_MARK,
};
static const unsigned int scif5_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
};
static const unsigned int scif5_data_b_mux[] = {
RX5_B_MARK, TX5_B_MARK,
};
static const unsigned int scif5_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int scif5_clk_b_mux[] = {
SCK5_B_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_a_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int scif_clk_a_mux[] = {
SCIF_CLK_A_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
};
static const unsigned int sdhi0_ctrl_mux[] = {
SD0_CLK_MARK, SD0_CMD_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
RCAR_GP_PIN(3, 12),
};
static const unsigned int sdhi0_cd_mux[] = {
SD0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
RCAR_GP_PIN(3, 13),
};
static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
};
static const unsigned int sdhi1_ctrl_mux[] = {
SD1_CLK_MARK, SD1_CMD_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
RCAR_GP_PIN(3, 14),
};
static const unsigned int sdhi1_cd_mux[] = {
SD1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
RCAR_GP_PIN(3, 15),
};
static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
SD2_DAT6_MARK, SD2_DAT7_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
};
static const unsigned int sdhi2_ctrl_mux[] = {
SD2_CLK_MARK, SD2_CMD_MARK,
};
static const unsigned int sdhi2_cd_a_pins[] = {
/* CD */
RCAR_GP_PIN(4, 13),
};
static const unsigned int sdhi2_cd_a_mux[] = {
SD2_CD_A_MARK,
};
static const unsigned int sdhi2_cd_b_pins[] = {
/* CD */
RCAR_GP_PIN(5, 10),
};
static const unsigned int sdhi2_cd_b_mux[] = {
SD2_CD_B_MARK,
};
static const unsigned int sdhi2_wp_a_pins[] = {
/* WP */
RCAR_GP_PIN(4, 14),
};
static const unsigned int sdhi2_wp_a_mux[] = {
SD2_WP_A_MARK,
};
static const unsigned int sdhi2_wp_b_pins[] = {
/* WP */
RCAR_GP_PIN(5, 11),
};
static const unsigned int sdhi2_wp_b_mux[] = {
SD2_WP_B_MARK,
};
static const unsigned int sdhi2_ds_pins[] = {
/* DS */
RCAR_GP_PIN(4, 6),
};
static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
SD3_DAT6_MARK, SD3_DAT7_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
};
static const unsigned int sdhi3_ctrl_mux[] = {
SD3_CLK_MARK, SD3_CMD_MARK,
};
static const unsigned int sdhi3_cd_pins[] = {
/* CD */
RCAR_GP_PIN(4, 15),
};
static const unsigned int sdhi3_cd_mux[] = {
SD3_CD_MARK,
};
static const unsigned int sdhi3_wp_pins[] = {
/* WP */
RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_wp_mux[] = {
SD3_WP_MARK,
};
static const unsigned int sdhi3_ds_pins[] = {
/* DS */
RCAR_GP_PIN(4, 17),
};
static const unsigned int sdhi3_ds_mux[] = {
SD3_DS_MARK,
};
/* - SSI -------------------------------------------------------------------- */
static const unsigned int ssi0_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 2),
};
static const unsigned int ssi0_data_mux[] = {
SSI_SDATA0_MARK,
};
static const unsigned int ssi01239_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
};
static const unsigned int ssi01239_ctrl_mux[] = {
SSI_SCK01239_MARK, SSI_WS01239_MARK,
};
static const unsigned int ssi1_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 3),
};
static const unsigned int ssi1_data_a_mux[] = {
SSI_SDATA1_A_MARK,
};
static const unsigned int ssi1_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 12),
};
static const unsigned int ssi1_data_b_mux[] = {
SSI_SDATA1_B_MARK,
};
static const unsigned int ssi1_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int ssi1_ctrl_a_mux[] = {
SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
};
static const unsigned int ssi1_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
};
static const unsigned int ssi1_ctrl_b_mux[] = {
SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
};
static const unsigned int ssi2_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 4),
};
static const unsigned int ssi2_data_a_mux[] = {
SSI_SDATA2_A_MARK,
};
static const unsigned int ssi2_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 13),
};
static const unsigned int ssi2_data_b_mux[] = {
SSI_SDATA2_B_MARK,
};
static const unsigned int ssi2_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
};
static const unsigned int ssi2_ctrl_a_mux[] = {
SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
};
static const unsigned int ssi2_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int ssi2_ctrl_b_mux[] = {
SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
};
static const unsigned int ssi3_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 7),
};
static const unsigned int ssi3_data_mux[] = {
SSI_SDATA3_MARK,
};
static const unsigned int ssi349_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
};
static const unsigned int ssi349_ctrl_mux[] = {
SSI_SCK349_MARK, SSI_WS349_MARK,
};
static const unsigned int ssi4_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 10),
};
static const unsigned int ssi4_data_mux[] = {
SSI_SDATA4_MARK,
};
static const unsigned int ssi4_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int ssi4_ctrl_mux[] = {
SSI_SCK4_MARK, SSI_WS4_MARK,
};
static const unsigned int ssi5_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 13),
};
static const unsigned int ssi5_data_mux[] = {
SSI_SDATA5_MARK,
};
static const unsigned int ssi5_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
};
static const unsigned int ssi5_ctrl_mux[] = {
SSI_SCK5_MARK, SSI_WS5_MARK,
};
static const unsigned int ssi6_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 16),
};
static const unsigned int ssi6_data_mux[] = {
SSI_SDATA6_MARK,
};
static const unsigned int ssi6_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
};
static const unsigned int ssi6_ctrl_mux[] = {
SSI_SCK6_MARK, SSI_WS6_MARK,
};
static const unsigned int ssi7_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 19),
};
static const unsigned int ssi7_data_mux[] = {
SSI_SDATA7_MARK,
};
static const unsigned int ssi78_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int ssi78_ctrl_mux[] = {
SSI_SCK78_MARK, SSI_WS78_MARK,
};
static const unsigned int ssi8_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 20),
};
static const unsigned int ssi8_data_mux[] = {
SSI_SDATA8_MARK,
};
static const unsigned int ssi9_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 21),
};
static const unsigned int ssi9_data_a_mux[] = {
SSI_SDATA9_A_MARK,
};
static const unsigned int ssi9_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 14),
};
static const unsigned int ssi9_data_b_mux[] = {
SSI_SDATA9_B_MARK,
};
static const unsigned int ssi9_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
};
static const unsigned int ssi9_ctrl_a_mux[] = {
SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
};
static const unsigned int ssi9_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
};
static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const unsigned int tmu_tclk1_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int tmu_tclk1_a_mux[] = {
TCLK1_A_MARK,
};
static const unsigned int tmu_tclk1_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(5, 19),
};
static const unsigned int tmu_tclk1_b_mux[] = {
TCLK1_B_MARK,
};
static const unsigned int tmu_tclk2_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 19),
};
static const unsigned int tmu_tclk2_a_mux[] = {
TCLK2_A_MARK,
};
static const unsigned int tmu_tclk2_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
/* - USB30 ------------------------------------------------------------------ */
static const unsigned int usb30_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
/* FIELD */
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
/* CLKENB */
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
/* CLK */
VI5_CLK_MARK,
};
static const struct {
struct sh_pfc_pin_group common[324];
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_pin_group automotive[31];
#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
SH_PFC_PIN_GROUP(audio_clk_a_c),
SH_PFC_PIN_GROUP(audio_clk_b_a),
SH_PFC_PIN_GROUP(audio_clk_b_b),
SH_PFC_PIN_GROUP(audio_clk_c_a),
SH_PFC_PIN_GROUP(audio_clk_c_b),
SH_PFC_PIN_GROUP(audio_clkout_a),
SH_PFC_PIN_GROUP(audio_clkout_b),
SH_PFC_PIN_GROUP(audio_clkout_c),
SH_PFC_PIN_GROUP(audio_clkout_d),
SH_PFC_PIN_GROUP(audio_clkout1_a),
SH_PFC_PIN_GROUP(audio_clkout1_b),
SH_PFC_PIN_GROUP(audio_clkout2_a),
SH_PFC_PIN_GROUP(audio_clkout2_b),
SH_PFC_PIN_GROUP(audio_clkout3_a),
SH_PFC_PIN_GROUP(audio_clkout3_b),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_clk_out_1),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif1_data_a),
SH_PFC_PIN_GROUP(hscif1_clk_a),
SH_PFC_PIN_GROUP(hscif1_ctrl_a),
SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_a),
SH_PFC_PIN_GROUP(hscif2_clk_a),
SH_PFC_PIN_GROUP(hscif2_ctrl_a),
SH_PFC_PIN_GROUP(hscif2_data_b),
SH_PFC_PIN_GROUP(hscif2_clk_b),
SH_PFC_PIN_GROUP(hscif2_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_c),
SH_PFC_PIN_GROUP(hscif2_clk_c),
SH_PFC_PIN_GROUP(hscif2_ctrl_c),
SH_PFC_PIN_GROUP(hscif3_data_a),
SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(hscif3_ctrl),
SH_PFC_PIN_GROUP(hscif3_data_b),
SH_PFC_PIN_GROUP(hscif3_data_c),
SH_PFC_PIN_GROUP(hscif3_data_d),
SH_PFC_PIN_GROUP(hscif4_data_a),
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk_a),
SH_PFC_PIN_GROUP(msiof1_sync_a),
SH_PFC_PIN_GROUP(msiof1_ss1_a),
SH_PFC_PIN_GROUP(msiof1_ss2_a),
SH_PFC_PIN_GROUP(msiof1_txd_a),
SH_PFC_PIN_GROUP(msiof1_rxd_a),
SH_PFC_PIN_GROUP(msiof1_clk_b),
SH_PFC_PIN_GROUP(msiof1_sync_b),
SH_PFC_PIN_GROUP(msiof1_ss1_b),
SH_PFC_PIN_GROUP(msiof1_ss2_b),
SH_PFC_PIN_GROUP(msiof1_txd_b),
SH_PFC_PIN_GROUP(msiof1_rxd_b),
SH_PFC_PIN_GROUP(msiof1_clk_c),
SH_PFC_PIN_GROUP(msiof1_sync_c),
SH_PFC_PIN_GROUP(msiof1_ss1_c),
SH_PFC_PIN_GROUP(msiof1_ss2_c),
SH_PFC_PIN_GROUP(msiof1_txd_c),
SH_PFC_PIN_GROUP(msiof1_rxd_c),
SH_PFC_PIN_GROUP(msiof1_clk_d),
SH_PFC_PIN_GROUP(msiof1_sync_d),
SH_PFC_PIN_GROUP(msiof1_ss1_d),
SH_PFC_PIN_GROUP(msiof1_ss2_d),
SH_PFC_PIN_GROUP(msiof1_txd_d),
SH_PFC_PIN_GROUP(msiof1_rxd_d),
SH_PFC_PIN_GROUP(msiof1_clk_e),
SH_PFC_PIN_GROUP(msiof1_sync_e),
SH_PFC_PIN_GROUP(msiof1_ss1_e),
SH_PFC_PIN_GROUP(msiof1_ss2_e),
SH_PFC_PIN_GROUP(msiof1_txd_e),
SH_PFC_PIN_GROUP(msiof1_rxd_e),
SH_PFC_PIN_GROUP(msiof1_clk_f),
SH_PFC_PIN_GROUP(msiof1_sync_f),
SH_PFC_PIN_GROUP(msiof1_ss1_f),
SH_PFC_PIN_GROUP(msiof1_ss2_f),
SH_PFC_PIN_GROUP(msiof1_txd_f),
SH_PFC_PIN_GROUP(msiof1_rxd_f),
SH_PFC_PIN_GROUP(msiof1_clk_g),
SH_PFC_PIN_GROUP(msiof1_sync_g),
SH_PFC_PIN_GROUP(msiof1_ss1_g),
SH_PFC_PIN_GROUP(msiof1_ss2_g),
SH_PFC_PIN_GROUP(msiof1_txd_g),
SH_PFC_PIN_GROUP(msiof1_rxd_g),
SH_PFC_PIN_GROUP(msiof2_clk_a),
SH_PFC_PIN_GROUP(msiof2_sync_a),
SH_PFC_PIN_GROUP(msiof2_ss1_a),
SH_PFC_PIN_GROUP(msiof2_ss2_a),
SH_PFC_PIN_GROUP(msiof2_txd_a),
SH_PFC_PIN_GROUP(msiof2_rxd_a),
SH_PFC_PIN_GROUP(msiof2_clk_b),
SH_PFC_PIN_GROUP(msiof2_sync_b),
SH_PFC_PIN_GROUP(msiof2_ss1_b),
SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof2_txd_b),
SH_PFC_PIN_GROUP(msiof2_rxd_b),
SH_PFC_PIN_GROUP(msiof2_clk_c),
SH_PFC_PIN_GROUP(msiof2_sync_c),
SH_PFC_PIN_GROUP(msiof2_ss1_c),
SH_PFC_PIN_GROUP(msiof2_ss2_c),
SH_PFC_PIN_GROUP(msiof2_txd_c),
SH_PFC_PIN_GROUP(msiof2_rxd_c),
SH_PFC_PIN_GROUP(msiof2_clk_d),
SH_PFC_PIN_GROUP(msiof2_sync_d),
SH_PFC_PIN_GROUP(msiof2_ss1_d),
SH_PFC_PIN_GROUP(msiof2_ss2_d),
SH_PFC_PIN_GROUP(msiof2_txd_d),
SH_PFC_PIN_GROUP(msiof2_rxd_d),
SH_PFC_PIN_GROUP(msiof3_clk_a),
SH_PFC_PIN_GROUP(msiof3_sync_a),
SH_PFC_PIN_GROUP(msiof3_ss1_a),
SH_PFC_PIN_GROUP(msiof3_ss2_a),
SH_PFC_PIN_GROUP(msiof3_txd_a),
SH_PFC_PIN_GROUP(msiof3_rxd_a),
SH_PFC_PIN_GROUP(msiof3_clk_b),
SH_PFC_PIN_GROUP(msiof3_sync_b),
SH_PFC_PIN_GROUP(msiof3_ss1_b),
SH_PFC_PIN_GROUP(msiof3_ss2_b),
SH_PFC_PIN_GROUP(msiof3_txd_b),
SH_PFC_PIN_GROUP(msiof3_rxd_b),
SH_PFC_PIN_GROUP(msiof3_clk_c),
SH_PFC_PIN_GROUP(msiof3_sync_c),
SH_PFC_PIN_GROUP(msiof3_txd_c),
SH_PFC_PIN_GROUP(msiof3_rxd_c),
SH_PFC_PIN_GROUP(msiof3_clk_d),
SH_PFC_PIN_GROUP(msiof3_sync_d),
SH_PFC_PIN_GROUP(msiof3_ss1_d),
SH_PFC_PIN_GROUP(msiof3_txd_d),
SH_PFC_PIN_GROUP(msiof3_rxd_d),
SH_PFC_PIN_GROUP(msiof3_clk_e),
SH_PFC_PIN_GROUP(msiof3_sync_e),
SH_PFC_PIN_GROUP(msiof3_ss1_e),
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm2_a),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(pwm5_a),
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data_a),
SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(scif1_data_b),
SH_PFC_PIN_GROUP(scif2_data_a),
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif2_data_b),
SH_PFC_PIN_GROUP(scif3_data_a),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
SH_PFC_PIN_GROUP(scif3_data_b),
SH_PFC_PIN_GROUP(scif4_data_a),
SH_PFC_PIN_GROUP(scif4_clk_a),
SH_PFC_PIN_GROUP(scif4_ctrl_a),
SH_PFC_PIN_GROUP(scif4_data_b),
SH_PFC_PIN_GROUP(scif4_clk_b),
SH_PFC_PIN_GROUP(scif4_ctrl_b),
SH_PFC_PIN_GROUP(scif4_data_c),
SH_PFC_PIN_GROUP(scif4_clk_c),
SH_PFC_PIN_GROUP(scif4_ctrl_c),
SH_PFC_PIN_GROUP(scif5_data_a),
SH_PFC_PIN_GROUP(scif5_clk_a),
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
SH_PFC_PIN_GROUP(sdhi3_ds),
SH_PFC_PIN_GROUP(ssi0_data),
SH_PFC_PIN_GROUP(ssi01239_ctrl),
SH_PFC_PIN_GROUP(ssi1_data_a),
SH_PFC_PIN_GROUP(ssi1_data_b),
SH_PFC_PIN_GROUP(ssi1_ctrl_a),
SH_PFC_PIN_GROUP(ssi1_ctrl_b),
SH_PFC_PIN_GROUP(ssi2_data_a),
SH_PFC_PIN_GROUP(ssi2_data_b),
SH_PFC_PIN_GROUP(ssi2_ctrl_a),
SH_PFC_PIN_GROUP(ssi2_ctrl_b),
SH_PFC_PIN_GROUP(ssi3_data),
SH_PFC_PIN_GROUP(ssi349_ctrl),
SH_PFC_PIN_GROUP(ssi4_data),
SH_PFC_PIN_GROUP(ssi4_ctrl),
SH_PFC_PIN_GROUP(ssi5_data),
SH_PFC_PIN_GROUP(ssi5_ctrl),
SH_PFC_PIN_GROUP(ssi6_data),
SH_PFC_PIN_GROUP(ssi6_ctrl),
SH_PFC_PIN_GROUP(ssi7_data),
SH_PFC_PIN_GROUP(ssi78_ctrl),
SH_PFC_PIN_GROUP(ssi8_data),
SH_PFC_PIN_GROUP(ssi9_data_a),
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
SH_PFC_PIN_GROUP(drif0_ctrl_b),
SH_PFC_PIN_GROUP(drif0_data0_b),
SH_PFC_PIN_GROUP(drif0_data1_b),
SH_PFC_PIN_GROUP(drif0_ctrl_c),
SH_PFC_PIN_GROUP(drif0_data0_c),
SH_PFC_PIN_GROUP(drif0_data1_c),
SH_PFC_PIN_GROUP(drif1_ctrl_a),
SH_PFC_PIN_GROUP(drif1_data0_a),
SH_PFC_PIN_GROUP(drif1_data1_a),
SH_PFC_PIN_GROUP(drif1_ctrl_b),
SH_PFC_PIN_GROUP(drif1_data0_b),
SH_PFC_PIN_GROUP(drif1_data1_b),
SH_PFC_PIN_GROUP(drif1_ctrl_c),
SH_PFC_PIN_GROUP(drif1_data0_c),
SH_PFC_PIN_GROUP(drif1_data1_c),
SH_PFC_PIN_GROUP(drif2_ctrl_a),
SH_PFC_PIN_GROUP(drif2_data0_a),
SH_PFC_PIN_GROUP(drif2_data1_a),
SH_PFC_PIN_GROUP(drif2_ctrl_b),
SH_PFC_PIN_GROUP(drif2_data0_b),
SH_PFC_PIN_GROUP(drif2_data1_b),
SH_PFC_PIN_GROUP(drif3_ctrl_a),
SH_PFC_PIN_GROUP(drif3_data0_a),
SH_PFC_PIN_GROUP(drif3_data1_a),
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
SH_PFC_PIN_GROUP(mlb_3pin),
}
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const char * const audio_clk_groups[] = {
"audio_clk_a_a",
"audio_clk_a_b",
"audio_clk_a_c",
"audio_clk_b_a",
"audio_clk_b_b",
"audio_clk_c_a",
"audio_clk_c_b",
"audio_clkout_a",
"audio_clkout_b",
"audio_clkout_c",
"audio_clkout_d",
"audio_clkout1_a",
"audio_clkout1_b",
"audio_clkout2_a",
"audio_clkout2_b",
"audio_clkout3_a",
"audio_clkout3_b",
};
static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc", /* Deprecated, please use "avb_mdio" instead */
"avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
"avb_avtp_capture_a",
"avb_avtp_match_b",
"avb_avtp_capture_b",
};
static const char * const can0_groups[] = {
"can0_data_a",
"can0_data_b",
};
static const char * const can1_groups[] = {
"can1_data",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const canfd0_groups[] = {
"canfd0_data_a",
"canfd0_data_b",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
"drif0_data1_a",
"drif0_ctrl_b",
"drif0_data0_b",
"drif0_data1_b",
"drif0_ctrl_c",
"drif0_data0_c",
"drif0_data1_c",
};
static const char * const drif1_groups[] = {
"drif1_ctrl_a",
"drif1_data0_a",
"drif1_data1_a",
"drif1_ctrl_b",
"drif1_data0_b",
"drif1_data1_b",
"drif1_ctrl_c",
"drif1_data0_c",
"drif1_data1_c",
};
static const char * const drif2_groups[] = {
"drif2_ctrl_a",
"drif2_data0_a",
"drif2_data1_a",
"drif2_ctrl_b",
"drif2_data0_b",
"drif2_data1_b",
};
static const char * const drif3_groups[] = {
"drif3_ctrl_a",
"drif3_data0_a",
"drif3_data1_a",
"drif3_ctrl_b",
"drif3_data0_b",
"drif3_data1_b",
};
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_out_0",
"du_clk_out_1",
"du_sync",
"du_oddf",
"du_cde",
"du_disp",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
};
static const char * const hscif1_groups[] = {
"hscif1_data_a",
"hscif1_clk_a",
"hscif1_ctrl_a",
"hscif1_data_b",
"hscif1_clk_b",
"hscif1_ctrl_b",
};
static const char * const hscif2_groups[] = {
"hscif2_data_a",
"hscif2_clk_a",
"hscif2_ctrl_a",
"hscif2_data_b",
"hscif2_clk_b",
"hscif2_ctrl_b",
"hscif2_data_c",
"hscif2_clk_c",
"hscif2_ctrl_c",
};
static const char * const hscif3_groups[] = {
"hscif3_data_a",
"hscif3_clk",
"hscif3_ctrl",
"hscif3_data_b",
"hscif3_data_c",
"hscif3_data_d",
};
static const char * const hscif4_groups[] = {
"hscif4_data_a",
"hscif4_clk",
"hscif4_ctrl",
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
};
static const char * const i2c2_groups[] = {
"i2c2_a",
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
"i2c6_c",
};
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
"intc_ex_irq2",
"intc_ex_irq3",
"intc_ex_irq4",
"intc_ex_irq5",
};
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
static const char * const mlb_3pin_groups[] = {
"mlb_3pin",
};
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk_a",
"msiof1_sync_a",
"msiof1_ss1_a",
"msiof1_ss2_a",
"msiof1_txd_a",
"msiof1_rxd_a",
"msiof1_clk_b",
"msiof1_sync_b",
"msiof1_ss1_b",
"msiof1_ss2_b",
"msiof1_txd_b",
"msiof1_rxd_b",
"msiof1_clk_c",
"msiof1_sync_c",
"msiof1_ss1_c",
"msiof1_ss2_c",
"msiof1_txd_c",
"msiof1_rxd_c",
"msiof1_clk_d",
"msiof1_sync_d",
"msiof1_ss1_d",
"msiof1_ss2_d",
"msiof1_txd_d",
"msiof1_rxd_d",
"msiof1_clk_e",
"msiof1_sync_e",
"msiof1_ss1_e",
"msiof1_ss2_e",
"msiof1_txd_e",
"msiof1_rxd_e",
"msiof1_clk_f",
"msiof1_sync_f",
"msiof1_ss1_f",
"msiof1_ss2_f",
"msiof1_txd_f",
"msiof1_rxd_f",
"msiof1_clk_g",
"msiof1_sync_g",
"msiof1_ss1_g",
"msiof1_ss2_g",
"msiof1_txd_g",
"msiof1_rxd_g",
};
static const char * const msiof2_groups[] = {
"msiof2_clk_a",
"msiof2_sync_a",
"msiof2_ss1_a",
"msiof2_ss2_a",
"msiof2_txd_a",
"msiof2_rxd_a",
"msiof2_clk_b",
"msiof2_sync_b",
"msiof2_ss1_b",
"msiof2_ss2_b",
"msiof2_txd_b",
"msiof2_rxd_b",
"msiof2_clk_c",
"msiof2_sync_c",
"msiof2_ss1_c",
"msiof2_ss2_c",
"msiof2_txd_c",
"msiof2_rxd_c",
"msiof2_clk_d",
"msiof2_sync_d",
"msiof2_ss1_d",
"msiof2_ss2_d",
"msiof2_txd_d",
"msiof2_rxd_d",
};
static const char * const msiof3_groups[] = {
"msiof3_clk_a",
"msiof3_sync_a",
"msiof3_ss1_a",
"msiof3_ss2_a",
"msiof3_txd_a",
"msiof3_rxd_a",
"msiof3_clk_b",
"msiof3_sync_b",
"msiof3_ss1_b",
"msiof3_ss2_b",
"msiof3_txd_b",
"msiof3_rxd_b",
"msiof3_clk_c",
"msiof3_sync_c",
"msiof3_txd_c",
"msiof3_rxd_c",
"msiof3_clk_d",
"msiof3_sync_d",
"msiof3_ss1_d",
"msiof3_txd_d",
"msiof3_rxd_d",
"msiof3_clk_e",
"msiof3_sync_e",
"msiof3_ss1_e",
"msiof3_ss2_e",
"msiof3_txd_e",
"msiof3_rxd_e",
};
static const char * const pwm0_groups[] = {
"pwm0",
};
static const char * const pwm1_groups[] = {
"pwm1_a",
"pwm1_b",
};
static const char * const pwm2_groups[] = {
"pwm2_a",
"pwm2_b",
};
static const char * const pwm3_groups[] = {
"pwm3_a",
"pwm3_b",
};
static const char * const pwm4_groups[] = {
"pwm4_a",
"pwm4_b",
};
static const char * const pwm5_groups[] = {
"pwm5_a",
"pwm5_b",
};
static const char * const pwm6_groups[] = {
"pwm6_a",
"pwm6_b",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
"scif1_data_a",
"scif1_clk",
"scif1_ctrl",
"scif1_data_b",
};
static const char * const scif2_groups[] = {
"scif2_data_a",
"scif2_clk",
"scif2_data_b",
};
static const char * const scif3_groups[] = {
"scif3_data_a",
"scif3_clk",
"scif3_ctrl",
"scif3_data_b",
};
static const char * const scif4_groups[] = {
"scif4_data_a",
"scif4_clk_a",
"scif4_ctrl_a",
"scif4_data_b",
"scif4_clk_b",
"scif4_ctrl_b",
"scif4_data_c",
"scif4_clk_c",
"scif4_ctrl_c",
};
static const char * const scif5_groups[] = {
"scif5_data_a",
"scif5_clk_a",
"scif5_data_b",
"scif5_clk_b",
};
static const char * const scif_clk_groups[] = {
"scif_clk_a",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_data8",
"sdhi2_ctrl",
"sdhi2_cd_a",
"sdhi2_wp_a",
"sdhi2_cd_b",
"sdhi2_wp_b",
"sdhi2_ds",
};
static const char * const sdhi3_groups[] = {
"sdhi3_data1",
"sdhi3_data4",
"sdhi3_data8",
"sdhi3_ctrl",
"sdhi3_cd",
"sdhi3_wp",
"sdhi3_ds",
};
static const char * const ssi_groups[] = {
"ssi0_data",
"ssi01239_ctrl",
"ssi1_data_a",
"ssi1_data_b",
"ssi1_ctrl_a",
"ssi1_ctrl_b",
"ssi2_data_a",
"ssi2_data_b",
"ssi2_ctrl_a",
"ssi2_ctrl_b",
"ssi3_data",
"ssi349_ctrl",
"ssi4_data",
"ssi4_ctrl",
"ssi5_data",
"ssi5_ctrl",
"ssi6_data",
"ssi6_ctrl",
"ssi7_data",
"ssi78_ctrl",
"ssi8_data",
"ssi9_data_a",
"ssi9_data_b",
"ssi9_ctrl_a",
"ssi9_ctrl_b",
};
static const char * const tmu_groups[] = {
"tmu_tclk1_a",
"tmu_tclk1_b",
"tmu_tclk2_a",
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const usb1_groups[] = {
"usb1",
};
static const char * const usb30_groups[] = {
"usb30",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_high8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct {
struct sh_pfc_function common[52];
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_function automotive[5];
#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(mlb_3pin),
}
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
GP_0_12_FN, GPSR0_12,
GP_0_11_FN, GPSR0_11,
GP_0_10_FN, GPSR0_10,
GP_0_9_FN, GPSR0_9,
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
GP_0_5_FN, GPSR0_5,
GP_0_4_FN, GPSR0_4,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_28_FN, GPSR1_28,
GP_1_27_FN, GPSR1_27,
GP_1_26_FN, GPSR1_26,
GP_1_25_FN, GPSR1_25,
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
GP_1_19_FN, GPSR1_19,
GP_1_18_FN, GPSR1_18,
GP_1_17_FN, GPSR1_17,
GP_1_16_FN, GPSR1_16,
GP_1_15_FN, GPSR1_15,
GP_1_14_FN, GPSR1_14,
GP_1_13_FN, GPSR1_13,
GP_1_12_FN, GPSR1_12,
GP_1_11_FN, GPSR1_11,
GP_1_10_FN, GPSR1_10,
GP_1_9_FN, GPSR1_9,
GP_1_8_FN, GPSR1_8,
GP_1_7_FN, GPSR1_7,
GP_1_6_FN, GPSR1_6,
GP_1_5_FN, GPSR1_5,
GP_1_4_FN, GPSR1_4,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
GP_2_11_FN, GPSR2_11,
GP_2_10_FN, GPSR2_10,
GP_2_9_FN, GPSR2_9,
GP_2_8_FN, GPSR2_8,
GP_2_7_FN, GPSR2_7,
GP_2_6_FN, GPSR2_6,
GP_2_5_FN, GPSR2_5,
GP_2_4_FN, GPSR2_4,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
GP_3_12_FN, GPSR3_12,
GP_3_11_FN, GPSR3_11,
GP_3_10_FN, GPSR3_10,
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
GP_3_6_FN, GPSR3_6,
GP_3_5_FN, GPSR3_5,
GP_3_4_FN, GPSR3_4,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
GP_4_14_FN, GPSR4_14,
GP_4_13_FN, GPSR4_13,
GP_4_12_FN, GPSR4_12,
GP_4_11_FN, GPSR4_11,
GP_4_10_FN, GPSR4_10,
GP_4_9_FN, GPSR4_9,
GP_4_8_FN, GPSR4_8,
GP_4_7_FN, GPSR4_7,
GP_4_6_FN, GPSR4_6,
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
GP_5_25_FN, GPSR5_25,
GP_5_24_FN, GPSR5_24,
GP_5_23_FN, GPSR5_23,
GP_5_22_FN, GPSR5_22,
GP_5_21_FN, GPSR5_21,
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
GP_5_17_FN, GPSR5_17,
GP_5_16_FN, GPSR5_16,
GP_5_15_FN, GPSR5_15,
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
GP_5_11_FN, GPSR5_11,
GP_5_10_FN, GPSR5_10,
GP_5_9_FN, GPSR5_9,
GP_5_8_FN, GPSR5_8,
GP_5_7_FN, GPSR5_7,
GP_5_6_FN, GPSR5_6,
GP_5_5_FN, GPSR5_5,
GP_5_4_FN, GPSR5_4,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
GP_6_28_FN, GPSR6_28,
GP_6_27_FN, GPSR6_27,
GP_6_26_FN, GPSR6_26,
GP_6_25_FN, GPSR6_25,
GP_6_24_FN, GPSR6_24,
GP_6_23_FN, GPSR6_23,
GP_6_22_FN, GPSR6_22,
GP_6_21_FN, GPSR6_21,
GP_6_20_FN, GPSR6_20,
GP_6_19_FN, GPSR6_19,
GP_6_18_FN, GPSR6_18,
GP_6_17_FN, GPSR6_17,
GP_6_16_FN, GPSR6_16,
GP_6_15_FN, GPSR6_15,
GP_6_14_FN, GPSR6_14,
GP_6_13_FN, GPSR6_13,
GP_6_12_FN, GPSR6_12,
GP_6_11_FN, GPSR6_11,
GP_6_10_FN, GPSR6_10,
GP_6_9_FN, GPSR6_9,
GP_6_8_FN, GPSR6_8,
GP_6_7_FN, GPSR6_7,
GP_6_6_FN, GPSR6_6,
GP_6_5_FN, GPSR6_5,
GP_6_4_FN, GPSR6_4,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_19_16
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_19_16
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_19_16
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_19_16
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_19_16
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_19_16
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_19_16
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
/* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_19_16
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_19_16
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_19_16
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_19_16
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_19_16
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_19_16
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_19_16
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_19_16
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
IP16_19_16
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
IP17_19_16
IP17_15_12
IP17_11_8
IP17_7_4
IP17_3_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
MOD_SEL0_23
MOD_SEL0_22
MOD_SEL0_21
MOD_SEL0_20
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
/* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
MOD_SEL0_10
MOD_SEL0_9_8
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
MOD_SEL1_25_24
MOD_SEL1_23_22_21
MOD_SEL1_20
MOD_SEL1_19
MOD_SEL1_18_17
MOD_SEL1_16
MOD_SEL1_15_14
MOD_SEL1_13
MOD_SEL1_12
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
-16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
MOD_SEL2_28_27
MOD_SEL2_26
MOD_SEL2_25_24_23
MOD_SEL2_22
MOD_SEL2_21
MOD_SEL2_20
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
} },
{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
} },
{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
{ /* sentinel */ }
};
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ }
};
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
bit = (pin & 0x1f) + 12;
return bit;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
[ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
[ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
[ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
[ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
[ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
[ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
[ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
[ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
[ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
[12] = RCAR_GP_PIN(1, 0), /* A0 */
[13] = RCAR_GP_PIN(1, 1), /* A1 */
[14] = RCAR_GP_PIN(1, 2), /* A2 */
[15] = RCAR_GP_PIN(1, 3), /* A3 */
[16] = RCAR_GP_PIN(1, 4), /* A4 */
[17] = RCAR_GP_PIN(1, 5), /* A5 */
[18] = RCAR_GP_PIN(1, 6), /* A6 */
[19] = RCAR_GP_PIN(1, 7), /* A7 */
[20] = RCAR_GP_PIN(1, 8), /* A8 */
[21] = RCAR_GP_PIN(1, 9), /* A9 */
[22] = RCAR_GP_PIN(1, 10), /* A10 */
[23] = RCAR_GP_PIN(1, 11), /* A11 */
[24] = RCAR_GP_PIN(1, 12), /* A12 */
[25] = RCAR_GP_PIN(1, 13), /* A13 */
[26] = RCAR_GP_PIN(1, 14), /* A14 */
[27] = RCAR_GP_PIN(1, 15), /* A15 */
[28] = RCAR_GP_PIN(1, 16), /* A16 */
[29] = RCAR_GP_PIN(1, 17), /* A17 */
[30] = RCAR_GP_PIN(1, 18), /* A18 */
[31] = RCAR_GP_PIN(1, 19), /* A19 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
[ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
[ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
[13] = RCAR_GP_PIN(0, 3), /* D3 */
[14] = RCAR_GP_PIN(0, 4), /* D4 */
[15] = RCAR_GP_PIN(0, 5), /* D5 */
[16] = RCAR_GP_PIN(0, 6), /* D6 */
[17] = RCAR_GP_PIN(0, 7), /* D7 */
[18] = RCAR_GP_PIN(0, 8), /* D8 */
[19] = RCAR_GP_PIN(0, 9), /* D9 */
[20] = RCAR_GP_PIN(0, 10), /* D10 */
[21] = RCAR_GP_PIN(0, 11), /* D11 */
[22] = RCAR_GP_PIN(0, 12), /* D12 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
[24] = RCAR_GP_PIN(0, 14), /* D14 */
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[ 1] = SH_PFC_PIN_NONE,
[ 2] = PIN_FSCLKST, /* FSCLKST */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
} },
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
[ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
[ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
[ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
[ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
[ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
[ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
[ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
[ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
[ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
[ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
[ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
[ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
[ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
} },
{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
[ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
[ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
[ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
[ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = PIN_PRESET_N, /* PRESET# */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
.name = "r8a774a1_pfc",
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77960
const struct sh_pfc_soc_info r8a77960_pinmux_info = {
.name = "r8a77960_pfc",
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
ARRAY_SIZE(pinmux_groups.automotive),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77961
const struct sh_pfc_soc_info r8a77961_pinmux_info = {
.name = "r8a77961_pfc",
.ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
ARRAY_SIZE(pinmux_groups.automotive),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a7796.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A77965 processor support - PFC hardware block.
*
* Copyright (C) 2018 Jacopo Mondi <[email protected]>
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
*/
/* GPSR0 */
#define GPSR0_15 F_(D15, IP7_11_8)
#define GPSR0_14 F_(D14, IP7_7_4)
#define GPSR0_13 F_(D13, IP7_3_0)
#define GPSR0_12 F_(D12, IP6_31_28)
#define GPSR0_11 F_(D11, IP6_27_24)
#define GPSR0_10 F_(D10, IP6_23_20)
#define GPSR0_9 F_(D9, IP6_19_16)
#define GPSR0_8 F_(D8, IP6_15_12)
#define GPSR0_7 F_(D7, IP6_11_8)
#define GPSR0_6 F_(D6, IP6_7_4)
#define GPSR0_5 F_(D5, IP6_3_0)
#define GPSR0_4 F_(D4, IP5_31_28)
#define GPSR0_3 F_(D3, IP5_27_24)
#define GPSR0_2 F_(D2, IP5_23_20)
#define GPSR0_1 F_(D1, IP5_19_16)
#define GPSR0_0 F_(D0, IP5_15_12)
/* GPSR1 */
#define GPSR1_28 FM(CLKOUT)
#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
#define GPSR1_26 F_(WE1_N, IP5_7_4)
#define GPSR1_25 F_(WE0_N, IP5_3_0)
#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
#define GPSR1_23 F_(RD_N, IP4_27_24)
#define GPSR1_22 F_(BS_N, IP4_23_20)
#define GPSR1_21 F_(CS1_N, IP4_19_16)
#define GPSR1_20 F_(CS0_N, IP4_15_12)
#define GPSR1_19 F_(A19, IP4_11_8)
#define GPSR1_18 F_(A18, IP4_7_4)
#define GPSR1_17 F_(A17, IP4_3_0)
#define GPSR1_16 F_(A16, IP3_31_28)
#define GPSR1_15 F_(A15, IP3_27_24)
#define GPSR1_14 F_(A14, IP3_23_20)
#define GPSR1_13 F_(A13, IP3_19_16)
#define GPSR1_12 F_(A12, IP3_15_12)
#define GPSR1_11 F_(A11, IP3_11_8)
#define GPSR1_10 F_(A10, IP3_7_4)
#define GPSR1_9 F_(A9, IP3_3_0)
#define GPSR1_8 F_(A8, IP2_31_28)
#define GPSR1_7 F_(A7, IP2_27_24)
#define GPSR1_6 F_(A6, IP2_23_20)
#define GPSR1_5 F_(A5, IP2_19_16)
#define GPSR1_4 F_(A4, IP2_15_12)
#define GPSR1_3 F_(A3, IP2_11_8)
#define GPSR1_2 F_(A2, IP2_7_4)
#define GPSR1_1 F_(A1, IP2_3_0)
#define GPSR1_0 F_(A0, IP1_31_28)
/* GPSR2 */
#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
#define GPSR2_8 F_(PWM2_A, IP1_27_24)
#define GPSR2_7 F_(PWM1_A, IP1_23_20)
#define GPSR2_6 F_(PWM0, IP1_19_16)
#define GPSR2_5 F_(IRQ5, IP1_15_12)
#define GPSR2_4 F_(IRQ4, IP1_11_8)
#define GPSR2_3 F_(IRQ3, IP1_7_4)
#define GPSR2_2 F_(IRQ2, IP1_3_0)
#define GPSR2_1 F_(IRQ1, IP0_31_28)
#define GPSR2_0 F_(IRQ0, IP0_27_24)
/* GPSR3 */
#define GPSR3_15 F_(SD1_WP, IP11_23_20)
#define GPSR3_14 F_(SD1_CD, IP11_19_16)
#define GPSR3_13 F_(SD0_WP, IP11_15_12)
#define GPSR3_12 F_(SD0_CD, IP11_11_8)
#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
/* GPSR4 */
#define GPSR4_17 F_(SD3_DS, IP11_7_4)
#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
#define GPSR4_6 F_(SD2_DS, IP9_27_24)
#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
/* GPSR5 */
#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
#define GPSR5_22 FM(MSIOF0_RXD)
#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
#define GPSR5_20 FM(MSIOF0_TXD)
#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
#define GPSR5_17 FM(MSIOF0_SCK)
#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
#define GPSR5_14 F_(HTX0, IP13_19_16)
#define GPSR5_13 F_(HRX0, IP13_15_12)
#define GPSR5_12 F_(HSCK0, IP13_11_8)
#define GPSR5_11 F_(RX2_A, IP13_7_4)
#define GPSR5_10 F_(TX2_A, IP13_3_0)
#define GPSR5_9 F_(SCK2, IP12_31_28)
#define GPSR5_8 F_(RTS1_N, IP12_27_24)
#define GPSR5_7 F_(CTS1_N, IP12_23_20)
#define GPSR5_6 F_(TX1_A, IP12_19_16)
#define GPSR5_5 F_(RX1_A, IP12_15_12)
#define GPSR5_4 F_(RTS0_N, IP12_11_8)
#define GPSR5_3 F_(CTS0_N, IP12_7_4)
#define GPSR5_2 F_(TX0, IP12_3_0)
#define GPSR5_1 F_(RX0, IP11_31_28)
#define GPSR5_0 F_(SCK0, IP11_27_24)
/* GPSR6 */
#define GPSR6_31 F_(GP6_31, IP18_7_4)
#define GPSR6_30 F_(GP6_30, IP18_3_0)
#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
#define GPSR6_13 FM(SSI_SDATA5)
#define GPSR6_12 FM(SSI_WS5)
#define GPSR6_11 FM(SSI_SCK5)
#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
GPSR6_31 \
GPSR6_30 \
GPSR6_29 \
GPSR1_28 GPSR6_28 \
GPSR1_27 GPSR6_27 \
GPSR1_26 GPSR6_26 \
GPSR1_25 GPSR5_25 GPSR6_25 \
GPSR1_24 GPSR5_24 GPSR6_24 \
GPSR1_23 GPSR5_23 GPSR6_23 \
GPSR1_22 GPSR5_22 GPSR6_22 \
GPSR1_21 GPSR5_21 GPSR6_21 \
GPSR1_20 GPSR5_20 GPSR6_20 \
GPSR1_19 GPSR5_19 GPSR6_19 \
GPSR1_18 GPSR5_18 GPSR6_18 \
GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
#define PINMUX_IPSR \
\
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
\
FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
\
FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
\
FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
\
FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
\
MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
MOD_SEL2_30 \
MOD_SEL1_29_28_27 MOD_SEL2_29 \
MOD_SEL0_28_27 MOD_SEL2_28_27 \
MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
MOD_SEL0_23 MOD_SEL1_23_22_21 \
MOD_SEL0_22 MOD_SEL2_22 \
MOD_SEL0_21 MOD_SEL2_21 \
MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
MOD_SEL2_17 \
MOD_SEL0_16 MOD_SEL1_16 \
MOD_SEL1_15_14 \
MOD_SEL0_14_13 \
MOD_SEL1_13 \
MOD_SEL0_12 MOD_SEL1_12 \
MOD_SEL0_11 MOD_SEL1_11 \
MOD_SEL0_10 MOD_SEL1_10 \
MOD_SEL0_9_8 MOD_SEL1_9 \
MOD_SEL0_7_6 \
MOD_SEL1_6 \
MOD_SEL0_5 MOD_SEL1_5 \
MOD_SEL0_4_3 MOD_SEL1_4 \
MOD_SEL1_3 \
MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0 MOD_SEL2_0
/*
* These pins are not able to be muxed but have other properties
* that can be set, such as drive-strength or pull-up/pull-down enable.
*/
#define PINMUX_STATIC \
FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
FM(QSPI0_IO2) FM(QSPI0_IO3) \
FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
FM(QSPI1_IO2) FM(QSPI1_IO3) \
FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
FM(PRESETOUT) \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_SINGLE(SSI_SCK5),
PINMUX_SINGLE(SSI_SDATA5),
PINMUX_SINGLE(SSI_WS5),
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
/* IPSR2 */
PINMUX_IPSR_GPSR(IP2_3_0, A1),
PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
PINMUX_IPSR_GPSR(IP2_7_4, A2),
PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
PINMUX_IPSR_GPSR(IP2_11_8, A3),
PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
PINMUX_IPSR_GPSR(IP2_15_12, A4),
PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
PINMUX_IPSR_GPSR(IP2_19_16, A5),
PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
PINMUX_IPSR_GPSR(IP2_23_20, A6),
PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
PINMUX_IPSR_GPSR(IP2_27_24, A7),
PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
PINMUX_IPSR_GPSR(IP2_31_28, A8),
PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_3_0, A9),
PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
PINMUX_IPSR_GPSR(IP3_7_4, A10),
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
PINMUX_IPSR_GPSR(IP3_11_8, A11),
PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
PINMUX_IPSR_GPSR(IP3_15_12, A12),
PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
PINMUX_IPSR_GPSR(IP3_19_16, A13),
PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
PINMUX_IPSR_GPSR(IP3_23_20, A14),
PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
PINMUX_IPSR_GPSR(IP3_27_24, A15),
PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
PINMUX_IPSR_GPSR(IP3_31_28, A16),
PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
/* IPSR4 */
PINMUX_IPSR_GPSR(IP4_3_0, A17),
PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
PINMUX_IPSR_GPSR(IP4_7_4, A18),
PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
PINMUX_IPSR_GPSR(IP4_11_8, A19),
PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
PINMUX_IPSR_GPSR(IP5_15_12, D0),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
PINMUX_IPSR_GPSR(IP5_19_16, D1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
PINMUX_IPSR_GPSR(IP5_23_20, D2),
PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
PINMUX_IPSR_GPSR(IP5_27_24, D3),
PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
PINMUX_IPSR_GPSR(IP5_31_28, D4),
PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_3_0, D5),
PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
PINMUX_IPSR_GPSR(IP6_7_4, D6),
PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
PINMUX_IPSR_GPSR(IP6_11_8, D7),
PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
PINMUX_IPSR_GPSR(IP6_15_12, D8),
PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
PINMUX_IPSR_GPSR(IP6_19_16, D9),
PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
PINMUX_IPSR_GPSR(IP6_23_20, D10),
PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
PINMUX_IPSR_GPSR(IP6_27_24, D11),
PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
PINMUX_IPSR_GPSR(IP6_31_28, D12),
PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_3_0, D13),
PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
PINMUX_IPSR_GPSR(IP7_7_4, D14),
PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
PINMUX_IPSR_GPSR(IP7_11_8, D15),
PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
/* IPSR8 */
PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
/* IPSR10 */
PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP11_31_28, RX0),
PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
/* IPSR12 */
PINMUX_IPSR_GPSR(IP12_3_0, TX0),
PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
/* IPSR13 */
PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
/* IPSR16 */
PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
* pin to the list without an associated function. The sh-pfc
* core will do the right thing and skip trying to mux the pin
* while still applying configuration to it.
*/
#define FM(x) PINMUX_DATA(x##_MARK, 0),
PINMUX_STATIC
#undef FM
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
static const unsigned int audio_clk_a_a_pins[] = {
/* CLK A */
RCAR_GP_PIN(6, 22),
};
static const unsigned int audio_clk_a_a_mux[] = {
AUDIO_CLKA_A_MARK,
};
static const unsigned int audio_clk_a_b_pins[] = {
/* CLK A */
RCAR_GP_PIN(5, 4),
};
static const unsigned int audio_clk_a_b_mux[] = {
AUDIO_CLKA_B_MARK,
};
static const unsigned int audio_clk_a_c_pins[] = {
/* CLK A */
RCAR_GP_PIN(5, 19),
};
static const unsigned int audio_clk_a_c_mux[] = {
AUDIO_CLKA_C_MARK,
};
static const unsigned int audio_clk_b_a_pins[] = {
/* CLK B */
RCAR_GP_PIN(5, 12),
};
static const unsigned int audio_clk_b_a_mux[] = {
AUDIO_CLKB_A_MARK,
};
static const unsigned int audio_clk_b_b_pins[] = {
/* CLK B */
RCAR_GP_PIN(6, 23),
};
static const unsigned int audio_clk_b_b_mux[] = {
AUDIO_CLKB_B_MARK,
};
static const unsigned int audio_clk_c_a_pins[] = {
/* CLK C */
RCAR_GP_PIN(5, 21),
};
static const unsigned int audio_clk_c_a_mux[] = {
AUDIO_CLKC_A_MARK,
};
static const unsigned int audio_clk_c_b_pins[] = {
/* CLK C */
RCAR_GP_PIN(5, 0),
};
static const unsigned int audio_clk_c_b_mux[] = {
AUDIO_CLKC_B_MARK,
};
static const unsigned int audio_clkout_a_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 18),
};
static const unsigned int audio_clkout_a_mux[] = {
AUDIO_CLKOUT_A_MARK,
};
static const unsigned int audio_clkout_b_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(6, 28),
};
static const unsigned int audio_clkout_b_mux[] = {
AUDIO_CLKOUT_B_MARK,
};
static const unsigned int audio_clkout_c_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 3),
};
static const unsigned int audio_clkout_c_mux[] = {
AUDIO_CLKOUT_C_MARK,
};
static const unsigned int audio_clkout_d_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(5, 21),
};
static const unsigned int audio_clkout_d_mux[] = {
AUDIO_CLKOUT_D_MARK,
};
static const unsigned int audio_clkout1_a_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(5, 15),
};
static const unsigned int audio_clkout1_a_mux[] = {
AUDIO_CLKOUT1_A_MARK,
};
static const unsigned int audio_clkout1_b_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int audio_clkout1_b_mux[] = {
AUDIO_CLKOUT1_B_MARK,
};
static const unsigned int audio_clkout2_a_pins[] = {
/* CLKOUT2 */
RCAR_GP_PIN(5, 16),
};
static const unsigned int audio_clkout2_a_mux[] = {
AUDIO_CLKOUT2_A_MARK,
};
static const unsigned int audio_clkout2_b_pins[] = {
/* CLKOUT2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int audio_clkout2_b_mux[] = {
AUDIO_CLKOUT2_B_MARK,
};
static const unsigned int audio_clkout3_a_pins[] = {
/* CLKOUT3 */
RCAR_GP_PIN(5, 19),
};
static const unsigned int audio_clkout3_a_mux[] = {
AUDIO_CLKOUT3_A_MARK,
};
static const unsigned int audio_clkout3_b_pins[] = {
/* CLKOUT3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int audio_clkout3_b_mux[] = {
AUDIO_CLKOUT3_B_MARK,
};
/* - EtherAVB --------------------------------------------------------------- */
static const unsigned int avb_link_pins[] = {
/* AVB_LINK */
RCAR_GP_PIN(2, 12),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
/* AVB_MAGIC_ */
RCAR_GP_PIN(2, 10),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
/* AVB_PHY_INT */
RCAR_GP_PIN(2, 11),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
/*
* AVB_TX_CTL, AVB_TXC, AVB_TD0,
* AVB_TD1, AVB_TD2, AVB_TD3,
* AVB_RX_CTL, AVB_RXC, AVB_RD0,
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
AVB_TXCREFCLK_MARK,
};
static const unsigned int avb_avtp_pps_pins[] = {
/* AVB_AVTP_PPS */
RCAR_GP_PIN(2, 6),
};
static const unsigned int avb_avtp_pps_mux[] = {
AVB_AVTP_PPS_MARK,
};
static const unsigned int avb_avtp_match_a_pins[] = {
/* AVB_AVTP_MATCH_A */
RCAR_GP_PIN(2, 13),
};
static const unsigned int avb_avtp_match_a_mux[] = {
AVB_AVTP_MATCH_A_MARK,
};
static const unsigned int avb_avtp_capture_a_pins[] = {
/* AVB_AVTP_CAPTURE_A */
RCAR_GP_PIN(2, 14),
};
static const unsigned int avb_avtp_capture_a_mux[] = {
AVB_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb_avtp_match_b_pins[] = {
/* AVB_AVTP_MATCH_B */
RCAR_GP_PIN(1, 8),
};
static const unsigned int avb_avtp_match_b_mux[] = {
AVB_AVTP_MATCH_B_MARK,
};
static const unsigned int avb_avtp_capture_b_pins[] = {
/* AVB_AVTP_CAPTURE_B */
RCAR_GP_PIN(1, 11),
};
static const unsigned int avb_avtp_capture_b_mux[] = {
AVB_AVTP_CAPTURE_B_MARK,
};
/* - CAN ------------------------------------------------------------------ */
static const unsigned int can0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int can0_data_a_mux[] = {
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int can1_data_mux[] = {
CAN1_TX_MARK, CAN1_RX_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 25),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - CAN FD --------------------------------------------------------------- */
static const unsigned int canfd0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int canfd0_data_a_mux[] = {
CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
};
static const unsigned int canfd0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int canfd0_data_b_mux[] = {
CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
};
static const unsigned int canfd1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
#ifdef CONFIG_PINCTRL_PFC_R8A77965
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif0_ctrl_a_mux[] = {
RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
};
static const unsigned int drif0_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif0_data0_a_mux[] = {
RIF0_D0_A_MARK,
};
static const unsigned int drif0_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif0_data1_a_mux[] = {
RIF0_D1_A_MARK,
};
static const unsigned int drif0_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int drif0_ctrl_b_mux[] = {
RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
};
static const unsigned int drif0_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 1),
};
static const unsigned int drif0_data0_b_mux[] = {
RIF0_D0_B_MARK,
};
static const unsigned int drif0_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 2),
};
static const unsigned int drif0_data1_b_mux[] = {
RIF0_D1_B_MARK,
};
static const unsigned int drif0_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
};
static const unsigned int drif0_ctrl_c_mux[] = {
RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
};
static const unsigned int drif0_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 13),
};
static const unsigned int drif0_data0_c_mux[] = {
RIF0_D0_C_MARK,
};
static const unsigned int drif0_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 14),
};
static const unsigned int drif0_data1_c_mux[] = {
RIF0_D1_C_MARK,
};
/* - DRIF1 --------------------------------------------------------------- */
static const unsigned int drif1_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif1_ctrl_a_mux[] = {
RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
};
static const unsigned int drif1_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif1_data0_a_mux[] = {
RIF1_D0_A_MARK,
};
static const unsigned int drif1_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif1_data1_a_mux[] = {
RIF1_D1_A_MARK,
};
static const unsigned int drif1_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
};
static const unsigned int drif1_ctrl_b_mux[] = {
RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
};
static const unsigned int drif1_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 7),
};
static const unsigned int drif1_data0_b_mux[] = {
RIF1_D0_B_MARK,
};
static const unsigned int drif1_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 8),
};
static const unsigned int drif1_data1_b_mux[] = {
RIF1_D1_B_MARK,
};
static const unsigned int drif1_ctrl_c_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
};
static const unsigned int drif1_ctrl_c_mux[] = {
RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
};
static const unsigned int drif1_data0_c_pins[] = {
/* D0 */
RCAR_GP_PIN(5, 6),
};
static const unsigned int drif1_data0_c_mux[] = {
RIF1_D0_C_MARK,
};
static const unsigned int drif1_data1_c_pins[] = {
/* D1 */
RCAR_GP_PIN(5, 10),
};
static const unsigned int drif1_data1_c_mux[] = {
RIF1_D1_C_MARK,
};
/* - DRIF2 --------------------------------------------------------------- */
static const unsigned int drif2_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int drif2_ctrl_a_mux[] = {
RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
};
static const unsigned int drif2_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 7),
};
static const unsigned int drif2_data0_a_mux[] = {
RIF2_D0_A_MARK,
};
static const unsigned int drif2_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 10),
};
static const unsigned int drif2_data1_a_mux[] = {
RIF2_D1_A_MARK,
};
static const unsigned int drif2_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int drif2_ctrl_b_mux[] = {
RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
};
static const unsigned int drif2_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int drif2_data0_b_mux[] = {
RIF2_D0_B_MARK,
};
static const unsigned int drif2_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int drif2_data1_b_mux[] = {
RIF2_D1_B_MARK,
};
/* - DRIF3 --------------------------------------------------------------- */
static const unsigned int drif3_ctrl_a_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int drif3_ctrl_a_mux[] = {
RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
};
static const unsigned int drif3_data0_a_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 19),
};
static const unsigned int drif3_data0_a_mux[] = {
RIF3_D0_A_MARK,
};
static const unsigned int drif3_data1_a_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 20),
};
static const unsigned int drif3_data1_a_mux[] = {
RIF3_D1_A_MARK,
};
static const unsigned int drif3_ctrl_b_pins[] = {
/* CLK, SYNC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int drif3_ctrl_b_mux[] = {
RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
};
static const unsigned int drif3_data0_b_pins[] = {
/* D0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int drif3_data0_b_mux[] = {
RIF3_D0_B_MARK,
};
static const unsigned int drif3_data1_b_pins[] = {
/* D1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_clk_out_1_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(2, 3),
};
static const unsigned int du_clk_out_1_mux[] = {
DU_DOTCLKOUT1_MARK
};
static const unsigned int du_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
};
static const unsigned int du_sync_mux[] = {
DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
};
static const unsigned int du_oddf_pins[] = {
/* EXDISP/EXODDF/EXCDE */
RCAR_GP_PIN(2, 2),
};
static const unsigned int du_oddf_mux[] = {
DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(2, 0),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(2, 1),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
};
static const unsigned int hscif0_data_mux[] = {
HRX0_MARK, HTX0_MARK,
};
static const unsigned int hscif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK,
};
static const unsigned int hscif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
};
static const unsigned int hscif0_ctrl_mux[] = {
HRTS0_N_MARK, HCTS0_N_MARK,
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
};
static const unsigned int hscif1_data_a_mux[] = {
HRX1_A_MARK, HTX1_A_MARK,
};
static const unsigned int hscif1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif1_clk_a_mux[] = {
HSCK1_A_MARK,
};
static const unsigned int hscif1_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int hscif1_ctrl_a_mux[] = {
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
};
static const unsigned int hscif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int hscif1_data_b_mux[] = {
HRX1_B_MARK, HTX1_B_MARK,
};
static const unsigned int hscif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int hscif1_clk_b_mux[] = {
HSCK1_B_MARK,
};
static const unsigned int hscif1_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int hscif1_ctrl_b_mux[] = {
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int hscif2_data_a_mux[] = {
HRX2_A_MARK, HTX2_A_MARK,
};
static const unsigned int hscif2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 10),
};
static const unsigned int hscif2_clk_a_mux[] = {
HSCK2_A_MARK,
};
static const unsigned int hscif2_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
};
static const unsigned int hscif2_ctrl_a_mux[] = {
HRTS2_N_A_MARK, HCTS2_N_A_MARK,
};
static const unsigned int hscif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int hscif2_data_b_mux[] = {
HRX2_B_MARK, HTX2_B_MARK,
};
static const unsigned int hscif2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif2_clk_b_mux[] = {
HSCK2_B_MARK,
};
static const unsigned int hscif2_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
};
static const unsigned int hscif2_ctrl_b_mux[] = {
HRTS2_N_B_MARK, HCTS2_N_B_MARK,
};
static const unsigned int hscif2_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
};
static const unsigned int hscif2_data_c_mux[] = {
HRX2_C_MARK, HTX2_C_MARK,
};
static const unsigned int hscif2_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 24),
};
static const unsigned int hscif2_clk_c_mux[] = {
HSCK2_C_MARK,
};
static const unsigned int hscif2_ctrl_c_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
};
static const unsigned int hscif2_ctrl_c_mux[] = {
HRTS2_N_C_MARK, HCTS2_N_C_MARK,
};
/* - HSCIF3 ----------------------------------------------------------------- */
static const unsigned int hscif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int hscif3_data_a_mux[] = {
HRX3_A_MARK, HTX3_A_MARK,
};
static const unsigned int hscif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int hscif3_clk_mux[] = {
HSCK3_MARK,
};
static const unsigned int hscif3_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
static const unsigned int hscif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
};
static const unsigned int hscif3_data_b_mux[] = {
HRX3_B_MARK, HTX3_B_MARK,
};
static const unsigned int hscif3_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int hscif3_data_c_mux[] = {
HRX3_C_MARK, HTX3_C_MARK,
};
static const unsigned int hscif3_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int hscif3_data_d_mux[] = {
HRX3_D_MARK, HTX3_D_MARK,
};
/* - HSCIF4 ----------------------------------------------------------------- */
static const unsigned int hscif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const unsigned int hscif4_data_a_mux[] = {
HRX4_A_MARK, HTX4_A_MARK,
};
static const unsigned int hscif4_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_clk_mux[] = {
HSCK4_MARK,
};
static const unsigned int hscif4_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
};
static const unsigned int hscif4_ctrl_mux[] = {
HRTS4_N_MARK, HCTS4_N_MARK,
};
static const unsigned int hscif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_data_b_mux[] = {
HRX4_B_MARK, HTX4_B_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
static const unsigned int i2c1_a_mux[] = {
SDA1_A_MARK, SCL1_A_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
};
static const unsigned int i2c1_b_mux[] = {
SDA1_B_MARK, SCL1_B_MARK,
};
static const unsigned int i2c2_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int i2c2_a_mux[] = {
SDA2_A_MARK, SCL2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int i2c6_a_mux[] = {
SDA6_A_MARK, SCL6_A_MARK,
};
static const unsigned int i2c6_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int i2c6_b_mux[] = {
SDA6_B_MARK, SCL6_B_MARK,
};
static const unsigned int i2c6_c_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
RCAR_GP_PIN(2, 0),
};
static const unsigned int intc_ex_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_ex_irq1_pins[] = {
/* IRQ1 */
RCAR_GP_PIN(2, 1),
};
static const unsigned int intc_ex_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_ex_irq2_pins[] = {
/* IRQ2 */
RCAR_GP_PIN(2, 2),
};
static const unsigned int intc_ex_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_ex_irq3_pins[] = {
/* IRQ3 */
RCAR_GP_PIN(2, 3),
};
static const unsigned int intc_ex_irq3_mux[] = {
IRQ3_MARK,
};
static const unsigned int intc_ex_irq4_pins[] = {
/* IRQ4 */
RCAR_GP_PIN(2, 4),
};
static const unsigned int intc_ex_irq4_mux[] = {
IRQ4_MARK,
};
static const unsigned int intc_ex_irq5_pins[] = {
/* IRQ5 */
RCAR_GP_PIN(2, 5),
};
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
#ifdef CONFIG_PINCTRL_PFC_R8A77965
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
};
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 17),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 18),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 19),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 21),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 20),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 22),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 8),
};
static const unsigned int msiof1_clk_a_mux[] = {
MSIOF1_SCK_A_MARK,
};
static const unsigned int msiof1_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(6, 9),
};
static const unsigned int msiof1_sync_a_mux[] = {
MSIOF1_SYNC_A_MARK,
};
static const unsigned int msiof1_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 5),
};
static const unsigned int msiof1_ss1_a_mux[] = {
MSIOF1_SS1_A_MARK,
};
static const unsigned int msiof1_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 6),
};
static const unsigned int msiof1_ss2_a_mux[] = {
MSIOF1_SS2_A_MARK,
};
static const unsigned int msiof1_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 7),
};
static const unsigned int msiof1_txd_a_mux[] = {
MSIOF1_TXD_A_MARK,
};
static const unsigned int msiof1_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(6, 10),
};
static const unsigned int msiof1_rxd_a_mux[] = {
MSIOF1_RXD_A_MARK,
};
static const unsigned int msiof1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int msiof1_clk_b_mux[] = {
MSIOF1_SCK_B_MARK,
};
static const unsigned int msiof1_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 3),
};
static const unsigned int msiof1_sync_b_mux[] = {
MSIOF1_SYNC_B_MARK,
};
static const unsigned int msiof1_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 4),
};
static const unsigned int msiof1_ss1_b_mux[] = {
MSIOF1_SS1_B_MARK,
};
static const unsigned int msiof1_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 0),
};
static const unsigned int msiof1_ss2_b_mux[] = {
MSIOF1_SS2_B_MARK,
};
static const unsigned int msiof1_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 8),
};
static const unsigned int msiof1_txd_b_mux[] = {
MSIOF1_TXD_B_MARK,
};
static const unsigned int msiof1_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 7),
};
static const unsigned int msiof1_rxd_b_mux[] = {
MSIOF1_RXD_B_MARK,
};
static const unsigned int msiof1_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 17),
};
static const unsigned int msiof1_clk_c_mux[] = {
MSIOF1_SCK_C_MARK,
};
static const unsigned int msiof1_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(6, 18),
};
static const unsigned int msiof1_sync_c_mux[] = {
MSIOF1_SYNC_C_MARK,
};
static const unsigned int msiof1_ss1_c_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 21),
};
static const unsigned int msiof1_ss1_c_mux[] = {
MSIOF1_SS1_C_MARK,
};
static const unsigned int msiof1_ss2_c_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 27),
};
static const unsigned int msiof1_ss2_c_mux[] = {
MSIOF1_SS2_C_MARK,
};
static const unsigned int msiof1_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 20),
};
static const unsigned int msiof1_txd_c_mux[] = {
MSIOF1_TXD_C_MARK,
};
static const unsigned int msiof1_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(6, 19),
};
static const unsigned int msiof1_rxd_c_mux[] = {
MSIOF1_RXD_C_MARK,
};
static const unsigned int msiof1_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int msiof1_clk_d_mux[] = {
MSIOF1_SCK_D_MARK,
};
static const unsigned int msiof1_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 15),
};
static const unsigned int msiof1_sync_d_mux[] = {
MSIOF1_SYNC_D_MARK,
};
static const unsigned int msiof1_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(5, 16),
};
static const unsigned int msiof1_ss1_d_mux[] = {
MSIOF1_SS1_D_MARK,
};
static const unsigned int msiof1_ss2_d_pins[] = {
/* SS2 */
RCAR_GP_PIN(5, 21),
};
static const unsigned int msiof1_ss2_d_mux[] = {
MSIOF1_SS2_D_MARK,
};
static const unsigned int msiof1_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(5, 14),
};
static const unsigned int msiof1_txd_d_mux[] = {
MSIOF1_TXD_D_MARK,
};
static const unsigned int msiof1_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 13),
};
static const unsigned int msiof1_rxd_d_mux[] = {
MSIOF1_RXD_D_MARK,
};
static const unsigned int msiof1_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 0),
};
static const unsigned int msiof1_clk_e_mux[] = {
MSIOF1_SCK_E_MARK,
};
static const unsigned int msiof1_sync_e_pins[] = {
/* SYNC */
RCAR_GP_PIN(3, 1),
};
static const unsigned int msiof1_sync_e_mux[] = {
MSIOF1_SYNC_E_MARK,
};
static const unsigned int msiof1_ss1_e_pins[] = {
/* SS1 */
RCAR_GP_PIN(3, 4),
};
static const unsigned int msiof1_ss1_e_mux[] = {
MSIOF1_SS1_E_MARK,
};
static const unsigned int msiof1_ss2_e_pins[] = {
/* SS2 */
RCAR_GP_PIN(3, 5),
};
static const unsigned int msiof1_ss2_e_mux[] = {
MSIOF1_SS2_E_MARK,
};
static const unsigned int msiof1_txd_e_pins[] = {
/* TXD */
RCAR_GP_PIN(3, 3),
};
static const unsigned int msiof1_txd_e_mux[] = {
MSIOF1_TXD_E_MARK,
};
static const unsigned int msiof1_rxd_e_pins[] = {
/* RXD */
RCAR_GP_PIN(3, 2),
};
static const unsigned int msiof1_rxd_e_mux[] = {
MSIOF1_RXD_E_MARK,
};
static const unsigned int msiof1_clk_f_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 23),
};
static const unsigned int msiof1_clk_f_mux[] = {
MSIOF1_SCK_F_MARK,
};
static const unsigned int msiof1_sync_f_pins[] = {
/* SYNC */
RCAR_GP_PIN(5, 24),
};
static const unsigned int msiof1_sync_f_mux[] = {
MSIOF1_SYNC_F_MARK,
};
static const unsigned int msiof1_ss1_f_pins[] = {
/* SS1 */
RCAR_GP_PIN(6, 1),
};
static const unsigned int msiof1_ss1_f_mux[] = {
MSIOF1_SS1_F_MARK,
};
static const unsigned int msiof1_ss2_f_pins[] = {
/* SS2 */
RCAR_GP_PIN(6, 2),
};
static const unsigned int msiof1_ss2_f_mux[] = {
MSIOF1_SS2_F_MARK,
};
static const unsigned int msiof1_txd_f_pins[] = {
/* TXD */
RCAR_GP_PIN(6, 0),
};
static const unsigned int msiof1_txd_f_mux[] = {
MSIOF1_TXD_F_MARK,
};
static const unsigned int msiof1_rxd_f_pins[] = {
/* RXD */
RCAR_GP_PIN(5, 25),
};
static const unsigned int msiof1_rxd_f_mux[] = {
MSIOF1_RXD_F_MARK,
};
static const unsigned int msiof1_clk_g_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 6),
};
static const unsigned int msiof1_clk_g_mux[] = {
MSIOF1_SCK_G_MARK,
};
static const unsigned int msiof1_sync_g_pins[] = {
/* SYNC */
RCAR_GP_PIN(3, 7),
};
static const unsigned int msiof1_sync_g_mux[] = {
MSIOF1_SYNC_G_MARK,
};
static const unsigned int msiof1_ss1_g_pins[] = {
/* SS1 */
RCAR_GP_PIN(3, 10),
};
static const unsigned int msiof1_ss1_g_mux[] = {
MSIOF1_SS1_G_MARK,
};
static const unsigned int msiof1_ss2_g_pins[] = {
/* SS2 */
RCAR_GP_PIN(3, 11),
};
static const unsigned int msiof1_ss2_g_mux[] = {
MSIOF1_SS2_G_MARK,
};
static const unsigned int msiof1_txd_g_pins[] = {
/* TXD */
RCAR_GP_PIN(3, 9),
};
static const unsigned int msiof1_txd_g_mux[] = {
MSIOF1_TXD_G_MARK,
};
static const unsigned int msiof1_rxd_g_pins[] = {
/* RXD */
RCAR_GP_PIN(3, 8),
};
static const unsigned int msiof1_rxd_g_mux[] = {
MSIOF1_RXD_G_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 9),
};
static const unsigned int msiof2_clk_a_mux[] = {
MSIOF2_SCK_A_MARK,
};
static const unsigned int msiof2_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 8),
};
static const unsigned int msiof2_sync_a_mux[] = {
MSIOF2_SYNC_A_MARK,
};
static const unsigned int msiof2_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof2_ss1_a_mux[] = {
MSIOF2_SS1_A_MARK,
};
static const unsigned int msiof2_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof2_ss2_a_mux[] = {
MSIOF2_SS2_A_MARK,
};
static const unsigned int msiof2_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 11),
};
static const unsigned int msiof2_txd_a_mux[] = {
MSIOF2_TXD_A_MARK,
};
static const unsigned int msiof2_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 10),
};
static const unsigned int msiof2_rxd_a_mux[] = {
MSIOF2_RXD_A_MARK,
};
static const unsigned int msiof2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof2_clk_b_mux[] = {
MSIOF2_SCK_B_MARK,
};
static const unsigned int msiof2_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof2_sync_b_mux[] = {
MSIOF2_SYNC_B_MARK,
};
static const unsigned int msiof2_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 0),
};
static const unsigned int msiof2_ss1_b_mux[] = {
MSIOF2_SS1_B_MARK,
};
static const unsigned int msiof2_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof2_ss2_b_mux[] = {
MSIOF2_SS2_B_MARK,
};
static const unsigned int msiof2_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof2_txd_b_mux[] = {
MSIOF2_TXD_B_MARK,
};
static const unsigned int msiof2_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof2_rxd_b_mux[] = {
MSIOF2_RXD_B_MARK,
};
static const unsigned int msiof2_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 12),
};
static const unsigned int msiof2_clk_c_mux[] = {
MSIOF2_SCK_C_MARK,
};
static const unsigned int msiof2_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(2, 11),
};
static const unsigned int msiof2_sync_c_mux[] = {
MSIOF2_SYNC_C_MARK,
};
static const unsigned int msiof2_ss1_c_pins[] = {
/* SS1 */
RCAR_GP_PIN(2, 10),
};
static const unsigned int msiof2_ss1_c_mux[] = {
MSIOF2_SS1_C_MARK,
};
static const unsigned int msiof2_ss2_c_pins[] = {
/* SS2 */
RCAR_GP_PIN(2, 9),
};
static const unsigned int msiof2_ss2_c_mux[] = {
MSIOF2_SS2_C_MARK,
};
static const unsigned int msiof2_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(2, 14),
};
static const unsigned int msiof2_txd_c_mux[] = {
MSIOF2_TXD_C_MARK,
};
static const unsigned int msiof2_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(2, 13),
};
static const unsigned int msiof2_rxd_c_mux[] = {
MSIOF2_RXD_C_MARK,
};
static const unsigned int msiof2_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof2_clk_d_mux[] = {
MSIOF2_SCK_D_MARK,
};
static const unsigned int msiof2_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 9),
};
static const unsigned int msiof2_sync_d_mux[] = {
MSIOF2_SYNC_D_MARK,
};
static const unsigned int msiof2_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 12),
};
static const unsigned int msiof2_ss1_d_mux[] = {
MSIOF2_SS1_D_MARK,
};
static const unsigned int msiof2_ss2_d_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 13),
};
static const unsigned int msiof2_ss2_d_mux[] = {
MSIOF2_SS2_D_MARK,
};
static const unsigned int msiof2_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 11),
};
static const unsigned int msiof2_txd_d_mux[] = {
MSIOF2_TXD_D_MARK,
};
static const unsigned int msiof2_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 10),
};
static const unsigned int msiof2_rxd_d_mux[] = {
MSIOF2_RXD_D_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 0),
};
static const unsigned int msiof3_clk_a_mux[] = {
MSIOF3_SCK_A_MARK,
};
static const unsigned int msiof3_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof3_sync_a_mux[] = {
MSIOF3_SYNC_A_MARK,
};
static const unsigned int msiof3_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int msiof3_ss1_a_mux[] = {
MSIOF3_SS1_A_MARK,
};
static const unsigned int msiof3_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int msiof3_ss2_a_mux[] = {
MSIOF3_SS2_A_MARK,
};
static const unsigned int msiof3_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof3_txd_a_mux[] = {
MSIOF3_TXD_A_MARK,
};
static const unsigned int msiof3_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof3_rxd_a_mux[] = {
MSIOF3_RXD_A_MARK,
};
static const unsigned int msiof3_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 2),
};
static const unsigned int msiof3_clk_b_mux[] = {
MSIOF3_SCK_B_MARK,
};
static const unsigned int msiof3_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 0),
};
static const unsigned int msiof3_sync_b_mux[] = {
MSIOF3_SYNC_B_MARK,
};
static const unsigned int msiof3_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 4),
};
static const unsigned int msiof3_ss1_b_mux[] = {
MSIOF3_SS1_B_MARK,
};
static const unsigned int msiof3_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(1, 5),
};
static const unsigned int msiof3_ss2_b_mux[] = {
MSIOF3_SS2_B_MARK,
};
static const unsigned int msiof3_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 1),
};
static const unsigned int msiof3_txd_b_mux[] = {
MSIOF3_TXD_B_MARK,
};
static const unsigned int msiof3_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 3),
};
static const unsigned int msiof3_rxd_b_mux[] = {
MSIOF3_RXD_B_MARK,
};
static const unsigned int msiof3_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 12),
};
static const unsigned int msiof3_clk_c_mux[] = {
MSIOF3_SCK_C_MARK,
};
static const unsigned int msiof3_sync_c_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 13),
};
static const unsigned int msiof3_sync_c_mux[] = {
MSIOF3_SYNC_C_MARK,
};
static const unsigned int msiof3_txd_c_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 15),
};
static const unsigned int msiof3_txd_c_mux[] = {
MSIOF3_TXD_C_MARK,
};
static const unsigned int msiof3_rxd_c_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 14),
};
static const unsigned int msiof3_rxd_c_mux[] = {
MSIOF3_RXD_C_MARK,
};
static const unsigned int msiof3_clk_d_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int msiof3_clk_d_mux[] = {
MSIOF3_SCK_D_MARK,
};
static const unsigned int msiof3_sync_d_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 23),
};
static const unsigned int msiof3_sync_d_mux[] = {
MSIOF3_SYNC_D_MARK,
};
static const unsigned int msiof3_ss1_d_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 26),
};
static const unsigned int msiof3_ss1_d_mux[] = {
MSIOF3_SS1_D_MARK,
};
static const unsigned int msiof3_txd_d_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 25),
};
static const unsigned int msiof3_txd_d_mux[] = {
MSIOF3_TXD_D_MARK,
};
static const unsigned int msiof3_rxd_d_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 24),
};
static const unsigned int msiof3_rxd_d_mux[] = {
MSIOF3_RXD_D_MARK,
};
static const unsigned int msiof3_clk_e_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 3),
};
static const unsigned int msiof3_clk_e_mux[] = {
MSIOF3_SCK_E_MARK,
};
static const unsigned int msiof3_sync_e_pins[] = {
/* SYNC */
RCAR_GP_PIN(2, 2),
};
static const unsigned int msiof3_sync_e_mux[] = {
MSIOF3_SYNC_E_MARK,
};
static const unsigned int msiof3_ss1_e_pins[] = {
/* SS1 */
RCAR_GP_PIN(2, 1),
};
static const unsigned int msiof3_ss1_e_mux[] = {
MSIOF3_SS1_E_MARK,
};
static const unsigned int msiof3_ss2_e_pins[] = {
/* SS2 */
RCAR_GP_PIN(2, 0),
};
static const unsigned int msiof3_ss2_e_mux[] = {
MSIOF3_SS2_E_MARK,
};
static const unsigned int msiof3_txd_e_pins[] = {
/* TXD */
RCAR_GP_PIN(2, 5),
};
static const unsigned int msiof3_txd_e_mux[] = {
MSIOF3_TXD_E_MARK,
};
static const unsigned int msiof3_rxd_e_pins[] = {
/* RXD */
RCAR_GP_PIN(2, 4),
};
static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
};
/* - PWM0 --------------------------------------------------------------------*/
static const unsigned int pwm0_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 6),
};
static const unsigned int pwm0_mux[] = {
PWM0_MARK,
};
/* - PWM1 --------------------------------------------------------------------*/
static const unsigned int pwm1_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 7),
};
static const unsigned int pwm1_a_mux[] = {
PWM1_A_MARK,
};
static const unsigned int pwm1_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 8),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
/* - PWM2 --------------------------------------------------------------------*/
static const unsigned int pwm2_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 8),
};
static const unsigned int pwm2_a_mux[] = {
PWM2_A_MARK,
};
static const unsigned int pwm2_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 11),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
/* - PWM3 --------------------------------------------------------------------*/
static const unsigned int pwm3_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 0),
};
static const unsigned int pwm3_a_mux[] = {
PWM3_A_MARK,
};
static const unsigned int pwm3_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 2),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
/* - PWM4 --------------------------------------------------------------------*/
static const unsigned int pwm4_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 1),
};
static const unsigned int pwm4_a_mux[] = {
PWM4_A_MARK,
};
static const unsigned int pwm4_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 3),
};
static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
/* - PWM5 --------------------------------------------------------------------*/
static const unsigned int pwm5_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 2),
};
static const unsigned int pwm5_a_mux[] = {
PWM5_A_MARK,
};
static const unsigned int pwm5_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 4),
};
static const unsigned int pwm5_b_mux[] = {
PWM5_B_MARK,
};
/* - PWM6 --------------------------------------------------------------------*/
static const unsigned int pwm6_a_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 3),
};
static const unsigned int pwm6_a_mux[] = {
PWM6_A_MARK,
};
static const unsigned int pwm6_b_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 5),
};
static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
/* - SATA --------------------------------------------------------------------*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
RCAR_GP_PIN(6, 16),
};
static const unsigned int sata0_devslp_a_mux[] = {
SATA_DEVSLP_A_MARK,
};
static const unsigned int sata0_devslp_b_pins[] = {
/* DEVSLP */
RCAR_GP_PIN(4, 6),
};
static const unsigned int sata0_devslp_b_mux[] = {
SATA_DEVSLP_B_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
};
static const unsigned int scif1_data_a_mux[] = {
RX1_A_MARK, TX1_A_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
static const unsigned int scif2_data_a_mux[] = {
RX2_A_MARK, TX2_A_MARK,
};
static const unsigned int scif2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int scif2_clk_mux[] = {
SCK2_MARK,
};
static const unsigned int scif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
};
static const unsigned int scif2_data_b_mux[] = {
RX2_B_MARK, TX2_B_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int scif3_data_a_mux[] = {
RX3_A_MARK, TX3_A_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
static const unsigned int scif3_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int scif3_data_b_mux[] = {
RX3_B_MARK, TX3_B_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
};
static const unsigned int scif4_data_a_mux[] = {
RX4_A_MARK, TX4_A_MARK,
};
static const unsigned int scif4_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 10),
};
static const unsigned int scif4_clk_a_mux[] = {
SCK4_A_MARK,
};
static const unsigned int scif4_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
};
static const unsigned int scif4_ctrl_a_mux[] = {
RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int scif4_data_b_mux[] = {
RX4_B_MARK, TX4_B_MARK,
};
static const unsigned int scif4_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 5),
};
static const unsigned int scif4_clk_b_mux[] = {
SCK4_B_MARK,
};
static const unsigned int scif4_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int scif4_ctrl_b_mux[] = {
RTS4_N_B_MARK, CTS4_N_B_MARK,
};
static const unsigned int scif4_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
};
static const unsigned int scif4_data_c_mux[] = {
RX4_C_MARK, TX4_C_MARK,
};
static const unsigned int scif4_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 8),
};
static const unsigned int scif4_clk_c_mux[] = {
SCK4_C_MARK,
};
static const unsigned int scif4_ctrl_c_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
};
static const unsigned int scif4_ctrl_c_mux[] = {
RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
static const unsigned int scif5_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
};
static const unsigned int scif5_data_a_mux[] = {
RX5_A_MARK, TX5_A_MARK,
};
static const unsigned int scif5_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int scif5_clk_a_mux[] = {
SCK5_A_MARK,
};
static const unsigned int scif5_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
};
static const unsigned int scif5_data_b_mux[] = {
RX5_B_MARK, TX5_B_MARK,
};
static const unsigned int scif5_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int scif5_clk_b_mux[] = {
SCK5_B_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_a_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int scif_clk_a_mux[] = {
SCIF_CLK_A_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(5, 9),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
};
static const unsigned int sdhi0_ctrl_mux[] = {
SD0_CLK_MARK, SD0_CMD_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
RCAR_GP_PIN(3, 12),
};
static const unsigned int sdhi0_cd_mux[] = {
SD0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
RCAR_GP_PIN(3, 13),
};
static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
};
static const unsigned int sdhi1_ctrl_mux[] = {
SD1_CLK_MARK, SD1_CMD_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
RCAR_GP_PIN(3, 14),
};
static const unsigned int sdhi1_cd_mux[] = {
SD1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
RCAR_GP_PIN(3, 15),
};
static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
SD2_DAT6_MARK, SD2_DAT7_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
};
static const unsigned int sdhi2_ctrl_mux[] = {
SD2_CLK_MARK, SD2_CMD_MARK,
};
static const unsigned int sdhi2_cd_a_pins[] = {
/* CD */
RCAR_GP_PIN(4, 13),
};
static const unsigned int sdhi2_cd_a_mux[] = {
SD2_CD_A_MARK,
};
static const unsigned int sdhi2_cd_b_pins[] = {
/* CD */
RCAR_GP_PIN(5, 10),
};
static const unsigned int sdhi2_cd_b_mux[] = {
SD2_CD_B_MARK,
};
static const unsigned int sdhi2_wp_a_pins[] = {
/* WP */
RCAR_GP_PIN(4, 14),
};
static const unsigned int sdhi2_wp_a_mux[] = {
SD2_WP_A_MARK,
};
static const unsigned int sdhi2_wp_b_pins[] = {
/* WP */
RCAR_GP_PIN(5, 11),
};
static const unsigned int sdhi2_wp_b_mux[] = {
SD2_WP_B_MARK,
};
static const unsigned int sdhi2_ds_pins[] = {
/* DS */
RCAR_GP_PIN(4, 6),
};
static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
SD3_DAT6_MARK, SD3_DAT7_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
};
static const unsigned int sdhi3_ctrl_mux[] = {
SD3_CLK_MARK, SD3_CMD_MARK,
};
static const unsigned int sdhi3_cd_pins[] = {
/* CD */
RCAR_GP_PIN(4, 15),
};
static const unsigned int sdhi3_cd_mux[] = {
SD3_CD_MARK,
};
static const unsigned int sdhi3_wp_pins[] = {
/* WP */
RCAR_GP_PIN(4, 16),
};
static const unsigned int sdhi3_wp_mux[] = {
SD3_WP_MARK,
};
static const unsigned int sdhi3_ds_pins[] = {
/* DS */
RCAR_GP_PIN(4, 17),
};
static const unsigned int sdhi3_ds_mux[] = {
SD3_DS_MARK,
};
/* - SSI -------------------------------------------------------------------- */
static const unsigned int ssi0_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 2),
};
static const unsigned int ssi0_data_mux[] = {
SSI_SDATA0_MARK,
};
static const unsigned int ssi01239_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
};
static const unsigned int ssi01239_ctrl_mux[] = {
SSI_SCK01239_MARK, SSI_WS01239_MARK,
};
static const unsigned int ssi1_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 3),
};
static const unsigned int ssi1_data_a_mux[] = {
SSI_SDATA1_A_MARK,
};
static const unsigned int ssi1_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 12),
};
static const unsigned int ssi1_data_b_mux[] = {
SSI_SDATA1_B_MARK,
};
static const unsigned int ssi1_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int ssi1_ctrl_a_mux[] = {
SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
};
static const unsigned int ssi1_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
};
static const unsigned int ssi1_ctrl_b_mux[] = {
SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
};
static const unsigned int ssi2_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 4),
};
static const unsigned int ssi2_data_a_mux[] = {
SSI_SDATA2_A_MARK,
};
static const unsigned int ssi2_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 13),
};
static const unsigned int ssi2_data_b_mux[] = {
SSI_SDATA2_B_MARK,
};
static const unsigned int ssi2_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
};
static const unsigned int ssi2_ctrl_a_mux[] = {
SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
};
static const unsigned int ssi2_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int ssi2_ctrl_b_mux[] = {
SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
};
static const unsigned int ssi3_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 7),
};
static const unsigned int ssi3_data_mux[] = {
SSI_SDATA3_MARK,
};
static const unsigned int ssi349_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
};
static const unsigned int ssi349_ctrl_mux[] = {
SSI_SCK349_MARK, SSI_WS349_MARK,
};
static const unsigned int ssi4_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 10),
};
static const unsigned int ssi4_data_mux[] = {
SSI_SDATA4_MARK,
};
static const unsigned int ssi4_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int ssi4_ctrl_mux[] = {
SSI_SCK4_MARK, SSI_WS4_MARK,
};
static const unsigned int ssi5_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 13),
};
static const unsigned int ssi5_data_mux[] = {
SSI_SDATA5_MARK,
};
static const unsigned int ssi5_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
};
static const unsigned int ssi5_ctrl_mux[] = {
SSI_SCK5_MARK, SSI_WS5_MARK,
};
static const unsigned int ssi6_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 16),
};
static const unsigned int ssi6_data_mux[] = {
SSI_SDATA6_MARK,
};
static const unsigned int ssi6_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
};
static const unsigned int ssi6_ctrl_mux[] = {
SSI_SCK6_MARK, SSI_WS6_MARK,
};
static const unsigned int ssi7_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 19),
};
static const unsigned int ssi7_data_mux[] = {
SSI_SDATA7_MARK,
};
static const unsigned int ssi78_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int ssi78_ctrl_mux[] = {
SSI_SCK78_MARK, SSI_WS78_MARK,
};
static const unsigned int ssi8_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 20),
};
static const unsigned int ssi8_data_mux[] = {
SSI_SDATA8_MARK,
};
static const unsigned int ssi9_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(6, 21),
};
static const unsigned int ssi9_data_a_mux[] = {
SSI_SDATA9_A_MARK,
};
static const unsigned int ssi9_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(5, 14),
};
static const unsigned int ssi9_data_b_mux[] = {
SSI_SDATA9_B_MARK,
};
static const unsigned int ssi9_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
};
static const unsigned int ssi9_ctrl_a_mux[] = {
SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
};
static const unsigned int ssi9_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
};
static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const unsigned int tmu_tclk1_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int tmu_tclk1_a_mux[] = {
TCLK1_A_MARK,
};
static const unsigned int tmu_tclk1_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(5, 19),
};
static const unsigned int tmu_tclk1_b_mux[] = {
TCLK1_B_MARK,
};
static const unsigned int tmu_tclk2_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 19),
};
static const unsigned int tmu_tclk2_a_mux[] = {
TCLK2_A_MARK,
};
static const unsigned int tmu_tclk2_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
/* - USB30 ------------------------------------------------------------------ */
static const unsigned int usb30_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_a_mux[] = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_b_pins[] = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data_b_mux[] = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_data_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK,
};
static const struct {
struct sh_pfc_pin_group common[326];
#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_pin_group automotive[31];
#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
SH_PFC_PIN_GROUP(audio_clk_a_c),
SH_PFC_PIN_GROUP(audio_clk_b_a),
SH_PFC_PIN_GROUP(audio_clk_b_b),
SH_PFC_PIN_GROUP(audio_clk_c_a),
SH_PFC_PIN_GROUP(audio_clk_c_b),
SH_PFC_PIN_GROUP(audio_clkout_a),
SH_PFC_PIN_GROUP(audio_clkout_b),
SH_PFC_PIN_GROUP(audio_clkout_c),
SH_PFC_PIN_GROUP(audio_clkout_d),
SH_PFC_PIN_GROUP(audio_clkout1_a),
SH_PFC_PIN_GROUP(audio_clkout1_b),
SH_PFC_PIN_GROUP(audio_clkout2_a),
SH_PFC_PIN_GROUP(audio_clkout2_b),
SH_PFC_PIN_GROUP(audio_clkout3_a),
SH_PFC_PIN_GROUP(audio_clkout3_b),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_clk_out_1),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif1_data_a),
SH_PFC_PIN_GROUP(hscif1_clk_a),
SH_PFC_PIN_GROUP(hscif1_ctrl_a),
SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_a),
SH_PFC_PIN_GROUP(hscif2_clk_a),
SH_PFC_PIN_GROUP(hscif2_ctrl_a),
SH_PFC_PIN_GROUP(hscif2_data_b),
SH_PFC_PIN_GROUP(hscif2_clk_b),
SH_PFC_PIN_GROUP(hscif2_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_c),
SH_PFC_PIN_GROUP(hscif2_clk_c),
SH_PFC_PIN_GROUP(hscif2_ctrl_c),
SH_PFC_PIN_GROUP(hscif3_data_a),
SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(hscif3_ctrl),
SH_PFC_PIN_GROUP(hscif3_data_b),
SH_PFC_PIN_GROUP(hscif3_data_c),
SH_PFC_PIN_GROUP(hscif3_data_d),
SH_PFC_PIN_GROUP(hscif4_data_a),
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk_a),
SH_PFC_PIN_GROUP(msiof1_sync_a),
SH_PFC_PIN_GROUP(msiof1_ss1_a),
SH_PFC_PIN_GROUP(msiof1_ss2_a),
SH_PFC_PIN_GROUP(msiof1_txd_a),
SH_PFC_PIN_GROUP(msiof1_rxd_a),
SH_PFC_PIN_GROUP(msiof1_clk_b),
SH_PFC_PIN_GROUP(msiof1_sync_b),
SH_PFC_PIN_GROUP(msiof1_ss1_b),
SH_PFC_PIN_GROUP(msiof1_ss2_b),
SH_PFC_PIN_GROUP(msiof1_txd_b),
SH_PFC_PIN_GROUP(msiof1_rxd_b),
SH_PFC_PIN_GROUP(msiof1_clk_c),
SH_PFC_PIN_GROUP(msiof1_sync_c),
SH_PFC_PIN_GROUP(msiof1_ss1_c),
SH_PFC_PIN_GROUP(msiof1_ss2_c),
SH_PFC_PIN_GROUP(msiof1_txd_c),
SH_PFC_PIN_GROUP(msiof1_rxd_c),
SH_PFC_PIN_GROUP(msiof1_clk_d),
SH_PFC_PIN_GROUP(msiof1_sync_d),
SH_PFC_PIN_GROUP(msiof1_ss1_d),
SH_PFC_PIN_GROUP(msiof1_ss2_d),
SH_PFC_PIN_GROUP(msiof1_txd_d),
SH_PFC_PIN_GROUP(msiof1_rxd_d),
SH_PFC_PIN_GROUP(msiof1_clk_e),
SH_PFC_PIN_GROUP(msiof1_sync_e),
SH_PFC_PIN_GROUP(msiof1_ss1_e),
SH_PFC_PIN_GROUP(msiof1_ss2_e),
SH_PFC_PIN_GROUP(msiof1_txd_e),
SH_PFC_PIN_GROUP(msiof1_rxd_e),
SH_PFC_PIN_GROUP(msiof1_clk_f),
SH_PFC_PIN_GROUP(msiof1_sync_f),
SH_PFC_PIN_GROUP(msiof1_ss1_f),
SH_PFC_PIN_GROUP(msiof1_ss2_f),
SH_PFC_PIN_GROUP(msiof1_txd_f),
SH_PFC_PIN_GROUP(msiof1_rxd_f),
SH_PFC_PIN_GROUP(msiof1_clk_g),
SH_PFC_PIN_GROUP(msiof1_sync_g),
SH_PFC_PIN_GROUP(msiof1_ss1_g),
SH_PFC_PIN_GROUP(msiof1_ss2_g),
SH_PFC_PIN_GROUP(msiof1_txd_g),
SH_PFC_PIN_GROUP(msiof1_rxd_g),
SH_PFC_PIN_GROUP(msiof2_clk_a),
SH_PFC_PIN_GROUP(msiof2_sync_a),
SH_PFC_PIN_GROUP(msiof2_ss1_a),
SH_PFC_PIN_GROUP(msiof2_ss2_a),
SH_PFC_PIN_GROUP(msiof2_txd_a),
SH_PFC_PIN_GROUP(msiof2_rxd_a),
SH_PFC_PIN_GROUP(msiof2_clk_b),
SH_PFC_PIN_GROUP(msiof2_sync_b),
SH_PFC_PIN_GROUP(msiof2_ss1_b),
SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof2_txd_b),
SH_PFC_PIN_GROUP(msiof2_rxd_b),
SH_PFC_PIN_GROUP(msiof2_clk_c),
SH_PFC_PIN_GROUP(msiof2_sync_c),
SH_PFC_PIN_GROUP(msiof2_ss1_c),
SH_PFC_PIN_GROUP(msiof2_ss2_c),
SH_PFC_PIN_GROUP(msiof2_txd_c),
SH_PFC_PIN_GROUP(msiof2_rxd_c),
SH_PFC_PIN_GROUP(msiof2_clk_d),
SH_PFC_PIN_GROUP(msiof2_sync_d),
SH_PFC_PIN_GROUP(msiof2_ss1_d),
SH_PFC_PIN_GROUP(msiof2_ss2_d),
SH_PFC_PIN_GROUP(msiof2_txd_d),
SH_PFC_PIN_GROUP(msiof2_rxd_d),
SH_PFC_PIN_GROUP(msiof3_clk_a),
SH_PFC_PIN_GROUP(msiof3_sync_a),
SH_PFC_PIN_GROUP(msiof3_ss1_a),
SH_PFC_PIN_GROUP(msiof3_ss2_a),
SH_PFC_PIN_GROUP(msiof3_txd_a),
SH_PFC_PIN_GROUP(msiof3_rxd_a),
SH_PFC_PIN_GROUP(msiof3_clk_b),
SH_PFC_PIN_GROUP(msiof3_sync_b),
SH_PFC_PIN_GROUP(msiof3_ss1_b),
SH_PFC_PIN_GROUP(msiof3_ss2_b),
SH_PFC_PIN_GROUP(msiof3_txd_b),
SH_PFC_PIN_GROUP(msiof3_rxd_b),
SH_PFC_PIN_GROUP(msiof3_clk_c),
SH_PFC_PIN_GROUP(msiof3_sync_c),
SH_PFC_PIN_GROUP(msiof3_txd_c),
SH_PFC_PIN_GROUP(msiof3_rxd_c),
SH_PFC_PIN_GROUP(msiof3_clk_d),
SH_PFC_PIN_GROUP(msiof3_sync_d),
SH_PFC_PIN_GROUP(msiof3_ss1_d),
SH_PFC_PIN_GROUP(msiof3_txd_d),
SH_PFC_PIN_GROUP(msiof3_rxd_d),
SH_PFC_PIN_GROUP(msiof3_clk_e),
SH_PFC_PIN_GROUP(msiof3_sync_e),
SH_PFC_PIN_GROUP(msiof3_ss1_e),
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm2_a),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(pwm5_a),
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data_a),
SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(scif1_data_b),
SH_PFC_PIN_GROUP(scif2_data_a),
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif2_data_b),
SH_PFC_PIN_GROUP(scif3_data_a),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
SH_PFC_PIN_GROUP(scif3_data_b),
SH_PFC_PIN_GROUP(scif4_data_a),
SH_PFC_PIN_GROUP(scif4_clk_a),
SH_PFC_PIN_GROUP(scif4_ctrl_a),
SH_PFC_PIN_GROUP(scif4_data_b),
SH_PFC_PIN_GROUP(scif4_clk_b),
SH_PFC_PIN_GROUP(scif4_ctrl_b),
SH_PFC_PIN_GROUP(scif4_data_c),
SH_PFC_PIN_GROUP(scif4_clk_c),
SH_PFC_PIN_GROUP(scif4_ctrl_c),
SH_PFC_PIN_GROUP(scif5_data_a),
SH_PFC_PIN_GROUP(scif5_clk_a),
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
BUS_DATA_PIN_GROUP(sdhi3_data, 1),
BUS_DATA_PIN_GROUP(sdhi3_data, 4),
BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
SH_PFC_PIN_GROUP(sdhi3_ds),
SH_PFC_PIN_GROUP(ssi0_data),
SH_PFC_PIN_GROUP(ssi01239_ctrl),
SH_PFC_PIN_GROUP(ssi1_data_a),
SH_PFC_PIN_GROUP(ssi1_data_b),
SH_PFC_PIN_GROUP(ssi1_ctrl_a),
SH_PFC_PIN_GROUP(ssi1_ctrl_b),
SH_PFC_PIN_GROUP(ssi2_data_a),
SH_PFC_PIN_GROUP(ssi2_data_b),
SH_PFC_PIN_GROUP(ssi2_ctrl_a),
SH_PFC_PIN_GROUP(ssi2_ctrl_b),
SH_PFC_PIN_GROUP(ssi3_data),
SH_PFC_PIN_GROUP(ssi349_ctrl),
SH_PFC_PIN_GROUP(ssi4_data),
SH_PFC_PIN_GROUP(ssi4_ctrl),
SH_PFC_PIN_GROUP(ssi5_data),
SH_PFC_PIN_GROUP(ssi5_ctrl),
SH_PFC_PIN_GROUP(ssi6_data),
SH_PFC_PIN_GROUP(ssi6_ctrl),
SH_PFC_PIN_GROUP(ssi7_data),
SH_PFC_PIN_GROUP(ssi78_ctrl),
SH_PFC_PIN_GROUP(ssi8_data),
SH_PFC_PIN_GROUP(ssi9_data_a),
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
BUS_DATA_PIN_GROUP(vin5_data, 8),
BUS_DATA_PIN_GROUP(vin5_data, 10),
BUS_DATA_PIN_GROUP(vin5_data, 12),
BUS_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
SH_PFC_PIN_GROUP(drif0_ctrl_b),
SH_PFC_PIN_GROUP(drif0_data0_b),
SH_PFC_PIN_GROUP(drif0_data1_b),
SH_PFC_PIN_GROUP(drif0_ctrl_c),
SH_PFC_PIN_GROUP(drif0_data0_c),
SH_PFC_PIN_GROUP(drif0_data1_c),
SH_PFC_PIN_GROUP(drif1_ctrl_a),
SH_PFC_PIN_GROUP(drif1_data0_a),
SH_PFC_PIN_GROUP(drif1_data1_a),
SH_PFC_PIN_GROUP(drif1_ctrl_b),
SH_PFC_PIN_GROUP(drif1_data0_b),
SH_PFC_PIN_GROUP(drif1_data1_b),
SH_PFC_PIN_GROUP(drif1_ctrl_c),
SH_PFC_PIN_GROUP(drif1_data0_c),
SH_PFC_PIN_GROUP(drif1_data1_c),
SH_PFC_PIN_GROUP(drif2_ctrl_a),
SH_PFC_PIN_GROUP(drif2_data0_a),
SH_PFC_PIN_GROUP(drif2_data1_a),
SH_PFC_PIN_GROUP(drif2_ctrl_b),
SH_PFC_PIN_GROUP(drif2_data0_b),
SH_PFC_PIN_GROUP(drif2_data1_b),
SH_PFC_PIN_GROUP(drif3_ctrl_a),
SH_PFC_PIN_GROUP(drif3_data0_a),
SH_PFC_PIN_GROUP(drif3_data1_a),
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
SH_PFC_PIN_GROUP(mlb_3pin),
}
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const char * const audio_clk_groups[] = {
"audio_clk_a_a",
"audio_clk_a_b",
"audio_clk_a_c",
"audio_clk_b_a",
"audio_clk_b_b",
"audio_clk_c_a",
"audio_clk_c_b",
"audio_clkout_a",
"audio_clkout_b",
"audio_clkout_c",
"audio_clkout_d",
"audio_clkout1_a",
"audio_clkout1_b",
"audio_clkout2_a",
"audio_clkout2_b",
"audio_clkout3_a",
"audio_clkout3_b",
};
static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc", /* Deprecated, please use "avb_mdio" instead */
"avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
"avb_avtp_capture_a",
"avb_avtp_match_b",
"avb_avtp_capture_b",
};
static const char * const can0_groups[] = {
"can0_data_a",
"can0_data_b",
};
static const char * const can1_groups[] = {
"can1_data",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const canfd0_groups[] = {
"canfd0_data_a",
"canfd0_data_b",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
#ifdef CONFIG_PINCTRL_PFC_R8A77965
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
"drif0_data1_a",
"drif0_ctrl_b",
"drif0_data0_b",
"drif0_data1_b",
"drif0_ctrl_c",
"drif0_data0_c",
"drif0_data1_c",
};
static const char * const drif1_groups[] = {
"drif1_ctrl_a",
"drif1_data0_a",
"drif1_data1_a",
"drif1_ctrl_b",
"drif1_data0_b",
"drif1_data1_b",
"drif1_ctrl_c",
"drif1_data0_c",
"drif1_data1_c",
};
static const char * const drif2_groups[] = {
"drif2_ctrl_a",
"drif2_data0_a",
"drif2_data1_a",
"drif2_ctrl_b",
"drif2_data0_b",
"drif2_data1_b",
};
static const char * const drif3_groups[] = {
"drif3_ctrl_a",
"drif3_data0_a",
"drif3_data1_a",
"drif3_ctrl_b",
"drif3_data0_b",
"drif3_data1_b",
};
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_out_0",
"du_clk_out_1",
"du_sync",
"du_oddf",
"du_cde",
"du_disp",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
};
static const char * const hscif1_groups[] = {
"hscif1_data_a",
"hscif1_clk_a",
"hscif1_ctrl_a",
"hscif1_data_b",
"hscif1_clk_b",
"hscif1_ctrl_b",
};
static const char * const hscif2_groups[] = {
"hscif2_data_a",
"hscif2_clk_a",
"hscif2_ctrl_a",
"hscif2_data_b",
"hscif2_clk_b",
"hscif2_ctrl_b",
"hscif2_data_c",
"hscif2_clk_c",
"hscif2_ctrl_c",
};
static const char * const hscif3_groups[] = {
"hscif3_data_a",
"hscif3_clk",
"hscif3_ctrl",
"hscif3_data_b",
"hscif3_data_c",
"hscif3_data_d",
};
static const char * const hscif4_groups[] = {
"hscif4_data_a",
"hscif4_clk",
"hscif4_ctrl",
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
};
static const char * const i2c2_groups[] = {
"i2c2_a",
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
"i2c6_c",
};
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
"intc_ex_irq2",
"intc_ex_irq3",
"intc_ex_irq4",
"intc_ex_irq5",
};
#ifdef CONFIG_PINCTRL_PFC_R8A77965
static const char * const mlb_3pin_groups[] = {
"mlb_3pin",
};
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk_a",
"msiof1_sync_a",
"msiof1_ss1_a",
"msiof1_ss2_a",
"msiof1_txd_a",
"msiof1_rxd_a",
"msiof1_clk_b",
"msiof1_sync_b",
"msiof1_ss1_b",
"msiof1_ss2_b",
"msiof1_txd_b",
"msiof1_rxd_b",
"msiof1_clk_c",
"msiof1_sync_c",
"msiof1_ss1_c",
"msiof1_ss2_c",
"msiof1_txd_c",
"msiof1_rxd_c",
"msiof1_clk_d",
"msiof1_sync_d",
"msiof1_ss1_d",
"msiof1_ss2_d",
"msiof1_txd_d",
"msiof1_rxd_d",
"msiof1_clk_e",
"msiof1_sync_e",
"msiof1_ss1_e",
"msiof1_ss2_e",
"msiof1_txd_e",
"msiof1_rxd_e",
"msiof1_clk_f",
"msiof1_sync_f",
"msiof1_ss1_f",
"msiof1_ss2_f",
"msiof1_txd_f",
"msiof1_rxd_f",
"msiof1_clk_g",
"msiof1_sync_g",
"msiof1_ss1_g",
"msiof1_ss2_g",
"msiof1_txd_g",
"msiof1_rxd_g",
};
static const char * const msiof2_groups[] = {
"msiof2_clk_a",
"msiof2_sync_a",
"msiof2_ss1_a",
"msiof2_ss2_a",
"msiof2_txd_a",
"msiof2_rxd_a",
"msiof2_clk_b",
"msiof2_sync_b",
"msiof2_ss1_b",
"msiof2_ss2_b",
"msiof2_txd_b",
"msiof2_rxd_b",
"msiof2_clk_c",
"msiof2_sync_c",
"msiof2_ss1_c",
"msiof2_ss2_c",
"msiof2_txd_c",
"msiof2_rxd_c",
"msiof2_clk_d",
"msiof2_sync_d",
"msiof2_ss1_d",
"msiof2_ss2_d",
"msiof2_txd_d",
"msiof2_rxd_d",
};
static const char * const msiof3_groups[] = {
"msiof3_clk_a",
"msiof3_sync_a",
"msiof3_ss1_a",
"msiof3_ss2_a",
"msiof3_txd_a",
"msiof3_rxd_a",
"msiof3_clk_b",
"msiof3_sync_b",
"msiof3_ss1_b",
"msiof3_ss2_b",
"msiof3_txd_b",
"msiof3_rxd_b",
"msiof3_clk_c",
"msiof3_sync_c",
"msiof3_txd_c",
"msiof3_rxd_c",
"msiof3_clk_d",
"msiof3_sync_d",
"msiof3_ss1_d",
"msiof3_txd_d",
"msiof3_rxd_d",
"msiof3_clk_e",
"msiof3_sync_e",
"msiof3_ss1_e",
"msiof3_ss2_e",
"msiof3_txd_e",
"msiof3_rxd_e",
};
static const char * const pwm0_groups[] = {
"pwm0",
};
static const char * const pwm1_groups[] = {
"pwm1_a",
"pwm1_b",
};
static const char * const pwm2_groups[] = {
"pwm2_a",
"pwm2_b",
};
static const char * const pwm3_groups[] = {
"pwm3_a",
"pwm3_b",
};
static const char * const pwm4_groups[] = {
"pwm4_a",
"pwm4_b",
};
static const char * const pwm5_groups[] = {
"pwm5_a",
"pwm5_b",
};
static const char * const pwm6_groups[] = {
"pwm6_a",
"pwm6_b",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
"scif1_data_a",
"scif1_clk",
"scif1_ctrl",
"scif1_data_b",
};
static const char * const scif2_groups[] = {
"scif2_data_a",
"scif2_clk",
"scif2_data_b",
};
static const char * const scif3_groups[] = {
"scif3_data_a",
"scif3_clk",
"scif3_ctrl",
"scif3_data_b",
};
static const char * const scif4_groups[] = {
"scif4_data_a",
"scif4_clk_a",
"scif4_ctrl_a",
"scif4_data_b",
"scif4_clk_b",
"scif4_ctrl_b",
"scif4_data_c",
"scif4_clk_c",
"scif4_ctrl_c",
};
static const char * const scif5_groups[] = {
"scif5_data_a",
"scif5_clk_a",
"scif5_data_b",
"scif5_clk_b",
};
static const char * const scif_clk_groups[] = {
"scif_clk_a",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_data8",
"sdhi2_ctrl",
"sdhi2_cd_a",
"sdhi2_wp_a",
"sdhi2_cd_b",
"sdhi2_wp_b",
"sdhi2_ds",
};
static const char * const sdhi3_groups[] = {
"sdhi3_data1",
"sdhi3_data4",
"sdhi3_data8",
"sdhi3_ctrl",
"sdhi3_cd",
"sdhi3_wp",
"sdhi3_ds",
};
static const char * const ssi_groups[] = {
"ssi0_data",
"ssi01239_ctrl",
"ssi1_data_a",
"ssi1_data_b",
"ssi1_ctrl_a",
"ssi1_ctrl_b",
"ssi2_data_a",
"ssi2_data_b",
"ssi2_ctrl_a",
"ssi2_ctrl_b",
"ssi3_data",
"ssi349_ctrl",
"ssi4_data",
"ssi4_ctrl",
"ssi5_data",
"ssi5_ctrl",
"ssi6_data",
"ssi6_ctrl",
"ssi7_data",
"ssi78_ctrl",
"ssi8_data",
"ssi9_data_a",
"ssi9_data_b",
"ssi9_ctrl_a",
"ssi9_ctrl_b",
};
static const char * const tmu_groups[] = {
"tmu_tclk1_a",
"tmu_tclk1_b",
"tmu_tclk2_a",
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const usb1_groups[] = {
"usb1",
};
static const char * const usb30_groups[] = {
"usb30",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_high8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct {
struct sh_pfc_function common[53];
#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_function automotive[5];
#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
#ifdef CONFIG_PINCTRL_PFC_R8A77965
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(mlb_3pin),
}
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
GP_0_12_FN, GPSR0_12,
GP_0_11_FN, GPSR0_11,
GP_0_10_FN, GPSR0_10,
GP_0_9_FN, GPSR0_9,
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
GP_0_5_FN, GPSR0_5,
GP_0_4_FN, GPSR0_4,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_28_FN, GPSR1_28,
GP_1_27_FN, GPSR1_27,
GP_1_26_FN, GPSR1_26,
GP_1_25_FN, GPSR1_25,
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
GP_1_19_FN, GPSR1_19,
GP_1_18_FN, GPSR1_18,
GP_1_17_FN, GPSR1_17,
GP_1_16_FN, GPSR1_16,
GP_1_15_FN, GPSR1_15,
GP_1_14_FN, GPSR1_14,
GP_1_13_FN, GPSR1_13,
GP_1_12_FN, GPSR1_12,
GP_1_11_FN, GPSR1_11,
GP_1_10_FN, GPSR1_10,
GP_1_9_FN, GPSR1_9,
GP_1_8_FN, GPSR1_8,
GP_1_7_FN, GPSR1_7,
GP_1_6_FN, GPSR1_6,
GP_1_5_FN, GPSR1_5,
GP_1_4_FN, GPSR1_4,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1),
GROUP(
/* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
GP_2_11_FN, GPSR2_11,
GP_2_10_FN, GPSR2_10,
GP_2_9_FN, GPSR2_9,
GP_2_8_FN, GPSR2_8,
GP_2_7_FN, GPSR2_7,
GP_2_6_FN, GPSR2_6,
GP_2_5_FN, GPSR2_5,
GP_2_4_FN, GPSR2_4,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
GP_3_12_FN, GPSR3_12,
GP_3_11_FN, GPSR3_11,
GP_3_10_FN, GPSR3_10,
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
GP_3_6_FN, GPSR3_6,
GP_3_5_FN, GPSR3_5,
GP_3_4_FN, GPSR3_4,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
GP_4_14_FN, GPSR4_14,
GP_4_13_FN, GPSR4_13,
GP_4_12_FN, GPSR4_12,
GP_4_11_FN, GPSR4_11,
GP_4_10_FN, GPSR4_10,
GP_4_9_FN, GPSR4_9,
GP_4_8_FN, GPSR4_8,
GP_4_7_FN, GPSR4_7,
GP_4_6_FN, GPSR4_6,
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
GP_5_25_FN, GPSR5_25,
GP_5_24_FN, GPSR5_24,
GP_5_23_FN, GPSR5_23,
GP_5_22_FN, GPSR5_22,
GP_5_21_FN, GPSR5_21,
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
GP_5_17_FN, GPSR5_17,
GP_5_16_FN, GPSR5_16,
GP_5_15_FN, GPSR5_15,
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
GP_5_11_FN, GPSR5_11,
GP_5_10_FN, GPSR5_10,
GP_5_9_FN, GPSR5_9,
GP_5_8_FN, GPSR5_8,
GP_5_7_FN, GPSR5_7,
GP_5_6_FN, GPSR5_6,
GP_5_5_FN, GPSR5_5,
GP_5_4_FN, GPSR5_4,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
GP_6_28_FN, GPSR6_28,
GP_6_27_FN, GPSR6_27,
GP_6_26_FN, GPSR6_26,
GP_6_25_FN, GPSR6_25,
GP_6_24_FN, GPSR6_24,
GP_6_23_FN, GPSR6_23,
GP_6_22_FN, GPSR6_22,
GP_6_21_FN, GPSR6_21,
GP_6_20_FN, GPSR6_20,
GP_6_19_FN, GPSR6_19,
GP_6_18_FN, GPSR6_18,
GP_6_17_FN, GPSR6_17,
GP_6_16_FN, GPSR6_16,
GP_6_15_FN, GPSR6_15,
GP_6_14_FN, GPSR6_14,
GP_6_13_FN, GPSR6_13,
GP_6_12_FN, GPSR6_12,
GP_6_11_FN, GPSR6_11,
GP_6_10_FN, GPSR6_10,
GP_6_9_FN, GPSR6_9,
GP_6_8_FN, GPSR6_8,
GP_6_7_FN, GPSR6_7,
GP_6_6_FN, GPSR6_6,
GP_6_5_FN, GPSR6_5,
GP_6_4_FN, GPSR6_4,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
GROUP(-28, 1, 1, 1, 1),
GROUP(
/* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_19_16
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_19_16
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_19_16
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_19_16
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_19_16
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_19_16
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_19_16
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
GROUP(4, 4, 4, 4, -4, 4, 4, 4),
GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
/* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_19_16
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_19_16
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_19_16
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_19_16
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_19_16
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
IP13_19_16
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
IP14_19_16
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
IP15_19_16
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
IP16_19_16
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
IP17_19_16
IP17_15_12
IP17_11_8
IP17_7_4
IP17_3_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
MOD_SEL0_23
MOD_SEL0_22
MOD_SEL0_21
MOD_SEL0_20
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
/* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
MOD_SEL0_10
MOD_SEL0_9_8
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
MOD_SEL1_25_24
MOD_SEL1_23_22_21
MOD_SEL1_20
MOD_SEL1_19
MOD_SEL1_18_17
MOD_SEL1_16
MOD_SEL1_15_14
MOD_SEL1_13
MOD_SEL1_12
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
/* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
-16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
MOD_SEL2_28_27
MOD_SEL2_26
MOD_SEL2_25_24_23
MOD_SEL2_22
MOD_SEL2_21
MOD_SEL2_20
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
{ RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
{ RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
{ RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
{ RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
{ RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
{ RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
{ RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
{ RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
{ RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
{ RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
{ RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
{ RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
{ RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
{ RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
{ RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
{ RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
{ RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
{ RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
{ RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
{ RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
{ RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
{ RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
{ RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
{ RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
{ RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
{ RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
{ RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
{ RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
{ RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
{ RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
{ RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
{ RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
{ RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
{ RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
{ RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
{ RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
{ RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
{ RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
{ RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
{ RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
} },
{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
{ RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
{ RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
{ RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
{ RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
{ RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
{ RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
{ RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
{ RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
{ RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
{ RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
{ RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
{ RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
{ RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
{ RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
{ RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
{ RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
{ RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
{ RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
{ RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
{ RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
{ RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
{ RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
{ RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
{ RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
{ RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
{ RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
} },
{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
{ RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
{ RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
{ RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
{ RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
{ RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
{ /* sentinel */ }
};
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ }
};
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
bit = (pin & 0x1f) + 12;
return bit;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
[ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
[ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
[ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
[ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
[ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
[ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
[ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
[ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
[ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
[10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
[11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
[12] = RCAR_GP_PIN(1, 0), /* A0 */
[13] = RCAR_GP_PIN(1, 1), /* A1 */
[14] = RCAR_GP_PIN(1, 2), /* A2 */
[15] = RCAR_GP_PIN(1, 3), /* A3 */
[16] = RCAR_GP_PIN(1, 4), /* A4 */
[17] = RCAR_GP_PIN(1, 5), /* A5 */
[18] = RCAR_GP_PIN(1, 6), /* A6 */
[19] = RCAR_GP_PIN(1, 7), /* A7 */
[20] = RCAR_GP_PIN(1, 8), /* A8 */
[21] = RCAR_GP_PIN(1, 9), /* A9 */
[22] = RCAR_GP_PIN(1, 10), /* A10 */
[23] = RCAR_GP_PIN(1, 11), /* A11 */
[24] = RCAR_GP_PIN(1, 12), /* A12 */
[25] = RCAR_GP_PIN(1, 13), /* A13 */
[26] = RCAR_GP_PIN(1, 14), /* A14 */
[27] = RCAR_GP_PIN(1, 15), /* A15 */
[28] = RCAR_GP_PIN(1, 16), /* A16 */
[29] = RCAR_GP_PIN(1, 17), /* A17 */
[30] = RCAR_GP_PIN(1, 18), /* A18 */
[31] = RCAR_GP_PIN(1, 19), /* A19 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
[ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
[ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
[13] = RCAR_GP_PIN(0, 3), /* D3 */
[14] = RCAR_GP_PIN(0, 4), /* D4 */
[15] = RCAR_GP_PIN(0, 5), /* D5 */
[16] = RCAR_GP_PIN(0, 6), /* D6 */
[17] = RCAR_GP_PIN(0, 7), /* D7 */
[18] = RCAR_GP_PIN(0, 8), /* D8 */
[19] = RCAR_GP_PIN(0, 9), /* D9 */
[20] = RCAR_GP_PIN(0, 10), /* D10 */
[21] = RCAR_GP_PIN(0, 11), /* D11 */
[22] = RCAR_GP_PIN(0, 12), /* D12 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
[24] = RCAR_GP_PIN(0, 14), /* D14 */
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = SH_PFC_PIN_NONE,
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[ 2] = PIN_FSCLKST, /* FSCLKST */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
} },
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
[ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
[ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
[ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
[ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
[ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
[ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
[ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
[ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
[ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
[ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
[24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
[25] = RCAR_GP_PIN(5, 13), /* HRX0 */
[26] = RCAR_GP_PIN(5, 14), /* HTX0 */
[27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
[28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
[29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
[30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
[31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
[ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
[ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
[ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
[11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
[12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
[13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
[14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
[15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
[16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
[17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
[18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
[19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
[20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
[21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
[22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
[23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
[24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
[25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
[26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
[27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
[28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
[29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
[30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
[31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
} },
{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
[ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
[ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
[ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
[ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
.name = "r8a774b1_pfc",
.ops = &r8a77965_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
const struct sh_pfc_soc_info r8a77965_pinmux_info = {
.name = "r8a77965_pfc",
.ops = &r8a77965_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
ARRAY_SIZE(pinmux_groups.automotive),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a77965.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
*
* Copyright (C) 2018 Chris Brandt
*/
/*
* This pin controller/gpio combined driver supports Renesas devices of RZ/A2
* family.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include "../core.h"
#include "../pinmux.h"
#define DRIVER_NAME "pinctrl-rza2"
#define RZA2_PINS_PER_PORT 8
#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
/*
* Use 16 lower bits [15:0] for pin identifier
* Use 16 higher bits [31:16] for pin mux function
*/
#define MUX_PIN_ID_MASK GENMASK(15, 0)
#define MUX_FUNC_MASK GENMASK(31, 16)
#define MUX_FUNC_OFFS 16
#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
static const char port_names[] = "0123456789ABCDEFGHJKLM";
struct rza2_pinctrl_priv {
struct device *dev;
void __iomem *base;
struct pinctrl_pin_desc *pins;
struct pinctrl_desc desc;
struct pinctrl_dev *pctl;
struct pinctrl_gpio_range gpio_range;
int npins;
struct mutex mutex; /* serialize adding groups and functions */
};
#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
#define RZA2_PDR_INPUT 0x02
#define RZA2_PDR_OUTPUT 0x03
#define RZA2_PDR_MASK 0x03
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
#define PFS_ISEL BIT(6) /* Interrupt Select */
static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
u8 func)
{
u16 mask16;
u16 reg16;
u8 reg8;
/* Set pin to 'Non-use (Hi-z input protection)' */
reg16 = readw(pfc_base + RZA2_PDR(port));
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
writew(reg16, pfc_base + RZA2_PDR(port));
/* Temporarily switch to GPIO */
reg8 = readb(pfc_base + RZA2_PMR(port));
reg8 &= ~BIT(pin);
writeb(reg8, pfc_base + RZA2_PMR(port));
/* PFS Register Write Protect : OFF */
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
/* Set Pin function (interrupt disabled, ISEL=0) */
writeb(func, pfc_base + RZA2_PFS(port, pin));
/* PFS Register Write Protect : ON */
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
/* Port Mode : Peripheral module pin functions */
reg8 = readb(pfc_base + RZA2_PMR(port));
reg8 |= BIT(pin);
writeb(reg8, pfc_base + RZA2_PMR(port));
}
static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
u8 dir)
{
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u16 mask16;
u16 reg16;
reg16 = readw(pfc_base + RZA2_PDR(port));
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
if (dir)
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
else
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
writew(reg16, pfc_base + RZA2_PDR(port));
}
static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u16 reg16;
reg16 = readw(priv->base + RZA2_PDR(port));
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
if (reg16 == RZA2_PDR_OUTPUT)
return GPIO_LINE_DIRECTION_OUT;
if (reg16 == RZA2_PDR_INPUT)
return GPIO_LINE_DIRECTION_IN;
/*
* This GPIO controller has a default Hi-Z state that is not input or
* output, so force the pin to input now.
*/
rza2_pin_to_gpio(priv->base, offset, 1);
return GPIO_LINE_DIRECTION_IN;
}
static int rza2_chip_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_pin_to_gpio(priv->base, offset, 1);
return 0;
}
static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
}
static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u8 new_value;
new_value = readb(priv->base + RZA2_PODR(port));
if (value)
new_value |= BIT(pin);
else
new_value &= ~BIT(pin);
writeb(new_value, priv->base + RZA2_PODR(port));
}
static int rza2_chip_direction_output(struct gpio_chip *chip,
unsigned int offset, int val)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_chip_set(chip, offset, val);
rza2_pin_to_gpio(priv->base, offset, 0);
return 0;
}
static const char * const rza2_gpio_names[] = {
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
"PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
"PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
"PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
"PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
/* port I does not exist */
"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
"PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
"PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
"PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
};
static struct gpio_chip chip = {
.names = rza2_gpio_names,
.base = -1,
.get_direction = rza2_chip_get_direction,
.direction_input = rza2_chip_direction_input,
.direction_output = rza2_chip_direction_output,
.get = rza2_chip_get,
.set = rza2_chip_set,
};
static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
{
struct device_node *np = priv->dev->of_node;
struct of_phandle_args of_args;
int ret;
chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
chip.parent = priv->dev;
chip.ngpio = priv->npins;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
&of_args);
if (ret) {
dev_err(priv->dev, "Unable to parse gpio-ranges\n");
return ret;
}
if ((of_args.args[0] != 0) ||
(of_args.args[1] != 0) ||
(of_args.args[2] != priv->npins)) {
dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
return -EINVAL;
}
priv->gpio_range.id = 0;
priv->gpio_range.pin_base = priv->gpio_range.base = 0;
priv->gpio_range.npins = priv->npins;
priv->gpio_range.name = chip.label;
priv->gpio_range.gc = &chip;
/* Register our gpio chip with gpiolib */
ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
if (ret)
return ret;
/* Register pin range with pinctrl core */
pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
dev_dbg(priv->dev, "Registered gpio controller\n");
return 0;
}
static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
{
struct pinctrl_pin_desc *pins;
unsigned int i;
int ret;
pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
priv->pins = pins;
priv->desc.pins = pins;
priv->desc.npins = priv->npins;
for (i = 0; i < priv->npins; i++) {
pins[i].number = i;
pins[i].name = rza2_gpio_names[i];
}
ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
&priv->pctl);
if (ret) {
dev_err(priv->dev, "pinctrl registration failed\n");
return ret;
}
ret = pinctrl_enable(priv->pctl);
if (ret) {
dev_err(priv->dev, "pinctrl enable failed\n");
return ret;
}
ret = rza2_gpio_register(priv);
if (ret) {
dev_err(priv->dev, "GPIO registration failed\n");
return ret;
}
return 0;
}
/*
* For each DT node, create a single pin mapping. That pin mapping will only
* contain a single group of pins, and that group of pins will only have a
* single function that can be selected.
*/
static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int *pins, *psel_val;
int i, ret, npins, gsel, fsel;
struct property *of_pins;
const char **pin_fn;
/* Find out how many pins to map */
of_pins = of_find_property(np, "pinmux", NULL);
if (!of_pins) {
dev_info(priv->dev, "Missing pinmux property\n");
return -ENOENT;
}
npins = of_pins->length / sizeof(u32);
pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
GFP_KERNEL);
pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
if (!pins || !psel_val || !pin_fn)
return -ENOMEM;
/* Collect pin locations and mux settings from DT properties */
for (i = 0; i < npins; ++i) {
u32 value;
ret = of_property_read_u32_index(np, "pinmux", i, &value);
if (ret)
return ret;
pins[i] = value & MUX_PIN_ID_MASK;
psel_val[i] = MUX_FUNC(value);
}
mutex_lock(&priv->mutex);
/* Register a single pin group listing all the pins we read from DT */
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
if (gsel < 0) {
ret = gsel;
goto unlock;
}
/*
* Register a single group function where the 'data' is an array PSEL
* register values read from DT.
*/
pin_fn[0] = np->name;
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
psel_val);
if (fsel < 0) {
ret = fsel;
goto remove_group;
}
dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
/* Create map where to retrieve function and mux settings from */
*num_maps = 0;
*map = kzalloc(sizeof(**map), GFP_KERNEL);
if (!*map) {
ret = -ENOMEM;
goto remove_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
*num_maps = 1;
mutex_unlock(&priv->mutex);
return 0;
remove_function:
pinmux_generic_remove_function(pctldev, fsel);
remove_group:
pinctrl_generic_remove_group(pctldev, gsel);
unlock:
mutex_unlock(&priv->mutex);
dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
return ret;
}
static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned int num_maps)
{
kfree(map);
}
static const struct pinctrl_ops rza2_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = rza2_dt_node_to_map,
.dt_free_map = rza2_dt_free_map,
};
static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
unsigned int group)
{
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
unsigned int i, *psel_val;
struct group_desc *grp;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
psel_val = func->data;
for (i = 0; i < grp->num_pins; ++i) {
dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
psel_val[i]);
rza2_set_pin_function(
priv->base,
RZA2_PIN_ID_TO_PORT(grp->pins[i]),
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
psel_val[i]);
}
return 0;
}
static const struct pinmux_ops rza2_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = rza2_set_mux,
.strict = true,
};
static int rza2_pinctrl_probe(struct platform_device *pdev)
{
struct rza2_pinctrl_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
mutex_init(&priv->mutex);
platform_set_drvdata(pdev, priv);
priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
RZA2_PINS_PER_PORT;
priv->desc.name = DRIVER_NAME;
priv->desc.pctlops = &rza2_pinctrl_ops;
priv->desc.pmxops = &rza2_pinmux_ops;
priv->desc.owner = THIS_MODULE;
ret = rza2_pinctrl_register(priv);
if (ret)
return ret;
dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
return 0;
}
static const struct of_device_id rza2_pinctrl_of_match[] = {
{ .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
{ /* sentinel */ }
};
static struct platform_driver rza2_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = rza2_pinctrl_of_match,
},
.probe = rza2_pinctrl_probe,
};
static int __init rza2_pinctrl_init(void)
{
return platform_driver_register(&rza2_pinctrl_driver);
}
core_initcall(rza2_pinctrl_init);
MODULE_AUTHOR("Chris Brandt <[email protected]>");
MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
|
linux-master
|
drivers/pinctrl/renesas/pinctrl-rza2.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A779A0 processor support - PFC hardware block.
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
/* GPSR0 */
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
#define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
#define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
#define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
#define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
#define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
#define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
/* GPSR1 */
#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
#define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
#define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
#define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
#define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
#define GPSR1_16 F_(HRX0, IP2SR1_3_0)
#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
#define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
#define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
#define GPSR1_12 F_(HTX0, IP1SR1_19_16)
#define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
#define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
#define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
#define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
#define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
#define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
#define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
#define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
#define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
#define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
#define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
/* GPSR2 */
#define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
#define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
#define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
#define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
#define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
#define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
#define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
#define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
#define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
#define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
/* GPSR3 */
#define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
#define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
#define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
#define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
#define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
#define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
#define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
#define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
#define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
#define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
#define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
#define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
#define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
#define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
#define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
#define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
#define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
#define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
#define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
#define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
#define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
#define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
#define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
#define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
#define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
#define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
#define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
#define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
#define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
/* GPSR4 */
#define GPSR4_24 F_(AVS1, IP3SR4_3_0)
#define GPSR4_23 F_(AVS0, IP2SR4_31_28)
#define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)
#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
#define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)
#define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)
#define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)
#define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)
#define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)
#define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)
#define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)
#define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)
#define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)
#define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)
#define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)
#define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)
#define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)
#define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)
#define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)
#define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)
#define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)
#define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)
#define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)
#define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)
#define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)
/* GPSR 5 */
#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
/* GPSR 6 */
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
/* GPSR7 */
#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
/* GPSR8 */
#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
#define GPSR8_11 F_(SDA5, IP1SR8_15_12)
#define GPSR8_10 F_(SCL5, IP1SR8_11_8)
#define GPSR8_9 F_(SDA4, IP1SR8_7_4)
#define GPSR8_8 F_(SCL4, IP1SR8_3_0)
#define GPSR8_7 F_(SDA3, IP0SR8_31_28)
#define GPSR8_6 F_(SCL3, IP0SR8_27_24)
#define GPSR8_5 F_(SDA2, IP0SR8_23_20)
#define GPSR8_4 F_(SCL2, IP0SR8_19_16)
#define GPSR8_3 F_(SDA1, IP0SR8_15_12)
#define GPSR8_2 F_(SCL1, IP0SR8_11_8)
#define GPSR8_1 F_(SDA0, IP0SR8_7_4)
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR3 */
/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR4 */
/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR5 */
/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR6 */
/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR7 */
/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR8 */
/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
GPSR3_29 \
GPSR1_28 GPSR3_28 \
GPSR1_27 GPSR3_27 \
GPSR1_26 GPSR3_26 \
GPSR1_25 GPSR3_25 \
GPSR1_24 GPSR3_24 GPSR4_24 \
GPSR1_23 GPSR3_23 GPSR4_23 \
GPSR1_22 GPSR3_22 GPSR4_22 \
GPSR1_21 GPSR3_21 GPSR4_21 \
GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
#define PINMUX_IPSR \
\
FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
\
FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
\
FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
\
FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
\
FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
\
FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
\
FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
\
FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
\
FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
FM(IP0SR8_27_24) IP0SR8_27_24 \
FM(IP0SR8_31_28) IP0SR8_31_28
/* MOD_SEL8 */ /* 0 */ /* 1 */
#define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
#define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
#define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
#define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
#define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
#define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
#define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
#define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
#define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
#define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
#define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
#define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
#define PINMUX_MOD_SELS \
\
MOD_SEL8_11 \
MOD_SEL8_10 \
MOD_SEL8_9 \
MOD_SEL8_8 \
MOD_SEL8_7 \
MOD_SEL8_6 \
MOD_SEL8_5 \
MOD_SEL8_4 \
MOD_SEL8_3 \
MOD_SEL8_2 \
MOD_SEL8_1 \
MOD_SEL8_0
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
/* IP1SR0 */
PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
/* IP2SR0 */
PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
/* IP1SR1 */
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X),
PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X),
PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
/* IP2SR1 */
PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
/* IP3SR1 */
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
/* IP0SR2 */
PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
/* IP1SR2 */
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X),
PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X),
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
/* IP2SR2 */
PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
/* IP0SR3 */
PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
/* IP1SR3 */
PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
/* IP2SR3 */
PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
/* IP3SR3 */
PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
/* IP0SR4 */
PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),
PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),
PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),
PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),
PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),
/* IP1SR4 */
PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),
PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),
PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),
PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),
PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),
PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),
PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),
PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),
/* IP2SR4 */
PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),
PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),
PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),
PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),
PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),
PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),
PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
/* IP3SR4 */
PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
/* IP0SR5 */
PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
/* IP1SR5 */
PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
/* IP2SR5 */
PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
/* IP0SR6 */
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
/* IP0SR7 */
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
/* IP1SR7 */
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
/* IP2SR7 */
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
/* IP0SR8 */
PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
/* IP1SR8 */
PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ----------------------------------------- */
static const unsigned int audio_clkin_pins[] = {
/* CLK IN */
RCAR_GP_PIN(1, 22),
};
static const unsigned int audio_clkin_mux[] = {
AUDIO_CLKIN_MARK,
};
static const unsigned int audio_clkout_pins[] = {
/* CLK OUT */
RCAR_GP_PIN(1, 21),
};
static const unsigned int audio_clkout_mux[] = {
AUDIO_CLKOUT_MARK,
};
/* - AVB0 ------------------------------------------------ */
static const unsigned int avb0_link_pins[] = {
/* AVB0_LINK */
RCAR_GP_PIN(7, 4),
};
static const unsigned int avb0_link_mux[] = {
AVB0_LINK_MARK,
};
static const unsigned int avb0_magic_pins[] = {
/* AVB0_MAGIC */
RCAR_GP_PIN(7, 10),
};
static const unsigned int avb0_magic_mux[] = {
AVB0_MAGIC_MARK,
};
static const unsigned int avb0_phy_int_pins[] = {
/* AVB0_PHY_INT */
RCAR_GP_PIN(7, 5),
};
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
};
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_rgmii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
*/
RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
};
static const unsigned int avb0_rgmii_mux[] = {
AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
AVB0_TD0_MARK, AVB0_TD1_MARK,
AVB0_TD2_MARK, AVB0_TD3_MARK,
AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
AVB0_RD0_MARK, AVB0_RD1_MARK,
AVB0_RD2_MARK, AVB0_RD3_MARK,
};
static const unsigned int avb0_txcrefclk_pins[] = {
/* AVB0_TXCREFCLK */
RCAR_GP_PIN(7, 9),
};
static const unsigned int avb0_txcrefclk_mux[] = {
AVB0_TXCREFCLK_MARK,
};
static const unsigned int avb0_avtp_pps_pins[] = {
/* AVB0_AVTP_PPS */
RCAR_GP_PIN(7, 0),
};
static const unsigned int avb0_avtp_pps_mux[] = {
AVB0_AVTP_PPS_MARK,
};
static const unsigned int avb0_avtp_capture_pins[] = {
/* AVB0_AVTP_CAPTURE */
RCAR_GP_PIN(7, 1),
};
static const unsigned int avb0_avtp_capture_mux[] = {
AVB0_AVTP_CAPTURE_MARK,
};
static const unsigned int avb0_avtp_match_pins[] = {
/* AVB0_AVTP_MATCH */
RCAR_GP_PIN(7, 2),
};
static const unsigned int avb0_avtp_match_mux[] = {
AVB0_AVTP_MATCH_MARK,
};
/* - AVB1 ------------------------------------------------ */
static const unsigned int avb1_link_pins[] = {
/* AVB1_LINK */
RCAR_GP_PIN(6, 4),
};
static const unsigned int avb1_link_mux[] = {
AVB1_LINK_MARK,
};
static const unsigned int avb1_magic_pins[] = {
/* AVB1_MAGIC */
RCAR_GP_PIN(6, 1),
};
static const unsigned int avb1_magic_mux[] = {
AVB1_MAGIC_MARK,
};
static const unsigned int avb1_phy_int_pins[] = {
/* AVB1_PHY_INT */
RCAR_GP_PIN(6, 3),
};
static const unsigned int avb1_phy_int_mux[] = {
AVB1_PHY_INT_MARK,
};
static const unsigned int avb1_mdio_pins[] = {
/* AVB1_MDC, AVB1_MDIO */
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
};
static const unsigned int avb1_mdio_mux[] = {
AVB1_MDC_MARK, AVB1_MDIO_MARK,
};
static const unsigned int avb1_rgmii_pins[] = {
/*
* AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
* AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
*/
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
};
static const unsigned int avb1_rgmii_mux[] = {
AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
AVB1_TD0_MARK, AVB1_TD1_MARK,
AVB1_TD2_MARK, AVB1_TD3_MARK,
AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
AVB1_RD0_MARK, AVB1_RD1_MARK,
AVB1_RD2_MARK, AVB1_RD3_MARK,
};
static const unsigned int avb1_txcrefclk_pins[] = {
/* AVB1_TXCREFCLK */
RCAR_GP_PIN(6, 20),
};
static const unsigned int avb1_txcrefclk_mux[] = {
AVB1_TXCREFCLK_MARK,
};
static const unsigned int avb1_avtp_pps_pins[] = {
/* AVB1_AVTP_PPS */
RCAR_GP_PIN(6, 10),
};
static const unsigned int avb1_avtp_pps_mux[] = {
AVB1_AVTP_PPS_MARK,
};
static const unsigned int avb1_avtp_capture_pins[] = {
/* AVB1_AVTP_CAPTURE */
RCAR_GP_PIN(6, 11),
};
static const unsigned int avb1_avtp_capture_mux[] = {
AVB1_AVTP_CAPTURE_MARK,
};
static const unsigned int avb1_avtp_match_pins[] = {
/* AVB1_AVTP_MATCH */
RCAR_GP_PIN(6, 5),
};
static const unsigned int avb1_avtp_match_mux[] = {
AVB1_AVTP_MATCH_MARK,
};
/* - AVB2 ------------------------------------------------ */
static const unsigned int avb2_link_pins[] = {
/* AVB2_LINK */
RCAR_GP_PIN(5, 3),
};
static const unsigned int avb2_link_mux[] = {
AVB2_LINK_MARK,
};
static const unsigned int avb2_magic_pins[] = {
/* AVB2_MAGIC */
RCAR_GP_PIN(5, 5),
};
static const unsigned int avb2_magic_mux[] = {
AVB2_MAGIC_MARK,
};
static const unsigned int avb2_phy_int_pins[] = {
/* AVB2_PHY_INT */
RCAR_GP_PIN(5, 4),
};
static const unsigned int avb2_phy_int_mux[] = {
AVB2_PHY_INT_MARK,
};
static const unsigned int avb2_mdio_pins[] = {
/* AVB2_MDC, AVB2_MDIO */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
};
static const unsigned int avb2_mdio_mux[] = {
AVB2_MDC_MARK, AVB2_MDIO_MARK,
};
static const unsigned int avb2_rgmii_pins[] = {
/*
* AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
* AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
*/
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
};
static const unsigned int avb2_rgmii_mux[] = {
AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
AVB2_TD0_MARK, AVB2_TD1_MARK,
AVB2_TD2_MARK, AVB2_TD3_MARK,
AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
AVB2_RD0_MARK, AVB2_RD1_MARK,
AVB2_RD2_MARK, AVB2_RD3_MARK,
};
static const unsigned int avb2_txcrefclk_pins[] = {
/* AVB2_TXCREFCLK */
RCAR_GP_PIN(5, 7),
};
static const unsigned int avb2_txcrefclk_mux[] = {
AVB2_TXCREFCLK_MARK,
};
static const unsigned int avb2_avtp_pps_pins[] = {
/* AVB2_AVTP_PPS */
RCAR_GP_PIN(5, 0),
};
static const unsigned int avb2_avtp_pps_mux[] = {
AVB2_AVTP_PPS_MARK,
};
static const unsigned int avb2_avtp_capture_pins[] = {
/* AVB2_AVTP_CAPTURE */
RCAR_GP_PIN(5, 1),
};
static const unsigned int avb2_avtp_capture_mux[] = {
AVB2_AVTP_CAPTURE_MARK,
};
static const unsigned int avb2_avtp_match_pins[] = {
/* AVB2_AVTP_MATCH */
RCAR_GP_PIN(5, 2),
};
static const unsigned int avb2_avtp_match_mux[] = {
AVB2_AVTP_MATCH_MARK,
};
/* - CANFD0 ----------------------------------------------------------------- */
static const unsigned int canfd0_data_pins[] = {
/* CANFD0_TX, CANFD0_RX */
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
};
static const unsigned int canfd0_data_mux[] = {
CANFD0_TX_MARK, CANFD0_RX_MARK,
};
/* - CANFD1 ----------------------------------------------------------------- */
static const unsigned int canfd1_data_pins[] = {
/* CANFD1_TX, CANFD1_RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - CANFD2 ----------------------------------------------------------------- */
static const unsigned int canfd2_data_pins[] = {
/* CANFD2_TX, CANFD2_RX */
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
};
static const unsigned int canfd2_data_mux[] = {
CANFD2_TX_MARK, CANFD2_RX_MARK,
};
/* - CANFD3 ----------------------------------------------------------------- */
static const unsigned int canfd3_data_pins[] = {
/* CANFD3_TX, CANFD3_RX */
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
};
static const unsigned int canfd3_data_mux[] = {
CANFD3_TX_MARK, CANFD3_RX_MARK,
};
/* - CANFD4 ----------------------------------------------------------------- */
static const unsigned int canfd4_data_pins[] = {
/* CANFD4_TX, CANFD4_RX */
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
};
static const unsigned int canfd4_data_mux[] = {
CANFD4_TX_MARK, CANFD4_RX_MARK,
};
/* - CANFD5 ----------------------------------------------------------------- */
static const unsigned int canfd5_data_pins[] = {
/* CANFD5_TX, CANFD5_RX */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
};
static const unsigned int canfd5_data_mux[] = {
CANFD5_TX_MARK, CANFD5_RX_MARK,
};
/* - CANFD5_B ----------------------------------------------------------------- */
static const unsigned int canfd5_data_b_pins[] = {
/* CANFD5_TX_B, CANFD5_RX_B */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
};
static const unsigned int canfd5_data_b_mux[] = {
CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
};
/* - CANFD6 ----------------------------------------------------------------- */
static const unsigned int canfd6_data_pins[] = {
/* CANFD6_TX, CANFD6_RX */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int canfd6_data_mux[] = {
CANFD6_TX_MARK, CANFD6_RX_MARK,
};
/* - CANFD7 ----------------------------------------------------------------- */
static const unsigned int canfd7_data_pins[] = {
/* CANFD7_TX, CANFD7_RX */
RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
};
static const unsigned int canfd7_data_mux[] = {
CANFD7_TX_MARK, CANFD7_RX_MARK,
};
/* - CANFD Clock ------------------------------------------------------------ */
static const unsigned int can_clk_pins[] = {
/* CAN_CLK */
RCAR_GP_PIN(2, 9),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* HRX0, HTX0 */
RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
};
static const unsigned int hscif0_data_mux[] = {
HRX0_MARK, HTX0_MARK,
};
static const unsigned int hscif0_clk_pins[] = {
/* HSCK0 */
RCAR_GP_PIN(1, 15),
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK,
};
static const unsigned int hscif0_ctrl_pins[] = {
/* HRTS0_N, HCTS0_N */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
};
static const unsigned int hscif0_ctrl_mux[] = {
HRTS0_N_MARK, HCTS0_N_MARK,
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_pins[] = {
/* HRX1, HTX1 */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
static const unsigned int hscif1_data_mux[] = {
HRX1_MARK, HTX1_MARK,
};
static const unsigned int hscif1_clk_pins[] = {
/* HSCK1 */
RCAR_GP_PIN(0, 18),
};
static const unsigned int hscif1_clk_mux[] = {
HSCK1_MARK,
};
static const unsigned int hscif1_ctrl_pins[] = {
/* HRTS1_N, HCTS1_N */
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
};
static const unsigned int hscif1_ctrl_mux[] = {
HRTS1_N_MARK, HCTS1_N_MARK,
};
/* - HSCIF1_X---------------------------------------------------------------- */
static const unsigned int hscif1_data_x_pins[] = {
/* HRX1_X, HTX1_X */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
};
static const unsigned int hscif1_data_x_mux[] = {
HRX1_X_MARK, HTX1_X_MARK,
};
static const unsigned int hscif1_clk_x_pins[] = {
/* HSCK1_X */
RCAR_GP_PIN(1, 10),
};
static const unsigned int hscif1_clk_x_mux[] = {
HSCK1_X_MARK,
};
static const unsigned int hscif1_ctrl_x_pins[] = {
/* HRTS1_N_X, HCTS1_N_X */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
};
static const unsigned int hscif1_ctrl_x_mux[] = {
HRTS1_N_X_MARK, HCTS1_N_X_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_pins[] = {
/* HRX2, HTX2 */
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
};
static const unsigned int hscif2_data_mux[] = {
HRX2_MARK, HTX2_MARK,
};
static const unsigned int hscif2_clk_pins[] = {
/* HSCK2 */
RCAR_GP_PIN(8, 13),
};
static const unsigned int hscif2_clk_mux[] = {
HSCK2_MARK,
};
static const unsigned int hscif2_ctrl_pins[] = {
/* HRTS2_N, HCTS2_N */
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
};
static const unsigned int hscif2_ctrl_mux[] = {
HRTS2_N_MARK, HCTS2_N_MARK,
};
/* - HSCIF3 ----------------------------------------------------------------- */
static const unsigned int hscif3_data_pins[] = {
/* HRX3, HTX3 */
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
};
static const unsigned int hscif3_data_mux[] = {
HRX3_MARK, HTX3_MARK,
};
static const unsigned int hscif3_clk_pins[] = {
/* HSCK3 */
RCAR_GP_PIN(1, 25),
};
static const unsigned int hscif3_clk_mux[] = {
HSCK3_MARK,
};
static const unsigned int hscif3_ctrl_pins[] = {
/* HRTS3_N, HCTS3_N */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
};
static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
/* - HSCIF3_A ----------------------------------------------------------------- */
static const unsigned int hscif3_data_a_pins[] = {
/* HRX3_A, HTX3_A */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
};
static const unsigned int hscif3_data_a_mux[] = {
HRX3_A_MARK, HTX3_A_MARK,
};
static const unsigned int hscif3_clk_a_pins[] = {
/* HSCK3_A */
RCAR_GP_PIN(1, 3),
};
static const unsigned int hscif3_clk_a_mux[] = {
HSCK3_A_MARK,
};
static const unsigned int hscif3_ctrl_a_pins[] = {
/* HRTS3_N_A, HCTS3_N_A */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
};
static const unsigned int hscif3_ctrl_a_mux[] = {
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
};
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SDA0, SCL0 */
RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
};
static const unsigned int i2c0_mux[] = {
SDA0_MARK, SCL0_MARK,
};
/* - I2C1 ------------------------------------------------------------------- */
static const unsigned int i2c1_pins[] = {
/* SDA1, SCL1 */
RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
};
static const unsigned int i2c1_mux[] = {
SDA1_MARK, SCL1_MARK,
};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_pins[] = {
/* SDA2, SCL2 */
RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
};
static const unsigned int i2c2_mux[] = {
SDA2_MARK, SCL2_MARK,
};
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_pins[] = {
/* SDA3, SCL3 */
RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
};
static const unsigned int i2c3_mux[] = {
SDA3_MARK, SCL3_MARK,
};
/* - I2C4 ------------------------------------------------------------------- */
static const unsigned int i2c4_pins[] = {
/* SDA4, SCL4 */
RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
};
static const unsigned int i2c4_mux[] = {
SDA4_MARK, SCL4_MARK,
};
/* - I2C5 ------------------------------------------------------------------- */
static const unsigned int i2c5_pins[] = {
/* SDA5, SCL5 */
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
};
static const unsigned int i2c5_mux[] = {
SDA5_MARK, SCL5_MARK,
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* MMC_SD_D[0:3], MMC_D[4:7] */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
};
static const unsigned int mmc_data_mux[] = {
MMC_SD_D0_MARK, MMC_SD_D1_MARK,
MMC_SD_D2_MARK, MMC_SD_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
MMC_D6_MARK, MMC_D7_MARK,
};
static const unsigned int mmc_ctrl_pins[] = {
/* MMC_SD_CLK, MMC_SD_CMD */
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
};
static const unsigned int mmc_ctrl_mux[] = {
MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
};
static const unsigned int mmc_cd_pins[] = {
/* SD_CD */
RCAR_GP_PIN(3, 11),
};
static const unsigned int mmc_cd_mux[] = {
SD_CD_MARK,
};
static const unsigned int mmc_wp_pins[] = {
/* SD_WP */
RCAR_GP_PIN(3, 12),
};
static const unsigned int mmc_wp_mux[] = {
SD_WP_MARK,
};
static const unsigned int mmc_ds_pins[] = {
/* MMC_DS */
RCAR_GP_PIN(3, 4),
};
static const unsigned int mmc_ds_mux[] = {
MMC_DS_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* MSIOF0_SCK */
RCAR_GP_PIN(1, 10),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* MSIOF0_SYNC */
RCAR_GP_PIN(1, 8),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* MSIOF0_SS1 */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* MSIOF0_SS2 */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* MSIOF0_TXD */
RCAR_GP_PIN(1, 9),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* MSIOF0_RXD */
RCAR_GP_PIN(1, 11),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* MSIOF1_SCK */
RCAR_GP_PIN(1, 3),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* MSIOF1_SYNC */
RCAR_GP_PIN(1, 2),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* MSIOF1_SS1 */
RCAR_GP_PIN(1, 1),
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* MSIOF1_SS2 */
RCAR_GP_PIN(1, 0),
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* MSIOF1_TXD */
RCAR_GP_PIN(1, 4),
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* MSIOF1_RXD */
RCAR_GP_PIN(1, 5),
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_pins[] = {
/* MSIOF2_SCK */
RCAR_GP_PIN(0, 17),
};
static const unsigned int msiof2_clk_mux[] = {
MSIOF2_SCK_MARK,
};
static const unsigned int msiof2_sync_pins[] = {
/* MSIOF2_SYNC */
RCAR_GP_PIN(0, 15),
};
static const unsigned int msiof2_sync_mux[] = {
MSIOF2_SYNC_MARK,
};
static const unsigned int msiof2_ss1_pins[] = {
/* MSIOF2_SS1 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int msiof2_ss1_mux[] = {
MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_pins[] = {
/* MSIOF2_SS2 */
RCAR_GP_PIN(0, 13),
};
static const unsigned int msiof2_ss2_mux[] = {
MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* MSIOF2_TXD */
RCAR_GP_PIN(0, 16),
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_rxd_pins[] = {
/* MSIOF2_RXD */
RCAR_GP_PIN(0, 18),
};
static const unsigned int msiof2_rxd_mux[] = {
MSIOF2_RXD_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_pins[] = {
/* MSIOF3_SCK */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof3_clk_mux[] = {
MSIOF3_SCK_MARK,
};
static const unsigned int msiof3_sync_pins[] = {
/* MSIOF3_SYNC */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof3_sync_mux[] = {
MSIOF3_SYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* MSIOF3_SS1 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof3_ss1_mux[] = {
MSIOF3_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* MSIOF3_SS2 */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof3_ss2_mux[] = {
MSIOF3_SS2_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* MSIOF3_TXD */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof3_txd_mux[] = {
MSIOF3_TXD_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* MSIOF3_RXD */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof3_rxd_mux[] = {
MSIOF3_RXD_MARK,
};
/* - MSIOF4 ----------------------------------------------------------------- */
static const unsigned int msiof4_clk_pins[] = {
/* MSIOF4_SCK */
RCAR_GP_PIN(1, 25),
};
static const unsigned int msiof4_clk_mux[] = {
MSIOF4_SCK_MARK,
};
static const unsigned int msiof4_sync_pins[] = {
/* MSIOF4_SYNC */
RCAR_GP_PIN(1, 28),
};
static const unsigned int msiof4_sync_mux[] = {
MSIOF4_SYNC_MARK,
};
static const unsigned int msiof4_ss1_pins[] = {
/* MSIOF4_SS1 */
RCAR_GP_PIN(1, 23),
};
static const unsigned int msiof4_ss1_mux[] = {
MSIOF4_SS1_MARK,
};
static const unsigned int msiof4_ss2_pins[] = {
/* MSIOF4_SS2 */
RCAR_GP_PIN(1, 24),
};
static const unsigned int msiof4_ss2_mux[] = {
MSIOF4_SS2_MARK,
};
static const unsigned int msiof4_txd_pins[] = {
/* MSIOF4_TXD */
RCAR_GP_PIN(1, 26),
};
static const unsigned int msiof4_txd_mux[] = {
MSIOF4_TXD_MARK,
};
static const unsigned int msiof4_rxd_pins[] = {
/* MSIOF4_RXD */
RCAR_GP_PIN(1, 27),
};
static const unsigned int msiof4_rxd_mux[] = {
MSIOF4_RXD_MARK,
};
/* - MSIOF5 ----------------------------------------------------------------- */
static const unsigned int msiof5_clk_pins[] = {
/* MSIOF5_SCK */
RCAR_GP_PIN(0, 11),
};
static const unsigned int msiof5_clk_mux[] = {
MSIOF5_SCK_MARK,
};
static const unsigned int msiof5_sync_pins[] = {
/* MSIOF5_SYNC */
RCAR_GP_PIN(0, 9),
};
static const unsigned int msiof5_sync_mux[] = {
MSIOF5_SYNC_MARK,
};
static const unsigned int msiof5_ss1_pins[] = {
/* MSIOF5_SS1 */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof5_ss1_mux[] = {
MSIOF5_SS1_MARK,
};
static const unsigned int msiof5_ss2_pins[] = {
/* MSIOF5_SS2 */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof5_ss2_mux[] = {
MSIOF5_SS2_MARK,
};
static const unsigned int msiof5_txd_pins[] = {
/* MSIOF5_TXD */
RCAR_GP_PIN(0, 10),
};
static const unsigned int msiof5_txd_mux[] = {
MSIOF5_TXD_MARK,
};
static const unsigned int msiof5_rxd_pins[] = {
/* MSIOF5_RXD */
RCAR_GP_PIN(0, 12),
};
static const unsigned int msiof5_rxd_mux[] = {
MSIOF5_RXD_MARK,
};
/* - PCIE ------------------------------------------------------------------- */
static const unsigned int pcie0_clkreq_n_pins[] = {
/* PCIE0_CLKREQ_N */
RCAR_GP_PIN(4, 21),
};
static const unsigned int pcie0_clkreq_n_mux[] = {
PCIE0_CLKREQ_N_MARK,
};
static const unsigned int pcie1_clkreq_n_pins[] = {
/* PCIE1_CLKREQ_N */
RCAR_GP_PIN(4, 22),
};
static const unsigned int pcie1_clkreq_n_mux[] = {
PCIE1_CLKREQ_N_MARK,
};
/* - PWM0_A ------------------------------------------------------------------- */
static const unsigned int pwm0_a_pins[] = {
/* PWM0_A */
RCAR_GP_PIN(1, 15),
};
static const unsigned int pwm0_a_mux[] = {
PWM0_A_MARK,
};
/* - PWM1_A ------------------------------------------------------------------- */
static const unsigned int pwm1_a_pins[] = {
/* PWM1_A */
RCAR_GP_PIN(3, 13),
};
static const unsigned int pwm1_a_mux[] = {
PWM1_A_MARK,
};
/* - PWM1_B ------------------------------------------------------------------- */
static const unsigned int pwm1_b_pins[] = {
/* PWM1_B */
RCAR_GP_PIN(2, 13),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
/* - PWM2_B ------------------------------------------------------------------- */
static const unsigned int pwm2_b_pins[] = {
/* PWM2_B */
RCAR_GP_PIN(2, 14),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
/* - PWM3_A ------------------------------------------------------------------- */
static const unsigned int pwm3_a_pins[] = {
/* PWM3_A */
RCAR_GP_PIN(1, 22),
};
static const unsigned int pwm3_a_mux[] = {
PWM3_A_MARK,
};
/* - PWM3_B ------------------------------------------------------------------- */
static const unsigned int pwm3_b_pins[] = {
/* PWM3_B */
RCAR_GP_PIN(2, 15),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
/* - PWM4 ------------------------------------------------------------------- */
static const unsigned int pwm4_pins[] = {
/* PWM4 */
RCAR_GP_PIN(2, 16),
};
static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
/* - PWM5 ------------------------------------------------------------------- */
static const unsigned int pwm5_pins[] = {
/* PWM5 */
RCAR_GP_PIN(2, 17),
};
static const unsigned int pwm5_mux[] = {
PWM5_MARK,
};
/* - PWM6 ------------------------------------------------------------------- */
static const unsigned int pwm6_pins[] = {
/* PWM6 */
RCAR_GP_PIN(2, 18),
};
static const unsigned int pwm6_mux[] = {
PWM6_MARK,
};
/* - PWM7 ------------------------------------------------------------------- */
static const unsigned int pwm7_pins[] = {
/* PWM7 */
RCAR_GP_PIN(2, 19),
};
static const unsigned int pwm7_mux[] = {
PWM7_MARK,
};
/* - PWM8_A ------------------------------------------------------------------- */
static const unsigned int pwm8_a_pins[] = {
/* PWM8_A */
RCAR_GP_PIN(1, 13),
};
static const unsigned int pwm8_a_mux[] = {
PWM8_A_MARK,
};
/* - PWM9_A ------------------------------------------------------------------- */
static const unsigned int pwm9_a_pins[] = {
/* PWM9_A */
RCAR_GP_PIN(1, 14),
};
static const unsigned int pwm9_a_mux[] = {
PWM9_A_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
};
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
};
static const unsigned int scif0_data_mux[] = {
RX0_MARK, TX0_MARK,
};
static const unsigned int scif0_clk_pins[] = {
/* SCK0 */
RCAR_GP_PIN(1, 15),
};
static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS0_N, CTS0_N */
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_pins[] = {
/* RX1, TX1 */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
static const unsigned int scif1_data_mux[] = {
RX1_MARK, TX1_MARK,
};
static const unsigned int scif1_clk_pins[] = {
/* SCK1 */
RCAR_GP_PIN(0, 18),
};
static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS1_N, CTS1_N */
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF1_X ------------------------------------------------------------------ */
static const unsigned int scif1_data_x_pins[] = {
/* RX1_X, TX1_X */
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
};
static const unsigned int scif1_data_x_mux[] = {
RX1_X_MARK, TX1_X_MARK,
};
static const unsigned int scif1_clk_x_pins[] = {
/* SCK1_X */
RCAR_GP_PIN(1, 10),
};
static const unsigned int scif1_clk_x_mux[] = {
SCK1_X_MARK,
};
static const unsigned int scif1_ctrl_x_pins[] = {
/* RTS1_N_X, CTS1_N_X */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
};
static const unsigned int scif1_ctrl_x_mux[] = {
RTS1_N_X_MARK, CTS1_N_X_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_pins[] = {
/* RX3, TX3 */
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int scif3_data_mux[] = {
RX3_MARK, TX3_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK3 */
RCAR_GP_PIN(1, 4),
};
static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
static const unsigned int scif3_ctrl_pins[] = {
/* RTS3_N, CTS3_N */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF3_A ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX3_A, TX3_A */
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
};
static const unsigned int scif3_data_a_mux[] = {
RX3_A_MARK, TX3_A_MARK,
};
static const unsigned int scif3_clk_a_pins[] = {
/* SCK3_A */
RCAR_GP_PIN(1, 24),
};
static const unsigned int scif3_clk_a_mux[] = {
SCK3_A_MARK,
};
static const unsigned int scif3_ctrl_a_pins[] = {
/* RTS3_N_A, CTS3_N_A */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int scif3_ctrl_a_mux[] = {
RTS3_N_A_MARK, CTS3_N_A_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_pins[] = {
/* RX4, TX4 */
RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
};
static const unsigned int scif4_data_mux[] = {
RX4_MARK, TX4_MARK,
};
static const unsigned int scif4_clk_pins[] = {
/* SCK4 */
RCAR_GP_PIN(8, 8),
};
static const unsigned int scif4_clk_mux[] = {
SCK4_MARK,
};
static const unsigned int scif4_ctrl_pins[] = {
/* RTS4_N, CTS4_N */
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
};
static const unsigned int scif4_ctrl_mux[] = {
RTS4_N_MARK, CTS4_N_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(1, 17),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
/* - SSI ------------------------------------------------- */
static const unsigned int ssi_data_pins[] = {
/* SSI_SD */
RCAR_GP_PIN(1, 20),
};
static const unsigned int ssi_data_mux[] = {
SSI_SD_MARK,
};
static const unsigned int ssi_ctrl_pins[] = {
/* SSI_SCK, SSI_WS */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
};
static const unsigned int ssi_ctrl_mux[] = {
SSI_SCK_MARK, SSI_WS_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(2, 8),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(2, 7),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(2, 12),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(2, 13),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - TPU_A ------------------------------------------------------------------- */
static const unsigned int tpu_to0_a_pins[] = {
/* TPU0TO0_A */
RCAR_GP_PIN(1, 25),
};
static const unsigned int tpu_to0_a_mux[] = {
TPU0TO0_A_MARK,
};
static const unsigned int tpu_to1_a_pins[] = {
/* TPU0TO1_A */
RCAR_GP_PIN(1, 26),
};
static const unsigned int tpu_to1_a_mux[] = {
TPU0TO1_A_MARK,
};
static const unsigned int tpu_to2_a_pins[] = {
/* TPU0TO2_A */
RCAR_GP_PIN(2, 0),
};
static const unsigned int tpu_to2_a_mux[] = {
TPU0TO2_A_MARK,
};
static const unsigned int tpu_to3_a_pins[] = {
/* TPU0TO3_A */
RCAR_GP_PIN(2, 1),
};
static const unsigned int tpu_to3_a_mux[] = {
TPU0TO3_A_MARK,
};
/* - TSN0 ------------------------------------------------ */
static const unsigned int tsn0_link_pins[] = {
/* TSN0_LINK */
RCAR_GP_PIN(4, 4),
};
static const unsigned int tsn0_link_mux[] = {
TSN0_LINK_MARK,
};
static const unsigned int tsn0_phy_int_pins[] = {
/* TSN0_PHY_INT */
RCAR_GP_PIN(4, 3),
};
static const unsigned int tsn0_phy_int_mux[] = {
TSN0_PHY_INT_MARK,
};
static const unsigned int tsn0_mdio_pins[] = {
/* TSN0_MDC, TSN0_MDIO */
RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
};
static const unsigned int tsn0_mdio_mux[] = {
TSN0_MDC_MARK, TSN0_MDIO_MARK,
};
static const unsigned int tsn0_rgmii_pins[] = {
/*
* TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
* TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
*/
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
};
static const unsigned int tsn0_rgmii_mux[] = {
TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
TSN0_TD0_MARK, TSN0_TD1_MARK,
TSN0_TD2_MARK, TSN0_TD3_MARK,
TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
TSN0_RD0_MARK, TSN0_RD1_MARK,
TSN0_RD2_MARK, TSN0_RD3_MARK,
};
static const unsigned int tsn0_txcrefclk_pins[] = {
/* TSN0_TXCREFCLK */
RCAR_GP_PIN(4, 20),
};
static const unsigned int tsn0_txcrefclk_mux[] = {
TSN0_TXCREFCLK_MARK,
};
static const unsigned int tsn0_avtp_pps_pins[] = {
/* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
};
static const unsigned int tsn0_avtp_pps_mux[] = {
TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
};
static const unsigned int tsn0_avtp_capture_pins[] = {
/* TSN0_AVTP_CAPTURE */
RCAR_GP_PIN(4, 6),
};
static const unsigned int tsn0_avtp_capture_mux[] = {
TSN0_AVTP_CAPTURE_MARK,
};
static const unsigned int tsn0_avtp_match_pins[] = {
/* TSN0_AVTP_MATCH */
RCAR_GP_PIN(4, 5),
};
static const unsigned int tsn0_avtp_match_mux[] = {
TSN0_AVTP_MATCH_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clkin),
SH_PFC_PIN_GROUP(audio_clkout),
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_rgmii),
SH_PFC_PIN_GROUP(avb0_txcrefclk),
SH_PFC_PIN_GROUP(avb0_avtp_pps),
SH_PFC_PIN_GROUP(avb0_avtp_capture),
SH_PFC_PIN_GROUP(avb0_avtp_match),
SH_PFC_PIN_GROUP(avb1_link),
SH_PFC_PIN_GROUP(avb1_magic),
SH_PFC_PIN_GROUP(avb1_phy_int),
SH_PFC_PIN_GROUP(avb1_mdio),
SH_PFC_PIN_GROUP(avb1_rgmii),
SH_PFC_PIN_GROUP(avb1_txcrefclk),
SH_PFC_PIN_GROUP(avb1_avtp_pps),
SH_PFC_PIN_GROUP(avb1_avtp_capture),
SH_PFC_PIN_GROUP(avb1_avtp_match),
SH_PFC_PIN_GROUP(avb2_link),
SH_PFC_PIN_GROUP(avb2_magic),
SH_PFC_PIN_GROUP(avb2_phy_int),
SH_PFC_PIN_GROUP(avb2_mdio),
SH_PFC_PIN_GROUP(avb2_rgmii),
SH_PFC_PIN_GROUP(avb2_txcrefclk),
SH_PFC_PIN_GROUP(avb2_avtp_pps),
SH_PFC_PIN_GROUP(avb2_avtp_capture),
SH_PFC_PIN_GROUP(avb2_avtp_match),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(canfd2_data),
SH_PFC_PIN_GROUP(canfd3_data),
SH_PFC_PIN_GROUP(canfd4_data),
SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */
SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */
SH_PFC_PIN_GROUP(canfd6_data),
SH_PFC_PIN_GROUP(canfd7_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif2_data),
SH_PFC_PIN_GROUP(hscif2_clk),
SH_PFC_PIN_GROUP(hscif2_ctrl),
SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c4),
SH_PFC_PIN_GROUP(i2c5),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof2_clk),
SH_PFC_PIN_GROUP(msiof2_sync),
SH_PFC_PIN_GROUP(msiof2_ss1),
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_rxd),
SH_PFC_PIN_GROUP(msiof3_clk),
SH_PFC_PIN_GROUP(msiof3_sync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(msiof4_clk),
SH_PFC_PIN_GROUP(msiof4_sync),
SH_PFC_PIN_GROUP(msiof4_ss1),
SH_PFC_PIN_GROUP(msiof4_ss2),
SH_PFC_PIN_GROUP(msiof4_txd),
SH_PFC_PIN_GROUP(msiof4_rxd),
SH_PFC_PIN_GROUP(msiof5_clk),
SH_PFC_PIN_GROUP(msiof5_sync),
SH_PFC_PIN_GROUP(msiof5_ss1),
SH_PFC_PIN_GROUP(msiof5_ss2),
SH_PFC_PIN_GROUP(msiof5_txd),
SH_PFC_PIN_GROUP(msiof5_rxd),
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm7),
SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(ssi_data),
SH_PFC_PIN_GROUP(ssi_ctrl),
SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
SH_PFC_PIN_GROUP(tsn0_link),
SH_PFC_PIN_GROUP(tsn0_phy_int),
SH_PFC_PIN_GROUP(tsn0_mdio),
SH_PFC_PIN_GROUP(tsn0_rgmii),
SH_PFC_PIN_GROUP(tsn0_txcrefclk),
SH_PFC_PIN_GROUP(tsn0_avtp_pps),
SH_PFC_PIN_GROUP(tsn0_avtp_capture),
SH_PFC_PIN_GROUP(tsn0_avtp_match),
};
static const char * const audio_clk_groups[] = {
"audio_clkin",
"audio_clkout",
};
static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
"avb0_mdio",
"avb0_rgmii",
"avb0_txcrefclk",
"avb0_avtp_pps",
"avb0_avtp_capture",
"avb0_avtp_match",
};
static const char * const avb1_groups[] = {
"avb1_link",
"avb1_magic",
"avb1_phy_int",
"avb1_mdio",
"avb1_rgmii",
"avb1_txcrefclk",
"avb1_avtp_pps",
"avb1_avtp_capture",
"avb1_avtp_match",
};
static const char * const avb2_groups[] = {
"avb2_link",
"avb2_magic",
"avb2_phy_int",
"avb2_mdio",
"avb2_rgmii",
"avb2_txcrefclk",
"avb2_avtp_pps",
"avb2_avtp_capture",
"avb2_avtp_match",
};
static const char * const canfd0_groups[] = {
"canfd0_data",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const canfd2_groups[] = {
"canfd2_data",
};
static const char * const canfd3_groups[] = {
"canfd3_data",
};
static const char * const canfd4_groups[] = {
"canfd4_data",
};
static const char * const canfd5_groups[] = {
/* suffix might be updated */
"canfd5_data",
"canfd5_data_b",
};
static const char * const canfd6_groups[] = {
"canfd6_data",
};
static const char * const canfd7_groups[] = {
"canfd7_data",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
};
static const char * const hscif1_groups[] = {
/* suffix might be updated */
"hscif1_data",
"hscif1_clk",
"hscif1_ctrl",
"hscif1_data_x",
"hscif1_clk_x",
"hscif1_ctrl_x",
};
static const char * const hscif2_groups[] = {
"hscif2_data",
"hscif2_clk",
"hscif2_ctrl",
};
static const char * const hscif3_groups[] = {
/* suffix might be updated */
"hscif3_data",
"hscif3_clk",
"hscif3_ctrl",
"hscif3_data_a",
"hscif3_clk_a",
"hscif3_ctrl_a",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1",
};
static const char * const i2c2_groups[] = {
"i2c2",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c4_groups[] = {
"i2c4",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
"mmc_ctrl",
"mmc_cd",
"mmc_wp",
"mmc_ds",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_txd",
"msiof1_rxd",
};
static const char * const msiof2_groups[] = {
"msiof2_clk",
"msiof2_sync",
"msiof2_ss1",
"msiof2_ss2",
"msiof2_txd",
"msiof2_rxd",
};
static const char * const msiof3_groups[] = {
"msiof3_clk",
"msiof3_sync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_txd",
"msiof3_rxd",
};
static const char * const msiof4_groups[] = {
"msiof4_clk",
"msiof4_sync",
"msiof4_ss1",
"msiof4_ss2",
"msiof4_txd",
"msiof4_rxd",
};
static const char * const msiof5_groups[] = {
"msiof5_clk",
"msiof5_sync",
"msiof5_ss1",
"msiof5_ss2",
"msiof5_txd",
"msiof5_rxd",
};
static const char * const pcie_groups[] = {
"pcie0_clkreq_n",
"pcie1_clkreq_n",
};
static const char * const pwm0_groups[] = {
/* suffix might be updated */
"pwm0_a",
};
static const char * const pwm1_groups[] = {
"pwm1_a",
"pwm1_b",
};
static const char * const pwm2_groups[] = {
/* suffix might be updated */
"pwm2_b",
};
static const char * const pwm3_groups[] = {
"pwm3_a",
"pwm3_b",
};
static const char * const pwm4_groups[] = {
"pwm4",
};
static const char * const pwm5_groups[] = {
"pwm5",
};
static const char * const pwm6_groups[] = {
"pwm6",
};
static const char * const pwm7_groups[] = {
"pwm7",
};
static const char * const pwm8_groups[] = {
/* suffix might be updated */
"pwm8_a",
};
static const char * const pwm9_groups[] = {
/* suffix might be updated */
"pwm9_a",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
/* suffix might be updated */
"scif1_data",
"scif1_clk",
"scif1_ctrl",
"scif1_data_x",
"scif1_clk_x",
"scif1_ctrl_x",
};
static const char * const scif3_groups[] = {
/* suffix might be updated */
"scif3_data",
"scif3_clk",
"scif3_ctrl",
"scif3_data_a",
"scif3_clk_a",
"scif3_ctrl_a",
};
static const char * const scif4_groups[] = {
"scif4_data",
"scif4_clk",
"scif4_ctrl",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
};
static const char * const ssi_groups[] = {
"ssi_data",
"ssi_ctrl",
};
static const char * const tpu_groups[] = {
/* suffix might be updated */
"tpu_to0",
"tpu_to0_a",
"tpu_to1",
"tpu_to1_a",
"tpu_to2",
"tpu_to2_a",
"tpu_to3",
"tpu_to3_a",
};
static const char * const tsn0_groups[] = {
"tsn0_link",
"tsn0_phy_int",
"tsn0_mdio",
"tsn0_rgmii",
"tsn0_txcrefclk",
"tsn0_avtp_pps",
"tsn0_avtp_capture",
"tsn0_avtp_match",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
SH_PFC_FUNCTION(avb2),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(canfd2),
SH_PFC_FUNCTION(canfd3),
SH_PFC_FUNCTION(canfd4),
SH_PFC_FUNCTION(canfd5),
SH_PFC_FUNCTION(canfd6),
SH_PFC_FUNCTION(canfd7),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(msiof4),
SH_PFC_FUNCTION(msiof5),
SH_PFC_FUNCTION(pcie),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(pwm7),
SH_PFC_FUNCTION(pwm8),
SH_PFC_FUNCTION(pwm9),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(tsn0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_19 RESERVED */
GP_0_18_FN, GPSR0_18,
GP_0_17_FN, GPSR0_17,
GP_0_16_FN, GPSR0_16,
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
GP_0_12_FN, GPSR0_12,
GP_0_11_FN, GPSR0_11,
GP_0_10_FN, GPSR0_10,
GP_0_9_FN, GPSR0_9,
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
GP_0_5_FN, GPSR0_5,
GP_0_4_FN, GPSR0_4,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
GP_1_28_FN, GPSR1_28,
GP_1_27_FN, GPSR1_27,
GP_1_26_FN, GPSR1_26,
GP_1_25_FN, GPSR1_25,
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
GP_1_19_FN, GPSR1_19,
GP_1_18_FN, GPSR1_18,
GP_1_17_FN, GPSR1_17,
GP_1_16_FN, GPSR1_16,
GP_1_15_FN, GPSR1_15,
GP_1_14_FN, GPSR1_14,
GP_1_13_FN, GPSR1_13,
GP_1_12_FN, GPSR1_12,
GP_1_11_FN, GPSR1_11,
GP_1_10_FN, GPSR1_10,
GP_1_9_FN, GPSR1_9,
GP_1_8_FN, GPSR1_8,
GP_1_7_FN, GPSR1_7,
GP_1_6_FN, GPSR1_6,
GP_1_5_FN, GPSR1_5,
GP_1_4_FN, GPSR1_4,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP2_31_20 RESERVED */
GP_2_19_FN, GPSR2_19,
GP_2_18_FN, GPSR2_18,
GP_2_17_FN, GPSR2_17,
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
GP_2_11_FN, GPSR2_11,
GP_2_10_FN, GPSR2_10,
GP_2_9_FN, GPSR2_9,
GP_2_8_FN, GPSR2_8,
GP_2_7_FN, GPSR2_7,
GP_2_6_FN, GPSR2_6,
GP_2_5_FN, GPSR2_5,
GP_2_4_FN, GPSR2_4,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
0, 0,
0, 0,
GP_3_29_FN, GPSR3_29,
GP_3_28_FN, GPSR3_28,
GP_3_27_FN, GPSR3_27,
GP_3_26_FN, GPSR3_26,
GP_3_25_FN, GPSR3_25,
GP_3_24_FN, GPSR3_24,
GP_3_23_FN, GPSR3_23,
GP_3_22_FN, GPSR3_22,
GP_3_21_FN, GPSR3_21,
GP_3_20_FN, GPSR3_20,
GP_3_19_FN, GPSR3_19,
GP_3_18_FN, GPSR3_18,
GP_3_17_FN, GPSR3_17,
GP_3_16_FN, GPSR3_16,
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
GP_3_12_FN, GPSR3_12,
GP_3_11_FN, GPSR3_11,
GP_3_10_FN, GPSR3_10,
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
GP_3_6_FN, GPSR3_6,
GP_3_5_FN, GPSR3_5,
GP_3_4_FN, GPSR3_4,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
GP_4_24_FN, GPSR4_24,
GP_4_23_FN, GPSR4_23,
GP_4_22_FN, GPSR4_22,
GP_4_21_FN, GPSR4_21,
GP_4_20_FN, GPSR4_20,
GP_4_19_FN, GPSR4_19,
GP_4_18_FN, GPSR4_18,
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
GP_4_14_FN, GPSR4_14,
GP_4_13_FN, GPSR4_13,
GP_4_12_FN, GPSR4_12,
GP_4_11_FN, GPSR4_11,
GP_4_10_FN, GPSR4_10,
GP_4_9_FN, GPSR4_9,
GP_4_8_FN, GPSR4_8,
GP_4_7_FN, GPSR4_7,
GP_4_6_FN, GPSR4_6,
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP5_31_21 RESERVED */
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
GP_5_17_FN, GPSR5_17,
GP_5_16_FN, GPSR5_16,
GP_5_15_FN, GPSR5_15,
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
GP_5_11_FN, GPSR5_11,
GP_5_10_FN, GPSR5_10,
GP_5_9_FN, GPSR5_9,
GP_5_8_FN, GPSR5_8,
GP_5_7_FN, GPSR5_7,
GP_5_6_FN, GPSR5_6,
GP_5_5_FN, GPSR5_5,
GP_5_4_FN, GPSR5_4,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP6_31_21 RESERVED */
GP_6_20_FN, GPSR6_20,
GP_6_19_FN, GPSR6_19,
GP_6_18_FN, GPSR6_18,
GP_6_17_FN, GPSR6_17,
GP_6_16_FN, GPSR6_16,
GP_6_15_FN, GPSR6_15,
GP_6_14_FN, GPSR6_14,
GP_6_13_FN, GPSR6_13,
GP_6_12_FN, GPSR6_12,
GP_6_11_FN, GPSR6_11,
GP_6_10_FN, GPSR6_10,
GP_6_9_FN, GPSR6_9,
GP_6_8_FN, GPSR6_8,
GP_6_7_FN, GPSR6_7,
GP_6_6_FN, GPSR6_6,
GP_6_5_FN, GPSR6_5,
GP_6_4_FN, GPSR6_4,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP7_31_21 RESERVED */
GP_7_20_FN, GPSR7_20,
GP_7_19_FN, GPSR7_19,
GP_7_18_FN, GPSR7_18,
GP_7_17_FN, GPSR7_17,
GP_7_16_FN, GPSR7_16,
GP_7_15_FN, GPSR7_15,
GP_7_14_FN, GPSR7_14,
GP_7_13_FN, GPSR7_13,
GP_7_12_FN, GPSR7_12,
GP_7_11_FN, GPSR7_11,
GP_7_10_FN, GPSR7_10,
GP_7_9_FN, GPSR7_9,
GP_7_8_FN, GPSR7_8,
GP_7_7_FN, GPSR7_7,
GP_7_6_FN, GPSR7_6,
GP_7_5_FN, GPSR7_5,
GP_7_4_FN, GPSR7_4,
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
GROUP(-18, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP8_31_14 RESERVED */
GP_8_13_FN, GPSR8_13,
GP_8_12_FN, GPSR8_12,
GP_8_11_FN, GPSR8_11,
GP_8_10_FN, GPSR8_10,
GP_8_9_FN, GPSR8_9,
GP_8_8_FN, GPSR8_8,
GP_8_7_FN, GPSR8_7,
GP_8_6_FN, GPSR8_6,
GP_8_5_FN, GPSR8_5,
GP_8_4_FN, GPSR8_4,
GP_8_3_FN, GPSR8_3,
GP_8_2_FN, GPSR8_2,
GP_8_1_FN, GPSR8_1,
GP_8_0_FN, GPSR8_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
IP0SR0_31_28
IP0SR0_27_24
IP0SR0_23_20
IP0SR0_19_16
IP0SR0_15_12
IP0SR0_11_8
IP0SR0_7_4
IP0SR0_3_0))
},
{ PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
IP1SR0_31_28
IP1SR0_27_24
IP1SR0_23_20
IP1SR0_19_16
IP1SR0_15_12
IP1SR0_11_8
IP1SR0_7_4
IP1SR0_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
GROUP(-20, 4, 4, 4),
GROUP(
/* IP2SR0_31_12 RESERVED */
IP2SR0_11_8
IP2SR0_7_4
IP2SR0_3_0))
},
{ PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
IP0SR1_31_28
IP0SR1_27_24
IP0SR1_23_20
IP0SR1_19_16
IP0SR1_15_12
IP0SR1_11_8
IP0SR1_7_4
IP0SR1_3_0))
},
{ PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
IP1SR1_31_28
IP1SR1_27_24
IP1SR1_23_20
IP1SR1_19_16
IP1SR1_15_12
IP1SR1_11_8
IP1SR1_7_4
IP1SR1_3_0))
},
{ PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
IP2SR1_31_28
IP2SR1_27_24
IP2SR1_23_20
IP2SR1_19_16
IP2SR1_15_12
IP2SR1_11_8
IP2SR1_7_4
IP2SR1_3_0))
},
{ PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
GROUP(-12, 4, 4, 4, 4, 4),
GROUP(
/* IP3SR1_31_20 RESERVED */
IP3SR1_19_16
IP3SR1_15_12
IP3SR1_11_8
IP3SR1_7_4
IP3SR1_3_0))
},
{ PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
IP0SR2_31_28
IP0SR2_27_24
IP0SR2_23_20
IP0SR2_19_16
IP0SR2_15_12
IP0SR2_11_8
IP0SR2_7_4
IP0SR2_3_0))
},
{ PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
IP1SR2_31_28
IP1SR2_27_24
IP1SR2_23_20
IP1SR2_19_16
IP1SR2_15_12
IP1SR2_11_8
IP1SR2_7_4
IP1SR2_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
GROUP(-16, 4, 4, 4, 4),
GROUP(
/* IP2SR2_31_16 RESERVED */
IP2SR2_15_12
IP2SR2_11_8
IP2SR2_7_4
IP2SR2_3_0))
},
{ PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
IP0SR3_31_28
IP0SR3_27_24
IP0SR3_23_20
IP0SR3_19_16
IP0SR3_15_12
IP0SR3_11_8
IP0SR3_7_4
IP0SR3_3_0))
},
{ PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
IP1SR3_31_28
IP1SR3_27_24
IP1SR3_23_20
IP1SR3_19_16
IP1SR3_15_12
IP1SR3_11_8
IP1SR3_7_4
IP1SR3_3_0))
},
{ PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
IP2SR3_31_28
IP2SR3_27_24
IP2SR3_23_20
IP2SR3_19_16
IP2SR3_15_12
IP2SR3_11_8
IP2SR3_7_4
IP2SR3_3_0))
},
{ PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
GROUP(-8, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP3SR3_31_24 RESERVED */
IP3SR3_23_20
IP3SR3_19_16
IP3SR3_15_12
IP3SR3_11_8
IP3SR3_7_4
IP3SR3_3_0))
},
{ PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
IP0SR4_31_28
IP0SR4_27_24
IP0SR4_23_20
IP0SR4_19_16
IP0SR4_15_12
IP0SR4_11_8
IP0SR4_7_4
IP0SR4_3_0))
},
{ PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
IP1SR4_31_28
IP1SR4_27_24
IP1SR4_23_20
IP1SR4_19_16
IP1SR4_15_12
IP1SR4_11_8
IP1SR4_7_4
IP1SR4_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
IP2SR4_31_28
IP2SR4_27_24
IP2SR4_23_20
IP2SR4_19_16
IP2SR4_15_12
IP2SR4_11_8
IP2SR4_7_4
IP2SR4_3_0))
},
{ PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
GROUP(-28, 4),
GROUP(
/* IP3SR4_31_4 RESERVED */
IP3SR4_3_0))
},
{ PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
IP0SR5_31_28
IP0SR5_27_24
IP0SR5_23_20
IP0SR5_19_16
IP0SR5_15_12
IP0SR5_11_8
IP0SR5_7_4
IP0SR5_3_0))
},
{ PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
IP1SR5_31_28
IP1SR5_27_24
IP1SR5_23_20
IP1SR5_19_16
IP1SR5_15_12
IP1SR5_11_8
IP1SR5_7_4
IP1SR5_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
GROUP(-12, 4, 4, 4, 4, 4),
GROUP(
/* IP2SR5_31_20 RESERVED */
IP2SR5_19_16
IP2SR5_15_12
IP2SR5_11_8
IP2SR5_7_4
IP2SR5_3_0))
},
{ PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
IP0SR6_31_28
IP0SR6_27_24
IP0SR6_23_20
IP0SR6_19_16
IP0SR6_15_12
IP0SR6_11_8
IP0SR6_7_4
IP0SR6_3_0))
},
{ PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
IP1SR6_31_28
IP1SR6_27_24
IP1SR6_23_20
IP1SR6_19_16
IP1SR6_15_12
IP1SR6_11_8
IP1SR6_7_4
IP1SR6_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
GROUP(-12, 4, 4, 4, 4, 4),
GROUP(
/* IP2SR6_31_20 RESERVED */
IP2SR6_19_16
IP2SR6_15_12
IP2SR6_11_8
IP2SR6_7_4
IP2SR6_3_0))
},
{ PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
IP0SR7_31_28
IP0SR7_27_24
IP0SR7_23_20
IP0SR7_19_16
IP0SR7_15_12
IP0SR7_11_8
IP0SR7_7_4
IP0SR7_3_0))
},
{ PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
IP1SR7_31_28
IP1SR7_27_24
IP1SR7_23_20
IP1SR7_19_16
IP1SR7_15_12
IP1SR7_11_8
IP1SR7_7_4
IP1SR7_3_0))
},
{ PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
GROUP(-12, 4, 4, 4, 4, 4),
GROUP(
/* IP2SR7_31_20 RESERVED */
IP2SR7_19_16
IP2SR7_15_12
IP2SR7_11_8
IP2SR7_7_4
IP2SR7_3_0))
},
{ PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
IP0SR8_31_28
IP0SR8_27_24
IP0SR8_23_20
IP0SR8_19_16
IP0SR8_15_12
IP0SR8_11_8
IP0SR8_7_4
IP0SR8_3_0))
},
{ PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
GROUP(-8, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP1SR8_31_24 RESERVED */
IP1SR8_23_20
IP1SR8_19_16
IP1SR8_15_12
IP1SR8_11_8
IP1SR8_7_4
IP1SR8_3_0))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31-12 */
MOD_SEL8_11
MOD_SEL8_10
MOD_SEL8_9
MOD_SEL8_8
MOD_SEL8_7
MOD_SEL8_6
MOD_SEL8_5
MOD_SEL8_4
MOD_SEL8_3
MOD_SEL8_2
MOD_SEL8_1
MOD_SEL8_0))
},
{ /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
{ RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
{ RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
{ RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
{ RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
{ RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
{ RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
{ RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
{ RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
{ RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
{ RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
{ RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
{ RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
{ RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
{ RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
{ RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
{ RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
{ RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
{ RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
{ RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
{ RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
{ RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
{ RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
{ RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
{ RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
{ RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
{ RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
{ RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
{ RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
{ RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
{ RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
{ RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
{ RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
{ RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
{ RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
{ RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
{ RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
{ RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
{ RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
{ RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
{ RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
{ RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
{ RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
} },
{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
{ RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
{ RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
{ RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
{ RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
{ RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
{ RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
{ RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
{ RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
{ RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
{ RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
{ RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
{ RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
{ RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
{ RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
{ RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
{ RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
{ RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
{ RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
{ RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
{ RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
{ RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
{ RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
{ RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
{ RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
{ RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
{ RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
{ RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
{ RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
{ RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
{ RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
{ RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
{ RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
{ RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
{ RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
{ RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
{ RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
{ RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
{ RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
{ RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
{ RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
{ RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
{ RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
{ RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
{ RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
{ RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
{ RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
{ RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
{ RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
{ RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
} },
{ PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
{ RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
{ RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
{ RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
{ RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
{ RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
{ RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
{ RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
{ RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
{ RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
{ RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
{ RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
{ RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
{ RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
{ RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
{ RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
{ RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
{ RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
{ RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
{ RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
{ RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
{ RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
{ RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
{ RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
{ RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
{ RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
{ RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
{ RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
{ RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
{ RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
{ RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
} },
{ PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
{ RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
{ RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
{ RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
{ RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
{ RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
{ RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
{ RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
{ RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
{ RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
{ RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
{ RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
{ RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
{ RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
{ RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
{ RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
{ RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
{ RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
{ RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
{ RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
{ RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
{ RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
{ RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
{ RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
{ RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
{ RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
{ RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
{ RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
{ RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
{ RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
{ RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
{ RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
{ RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
{ RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
{ RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
{ RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
{ RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
{ RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
{ RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
{ RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
{ RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
{ RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
{ RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
{ RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
{ RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
{ RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
{ RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
{ RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
{ RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
{ RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
{ RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
{ RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
{ RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
{ RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
{ RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
{ RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
{ RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
{ RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
{ RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
} },
{ PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
{ RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
{ RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
{ RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
{ RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
{ RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
} },
{ PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
{ RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
{ RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
{ RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
{ RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
{ RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
{ RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
{ RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
{ RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
} },
{ PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
{ RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
{ RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
{ RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
{ RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
{ RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
{ RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
} },
{ /* sentinel */ }
};
enum ioctrl_regs {
POC0,
POC1,
POC3,
POC4,
POC5,
POC6,
POC7,
POC8,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POC0] = { 0xE60500A0, },
[POC1] = { 0xE60508A0, },
[POC3] = { 0xE60588A0, },
[POC4] = { 0xE60600A0, },
[POC5] = { 0xE60608A0, },
[POC6] = { 0xE60610A0, },
[POC7] = { 0xE60618A0, },
[POC8] = { 0xE60680A0, },
{ /* sentinel */ }
};
static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
switch (pin) {
case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
*pocctrl = pinmux_ioctrl_regs[POC0].reg;
return bit;
case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
*pocctrl = pinmux_ioctrl_regs[POC1].reg;
return bit;
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
*pocctrl = pinmux_ioctrl_regs[POC3].reg;
return bit;
case PIN_VDDQ_TSN0:
*pocctrl = pinmux_ioctrl_regs[POC4].reg;
return 0;
case PIN_VDDQ_AVB2:
*pocctrl = pinmux_ioctrl_regs[POC5].reg;
return 0;
case PIN_VDDQ_AVB1:
*pocctrl = pinmux_ioctrl_regs[POC6].reg;
return 0;
case PIN_VDDQ_AVB0:
*pocctrl = pinmux_ioctrl_regs[POC7].reg;
return 0;
case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
*pocctrl = pinmux_ioctrl_regs[POC8].reg;
return bit;
default:
return -EINVAL;
}
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
[ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
[ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
[ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
[ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
[ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
[ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
[ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
[ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
[ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
[ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
[10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
[11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
[12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
[13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
[14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
[15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
[16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
[17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
[18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
[ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
[ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
[ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
[ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
[ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
[ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
[ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
[ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
[ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
[ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
[10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
[11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
[12] = RCAR_GP_PIN(1, 12), /* HTX0 */
[13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
[14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
[15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
[16] = RCAR_GP_PIN(1, 16), /* HRX0 */
[17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
[18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
[19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
[20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
[21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
[22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
[23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
[24] = RCAR_GP_PIN(1, 24), /* HRX3 */
[25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
[26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
[27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
[28] = RCAR_GP_PIN(1, 28), /* HTX3 */
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
[ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
[ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
[ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
[ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
[ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
[ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
[ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
[ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
[ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
[ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
[10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
[11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
[12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
[13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
[14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
[15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
[16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
[17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
[18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
[19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
[ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
[ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
[ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
[ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
[ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
[ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
[ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
[ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
[ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
[ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
[10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
[11] = RCAR_GP_PIN(3, 11), /* SD_CD */
[12] = RCAR_GP_PIN(3, 12), /* SD_WP */
[13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
[14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
[15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
[16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
[17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
[18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
[19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
[20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
[21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
[22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
[23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
[24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
[25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
[26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
[27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
[28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
[29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
[ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
[ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
[ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
[ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
[ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
[ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
[ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
[ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
[ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
[ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
[10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
[11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
[12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
[13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
[14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
[15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
[16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
[17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
[18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
[19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
[20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
[21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
[22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
[23] = RCAR_GP_PIN(4, 23), /* AVS0 */
[24] = RCAR_GP_PIN(4, 24), /* AVS1 */
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
[ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
[ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
[ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
[ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
[ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
[ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
[ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
[ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
[ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
[ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
[10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
[11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
[12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
[13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
[14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
[15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
[16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
[17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
[18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
[19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
[20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
[ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
[ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
[ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
[ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
[ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
[ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
[ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
[ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
[ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
[ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
[10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
[11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
[12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
[13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
[14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
[15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
[16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
[17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
[18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
[19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
[20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
[ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
[ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
[ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
[ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
[ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
[ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
[ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
[ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
[ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
[ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
[10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
[11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
[12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
[13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
[14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
[15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
[16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
[17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
[18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
[19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
[20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
[ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
[ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
[ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
[ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
[ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
[ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
[ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
[ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
[ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
[ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
[10] = RCAR_GP_PIN(8, 10), /* SCL5 */
[11] = RCAR_GP_PIN(8, 11), /* SDA5 */
[12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
[13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
.pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
.name = "r8a779g0_pfc",
.ops = &r8a779g0_pin_ops,
.unlock_reg = 0x1ff, /* PMMRn mask */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a779g0.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A77470 processor support - PFC hardware block.
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
/* GPSR0 */
FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
/* GPSR1 */
FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
/* GPSR2 */
FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
FN_IP7_31_28, FN_IP8_3_0,
/* GPSR3 */
FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
/* GPSR4 */
FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
/* GPSR5 */
FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
/* IPSR0 */
FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
FN_SD0_CD, FN_CAN0_RX_A,
FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
/* IPSR1 */
FN_MMC0_D4, FN_SD1_CD,
FN_MMC0_D5, FN_SD1_WP,
FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
/* IPSR2 */
FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
/* IPSR3 */
FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
FN_QSPI0_SPCLK, FN_WE0_N,
FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
FN_QSPI0_IO2, FN_CS0_N,
FN_QSPI0_IO3, FN_RD_N,
FN_QSPI0_SSL, FN_WE1_N,
/* IPSR4 */
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
FN_DU0_DR4, FN_RX1_D, FN_A4,
FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
FN_DU0_DR6, FN_RX2_C, FN_A6,
/* IPSR5 */
FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
FN_DU0_DG2, FN_RX4_D, FN_A10,
FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
FN_DU0_DG4, FN_HRX0_A, FN_A12,
FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
FN_DU0_DG6, FN_HRX1_C, FN_A14,
/* IPSR6 */
FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
FN_DU0_DB2, FN_HCTS0_N, FN_A18,
FN_DU0_DB3, FN_HRTS0_N, FN_A19,
FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
FN_DU0_DB6, FN_A22,
/* IPSR7 */
FN_DU0_DB7, FN_A23,
FN_DU0_DOTCLKIN, FN_A24,
FN_DU0_DOTCLKOUT0, FN_A25,
FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
FN_DU0_DISP, FN_CAN1_RX_C,
/* IPSR8 */
FN_DU0_CDE, FN_CAN1_TX_C,
FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
/* IPSR9 */
FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
/* IPSR10 */
FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
/* IPSR11 */
FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
/* IPSR12 */
FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
/* IPSR13 */
FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
/* IPSR14 */
FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
/* IPSR15 */
FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
/* IPSR16 */
FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
/* IPSR17 */
FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
/* MOD_SEL0 */
FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
FN_SEL_AVB_0, FN_SEL_AVB_1,
/* MOD_SEL1 */
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
FN_SEL_RCN_0, FN_SEL_RCN_1,
FN_SEL_TMU2_0, FN_SEL_TMU2_1,
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
/* MOD_SEL2 */
FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
FN_SEL_SSI8_0, FN_SEL_SSI8_1,
FN_SEL_SSI7_0, FN_SEL_SSI7_1,
FN_SEL_SSI6_0, FN_SEL_SSI6_1,
FN_SEL_SSI5_0, FN_SEL_SSI5_1,
FN_SEL_SSI4_0, FN_SEL_SSI4_1,
FN_SEL_SSI2_0, FN_SEL_SSI2_1,
FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
FN_SEL_SSI0_0, FN_SEL_SSI0_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
MMC0_D7_MARK,
/* IPSR0 */
SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
SD0_CD_MARK, CAN0_RX_A_MARK,
SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
/* IPSR1 */
MMC0_D4_MARK, SD1_CD_MARK,
MMC0_D5_MARK, SD1_WP_MARK,
D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
/* IPSR2 */
D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
/* IPSR3 */
D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
QSPI0_SPCLK_MARK, WE0_N_MARK,
QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
QSPI0_IO2_MARK, CS0_N_MARK,
QSPI0_IO3_MARK, RD_N_MARK,
QSPI0_SSL_MARK, WE1_N_MARK,
/* IPSR4 */
EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
/* IPSR5 */
DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
/* IPSR6 */
DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
DU0_DB6_MARK, A22_MARK,
/* IPSR7 */
DU0_DB7_MARK, A23_MARK,
DU0_DOTCLKIN_MARK, A24_MARK,
DU0_DOTCLKOUT0_MARK, A25_MARK,
DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
DU0_DISP_MARK, CAN1_RX_C_MARK,
/* IPSR8 */
DU0_CDE_MARK, CAN1_TX_C_MARK,
VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
/* IPSR9 */
VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
/* IPSR10 */
VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
/* IPSR11 */
SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
/* IPSR12 */
HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
/* IPSR13 */
SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
/* IPSR14 */
SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
/* IPSR15 */
SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
/* IPSR16 */
SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
/* IPSR17 */
SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
PINMUX_MARK_END,
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB1_PWEN),
PINMUX_SINGLE(USB1_OVC),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
PINMUX_SINGLE(MMC0_D6),
PINMUX_SINGLE(MMC0_D7),
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
PINMUX_IPSR_GPSR(IP1_11_8, D0),
PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
PINMUX_IPSR_GPSR(IP1_15_12, D1),
PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
PINMUX_IPSR_GPSR(IP1_19_16, D2),
PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
PINMUX_IPSR_GPSR(IP1_23_20, D3),
PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
PINMUX_IPSR_GPSR(IP1_27_24, D4),
PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
PINMUX_IPSR_GPSR(IP1_31_28, D5),
PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
/* IPSR2 */
PINMUX_IPSR_GPSR(IP2_3_0, D6),
PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
PINMUX_IPSR_GPSR(IP2_7_4, D7),
PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
PINMUX_IPSR_GPSR(IP2_11_8, D8),
PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
PINMUX_IPSR_GPSR(IP2_15_12, D9),
PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
PINMUX_IPSR_GPSR(IP2_19_16, D10),
PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_GPSR(IP2_23_20, D11),
PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_GPSR(IP2_27_24, D12),
PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
PINMUX_IPSR_GPSR(IP2_31_28, D13),
PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_3_0, D14),
PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
PINMUX_IPSR_GPSR(IP3_7_4, D15),
PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
/* IPSR4 */
PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
PINMUX_IPSR_GPSR(IP4_7_4, A0),
PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
PINMUX_IPSR_GPSR(IP4_11_8, A1),
PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
PINMUX_IPSR_GPSR(IP4_15_12, A2),
PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
PINMUX_IPSR_GPSR(IP4_19_16, A3),
PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
PINMUX_IPSR_GPSR(IP4_23_20, A4),
PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
PINMUX_IPSR_GPSR(IP4_27_24, A5),
PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
PINMUX_IPSR_GPSR(IP4_31_28, A6),
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
PINMUX_IPSR_GPSR(IP5_3_0, A7),
PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
PINMUX_IPSR_GPSR(IP5_7_4, A8),
PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
PINMUX_IPSR_GPSR(IP5_11_8, A9),
PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP5_15_12, A10),
PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
PINMUX_IPSR_GPSR(IP5_19_16, A11),
PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
PINMUX_IPSR_GPSR(IP5_23_20, A12),
PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
PINMUX_IPSR_GPSR(IP5_27_24, A13),
PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_GPSR(IP5_31_28, A14),
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
PINMUX_IPSR_GPSR(IP6_3_0, A15),
PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
PINMUX_IPSR_GPSR(IP6_7_4, A16),
PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
PINMUX_IPSR_GPSR(IP6_11_8, A17),
PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
PINMUX_IPSR_GPSR(IP6_15_12, A18),
PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
PINMUX_IPSR_GPSR(IP6_19_16, A19),
PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_GPSR(IP6_23_20, A20),
PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
PINMUX_IPSR_GPSR(IP6_27_24, A21),
PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
PINMUX_IPSR_GPSR(IP6_31_28, A22),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
PINMUX_IPSR_GPSR(IP7_3_0, A23),
PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
PINMUX_IPSR_GPSR(IP7_7_4, A24),
PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
PINMUX_IPSR_GPSR(IP7_11_8, A25),
PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
/* IPSR8 */
PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
/* IPSR10 */
PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
/* IPSR11 */
PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
/* IPSR12 */
PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
/* IPSR13 */
PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
/* IPSR14 */
PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
/* IPSR16 */
PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AVB -------------------------------------------------------------------- */
static const unsigned int avb_col_pins[] = {
RCAR_GP_PIN(5, 18),
};
static const unsigned int avb_col_mux[] = {
AVB_COL_MARK,
};
static const unsigned int avb_crs_pins[] = {
RCAR_GP_PIN(5, 17),
};
static const unsigned int avb_crs_mux[] = {
AVB_CRS_MARK,
};
static const unsigned int avb_link_pins[] = {
RCAR_GP_PIN(5, 14),
};
static const unsigned int avb_link_mux[] = {
AVB_LINK_MARK,
};
static const unsigned int avb_magic_pins[] = {
RCAR_GP_PIN(5, 15),
};
static const unsigned int avb_magic_mux[] = {
AVB_MAGIC_MARK,
};
static const unsigned int avb_phy_int_pins[] = {
RCAR_GP_PIN(5, 16),
};
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdio_pins[] = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_tx_rx_pins[] = {
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
RCAR_GP_PIN(3, 10),
};
static const unsigned int avb_mii_tx_rx_mux[] = {
AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
AVB_TXD3_MARK, AVB_TX_EN_MARK,
AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
};
static const unsigned int avb_mii_tx_er_pins[] = {
RCAR_GP_PIN(5, 23),
};
static const unsigned int avb_mii_tx_er_mux[] = {
AVB_TX_ER_MARK,
};
static const unsigned int avb_gmii_tx_rx_pins[] = {
RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
};
static const unsigned int avb_gmii_tx_rx_mux[] = {
AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
AVB_TX_ER_MARK,
AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
};
static const unsigned int avb_avtp_match_a_pins[] = {
RCAR_GP_PIN(1, 15),
};
static const unsigned int avb_avtp_match_a_mux[] = {
AVB_AVTP_MATCH_A_MARK,
};
static const unsigned int avb_avtp_capture_a_pins[] = {
RCAR_GP_PIN(1, 14),
};
static const unsigned int avb_avtp_capture_a_mux[] = {
AVB_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb_avtp_match_b_pins[] = {
RCAR_GP_PIN(5, 20),
};
static const unsigned int avb_avtp_match_b_mux[] = {
AVB_AVTP_MATCH_B_MARK,
};
static const unsigned int avb_avtp_capture_b_pins[] = {
RCAR_GP_PIN(5, 19),
};
static const unsigned int avb_avtp_capture_b_mux[] = {
AVB_AVTP_CAPTURE_B_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du0_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
};
static const unsigned int du0_rgb666_mux[] = {
DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
DU0_DR3_MARK, DU0_DR2_MARK,
DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
DU0_DG3_MARK, DU0_DG2_MARK,
DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
DU0_DB3_MARK, DU0_DB2_MARK,
};
static const unsigned int du0_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
};
static const unsigned int du0_rgb888_mux[] = {
DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
};
static const unsigned int du0_clk0_out_pins[] = {
/* DOTCLKOUT0 */
RCAR_GP_PIN(2, 25),
};
static const unsigned int du0_clk0_out_mux[] = {
DU0_DOTCLKOUT0_MARK
};
static const unsigned int du0_clk1_out_pins[] = {
/* DOTCLKOUT1 */
RCAR_GP_PIN(2, 26),
};
static const unsigned int du0_clk1_out_mux[] = {
DU0_DOTCLKOUT1_MARK
};
static const unsigned int du0_clk_in_pins[] = {
/* CLKIN */
RCAR_GP_PIN(2, 24),
};
static const unsigned int du0_clk_in_mux[] = {
DU0_DOTCLKIN_MARK
};
static const unsigned int du0_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
};
static const unsigned int du0_sync_mux[] = {
DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
};
static const unsigned int du0_oddf_pins[] = {
/* EXODDF/ODDF/DISP/CDE */
RCAR_GP_PIN(2, 29),
};
static const unsigned int du0_oddf_mux[] = {
DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
};
static const unsigned int du0_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(2, 31),
};
static const unsigned int du0_cde_mux[] = {
DU0_CDE_MARK,
};
static const unsigned int du0_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(2, 30),
};
static const unsigned int du0_disp_mux[] = {
DU0_DISP_MARK
};
static const unsigned int du1_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
};
static const unsigned int du1_rgb666_mux[] = {
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
DU1_DR3_MARK, DU1_DR2_MARK,
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
DU1_DG3_MARK, DU1_DG2_MARK,
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
DU1_DB3_MARK, DU1_DB2_MARK,
};
static const unsigned int du1_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
};
static const unsigned int du1_rgb888_mux[] = {
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
};
static const unsigned int du1_clk0_out_pins[] = {
/* DOTCLKOUT0 */
RCAR_GP_PIN(5, 2),
};
static const unsigned int du1_clk0_out_mux[] = {
DU1_DOTCLKOUT0_MARK
};
static const unsigned int du1_clk1_out_pins[] = {
/* DOTCLKOUT1 */
RCAR_GP_PIN(5, 0),
};
static const unsigned int du1_clk1_out_mux[] = {
DU1_DOTCLKOUT1_MARK
};
static const unsigned int du1_clk_in_pins[] = {
/* DOTCLKIN */
RCAR_GP_PIN(5, 1),
};
static const unsigned int du1_clk_in_mux[] = {
DU1_DOTCLKIN_MARK
};
static const unsigned int du1_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
};
static const unsigned int du1_sync_mux[] = {
DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
};
static const unsigned int du1_oddf_pins[] = {
/* EXODDF/ODDF/DISP/CDE */
RCAR_GP_PIN(5, 3),
};
static const unsigned int du1_oddf_mux[] = {
DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
};
static const unsigned int du1_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(5, 7),
};
static const unsigned int du1_cde_mux[] = {
DU1_CDE_MARK
};
static const unsigned int du1_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(5, 6),
};
static const unsigned int du1_disp_mux[] = {
DU1_DISP_MARK
};
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
};
static const unsigned int i2c0_a_mux[] = {
SCL0_A_MARK, SDA0_A_MARK,
};
static const unsigned int i2c0_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
};
static const unsigned int i2c0_b_mux[] = {
SCL0_B_MARK, SDA0_B_MARK,
};
static const unsigned int i2c0_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
};
static const unsigned int i2c0_c_mux[] = {
SCL0_C_MARK, SDA0_C_MARK,
};
static const unsigned int i2c0_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
};
static const unsigned int i2c0_d_mux[] = {
SCL0_D_MARK, SDA0_D_MARK,
};
static const unsigned int i2c0_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
};
static const unsigned int i2c0_e_mux[] = {
SCL0_E_MARK, SDA0_E_MARK,
};
/* - I2C1 ------------------------------------------------------------------- */
static const unsigned int i2c1_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
};
static const unsigned int i2c1_a_mux[] = {
SCL1_A_MARK, SDA1_A_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int i2c1_b_mux[] = {
SCL1_B_MARK, SDA1_B_MARK,
};
static const unsigned int i2c1_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
};
static const unsigned int i2c1_c_mux[] = {
SCL1_C_MARK, SDA1_C_MARK,
};
static const unsigned int i2c1_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
};
static const unsigned int i2c1_d_mux[] = {
SCL1_D_MARK, SDA1_D_MARK,
};
static const unsigned int i2c1_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
};
static const unsigned int i2c1_e_mux[] = {
SCL1_E_MARK, SDA1_E_MARK,
};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
};
static const unsigned int i2c2_a_mux[] = {
SCL2_A_MARK, SDA2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int i2c2_b_mux[] = {
SCL2_B_MARK, SDA2_B_MARK,
};
static const unsigned int i2c2_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int i2c2_c_mux[] = {
SCL2_C_MARK, SDA2_C_MARK,
};
static const unsigned int i2c2_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int i2c2_d_mux[] = {
SCL2_D_MARK, SDA2_D_MARK,
};
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
};
static const unsigned int i2c3_a_mux[] = {
SCL3_A_MARK, SDA3_A_MARK,
};
static const unsigned int i2c3_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
};
static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
static const unsigned int i2c3_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int i2c3_c_mux[] = {
SCL3_C_MARK, SDA3_C_MARK,
};
static const unsigned int i2c3_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
};
static const unsigned int i2c3_d_mux[] = {
SCL3_D_MARK, SDA3_D_MARK,
};
static const unsigned int i2c3_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
};
static const unsigned int i2c3_e_mux[] = {
SCL3_E_MARK, SDA3_E_MARK,
};
/* - I2C4 ------------------------------------------------------------------- */
static const unsigned int i2c4_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
};
static const unsigned int i2c4_a_mux[] = {
SCL4_A_MARK, SDA4_A_MARK,
};
static const unsigned int i2c4_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
};
static const unsigned int i2c4_b_mux[] = {
SCL4_B_MARK, SDA4_B_MARK,
};
static const unsigned int i2c4_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
};
static const unsigned int i2c4_c_mux[] = {
SCL4_C_MARK, SDA4_C_MARK,
};
static const unsigned int i2c4_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
};
static const unsigned int i2c4_d_mux[] = {
SCL4_D_MARK, SDA4_D_MARK,
};
static const unsigned int i2c4_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
};
static const unsigned int i2c4_e_mux[] = {
SCL4_E_MARK, SDA4_E_MARK,
};
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
};
static const unsigned int mmc_data_mux[] = {
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK,
MMC0_D6_MARK, MMC0_D7_MARK,
};
static const unsigned int mmc_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
};
static const unsigned int mmc_ctrl_mux[] = {
MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
RCAR_GP_PIN(1, 20),
};
static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8),
};
static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
};
static const unsigned int scif0_data_a_mux[] = {
RX0_A_MARK, TX0_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
};
static const unsigned int scif0_data_b_mux[] = {
RX0_B_MARK, TX0_B_MARK,
};
static const unsigned int scif0_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
};
static const unsigned int scif0_data_c_mux[] = {
RX0_C_MARK, TX0_C_MARK,
};
static const unsigned int scif0_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
};
static const unsigned int scif0_data_d_mux[] = {
RX0_D_MARK, TX0_D_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
};
static const unsigned int scif1_data_a_mux[] = {
RX1_A_MARK, TX1_A_MARK,
};
static const unsigned int scif1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 15),
};
static const unsigned int scif1_clk_a_mux[] = {
SCIF1_SCK_A_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
static const unsigned int scif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 18),
};
static const unsigned int scif1_clk_b_mux[] = {
SCIF1_SCK_B_MARK,
};
static const unsigned int scif1_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
};
static const unsigned int scif1_data_c_mux[] = {
RX1_C_MARK, TX1_C_MARK,
};
static const unsigned int scif1_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 7),
};
static const unsigned int scif1_clk_c_mux[] = {
SCIF1_SCK_C_MARK,
};
static const unsigned int scif1_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
};
static const unsigned int scif1_data_d_mux[] = {
RX1_D_MARK, TX1_D_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
};
static const unsigned int scif2_data_a_mux[] = {
RX2_A_MARK, TX2_A_MARK,
};
static const unsigned int scif2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 20),
};
static const unsigned int scif2_clk_a_mux[] = {
SCIF2_SCK_A_MARK,
};
static const unsigned int scif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
};
static const unsigned int scif2_data_b_mux[] = {
RX2_B_MARK, TX2_B_MARK,
};
static const unsigned int scif2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 27),
};
static const unsigned int scif2_clk_b_mux[] = {
SCIF2_SCK_B_MARK,
};
static const unsigned int scif2_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
};
static const unsigned int scif2_data_c_mux[] = {
RX2_C_MARK, TX2_C_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
};
static const unsigned int scif3_data_a_mux[] = {
RX3_A_MARK, TX3_A_MARK,
};
static const unsigned int scif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 21),
};
static const unsigned int scif3_clk_mux[] = {
SCIF3_SCK_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
};
static const unsigned int scif3_data_b_mux[] = {
RX3_B_MARK, TX3_B_MARK,
};
static const unsigned int scif3_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
};
static const unsigned int scif3_data_c_mux[] = {
RX3_C_MARK, TX3_C_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
};
static const unsigned int scif4_data_a_mux[] = {
RX4_A_MARK, TX4_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
};
static const unsigned int scif4_data_b_mux[] = {
RX4_B_MARK, TX4_B_MARK,
};
static const unsigned int scif4_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
};
static const unsigned int scif4_data_c_mux[] = {
RX4_C_MARK, TX4_C_MARK,
};
static const unsigned int scif4_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
};
static const unsigned int scif4_data_d_mux[] = {
RX4_D_MARK, TX4_D_MARK,
};
static const unsigned int scif4_data_e_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
};
static const unsigned int scif4_data_e_mux[] = {
RX4_E_MARK, TX4_E_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
static const unsigned int scif5_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int scif5_data_a_mux[] = {
RX5_A_MARK, TX5_A_MARK,
};
static const unsigned int scif5_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
};
static const unsigned int scif5_data_b_mux[] = {
RX5_B_MARK, TX5_B_MARK,
};
static const unsigned int scif5_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int scif5_data_c_mux[] = {
RX5_C_MARK, TX5_C_MARK,
};
static const unsigned int scif5_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int scif5_data_d_mux[] = {
RX5_D_MARK, TX5_D_MARK,
};
static const unsigned int scif5_data_e_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int scif5_data_e_mux[] = {
RX5_E_MARK, TX5_E_MARK,
};
static const unsigned int scif5_data_f_pins[] = {
/* RX, TX */
RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
};
static const unsigned int scif5_data_f_mux[] = {
RX5_F_MARK, TX5_F_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_a_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int scif_clk_a_mux[] = {
SCIF_CLK_A_MARK,
};
static const unsigned int scif_clk_b_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(3, 29),
};
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
};
static const unsigned int sdhi0_ctrl_mux[] = {
SD0_CLK_MARK, SD0_CMD_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
RCAR_GP_PIN(0, 11),
};
static const unsigned int sdhi0_cd_mux[] = {
SD0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
RCAR_GP_PIN(0, 12),
};
static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
RCAR_GP_PIN(0, 19),
};
static const unsigned int sdhi1_cd_mux[] = {
SD1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
RCAR_GP_PIN(0, 20),
};
static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
};
static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
};
static const unsigned int sdhi2_ctrl_mux[] = {
SD2_CLK_MARK, SD2_CMD_MARK,
};
static const unsigned int sdhi2_cd_pins[] = {
/* CD */
RCAR_GP_PIN(4, 20),
};
static const unsigned int sdhi2_cd_mux[] = {
SD2_CD_MARK,
};
static const unsigned int sdhi2_wp_pins[] = {
/* WP */
RCAR_GP_PIN(4, 21),
};
static const unsigned int sdhi2_wp_mux[] = {
SD2_WP_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
RCAR_GP_PIN(0, 0), /* PWEN */
RCAR_GP_PIN(0, 1), /* OVC */
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK,
USB0_OVC_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
RCAR_GP_PIN(0, 2), /* PWEN */
RCAR_GP_PIN(0, 3), /* OVC */
};
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK,
USB1_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const unsigned int vin0_data_pins[] = {
/* B */
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
};
static const unsigned int vin0_data_mux[] = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
};
static const unsigned int vin0_data18_mux[] = {
/* B */
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_sync_pins[] = {
RCAR_GP_PIN(5, 30), /* HSYNC */
RCAR_GP_PIN(5, 31), /* VSYNC */
};
static const unsigned int vin0_sync_mux[] = {
VI0_HSYNC_N_MARK,
VI0_VSYNC_N_MARK,
};
static const unsigned int vin0_field_pins[] = {
RCAR_GP_PIN(5, 29),
};
static const unsigned int vin0_field_mux[] = {
VI0_FIELD_MARK,
};
static const unsigned int vin0_clkenb_pins[] = {
RCAR_GP_PIN(5, 28),
};
static const unsigned int vin0_clkenb_mux[] = {
VI0_CLKENB_MARK,
};
static const unsigned int vin0_clk_pins[] = {
RCAR_GP_PIN(5, 18),
};
static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const unsigned int vin1_data_pins[] = {
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
};
static const unsigned int vin1_data_mux[] = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
};
static const unsigned int vin1_sync_pins[] = {
RCAR_GP_PIN(3, 11), /* HSYNC */
RCAR_GP_PIN(3, 12), /* VSYNC */
};
static const unsigned int vin1_sync_mux[] = {
VI1_HSYNC_N_MARK,
VI1_VSYNC_N_MARK,
};
static const unsigned int vin1_field_pins[] = {
RCAR_GP_PIN(3, 10),
};
static const unsigned int vin1_field_mux[] = {
VI1_FIELD_MARK,
};
static const unsigned int vin1_clkenb_pins[] = {
RCAR_GP_PIN(3, 9),
};
static const unsigned int vin1_clkenb_mux[] = {
VI1_CLKENB_MARK,
};
static const unsigned int vin1_clk_pins[] = {
RCAR_GP_PIN(3, 0),
};
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_col),
SH_PFC_PIN_GROUP(avb_crs),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii_tx_rx),
SH_PFC_PIN_GROUP(avb_mii_tx_er),
SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(du0_rgb666),
SH_PFC_PIN_GROUP(du0_rgb888),
SH_PFC_PIN_GROUP(du0_clk0_out),
SH_PFC_PIN_GROUP(du0_clk1_out),
SH_PFC_PIN_GROUP(du0_clk_in),
SH_PFC_PIN_GROUP(du0_sync),
SH_PFC_PIN_GROUP(du0_oddf),
SH_PFC_PIN_GROUP(du0_cde),
SH_PFC_PIN_GROUP(du0_disp),
SH_PFC_PIN_GROUP(du1_rgb666),
SH_PFC_PIN_GROUP(du1_rgb888),
SH_PFC_PIN_GROUP(du1_clk0_out),
SH_PFC_PIN_GROUP(du1_clk1_out),
SH_PFC_PIN_GROUP(du1_clk_in),
SH_PFC_PIN_GROUP(du1_sync),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_cde),
SH_PFC_PIN_GROUP(du1_disp),
SH_PFC_PIN_GROUP(i2c0_a),
SH_PFC_PIN_GROUP(i2c0_b),
SH_PFC_PIN_GROUP(i2c0_c),
SH_PFC_PIN_GROUP(i2c0_d),
SH_PFC_PIN_GROUP(i2c0_e),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
SH_PFC_PIN_GROUP(i2c1_d),
SH_PFC_PIN_GROUP(i2c1_e),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c2_c),
SH_PFC_PIN_GROUP(i2c2_d),
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(i2c3_c),
SH_PFC_PIN_GROUP(i2c3_d),
SH_PFC_PIN_GROUP(i2c3_e),
SH_PFC_PIN_GROUP(i2c4_a),
SH_PFC_PIN_GROUP(i2c4_b),
SH_PFC_PIN_GROUP(i2c4_c),
SH_PFC_PIN_GROUP(i2c4_d),
SH_PFC_PIN_GROUP(i2c4_e),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
BUS_DATA_PIN_GROUP(qspi1_data, 2),
BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
SH_PFC_PIN_GROUP(scif0_data_d),
SH_PFC_PIN_GROUP(scif1_data_a),
SH_PFC_PIN_GROUP(scif1_clk_a),
SH_PFC_PIN_GROUP(scif1_data_b),
SH_PFC_PIN_GROUP(scif1_clk_b),
SH_PFC_PIN_GROUP(scif1_data_c),
SH_PFC_PIN_GROUP(scif1_clk_c),
SH_PFC_PIN_GROUP(scif1_data_d),
SH_PFC_PIN_GROUP(scif2_data_a),
SH_PFC_PIN_GROUP(scif2_clk_a),
SH_PFC_PIN_GROUP(scif2_data_b),
SH_PFC_PIN_GROUP(scif2_clk_b),
SH_PFC_PIN_GROUP(scif2_data_c),
SH_PFC_PIN_GROUP(scif3_data_a),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_data_b),
SH_PFC_PIN_GROUP(scif3_data_c),
SH_PFC_PIN_GROUP(scif4_data_a),
SH_PFC_PIN_GROUP(scif4_data_b),
SH_PFC_PIN_GROUP(scif4_data_c),
SH_PFC_PIN_GROUP(scif4_data_d),
SH_PFC_PIN_GROUP(scif4_data_e),
SH_PFC_PIN_GROUP(scif5_data_a),
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif5_data_c),
SH_PFC_PIN_GROUP(scif5_data_d),
SH_PFC_PIN_GROUP(scif5_data_e),
SH_PFC_PIN_GROUP(scif5_data_f),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1),
SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4),
SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
BUS_DATA_PIN_GROUP(vin0_data, 24),
BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
BUS_DATA_PIN_GROUP(vin0_data, 16),
BUS_DATA_PIN_GROUP(vin0_data, 12),
BUS_DATA_PIN_GROUP(vin0_data, 10),
BUS_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
BUS_DATA_PIN_GROUP(vin1_data, 12),
BUS_DATA_PIN_GROUP(vin1_data, 10),
BUS_DATA_PIN_GROUP(vin1_data, 8),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
};
static const char * const avb_groups[] = {
"avb_col",
"avb_crs",
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdio",
"avb_mii_tx_rx",
"avb_mii_tx_er",
"avb_gmii_tx_rx",
"avb_avtp_match_a",
"avb_avtp_capture_a",
"avb_avtp_match_b",
"avb_avtp_capture_b",
};
static const char * const du0_groups[] = {
"du0_rgb666",
"du0_rgb888",
"du0_clk0_out",
"du0_clk1_out",
"du0_clk_in",
"du0_sync",
"du0_oddf",
"du0_cde",
"du0_disp",
};
static const char * const du1_groups[] = {
"du1_rgb666",
"du1_rgb888",
"du1_clk0_out",
"du1_clk1_out",
"du1_clk_in",
"du1_sync",
"du1_oddf",
"du1_cde",
"du1_disp",
};
static const char * const i2c0_groups[] = {
"i2c0_a",
"i2c0_b",
"i2c0_c",
"i2c0_d",
"i2c0_e",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
"i2c1_c",
"i2c1_d",
"i2c1_e",
};
static const char * const i2c2_groups[] = {
"i2c2_a",
"i2c2_b",
"i2c2_c",
"i2c2_d",
};
static const char * const i2c3_groups[] = {
"i2c3_a",
"i2c3_b",
"i2c3_c",
"i2c3_d",
"i2c3_e",
};
static const char * const i2c4_groups[] = {
"i2c4_a",
"i2c4_b",
"i2c4_c",
"i2c4_d",
"i2c4_e",
};
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
"mmc_ctrl",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_data_b",
"scif0_data_c",
"scif0_data_d",
};
static const char * const scif1_groups[] = {
"scif1_data_a",
"scif1_clk_a",
"scif1_data_b",
"scif1_clk_b",
"scif1_data_c",
"scif1_clk_c",
"scif1_data_d",
};
static const char * const scif2_groups[] = {
"scif2_data_a",
"scif2_clk_a",
"scif2_data_b",
"scif2_clk_b",
"scif2_data_c",
};
static const char * const scif3_groups[] = {
"scif3_data_a",
"scif3_clk",
"scif3_data_b",
"scif3_data_c",
};
static const char * const scif4_groups[] = {
"scif4_data_a",
"scif4_data_b",
"scif4_data_c",
"scif4_data_d",
"scif4_data_e",
};
static const char * const scif5_groups[] = {
"scif5_data_a",
"scif5_data_b",
"scif5_data_c",
"scif5_data_d",
"scif5_data_e",
"scif5_data_f",
};
static const char * const scif_clk_groups[] = {
"scif_clk_a",
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_ctrl",
"sdhi2_cd",
"sdhi2_wp",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const usb1_groups[] = {
"usb1",
};
static const char * const vin0_groups[] = {
"vin0_data24",
"vin0_data20",
"vin0_data18",
"vin0_data16",
"vin0_data12",
"vin0_data10",
"vin0_data8",
"vin0_sync",
"vin0_field",
"vin0_clkenb",
"vin0_clk",
};
static const char * const vin1_groups[] = {
"vin1_data12",
"vin1_data10",
"vin1_data8",
"vin1_sync",
"vin1_field",
"vin1_clkenb",
"vin1_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),
SH_PFC_FUNCTION(vin1),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_23 RESERVED */
GP_0_22_FN, FN_MMC0_D7,
GP_0_21_FN, FN_MMC0_D6,
GP_0_20_FN, FN_IP1_7_4,
GP_0_19_FN, FN_IP1_3_0,
GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
GP_0_12_FN, FN_IP0_31_28,
GP_0_11_FN, FN_IP0_27_24,
GP_0_10_FN, FN_IP0_23_20,
GP_0_9_FN, FN_IP0_19_16,
GP_0_8_FN, FN_IP0_15_12,
GP_0_7_FN, FN_IP0_11_8,
GP_0_6_FN, FN_IP0_7_4,
GP_0_5_FN, FN_IP0_3_0,
GP_0_4_FN, FN_CLKOUT,
GP_0_3_FN, FN_USB1_OVC,
GP_0_2_FN, FN_USB1_PWEN,
GP_0_1_FN, FN_USB0_OVC,
GP_0_0_FN, FN_USB0_PWEN, ))
},
{ PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP1_31_23 RESERVED */
GP_1_22_FN, FN_IP4_3_0,
GP_1_21_FN, FN_IP3_31_28,
GP_1_20_FN, FN_IP3_27_24,
GP_1_19_FN, FN_IP3_23_20,
GP_1_18_FN, FN_IP3_19_16,
GP_1_17_FN, FN_IP3_15_12,
GP_1_16_FN, FN_IP3_11_8,
GP_1_15_FN, FN_IP3_7_4,
GP_1_14_FN, FN_IP3_3_0,
GP_1_13_FN, FN_IP2_31_28,
GP_1_12_FN, FN_IP2_27_24,
GP_1_11_FN, FN_IP2_23_20,
GP_1_10_FN, FN_IP2_19_16,
GP_1_9_FN, FN_IP2_15_12,
GP_1_8_FN, FN_IP2_11_8,
GP_1_7_FN, FN_IP2_7_4,
GP_1_6_FN, FN_IP2_3_0,
GP_1_5_FN, FN_IP1_31_28,
GP_1_4_FN, FN_IP1_27_24,
GP_1_3_FN, FN_IP1_23_20,
GP_1_2_FN, FN_IP1_19_16,
GP_1_1_FN, FN_IP1_15_12,
GP_1_0_FN, FN_IP1_11_8, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP8_3_0,
GP_2_30_FN, FN_IP7_31_28,
GP_2_29_FN, FN_IP7_27_24,
GP_2_28_FN, FN_IP7_23_20,
GP_2_27_FN, FN_IP7_19_16,
GP_2_26_FN, FN_IP7_15_12,
GP_2_25_FN, FN_IP7_11_8,
GP_2_24_FN, FN_IP7_7_4,
GP_2_23_FN, FN_IP7_3_0,
GP_2_22_FN, FN_IP6_31_28,
GP_2_21_FN, FN_IP6_27_24,
GP_2_20_FN, FN_IP6_23_20,
GP_2_19_FN, FN_IP6_19_16,
GP_2_18_FN, FN_IP6_15_12,
GP_2_17_FN, FN_IP6_11_8,
GP_2_16_FN, FN_IP6_7_4,
GP_2_15_FN, FN_IP6_3_0,
GP_2_14_FN, FN_IP5_31_28,
GP_2_13_FN, FN_IP5_27_24,
GP_2_12_FN, FN_IP5_23_20,
GP_2_11_FN, FN_IP5_19_16,
GP_2_10_FN, FN_IP5_15_12,
GP_2_9_FN, FN_IP5_11_8,
GP_2_8_FN, FN_IP5_7_4,
GP_2_7_FN, FN_IP5_3_0,
GP_2_6_FN, FN_IP4_31_28,
GP_2_5_FN, FN_IP4_27_24,
GP_2_4_FN, FN_IP4_23_20,
GP_2_3_FN, FN_IP4_19_16,
GP_2_2_FN, FN_IP4_15_12,
GP_2_1_FN, FN_IP4_11_8,
GP_2_0_FN, FN_IP4_7_4, ))
},
{ PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32,
GROUP(-2, 1, 1, -10, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP3_31_30 RESERVED */
GP_3_29_FN, FN_IP10_19_16,
GP_3_28_FN, FN_IP10_15_12,
GP_3_27_FN, FN_IP10_11_8,
/* GP3_26_17 RESERVED */
GP_3_16_FN, FN_IP10_7_4,
GP_3_15_FN, FN_IP10_3_0,
GP_3_14_FN, FN_IP9_31_28,
GP_3_13_FN, FN_IP9_27_24,
GP_3_12_FN, FN_IP9_23_20,
GP_3_11_FN, FN_IP9_19_16,
GP_3_10_FN, FN_IP9_15_12,
GP_3_9_FN, FN_IP9_11_8,
GP_3_8_FN, FN_IP9_7_4,
GP_3_7_FN, FN_IP9_3_0,
GP_3_6_FN, FN_IP8_31_28,
GP_3_5_FN, FN_IP8_27_24,
GP_3_4_FN, FN_IP8_23_20,
GP_3_3_FN, FN_IP8_19_16,
GP_3_2_FN, FN_IP8_15_12,
GP_3_1_FN, FN_IP8_11_8,
GP_3_0_FN, FN_IP8_7_4, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
GP_4_25_FN, FN_IP13_27_24,
GP_4_24_FN, FN_IP13_23_20,
GP_4_23_FN, FN_IP13_19_16,
GP_4_22_FN, FN_IP13_15_12,
GP_4_21_FN, FN_IP13_11_8,
GP_4_20_FN, FN_IP13_7_4,
GP_4_19_FN, FN_IP13_3_0,
GP_4_18_FN, FN_IP12_31_28,
GP_4_17_FN, FN_IP12_27_24,
GP_4_16_FN, FN_IP12_23_20,
GP_4_15_FN, FN_IP12_19_16,
GP_4_14_FN, FN_IP12_15_12,
GP_4_13_FN, FN_IP12_11_8,
GP_4_12_FN, FN_IP12_7_4,
GP_4_11_FN, FN_IP12_3_0,
GP_4_10_FN, FN_IP11_31_28,
GP_4_9_FN, FN_IP11_27_24,
GP_4_8_FN, FN_IP11_23_20,
GP_4_7_FN, FN_IP11_19_16,
GP_4_6_FN, FN_IP11_15_12,
GP_4_5_FN, FN_IP11_11_8,
GP_4_4_FN, FN_IP11_7_4,
GP_4_3_FN, FN_IP11_3_0,
GP_4_2_FN, FN_IP10_31_28,
GP_4_1_FN, FN_IP10_27_24,
GP_4_0_FN, FN_IP10_23_20, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP17_27_24,
GP_5_30_FN, FN_IP17_23_20,
GP_5_29_FN, FN_IP17_19_16,
GP_5_28_FN, FN_IP17_15_12,
GP_5_27_FN, FN_IP17_11_8,
GP_5_26_FN, FN_IP17_7_4,
GP_5_25_FN, FN_IP17_3_0,
GP_5_24_FN, FN_IP16_31_28,
GP_5_23_FN, FN_IP16_27_24,
GP_5_22_FN, FN_IP16_23_20,
GP_5_21_FN, FN_IP16_19_16,
GP_5_20_FN, FN_IP16_15_12,
GP_5_19_FN, FN_IP16_11_8,
GP_5_18_FN, FN_IP16_7_4,
GP_5_17_FN, FN_IP16_3_0,
GP_5_16_FN, FN_IP15_31_28,
GP_5_15_FN, FN_IP15_27_24,
GP_5_14_FN, FN_IP15_23_20,
GP_5_13_FN, FN_IP15_19_16,
GP_5_12_FN, FN_IP15_15_12,
GP_5_11_FN, FN_IP15_11_8,
GP_5_10_FN, FN_IP15_7_4,
GP_5_9_FN, FN_IP15_3_0,
GP_5_8_FN, FN_IP14_31_28,
GP_5_7_FN, FN_IP14_27_24,
GP_5_6_FN, FN_IP14_23_20,
GP_5_5_FN, FN_IP14_19_16,
GP_5_4_FN, FN_IP14_15_12,
GP_5_3_FN, FN_IP14_11_8,
GP_5_2_FN, FN_IP14_7_4,
GP_5_1_FN, FN_IP14_3_0,
GP_5_0_FN, FN_IP13_31_28, ))
},
{ PINMUX_CFG_REG("IPSR0", 0xE6060040, 32, 4, GROUP(
/* IP0_31_28 [4] */
FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_23_20 [4] */
FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_19_16 [4] */
FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_15_12 [4] */
FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_11_8 [4] */
FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_7_4 [4] */
FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_3_0 [4] */
FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 4, GROUP(
/* IP1_31_28 [4] */
FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_23_20 [4] */
FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_19_16 [4] */
FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_15_12 [4] */
FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_11_8 [4] */
FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_7_4 [4] */
FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_3_0 [4] */
FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 4, GROUP(
/* IP2_31_28 [4] */
FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_23_20 [4] */
FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP2_19_16 [4] */
FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP2_15_12 [4] */
FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_11_8 [4] */
FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_7_4 [4] */
FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_3_0 [4] */
FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 4, GROUP(
/* IP3_31_28 [4] */
FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP3_27_24 [4] */
FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP3_23_20 [4] */
FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP3_19_16 [4] */
FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* IP3_15_12 [4] */
FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
/* IP3_11_8 [4] */
FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP3_7_4 [4] */
FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_3_0 [4] */
FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
0, FN_AVB_AVTP_CAPTURE_A,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR4", 0xE6060050, 32, 4, GROUP(
/* IP4_31_28 [4] */
FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_24 [4] */
FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_23_20 [4] */
FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP4_19_16 [4] */
FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_15_12 [4] */
FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_11_8 [4] */
FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_7_4 [4] */
FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_3_0 [4] */
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 4, GROUP(
/* IP5_31_28 [4] */
FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_23_20 [4] */
FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP5_19_16 [4] */
FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_15_12 [4] */
FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP5_11_8 [4] */
FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_7_4 [4] */
FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_3_0 [4] */
FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR6", 0xE6060058, 32, 4, GROUP(
/* IP6_31_28 [4] */
FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_23_20 [4] */
FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_19_16 [4] */
FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP6_15_12 [4] */
FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP6_11_8 [4] */
FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_7_4 [4] */
FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_3_0 [4] */
FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR7", 0xE606005C, 32, 4, GROUP(
/* IP7_31_28 [4] */
FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_23_20 [4] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_19_16 [4] */
FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_15_12 [4] */
FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_11_8 [4] */
FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP7_7_4 [4] */
FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP7_3_0 [4] */
FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR8", 0xE6060060, 32, 4, GROUP(
/* IP8_31_28 [4] */
FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP8_27_24 [4] */
FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP8_23_20 [4] */
FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP8_19_16 [4] */
FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP8_15_12 [4] */
FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP8_11_8 [4] */
FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP8_7_4 [4] */
FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP8_3_0 [4] */
FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR9", 0xE6060064, 32, 4, GROUP(
/* IP9_31_28 [4] */
FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP9_27_24 [4] */
FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP9_23_20 [4] */
FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP9_19_16 [4] */
FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP9_15_12 [4] */
FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP9_11_8 [4] */
FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP9_7_4 [4] */
FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP9_3_0 [4] */
FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR10", 0xE6060068, 32, 4, GROUP(
/* IP10_31_28 [4] */
FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP10_27_24 [4] */
FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP10_23_20 [4] */
FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP10_19_16 [4] */
FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP10_15_12 [4] */
FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP10_11_8 [4] */
FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP10_7_4 [4] */
FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
/* IP10_3_0 [4] */
FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR11", 0xE606006C, 32, 4, GROUP(
/* IP11_31_28 [4] */
FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_27_24 [4] */
FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_23_20 [4] */
FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_19_16 [4] */
FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
0, 0, 0, 0,
/* IP11_15_12 [4] */
FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_11_8 [4] */
FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_7_4 [4] */
FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_3_0 [4] */
FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR12", 0xE6060070, 32, 4, GROUP(
/* IP12_31_28 [4] */
FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_27_24 [4] */
FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_23_20 [4] */
FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_19_16 [4] */
FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_15_12 [4] */
FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_11_8 [4] */
FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_7_4 [4] */
FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_3_0 [4] */
FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR13", 0xE6060074, 32, 4, GROUP(
/* IP13_31_28 [4] */
FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP13_27_24 [4] */
FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_23_20 [4] */
FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_19_16 [4] */
FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_15_12 [4] */
FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
/* IP13_11_8 [4] */
FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_7_4 [4] */
FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_3_0 [4] */
FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR14", 0xE6060078, 32, 4, GROUP(
/* IP14_31_28 [4] */
FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_27_24 [4] */
FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
/* IP14_23_20 [4] */
FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP14_19_16 [4] */
FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_15_12 [4] */
FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_11_8 [4] */
FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_7_4 [4] */
FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_3_0 [4] */
FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR15", 0xE606007C, 32, 4, GROUP(
/* IP15_31_28 [4] */
FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP15_27_24 [4] */
FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
0, 0, 0, 0, 0, 0,
/* IP15_23_20 [4] */
FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_19_16 [4] */
FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_15_12 [4] */
FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_11_8 [4] */
FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_7_4 [4] */
FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_3_0 [4] */
FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("IPSR16", 0xE6060080, 32, 4, GROUP(
/* IP16_31_28 [4] */
FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_27_24 [4] */
FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_23_20 [4] */
FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_19_16 [4] */
FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_15_12 [4] */
FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
0, 0, 0,
/* IP16_11_8 [4] */
FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_7_4 [4] */
FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_3_0 [4] */
FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP17_31_28 [4] RESERVED */
/* IP17_27_24 [4] */
FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_23_20 [4] */
FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_19_16 [4] */
FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_15_12 [4] */
FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_11_8 [4] */
FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_7_4 [4] */
FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_3_0 [4] */
FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
GROUP(-5, 2, -2, 2, 2, 2, -1,
3, 3, -1, 2, 3, 3, 1),
GROUP(
/* RESERVED [5] */
/* SEL_ADGA [2] */
FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
/* RESERVED [2] */
/* SEL_CANCLK [2] */
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
FN_SEL_CANCLK_3,
/* SEL_CAN1 [2] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
/* SEL_CAN0 [2] */
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
/* RESERVED [1] */
/* SEL_I2C04 [3] */
FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
FN_SEL_I2C04_4, 0, 0, 0,
/* SEL_I2C03 [3] */
FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
FN_SEL_I2C03_4, 0, 0, 0,
/* RESERVED [1] */
/* SEL_I2C02 [2] */
FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
/* SEL_I2C01 [3] */
FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
FN_SEL_I2C01_4, 0, 0, 0,
/* SEL_I2C00 [3] */
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
FN_SEL_I2C00_4, 0, 0, 0,
/* SEL_AVB [1] */
FN_SEL_AVB_0, FN_SEL_AVB_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, -1, 1, -1,
1, 1, -2, 1, 1, -2, 2, 1),
GROUP(
/* SEL_SCIFCLK [1] */
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
/* SEL_SCIF5 [3] */
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
/* SEL_SCIF4 [3] */
FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
FN_SEL_SCIF4_4, 0, 0, 0,
/* SEL_SCIF3 [2] */
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
/* SEL_SCIF2 [2] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
/* SEL_SCIF2_CLK [1] */
FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
/* SEL_SCIF1 [2] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
/* SEL_MSIOF2 [2] */
FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
/* RESERVED [1] */
/* SEL_MSIOF1 [1] */
FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
/* RESERVED [1] */
/* SEL_MSIOF0 [1] */
FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
/* SEL_RCN [1] */
FN_SEL_RCN_0, FN_SEL_RCN_1,
/* RESERVED [2] */
/* SEL_TMU2 [1] */
FN_SEL_TMU2_0, FN_SEL_TMU2_1,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* RESERVED [2] */
/* SEL_HSCIF1 [2] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
/* SEL_HSCIF0 [1] */
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
GROUP(-10, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* RESERVED [10] */
/* SEL_ADGB [2] */
FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
/* SEL_ADGC [2] */
FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
/* SEL_SSI9 [2] */
FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
/* SEL_SSI8 [2] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
/* SEL_SSI7 [2] */
FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
/* SEL_SSI6 [2] */
FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
/* SEL_SSI5 [2] */
FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
/* SEL_SSI4 [2] */
FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
/* SEL_SSI2 [2] */
FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
/* SEL_SSI1 [2] */
FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
/* SEL_SSI0 [2] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
},
{ /* sentinel */ }
};
static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = 0xe60600b0;
if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
bit = 0;
if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
bit = 2;
if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
bit = 1;
return bit;
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
/* PUPR0 pull-up pins */
[ 0] = RCAR_GP_PIN(1, 0), /* D0 */
[ 1] = RCAR_GP_PIN(0, 22), /* MMC0_D7 */
[ 2] = RCAR_GP_PIN(0, 21), /* MMC0_D6 */
[ 3] = RCAR_GP_PIN(0, 20), /* MMC0_D5 */
[ 4] = RCAR_GP_PIN(0, 19), /* MMC0_D4 */
[ 5] = RCAR_GP_PIN(0, 18), /* MMC0_D3 */
[ 6] = RCAR_GP_PIN(0, 17), /* MMC0_D2 */
[ 7] = RCAR_GP_PIN(0, 16), /* MMC0_D1 */
[ 8] = RCAR_GP_PIN(0, 15), /* MMC0_D0 */
[ 9] = RCAR_GP_PIN(0, 14), /* MMC0_CMD */
[10] = RCAR_GP_PIN(0, 13), /* MMC0_CLK */
[11] = RCAR_GP_PIN(0, 12), /* SD0_WP */
[12] = RCAR_GP_PIN(0, 11), /* SD0_CD */
[13] = RCAR_GP_PIN(0, 10), /* SD0_DAT3 */
[14] = RCAR_GP_PIN(0, 9), /* SD0_DAT2 */
[15] = RCAR_GP_PIN(0, 8), /* SD0_DAT1 */
[16] = RCAR_GP_PIN(0, 7), /* SD0_DAT0 */
[17] = RCAR_GP_PIN(0, 6), /* SD0_CMD */
[18] = RCAR_GP_PIN(0, 5), /* SD0_CLK */
[19] = RCAR_GP_PIN(0, 4), /* CLKOUT */
[20] = PIN_NMI, /* NMI */
[21] = RCAR_GP_PIN(0, 3), /* USB1_OVC */
[22] = RCAR_GP_PIN(0, 2), /* USB1_PWEN */
[23] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
[24] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
[25] = SH_PFC_PIN_NONE,
[26] = PIN_TDO, /* TDO */
[27] = PIN_TDI, /* TDI */
[28] = PIN_TMS, /* TMS */
[29] = PIN_TCK, /* TCK */
[30] = PIN_TRST_N, /* TRST# */
[31] = PIN_PRESETOUT_N, /* PRESETOUT# */
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
/* PUPR0 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
[ 1] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */
[ 2] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */
[ 3] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */
[ 4] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
[ 5] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
[ 6] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */
[ 7] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */
[ 8] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */
[ 9] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
[10] = RCAR_GP_PIN(1, 22), /* EX_WAIT0 */
[11] = RCAR_GP_PIN(1, 21), /* QSPI0_SSL */
[12] = RCAR_GP_PIN(1, 20), /* QSPI0_IO3 */
[13] = RCAR_GP_PIN(1, 19), /* QSPI0_IO2 */
[14] = RCAR_GP_PIN(1, 18), /* QSPI0_MISO/QSPI0_IO1 */
[15] = RCAR_GP_PIN(1, 17), /* QSPI0_MOSI/QSPI0_IO0 */
[16] = RCAR_GP_PIN(1, 16), /* QSPI0_SPCLK */
[17] = RCAR_GP_PIN(1, 15), /* D15 */
[18] = RCAR_GP_PIN(1, 14), /* D14 */
[19] = RCAR_GP_PIN(1, 13), /* D13 */
[20] = RCAR_GP_PIN(1, 12), /* D12 */
[21] = RCAR_GP_PIN(1, 11), /* D11 */
[22] = RCAR_GP_PIN(1, 10), /* D10 */
[23] = RCAR_GP_PIN(1, 9), /* D9 */
[24] = RCAR_GP_PIN(1, 8), /* D8 */
[25] = RCAR_GP_PIN(1, 7), /* D7 */
[26] = RCAR_GP_PIN(1, 6), /* D6 */
[27] = RCAR_GP_PIN(1, 5), /* D5 */
[28] = RCAR_GP_PIN(1, 4), /* D4 */
[29] = RCAR_GP_PIN(1, 3), /* D3 */
[30] = RCAR_GP_PIN(1, 2), /* D2 */
[31] = RCAR_GP_PIN(1, 1), /* D1 */
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 9), /* VI1_CLKENB */
[ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */
[ 2] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */
[ 3] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */
[ 4] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
[ 5] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
[ 6] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */
[ 7] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */
[ 8] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */
[ 9] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
[10] = RCAR_GP_PIN(2, 31), /* DU0_CDE */
[11] = RCAR_GP_PIN(2, 30), /* DU0_DISP */
[12] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
[13] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */
[14] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */
[15] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */
[16] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */
[17] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */
[18] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */
[19] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */
[20] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */
[21] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */
[22] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */
[23] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */
[24] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */
[25] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */
[26] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */
[27] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */
[28] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */
[29] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */
[30] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */
[31] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 21), /* SD2_WP */
[ 1] = RCAR_GP_PIN(4, 20), /* SD2_CD */
[ 2] = RCAR_GP_PIN(4, 19), /* SD2_DAT3 */
[ 3] = RCAR_GP_PIN(4, 18), /* SD2_DAT2 */
[ 4] = RCAR_GP_PIN(4, 17), /* SD2_DAT1 */
[ 5] = RCAR_GP_PIN(4, 16), /* SD2_DAT0 */
[ 6] = RCAR_GP_PIN(4, 15), /* SD2_CMD */
[ 7] = RCAR_GP_PIN(4, 14), /* SD2_CLK */
[ 8] = RCAR_GP_PIN(4, 13), /* HRTS1#_A */
[ 9] = RCAR_GP_PIN(4, 12), /* HCTS1#_A */
[10] = RCAR_GP_PIN(4, 11), /* HTX1_A */
[11] = RCAR_GP_PIN(4, 10), /* HRX1_A */
[12] = RCAR_GP_PIN(4, 9), /* MSIOF0_SS2_A */
[13] = RCAR_GP_PIN(4, 8), /* MSIOF0_SS1_A */
[14] = RCAR_GP_PIN(4, 7), /* MSIOF0_SYNC_A */
[15] = RCAR_GP_PIN(4, 6), /* MSIOF0_SCK_A */
[16] = RCAR_GP_PIN(4, 5), /* MSIOF0_TXD_A */
[17] = RCAR_GP_PIN(4, 4), /* MSIOF0_RXD_A */
[18] = RCAR_GP_PIN(4, 3), /* SDA1_A */
[19] = RCAR_GP_PIN(4, 2), /* SCL1_A */
[20] = RCAR_GP_PIN(4, 1), /* SDA0_A */
[21] = RCAR_GP_PIN(4, 0), /* SCL0_A */
[22] = RCAR_GP_PIN(3, 29), /* AVB_TXD5 */
[23] = RCAR_GP_PIN(3, 28), /* AVB_TXD4 */
[24] = RCAR_GP_PIN(3, 27), /* AVB_TXD3 */
[25] = RCAR_GP_PIN(3, 16), /* VI1_DATA11 */
[26] = RCAR_GP_PIN(3, 15), /* VI1_DATA10 */
[27] = RCAR_GP_PIN(3, 14), /* VI1_DATA9 */
[28] = RCAR_GP_PIN(3, 13), /* VI1_DATA8 */
[29] = RCAR_GP_PIN(3, 12), /* VI1_VSYNC# */
[30] = RCAR_GP_PIN(3, 11), /* VI1_HSYNC# */
[31] = RCAR_GP_PIN(3, 10), /* VI1_FIELD */
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 27), /* SSI_SDATA9_A */
[ 1] = RCAR_GP_PIN(5, 26), /* SSI_WS9_A */
[ 2] = RCAR_GP_PIN(5, 25), /* SSI_SCK9_A */
[ 3] = RCAR_GP_PIN(5, 24), /* SSI_SDATA2_A */
[ 4] = RCAR_GP_PIN(5, 23), /* SSI_WS2_A */
[ 5] = RCAR_GP_PIN(5, 22), /* SSI_SCK2_A */
[ 6] = RCAR_GP_PIN(5, 21), /* SSI_SDATA1_A */
[ 7] = RCAR_GP_PIN(5, 20), /* SSI_WS1_A */
[ 8] = RCAR_GP_PIN(5, 19), /* SSI_SDATA8_A */
[ 9] = RCAR_GP_PIN(5, 18), /* SSI_SCK1_A */
[10] = RCAR_GP_PIN(5, 17), /* SSI_SDATA4_A */
[11] = RCAR_GP_PIN(5, 16), /* SSI_WS4_A */
[12] = RCAR_GP_PIN(5, 15), /* SSI_SCK4_A */
[13] = RCAR_GP_PIN(5, 14), /* SSI_SDATA3 */
[14] = RCAR_GP_PIN(5, 13), /* SSI_WS34 */
[15] = RCAR_GP_PIN(5, 12), /* SSI_SCK34 */
[16] = RCAR_GP_PIN(5, 11), /* SSI_SDATA0_A */
[17] = RCAR_GP_PIN(5, 10), /* SSI_WS0129_A */
[18] = RCAR_GP_PIN(5, 9), /* SSI_SCK0129_A */
[19] = RCAR_GP_PIN(5, 8), /* SSI_SDATA7_A */
[20] = RCAR_GP_PIN(5, 7), /* SSI_WS78_A */
[21] = RCAR_GP_PIN(5, 6), /* SSI_SCK78_A */
[22] = RCAR_GP_PIN(5, 5), /* SSI_SDATA6_A */
[23] = RCAR_GP_PIN(5, 4), /* SSI_WS6_A */
[24] = RCAR_GP_PIN(5, 3), /* SSI_SCK6_A */
[25] = RCAR_GP_PIN(5, 2), /* SSI_SDATA5_A */
[26] = RCAR_GP_PIN(5, 1), /* SSI_WS5_A */
[27] = RCAR_GP_PIN(5, 0), /* SSI_SCK5_A */
[28] = RCAR_GP_PIN(4, 25), /* SDA2_A */
[29] = RCAR_GP_PIN(4, 24), /* SCL2_A */
[30] = RCAR_GP_PIN(4, 23), /* TX3_A */
[31] = RCAR_GP_PIN(4, 22), /* RX3_A */
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = RCAR_GP_PIN(5, 31), /* AUDIO_CLKOUT_A */
[29] = RCAR_GP_PIN(5, 30), /* AUDIO_CLKC_A */
[30] = RCAR_GP_PIN(5, 29), /* AUDIO_CLKB_A */
[31] = RCAR_GP_PIN(5, 28), /* AUDIO_CLKA_A */
} },
{ /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77470_pfc_ops = {
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A77470
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
.name = "r8a77470_pfc",
.ops = &r8a77470_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a77470.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A7740 processor support
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <[email protected]>
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
PORT_10(200, fn, pfx##20, sfx), \
PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
#define IRQC_PIN_MUX(irq, pin) \
static const unsigned int intc_irq##irq##_pins[] = { \
pin, \
}; \
static const unsigned int intc_irq##irq##_mux[] = { \
IRQ##irq##_MARK, \
}
#define IRQC_PINS_MUX(irq, idx, pin) \
static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
pin, \
}; \
static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
IRQ##irq##_PORT##pin##_MARK, \
}
enum {
PINMUX_RESERVED = 0,
/* PORT0_DATA -> PORT211_DATA */
PINMUX_DATA_BEGIN,
PORT_ALL(DATA),
PINMUX_DATA_END,
/* PORT0_IN -> PORT211_IN */
PINMUX_INPUT_BEGIN,
PORT_ALL(IN),
PINMUX_INPUT_END,
/* PORT0_OUT -> PORT211_OUT */
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT),
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
MSEL1CR_28_0, MSEL1CR_28_1,
MSEL1CR_27_0, MSEL1CR_27_1,
MSEL1CR_26_0, MSEL1CR_26_1,
MSEL1CR_16_0, MSEL1CR_16_1,
MSEL1CR_15_0, MSEL1CR_15_1,
MSEL1CR_14_0, MSEL1CR_14_1,
MSEL1CR_13_0, MSEL1CR_13_1,
MSEL1CR_12_0, MSEL1CR_12_1,
MSEL1CR_9_0, MSEL1CR_9_1,
MSEL1CR_7_0, MSEL1CR_7_1,
MSEL1CR_6_0, MSEL1CR_6_1,
MSEL1CR_5_0, MSEL1CR_5_1,
MSEL1CR_4_0, MSEL1CR_4_1,
MSEL1CR_3_0, MSEL1CR_3_1,
MSEL1CR_2_0, MSEL1CR_2_1,
MSEL1CR_0_0, MSEL1CR_0_1,
MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
MSEL3CR_6_0, MSEL3CR_6_1,
MSEL4CR_19_0, MSEL4CR_19_1,
MSEL4CR_18_0, MSEL4CR_18_1,
MSEL4CR_15_0, MSEL4CR_15_1,
MSEL4CR_10_0, MSEL4CR_10_1,
MSEL4CR_6_0, MSEL4CR_6_1,
MSEL4CR_4_0, MSEL4CR_4_1,
MSEL4CR_1_0, MSEL4CR_1_1,
MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
MSEL5CR_27_0, MSEL5CR_27_1,
MSEL5CR_25_0, MSEL5CR_25_1,
MSEL5CR_23_0, MSEL5CR_23_1,
MSEL5CR_21_0, MSEL5CR_21_1,
MSEL5CR_19_0, MSEL5CR_19_1,
MSEL5CR_17_0, MSEL5CR_17_1,
MSEL5CR_15_0, MSEL5CR_15_1,
MSEL5CR_14_0, MSEL5CR_14_1,
MSEL5CR_13_0, MSEL5CR_13_1,
MSEL5CR_12_0, MSEL5CR_12_1,
MSEL5CR_11_0, MSEL5CR_11_1,
MSEL5CR_10_0, MSEL5CR_10_1,
MSEL5CR_8_0, MSEL5CR_8_1,
MSEL5CR_7_0, MSEL5CR_7_1,
MSEL5CR_6_0, MSEL5CR_6_1,
MSEL5CR_5_0, MSEL5CR_5_1,
MSEL5CR_4_0, MSEL5CR_4_1,
MSEL5CR_3_0, MSEL5CR_3_1,
MSEL5CR_2_0, MSEL5CR_2_1,
MSEL5CR_0_0, MSEL5CR_0_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* IRQ */
IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
IRQ1_MARK,
IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
IRQ8_MARK,
IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
IRQ10_MARK,
IRQ11_MARK,
IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
IRQ17_MARK,
IRQ18_MARK,
IRQ19_MARK,
IRQ20_MARK,
IRQ21_MARK,
IRQ22_MARK,
IRQ23_MARK,
IRQ24_MARK,
IRQ25_MARK,
IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
/* Function */
/* DBGT */
DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
DBGMD21_MARK,
/* FSI-A */
FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
FSIAISLD_PORT5_MARK,
FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
FSIASPDIF_PORT18_MARK,
FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
/* FSI-B */
FSIBCK_MARK,
/* FMSI */
FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
FMSISLD_PORT6_MARK,
FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
/* SCIFA0 */
SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
/* SCIFA1 */
SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
/* SCIFA2 */
SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
SCIFA2_SCK_PORT199_MARK,
SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
/* SCIFA3 */
SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
SCIFA3_SCK_PORT116_MARK,
SCIFA3_CTS_PORT117_MARK,
SCIFA3_RXD_PORT174_MARK,
SCIFA3_TXD_PORT175_MARK,
SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
SCIFA3_SCK_PORT158_MARK,
SCIFA3_CTS_PORT162_MARK,
SCIFA3_RXD_PORT159_MARK,
SCIFA3_TXD_PORT160_MARK,
/* SCIFA4 */
SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
SCIFA4_TXD_PORT13_MARK,
SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
SCIFA4_TXD_PORT203_MARK,
SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
SCIFA4_TXD_PORT93_MARK,
SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
SCIFA4_SCK_PORT205_MARK,
/* SCIFA5 */
SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
SCIFA5_RXD_PORT10_MARK,
SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
SCIFA5_TXD_PORT208_MARK,
SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
SCIFA5_RXD_PORT92_MARK,
SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
SCIFA5_SCK_PORT206_MARK,
/* SCIFA6 */
SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
/* SCIFA7 */
SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
/* SCIFB */
SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
SCIFB_RXD_PORT191_MARK,
SCIFB_TXD_PORT192_MARK,
SCIFB_RTS_PORT186_MARK,
SCIFB_CTS_PORT187_MARK,
SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
SCIFB_RXD_PORT3_MARK,
SCIFB_TXD_PORT4_MARK,
SCIFB_RTS_PORT172_MARK,
SCIFB_CTS_PORT173_MARK,
/* LCD0 */
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK,
LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
LCD0_LCLK_PORT165_MARK,
LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
LCD0_LCLK_PORT102_MARK,
/* LCD1 */
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
LCD1_DON_MARK, LCD1_VCPWC_MARK,
LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
/* RSPI */
RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
RSPI_MISO_A_MARK,
/* VIO CKO */
VIO_CKO1_MARK, /* needs fixup */
VIO_CKO2_MARK,
VIO_CKO_1_MARK,
VIO_CKO_MARK,
/* VIO0 */
VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
VIO0_FIELD_MARK,
VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
VIO0_D14_PORT25_MARK,
VIO0_D15_PORT24_MARK,
VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
VIO0_D14_PORT95_MARK,
VIO0_D15_PORT96_MARK,
/* VIO1 */
VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
/* TPU0 */
TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
TPU0TO2_PORT202_MARK,
/* SSP1 0 */
STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
/* SSP1 1 */
STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
STP1_IPSYNC_MARK,
STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
STP1_IPEN_PORT187_MARK,
STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
STP1_IPEN_PORT193_MARK,
/* SIM */
SIM_RST_MARK, SIM_CLK_MARK,
SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
SIM_D_PORT199_MARK,
/* SDHI0 */
SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
/* SDHI1 */
SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
/* SDHI2 */
SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
SDHI2_CLK_MARK, SDHI2_CMD_MARK,
SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
SDHI2_WP_PORT25_MARK,
SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
SDHI2_CD_PORT202_MARK,
/* MSIOF2 */
MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
MSIOF2_RSCK_MARK,
/* KEYSC */
KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
KEYIN1_PORT44_MARK,
KEYIN2_PORT45_MARK,
KEYIN3_PORT46_MARK,
KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
KEYIN1_PORT57_MARK,
KEYIN2_PORT56_MARK,
KEYIN3_PORT55_MARK,
/* VOU */
DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
/* MEMC */
MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
MEMC_CS1_MARK, /* MSEL4CR_6_0 */
MEMC_ADV_MARK,
MEMC_WAIT_MARK,
MEMC_BUSCLK_MARK,
MEMC_A1_MARK, /* MSEL4CR_6_1 */
MEMC_DREQ0_MARK,
MEMC_DREQ1_MARK,
MEMC_A0_MARK,
/* MMC */
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
/* MSIOF0 */
MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
MSIOF0_TSYNC_MARK,
/* MSIOF1 */
MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
MSIOF1_TSYNC_PORT120_MARK,
MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
MSIOF1_RXD_PORT75_MARK,
MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
/* GPIO */
GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
/* USB0 */
USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
/* USB1 */
USB1_OCI_MARK, USB1_PPON_MARK,
/* BBIF1 */
BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
/* BBIF2 */
BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
BBIF2_RXD2_PORT60_MARK,
BBIF2_TSYNC2_PORT6_MARK,
BBIF2_TSCK2_PORT59_MARK,
BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
BBIF2_TXD2_PORT183_MARK,
BBIF2_TSCK2_PORT89_MARK,
BBIF2_TSYNC2_PORT184_MARK,
/* BSC / FLCTL / PCMCIA */
CS0_MARK, CS2_MARK, CS4_MARK,
CS5B_MARK, CS6A_MARK,
CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
CS5A_PORT19_MARK,
IOIS16_MARK, /* ? */
A0_MARK, A1_MARK, A2_MARK, A3_MARK,
A4_FOE_MARK, /* share with FLCTL */
A5_FCDE_MARK, /* share with FLCTL */
A6_MARK, A7_MARK, A8_MARK, A9_MARK,
A10_MARK, A11_MARK, A12_MARK, A13_MARK,
A14_MARK, A15_MARK, A16_MARK, A17_MARK,
A18_MARK, A19_MARK, A20_MARK, A21_MARK,
A22_MARK, A23_MARK, A24_MARK, A25_MARK,
A26_MARK,
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
D15_NAF15_MARK, /* share with FLCTL */
D16_MARK, D17_MARK, D18_MARK, D19_MARK,
D20_MARK, D21_MARK, D22_MARK, D23_MARK,
D24_MARK, D25_MARK, D26_MARK, D27_MARK,
D28_MARK, D29_MARK, D30_MARK, D31_MARK,
WE0_FWE_MARK, /* share with FLCTL */
WE1_MARK,
WE2_ICIORD_MARK, /* share with PCMCIA */
WE3_ICIOWR_MARK, /* share with PCMCIA */
CKO_MARK, BS_MARK, RDWR_MARK,
RD_FSC_MARK, /* share with FLCTL */
WAIT_PORT177_MARK, /* WAIT Port 90/177 */
WAIT_PORT90_MARK,
FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
/* IRDA */
IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
/* ATAPI */
IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
/* RMII */
RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
RMII_REF50CK_MARK, /* for RMII */
RMII_REF125CK_MARK, /* for GMII */
/* GEther */
ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
ET_ETXD2_MARK, ET_ETXD3_MARK,
ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
/* DMA0 */
DREQ0_MARK, DACK0_MARK,
/* DMA1 */
DREQ1_MARK, DACK1_MARK,
/* SYSC */
RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
/* IRREM */
IROUT_MARK,
/* SDENC */
SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
/* HDMI */
HDMI_HPD_MARK, HDMI_CEC_MARK,
/* DEBUG */
EDEBGREQ_PULLUP_MARK, /* for JTAG */
EDEBGREQ_PULLDOWN_MARK,
TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
TRACEAUD_FROM_LCDC0_MARK,
TRACEAUD_FROM_MEMC_MARK,
PINMUX_MARK_END,
};
static const u16 pinmux_data[] = {
PINMUX_DATA_ALL(),
/* Port0 */
PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
/* Port1 */
PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
/* Port2 */
PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
/* Port3 */
PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
/* Port4 */
PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
/* Port5 */
PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
/* Port6 */
PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
/* Port7 */
PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
/* Port8 */
PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
/* Port9 */
PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
/* Port10 */
PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
/* Port11 */
PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
/* Port12 */
PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
/* Port13 */
PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
/* Port14 */
PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
/* Port15 */
PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
/* Port16 */
PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
/* Port17 */
PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
/* Port18 */
PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
/* Port19 */
PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
/* Port20 */
PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
/* Port21 */
PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
/* Port22 */
PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
/* Port23 */
PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
/* Port24 */
PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
/* Port25 */
PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
/* Port26 */
PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
/* Port27 - Port39 Function */
PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
/* Port38 IRQ */
PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
/* Port40 */
PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
/* Port41 */
PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
/* Port42 */
PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
/* Port43 */
PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
/* Port44 */
PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
/* Port45 */
PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
/* Port46 */
PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
/* Port47 */
PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
/* Port48 */
PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
/* Port49 */
PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
/* Port50 */
PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
/* Port51 */
PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
/* Port52 */
PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
/* Port53 */
PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
/* Port54 */
PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
/* Port55 */
PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
/* Port56 */
PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
/* Port57 */
PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
/* Port58 */
PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
/* Port59 */
PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
/* Port60 */
PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
/* Port61 */
PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
/* Port62 */
PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
/* Port63 */
PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
/* Port64 */
PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
/* Port65 */
PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
/* Port66 */
PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
/* Port67 - Port73 Function1 */
PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
/* Port67 - Port73 Function2 */
PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
/* Port67 - Port73 Function4 */
PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
/* Port67 - Port73 Function6 */
PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
/* Port67 - Port71 IRQ */
PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
/* Port74 */
PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
/* Port75 */
PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
/* Port76 - Port80 Function */
PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
/* Port81 */
PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
/* Port82 - Port88 Function */
PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
/* Port89 */
PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
/* Port90 */
PINMUX_DATA(DACK0_MARK, PORT90_FN1),
PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
/* Port91 */
PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
/* Port92 */
PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
/* Port93 */
PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
/* Port94 */
PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
/* Port95 */
PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
/* Port96 */
PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
/* Port97 */
PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
/* Port98 */
PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
/* Port99 */
PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
/* Port100 */
PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
/* Port101 */
PINMUX_DATA(FCE0_MARK, PORT101_FN1),
/* Port102 */
PINMUX_DATA(FRB_MARK, PORT102_FN1),
PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
/* Port103 */
PINMUX_DATA(CS5B_MARK, PORT103_FN1),
PINMUX_DATA(FCE1_MARK, PORT103_FN2),
PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
/* Port104 */
PINMUX_DATA(CS6A_MARK, PORT104_FN1),
PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
/* Port105 */
PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
/* Port106 */
PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
/* Port107 - Port115 Function */
PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
PINMUX_DATA(CS0_MARK, PORT109_FN1),
PINMUX_DATA(CS2_MARK, PORT110_FN1),
PINMUX_DATA(CS4_MARK, PORT111_FN1),
PINMUX_DATA(WE1_MARK, PORT112_FN1),
PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
PINMUX_DATA(RDWR_MARK, PORT114_FN1),
PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
/* Port116 */
PINMUX_DATA(A25_MARK, PORT116_FN1),
PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
PINMUX_DATA(GPO1_MARK, PORT116_FN5),
/* Port117 */
PINMUX_DATA(A24_MARK, PORT117_FN1),
PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
PINMUX_DATA(GPO0_MARK, PORT117_FN5),
/* Port118 */
PINMUX_DATA(A23_MARK, PORT118_FN1),
PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
PINMUX_DATA(GPI1_MARK, PORT118_FN5),
PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
/* Port119 */
PINMUX_DATA(A22_MARK, PORT119_FN1),
PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
PINMUX_DATA(GPI0_MARK, PORT119_FN5),
PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
/* Port120 */
PINMUX_DATA(A21_MARK, PORT120_FN1),
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
/* Port121 */
PINMUX_DATA(A20_MARK, PORT121_FN1),
PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
/* Port122 */
PINMUX_DATA(A19_MARK, PORT122_FN1),
PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
/* Port123 */
PINMUX_DATA(A18_MARK, PORT123_FN1),
PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
/* Port124 */
PINMUX_DATA(A17_MARK, PORT124_FN1),
PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
/* Port125 - Port141 Function */
PINMUX_DATA(A16_MARK, PORT125_FN1),
PINMUX_DATA(A15_MARK, PORT126_FN1),
PINMUX_DATA(A14_MARK, PORT127_FN1),
PINMUX_DATA(A13_MARK, PORT128_FN1),
PINMUX_DATA(A12_MARK, PORT129_FN1),
PINMUX_DATA(A11_MARK, PORT130_FN1),
PINMUX_DATA(A10_MARK, PORT131_FN1),
PINMUX_DATA(A9_MARK, PORT132_FN1),
PINMUX_DATA(A8_MARK, PORT133_FN1),
PINMUX_DATA(A7_MARK, PORT134_FN1),
PINMUX_DATA(A6_MARK, PORT135_FN1),
PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
PINMUX_DATA(A3_MARK, PORT138_FN1),
PINMUX_DATA(A2_MARK, PORT139_FN1),
PINMUX_DATA(A1_MARK, PORT140_FN1),
PINMUX_DATA(CKO_MARK, PORT141_FN1),
/* Port142 - Port157 Function1 */
PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
/* Port142 - Port149 Function3 */
PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
/* Port158 */
PINMUX_DATA(D31_MARK, PORT158_FN1),
PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
/* Port159 */
PINMUX_DATA(D30_MARK, PORT159_FN1),
PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
/* Port160 */
PINMUX_DATA(D29_MARK, PORT160_FN1),
PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
/* Port161 */
PINMUX_DATA(D28_MARK, PORT161_FN1),
PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
/* Port162 */
PINMUX_DATA(D27_MARK, PORT162_FN1),
PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
/* Port163 */
PINMUX_DATA(D26_MARK, PORT163_FN1),
PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
PINMUX_DATA(IROUT_MARK, PORT163_FN5),
PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
/* Port164 */
PINMUX_DATA(D25_MARK, PORT164_FN1),
PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
/* Port165 */
PINMUX_DATA(D24_MARK, PORT165_FN1),
PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
/* Port166 - Port171 Function1 */
PINMUX_DATA(D21_MARK, PORT166_FN1),
PINMUX_DATA(D20_MARK, PORT167_FN1),
PINMUX_DATA(D19_MARK, PORT168_FN1),
PINMUX_DATA(D18_MARK, PORT169_FN1),
PINMUX_DATA(D17_MARK, PORT170_FN1),
PINMUX_DATA(D16_MARK, PORT171_FN1),
/* Port166 - Port171 Function3 */
PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
/* Port166 - Port171 Function6 */
PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
/* Port167 - Port171 IRQ */
PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
/* Port172 */
PINMUX_DATA(D23_MARK, PORT172_FN1),
PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
/* Port173 */
PINMUX_DATA(D22_MARK, PORT173_FN1),
PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
/* Port174 */
PINMUX_DATA(A26_MARK, PORT174_FN1),
PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
/* Port175 */
PINMUX_DATA(A0_MARK, PORT175_FN1),
PINMUX_DATA(BS_MARK, PORT175_FN2),
PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
/* Port176 */
PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
/* Port177 */
PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
/* Port178 */
PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
/* Port179 */
PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
/* Port180 */
PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
/* Port181 */
PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
/* Port182 */
PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
/* Port183 */
PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
/* Port184 */
PINMUX_DATA(DACK1_MARK, PORT184_FN1),
PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
/* Port185 - Port192 Function1 */
PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
/* Port185 - Port192 Function3 */
PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
/* Port185 - Port192 Function6 */
PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
/* Port193 */
PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
/* Port194 */
PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
/* Port195 */
PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
/* Port196 */
PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
/* Port197 */
PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
/* Port198 */
PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
/* Port199 */
PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
/* Port200 */
PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
/* Port201 */
PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
/* Port202 */
PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
/* Port203 - Port208 Function1 */
PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
/* Port203 - Port208 Function3 */
PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
/* Port203 - Port208 Function6 */
PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
/* Port203 - Port208 Function7 */
PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
/* Port209 */
PINMUX_DATA(VBUS_MARK, PORT209_FN1),
PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
/* Port210 */
PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
/* Port211 */
PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
/* SDENC */
PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
/* SYSC */
PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
/* DEBUG */
PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
static const struct sh_pfc_pin pinmux_pins[] = {
/* Table 56-1 (I/O and Pull U/D) */
R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
};
/* - BSC -------------------------------------------------------------------- */
static const unsigned int bsc_data_pins[] = {
/* D[0:31] */
157, 156, 155, 154, 153, 152, 151, 150,
149, 148, 147, 146, 145, 144, 143, 142,
171, 170, 169, 168, 167, 166, 173, 172,
165, 164, 163, 162, 161, 160, 159, 158,
};
static const unsigned int bsc_data_mux[] = {
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
D16_MARK, D17_MARK, D18_MARK, D19_MARK,
D20_MARK, D21_MARK, D22_MARK, D23_MARK,
D24_MARK, D25_MARK, D26_MARK, D27_MARK,
D28_MARK, D29_MARK, D30_MARK, D31_MARK,
};
static const unsigned int bsc_cs0_pins[] = {
/* CS */
109,
};
static const unsigned int bsc_cs0_mux[] = {
CS0_MARK,
};
static const unsigned int bsc_cs2_pins[] = {
/* CS */
110,
};
static const unsigned int bsc_cs2_mux[] = {
CS2_MARK,
};
static const unsigned int bsc_cs4_pins[] = {
/* CS */
111,
};
static const unsigned int bsc_cs4_mux[] = {
CS4_MARK,
};
static const unsigned int bsc_cs5a_0_pins[] = {
/* CS */
105,
};
static const unsigned int bsc_cs5a_0_mux[] = {
CS5A_PORT105_MARK,
};
static const unsigned int bsc_cs5a_1_pins[] = {
/* CS */
19,
};
static const unsigned int bsc_cs5a_1_mux[] = {
CS5A_PORT19_MARK,
};
static const unsigned int bsc_cs5b_pins[] = {
/* CS */
103,
};
static const unsigned int bsc_cs5b_mux[] = {
CS5B_MARK,
};
static const unsigned int bsc_cs6a_pins[] = {
/* CS */
104,
};
static const unsigned int bsc_cs6a_mux[] = {
CS6A_MARK,
};
static const unsigned int bsc_rd_we_pins[] = {
/* RD, WE[0:3] */
115, 113, 112, 108, 107,
};
static const unsigned int bsc_rd_we_mux[] = {
RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
};
static const unsigned int bsc_bs_pins[] = {
/* BS */
175,
};
static const unsigned int bsc_bs_mux[] = {
BS_MARK,
};
static const unsigned int bsc_rdwr_pins[] = {
/* RDWR */
114,
};
static const unsigned int bsc_rdwr_mux[] = {
RDWR_MARK,
};
/* - CEU0 ------------------------------------------------------------------- */
static const unsigned int ceu0_data_0_7_pins[] = {
/* D[0:7] */
34, 33, 32, 31, 30, 29, 28, 27,
};
static const unsigned int ceu0_data_0_7_mux[] = {
VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
};
static const unsigned int ceu0_data_8_15_0_pins[] = {
/* D[8:15] */
182, 181, 180, 179, 178, 26, 25, 24,
};
static const unsigned int ceu0_data_8_15_0_mux[] = {
VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
VIO0_D15_PORT24_MARK,
};
static const unsigned int ceu0_data_8_15_1_pins[] = {
/* D[8:15] */
182, 181, 180, 179, 178, 22, 95, 96,
};
static const unsigned int ceu0_data_8_15_1_mux[] = {
VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
VIO0_D15_PORT96_MARK,
};
static const unsigned int ceu0_clk_0_pins[] = {
/* CKO */
36,
};
static const unsigned int ceu0_clk_0_mux[] = {
VIO_CKO_MARK,
};
static const unsigned int ceu0_clk_1_pins[] = {
/* CKO */
14,
};
static const unsigned int ceu0_clk_1_mux[] = {
VIO_CKO1_MARK,
};
static const unsigned int ceu0_clk_2_pins[] = {
/* CKO */
15,
};
static const unsigned int ceu0_clk_2_mux[] = {
VIO_CKO2_MARK,
};
static const unsigned int ceu0_sync_pins[] = {
/* CLK, VD, HD */
35, 39, 37,
};
static const unsigned int ceu0_sync_mux[] = {
VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
};
static const unsigned int ceu0_field_pins[] = {
/* FIELD */
38,
};
static const unsigned int ceu0_field_mux[] = {
VIO0_FIELD_MARK,
};
/* - CEU1 ------------------------------------------------------------------- */
static const unsigned int ceu1_data_pins[] = {
/* D[0:7] */
182, 181, 180, 179, 178, 26, 25, 24,
};
static const unsigned int ceu1_data_mux[] = {
VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
};
static const unsigned int ceu1_clk_pins[] = {
/* CKO */
23,
};
static const unsigned int ceu1_clk_mux[] = {
VIO_CKO_1_MARK,
};
static const unsigned int ceu1_sync_pins[] = {
/* CLK, VD, HD */
197, 198, 160,
};
static const unsigned int ceu1_sync_mux[] = {
VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
};
static const unsigned int ceu1_field_pins[] = {
/* FIELD */
21,
};
static const unsigned int ceu1_field_mux[] = {
VIO1_FIELD_MARK,
};
/* - FSIA ------------------------------------------------------------------- */
static const unsigned int fsia_mclk_in_pins[] = {
/* CK */
11,
};
static const unsigned int fsia_mclk_in_mux[] = {
FSIACK_MARK,
};
static const unsigned int fsia_mclk_out_pins[] = {
/* OMC */
10,
};
static const unsigned int fsia_mclk_out_mux[] = {
FSIAOMC_MARK,
};
static const unsigned int fsia_sclk_in_pins[] = {
/* ILR, IBT */
12, 13,
};
static const unsigned int fsia_sclk_in_mux[] = {
FSIAILR_MARK, FSIAIBT_MARK,
};
static const unsigned int fsia_sclk_out_pins[] = {
/* OLR, OBT */
7, 8,
};
static const unsigned int fsia_sclk_out_mux[] = {
FSIAOLR_MARK, FSIAOBT_MARK,
};
static const unsigned int fsia_data_in_0_pins[] = {
/* ISLD */
0,
};
static const unsigned int fsia_data_in_0_mux[] = {
FSIAISLD_PORT0_MARK,
};
static const unsigned int fsia_data_in_1_pins[] = {
/* ISLD */
5,
};
static const unsigned int fsia_data_in_1_mux[] = {
FSIAISLD_PORT5_MARK,
};
static const unsigned int fsia_data_out_0_pins[] = {
/* OSLD */
9,
};
static const unsigned int fsia_data_out_0_mux[] = {
FSIAOSLD_MARK,
};
static const unsigned int fsia_data_out_1_pins[] = {
/* OSLD */
0,
};
static const unsigned int fsia_data_out_1_mux[] = {
FSIAOSLD1_MARK,
};
static const unsigned int fsia_data_out_2_pins[] = {
/* OSLD */
1,
};
static const unsigned int fsia_data_out_2_mux[] = {
FSIAOSLD2_MARK,
};
static const unsigned int fsia_spdif_0_pins[] = {
/* SPDIF */
9,
};
static const unsigned int fsia_spdif_0_mux[] = {
FSIASPDIF_PORT9_MARK,
};
static const unsigned int fsia_spdif_1_pins[] = {
/* SPDIF */
18,
};
static const unsigned int fsia_spdif_1_mux[] = {
FSIASPDIF_PORT18_MARK,
};
/* - FSIB ------------------------------------------------------------------- */
static const unsigned int fsib_mclk_in_pins[] = {
/* CK */
11,
};
static const unsigned int fsib_mclk_in_mux[] = {
FSIBCK_MARK,
};
/* - GETHER ----------------------------------------------------------------- */
static const unsigned int gether_rmii_pins[] = {
/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
};
static const unsigned int gether_rmii_mux[] = {
RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
RMII_MDC_MARK, RMII_MDIO_MARK,
};
static const unsigned int gether_mii_pins[] = {
/* RXD[0:3], RX_CLK, RX_DV, RX_ER
* TXD[0:3], TX_CLK, TX_EN, TX_ER
* CRS, COL, MDC, MDIO,
*/
185, 186, 187, 188, 174, 161, 204,
171, 170, 169, 168, 184, 183, 203,
205, 163, 206, 207,
};
static const unsigned int gether_mii_mux[] = {
ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
};
static const unsigned int gether_gmii_pins[] = {
/* RXD[0:7], RX_CLK, RX_DV, RX_ER
* TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
* CRS, COL, MDC, MDIO, REF125CK_MARK,
*/
185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
205, 163, 206, 207, 158,
};
static const unsigned int gether_gmii_mux[] = {
ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
RMII_REF125CK_MARK,
};
static const unsigned int gether_int_pins[] = {
/* PHY_INT */
164,
};
static const unsigned int gether_int_mux[] = {
ET_PHY_INT_MARK,
};
static const unsigned int gether_link_pins[] = {
/* LINK */
177,
};
static const unsigned int gether_link_mux[] = {
ET_LINK_MARK,
};
static const unsigned int gether_wol_pins[] = {
/* WOL */
175,
};
static const unsigned int gether_wol_mux[] = {
ET_WOL_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi_pins[] = {
/* HPD, CEC */
210, 211,
};
static const unsigned int hdmi_mux[] = {
HDMI_HPD_MARK, HDMI_CEC_MARK,
};
/* - INTC ------------------------------------------------------------------- */
IRQC_PINS_MUX(0, 0, 2);
IRQC_PINS_MUX(0, 1, 13);
IRQC_PIN_MUX(1, 20);
IRQC_PINS_MUX(2, 0, 11);
IRQC_PINS_MUX(2, 1, 12);
IRQC_PINS_MUX(3, 0, 10);
IRQC_PINS_MUX(3, 1, 14);
IRQC_PINS_MUX(4, 0, 15);
IRQC_PINS_MUX(4, 1, 172);
IRQC_PINS_MUX(5, 0, 0);
IRQC_PINS_MUX(5, 1, 1);
IRQC_PINS_MUX(6, 0, 121);
IRQC_PINS_MUX(6, 1, 173);
IRQC_PINS_MUX(7, 0, 120);
IRQC_PINS_MUX(7, 1, 209);
IRQC_PIN_MUX(8, 119);
IRQC_PINS_MUX(9, 0, 118);
IRQC_PINS_MUX(9, 1, 210);
IRQC_PIN_MUX(10, 19);
IRQC_PIN_MUX(11, 104);
IRQC_PINS_MUX(12, 0, 42);
IRQC_PINS_MUX(12, 1, 97);
IRQC_PINS_MUX(13, 0, 64);
IRQC_PINS_MUX(13, 1, 98);
IRQC_PINS_MUX(14, 0, 63);
IRQC_PINS_MUX(14, 1, 99);
IRQC_PINS_MUX(15, 0, 62);
IRQC_PINS_MUX(15, 1, 100);
IRQC_PINS_MUX(16, 0, 68);
IRQC_PINS_MUX(16, 1, 211);
IRQC_PIN_MUX(17, 69);
IRQC_PIN_MUX(18, 70);
IRQC_PIN_MUX(19, 71);
IRQC_PIN_MUX(20, 67);
IRQC_PIN_MUX(21, 202);
IRQC_PIN_MUX(22, 95);
IRQC_PIN_MUX(23, 96);
IRQC_PIN_MUX(24, 180);
IRQC_PIN_MUX(25, 38);
IRQC_PINS_MUX(26, 0, 58);
IRQC_PINS_MUX(26, 1, 81);
IRQC_PINS_MUX(27, 0, 57);
IRQC_PINS_MUX(27, 1, 168);
IRQC_PINS_MUX(28, 0, 56);
IRQC_PINS_MUX(28, 1, 169);
IRQC_PINS_MUX(29, 0, 50);
IRQC_PINS_MUX(29, 1, 170);
IRQC_PINS_MUX(30, 0, 49);
IRQC_PINS_MUX(30, 1, 171);
IRQC_PINS_MUX(31, 0, 41);
IRQC_PINS_MUX(31, 1, 167);
/* - LCD0 ------------------------------------------------------------------- */
static const unsigned int lcd0_data24_0_pins[] = {
/* D[0:23] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41, 40, 4, 3, 2, 0, 1,
};
static const unsigned int lcd0_data24_0_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
LCD0_D23_PORT1_MARK,
};
static const unsigned int lcd0_data24_1_pins[] = {
/* D[0:23] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41, 163, 162, 161, 158, 160, 159,
};
static const unsigned int lcd0_data24_1_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
};
static const unsigned int lcd0_display_pins[] = {
/* DON, VCPWC, VEPWC */
61, 59, 60,
};
static const unsigned int lcd0_display_mux[] = {
LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
};
static const unsigned int lcd0_lclk_0_pins[] = {
/* LCLK */
102,
};
static const unsigned int lcd0_lclk_0_mux[] = {
LCD0_LCLK_PORT102_MARK,
};
static const unsigned int lcd0_lclk_1_pins[] = {
/* LCLK */
165,
};
static const unsigned int lcd0_lclk_1_mux[] = {
LCD0_LCLK_PORT165_MARK,
};
static const unsigned int lcd0_sync_pins[] = {
/* VSYN, HSYN, DCK, DISP */
63, 64, 62, 65,
};
static const unsigned int lcd0_sync_mux[] = {
LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
};
static const unsigned int lcd0_sys_pins[] = {
/* CS, WR, RD, RS */
64, 62, 164, 65,
};
static const unsigned int lcd0_sys_mux[] = {
LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
};
/* - LCD1 ------------------------------------------------------------------- */
static const unsigned int lcd1_data_pins[] = {
/* D[0:23] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
194, 193, 198, 197, 75, 74, 15, 14,
};
static const unsigned int lcd1_data_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
};
static const unsigned int lcd1_display_pins[] = {
/* DON, VCPWC, VEPWC */
100, 5, 6,
};
static const unsigned int lcd1_display_mux[] = {
LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
};
static const unsigned int lcd1_lclk_pins[] = {
/* LCLK */
40,
};
static const unsigned int lcd1_lclk_mux[] = {
LCD1_LCLK_MARK,
};
static const unsigned int lcd1_sync_pins[] = {
/* VSYN, HSYN, DCK, DISP */
98, 97, 99, 12,
};
static const unsigned int lcd1_sync_mux[] = {
LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
};
static const unsigned int lcd1_sys_pins[] = {
/* CS, WR, RD, RS */
97, 99, 13, 12,
};
static const unsigned int lcd1_sys_mux[] = {
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data_0_pins[] = {
/* D[0:7] */
68, 69, 70, 71, 72, 73, 74, 75,
};
static const unsigned int mmc0_data_0_mux[] = {
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
};
static const unsigned int mmc0_ctrl_0_pins[] = {
/* CMD, CLK */
67, 66,
};
static const unsigned int mmc0_ctrl_0_mux[] = {
MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
};
static const unsigned int mmc0_data_1_pins[] = {
/* D[0:7] */
149, 148, 147, 146, 145, 144, 143, 142,
};
static const unsigned int mmc0_data_1_mux[] = {
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
};
static const unsigned int mmc0_ctrl_1_pins[] = {
/* CMD, CLK */
104, 103,
};
static const unsigned int mmc0_ctrl_1_mux[] = {
MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
197, 198,
};
static const unsigned int scifa0_data_mux[] = {
SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
};
static const unsigned int scifa0_clk_pins[] = {
/* SCK */
188,
};
static const unsigned int scifa0_clk_mux[] = {
SCIFA0_SCK_MARK,
};
static const unsigned int scifa0_ctrl_pins[] = {
/* RTS, CTS */
194, 193,
};
static const unsigned int scifa0_ctrl_mux[] = {
SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
};
/* - SCIFA1 ----------------------------------------------------------------- */
static const unsigned int scifa1_data_pins[] = {
/* RXD, TXD */
195, 196,
};
static const unsigned int scifa1_data_mux[] = {
SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
};
static const unsigned int scifa1_clk_pins[] = {
/* SCK */
185,
};
static const unsigned int scifa1_clk_mux[] = {
SCIFA1_SCK_MARK,
};
static const unsigned int scifa1_ctrl_pins[] = {
/* RTS, CTS */
23, 21,
};
static const unsigned int scifa1_ctrl_mux[] = {
SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
};
/* - SCIFA2 ----------------------------------------------------------------- */
static const unsigned int scifa2_data_pins[] = {
/* RXD, TXD */
200, 201,
};
static const unsigned int scifa2_data_mux[] = {
SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
};
static const unsigned int scifa2_clk_0_pins[] = {
/* SCK */
22,
};
static const unsigned int scifa2_clk_0_mux[] = {
SCIFA2_SCK_PORT22_MARK,
};
static const unsigned int scifa2_clk_1_pins[] = {
/* SCK */
199,
};
static const unsigned int scifa2_clk_1_mux[] = {
SCIFA2_SCK_PORT199_MARK,
};
static const unsigned int scifa2_ctrl_pins[] = {
/* RTS, CTS */
96, 95,
};
static const unsigned int scifa2_ctrl_mux[] = {
SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
};
/* - SCIFA3 ----------------------------------------------------------------- */
static const unsigned int scifa3_data_0_pins[] = {
/* RXD, TXD */
174, 175,
};
static const unsigned int scifa3_data_0_mux[] = {
SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
};
static const unsigned int scifa3_clk_0_pins[] = {
/* SCK */
116,
};
static const unsigned int scifa3_clk_0_mux[] = {
SCIFA3_SCK_PORT116_MARK,
};
static const unsigned int scifa3_ctrl_0_pins[] = {
/* RTS, CTS */
105, 117,
};
static const unsigned int scifa3_ctrl_0_mux[] = {
SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
};
static const unsigned int scifa3_data_1_pins[] = {
/* RXD, TXD */
159, 160,
};
static const unsigned int scifa3_data_1_mux[] = {
SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
};
static const unsigned int scifa3_clk_1_pins[] = {
/* SCK */
158,
};
static const unsigned int scifa3_clk_1_mux[] = {
SCIFA3_SCK_PORT158_MARK,
};
static const unsigned int scifa3_ctrl_1_pins[] = {
/* RTS, CTS */
161, 162,
};
static const unsigned int scifa3_ctrl_1_mux[] = {
SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
};
/* - SCIFA4 ----------------------------------------------------------------- */
static const unsigned int scifa4_data_0_pins[] = {
/* RXD, TXD */
12, 13,
};
static const unsigned int scifa4_data_0_mux[] = {
SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
};
static const unsigned int scifa4_data_1_pins[] = {
/* RXD, TXD */
204, 203,
};
static const unsigned int scifa4_data_1_mux[] = {
SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
};
static const unsigned int scifa4_data_2_pins[] = {
/* RXD, TXD */
94, 93,
};
static const unsigned int scifa4_data_2_mux[] = {
SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
};
static const unsigned int scifa4_clk_0_pins[] = {
/* SCK */
21,
};
static const unsigned int scifa4_clk_0_mux[] = {
SCIFA4_SCK_PORT21_MARK,
};
static const unsigned int scifa4_clk_1_pins[] = {
/* SCK */
205,
};
static const unsigned int scifa4_clk_1_mux[] = {
SCIFA4_SCK_PORT205_MARK,
};
/* - SCIFA5 ----------------------------------------------------------------- */
static const unsigned int scifa5_data_0_pins[] = {
/* RXD, TXD */
10, 20,
};
static const unsigned int scifa5_data_0_mux[] = {
SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
};
static const unsigned int scifa5_data_1_pins[] = {
/* RXD, TXD */
207, 208,
};
static const unsigned int scifa5_data_1_mux[] = {
SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
};
static const unsigned int scifa5_data_2_pins[] = {
/* RXD, TXD */
92, 91,
};
static const unsigned int scifa5_data_2_mux[] = {
SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
};
static const unsigned int scifa5_clk_0_pins[] = {
/* SCK */
23,
};
static const unsigned int scifa5_clk_0_mux[] = {
SCIFA5_SCK_PORT23_MARK,
};
static const unsigned int scifa5_clk_1_pins[] = {
/* SCK */
206,
};
static const unsigned int scifa5_clk_1_mux[] = {
SCIFA5_SCK_PORT206_MARK,
};
/* - SCIFA6 ----------------------------------------------------------------- */
static const unsigned int scifa6_data_pins[] = {
/* RXD, TXD */
25, 26,
};
static const unsigned int scifa6_data_mux[] = {
SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
};
static const unsigned int scifa6_clk_pins[] = {
/* SCK */
24,
};
static const unsigned int scifa6_clk_mux[] = {
SCIFA6_SCK_MARK,
};
/* - SCIFA7 ----------------------------------------------------------------- */
static const unsigned int scifa7_data_pins[] = {
/* RXD, TXD */
0, 1,
};
static const unsigned int scifa7_data_mux[] = {
SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
};
/* - SCIFB ------------------------------------------------------------------ */
static const unsigned int scifb_data_0_pins[] = {
/* RXD, TXD */
191, 192,
};
static const unsigned int scifb_data_0_mux[] = {
SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
};
static const unsigned int scifb_clk_0_pins[] = {
/* SCK */
190,
};
static const unsigned int scifb_clk_0_mux[] = {
SCIFB_SCK_PORT190_MARK,
};
static const unsigned int scifb_ctrl_0_pins[] = {
/* RTS, CTS */
186, 187,
};
static const unsigned int scifb_ctrl_0_mux[] = {
SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
};
static const unsigned int scifb_data_1_pins[] = {
/* RXD, TXD */
3, 4,
};
static const unsigned int scifb_data_1_mux[] = {
SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
};
static const unsigned int scifb_clk_1_pins[] = {
/* SCK */
2,
};
static const unsigned int scifb_clk_1_mux[] = {
SCIFB_SCK_PORT2_MARK,
};
static const unsigned int scifb_ctrl_1_pins[] = {
/* RTS, CTS */
172, 173,
};
static const unsigned int scifb_ctrl_1_mux[] = {
SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
77, 78, 79, 80,
};
static const unsigned int sdhi0_data_mux[] = {
SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CMD, CLK */
76, 82,
};
static const unsigned int sdhi0_ctrl_mux[] = {
SDHI0_CMD_MARK, SDHI0_CLK_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
81,
};
static const unsigned int sdhi0_cd_mux[] = {
SDHI0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
83,
};
static const unsigned int sdhi0_wp_mux[] = {
SDHI0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
68, 69, 70, 71,
};
static const unsigned int sdhi1_data_mux[] = {
SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CMD, CLK */
67, 66,
};
static const unsigned int sdhi1_ctrl_mux[] = {
SDHI1_CMD_MARK, SDHI1_CLK_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
72,
};
static const unsigned int sdhi1_cd_mux[] = {
SDHI1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
73,
};
static const unsigned int sdhi1_wp_mux[] = {
SDHI1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
205, 206, 207, 208,
};
static const unsigned int sdhi2_data_mux[] = {
SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CMD, CLK */
204, 203,
};
static const unsigned int sdhi2_ctrl_mux[] = {
SDHI2_CMD_MARK, SDHI2_CLK_MARK,
};
static const unsigned int sdhi2_cd_0_pins[] = {
/* CD */
202,
};
static const unsigned int sdhi2_cd_0_mux[] = {
SDHI2_CD_PORT202_MARK,
};
static const unsigned int sdhi2_wp_0_pins[] = {
/* WP */
177,
};
static const unsigned int sdhi2_wp_0_mux[] = {
SDHI2_WP_PORT177_MARK,
};
static const unsigned int sdhi2_cd_1_pins[] = {
/* CD */
24,
};
static const unsigned int sdhi2_cd_1_mux[] = {
SDHI2_CD_PORT24_MARK,
};
static const unsigned int sdhi2_wp_1_pins[] = {
/* WP */
25,
};
static const unsigned int sdhi2_wp_1_mux[] = {
SDHI2_WP_PORT25_MARK,
};
/* - TPU0 ------------------------------------------------------------------- */
static const unsigned int tpu0_to0_pins[] = {
/* TO */
23,
};
static const unsigned int tpu0_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu0_to1_pins[] = {
/* TO */
21,
};
static const unsigned int tpu0_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu0_to2_0_pins[] = {
/* TO */
66,
};
static const unsigned int tpu0_to2_0_mux[] = {
TPU0TO2_PORT66_MARK,
};
static const unsigned int tpu0_to2_1_pins[] = {
/* TO */
202,
};
static const unsigned int tpu0_to2_1_mux[] = {
TPU0TO2_PORT202_MARK,
};
static const unsigned int tpu0_to3_pins[] = {
/* TO */
180,
};
static const unsigned int tpu0_to3_mux[] = {
TPU0TO3_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
BUS_DATA_PIN_GROUP(bsc_data, 8),
BUS_DATA_PIN_GROUP(bsc_data, 16),
BUS_DATA_PIN_GROUP(bsc_data, 32),
SH_PFC_PIN_GROUP(bsc_cs0),
SH_PFC_PIN_GROUP(bsc_cs2),
SH_PFC_PIN_GROUP(bsc_cs4),
SH_PFC_PIN_GROUP(bsc_cs5a_0),
SH_PFC_PIN_GROUP(bsc_cs5a_1),
SH_PFC_PIN_GROUP(bsc_cs5b),
SH_PFC_PIN_GROUP(bsc_cs6a),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3),
SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5),
SH_PFC_PIN_GROUP(bsc_bs),
SH_PFC_PIN_GROUP(bsc_rdwr),
SH_PFC_PIN_GROUP(ceu0_data_0_7),
SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
SH_PFC_PIN_GROUP(ceu0_clk_0),
SH_PFC_PIN_GROUP(ceu0_clk_1),
SH_PFC_PIN_GROUP(ceu0_clk_2),
SH_PFC_PIN_GROUP(ceu0_sync),
SH_PFC_PIN_GROUP(ceu0_field),
SH_PFC_PIN_GROUP(ceu1_data),
SH_PFC_PIN_GROUP(ceu1_clk),
SH_PFC_PIN_GROUP(ceu1_sync),
SH_PFC_PIN_GROUP(ceu1_field),
SH_PFC_PIN_GROUP(fsia_mclk_in),
SH_PFC_PIN_GROUP(fsia_mclk_out),
SH_PFC_PIN_GROUP(fsia_sclk_in),
SH_PFC_PIN_GROUP(fsia_sclk_out),
SH_PFC_PIN_GROUP(fsia_data_in_0),
SH_PFC_PIN_GROUP(fsia_data_in_1),
SH_PFC_PIN_GROUP(fsia_data_out_0),
SH_PFC_PIN_GROUP(fsia_data_out_1),
SH_PFC_PIN_GROUP(fsia_data_out_2),
SH_PFC_PIN_GROUP(fsia_spdif_0),
SH_PFC_PIN_GROUP(fsia_spdif_1),
SH_PFC_PIN_GROUP(fsib_mclk_in),
SH_PFC_PIN_GROUP(gether_rmii),
SH_PFC_PIN_GROUP(gether_mii),
SH_PFC_PIN_GROUP(gether_gmii),
SH_PFC_PIN_GROUP(gether_int),
SH_PFC_PIN_GROUP(gether_link),
SH_PFC_PIN_GROUP(gether_wol),
SH_PFC_PIN_GROUP(hdmi),
SH_PFC_PIN_GROUP(intc_irq0_0),
SH_PFC_PIN_GROUP(intc_irq0_1),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2_0),
SH_PFC_PIN_GROUP(intc_irq2_1),
SH_PFC_PIN_GROUP(intc_irq3_0),
SH_PFC_PIN_GROUP(intc_irq3_1),
SH_PFC_PIN_GROUP(intc_irq4_0),
SH_PFC_PIN_GROUP(intc_irq4_1),
SH_PFC_PIN_GROUP(intc_irq5_0),
SH_PFC_PIN_GROUP(intc_irq5_1),
SH_PFC_PIN_GROUP(intc_irq6_0),
SH_PFC_PIN_GROUP(intc_irq6_1),
SH_PFC_PIN_GROUP(intc_irq7_0),
SH_PFC_PIN_GROUP(intc_irq7_1),
SH_PFC_PIN_GROUP(intc_irq8),
SH_PFC_PIN_GROUP(intc_irq9_0),
SH_PFC_PIN_GROUP(intc_irq9_1),
SH_PFC_PIN_GROUP(intc_irq10),
SH_PFC_PIN_GROUP(intc_irq11),
SH_PFC_PIN_GROUP(intc_irq12_0),
SH_PFC_PIN_GROUP(intc_irq12_1),
SH_PFC_PIN_GROUP(intc_irq13_0),
SH_PFC_PIN_GROUP(intc_irq13_1),
SH_PFC_PIN_GROUP(intc_irq14_0),
SH_PFC_PIN_GROUP(intc_irq14_1),
SH_PFC_PIN_GROUP(intc_irq15_0),
SH_PFC_PIN_GROUP(intc_irq15_1),
SH_PFC_PIN_GROUP(intc_irq16_0),
SH_PFC_PIN_GROUP(intc_irq16_1),
SH_PFC_PIN_GROUP(intc_irq17),
SH_PFC_PIN_GROUP(intc_irq18),
SH_PFC_PIN_GROUP(intc_irq19),
SH_PFC_PIN_GROUP(intc_irq20),
SH_PFC_PIN_GROUP(intc_irq21),
SH_PFC_PIN_GROUP(intc_irq22),
SH_PFC_PIN_GROUP(intc_irq23),
SH_PFC_PIN_GROUP(intc_irq24),
SH_PFC_PIN_GROUP(intc_irq25),
SH_PFC_PIN_GROUP(intc_irq26_0),
SH_PFC_PIN_GROUP(intc_irq26_1),
SH_PFC_PIN_GROUP(intc_irq27_0),
SH_PFC_PIN_GROUP(intc_irq27_1),
SH_PFC_PIN_GROUP(intc_irq28_0),
SH_PFC_PIN_GROUP(intc_irq28_1),
SH_PFC_PIN_GROUP(intc_irq29_0),
SH_PFC_PIN_GROUP(intc_irq29_1),
SH_PFC_PIN_GROUP(intc_irq30_0),
SH_PFC_PIN_GROUP(intc_irq30_1),
SH_PFC_PIN_GROUP(intc_irq31_0),
SH_PFC_PIN_GROUP(intc_irq31_1),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16),
SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18),
SH_PFC_PIN_GROUP(lcd0_data24_0),
SH_PFC_PIN_GROUP(lcd0_data24_1),
SH_PFC_PIN_GROUP(lcd0_display),
SH_PFC_PIN_GROUP(lcd0_lclk_0),
SH_PFC_PIN_GROUP(lcd0_lclk_1),
SH_PFC_PIN_GROUP(lcd0_sync),
SH_PFC_PIN_GROUP(lcd0_sys),
BUS_DATA_PIN_GROUP(lcd1_data, 8),
BUS_DATA_PIN_GROUP(lcd1_data, 9),
BUS_DATA_PIN_GROUP(lcd1_data, 12),
BUS_DATA_PIN_GROUP(lcd1_data, 16),
BUS_DATA_PIN_GROUP(lcd1_data, 18),
BUS_DATA_PIN_GROUP(lcd1_data, 24),
SH_PFC_PIN_GROUP(lcd1_display),
SH_PFC_PIN_GROUP(lcd1_lclk),
SH_PFC_PIN_GROUP(lcd1_sync),
SH_PFC_PIN_GROUP(lcd1_sys),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _0),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _0),
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
BUS_DATA_PIN_GROUP(mmc0_data, 1, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 4, _1),
BUS_DATA_PIN_GROUP(mmc0_data, 8, _1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(scifa0_data),
SH_PFC_PIN_GROUP(scifa0_clk),
SH_PFC_PIN_GROUP(scifa0_ctrl),
SH_PFC_PIN_GROUP(scifa1_data),
SH_PFC_PIN_GROUP(scifa1_clk),
SH_PFC_PIN_GROUP(scifa1_ctrl),
SH_PFC_PIN_GROUP(scifa2_data),
SH_PFC_PIN_GROUP(scifa2_clk_0),
SH_PFC_PIN_GROUP(scifa2_clk_1),
SH_PFC_PIN_GROUP(scifa2_ctrl),
SH_PFC_PIN_GROUP(scifa3_data_0),
SH_PFC_PIN_GROUP(scifa3_clk_0),
SH_PFC_PIN_GROUP(scifa3_ctrl_0),
SH_PFC_PIN_GROUP(scifa3_data_1),
SH_PFC_PIN_GROUP(scifa3_clk_1),
SH_PFC_PIN_GROUP(scifa3_ctrl_1),
SH_PFC_PIN_GROUP(scifa4_data_0),
SH_PFC_PIN_GROUP(scifa4_data_1),
SH_PFC_PIN_GROUP(scifa4_data_2),
SH_PFC_PIN_GROUP(scifa4_clk_0),
SH_PFC_PIN_GROUP(scifa4_clk_1),
SH_PFC_PIN_GROUP(scifa5_data_0),
SH_PFC_PIN_GROUP(scifa5_data_1),
SH_PFC_PIN_GROUP(scifa5_data_2),
SH_PFC_PIN_GROUP(scifa5_clk_0),
SH_PFC_PIN_GROUP(scifa5_clk_1),
SH_PFC_PIN_GROUP(scifa6_data),
SH_PFC_PIN_GROUP(scifa6_clk),
SH_PFC_PIN_GROUP(scifa7_data),
SH_PFC_PIN_GROUP(scifb_data_0),
SH_PFC_PIN_GROUP(scifb_clk_0),
SH_PFC_PIN_GROUP(scifb_ctrl_0),
SH_PFC_PIN_GROUP(scifb_data_1),
SH_PFC_PIN_GROUP(scifb_clk_1),
SH_PFC_PIN_GROUP(scifb_ctrl_1),
BUS_DATA_PIN_GROUP(sdhi0_data, 1),
BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
BUS_DATA_PIN_GROUP(sdhi1_data, 1),
BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
BUS_DATA_PIN_GROUP(sdhi2_data, 1),
BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_0),
SH_PFC_PIN_GROUP(sdhi2_wp_0),
SH_PFC_PIN_GROUP(sdhi2_cd_1),
SH_PFC_PIN_GROUP(sdhi2_wp_1),
SH_PFC_PIN_GROUP(tpu0_to0),
SH_PFC_PIN_GROUP(tpu0_to1),
SH_PFC_PIN_GROUP(tpu0_to2_0),
SH_PFC_PIN_GROUP(tpu0_to2_1),
SH_PFC_PIN_GROUP(tpu0_to3),
};
static const char * const bsc_groups[] = {
"bsc_data8",
"bsc_data16",
"bsc_data32",
"bsc_cs0",
"bsc_cs2",
"bsc_cs4",
"bsc_cs5a_0",
"bsc_cs5a_1",
"bsc_cs5b",
"bsc_cs6a",
"bsc_rd_we8",
"bsc_rd_we16",
"bsc_rd_we32",
"bsc_bs",
"bsc_rdwr",
};
static const char * const ceu0_groups[] = {
"ceu0_data_0_7",
"ceu0_data_8_15_0",
"ceu0_data_8_15_1",
"ceu0_clk_0",
"ceu0_clk_1",
"ceu0_clk_2",
"ceu0_sync",
"ceu0_field",
};
static const char * const ceu1_groups[] = {
"ceu1_data",
"ceu1_clk",
"ceu1_sync",
"ceu1_field",
};
static const char * const fsia_groups[] = {
"fsia_mclk_in",
"fsia_mclk_out",
"fsia_sclk_in",
"fsia_sclk_out",
"fsia_data_in_0",
"fsia_data_in_1",
"fsia_data_out_0",
"fsia_data_out_1",
"fsia_data_out_2",
"fsia_spdif_0",
"fsia_spdif_1",
};
static const char * const fsib_groups[] = {
"fsib_mclk_in",
};
static const char * const gether_groups[] = {
"gether_rmii",
"gether_mii",
"gether_gmii",
"gether_int",
"gether_link",
"gether_wol",
};
static const char * const hdmi_groups[] = {
"hdmi",
};
static const char * const intc_groups[] = {
"intc_irq0_0",
"intc_irq0_1",
"intc_irq1",
"intc_irq2_0",
"intc_irq2_1",
"intc_irq3_0",
"intc_irq3_1",
"intc_irq4_0",
"intc_irq4_1",
"intc_irq5_0",
"intc_irq5_1",
"intc_irq6_0",
"intc_irq6_1",
"intc_irq7_0",
"intc_irq7_1",
"intc_irq8",
"intc_irq9_0",
"intc_irq9_1",
"intc_irq10",
"intc_irq11",
"intc_irq12_0",
"intc_irq12_1",
"intc_irq13_0",
"intc_irq13_1",
"intc_irq14_0",
"intc_irq14_1",
"intc_irq15_0",
"intc_irq15_1",
"intc_irq16_0",
"intc_irq16_1",
"intc_irq17",
"intc_irq18",
"intc_irq19",
"intc_irq20",
"intc_irq21",
"intc_irq22",
"intc_irq23",
"intc_irq24",
"intc_irq25",
"intc_irq26_0",
"intc_irq26_1",
"intc_irq27_0",
"intc_irq27_1",
"intc_irq28_0",
"intc_irq28_1",
"intc_irq29_0",
"intc_irq29_1",
"intc_irq30_0",
"intc_irq30_1",
"intc_irq31_0",
"intc_irq31_1",
};
static const char * const lcd0_groups[] = {
"lcd0_data8",
"lcd0_data9",
"lcd0_data12",
"lcd0_data16",
"lcd0_data18",
"lcd0_data24_0",
"lcd0_data24_1",
"lcd0_display",
"lcd0_lclk_0",
"lcd0_lclk_1",
"lcd0_sync",
"lcd0_sys",
};
static const char * const lcd1_groups[] = {
"lcd1_data8",
"lcd1_data9",
"lcd1_data12",
"lcd1_data16",
"lcd1_data18",
"lcd1_data24",
"lcd1_display",
"lcd1_lclk",
"lcd1_sync",
"lcd1_sys",
};
static const char * const mmc0_groups[] = {
"mmc0_data1_0",
"mmc0_data4_0",
"mmc0_data8_0",
"mmc0_ctrl_0",
"mmc0_data1_1",
"mmc0_data4_1",
"mmc0_data8_1",
"mmc0_ctrl_1",
};
static const char * const scifa0_groups[] = {
"scifa0_data",
"scifa0_clk",
"scifa0_ctrl",
};
static const char * const scifa1_groups[] = {
"scifa1_data",
"scifa1_clk",
"scifa1_ctrl",
};
static const char * const scifa2_groups[] = {
"scifa2_data",
"scifa2_clk_0",
"scifa2_clk_1",
"scifa2_ctrl",
};
static const char * const scifa3_groups[] = {
"scifa3_data_0",
"scifa3_clk_0",
"scifa3_ctrl_0",
"scifa3_data_1",
"scifa3_clk_1",
"scifa3_ctrl_1",
};
static const char * const scifa4_groups[] = {
"scifa4_data_0",
"scifa4_data_1",
"scifa4_data_2",
"scifa4_clk_0",
"scifa4_clk_1",
};
static const char * const scifa5_groups[] = {
"scifa5_data_0",
"scifa5_data_1",
"scifa5_data_2",
"scifa5_clk_0",
"scifa5_clk_1",
};
static const char * const scifa6_groups[] = {
"scifa6_data",
"scifa6_clk",
};
static const char * const scifa7_groups[] = {
"scifa7_data",
};
static const char * const scifb_groups[] = {
"scifb_data_0",
"scifb_clk_0",
"scifb_ctrl_0",
"scifb_data_1",
"scifb_clk_1",
"scifb_ctrl_1",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_ctrl",
"sdhi2_cd_0",
"sdhi2_wp_0",
"sdhi2_cd_1",
"sdhi2_wp_1",
};
static const char * const tpu0_groups[] = {
"tpu0_to0",
"tpu0_to1",
"tpu0_to2_0",
"tpu0_to2_1",
"tpu0_to3",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(bsc),
SH_PFC_FUNCTION(ceu0),
SH_PFC_FUNCTION(ceu1),
SH_PFC_FUNCTION(fsia),
SH_PFC_FUNCTION(fsib),
SH_PFC_FUNCTION(gether),
SH_PFC_FUNCTION(hdmi),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(lcd0),
SH_PFC_FUNCTION(lcd1),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(scifa0),
SH_PFC_FUNCTION(scifa1),
SH_PFC_FUNCTION(scifa2),
SH_PFC_FUNCTION(scifa3),
SH_PFC_FUNCTION(scifa4),
SH_PFC_FUNCTION(scifa5),
SH_PFC_FUNCTION(scifa6),
SH_PFC_FUNCTION(scifa7),
SH_PFC_FUNCTION(scifb),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(tpu0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
PORTCR(3, 0xe6050003), /* PORT3CR */
PORTCR(4, 0xe6050004), /* PORT4CR */
PORTCR(5, 0xe6050005), /* PORT5CR */
PORTCR(6, 0xe6050006), /* PORT6CR */
PORTCR(7, 0xe6050007), /* PORT7CR */
PORTCR(8, 0xe6050008), /* PORT8CR */
PORTCR(9, 0xe6050009), /* PORT9CR */
PORTCR(10, 0xe605000a), /* PORT10CR */
PORTCR(11, 0xe605000b), /* PORT11CR */
PORTCR(12, 0xe605000c), /* PORT12CR */
PORTCR(13, 0xe605000d), /* PORT13CR */
PORTCR(14, 0xe605000e), /* PORT14CR */
PORTCR(15, 0xe605000f), /* PORT15CR */
PORTCR(16, 0xe6050010), /* PORT16CR */
PORTCR(17, 0xe6050011), /* PORT17CR */
PORTCR(18, 0xe6050012), /* PORT18CR */
PORTCR(19, 0xe6050013), /* PORT19CR */
PORTCR(20, 0xe6050014), /* PORT20CR */
PORTCR(21, 0xe6050015), /* PORT21CR */
PORTCR(22, 0xe6050016), /* PORT22CR */
PORTCR(23, 0xe6050017), /* PORT23CR */
PORTCR(24, 0xe6050018), /* PORT24CR */
PORTCR(25, 0xe6050019), /* PORT25CR */
PORTCR(26, 0xe605001a), /* PORT26CR */
PORTCR(27, 0xe605001b), /* PORT27CR */
PORTCR(28, 0xe605001c), /* PORT28CR */
PORTCR(29, 0xe605001d), /* PORT29CR */
PORTCR(30, 0xe605001e), /* PORT30CR */
PORTCR(31, 0xe605001f), /* PORT31CR */
PORTCR(32, 0xe6050020), /* PORT32CR */
PORTCR(33, 0xe6050021), /* PORT33CR */
PORTCR(34, 0xe6050022), /* PORT34CR */
PORTCR(35, 0xe6050023), /* PORT35CR */
PORTCR(36, 0xe6050024), /* PORT36CR */
PORTCR(37, 0xe6050025), /* PORT37CR */
PORTCR(38, 0xe6050026), /* PORT38CR */
PORTCR(39, 0xe6050027), /* PORT39CR */
PORTCR(40, 0xe6050028), /* PORT40CR */
PORTCR(41, 0xe6050029), /* PORT41CR */
PORTCR(42, 0xe605002a), /* PORT42CR */
PORTCR(43, 0xe605002b), /* PORT43CR */
PORTCR(44, 0xe605002c), /* PORT44CR */
PORTCR(45, 0xe605002d), /* PORT45CR */
PORTCR(46, 0xe605002e), /* PORT46CR */
PORTCR(47, 0xe605002f), /* PORT47CR */
PORTCR(48, 0xe6050030), /* PORT48CR */
PORTCR(49, 0xe6050031), /* PORT49CR */
PORTCR(50, 0xe6050032), /* PORT50CR */
PORTCR(51, 0xe6050033), /* PORT51CR */
PORTCR(52, 0xe6050034), /* PORT52CR */
PORTCR(53, 0xe6050035), /* PORT53CR */
PORTCR(54, 0xe6050036), /* PORT54CR */
PORTCR(55, 0xe6050037), /* PORT55CR */
PORTCR(56, 0xe6050038), /* PORT56CR */
PORTCR(57, 0xe6050039), /* PORT57CR */
PORTCR(58, 0xe605003a), /* PORT58CR */
PORTCR(59, 0xe605003b), /* PORT59CR */
PORTCR(60, 0xe605003c), /* PORT60CR */
PORTCR(61, 0xe605003d), /* PORT61CR */
PORTCR(62, 0xe605003e), /* PORT62CR */
PORTCR(63, 0xe605003f), /* PORT63CR */
PORTCR(64, 0xe6050040), /* PORT64CR */
PORTCR(65, 0xe6050041), /* PORT65CR */
PORTCR(66, 0xe6050042), /* PORT66CR */
PORTCR(67, 0xe6050043), /* PORT67CR */
PORTCR(68, 0xe6050044), /* PORT68CR */
PORTCR(69, 0xe6050045), /* PORT69CR */
PORTCR(70, 0xe6050046), /* PORT70CR */
PORTCR(71, 0xe6050047), /* PORT71CR */
PORTCR(72, 0xe6050048), /* PORT72CR */
PORTCR(73, 0xe6050049), /* PORT73CR */
PORTCR(74, 0xe605004a), /* PORT74CR */
PORTCR(75, 0xe605004b), /* PORT75CR */
PORTCR(76, 0xe605004c), /* PORT76CR */
PORTCR(77, 0xe605004d), /* PORT77CR */
PORTCR(78, 0xe605004e), /* PORT78CR */
PORTCR(79, 0xe605004f), /* PORT79CR */
PORTCR(80, 0xe6050050), /* PORT80CR */
PORTCR(81, 0xe6050051), /* PORT81CR */
PORTCR(82, 0xe6050052), /* PORT82CR */
PORTCR(83, 0xe6050053), /* PORT83CR */
PORTCR(84, 0xe6051054), /* PORT84CR */
PORTCR(85, 0xe6051055), /* PORT85CR */
PORTCR(86, 0xe6051056), /* PORT86CR */
PORTCR(87, 0xe6051057), /* PORT87CR */
PORTCR(88, 0xe6051058), /* PORT88CR */
PORTCR(89, 0xe6051059), /* PORT89CR */
PORTCR(90, 0xe605105a), /* PORT90CR */
PORTCR(91, 0xe605105b), /* PORT91CR */
PORTCR(92, 0xe605105c), /* PORT92CR */
PORTCR(93, 0xe605105d), /* PORT93CR */
PORTCR(94, 0xe605105e), /* PORT94CR */
PORTCR(95, 0xe605105f), /* PORT95CR */
PORTCR(96, 0xe6051060), /* PORT96CR */
PORTCR(97, 0xe6051061), /* PORT97CR */
PORTCR(98, 0xe6051062), /* PORT98CR */
PORTCR(99, 0xe6051063), /* PORT99CR */
PORTCR(100, 0xe6051064), /* PORT100CR */
PORTCR(101, 0xe6051065), /* PORT101CR */
PORTCR(102, 0xe6051066), /* PORT102CR */
PORTCR(103, 0xe6051067), /* PORT103CR */
PORTCR(104, 0xe6051068), /* PORT104CR */
PORTCR(105, 0xe6051069), /* PORT105CR */
PORTCR(106, 0xe605106a), /* PORT106CR */
PORTCR(107, 0xe605106b), /* PORT107CR */
PORTCR(108, 0xe605106c), /* PORT108CR */
PORTCR(109, 0xe605106d), /* PORT109CR */
PORTCR(110, 0xe605106e), /* PORT110CR */
PORTCR(111, 0xe605106f), /* PORT111CR */
PORTCR(112, 0xe6051070), /* PORT112CR */
PORTCR(113, 0xe6051071), /* PORT113CR */
PORTCR(114, 0xe6051072), /* PORT114CR */
PORTCR(115, 0xe6052073), /* PORT115CR */
PORTCR(116, 0xe6052074), /* PORT116CR */
PORTCR(117, 0xe6052075), /* PORT117CR */
PORTCR(118, 0xe6052076), /* PORT118CR */
PORTCR(119, 0xe6052077), /* PORT119CR */
PORTCR(120, 0xe6052078), /* PORT120CR */
PORTCR(121, 0xe6052079), /* PORT121CR */
PORTCR(122, 0xe605207a), /* PORT122CR */
PORTCR(123, 0xe605207b), /* PORT123CR */
PORTCR(124, 0xe605207c), /* PORT124CR */
PORTCR(125, 0xe605207d), /* PORT125CR */
PORTCR(126, 0xe605207e), /* PORT126CR */
PORTCR(127, 0xe605207f), /* PORT127CR */
PORTCR(128, 0xe6052080), /* PORT128CR */
PORTCR(129, 0xe6052081), /* PORT129CR */
PORTCR(130, 0xe6052082), /* PORT130CR */
PORTCR(131, 0xe6052083), /* PORT131CR */
PORTCR(132, 0xe6052084), /* PORT132CR */
PORTCR(133, 0xe6052085), /* PORT133CR */
PORTCR(134, 0xe6052086), /* PORT134CR */
PORTCR(135, 0xe6052087), /* PORT135CR */
PORTCR(136, 0xe6052088), /* PORT136CR */
PORTCR(137, 0xe6052089), /* PORT137CR */
PORTCR(138, 0xe605208a), /* PORT138CR */
PORTCR(139, 0xe605208b), /* PORT139CR */
PORTCR(140, 0xe605208c), /* PORT140CR */
PORTCR(141, 0xe605208d), /* PORT141CR */
PORTCR(142, 0xe605208e), /* PORT142CR */
PORTCR(143, 0xe605208f), /* PORT143CR */
PORTCR(144, 0xe6052090), /* PORT144CR */
PORTCR(145, 0xe6052091), /* PORT145CR */
PORTCR(146, 0xe6052092), /* PORT146CR */
PORTCR(147, 0xe6052093), /* PORT147CR */
PORTCR(148, 0xe6052094), /* PORT148CR */
PORTCR(149, 0xe6052095), /* PORT149CR */
PORTCR(150, 0xe6052096), /* PORT150CR */
PORTCR(151, 0xe6052097), /* PORT151CR */
PORTCR(152, 0xe6052098), /* PORT152CR */
PORTCR(153, 0xe6052099), /* PORT153CR */
PORTCR(154, 0xe605209a), /* PORT154CR */
PORTCR(155, 0xe605209b), /* PORT155CR */
PORTCR(156, 0xe605209c), /* PORT156CR */
PORTCR(157, 0xe605209d), /* PORT157CR */
PORTCR(158, 0xe605209e), /* PORT158CR */
PORTCR(159, 0xe605209f), /* PORT159CR */
PORTCR(160, 0xe60520a0), /* PORT160CR */
PORTCR(161, 0xe60520a1), /* PORT161CR */
PORTCR(162, 0xe60520a2), /* PORT162CR */
PORTCR(163, 0xe60520a3), /* PORT163CR */
PORTCR(164, 0xe60520a4), /* PORT164CR */
PORTCR(165, 0xe60520a5), /* PORT165CR */
PORTCR(166, 0xe60520a6), /* PORT166CR */
PORTCR(167, 0xe60520a7), /* PORT167CR */
PORTCR(168, 0xe60520a8), /* PORT168CR */
PORTCR(169, 0xe60520a9), /* PORT169CR */
PORTCR(170, 0xe60520aa), /* PORT170CR */
PORTCR(171, 0xe60520ab), /* PORT171CR */
PORTCR(172, 0xe60520ac), /* PORT172CR */
PORTCR(173, 0xe60520ad), /* PORT173CR */
PORTCR(174, 0xe60520ae), /* PORT174CR */
PORTCR(175, 0xe60520af), /* PORT175CR */
PORTCR(176, 0xe60520b0), /* PORT176CR */
PORTCR(177, 0xe60520b1), /* PORT177CR */
PORTCR(178, 0xe60520b2), /* PORT178CR */
PORTCR(179, 0xe60520b3), /* PORT179CR */
PORTCR(180, 0xe60520b4), /* PORT180CR */
PORTCR(181, 0xe60520b5), /* PORT181CR */
PORTCR(182, 0xe60520b6), /* PORT182CR */
PORTCR(183, 0xe60520b7), /* PORT183CR */
PORTCR(184, 0xe60520b8), /* PORT184CR */
PORTCR(185, 0xe60520b9), /* PORT185CR */
PORTCR(186, 0xe60520ba), /* PORT186CR */
PORTCR(187, 0xe60520bb), /* PORT187CR */
PORTCR(188, 0xe60520bc), /* PORT188CR */
PORTCR(189, 0xe60520bd), /* PORT189CR */
PORTCR(190, 0xe60520be), /* PORT190CR */
PORTCR(191, 0xe60520bf), /* PORT191CR */
PORTCR(192, 0xe60520c0), /* PORT192CR */
PORTCR(193, 0xe60520c1), /* PORT193CR */
PORTCR(194, 0xe60520c2), /* PORT194CR */
PORTCR(195, 0xe60520c3), /* PORT195CR */
PORTCR(196, 0xe60520c4), /* PORT196CR */
PORTCR(197, 0xe60520c5), /* PORT197CR */
PORTCR(198, 0xe60520c6), /* PORT198CR */
PORTCR(199, 0xe60520c7), /* PORT199CR */
PORTCR(200, 0xe60520c8), /* PORT200CR */
PORTCR(201, 0xe60520c9), /* PORT201CR */
PORTCR(202, 0xe60520ca), /* PORT202CR */
PORTCR(203, 0xe60520cb), /* PORT203CR */
PORTCR(204, 0xe60520cc), /* PORT204CR */
PORTCR(205, 0xe60520cd), /* PORT205CR */
PORTCR(206, 0xe60520ce), /* PORT206CR */
PORTCR(207, 0xe60520cf), /* PORT207CR */
PORTCR(208, 0xe60520d0), /* PORT208CR */
PORTCR(209, 0xe60520d1), /* PORT209CR */
PORTCR(210, 0xe60530d2), /* PORT210CR */
PORTCR(211, 0xe60530d3), /* PORT211CR */
{ PINMUX_CFG_REG_VAR("MSEL1CR", 0xe605800c, 32,
GROUP(1, 1, 1, 1, 1, 1, -9, 1, 1, 1, 1, 1,
-2, 1, -1, 1, 1, 1, 1, 1, 1, -1, 1),
GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
MSEL1CR_28_0, MSEL1CR_28_1,
MSEL1CR_27_0, MSEL1CR_27_1,
MSEL1CR_26_0, MSEL1CR_26_1,
/* RESERVED [9] */
MSEL1CR_16_0, MSEL1CR_16_1,
MSEL1CR_15_0, MSEL1CR_15_1,
MSEL1CR_14_0, MSEL1CR_14_1,
MSEL1CR_13_0, MSEL1CR_13_1,
MSEL1CR_12_0, MSEL1CR_12_1,
/* RESERVED [2] */
MSEL1CR_9_0, MSEL1CR_9_1,
/* RESERVED [1] */
MSEL1CR_7_0, MSEL1CR_7_1,
MSEL1CR_6_0, MSEL1CR_6_1,
MSEL1CR_5_0, MSEL1CR_5_1,
MSEL1CR_4_0, MSEL1CR_4_1,
MSEL1CR_3_0, MSEL1CR_3_1,
MSEL1CR_2_0, MSEL1CR_2_1,
/* RESERVED [1] */
MSEL1CR_0_0, MSEL1CR_0_1,
))
},
{ PINMUX_CFG_REG_VAR("MSEL3CR", 0xE6058020, 32,
GROUP(-16, 1, -8, 1, -6),
GROUP(
/* RESERVED [16] */
MSEL3CR_15_0, MSEL3CR_15_1,
/* RESERVED [8] */
MSEL3CR_6_0, MSEL3CR_6_1,
/* RESERVED [6] */
))
},
{ PINMUX_CFG_REG_VAR("MSEL4CR", 0xE6058024, 32,
GROUP(-12, 1, 1, -2, 1, -4, 1, -3, 1, -1, 1, -2,
1, -1),
GROUP(
/* RESERVED [12] */
MSEL4CR_19_0, MSEL4CR_19_1,
MSEL4CR_18_0, MSEL4CR_18_1,
/* RESERVED [2] */
MSEL4CR_15_0, MSEL4CR_15_1,
/* RESERVED [4] */
MSEL4CR_10_0, MSEL4CR_10_1,
/* RESERVED [3] */
MSEL4CR_6_0, MSEL4CR_6_1,
/* RESERVED [1] */
MSEL4CR_4_0, MSEL4CR_4_1,
/* RESERVED [2] */
MSEL4CR_1_0, MSEL4CR_1_1,
/* RESERVED [1] */
))
},
{ PINMUX_CFG_REG_VAR("MSEL5CR", 0xE6058028, 32,
GROUP(1, 1, 1, -1, 1, -1, 1, -1, 1, -1, 1,
-1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
-1, 1, 1, 1, 1, 1, 1, 1, -1, 1),
GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
/* RESERVED [1] */
MSEL5CR_27_0, MSEL5CR_27_1,
/* RESERVED [1] */
MSEL5CR_25_0, MSEL5CR_25_1,
/* RESERVED [1] */
MSEL5CR_23_0, MSEL5CR_23_1,
/* RESERVED [1] */
MSEL5CR_21_0, MSEL5CR_21_1,
/* RESERVED [1] */
MSEL5CR_19_0, MSEL5CR_19_1,
/* RESERVED [1] */
MSEL5CR_17_0, MSEL5CR_17_1,
/* RESERVED [1] */
MSEL5CR_15_0, MSEL5CR_15_1,
MSEL5CR_14_0, MSEL5CR_14_1,
MSEL5CR_13_0, MSEL5CR_13_1,
MSEL5CR_12_0, MSEL5CR_12_1,
MSEL5CR_11_0, MSEL5CR_11_1,
MSEL5CR_10_0, MSEL5CR_10_1,
/* RESERVED [1] */
MSEL5CR_8_0, MSEL5CR_8_1,
MSEL5CR_7_0, MSEL5CR_7_1,
MSEL5CR_6_0, MSEL5CR_6_1,
MSEL5CR_5_0, MSEL5CR_5_1,
MSEL5CR_4_0, MSEL5CR_4_1,
MSEL5CR_3_0, MSEL5CR_3_1,
MSEL5CR_2_0, MSEL5CR_2_1,
/* RESERVED [1] */
MSEL5CR_0_0, MSEL5CR_0_1,
))
},
{ /* sentinel */ }
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
},
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
},
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
PORT115_DATA, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, PORT209_DATA, PORT208_DATA,
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
},
{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
PORT211_DATA, PORT210_DATA, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 ))
},
{ /* sentinel */ }
};
static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(2, 13), /* IRQ0A */
PINMUX_IRQ(20), /* IRQ1A */
PINMUX_IRQ(11, 12), /* IRQ2A */
PINMUX_IRQ(10, 14), /* IRQ3A */
PINMUX_IRQ(15, 172), /* IRQ4A */
PINMUX_IRQ(0, 1), /* IRQ5A */
PINMUX_IRQ(121, 173), /* IRQ6A */
PINMUX_IRQ(120, 209), /* IRQ7A */
PINMUX_IRQ(119), /* IRQ8A */
PINMUX_IRQ(118, 210), /* IRQ9A */
PINMUX_IRQ(19), /* IRQ10A */
PINMUX_IRQ(104), /* IRQ11A */
PINMUX_IRQ(42, 97), /* IRQ12A */
PINMUX_IRQ(64, 98), /* IRQ13A */
PINMUX_IRQ(63, 99), /* IRQ14A */
PINMUX_IRQ(62, 100), /* IRQ15A */
PINMUX_IRQ(68, 211), /* IRQ16A */
PINMUX_IRQ(69), /* IRQ17A */
PINMUX_IRQ(70), /* IRQ18A */
PINMUX_IRQ(71), /* IRQ19A */
PINMUX_IRQ(67), /* IRQ20A */
PINMUX_IRQ(202), /* IRQ21A */
PINMUX_IRQ(95), /* IRQ22A */
PINMUX_IRQ(96), /* IRQ23A */
PINMUX_IRQ(180), /* IRQ24A */
PINMUX_IRQ(38), /* IRQ25A */
PINMUX_IRQ(58, 81), /* IRQ26A */
PINMUX_IRQ(57, 168), /* IRQ27A */
PINMUX_IRQ(56, 169), /* IRQ28A */
PINMUX_IRQ(50, 170), /* IRQ29A */
PINMUX_IRQ(49, 171), /* IRQ30A */
PINMUX_IRQ(41, 167), /* IRQ31A */
};
struct r8a7740_portcr_group {
unsigned int end_pin;
unsigned int offset;
};
static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
};
static int r8a7740_pin_to_portcr(unsigned int pin)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
const struct r8a7740_portcr_group *group =
&r8a7740_portcr_offsets[i];
if (pin <= group->end_pin)
return group->offset + pin;
}
return -1;
}
static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
.get_bias = rmobile_pinmux_get_bias,
.set_bias = rmobile_pinmux_set_bias,
.pin_to_portcr = r8a7740_pin_to_portcr,
};
const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
.ops = &r8a7740_pfc_ops,
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN,
PINMUX_OUTPUT_END },
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
.gpio_irq = pinmux_irqs,
.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a7740.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* SuperH Pin Function Controller GPIO driver.
*
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2009 - 2012 Paul Mundt
*/
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include "core.h"
struct sh_pfc_gpio_data_reg {
const struct pinmux_data_reg *info;
u32 shadow;
};
struct sh_pfc_gpio_pin {
u8 dbit;
u8 dreg;
};
struct sh_pfc_chip {
struct sh_pfc *pfc;
struct gpio_chip gpio_chip;
struct sh_pfc_window *mem;
struct sh_pfc_gpio_data_reg *regs;
struct sh_pfc_gpio_pin *pins;
};
static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
{
struct sh_pfc_chip *chip = gpiochip_get_data(gc);
return chip->pfc;
}
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
struct sh_pfc_gpio_data_reg **reg,
unsigned int *bit)
{
int idx = sh_pfc_get_pin_index(chip->pfc, offset);
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
*reg = &chip->regs[gpio_pin->dreg];
*bit = gpio_pin->dbit;
}
static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
const struct pinmux_data_reg *dreg)
{
phys_addr_t address = dreg->reg;
void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
return sh_pfc_read_raw_reg(mem, dreg->reg_width);
}
static void gpio_write_data_reg(struct sh_pfc_chip *chip,
const struct pinmux_data_reg *dreg, u32 value)
{
phys_addr_t address = dreg->reg;
void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
{
struct sh_pfc *pfc = chip->pfc;
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
for (bit = 0; bit < dreg->reg_width; bit++) {
if (dreg->enum_ids[bit] == pin->enum_id) {
gpio_pin->dreg = i;
gpio_pin->dbit = bit;
return;
}
}
}
BUG();
}
static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
const struct pinmux_data_reg *dreg;
unsigned int i;
/* Count the number of data registers, allocate memory and initialize
* them.
*/
for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
;
chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
GFP_KERNEL);
if (chip->regs == NULL)
return -ENOMEM;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
chip->regs[i].info = dreg;
chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
}
for (i = 0; i < pfc->info->nr_pins; i++) {
if (pfc->info->pins[i].enum_id == 0)
continue;
gpio_setup_data_reg(chip, i);
}
return 0;
}
/* -----------------------------------------------------------------------------
* Pin GPIOs
*/
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
int idx = sh_pfc_get_pin_index(pfc, offset);
if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
return -EINVAL;
return pinctrl_gpio_request(gc->base + offset);
}
static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
{
return pinctrl_gpio_free(gc->base + offset);
}
static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
int value)
{
struct sh_pfc_gpio_data_reg *reg;
unsigned int bit;
unsigned int pos;
gpio_get_data_reg(chip, offset, ®, &bit);
pos = reg->info->reg_width - (bit + 1);
if (value)
reg->shadow |= BIT(pos);
else
reg->shadow &= ~BIT(pos);
gpio_write_data_reg(chip, reg->info, reg->shadow);
}
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
return pinctrl_gpio_direction_input(gc->base + offset);
}
static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
return pinctrl_gpio_direction_output(gc->base + offset);
}
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc_chip *chip = gpiochip_get_data(gc);
struct sh_pfc_gpio_data_reg *reg;
unsigned int bit;
unsigned int pos;
gpio_get_data_reg(chip, offset, ®, &bit);
pos = reg->info->reg_width - (bit + 1);
return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
}
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int i, k;
for (i = 0; i < pfc->info->gpio_irq_size; i++) {
const short *gpios = pfc->info->gpio_irq[i].gpios;
for (k = 0; gpios[k] >= 0; k++) {
if (gpios[k] == offset)
return pfc->irqs[i];
}
}
return 0;
}
static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
chip->pins = devm_kcalloc(pfc->dev,
pfc->info->nr_pins, sizeof(*chip->pins),
GFP_KERNEL);
if (chip->pins == NULL)
return -ENOMEM;
ret = gpio_setup_data_regs(chip);
if (ret < 0)
return ret;
gc->request = gpio_pin_request;
gc->free = gpio_pin_free;
gc->direction_input = gpio_pin_direction_input;
gc->get = gpio_pin_get;
gc->direction_output = gpio_pin_direction_output;
gc->set = gpio_pin_set;
gc->to_irq = gpio_pin_to_irq;
gc->label = pfc->info->name;
gc->parent = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = IS_ENABLED(CONFIG_PINCTRL_SH_FUNC_GPIO) ? 0 : -1;
gc->ngpio = pfc->nr_gpio_pins;
return 0;
}
/* -----------------------------------------------------------------------------
* Function GPIOs
*/
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret;
dev_notice_once(pfc->dev,
"Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
if (mark == 0)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
static int gpio_function_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
gc->request = gpio_function_request;
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
gc->base = pfc->nr_gpio_pins;
gc->ngpio = pfc->info->nr_func_gpios;
return 0;
}
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
/* -----------------------------------------------------------------------------
* Register/unregister
*/
static struct sh_pfc_chip *
sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
struct sh_pfc_window *mem)
{
struct sh_pfc_chip *chip;
int ret;
chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
if (unlikely(!chip))
return ERR_PTR(-ENOMEM);
chip->mem = mem;
chip->pfc = pfc;
ret = setup(chip);
if (ret < 0)
return ERR_PTR(ret);
ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
if (unlikely(ret < 0))
return ERR_PTR(ret);
dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
chip->gpio_chip.label, chip->gpio_chip.base,
chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
return chip;
}
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
struct sh_pfc_chip *chip;
phys_addr_t address;
unsigned int i;
if (pfc->info->data_regs == NULL)
return 0;
/* Find the memory window that contains the GPIO registers. Boards that
* register a separate GPIO device will not supply a memory resource
* that covers the data registers. In that case don't try to handle
* GPIOs.
*/
address = pfc->info->data_regs[0].reg;
for (i = 0; i < pfc->num_windows; ++i) {
struct sh_pfc_window *window = &pfc->windows[i];
if (address >= window->phys &&
address < window->phys + window->size)
break;
}
if (i == pfc->num_windows)
return 0;
/* If we have IRQ resources make sure their number is correct. */
if (pfc->num_irqs != pfc->info->gpio_irq_size) {
dev_err(pfc->dev, "invalid number of IRQ resources\n");
return -EINVAL;
}
/* Register the real GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
if (IS_ERR(chip))
return PTR_ERR(chip);
pfc->gpio = chip;
if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
return 0;
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
/*
* Register the GPIO to pin mappings. As pins with GPIO ports
* must come first in the ranges, skip the pins without GPIO
* ports by stopping at the first range that contains such a
* pin.
*/
for (i = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
int ret;
if (range->start >= pfc->nr_gpio_pins)
break;
ret = gpiochip_add_pin_range(&chip->gpio_chip,
dev_name(pfc->dev), range->start, range->start,
range->end - range->start + 1);
if (ret < 0)
return ret;
}
/* Register the function GPIOs chip. */
if (pfc->info->nr_func_gpios) {
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
if (IS_ERR(chip))
return PTR_ERR(chip);
}
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
return 0;
}
|
linux-master
|
drivers/pinctrl/renesas/gpio.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/V2M Pin Control and GPIO driver core
*
* Based on:
* Renesas RZ/G2L Pin Control and GPIO driver core
*
* Copyright (C) 2022 Renesas Electronics Corporation.
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinmux.h"
#define DRV_NAME "pinctrl-rzv2m"
/*
* Use 16 lower bits [15:0] for pin identifier
* Use 16 higher bits [31:16] for pin mux function
*/
#define MUX_PIN_ID_MASK GENMASK(15, 0)
#define MUX_FUNC_MASK GENMASK(31, 16)
#define MUX_FUNC(pinconf) FIELD_GET(MUX_FUNC_MASK, (pinconf))
/* PIN capabilities */
#define PIN_CFG_GRP_1_8V_2 1
#define PIN_CFG_GRP_1_8V_3 2
#define PIN_CFG_GRP_SWIO_1 3
#define PIN_CFG_GRP_SWIO_2 4
#define PIN_CFG_GRP_3_3V 5
#define PIN_CFG_GRP_MASK GENMASK(2, 0)
#define PIN_CFG_BIAS BIT(3)
#define PIN_CFG_DRV BIT(4)
#define PIN_CFG_SLEW BIT(5)
#define RZV2M_MPXED_PIN_FUNCS (PIN_CFG_BIAS | \
PIN_CFG_DRV | \
PIN_CFG_SLEW)
/*
* n indicates number of pins in the port, a is the register index
* and f is pin configuration capabilities supported.
*/
#define RZV2M_GPIO_PORT_PACK(n, a, f) (((n) << 24) | ((a) << 16) | (f))
#define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x))
#define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x))
#define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
#define RZV2M_DEDICATED_PORT_IDX 22
/*
* BIT(31) indicates dedicated pin, b is the register bits (b * 16)
* and f is the pin configuration capabilities supported.
*/
#define RZV2M_SINGLE_PIN BIT(31)
#define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \
((RZV2M_DEDICATED_PORT_IDX) << 24) | \
((b) << 16) | (f))
#define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x))
#define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x))
#define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
#define RZV2M_PIN_ID_TO_PORT(id) ((id) / RZV2M_PINS_PER_PORT)
#define RZV2M_PIN_ID_TO_PIN(id) ((id) % RZV2M_PINS_PER_PORT)
#define DO(n) (0x00 + (n) * 0x40)
#define OE(n) (0x04 + (n) * 0x40)
#define IE(n) (0x08 + (n) * 0x40)
#define PFSEL(n) (0x10 + (n) * 0x40)
#define DI(n) (0x20 + (n) * 0x40)
#define PUPD(n) (0x24 + (n) * 0x40)
#define DRV(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \
: 0x590)
#define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \
: 0x594)
#define DI_MSK(n) (0x30 + (n) * 0x40)
#define EN_MSK(n) (0x34 + (n) * 0x40)
#define PFC_MASK 0x07
#define PUPD_MASK 0x03
#define DRV_MASK 0x03
struct rzv2m_dedicated_configs {
const char *name;
u32 config;
};
struct rzv2m_pinctrl_data {
const char * const *port_pins;
const u32 *port_pin_configs;
const struct rzv2m_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
};
struct rzv2m_pinctrl {
struct pinctrl_dev *pctl;
struct pinctrl_desc desc;
struct pinctrl_pin_desc *pins;
const struct rzv2m_pinctrl_data *data;
void __iomem *base;
struct device *dev;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
spinlock_t lock; /* lock read/write registers */
struct mutex mutex; /* serialize adding groups and functions */
};
static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 };
static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 };
static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 };
static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 };
/* Helper for registers that have a write enable bit in the upper word */
static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value)
{
writel((BIT(16) | value) << shift, addr);
}
static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl,
u8 port, u8 pin, u8 func)
{
void __iomem *addr;
/* Mask input/output */
rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
/* Select the function and set the write enable bits */
addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr);
/* Unmask input/output */
rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
};
static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int func_selector,
unsigned int group_selector)
{
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
unsigned int i, *psel_val;
struct group_desc *group;
int *pins;
func = pinmux_generic_get_function(pctldev, func_selector);
if (!func)
return -EINVAL;
group = pinctrl_generic_get_group(pctldev, group_selector);
if (!group)
return -EINVAL;
psel_val = func->data;
pins = group->pins;
for (i = 0; i < group->num_pins; i++) {
dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
psel_val[i]);
rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]),
RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
}
return 0;
};
static int rzv2m_map_add_config(struct pinctrl_map *map,
const char *group_or_pin,
enum pinctrl_map_type type,
unsigned long *configs,
unsigned int num_configs)
{
unsigned long *cfgs;
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
GFP_KERNEL);
if (!cfgs)
return -ENOMEM;
map->type = type;
map->data.configs.group_or_pin = group_or_pin;
map->data.configs.configs = cfgs;
map->data.configs.num_configs = num_configs;
return 0;
}
static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct device_node *parent,
struct pinctrl_map **map,
unsigned int *num_maps,
unsigned int *index)
{
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_map *maps = *map;
unsigned int nmaps = *num_maps;
unsigned long *configs = NULL;
unsigned int *pins, *psel_val;
unsigned int num_pinmux = 0;
unsigned int idx = *index;
unsigned int num_pins, i;
unsigned int num_configs;
struct property *pinmux;
struct property *prop;
int ret, gsel, fsel;
const char **pin_fn;
const char *name;
const char *pin;
pinmux = of_find_property(np, "pinmux", NULL);
if (pinmux)
num_pinmux = pinmux->length / sizeof(u32);
ret = of_property_count_strings(np, "pins");
if (ret == -EINVAL) {
num_pins = 0;
} else if (ret < 0) {
dev_err(pctrl->dev, "Invalid pins list in DT\n");
return ret;
} else {
num_pins = ret;
}
if (!num_pinmux && !num_pins)
return 0;
if (num_pinmux && num_pins) {
dev_err(pctrl->dev,
"DT node must contain either a pinmux or pins and not both\n");
return -EINVAL;
}
ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
if (ret < 0)
return ret;
if (num_pins && !num_configs) {
dev_err(pctrl->dev, "DT node must contain a config\n");
ret = -ENODEV;
goto done;
}
if (num_pinmux)
nmaps += 1;
if (num_pins)
nmaps += num_pins;
maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
if (!maps) {
ret = -ENOMEM;
goto done;
}
*map = maps;
*num_maps = nmaps;
if (num_pins) {
of_property_for_each_string(np, "pins", prop, pin) {
ret = rzv2m_map_add_config(&maps[idx], pin,
PIN_MAP_TYPE_CONFIGS_PIN,
configs, num_configs);
if (ret < 0)
goto done;
idx++;
}
ret = 0;
goto done;
}
pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
GFP_KERNEL);
pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
if (!pins || !psel_val || !pin_fn) {
ret = -ENOMEM;
goto done;
}
/* Collect pin locations and mux settings from DT properties */
for (i = 0; i < num_pinmux; ++i) {
u32 value;
ret = of_property_read_u32_index(np, "pinmux", i, &value);
if (ret)
goto done;
pins[i] = value & MUX_PIN_ID_MASK;
psel_val[i] = MUX_FUNC(value);
}
if (parent) {
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
parent, np);
if (!name) {
ret = -ENOMEM;
goto done;
}
} else {
name = np->name;
}
mutex_lock(&pctrl->mutex);
/* Register a single pin group listing all the pins we read from DT */
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
if (gsel < 0) {
ret = gsel;
goto unlock;
}
/*
* Register a single group function where the 'data' is an array PSEL
* register values read from DT.
*/
pin_fn[0] = name;
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
if (fsel < 0) {
ret = fsel;
goto remove_group;
}
mutex_unlock(&pctrl->mutex);
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
maps[idx].data.mux.group = name;
maps[idx].data.mux.function = name;
idx++;
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
ret = 0;
goto done;
remove_group:
pinctrl_generic_remove_group(pctldev, gsel);
unlock:
mutex_unlock(&pctrl->mutex);
done:
*index = idx;
kfree(configs);
return ret;
}
static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned int num_maps)
{
unsigned int i;
if (!map)
return;
for (i = 0; i < num_maps; ++i) {
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree(map[i].data.configs.configs);
}
kfree(map);
}
static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct device_node *child;
unsigned int index;
int ret;
*map = NULL;
*num_maps = 0;
index = 0;
for_each_child_of_node(np, child) {
ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
num_maps, &index);
if (ret < 0) {
of_node_put(child);
goto done;
}
}
if (*num_maps == 0) {
ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map,
num_maps, &index);
if (ret < 0)
goto done;
}
if (*num_maps)
return 0;
dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
ret = -EINVAL;
done:
rzv2m_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl,
u32 cfg, u32 port, u8 bit)
{
u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg);
u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg);
u32 data;
if (bit >= pincount || port >= pctrl->data->n_port_pins)
return -EINVAL;
data = pctrl->data->port_pin_configs[port];
if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data))
return -EINVAL;
return 0;
}
static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset,
u8 shift, u32 mask, u32 val)
{
void __iomem *addr = pctrl->base + offset;
unsigned long flags;
u32 reg;
spin_lock_irqsave(&pctrl->lock, flags);
reg = readl(addr) & ~(mask << shift);
writel(reg | (val << shift), addr);
spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *config)
{
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
unsigned int *pin_data = pin->drv_data;
unsigned int arg = 0;
u32 port;
u32 cfg;
u8 bit;
u32 val;
if (!pin_data)
return -EINVAL;
if (*pin_data & RZV2M_SINGLE_PIN) {
port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
} else {
cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
port = RZV2M_PIN_ID_TO_PORT(_pin);
bit = RZV2M_PIN_ID_TO_PIN(_pin);
if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
return -EINVAL;
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN: {
enum pin_config_param bias;
if (!(cfg & PIN_CFG_BIAS))
return -EINVAL;
/* PUPD uses 2-bits per pin */
bit *= 2;
switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
case 0:
bias = PIN_CONFIG_BIAS_PULL_DOWN;
break;
case 2:
bias = PIN_CONFIG_BIAS_PULL_UP;
break;
default:
bias = PIN_CONFIG_BIAS_DISABLE;
}
if (bias != param)
return -EINVAL;
break;
}
case PIN_CONFIG_DRIVE_STRENGTH_UA:
if (!(cfg & PIN_CFG_DRV))
return -EINVAL;
/* DRV uses 2-bits per pin */
bit *= 2;
val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
switch (cfg & PIN_CFG_GRP_MASK) {
case PIN_CFG_GRP_1_8V_2:
arg = drv_1_8V_group2_uA[val];
break;
case PIN_CFG_GRP_1_8V_3:
arg = drv_1_8V_group3_uA[val];
break;
case PIN_CFG_GRP_SWIO_2:
arg = drv_SWIO_group2_3_3V_uA[val];
break;
case PIN_CFG_GRP_SWIO_1:
case PIN_CFG_GRP_3_3V:
arg = drv_3_3V_group_uA[val];
break;
default:
return -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
if (!(cfg & PIN_CFG_SLEW))
return -EINVAL;
arg = readl(pctrl->base + SR(port)) & BIT(bit);
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
};
static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *_configs,
unsigned int num_configs)
{
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
unsigned int *pin_data = pin->drv_data;
enum pin_config_param param;
u32 port;
unsigned int i;
u32 cfg;
u8 bit;
u32 val;
if (!pin_data)
return -EINVAL;
if (*pin_data & RZV2M_SINGLE_PIN) {
port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
} else {
cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
port = RZV2M_PIN_ID_TO_PORT(_pin);
bit = RZV2M_PIN_ID_TO_PIN(_pin);
if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
return -EINVAL;
}
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(_configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!(cfg & PIN_CFG_BIAS))
return -EINVAL;
/* PUPD uses 2-bits per pin */
bit *= 2;
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
val = 0;
break;
case PIN_CONFIG_BIAS_PULL_UP:
val = 2;
break;
default:
val = 1;
}
rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA: {
unsigned int arg = pinconf_to_config_argument(_configs[i]);
const unsigned int *drv_strengths;
unsigned int index;
if (!(cfg & PIN_CFG_DRV))
return -EINVAL;
switch (cfg & PIN_CFG_GRP_MASK) {
case PIN_CFG_GRP_1_8V_2:
drv_strengths = drv_1_8V_group2_uA;
break;
case PIN_CFG_GRP_1_8V_3:
drv_strengths = drv_1_8V_group3_uA;
break;
case PIN_CFG_GRP_SWIO_2:
drv_strengths = drv_SWIO_group2_3_3V_uA;
break;
case PIN_CFG_GRP_SWIO_1:
case PIN_CFG_GRP_3_3V:
drv_strengths = drv_3_3V_group_uA;
break;
default:
return -EINVAL;
}
for (index = 0; index < 4; index++) {
if (arg == drv_strengths[index])
break;
}
if (index >= 4)
return -EINVAL;
/* DRV uses 2-bits per pin */
bit *= 2;
rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
break;
}
case PIN_CONFIG_SLEW_RATE: {
unsigned int arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_SLEW))
return -EINVAL;
rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
break;
}
default:
return -EOPNOTSUPP;
}
}
return 0;
}
static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs,
num_configs);
if (ret)
return ret;
}
return 0;
};
static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
const unsigned int *pins;
unsigned int i, npins, prev_config = 0;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config);
if (ret)
return ret;
/* Check config matches previous pins */
if (i && prev_config != *config)
return -EOPNOTSUPP;
prev_config = *config;
}
return 0;
};
static const struct pinctrl_ops rzv2m_pinctrl_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = rzv2m_dt_node_to_map,
.dt_free_map = rzv2m_dt_free_map,
};
static const struct pinmux_ops rzv2m_pinctrl_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = rzv2m_pinctrl_set_mux,
.strict = true,
};
static const struct pinconf_ops rzv2m_pinctrl_confops = {
.is_generic = true,
.pin_config_get = rzv2m_pinctrl_pinconf_get,
.pin_config_set = rzv2m_pinctrl_pinconf_set,
.pin_config_group_set = rzv2m_pinctrl_pinconf_group_set,
.pin_config_group_get = rzv2m_pinctrl_pinconf_group_get,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
int ret;
ret = pinctrl_gpio_request(chip->base + offset);
if (ret)
return ret;
rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0);
return 0;
}
static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port,
u8 bit, bool output)
{
rzv2m_writel_we(pctrl->base + OE(port), bit, output);
rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
}
static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int rzv2m_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
rzv2m_gpio_set_direction(pctrl, port, bit, false);
return 0;
}
static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
}
static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
rzv2m_gpio_set(chip, offset, value);
rzv2m_gpio_set_direction(pctrl, port, bit, true);
return 0;
}
static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
u32 port = RZV2M_PIN_ID_TO_PORT(offset);
u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
int direction = rzv2m_gpio_get_direction(chip, offset);
if (direction == GPIO_LINE_DIRECTION_IN)
return !!(readl(pctrl->base + DI(port)) & BIT(bit));
else
return !!(readl(pctrl->base + DO(port)) & BIT(bit));
}
static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
pinctrl_gpio_free(chip->base + offset);
/*
* Set the GPIO as an input to ensure that the next GPIO request won't
* drive the GPIO pin as an output.
*/
rzv2m_gpio_direction_input(chip, offset);
}
static const char * const rzv2m_gpio_names[] = {
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
"P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15",
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
"P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15",
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
"P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15",
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
"P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15",
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
"P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15",
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
"P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15",
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
"P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15",
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
"P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15",
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
"P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15",
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
"P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15",
"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
"P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15",
"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
"P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15",
"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
"P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15",
"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
"P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15",
"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
"P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15",
"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
"P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15",
"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
"P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15",
"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
"P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15",
"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
"P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15",
"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
"P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15",
"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
"P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15",
"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
"P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15",
};
static const u32 rzv2m_gpio_configs[] = {
RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(8, 2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(8, 4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(4, 5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(6, 7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(8, 8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(8, 9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(9, 10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(9, 11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(4, 12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(8, 14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(1, 17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
RZV2M_GPIO_PORT_PACK(0, 18, 0),
RZV2M_GPIO_PORT_PACK(0, 19, 0),
RZV2M_GPIO_PORT_PACK(3, 20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV),
RZV2M_GPIO_PORT_PACK(1, 21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW),
};
static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = {
{ "NAWPN", RZV2M_SINGLE_PIN_PACK(0,
(PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "IM0CLK", RZV2M_SINGLE_PIN_PACK(1,
(PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "IM1CLK", RZV2M_SINGLE_PIN_PACK(2,
(PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "DETDO", RZV2M_SINGLE_PIN_PACK(5,
(PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "DETMS", RZV2M_SINGLE_PIN_PACK(6,
(PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12,
(PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
{ "USPWEN", RZV2M_SINGLE_PIN_PACK(14,
(PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
};
static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
{
struct device_node *np = pctrl->dev->of_node;
struct gpio_chip *chip = &pctrl->gpio_chip;
const char *name = dev_name(pctrl->dev);
struct of_phandle_args of_args;
int ret;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
if (ret) {
dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
return ret;
}
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
of_args.args[2] != pctrl->data->n_port_pins) {
dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
return -EINVAL;
}
chip->names = pctrl->data->port_pins;
chip->request = rzv2m_gpio_request;
chip->free = rzv2m_gpio_free;
chip->get_direction = rzv2m_gpio_get_direction;
chip->direction_input = rzv2m_gpio_direction_input;
chip->direction_output = rzv2m_gpio_direction_output;
chip->get = rzv2m_gpio_get;
chip->set = rzv2m_gpio_set;
chip->label = name;
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
chip->base = -1;
chip->ngpio = of_args.args[2];
pctrl->gpio_range.id = 0;
pctrl->gpio_range.pin_base = 0;
pctrl->gpio_range.base = 0;
pctrl->gpio_range.npins = chip->ngpio;
pctrl->gpio_range.name = chip->label;
pctrl->gpio_range.gc = chip;
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO controller\n");
return ret;
}
dev_dbg(pctrl->dev, "Registered gpio controller\n");
return 0;
}
static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
{
struct pinctrl_pin_desc *pins;
unsigned int i, j;
u32 *pin_data;
int ret;
pctrl->desc.name = DRV_NAME;
pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
pctrl->desc.confops = &rzv2m_pinctrl_confops;
pctrl->desc.owner = THIS_MODULE;
pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
sizeof(*pin_data), GFP_KERNEL);
if (!pin_data)
return -ENOMEM;
pctrl->pins = pins;
pctrl->desc.pins = pins;
for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
pins[i].number = i;
pins[i].name = pctrl->data->port_pins[i];
if (i && !(i % RZV2M_PINS_PER_PORT))
j++;
pin_data[i] = pctrl->data->port_pin_configs[j];
pins[i].drv_data = &pin_data[i];
}
for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
unsigned int index = pctrl->data->n_port_pins + i;
pins[index].number = index;
pins[index].name = pctrl->data->dedicated_pins[i].name;
pin_data[index] = pctrl->data->dedicated_pins[i].config;
pins[index].drv_data = &pin_data[index];
}
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
&pctrl->pctl);
if (ret) {
dev_err(pctrl->dev, "pinctrl registration failed\n");
return ret;
}
ret = pinctrl_enable(pctrl->pctl);
if (ret) {
dev_err(pctrl->dev, "pinctrl enable failed\n");
return ret;
}
ret = rzv2m_gpio_register(pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
return ret;
}
return 0;
}
static int rzv2m_pinctrl_probe(struct platform_device *pdev)
{
struct rzv2m_pinctrl *pctrl;
struct clk *clk;
int ret;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
pctrl->data = of_device_get_match_data(&pdev->dev);
if (!pctrl->data)
return -EINVAL;
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);
clk = devm_clk_get_enabled(pctrl->dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(pctrl->dev, PTR_ERR(clk),
"failed to enable GPIO clk\n");
spin_lock_init(&pctrl->lock);
mutex_init(&pctrl->mutex);
platform_set_drvdata(pdev, pctrl);
ret = rzv2m_pinctrl_register(pctrl);
if (ret)
return ret;
dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
return 0;
}
static struct rzv2m_pinctrl_data r9a09g011_data = {
.port_pins = rzv2m_gpio_names,
.port_pin_configs = rzv2m_gpio_configs,
.dedicated_pins = rzv2m_dedicated_pins,
.n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins),
};
static const struct of_device_id rzv2m_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a09g011-pinctrl",
.data = &r9a09g011_data,
},
{ /* sentinel */ }
};
static struct platform_driver rzv2m_pinctrl_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(rzv2m_pinctrl_of_table),
},
.probe = rzv2m_pinctrl_probe,
};
static int __init rzv2m_pinctrl_init(void)
{
return platform_driver_register(&rzv2m_pinctrl_driver);
}
core_initcall(rzv2m_pinctrl_init);
MODULE_AUTHOR("Phil Edworthy <[email protected]>");
MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M");
|
linux-master
|
drivers/pinctrl/renesas/pinctrl-rzv2m.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* R8A77995 processor support - PFC hardware block.
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
*/
/* GPSR0 */
#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
#define GPSR0_1 FM(USB0_OVC)
#define GPSR0_0 FM(USB0_PWEN)
/* GPSR1 */
#define GPSR1_31 F_(QPOLB, IP4_27_24)
#define GPSR1_30 F_(QPOLA, IP4_23_20)
#define GPSR1_29 F_(DU_CDE, IP4_19_16)
#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
#define GPSR1_27 F_(DU_DISP, IP4_11_8)
#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
#define GPSR1_23 F_(DU_DR7, IP3_27_24)
#define GPSR1_22 F_(DU_DR6, IP3_23_20)
#define GPSR1_21 F_(DU_DR5, IP3_19_16)
#define GPSR1_20 F_(DU_DR4, IP3_15_12)
#define GPSR1_19 F_(DU_DR3, IP3_11_8)
#define GPSR1_18 F_(DU_DR2, IP3_7_4)
#define GPSR1_17 F_(DU_DR1, IP3_3_0)
#define GPSR1_16 F_(DU_DR0, IP2_31_28)
#define GPSR1_15 F_(DU_DG7, IP2_27_24)
#define GPSR1_14 F_(DU_DG6, IP2_23_20)
#define GPSR1_13 F_(DU_DG5, IP2_19_16)
#define GPSR1_12 F_(DU_DG4, IP2_15_12)
#define GPSR1_11 F_(DU_DG3, IP2_11_8)
#define GPSR1_10 F_(DU_DG2, IP2_7_4)
#define GPSR1_9 F_(DU_DG1, IP2_3_0)
#define GPSR1_8 F_(DU_DG0, IP1_31_28)
#define GPSR1_7 F_(DU_DB7, IP1_27_24)
#define GPSR1_6 F_(DU_DB6, IP1_23_20)
#define GPSR1_5 F_(DU_DB5, IP1_19_16)
#define GPSR1_4 F_(DU_DB4, IP1_15_12)
#define GPSR1_3 F_(DU_DB3, IP1_11_8)
#define GPSR1_2 F_(DU_DB2, IP1_7_4)
#define GPSR1_1 F_(DU_DB1, IP1_3_0)
#define GPSR1_0 F_(DU_DB0, IP0_31_28)
/* GPSR2 */
#define GPSR2_31 F_(NFCE_N, IP8_19_16)
#define GPSR2_30 F_(NFCLE, IP8_15_12)
#define GPSR2_29 F_(NFALE, IP8_11_8)
#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
#define GPSR2_5 FM(VI4_DATA4)
#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
#define GPSR2_0 FM(VI4_CLK)
/* GPSR3 */
#define GPSR3_9 F_(NFDATA7, IP9_31_28)
#define GPSR3_8 F_(NFDATA6, IP9_27_24)
#define GPSR3_7 F_(NFDATA5, IP9_23_20)
#define GPSR3_6 F_(NFDATA4, IP9_19_16)
#define GPSR3_5 F_(NFDATA3, IP9_15_12)
#define GPSR3_4 F_(NFDATA2, IP9_11_8)
#define GPSR3_3 F_(NFDATA1, IP9_7_4)
#define GPSR3_2 F_(NFDATA0, IP9_3_0)
#define GPSR3_1 F_(NFWE_N, IP8_31_28)
#define GPSR3_0 F_(NFRE_N, IP8_27_24)
/* GPSR4 */
#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
#define GPSR4_27 FM(TX2)
#define GPSR4_26 FM(RX2)
#define GPSR4_25 F_(SCK2, IP12_11_8)
#define GPSR4_24 F_(TX1_A, IP12_7_4)
#define GPSR4_23 F_(RX1_A, IP12_3_0)
#define GPSR4_22 F_(SCK1_A, IP11_31_28)
#define GPSR4_21 F_(TX0_A, IP11_27_24)
#define GPSR4_20 F_(RX0_A, IP11_23_20)
#define GPSR4_19 F_(SCK0_A, IP11_19_16)
#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
#define GPSR4_15 FM(MSIOF0_RXD)
#define GPSR4_14 FM(MSIOF0_TXD)
#define GPSR4_13 FM(MSIOF0_SYNC)
#define GPSR4_12 FM(MSIOF0_SCK)
#define GPSR4_11 F_(SDA1, IP11_3_0)
#define GPSR4_10 F_(SCL1, IP10_31_28)
#define GPSR4_9 FM(SDA0)
#define GPSR4_8 FM(SCL0)
#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
#define GPSR4_0 F_(NFRB_N, IP8_23_20)
/* GPSR5 */
#define GPSR5_20 FM(AVB0_LINK)
#define GPSR5_19 FM(AVB0_PHY_INT)
#define GPSR5_18 FM(AVB0_MAGIC)
#define GPSR5_17 FM(AVB0_MDC)
#define GPSR5_16 FM(AVB0_MDIO)
#define GPSR5_15 FM(AVB0_TXCREFCLK)
#define GPSR5_14 FM(AVB0_TD3)
#define GPSR5_13 FM(AVB0_TD2)
#define GPSR5_12 FM(AVB0_TD1)
#define GPSR5_11 FM(AVB0_TD0)
#define GPSR5_10 FM(AVB0_TXC)
#define GPSR5_9 FM(AVB0_TX_CTL)
#define GPSR5_8 FM(AVB0_RD3)
#define GPSR5_7 FM(AVB0_RD2)
#define GPSR5_6 FM(AVB0_RD1)
#define GPSR5_5 FM(AVB0_RD0)
#define GPSR5_4 FM(AVB0_RXC)
#define GPSR5_3 FM(AVB0_RX_CTL)
#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
/* GPSR6 */
#define GPSR6_13 FM(RPC_INT_N)
#define GPSR6_12 FM(RPC_RESET_N)
#define GPSR6_11 FM(QSPI1_SSL)
#define GPSR6_10 FM(QSPI1_IO3)
#define GPSR6_9 FM(QSPI1_IO2)
#define GPSR6_8 FM(QSPI1_MISO_IO1)
#define GPSR6_7 FM(QSPI1_MOSI_IO0)
#define GPSR6_6 FM(QSPI1_SPCLK)
#define GPSR6_5 FM(QSPI0_SSL)
#define GPSR6_4 FM(QSPI0_IO3)
#define GPSR6_3 FM(QSPI0_IO2)
#define GPSR6_2 FM(QSPI0_MISO_IO1)
#define GPSR6_1 FM(QSPI0_MOSI_IO0)
#define GPSR6_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
GPSR1_31 GPSR2_31 GPSR4_31 \
GPSR1_30 GPSR2_30 GPSR4_30 \
GPSR1_29 GPSR2_29 GPSR4_29 \
GPSR1_28 GPSR2_28 GPSR4_28 \
GPSR1_27 GPSR2_27 GPSR4_27 \
GPSR1_26 GPSR2_26 GPSR4_26 \
GPSR1_25 GPSR2_25 GPSR4_25 \
GPSR1_24 GPSR2_24 GPSR4_24 \
GPSR1_23 GPSR2_23 GPSR4_23 \
GPSR1_22 GPSR2_22 GPSR4_22 \
GPSR1_21 GPSR2_21 GPSR4_21 \
GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
#define PINMUX_IPSR \
\
FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
\
FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
\
FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
\
FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
FM(IP12_11_8) IP12_11_8 \
FM(IP12_15_12) IP12_15_12 \
FM(IP12_19_16) IP12_19_16 \
FM(IP12_23_20) IP12_23_20 \
FM(IP12_27_24) IP12_27_24 \
FM(IP12_31_28) IP12_31_28 \
/* The bit numbering in MOD_SEL fields is reversed */
#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
#define PINMUX_MOD_SELS \
\
MOD_SEL1_31 \
MOD_SEL0_30 MOD_SEL1_30 \
MOD_SEL0_29 MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27 MOD_SEL1_27 \
MOD_SEL0_26 MOD_SEL1_26 \
MOD_SEL0_25 \
MOD_SEL0_24_23 \
MOD_SEL0_22_21 \
MOD_SEL0_20_19 \
MOD_SEL0_18_17 \
MOD_SEL0_15 \
MOD_SEL0_14 \
MOD_SEL0_13 \
MOD_SEL0_12 \
MOD_SEL0_11 \
MOD_SEL0_10 \
MOD_SEL0_5 \
MOD_SEL0_4 \
MOD_SEL0_3 \
MOD_SEL0_2 \
MOD_SEL0_1 \
MOD_SEL0_0
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
PINMUX_SINGLE(USB0_OVC),
PINMUX_SINGLE(USB0_PWEN),
PINMUX_SINGLE(VI4_DATA4),
PINMUX_SINGLE(VI4_CLK),
PINMUX_SINGLE(TX2),
PINMUX_SINGLE(RX2),
PINMUX_SINGLE(AVB0_LINK),
PINMUX_SINGLE(AVB0_PHY_INT),
PINMUX_SINGLE(AVB0_MAGIC),
PINMUX_SINGLE(AVB0_MDC),
PINMUX_SINGLE(AVB0_MDIO),
PINMUX_SINGLE(AVB0_TXCREFCLK),
PINMUX_SINGLE(AVB0_TD3),
PINMUX_SINGLE(AVB0_TD2),
PINMUX_SINGLE(AVB0_TD1),
PINMUX_SINGLE(AVB0_TD0),
PINMUX_SINGLE(AVB0_TXC),
PINMUX_SINGLE(AVB0_TX_CTL),
PINMUX_SINGLE(AVB0_RD3),
PINMUX_SINGLE(AVB0_RD2),
PINMUX_SINGLE(AVB0_RD1),
PINMUX_SINGLE(AVB0_RD0),
PINMUX_SINGLE(AVB0_RXC),
PINMUX_SINGLE(AVB0_RX_CTL),
PINMUX_SINGLE(RPC_INT_N),
PINMUX_SINGLE(RPC_RESET_N),
PINMUX_SINGLE(QSPI1_SSL),
PINMUX_SINGLE(QSPI1_IO3),
PINMUX_SINGLE(QSPI1_IO2),
PINMUX_SINGLE(QSPI1_MISO_IO1),
PINMUX_SINGLE(QSPI1_MOSI_IO0),
PINMUX_SINGLE(QSPI1_SPCLK),
PINMUX_SINGLE(QSPI0_SSL),
PINMUX_SINGLE(QSPI0_IO3),
PINMUX_SINGLE(QSPI0_IO2),
PINMUX_SINGLE(QSPI0_MISO_IO1),
PINMUX_SINGLE(QSPI0_MOSI_IO0),
PINMUX_SINGLE(QSPI0_SPCLK),
PINMUX_SINGLE(SCL0),
PINMUX_SINGLE(SDA0),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_TXD),
PINMUX_SINGLE(MSIOF0_SYNC),
PINMUX_SINGLE(MSIOF0_SCK),
/* IPSR0 */
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
/* IPSR2 */
PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
/* IPSR3 */
PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
PINMUX_IPSR_GPSR(IP3_19_16, NMI),
PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
/* IPSR4 */
PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
/* IPSR5 */
PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
/* IPSR6 */
PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
/* IPSR8 */
PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
/* IPSR10 */
PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
/* IPSR12 */
PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
/* IPSR13 */
PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------- */
static const unsigned int audio_clk_a_pins[] = {
/* CLK A */
RCAR_GP_PIN(4, 1),
};
static const unsigned int audio_clk_a_mux[] = {
AUDIO_CLKA_MARK,
};
static const unsigned int audio_clk_b_pins[] = {
/* CLK B */
RCAR_GP_PIN(2, 27),
};
static const unsigned int audio_clk_b_mux[] = {
AUDIO_CLKB_MARK,
};
static const unsigned int audio_clkout_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(4, 5),
};
static const unsigned int audio_clkout_mux[] = {
AUDIO_CLKOUT_MARK,
};
static const unsigned int audio_clkout1_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(4, 22),
};
static const unsigned int audio_clkout1_mux[] = {
AUDIO_CLKOUT1_MARK,
};
/* - EtherAVB --------------------------------------------------------------- */
static const unsigned int avb0_link_pins[] = {
/* AVB0_LINK */
RCAR_GP_PIN(5, 20),
};
static const unsigned int avb0_link_mux[] = {
AVB0_LINK_MARK,
};
static const unsigned int avb0_magic_pins[] = {
/* AVB0_MAGIC */
RCAR_GP_PIN(5, 18),
};
static const unsigned int avb0_magic_mux[] = {
AVB0_MAGIC_MARK,
};
static const unsigned int avb0_phy_int_pins[] = {
/* AVB0_PHY_INT */
RCAR_GP_PIN(5, 19),
};
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
};
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_mii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
* AVB0_TD1, AVB0_TD2, AVB0_TD3,
* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
* AVB0_RD1, AVB0_RD2, AVB0_RD3,
* AVB0_TXCREFCLK
*/
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 15),
};
static const unsigned int avb0_mii_mux[] = {
AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
AVB0_TXCREFCLK_MARK,
};
static const unsigned int avb0_avtp_pps_a_pins[] = {
/* AVB0_AVTP_PPS_A */
RCAR_GP_PIN(5, 2),
};
static const unsigned int avb0_avtp_pps_a_mux[] = {
AVB0_AVTP_PPS_A_MARK,
};
static const unsigned int avb0_avtp_match_a_pins[] = {
/* AVB0_AVTP_MATCH_A */
RCAR_GP_PIN(5, 1),
};
static const unsigned int avb0_avtp_match_a_mux[] = {
AVB0_AVTP_MATCH_A_MARK,
};
static const unsigned int avb0_avtp_capture_a_pins[] = {
/* AVB0_AVTP_CAPTURE_A */
RCAR_GP_PIN(5, 0),
};
static const unsigned int avb0_avtp_capture_a_mux[] = {
AVB0_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb0_avtp_pps_b_pins[] = {
/* AVB0_AVTP_PPS_B */
RCAR_GP_PIN(4, 16),
};
static const unsigned int avb0_avtp_pps_b_mux[] = {
AVB0_AVTP_PPS_B_MARK,
};
static const unsigned int avb0_avtp_match_b_pins[] = {
/* AVB0_AVTP_MATCH_B */
RCAR_GP_PIN(4, 18),
};
static const unsigned int avb0_avtp_match_b_mux[] = {
AVB0_AVTP_MATCH_B_MARK,
};
static const unsigned int avb0_avtp_capture_b_pins[] = {
/* AVB0_AVTP_CAPTURE_B */
RCAR_GP_PIN(4, 17),
};
static const unsigned int avb0_avtp_capture_b_mux[] = {
AVB0_AVTP_CAPTURE_B_MARK,
};
/* - CAN ------------------------------------------------------------------ */
static const unsigned int can0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
};
static const unsigned int can0_data_a_mux[] = {
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can1_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
};
static const unsigned int can1_data_a_mux[] = {
CAN1_TX_A_MARK, CAN1_RX_A_MARK,
};
static const unsigned int can1_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
};
static const unsigned int can1_data_b_mux[] = {
CAN1_TX_B_MARK, CAN1_RX_B_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(5, 2),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - CAN FD ----------------------------------------------------------------- */
static const unsigned int canfd0_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
};
static const unsigned int canfd0_data_mux[] = {
CANFD0_TX_MARK, CANFD0_RX_MARK,
};
static const unsigned int canfd1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_in_1_pins[] = {
/* CLKIN */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_clk_in_1_mux[] = {
DU_DOTCLKIN1_MARK
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 24),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_sync_pins[] = {
/* VSYNC, HSYNC */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int du_sync_mux[] = {
DU_VSYNC_MARK, DU_HSYNC_MARK
};
static const unsigned int du_disp_cde_pins[] = {
/* DISP_CDE */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_disp_cde_mux[] = {
DU_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(1, 29),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
};
static const unsigned int i2c1_mux[] = {
SCL1_MARK, SDA1_MARK,
};
static const unsigned int i2c2_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
};
static const unsigned int i2c2_a_mux[] = {
SCL2_A_MARK, SDA2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
};
static const unsigned int i2c2_b_mux[] = {
SCL2_B_MARK, SDA2_B_MARK,
};
static const unsigned int i2c3_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
};
static const unsigned int i2c3_a_mux[] = {
SCL3_A_MARK, SDA3_A_MARK,
};
static const unsigned int i2c3_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
};
static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
/* - MLB+ ------------------------------------------------------------------- */
static const unsigned int mlb_3pin_pins[] = {
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
};
static const unsigned int mlb_3pin_mux[] = {
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
};
/* - MMC ------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
};
static const unsigned int mmc_data_mux[] = {
MMC_D0_MARK, MMC_D1_MARK,
MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK,
MMC_D6_MARK, MMC_D7_MARK,
};
static const unsigned int mmc_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
};
static const unsigned int mmc_ctrl_mux[] = {
MMC_CLK_MARK, MMC_CMD_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 12),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(4, 13),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(4, 20),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(4, 21),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
RCAR_GP_PIN(4, 14),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
RCAR_GP_PIN(4, 15),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 16),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* SYNC */
RCAR_GP_PIN(4, 19),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(4, 25),
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(4, 22),
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* TXD */
RCAR_GP_PIN(4, 17),
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* RXD */
RCAR_GP_PIN(4, 18),
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof2_clk_mux[] = {
MSIOF2_SCK_MARK,
};
static const unsigned int msiof2_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof2_sync_a_mux[] = {
MSIOF2_SYNC_A_MARK,
};
static const unsigned int msiof2_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof2_sync_b_mux[] = {
MSIOF2_SYNC_B_MARK,
};
static const unsigned int msiof2_ss1_pins[] = {
/* SS1 */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof2_ss1_mux[] = {
MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_pins[] = {
/* SS2 */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof2_ss2_mux[] = {
MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* TXD */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_rxd_pins[] = {
/* RXD */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof2_rxd_mux[] = {
MSIOF2_RXD_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 24),
};
static const unsigned int msiof3_clk_a_mux[] = {
MSIOF3_SCK_A_MARK,
};
static const unsigned int msiof3_sync_a_pins[] = {
/* SYNC */
RCAR_GP_PIN(2, 21),
};
static const unsigned int msiof3_sync_a_mux[] = {
MSIOF3_SYNC_A_MARK,
};
static const unsigned int msiof3_ss1_a_pins[] = {
/* SS1 */
RCAR_GP_PIN(2, 14),
};
static const unsigned int msiof3_ss1_a_mux[] = {
MSIOF3_SS1_A_MARK,
};
static const unsigned int msiof3_ss2_a_pins[] = {
/* SS2 */
RCAR_GP_PIN(2, 10),
};
static const unsigned int msiof3_ss2_a_mux[] = {
MSIOF3_SS2_A_MARK,
};
static const unsigned int msiof3_txd_a_pins[] = {
/* TXD */
RCAR_GP_PIN(2, 22),
};
static const unsigned int msiof3_txd_a_mux[] = {
MSIOF3_TXD_A_MARK,
};
static const unsigned int msiof3_rxd_a_pins[] = {
/* RXD */
RCAR_GP_PIN(2, 23),
};
static const unsigned int msiof3_rxd_a_mux[] = {
MSIOF3_RXD_A_MARK,
};
static const unsigned int msiof3_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 8),
};
static const unsigned int msiof3_clk_b_mux[] = {
MSIOF3_SCK_B_MARK,
};
static const unsigned int msiof3_sync_b_pins[] = {
/* SYNC */
RCAR_GP_PIN(1, 9),
};
static const unsigned int msiof3_sync_b_mux[] = {
MSIOF3_SYNC_B_MARK,
};
static const unsigned int msiof3_ss1_b_pins[] = {
/* SS1 */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof3_ss1_b_mux[] = {
MSIOF3_SS1_B_MARK,
};
static const unsigned int msiof3_ss2_b_pins[] = {
/* SS2 */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof3_ss2_b_mux[] = {
MSIOF3_SS2_B_MARK,
};
static const unsigned int msiof3_txd_b_pins[] = {
/* TXD */
RCAR_GP_PIN(1, 0),
};
static const unsigned int msiof3_txd_b_mux[] = {
MSIOF3_TXD_B_MARK,
};
static const unsigned int msiof3_rxd_b_pins[] = {
/* RXD */
RCAR_GP_PIN(1, 1),
};
static const unsigned int msiof3_rxd_b_mux[] = {
MSIOF3_RXD_B_MARK,
};
/* - PWM0 ------------------------------------------------------------------ */
static const unsigned int pwm0_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 1),
};
static const unsigned int pwm0_a_mux[] = {
PWM0_A_MARK,
};
static const unsigned int pwm0_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 18),
};
static const unsigned int pwm0_b_mux[] = {
PWM0_B_MARK,
};
static const unsigned int pwm0_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 29),
};
static const unsigned int pwm0_c_mux[] = {
PWM0_C_MARK,
};
/* - PWM1 ------------------------------------------------------------------ */
static const unsigned int pwm1_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 2),
};
static const unsigned int pwm1_a_mux[] = {
PWM1_A_MARK,
};
static const unsigned int pwm1_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 19),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
static const unsigned int pwm1_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 30),
};
static const unsigned int pwm1_c_mux[] = {
PWM1_C_MARK,
};
/* - PWM2 ------------------------------------------------------------------ */
static const unsigned int pwm2_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 3),
};
static const unsigned int pwm2_a_mux[] = {
PWM2_A_MARK,
};
static const unsigned int pwm2_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 22),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
static const unsigned int pwm2_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 31),
};
static const unsigned int pwm2_c_mux[] = {
PWM2_C_MARK,
};
/* - PWM3 ------------------------------------------------------------------ */
static const unsigned int pwm3_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 4),
};
static const unsigned int pwm3_a_mux[] = {
PWM3_A_MARK,
};
static const unsigned int pwm3_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 27),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
static const unsigned int pwm3_c_pins[] = {
/* PWM */
RCAR_GP_PIN(4, 0),
};
static const unsigned int pwm3_c_mux[] = {
PWM3_C_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
/* - RPC -------------------------------------------------------------------- */
static const unsigned int rpc_clk_pins[] = {
/* Octal-SPI flash: C/SCLK */
/* HyperFlash: CK, CK# */
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
};
static const unsigned int rpc_clk_mux[] = {
QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
};
static const unsigned int rpc_ctrl_pins[] = {
/* Octal-SPI flash: S#/CS, DQS */
/* HyperFlash: CS#, RDS */
RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
};
static const unsigned int rpc_ctrl_mux[] = {
QSPI0_SSL_MARK, QSPI1_SSL_MARK,
};
static const unsigned int rpc_data_pins[] = {
/* DQ[0:7] */
RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
};
static const unsigned int rpc_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
static const unsigned int rpc_reset_pins[] = {
/* RPC_RESET# */
RCAR_GP_PIN(6, 12),
};
static const unsigned int rpc_reset_mux[] = {
RPC_RESET_N_MARK,
};
static const unsigned int rpc_int_pins[] = {
/* RPC_INT# */
RCAR_GP_PIN(6, 13),
};
static const unsigned int rpc_int_mux[] = {
RPC_INT_N_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
};
static const unsigned int scif0_data_a_mux[] = {
RX0_A_MARK, TX0_A_MARK,
};
static const unsigned int scif0_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 19),
};
static const unsigned int scif0_clk_a_mux[] = {
SCK0_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
};
static const unsigned int scif0_data_b_mux[] = {
RX0_B_MARK, TX0_B_MARK,
};
static const unsigned int scif0_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 2),
};
static const unsigned int scif0_clk_b_mux[] = {
SCK0_B_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
};
static const unsigned int scif1_data_a_mux[] = {
RX1_A_MARK, TX1_A_MARK,
};
static const unsigned int scif1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 22),
};
static const unsigned int scif1_clk_a_mux[] = {
SCK1_A_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
};
static const unsigned int scif1_data_b_mux[] = {
RX1_B_MARK, TX1_B_MARK,
};
static const unsigned int scif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 25),
};
static const unsigned int scif1_clk_b_mux[] = {
SCK1_B_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
static const unsigned int scif2_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
};
static const unsigned int scif2_data_mux[] = {
RX2_MARK, TX2_MARK,
};
static const unsigned int scif2_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 25),
};
static const unsigned int scif2_clk_mux[] = {
SCK2_MARK,
};
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
};
static const unsigned int scif3_data_a_mux[] = {
RX3_A_MARK, TX3_A_MARK,
};
static const unsigned int scif3_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 30),
};
static const unsigned int scif3_clk_a_mux[] = {
SCK3_A_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
};
static const unsigned int scif3_data_b_mux[] = {
RX3_B_MARK, TX3_B_MARK,
};
static const unsigned int scif3_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 29),
};
static const unsigned int scif3_clk_b_mux[] = {
SCK3_B_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
};
static const unsigned int scif4_data_a_mux[] = {
RX4_A_MARK, TX4_A_MARK,
};
static const unsigned int scif4_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 6),
};
static const unsigned int scif4_clk_a_mux[] = {
SCK4_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
};
static const unsigned int scif4_data_b_mux[] = {
RX4_B_MARK, TX4_B_MARK,
};
static const unsigned int scif4_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 15),
};
static const unsigned int scif4_clk_b_mux[] = {
SCK4_B_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
static const unsigned int scif5_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
};
static const unsigned int scif5_data_a_mux[] = {
RX5_A_MARK, TX5_A_MARK,
};
static const unsigned int scif5_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 6),
};
static const unsigned int scif5_clk_a_mux[] = {
SCK5_A_MARK,
};
static const unsigned int scif5_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
};
static const unsigned int scif5_data_b_mux[] = {
RX5_B_MARK, TX5_B_MARK,
};
static const unsigned int scif5_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 3),
};
static const unsigned int scif5_clk_b_mux[] = {
SCK5_B_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_pins[] = {
/* SCIF_CLK */
RCAR_GP_PIN(2, 27),
};
static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
/* - SSI ---------------------------------------------------------------*/
static const unsigned int ssi3_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(4, 3),
};
static const unsigned int ssi3_data_mux[] = {
SSI_SDATA3_MARK,
};
static const unsigned int ssi34_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
};
static const unsigned int ssi34_ctrl_mux[] = {
SSI_SCK34_MARK, SSI_WS34_MARK,
};
static const unsigned int ssi4_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
};
static const unsigned int ssi4_ctrl_a_mux[] = {
SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
};
static const unsigned int ssi4_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(4, 6),
};
static const unsigned int ssi4_data_a_mux[] = {
SSI_SDATA4_A_MARK,
};
static const unsigned int ssi4_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
};
static const unsigned int ssi4_ctrl_b_mux[] = {
SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
};
static const unsigned int ssi4_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(2, 16),
};
static const unsigned int ssi4_data_b_mux[] = {
SSI_SDATA4_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_pins[] = {
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
};
static const unsigned int vin4_data18_mux[] = {
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data_pins[] = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
};
static const unsigned int vin4_data_mux[] = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(2, 27),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(2, 28),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(2, 0),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a),
SH_PFC_PIN_GROUP(audio_clk_b),
SH_PFC_PIN_GROUP(audio_clkout),
SH_PFC_PIN_GROUP(audio_clkout1),
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_mii),
SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
SH_PFC_PIN_GROUP(avb0_avtp_match_a),
SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
SH_PFC_PIN_GROUP(avb0_avtp_match_b),
SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data_a),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_1),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_disp_cde),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(mlb_3pin),
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof2_clk),
SH_PFC_PIN_GROUP(msiof2_sync_a),
SH_PFC_PIN_GROUP(msiof2_sync_b),
SH_PFC_PIN_GROUP(msiof2_ss1),
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_rxd),
SH_PFC_PIN_GROUP(msiof3_clk_a),
SH_PFC_PIN_GROUP(msiof3_sync_a),
SH_PFC_PIN_GROUP(msiof3_ss1_a),
SH_PFC_PIN_GROUP(msiof3_ss2_a),
SH_PFC_PIN_GROUP(msiof3_txd_a),
SH_PFC_PIN_GROUP(msiof3_rxd_a),
SH_PFC_PIN_GROUP(msiof3_clk_b),
SH_PFC_PIN_GROUP(msiof3_sync_b),
SH_PFC_PIN_GROUP(msiof3_ss1_b),
SH_PFC_PIN_GROUP(msiof3_ss2_b),
SH_PFC_PIN_GROUP(msiof3_txd_b),
SH_PFC_PIN_GROUP(msiof3_rxd_b),
SH_PFC_PIN_GROUP(pwm0_a),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm0_c),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm1_c),
SH_PFC_PIN_GROUP(pwm2_a),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm2_c),
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm3_c),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
BUS_DATA_PIN_GROUP(rpc_clk, 1),
BUS_DATA_PIN_GROUP(rpc_clk, 2),
SH_PFC_PIN_GROUP(rpc_ctrl),
SH_PFC_PIN_GROUP(rpc_data),
SH_PFC_PIN_GROUP(rpc_reset),
SH_PFC_PIN_GROUP(rpc_int),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_clk_b),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scif1_data_a),
SH_PFC_PIN_GROUP(scif1_clk_a),
SH_PFC_PIN_GROUP(scif1_data_b),
SH_PFC_PIN_GROUP(scif1_clk_b),
SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(scif2_data),
SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(scif3_data_a),
SH_PFC_PIN_GROUP(scif3_clk_a),
SH_PFC_PIN_GROUP(scif3_data_b),
SH_PFC_PIN_GROUP(scif3_clk_b),
SH_PFC_PIN_GROUP(scif4_data_a),
SH_PFC_PIN_GROUP(scif4_clk_a),
SH_PFC_PIN_GROUP(scif4_data_b),
SH_PFC_PIN_GROUP(scif4_clk_b),
SH_PFC_PIN_GROUP(scif5_data_a),
SH_PFC_PIN_GROUP(scif5_clk_a),
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(ssi3_data),
SH_PFC_PIN_GROUP(ssi34_ctrl),
SH_PFC_PIN_GROUP(ssi4_ctrl_a),
SH_PFC_PIN_GROUP(ssi4_data_a),
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
BUS_DATA_PIN_GROUP(vin4_data, 8),
BUS_DATA_PIN_GROUP(vin4_data, 10),
BUS_DATA_PIN_GROUP(vin4_data, 12),
BUS_DATA_PIN_GROUP(vin4_data, 16),
SH_PFC_PIN_GROUP(vin4_data18),
BUS_DATA_PIN_GROUP(vin4_data, 20),
BUS_DATA_PIN_GROUP(vin4_data, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
};
static const char * const audio_clk_groups[] = {
"audio_clk_a",
"audio_clk_b",
"audio_clkout",
"audio_clkout1",
};
static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
"avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
"avb0_mdio",
"avb0_mii",
"avb0_avtp_pps_a",
"avb0_avtp_match_a",
"avb0_avtp_capture_a",
"avb0_avtp_pps_b",
"avb0_avtp_match_b",
"avb0_avtp_capture_b",
};
static const char * const can0_groups[] = {
"can0_data_a",
"can0_data_b",
};
static const char * const can1_groups[] = {
"can1_data_a",
"can1_data_b",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const canfd0_groups[] = {
"canfd0_data",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_in_1",
"du_clk_out_0",
"du_sync",
"du_disp_cde",
"du_cde",
"du_disp",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1",
};
static const char * const i2c2_groups[] = {
"i2c2_a",
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3_a",
"i2c3_b",
};
static const char * const mlb_3pin_groups[] = {
"mlb_3pin",
};
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
"mmc_ctrl",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_txd",
"msiof1_rxd",
};
static const char * const msiof2_groups[] = {
"msiof2_clk",
"msiof2_sync_a",
"msiof2_sync_b",
"msiof2_ss1",
"msiof2_ss2",
"msiof2_txd",
"msiof2_rxd",
};
static const char * const msiof3_groups[] = {
"msiof3_clk_a",
"msiof3_sync_a",
"msiof3_ss1_a",
"msiof3_ss2_a",
"msiof3_txd_a",
"msiof3_rxd_a",
"msiof3_clk_b",
"msiof3_sync_b",
"msiof3_ss1_b",
"msiof3_ss2_b",
"msiof3_txd_b",
"msiof3_rxd_b",
};
static const char * const pwm0_groups[] = {
"pwm0_a",
"pwm0_b",
"pwm0_c",
};
static const char * const pwm1_groups[] = {
"pwm1_a",
"pwm1_b",
"pwm1_c",
};
static const char * const pwm2_groups[] = {
"pwm2_a",
"pwm2_b",
"pwm2_c",
};
static const char * const pwm3_groups[] = {
"pwm3_a",
"pwm3_b",
"pwm3_c",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const rpc_groups[] = {
"rpc_clk1",
"rpc_clk2",
"rpc_ctrl",
"rpc_data",
"rpc_reset",
"rpc_int",
};
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_clk_a",
"scif0_data_b",
"scif0_clk_b",
"scif0_ctrl",
};
static const char * const scif1_groups[] = {
"scif1_data_a",
"scif1_clk_a",
"scif1_data_b",
"scif1_clk_b",
"scif1_ctrl",
};
static const char * const scif2_groups[] = {
"scif2_data",
"scif2_clk",
};
static const char * const scif3_groups[] = {
"scif3_data_a",
"scif3_clk_a",
"scif3_data_b",
"scif3_clk_b",
};
static const char * const scif4_groups[] = {
"scif4_data_a",
"scif4_clk_a",
"scif4_data_b",
"scif4_clk_b",
};
static const char * const scif5_groups[] = {
"scif5_data_a",
"scif5_clk_a",
"scif5_data_b",
"scif5_clk_b",
};
static const char * const scif_clk_groups[] = {
"scif_clk",
};
static const char * const ssi_groups[] = {
"ssi3_data",
"ssi34_ctrl",
"ssi4_ctrl_a",
"ssi4_data_a",
"ssi4_ctrl_b",
"ssi4_data_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const vin4_groups[] = {
"vin4_data8",
"vin4_data10",
"vin4_data12",
"vin4_data16",
"vin4_data18",
"vin4_data20",
"vin4_data24",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(mlb_3pin),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(rpc),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(vin4),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP0_31_9 RESERVED */
GP_0_8_FN, GPSR0_8,
GP_0_7_FN, GPSR0_7,
GP_0_6_FN, GPSR0_6,
GP_0_5_FN, GPSR0_5,
GP_0_4_FN, GPSR0_4,
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
GP_1_31_FN, GPSR1_31,
GP_1_30_FN, GPSR1_30,
GP_1_29_FN, GPSR1_29,
GP_1_28_FN, GPSR1_28,
GP_1_27_FN, GPSR1_27,
GP_1_26_FN, GPSR1_26,
GP_1_25_FN, GPSR1_25,
GP_1_24_FN, GPSR1_24,
GP_1_23_FN, GPSR1_23,
GP_1_22_FN, GPSR1_22,
GP_1_21_FN, GPSR1_21,
GP_1_20_FN, GPSR1_20,
GP_1_19_FN, GPSR1_19,
GP_1_18_FN, GPSR1_18,
GP_1_17_FN, GPSR1_17,
GP_1_16_FN, GPSR1_16,
GP_1_15_FN, GPSR1_15,
GP_1_14_FN, GPSR1_14,
GP_1_13_FN, GPSR1_13,
GP_1_12_FN, GPSR1_12,
GP_1_11_FN, GPSR1_11,
GP_1_10_FN, GPSR1_10,
GP_1_9_FN, GPSR1_9,
GP_1_8_FN, GPSR1_8,
GP_1_7_FN, GPSR1_7,
GP_1_6_FN, GPSR1_6,
GP_1_5_FN, GPSR1_5,
GP_1_4_FN, GPSR1_4,
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
GP_2_31_FN, GPSR2_31,
GP_2_30_FN, GPSR2_30,
GP_2_29_FN, GPSR2_29,
GP_2_28_FN, GPSR2_28,
GP_2_27_FN, GPSR2_27,
GP_2_26_FN, GPSR2_26,
GP_2_25_FN, GPSR2_25,
GP_2_24_FN, GPSR2_24,
GP_2_23_FN, GPSR2_23,
GP_2_22_FN, GPSR2_22,
GP_2_21_FN, GPSR2_21,
GP_2_20_FN, GPSR2_20,
GP_2_19_FN, GPSR2_19,
GP_2_18_FN, GPSR2_18,
GP_2_17_FN, GPSR2_17,
GP_2_16_FN, GPSR2_16,
GP_2_15_FN, GPSR2_15,
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
GP_2_11_FN, GPSR2_11,
GP_2_10_FN, GPSR2_10,
GP_2_9_FN, GPSR2_9,
GP_2_8_FN, GPSR2_8,
GP_2_7_FN, GPSR2_7,
GP_2_6_FN, GPSR2_6,
GP_2_5_FN, GPSR2_5,
GP_2_4_FN, GPSR2_4,
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP3_31_10 RESERVED */
GP_3_9_FN, GPSR3_9,
GP_3_8_FN, GPSR3_8,
GP_3_7_FN, GPSR3_7,
GP_3_6_FN, GPSR3_6,
GP_3_5_FN, GPSR3_5,
GP_3_4_FN, GPSR3_4,
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
GP_4_31_FN, GPSR4_31,
GP_4_30_FN, GPSR4_30,
GP_4_29_FN, GPSR4_29,
GP_4_28_FN, GPSR4_28,
GP_4_27_FN, GPSR4_27,
GP_4_26_FN, GPSR4_26,
GP_4_25_FN, GPSR4_25,
GP_4_24_FN, GPSR4_24,
GP_4_23_FN, GPSR4_23,
GP_4_22_FN, GPSR4_22,
GP_4_21_FN, GPSR4_21,
GP_4_20_FN, GPSR4_20,
GP_4_19_FN, GPSR4_19,
GP_4_18_FN, GPSR4_18,
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
GP_4_14_FN, GPSR4_14,
GP_4_13_FN, GPSR4_13,
GP_4_12_FN, GPSR4_12,
GP_4_11_FN, GPSR4_11,
GP_4_10_FN, GPSR4_10,
GP_4_9_FN, GPSR4_9,
GP_4_8_FN, GPSR4_8,
GP_4_7_FN, GPSR4_7,
GP_4_6_FN, GPSR4_6,
GP_4_5_FN, GPSR4_5,
GP_4_4_FN, GPSR4_4,
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* GP5_31_21 RESERVED */
GP_5_20_FN, GPSR5_20,
GP_5_19_FN, GPSR5_19,
GP_5_18_FN, GPSR5_18,
GP_5_17_FN, GPSR5_17,
GP_5_16_FN, GPSR5_16,
GP_5_15_FN, GPSR5_15,
GP_5_14_FN, GPSR5_14,
GP_5_13_FN, GPSR5_13,
GP_5_12_FN, GPSR5_12,
GP_5_11_FN, GPSR5_11,
GP_5_10_FN, GPSR5_10,
GP_5_9_FN, GPSR5_9,
GP_5_8_FN, GPSR5_8,
GP_5_7_FN, GPSR5_7,
GP_5_6_FN, GPSR5_6,
GP_5_5_FN, GPSR5_5,
GP_5_4_FN, GPSR5_4,
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1),
GROUP(
/* GP6_31_14 RESERVED */
GP_6_13_FN, GPSR6_13,
GP_6_12_FN, GPSR6_12,
GP_6_11_FN, GPSR6_11,
GP_6_10_FN, GPSR6_10,
GP_6_9_FN, GPSR6_9,
GP_6_8_FN, GPSR6_8,
GP_6_7_FN, GPSR6_7,
GP_6_6_FN, GPSR6_6,
GP_6_5_FN, GPSR6_5,
GP_6_4_FN, GPSR6_4,
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
IP0_19_16
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
IP1_19_16
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
IP2_19_16
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
IP3_19_16
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
IP4_19_16
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
IP5_19_16
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
IP6_19_16
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
IP8_19_16
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
IP9_19_16
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
IP10_19_16
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
IP11_19_16
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
IP12_19_16
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
GROUP(-24, 4, 4),
GROUP(
/* IP13_31_8 RESERVED */
IP13_7_4
IP13_3_0 ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31 */
MOD_SEL0_30
MOD_SEL0_29
MOD_SEL0_28
MOD_SEL0_27
MOD_SEL0_26
MOD_SEL0_25
MOD_SEL0_24_23
MOD_SEL0_22_21
MOD_SEL0_20_19
MOD_SEL0_18_17
/* RESERVED 16 */
MOD_SEL0_15
MOD_SEL0_14
MOD_SEL0_13
MOD_SEL0_12
MOD_SEL0_11
MOD_SEL0_10
/* RESERVED 9, 8, 7, 6 */
MOD_SEL0_5
MOD_SEL0_4
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
MOD_SEL0_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(1, 1, 1, 1, 1, 1, -26),
GROUP(
MOD_SEL1_31
MOD_SEL1_30
MOD_SEL1_29
MOD_SEL1_28
MOD_SEL1_27
MOD_SEL1_26
/* RESERVED 25-0 */ ))
},
{ /* sentinel */ }
};
enum ioctrl_regs {
POCCTRL0,
POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
[POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ }
};
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
switch (pin) {
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return 29 - (pin - RCAR_GP_PIN(3, 0));
case PIN_VDDQ_AVB0:
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
return 0;
default:
return -EINVAL;
}
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
[10] = PIN_MLB_REF, /* MLB_REF */
[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[22] = PIN_FSCLKST_N, /* FSCLKST# */
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = PIN_TDI, /* TDI */
[29] = PIN_TMS, /* TMS */
[30] = PIN_TCK, /* TCK */
[31] = PIN_TRST_N, /* TRST# */
} },
{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
[12] = RCAR_GP_PIN(2, 29), /* NFALE */
[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
} },
{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
} },
{ /* sentinel */ }
};
static const struct pinmux_bias_reg *
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *puen_bit, unsigned int *pud_bit)
{
const struct pinmux_bias_reg *reg;
unsigned int bit;
reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
if (!reg)
return reg;
*puen_bit = bit;
/* NFWE# and NFRE# use different bit positions in PUD2 */
switch (pin) {
case RCAR_GP_PIN(3, 0): /* NFRE# */
*pud_bit = 7;
break;
case RCAR_GP_PIN(3, 1): /* NFWE# */
*pud_bit = 8;
break;
default:
*pud_bit = bit;
break;
}
return reg;
}
static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
{
const struct pinmux_bias_reg *reg;
unsigned int puen_bit, pud_bit;
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
if (!reg)
return PIN_CONFIG_BIAS_DISABLE;
if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
return PIN_CONFIG_BIAS_DISABLE;
else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
}
static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
const struct pinmux_bias_reg *reg;
unsigned int puen_bit, pud_bit;
u32 enable, updown;
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
if (!reg)
return;
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
if (bias != PIN_CONFIG_BIAS_DISABLE) {
enable |= BIT(puen_bit);
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
if (bias == PIN_CONFIG_BIAS_PULL_UP)
updown |= BIT(pud_bit);
sh_pfc_write(pfc, reg->pud, updown);
}
sh_pfc_write(pfc, reg->puen, enable);
}
static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
.get_bias = r8a77995_pinmux_get_bias,
.set_bias = r8a77995_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
.name = "r8a77995_pfc",
.ops = &r8a77995_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
|
linux-master
|
drivers/pinctrl/renesas/pfc-r8a77995.c
|
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