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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Zhiyong Tao <[email protected]>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8365.h"
static const struct mtk_drv_group_desc mt8365_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8365_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
MTK_PIN_DRV_GRP(7, 0x710, 4, 2),
MTK_PIN_DRV_GRP(8, 0x710, 8, 2),
MTK_PIN_DRV_GRP(9, 0x710, 8, 2),
MTK_PIN_DRV_GRP(10, 0x710, 8, 2),
MTK_PIN_DRV_GRP(11, 0x710, 8, 2),
MTK_PIN_DRV_GRP(12, 0x710, 12, 2),
MTK_PIN_DRV_GRP(13, 0x710, 12, 2),
MTK_PIN_DRV_GRP(14, 0x710, 12, 2),
MTK_PIN_DRV_GRP(15, 0x710, 12, 2),
MTK_PIN_DRV_GRP(16, 0x710, 16, 2),
MTK_PIN_DRV_GRP(17, 0x710, 16, 2),
MTK_PIN_DRV_GRP(18, 0x710, 16, 2),
MTK_PIN_DRV_GRP(19, 0x710, 20, 2),
MTK_PIN_DRV_GRP(20, 0x710, 24, 2),
MTK_PIN_DRV_GRP(21, 0x710, 24, 2),
MTK_PIN_DRV_GRP(22, 0x710, 28, 2),
MTK_PIN_DRV_GRP(23, 0x720, 0, 2),
MTK_PIN_DRV_GRP(24, 0x720, 0, 2),
MTK_PIN_DRV_GRP(25, 0x720, 0, 2),
MTK_PIN_DRV_GRP(26, 0x720, 4, 2),
MTK_PIN_DRV_GRP(27, 0x720, 4, 2),
MTK_PIN_DRV_GRP(28, 0x720, 4, 2),
MTK_PIN_DRV_GRP(29, 0x720, 4, 2),
MTK_PIN_DRV_GRP(30, 0x720, 8, 2),
MTK_PIN_DRV_GRP(31, 0x720, 8, 2),
MTK_PIN_DRV_GRP(32, 0x720, 8, 2),
MTK_PIN_DRV_GRP(33, 0x720, 8, 2),
MTK_PIN_DRV_GRP(34, 0x720, 8, 2),
MTK_PIN_DRV_GRP(35, 0x720, 12, 2),
MTK_PIN_DRV_GRP(36, 0x720, 12, 2),
MTK_PIN_DRV_GRP(37, 0x720, 12, 2),
MTK_PIN_DRV_GRP(38, 0x720, 12, 2),
MTK_PIN_DRV_GRP(39, 0x720, 12, 2),
MTK_PIN_DRV_GRP(40, 0x720, 12, 2),
MTK_PIN_DRV_GRP(41, 0x720, 16, 2),
MTK_PIN_DRV_GRP(42, 0x720, 16, 2),
MTK_PIN_DRV_GRP(43, 0x720, 16, 2),
MTK_PIN_DRV_GRP(44, 0x720, 16, 2),
MTK_PIN_DRV_GRP(45, 0x720, 20, 2),
MTK_PIN_DRV_GRP(46, 0x720, 20, 2),
MTK_PIN_DRV_GRP(47, 0x720, 20, 2),
MTK_PIN_DRV_GRP(48, 0x720, 20, 2),
MTK_PIN_DRV_GRP(49, 0x720, 24, 2),
MTK_PIN_DRV_GRP(50, 0x720, 24, 2),
MTK_PIN_DRV_GRP(51, 0x720, 24, 2),
MTK_PIN_DRV_GRP(52, 0x720, 24, 2),
MTK_PIN_DRV_GRP(53, 0x720, 24, 2),
MTK_PIN_DRV_GRP(54, 0x720, 24, 2),
MTK_PIN_DRV_GRP(55, 0x720, 24, 2),
MTK_PIN_DRV_GRP(56, 0x720, 24, 2),
MTK_PIN_DRV_GRP(57, 0x720, 28, 2),
MTK_PIN_DRV_GRP(58, 0x720, 28, 2),
MTK_PIN_DRV_GRP(59, 0x730, 0, 2),
MTK_PIN_DRV_GRP(60, 0x730, 0, 2),
MTK_PIN_DRV_GRP(61, 0x730, 4, 2),
MTK_PIN_DRV_GRP(62, 0x730, 4, 2),
MTK_PIN_DRV_GRP(63, 0x730, 8, 2),
MTK_PIN_DRV_GRP(64, 0x730, 8, 2),
MTK_PIN_DRV_GRP(65, 0x730, 12, 2),
MTK_PIN_DRV_GRP(66, 0x730, 12, 2),
MTK_PIN_DRV_GRP(67, 0x730, 12, 2),
MTK_PIN_DRV_GRP(68, 0x730, 12, 2),
MTK_PIN_DRV_GRP(69, 0x730, 12, 2),
MTK_PIN_DRV_GRP(70, 0x730, 12, 2),
MTK_PIN_DRV_GRP(71, 0x730, 16, 2),
MTK_PIN_DRV_GRP(72, 0x730, 16, 2),
MTK_PIN_DRV_GRP(73, 0x730, 16, 2),
MTK_PIN_DRV_GRP(74, 0x730, 16, 2),
MTK_PIN_DRV_GRP(75, 0x730, 16, 2),
MTK_PIN_DRV_GRP(76, 0x730, 16, 2),
MTK_PIN_DRV_GRP(77, 0x730, 16, 2),
MTK_PIN_DRV_GRP(78, 0x730, 16, 2),
MTK_PIN_DRV_GRP(79, 0x730, 16, 2),
MTK_PIN_DRV_GRP(80, 0x730, 20, 2),
MTK_PIN_DRV_GRP(81, 0x730, 24, 2),
MTK_PIN_DRV_GRP(82, 0x730, 28, 2),
MTK_PIN_DRV_GRP(83, 0x730, 28, 2),
MTK_PIN_DRV_GRP(84, 0x730, 28, 2),
MTK_PIN_DRV_GRP(85, 0x730, 28, 2),
MTK_PIN_DRV_GRP(86, 0x740, 12, 2),
MTK_PIN_DRV_GRP(87, 0x740, 16, 2),
MTK_PIN_DRV_GRP(88, 0x740, 20, 2),
MTK_PIN_DRV_GRP(89, 0x740, 24, 2),
MTK_PIN_DRV_GRP(90, 0x740, 24, 2),
MTK_PIN_DRV_GRP(91, 0x740, 24, 2),
MTK_PIN_DRV_GRP(92, 0x740, 24, 2),
MTK_PIN_DRV_GRP(93, 0x750, 8, 2),
MTK_PIN_DRV_GRP(94, 0x750, 8, 2),
MTK_PIN_DRV_GRP(95, 0x750, 8, 2),
MTK_PIN_DRV_GRP(96, 0x750, 8, 2),
MTK_PIN_DRV_GRP(97, 0x750, 24, 2),
MTK_PIN_DRV_GRP(98, 0x750, 28, 2),
MTK_PIN_DRV_GRP(99, 0x760, 0, 2),
MTK_PIN_DRV_GRP(100, 0x750, 8, 2),
MTK_PIN_DRV_GRP(101, 0x750, 8, 2),
MTK_PIN_DRV_GRP(102, 0x750, 8, 2),
MTK_PIN_DRV_GRP(103, 0x750, 8, 2),
MTK_PIN_DRV_GRP(104, 0x760, 20, 2),
MTK_PIN_DRV_GRP(105, 0x760, 24, 2),
MTK_PIN_DRV_GRP(106, 0x760, 24, 2),
MTK_PIN_DRV_GRP(107, 0x760, 24, 2),
MTK_PIN_DRV_GRP(108, 0x760, 24, 2),
MTK_PIN_DRV_GRP(109, 0x760, 24, 2),
MTK_PIN_DRV_GRP(110, 0x760, 28, 2),
MTK_PIN_DRV_GRP(111, 0x760, 28, 2),
MTK_PIN_DRV_GRP(112, 0x760, 28, 2),
MTK_PIN_DRV_GRP(113, 0x760, 28, 2),
MTK_PIN_DRV_GRP(114, 0x770, 0, 2),
MTK_PIN_DRV_GRP(115, 0x770, 0, 2),
MTK_PIN_DRV_GRP(116, 0x770, 0, 2),
MTK_PIN_DRV_GRP(117, 0x770, 4, 2),
MTK_PIN_DRV_GRP(118, 0x770, 4, 2),
MTK_PIN_DRV_GRP(119, 0x770, 4, 2),
MTK_PIN_DRV_GRP(120, 0x770, 8, 2),
MTK_PIN_DRV_GRP(121, 0x770, 8, 2),
MTK_PIN_DRV_GRP(122, 0x770, 8, 2),
MTK_PIN_DRV_GRP(123, 0x770, 12, 2),
MTK_PIN_DRV_GRP(124, 0x770, 12, 2),
MTK_PIN_DRV_GRP(125, 0x770, 12, 2),
MTK_PIN_DRV_GRP(126, 0x770, 16, 2),
MTK_PIN_DRV_GRP(127, 0x770, 16, 2),
MTK_PIN_DRV_GRP(128, 0x770, 16, 2),
MTK_PIN_DRV_GRP(129, 0x770, 20, 2),
MTK_PIN_DRV_GRP(130, 0x770, 20, 2),
MTK_PIN_DRV_GRP(131, 0x770, 20, 2),
MTK_PIN_DRV_GRP(132, 0x770, 20, 2),
MTK_PIN_DRV_GRP(133, 0x770, 20, 2),
MTK_PIN_DRV_GRP(134, 0x770, 20, 2),
MTK_PIN_DRV_GRP(135, 0x770, 20, 2),
MTK_PIN_DRV_GRP(136, 0x770, 24, 2),
MTK_PIN_DRV_GRP(137, 0x770, 24, 2),
MTK_PIN_DRV_GRP(138, 0x770, 24, 2),
MTK_PIN_DRV_GRP(139, 0x770, 24, 2),
MTK_PIN_DRV_GRP(140, 0x770, 24, 2),
MTK_PIN_DRV_GRP(141, 0x770, 24, 2),
MTK_PIN_DRV_GRP(142, 0x770, 24, 2),
MTK_PIN_DRV_GRP(143, 0x770, 24, 2),
MTK_PIN_DRV_GRP(144, 0x770, 24, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8365_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(22, 0x070, 0, 2, 1),
MTK_PIN_PUPD_SPEC_SR(23, 0x070, 3, 5, 4),
MTK_PIN_PUPD_SPEC_SR(24, 0x070, 6, 8, 7),
MTK_PIN_PUPD_SPEC_SR(25, 0x070, 9, 11, 10),
MTK_PIN_PUPD_SPEC_SR(80, 0x070, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(81, 0x070, 17, 16, 15),
MTK_PIN_PUPD_SPEC_SR(82, 0x070, 20, 19, 18),
MTK_PIN_PUPD_SPEC_SR(83, 0x070, 23, 22, 21),
MTK_PIN_PUPD_SPEC_SR(84, 0x070, 26, 25, 24),
MTK_PIN_PUPD_SPEC_SR(85, 0x070, 29, 28, 27),
MTK_PIN_PUPD_SPEC_SR(86, 0x080, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(87, 0x080, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(88, 0x080, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(89, 0x080, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(90, 0x080, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(91, 0x080, 17, 16, 15),
MTK_PIN_PUPD_SPEC_SR(92, 0x080, 20, 19, 18),
MTK_PIN_PUPD_SPEC_SR(93, 0x080, 23, 22, 21),
MTK_PIN_PUPD_SPEC_SR(94, 0x080, 26, 25, 24),
MTK_PIN_PUPD_SPEC_SR(95, 0x080, 29, 28, 27),
MTK_PIN_PUPD_SPEC_SR(96, 0x090, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(97, 0x090, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(98, 0x090, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(99, 0x090, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(100, 0x090, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(101, 0x090, 17, 16, 15),
MTK_PIN_PUPD_SPEC_SR(102, 0x090, 20, 19, 18),
MTK_PIN_PUPD_SPEC_SR(103, 0x090, 23, 22, 21),
MTK_PIN_PUPD_SPEC_SR(104, 0x090, 26, 25, 24),
MTK_PIN_PUPD_SPEC_SR(105, 0x090, 29, 28, 27),
MTK_PIN_PUPD_SPEC_SR(106, 0x0F0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(107, 0x0F0, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(108, 0x0F0, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(109, 0x0F0, 11, 10, 9),
};
static const struct mtk_pin_ies_smt_set mt8365_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x410, 0),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x410, 1),
MTK_PIN_IES_SMT_SPEC(8, 11, 0x410, 2),
MTK_PIN_IES_SMT_SPEC(12, 15, 0x410, 3),
MTK_PIN_IES_SMT_SPEC(16, 18, 0x410, 4),
MTK_PIN_IES_SMT_SPEC(19, 19, 0x410, 5),
MTK_PIN_IES_SMT_SPEC(20, 21, 0x410, 6),
MTK_PIN_IES_SMT_SPEC(22, 22, 0x410, 7),
MTK_PIN_IES_SMT_SPEC(23, 25, 0x410, 8),
MTK_PIN_IES_SMT_SPEC(26, 29, 0x410, 9),
MTK_PIN_IES_SMT_SPEC(30, 34, 0x410, 10),
MTK_PIN_IES_SMT_SPEC(35, 40, 0x410, 11),
MTK_PIN_IES_SMT_SPEC(41, 44, 0x410, 12),
MTK_PIN_IES_SMT_SPEC(45, 48, 0x410, 13),
MTK_PIN_IES_SMT_SPEC(49, 56, 0x410, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0x410, 15),
MTK_PIN_IES_SMT_SPEC(59, 60, 0x410, 16),
MTK_PIN_IES_SMT_SPEC(61, 62, 0x410, 17),
MTK_PIN_IES_SMT_SPEC(63, 64, 0x410, 18),
MTK_PIN_IES_SMT_SPEC(65, 70, 0x410, 19),
MTK_PIN_IES_SMT_SPEC(71, 79, 0x410, 20),
MTK_PIN_IES_SMT_SPEC(80, 80, 0x410, 21),
MTK_PIN_IES_SMT_SPEC(81, 81, 0x410, 22),
MTK_PIN_IES_SMT_SPEC(82, 82, 0x410, 23),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x410, 24),
MTK_PIN_IES_SMT_SPEC(84, 84, 0x410, 25),
MTK_PIN_IES_SMT_SPEC(85, 85, 0x410, 26),
MTK_PIN_IES_SMT_SPEC(86, 86, 0x410, 27),
MTK_PIN_IES_SMT_SPEC(87, 87, 0x410, 28),
MTK_PIN_IES_SMT_SPEC(88, 88, 0x410, 29),
MTK_PIN_IES_SMT_SPEC(89, 89, 0x410, 30),
MTK_PIN_IES_SMT_SPEC(90, 90, 0x410, 31),
MTK_PIN_IES_SMT_SPEC(91, 91, 0x420, 0),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x420, 1),
MTK_PIN_IES_SMT_SPEC(93, 93, 0x420, 2),
MTK_PIN_IES_SMT_SPEC(94, 94, 0x420, 3),
MTK_PIN_IES_SMT_SPEC(95, 95, 0x420, 4),
MTK_PIN_IES_SMT_SPEC(96, 96, 0x420, 5),
MTK_PIN_IES_SMT_SPEC(97, 97, 0x420, 6),
MTK_PIN_IES_SMT_SPEC(98, 98, 0x420, 7),
MTK_PIN_IES_SMT_SPEC(99, 99, 0x420, 8),
MTK_PIN_IES_SMT_SPEC(100, 100, 0x420, 9),
MTK_PIN_IES_SMT_SPEC(101, 101, 0x420, 10),
MTK_PIN_IES_SMT_SPEC(102, 102, 0x420, 11),
MTK_PIN_IES_SMT_SPEC(103, 103, 0x420, 12),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x420, 13),
MTK_PIN_IES_SMT_SPEC(105, 109, 0x420, 14),
MTK_PIN_IES_SMT_SPEC(110, 113, 0x420, 15),
MTK_PIN_IES_SMT_SPEC(114, 116, 0x420, 16),
MTK_PIN_IES_SMT_SPEC(117, 119, 0x420, 17),
MTK_PIN_IES_SMT_SPEC(120, 122, 0x420, 18),
MTK_PIN_IES_SMT_SPEC(123, 125, 0x420, 19),
MTK_PIN_IES_SMT_SPEC(126, 128, 0x420, 20),
MTK_PIN_IES_SMT_SPEC(129, 135, 0x420, 21),
MTK_PIN_IES_SMT_SPEC(136, 144, 0x420, 22),
};
static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 0, 0x470, 0),
MTK_PIN_IES_SMT_SPEC(1, 1, 0x470, 0),
MTK_PIN_IES_SMT_SPEC(2, 2, 0x470, 0),
MTK_PIN_IES_SMT_SPEC(3, 3, 0x470, 0),
MTK_PIN_IES_SMT_SPEC(4, 4, 0x470, 1),
MTK_PIN_IES_SMT_SPEC(5, 5, 0x470, 1),
MTK_PIN_IES_SMT_SPEC(6, 6, 0x470, 1),
MTK_PIN_IES_SMT_SPEC(7, 7, 0x470, 1),
MTK_PIN_IES_SMT_SPEC(8, 8, 0x470, 2),
MTK_PIN_IES_SMT_SPEC(9, 9, 0x470, 2),
MTK_PIN_IES_SMT_SPEC(10, 10, 0x470, 2),
MTK_PIN_IES_SMT_SPEC(11, 11, 0x470, 2),
MTK_PIN_IES_SMT_SPEC(12, 12, 0x470, 3),
MTK_PIN_IES_SMT_SPEC(13, 13, 0x470, 3),
MTK_PIN_IES_SMT_SPEC(14, 14, 0x470, 3),
MTK_PIN_IES_SMT_SPEC(15, 15, 0x470, 3),
MTK_PIN_IES_SMT_SPEC(16, 16, 0x470, 4),
MTK_PIN_IES_SMT_SPEC(17, 17, 0x470, 4),
MTK_PIN_IES_SMT_SPEC(18, 18, 0x470, 4),
MTK_PIN_IES_SMT_SPEC(19, 19, 0x470, 5),
MTK_PIN_IES_SMT_SPEC(20, 20, 0x470, 6),
MTK_PIN_IES_SMT_SPEC(21, 21, 0x470, 6),
MTK_PIN_IES_SMT_SPEC(22, 22, 0x470, 7),
MTK_PIN_IES_SMT_SPEC(23, 23, 0x470, 8),
MTK_PIN_IES_SMT_SPEC(24, 24, 0x470, 8),
MTK_PIN_IES_SMT_SPEC(25, 25, 0x470, 8),
MTK_PIN_IES_SMT_SPEC(26, 26, 0x470, 9),
MTK_PIN_IES_SMT_SPEC(27, 27, 0x470, 9),
MTK_PIN_IES_SMT_SPEC(28, 28, 0x470, 9),
MTK_PIN_IES_SMT_SPEC(29, 29, 0x470, 9),
MTK_PIN_IES_SMT_SPEC(30, 30, 0x470, 10),
MTK_PIN_IES_SMT_SPEC(31, 31, 0x470, 10),
MTK_PIN_IES_SMT_SPEC(32, 32, 0x470, 10),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x470, 10),
MTK_PIN_IES_SMT_SPEC(34, 34, 0x470, 10),
MTK_PIN_IES_SMT_SPEC(35, 35, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(36, 36, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(37, 37, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(38, 38, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(39, 39, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(40, 40, 0x470, 11),
MTK_PIN_IES_SMT_SPEC(41, 41, 0x470, 12),
MTK_PIN_IES_SMT_SPEC(42, 42, 0x470, 12),
MTK_PIN_IES_SMT_SPEC(43, 43, 0x470, 12),
MTK_PIN_IES_SMT_SPEC(44, 44, 0x470, 12),
MTK_PIN_IES_SMT_SPEC(45, 45, 0x470, 13),
MTK_PIN_IES_SMT_SPEC(46, 46, 0x470, 13),
MTK_PIN_IES_SMT_SPEC(47, 47, 0x470, 13),
MTK_PIN_IES_SMT_SPEC(48, 48, 0x470, 13),
MTK_PIN_IES_SMT_SPEC(49, 49, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(50, 50, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(51, 51, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(52, 52, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(53, 53, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(54, 54, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(55, 55, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(56, 56, 0x470, 14),
MTK_PIN_IES_SMT_SPEC(57, 57, 0x470, 15),
MTK_PIN_IES_SMT_SPEC(58, 58, 0x470, 15),
MTK_PIN_IES_SMT_SPEC(59, 59, 0x470, 16),
MTK_PIN_IES_SMT_SPEC(60, 60, 0x470, 16),
MTK_PIN_IES_SMT_SPEC(61, 61, 0x470, 17),
MTK_PIN_IES_SMT_SPEC(62, 62, 0x470, 17),
MTK_PIN_IES_SMT_SPEC(63, 63, 0x470, 18),
MTK_PIN_IES_SMT_SPEC(64, 64, 0x470, 18),
MTK_PIN_IES_SMT_SPEC(65, 65, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(66, 66, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(67, 67, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(68, 68, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(69, 69, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(70, 70, 0x470, 19),
MTK_PIN_IES_SMT_SPEC(71, 71, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(72, 72, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(73, 73, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(74, 74, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(75, 75, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(76, 76, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(77, 77, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(78, 78, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(79, 79, 0x470, 20),
MTK_PIN_IES_SMT_SPEC(80, 80, 0x470, 21),
MTK_PIN_IES_SMT_SPEC(81, 81, 0x470, 22),
MTK_PIN_IES_SMT_SPEC(82, 82, 0x470, 23),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x470, 24),
MTK_PIN_IES_SMT_SPEC(84, 84, 0x470, 25),
MTK_PIN_IES_SMT_SPEC(85, 85, 0x470, 26),
MTK_PIN_IES_SMT_SPEC(86, 86, 0x470, 27),
MTK_PIN_IES_SMT_SPEC(87, 87, 0x470, 28),
MTK_PIN_IES_SMT_SPEC(88, 88, 0x470, 29),
MTK_PIN_IES_SMT_SPEC(89, 89, 0x470, 30),
MTK_PIN_IES_SMT_SPEC(90, 90, 0x470, 31),
MTK_PIN_IES_SMT_SPEC(91, 91, 0x480, 0),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x480, 1),
MTK_PIN_IES_SMT_SPEC(93, 93, 0x480, 2),
MTK_PIN_IES_SMT_SPEC(94, 94, 0x480, 3),
MTK_PIN_IES_SMT_SPEC(95, 95, 0x480, 4),
MTK_PIN_IES_SMT_SPEC(96, 96, 0x480, 5),
MTK_PIN_IES_SMT_SPEC(97, 97, 0x480, 6),
MTK_PIN_IES_SMT_SPEC(98, 98, 0x480, 7),
MTK_PIN_IES_SMT_SPEC(99, 99, 0x480, 8),
MTK_PIN_IES_SMT_SPEC(100, 100, 0x480, 9),
MTK_PIN_IES_SMT_SPEC(101, 101, 0x480, 10),
MTK_PIN_IES_SMT_SPEC(102, 102, 0x480, 11),
MTK_PIN_IES_SMT_SPEC(103, 103, 0x480, 12),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x480, 13),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x480, 14),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x480, 14),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x480, 14),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x480, 14),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x480, 14),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x480, 15),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x480, 15),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x480, 15),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x480, 15),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x480, 16),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x480, 16),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x480, 16),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x480, 17),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x480, 17),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x480, 17),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x480, 18),
MTK_PIN_IES_SMT_SPEC(121, 121, 0x480, 18),
MTK_PIN_IES_SMT_SPEC(122, 122, 0x480, 18),
MTK_PIN_IES_SMT_SPEC(123, 123, 0x480, 19),
MTK_PIN_IES_SMT_SPEC(124, 124, 0x480, 19),
MTK_PIN_IES_SMT_SPEC(125, 125, 0x480, 19),
MTK_PIN_IES_SMT_SPEC(126, 126, 0x480, 20),
MTK_PIN_IES_SMT_SPEC(127, 127, 0x480, 20),
MTK_PIN_IES_SMT_SPEC(128, 128, 0x480, 20),
MTK_PIN_IES_SMT_SPEC(129, 129, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(130, 130, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(131, 131, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(132, 132, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(133, 133, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(134, 134, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(135, 135, 0x480, 21),
MTK_PIN_IES_SMT_SPEC(136, 136, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(137, 137, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(138, 138, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(139, 139, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(140, 140, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(141, 141, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(142, 142, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(143, 143, 0x480, 22),
MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22),
};
static int mt8365_set_clr_mode(struct regmap *regmap,
unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
bool enable, bool isup)
{
int ret;
ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit);
if (ret)
return -EINVAL;
ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit);
if (ret)
return -EINVAL;
return 0;
}
static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
.pins = mtk_pins_mt8365,
.npins = ARRAY_SIZE(mtk_pins_mt8365),
.grp_desc = mt8365_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8365_drv_grp),
.pin_drv_grp = mt8365_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv),
.spec_ies = mt8365_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8365_ies_set),
.spec_smt = mt8365_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8365_smt_set),
.spec_pupd = mt8365_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.mt8365_set_clr_mode = mt8365_set_clr_mode,
.dir_offset = 0x0140,
.dout_offset = 0x00A0,
.din_offset = 0x0000,
.pinmux_offset = 0x01E0,
.ies_offset = 0x0410,
.smt_offset = 0x0470,
.pullen_offset = 0x0860,
.pullsel_offset = 0x0900,
.drv_offset = 0x0710,
.type1_start = 145,
.type1_end = 145,
.port_shf = 4,
.port_mask = 0x1f,
.port_align = 4,
.mode_mask = 0x1f,
.mode_per_reg = 10,
.mode_shf = 5,
.eint_hw = {
.port_mask = 7,
.ports = 5,
.ap_num = 160,
.db_cnt = 160,
.db_time = debounce_time_mt6765,
},
};
static const struct of_device_id mt8365_pctrl_match[] = {
{ .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data },
{}
};
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8365-pinctrl",
.of_match_table = mt8365_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver");
MODULE_AUTHOR("Zhiyong Tao <[email protected]>");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8365.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 MediaTek Inc.
*
* Author: Guodong Liu <[email protected]>
*
*/
#include "pinctrl-mtk-mt8186.h"
#include "pinctrl-paris.h"
/* MT8186 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
* iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
* iocfg[6]:0x10002C00.
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1)
static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = {
PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = {
PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_di_range[] = {
PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_do_range[] = {
PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1),
PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1),
PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1),
PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1),
PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1),
PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1),
PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1),
PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1),
PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1),
PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1),
PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1),
PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1),
PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1),
PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1),
PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1),
PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1),
PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1),
PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1),
PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1),
PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1),
PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1),
PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1),
PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1),
PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1),
PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1),
PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1),
PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1),
PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1),
PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1),
PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1),
PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1),
PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1),
PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1),
PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1),
PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1),
PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1),
PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1),
PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1),
PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1),
PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1),
PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = {
PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1),
PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1),
PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1),
PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1),
PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1),
PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1),
PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1),
PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1),
PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1),
PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1),
PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1),
PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1),
PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1),
PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1),
PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1),
PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1),
PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1),
PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1),
PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1),
PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1),
PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1),
PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1),
PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = {
PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1),
PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1),
PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1),
PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1),
PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1),
PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1),
PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1),
PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1),
PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1),
PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1),
PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1),
PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1),
PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1),
PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1),
PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1),
PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1),
PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1),
PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1),
PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1),
PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1),
PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1),
PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = {
PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = {
PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = {
PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1),
PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1),
PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1),
PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = {
PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3),
PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3),
};
static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = {
PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3),
};
static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = {
PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2),
PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2),
PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2),
PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2),
PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2),
PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2),
PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2),
PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2),
PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2),
PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2),
PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2),
PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2),
PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2),
PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2),
PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2),
PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2),
PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2),
PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2),
PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2),
PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2),
};
static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = {
PIN_RSEL(127, 128, 0x0, 75000, 75000),
PIN_RSEL(127, 128, 0x1, 10000, 75000),
PIN_RSEL(127, 128, 0x2, 5000, 5000),
PIN_RSEL(127, 128, 0x3, 1000, 5000),
PIN_RSEL(129, 130, 0x0, 75000, 75000),
PIN_RSEL(129, 130, 0x1, 10000, 75000),
PIN_RSEL(129, 130, 0x2, 5000, 5000),
PIN_RSEL(129, 130, 0x3, 1000, 5000),
PIN_RSEL(131, 132, 0x0, 75000, 75000),
PIN_RSEL(131, 132, 0x1, 10000, 75000),
PIN_RSEL(131, 132, 0x2, 5000, 5000),
PIN_RSEL(131, 132, 0x3, 1000, 5000),
PIN_RSEL(133, 134, 0x0, 75000, 75000),
PIN_RSEL(133, 134, 0x1, 10000, 75000),
PIN_RSEL(133, 134, 0x2, 5000, 5000),
PIN_RSEL(133, 134, 0x3, 1000, 5000),
PIN_RSEL(135, 136, 0x0, 75000, 75000),
PIN_RSEL(135, 136, 0x1, 10000, 75000),
PIN_RSEL(135, 136, 0x2, 5000, 5000),
PIN_RSEL(135, 136, 0x3, 1000, 5000),
PIN_RSEL(137, 138, 0x0, 75000, 75000),
PIN_RSEL(137, 138, 0x1, 10000, 75000),
PIN_RSEL(137, 138, 0x2, 5000, 5000),
PIN_RSEL(137, 138, 0x3, 1000, 5000),
PIN_RSEL(139, 140, 0x0, 75000, 75000),
PIN_RSEL(139, 140, 0x1, 10000, 75000),
PIN_RSEL(139, 140, 0x2, 5000, 5000),
PIN_RSEL(139, 140, 0x3, 1000, 5000),
PIN_RSEL(141, 142, 0x0, 75000, 75000),
PIN_RSEL(141, 142, 0x1, 10000, 75000),
PIN_RSEL(141, 142, 0x2, 5000, 5000),
PIN_RSEL(141, 142, 0x3, 1000, 5000),
PIN_RSEL(143, 144, 0x0, 75000, 75000),
PIN_RSEL(143, 144, 0x1, 10000, 75000),
PIN_RSEL(143, 144, 0x2, 5000, 5000),
PIN_RSEL(143, 144, 0x3, 1000, 5000),
PIN_RSEL(145, 146, 0x0, 75000, 75000),
PIN_RSEL(145, 146, 0x1, 10000, 75000),
PIN_RSEL(145, 146, 0x2, 5000, 5000),
PIN_RSEL(145, 146, 0x3, 1000, 5000),
};
static const unsigned int mt8186_pull_type[] = {
MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/
MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/
MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/
MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/
MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/
MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/
MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/
MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/
MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/
MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/
MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/
MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/
MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/
MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/
MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/
MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/
MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/
MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/
MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/
MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/
MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/
MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/
MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/
MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/
MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/
MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/
MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/
MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/
MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/
MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/
MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/
MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/
MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/
MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/
MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/
MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/
MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/
MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/
MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/
MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/
MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/
MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/
MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/
MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/
MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/
MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/
MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/
MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/
MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/
MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/
MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/
MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/
MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/
MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/
MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/
MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/
MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/
MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/
MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/
MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/
MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/
MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/
MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/
MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/
MTK_PULL_PU_PD_TYPE,/*184*/
};
static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range),
[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range),
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range),
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range),
};
static const char * const mt8186_pinctrl_register_base_names[] = {
"iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl",
"iocfg_rb", "iocfg_rt",
};
static const struct mtk_eint_hw mt8186_eint_hw = {
.port_mask = 0xf,
.ports = 7,
.ap_num = 217,
.db_cnt = 32,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt8186_data = {
.reg_cal = mt8186_reg_cals,
.pins = mtk_pins_mt8186,
.npins = ARRAY_SIZE(mtk_pins_mt8186),
.ngrps = ARRAY_SIZE(mtk_pins_mt8186),
.nfuncs = 8,
.gpio_m = 0,
.eint_hw = &mt8186_eint_hw,
.base_names = mt8186_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names),
.pull_type = mt8186_pull_type,
.pin_rsel = mt8186_pin_rsel_val_range,
.npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
};
static const struct of_device_id mt8186_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data },
{ }
};
static struct platform_driver mt8186_pinctrl_driver = {
.driver = {
.name = "mt8186-pinctrl",
.of_match_table = mt8186_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8186_pinctrl_init(void)
{
return platform_driver_register(&mt8186_pinctrl_driver);
}
arch_initcall(mt8186_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8186.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define MT7620_GPIO_MODE_UART0_SHIFT 2
#define MT7620_GPIO_MODE_UART0_MASK 0x7
#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
#define MT7620_GPIO_MODE_UARTF 0x0
#define MT7620_GPIO_MODE_PCM_UARTF 0x1
#define MT7620_GPIO_MODE_PCM_I2S 0x2
#define MT7620_GPIO_MODE_I2S_UARTF 0x3
#define MT7620_GPIO_MODE_PCM_GPIO 0x4
#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
#define MT7620_GPIO_MODE_GPIO_I2S 0x6
#define MT7620_GPIO_MODE_GPIO 0x7
#define MT7620_GPIO_MODE_NAND 0
#define MT7620_GPIO_MODE_SD 1
#define MT7620_GPIO_MODE_ND_SD_GPIO 2
#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
#define MT7620_GPIO_MODE_PCIE_RST 0
#define MT7620_GPIO_MODE_PCIE_REF 1
#define MT7620_GPIO_MODE_PCIE_GPIO 2
#define MT7620_GPIO_MODE_PCIE_MASK 0x3
#define MT7620_GPIO_MODE_PCIE_SHIFT 16
#define MT7620_GPIO_MODE_WDT_RST 0
#define MT7620_GPIO_MODE_WDT_REF 1
#define MT7620_GPIO_MODE_WDT_GPIO 2
#define MT7620_GPIO_MODE_WDT_MASK 0x3
#define MT7620_GPIO_MODE_WDT_SHIFT 21
#define MT7620_GPIO_MODE_MDIO 0
#define MT7620_GPIO_MODE_MDIO_REFCLK 1
#define MT7620_GPIO_MODE_MDIO_GPIO 2
#define MT7620_GPIO_MODE_MDIO_MASK 0x3
#define MT7620_GPIO_MODE_MDIO_SHIFT 7
#define MT7620_GPIO_MODE_I2C 0
#define MT7620_GPIO_MODE_UART1 5
#define MT7620_GPIO_MODE_RGMII1 9
#define MT7620_GPIO_MODE_RGMII2 10
#define MT7620_GPIO_MODE_SPI 11
#define MT7620_GPIO_MODE_SPI_REF_CLK 12
#define MT7620_GPIO_MODE_WLED 13
#define MT7620_GPIO_MODE_JTAG 15
#define MT7620_GPIO_MODE_EPHY 15
#define MT7620_GPIO_MODE_PA 20
static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
static struct mtmips_pmx_func mdio_grp[] = {
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
};
static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
static struct mtmips_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
static struct mtmips_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
static struct mtmips_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
static struct mtmips_pmx_func uartf_grp[] = {
FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct mtmips_pmx_func wdt_grp[] = {
FUNC("wdt rst", 0, 17, 1),
FUNC("wdt refclk", 0, 17, 1),
};
static struct mtmips_pmx_func pcie_rst_grp[] = {
FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
};
static struct mtmips_pmx_func nd_sd_grp[] = {
FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13)
};
static struct mtmips_pmx_group mt7620a_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
MT7620_GPIO_MODE_UART0_SHIFT),
GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
{ 0 }
};
static int mt7620_pinctrl_probe(struct platform_device *pdev)
{
return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data);
}
static const struct of_device_id mt7620_pinctrl_match[] = {
{ .compatible = "ralink,mt7620-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match);
static struct platform_driver mt7620_pinctrl_driver = {
.probe = mt7620_pinctrl_probe,
.driver = {
.name = "mt7620-pinctrl",
.of_match_table = mt7620_pinctrl_match,
},
};
static int __init mt7620_pinctrl_init(void)
{
return platform_driver_register(&mt7620_pinctrl_driver);
}
core_initcall_sync(mt7620_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7620.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Hui Liu <[email protected]>
*
*/
#include <linux/module.h>
#include "pinctrl-mtk-mt8188.h"
#include "pinctrl-paris.h"
/* MT8188 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
* iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 1)
static const struct mtk_pin_field_calc mt8188_pin_mode_range[] = {
PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8188_pin_dir_range[] = {
PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_di_range[] = {
PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_do_range[] = {
PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
PIN_FIELD_BASE(3, 3, 1, 0x0170, 0x10, 11, 1),
PIN_FIELD_BASE(4, 4, 1, 0x0170, 0x10, 18, 1),
PIN_FIELD_BASE(5, 5, 1, 0x0170, 0x10, 18, 1),
PIN_FIELD_BASE(6, 6, 1, 0x0170, 0x10, 18, 1),
PIN_FIELD_BASE(7, 7, 1, 0x0170, 0x10, 12, 1),
PIN_FIELD_BASE(8, 8, 1, 0x0170, 0x10, 13, 1),
PIN_FIELD_BASE(9, 9, 1, 0x0170, 0x10, 14, 1),
PIN_FIELD_BASE(10, 10, 1, 0x0170, 0x10, 15, 1),
PIN_FIELD_BASE(11, 11, 1, 0x0170, 0x10, 19, 1),
PIN_FIELD_BASE(12, 12, 2, 0x0160, 0x10, 12, 1),
PIN_FIELD_BASE(13, 13, 2, 0x0160, 0x10, 13, 1),
PIN_FIELD_BASE(14, 14, 2, 0x0160, 0x10, 14, 1),
PIN_FIELD_BASE(15, 15, 2, 0x0160, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 3, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(17, 17, 3, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(18, 18, 4, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(19, 19, 4, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(20, 20, 4, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(21, 21, 4, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(22, 22, 4, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 4, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 4, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 1, 0x0170, 0x10, 17, 1),
PIN_FIELD_BASE(26, 26, 1, 0x0170, 0x10, 17, 1),
PIN_FIELD_BASE(27, 27, 1, 0x0170, 0x10, 17, 1),
PIN_FIELD_BASE(28, 28, 1, 0x0170, 0x10, 18, 1),
PIN_FIELD_BASE(29, 29, 1, 0x0170, 0x10, 16, 1),
PIN_FIELD_BASE(30, 30, 1, 0x0170, 0x10, 17, 1),
PIN_FIELD_BASE(31, 31, 1, 0x0170, 0x10, 19, 1),
PIN_FIELD_BASE(32, 32, 1, 0x0170, 0x10, 19, 1),
PIN_FIELD_BASE(33, 33, 1, 0x0170, 0x10, 20, 1),
PIN_FIELD_BASE(34, 34, 1, 0x0170, 0x10, 20, 1),
PIN_FIELD_BASE(35, 35, 1, 0x0170, 0x10, 19, 1),
PIN_FIELD_BASE(36, 36, 1, 0x0170, 0x10, 20, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0170, 0x10, 21, 1),
PIN_FIELD_BASE(38, 38, 1, 0x0170, 0x10, 20, 1),
PIN_FIELD_BASE(39, 39, 1, 0x0170, 0x10, 21, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0170, 0x10, 21, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0170, 0x10, 21, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0160, 0x10, 21, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0160, 0x10, 22, 1),
PIN_FIELD_BASE(44, 44, 2, 0x0160, 0x10, 21, 1),
PIN_FIELD_BASE(45, 45, 2, 0x0160, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 3, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(47, 47, 1, 0x0170, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x0170, 0x10, 16, 1),
PIN_FIELD_BASE(49, 49, 1, 0x0170, 0x10, 16, 1),
PIN_FIELD_BASE(50, 50, 3, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(51, 51, 3, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(52, 52, 3, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(53, 53, 3, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(54, 54, 3, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0170, 0x10, 25, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0170, 0x10, 28, 1),
PIN_FIELD_BASE(57, 57, 2, 0x0160, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 2, 0x0160, 0x10, 31, 1),
PIN_FIELD_BASE(59, 59, 1, 0x0170, 0x10, 26, 1),
PIN_FIELD_BASE(60, 60, 1, 0x0170, 0x10, 29, 1),
PIN_FIELD_BASE(61, 61, 1, 0x0170, 0x10, 27, 1),
PIN_FIELD_BASE(62, 62, 1, 0x0170, 0x10, 30, 1),
PIN_FIELD_BASE(63, 63, 2, 0x0160, 0x10, 30, 1),
PIN_FIELD_BASE(64, 64, 2, 0x0170, 0x10, 0, 1),
PIN_FIELD_BASE(65, 65, 4, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(66, 66, 4, 0x00e0, 0x10, 12, 1),
PIN_FIELD_BASE(67, 67, 4, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(68, 68, 4, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0180, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0170, 0x10, 31, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0180, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0180, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0180, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0180, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0180, 0x10, 6, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0180, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 1, 0x0180, 0x10, 8, 1),
PIN_FIELD_BASE(78, 78, 1, 0x0180, 0x10, 7, 1),
PIN_FIELD_BASE(79, 79, 4, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(80, 80, 4, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(81, 81, 4, 0x00e0, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 4, 0x00e0, 0x10, 16, 1),
PIN_FIELD_BASE(83, 83, 2, 0x0160, 0x10, 26, 1),
PIN_FIELD_BASE(84, 84, 2, 0x0160, 0x10, 26, 1),
PIN_FIELD_BASE(85, 85, 2, 0x0160, 0x10, 27, 1),
PIN_FIELD_BASE(86, 86, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(87, 87, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(88, 88, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(90, 90, 2, 0x0160, 0x10, 27, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0160, 0x10, 27, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0160, 0x10, 18, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0160, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0160, 0x10, 18, 1),
PIN_FIELD_BASE(95, 95, 2, 0x0160, 0x10, 18, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0160, 0x10, 22, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0160, 0x10, 23, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0160, 0x10, 24, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0160, 0x10, 22, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0160, 0x10, 16, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0160, 0x10, 23, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0160, 0x10, 23, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0160, 0x10, 23, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0160, 0x10, 24, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0160, 0x10, 24, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0160, 0x10, 24, 1),
PIN_FIELD_BASE(107, 107, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(108, 108, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(109, 109, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(110, 110, 2, 0x0160, 0x10, 17, 1),
PIN_FIELD_BASE(111, 111, 2, 0x0160, 0x10, 19, 1),
PIN_FIELD_BASE(112, 112, 2, 0x0160, 0x10, 19, 1),
PIN_FIELD_BASE(113, 113, 2, 0x0160, 0x10, 19, 1),
PIN_FIELD_BASE(114, 114, 2, 0x0160, 0x10, 19, 1),
PIN_FIELD_BASE(115, 115, 2, 0x0160, 0x10, 20, 1),
PIN_FIELD_BASE(116, 116, 2, 0x0160, 0x10, 20, 1),
PIN_FIELD_BASE(117, 117, 2, 0x0160, 0x10, 20, 1),
PIN_FIELD_BASE(118, 118, 2, 0x0160, 0x10, 20, 1),
PIN_FIELD_BASE(119, 119, 2, 0x0160, 0x10, 21, 1),
PIN_FIELD_BASE(120, 120, 2, 0x0160, 0x10, 21, 1),
PIN_FIELD_BASE(121, 121, 3, 0x00d0, 0x10, 6, 1),
PIN_FIELD_BASE(122, 122, 3, 0x00d0, 0x10, 9, 1),
PIN_FIELD_BASE(123, 123, 3, 0x00d0, 0x10, 8, 1),
PIN_FIELD_BASE(124, 124, 3, 0x00d0, 0x10, 7, 1),
PIN_FIELD_BASE(125, 125, 2, 0x0160, 0x10, 25, 1),
PIN_FIELD_BASE(126, 126, 2, 0x0160, 0x10, 25, 1),
PIN_FIELD_BASE(127, 127, 2, 0x0160, 0x10, 25, 1),
PIN_FIELD_BASE(128, 128, 2, 0x0160, 0x10, 25, 1),
PIN_FIELD_BASE(129, 129, 2, 0x0160, 0x10, 26, 1),
PIN_FIELD_BASE(130, 130, 2, 0x0160, 0x10, 26, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0170, 0x10, 0, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0170, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0170, 0x10, 6, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0170, 0x10, 7, 1),
PIN_FIELD_BASE(135, 135, 1, 0x0170, 0x10, 22, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0170, 0x10, 22, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0170, 0x10, 22, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0170, 0x10, 22, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0170, 0x10, 23, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0170, 0x10, 23, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0170, 0x10, 23, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0170, 0x10, 23, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0170, 0x10, 2, 1),
PIN_FIELD_BASE(144, 144, 1, 0x0170, 0x10, 3, 1),
PIN_FIELD_BASE(145, 145, 1, 0x0170, 0x10, 4, 1),
PIN_FIELD_BASE(146, 146, 1, 0x0170, 0x10, 5, 1),
PIN_FIELD_BASE(147, 147, 1, 0x0170, 0x10, 24, 1),
PIN_FIELD_BASE(148, 148, 1, 0x0170, 0x10, 24, 1),
PIN_FIELD_BASE(149, 149, 1, 0x0170, 0x10, 24, 1),
PIN_FIELD_BASE(150, 150, 1, 0x0170, 0x10, 24, 1),
PIN_FIELD_BASE(151, 151, 2, 0x0160, 0x10, 9, 1),
PIN_FIELD_BASE(152, 152, 2, 0x0160, 0x10, 8, 1),
PIN_FIELD_BASE(153, 153, 2, 0x0160, 0x10, 7, 1),
PIN_FIELD_BASE(154, 154, 2, 0x0160, 0x10, 6, 1),
PIN_FIELD_BASE(155, 155, 2, 0x0160, 0x10, 11, 1),
PIN_FIELD_BASE(156, 156, 2, 0x0160, 0x10, 1, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0160, 0x10, 0, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0160, 0x10, 5, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0160, 0x10, 4, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0160, 0x10, 3, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0160, 0x10, 2, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0160, 0x10, 10, 1),
PIN_FIELD_BASE(163, 163, 4, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(164, 164, 4, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(165, 165, 4, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(166, 166, 4, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(167, 167, 4, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(168, 168, 4, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(169, 169, 3, 0x00d0, 0x10, 1, 1),
PIN_FIELD_BASE(170, 170, 3, 0x00d0, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 3, 0x00d0, 0x10, 2, 1),
PIN_FIELD_BASE(172, 172, 3, 0x00d0, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 3, 0x00d0, 0x10, 4, 1),
PIN_FIELD_BASE(174, 174, 3, 0x00d0, 0x10, 5, 1),
PIN_FIELD_BASE(175, 175, 2, 0x0160, 0x10, 28, 1),
PIN_FIELD_BASE(176, 176, 2, 0x0160, 0x10, 28, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(1, 1, 1, 0x0080, 0x10, 27, 1),
PIN_FIELD_BASE(2, 2, 1, 0x0080, 0x10, 28, 1),
PIN_FIELD_BASE(3, 3, 1, 0x0080, 0x10, 29, 1),
PIN_FIELD_BASE(4, 4, 1, 0x0080, 0x10, 30, 1),
PIN_FIELD_BASE(5, 5, 1, 0x0080, 0x10, 31, 1),
PIN_FIELD_BASE(6, 6, 1, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 1, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(9, 9, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(10, 10, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(12, 12, 2, 0x0070, 0x10, 24, 1),
PIN_FIELD_BASE(13, 13, 2, 0x0070, 0x10, 25, 1),
PIN_FIELD_BASE(14, 14, 2, 0x0070, 0x10, 26, 1),
PIN_FIELD_BASE(15, 15, 2, 0x0070, 0x10, 27, 1),
PIN_FIELD_BASE(16, 16, 3, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 3, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(18, 18, 4, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(19, 19, 4, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(20, 20, 4, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 4, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 4, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 4, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 1, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(26, 26, 1, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 1, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(28, 28, 1, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(29, 29, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 1, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 1, 0x0090, 0x10, 31, 1),
PIN_FIELD_BASE(32, 32, 1, 0x0090, 0x10, 30, 1),
PIN_FIELD_BASE(33, 33, 1, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(34, 34, 1, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(35, 35, 1, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(36, 36, 1, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(39, 39, 1, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(42, 42, 2, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(44, 44, 2, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(45, 45, 2, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(47, 47, 1, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(48, 48, 1, 0x0090, 0x10, 12, 1),
PIN_FIELD_BASE(49, 49, 1, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(57, 57, 2, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(58, 58, 2, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(59, 59, 1, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(60, 60, 1, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(61, 61, 1, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(62, 62, 1, 0x0090, 0x10, 19, 1),
PIN_FIELD_BASE(63, 63, 2, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(64, 64, 2, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(65, 65, 4, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(66, 66, 4, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(67, 67, 4, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(68, 68, 4, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 25, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 24, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 23, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 27, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 26, 1),
PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 29, 1),
PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 28, 1),
PIN_FIELD_BASE(79, 79, 4, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(80, 80, 4, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(81, 81, 4, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(82, 82, 4, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(83, 83, 2, 0x0080, 0x10, 30, 1),
PIN_FIELD_BASE(84, 84, 2, 0x0080, 0x10, 29, 1),
PIN_FIELD_BASE(85, 85, 2, 0x0080, 0x10, 31, 1),
PIN_FIELD_BASE(86, 86, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(87, 87, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(88, 88, 2, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(95, 95, 2, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(107, 107, 2, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(108, 108, 2, 0x0070, 0x10, 28, 1),
PIN_FIELD_BASE(109, 109, 2, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(110, 110, 2, 0x0070, 0x10, 29, 1),
PIN_FIELD_BASE(111, 111, 2, 0x0070, 0x10, 30, 1),
PIN_FIELD_BASE(112, 112, 2, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(113, 113, 2, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(114, 114, 2, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(115, 115, 2, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(116, 116, 2, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 2, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(118, 118, 2, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(119, 119, 2, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 2, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(121, 121, 3, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(122, 122, 3, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(123, 123, 3, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(124, 124, 3, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(125, 125, 2, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(126, 126, 2, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(127, 127, 2, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 2, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(129, 129, 2, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(130, 130, 2, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(135, 135, 1, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(144, 144, 1, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(145, 145, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(146, 146, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(147, 147, 1, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(148, 148, 1, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(149, 149, 1, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(150, 150, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(151, 151, 2, 0x0070, 0x10, 21, 1),
PIN_FIELD_BASE(152, 152, 2, 0x0070, 0x10, 20, 1),
PIN_FIELD_BASE(153, 153, 2, 0x0070, 0x10, 19, 1),
PIN_FIELD_BASE(154, 154, 2, 0x0070, 0x10, 18, 1),
PIN_FIELD_BASE(155, 155, 2, 0x0070, 0x10, 23, 1),
PIN_FIELD_BASE(156, 156, 2, 0x0070, 0x10, 13, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0070, 0x10, 12, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0070, 0x10, 17, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0070, 0x10, 16, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0070, 0x10, 15, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0070, 0x10, 14, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0070, 0x10, 22, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(169, 169, 3, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(170, 170, 3, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(171, 171, 3, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(172, 172, 3, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(173, 173, 3, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(174, 174, 3, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(175, 175, 2, 0x0080, 0x10, 27, 1),
PIN_FIELD_BASE(176, 176, 2, 0x0080, 0x10, 28, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_tdsel_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x01b0, 0x10, 0, 4),
PIN_FIELD_BASE(1, 1, 1, 0x01b0, 0x10, 4, 4),
PIN_FIELD_BASE(2, 2, 1, 0x01b0, 0x10, 8, 4),
PIN_FIELD_BASE(3, 3, 1, 0x01b0, 0x10, 12, 4),
PIN_FIELD_BASE(4, 4, 1, 0x01c0, 0x10, 16, 4),
PIN_FIELD_BASE(5, 5, 1, 0x01c0, 0x10, 20, 4),
PIN_FIELD_BASE(6, 6, 1, 0x01c0, 0x10, 20, 4),
PIN_FIELD_BASE(7, 7, 1, 0x01b0, 0x10, 16, 4),
PIN_FIELD_BASE(8, 8, 1, 0x01b0, 0x10, 20, 4),
PIN_FIELD_BASE(9, 9, 1, 0x01b0, 0x10, 24, 4),
PIN_FIELD_BASE(10, 10, 1, 0x01b0, 0x10, 28, 4),
PIN_FIELD_BASE(11, 11, 1, 0x01c0, 0x10, 20, 4),
PIN_FIELD_BASE(12, 12, 2, 0x0190, 0x10, 16, 4),
PIN_FIELD_BASE(13, 13, 2, 0x0190, 0x10, 20, 4),
PIN_FIELD_BASE(14, 14, 2, 0x0190, 0x10, 24, 4),
PIN_FIELD_BASE(15, 15, 2, 0x0190, 0x10, 28, 4),
PIN_FIELD_BASE(16, 16, 3, 0x0100, 0x10, 8, 4),
PIN_FIELD_BASE(17, 17, 3, 0x0100, 0x10, 8, 4),
PIN_FIELD_BASE(18, 18, 4, 0x0110, 0x10, 4, 4),
PIN_FIELD_BASE(19, 19, 4, 0x0110, 0x10, 8, 4),
PIN_FIELD_BASE(20, 20, 4, 0x0110, 0x10, 8, 4),
PIN_FIELD_BASE(21, 21, 4, 0x0110, 0x10, 8, 4),
PIN_FIELD_BASE(22, 22, 4, 0x0100, 0x10, 0, 4),
PIN_FIELD_BASE(23, 23, 4, 0x0100, 0x10, 4, 4),
PIN_FIELD_BASE(24, 24, 4, 0x0100, 0x10, 8, 4),
PIN_FIELD_BASE(25, 25, 1, 0x01c0, 0x10, 8, 4),
PIN_FIELD_BASE(26, 26, 1, 0x01c0, 0x10, 8, 4),
PIN_FIELD_BASE(27, 27, 1, 0x01c0, 0x10, 8, 4),
PIN_FIELD_BASE(28, 28, 1, 0x01c0, 0x10, 12, 4),
PIN_FIELD_BASE(29, 29, 1, 0x01c0, 0x10, 0, 4),
PIN_FIELD_BASE(30, 30, 1, 0x01c0, 0x10, 8, 4),
PIN_FIELD_BASE(31, 31, 1, 0x01c0, 0x10, 20, 4),
PIN_FIELD_BASE(32, 32, 1, 0x01c0, 0x10, 24, 4),
PIN_FIELD_BASE(33, 33, 1, 0x01c0, 0x10, 24, 4),
PIN_FIELD_BASE(34, 34, 1, 0x01c0, 0x10, 28, 4),
PIN_FIELD_BASE(35, 35, 1, 0x01c0, 0x10, 24, 4),
PIN_FIELD_BASE(36, 36, 1, 0x01c0, 0x10, 24, 4),
PIN_FIELD_BASE(37, 37, 1, 0x01c0, 0x10, 28, 4),
PIN_FIELD_BASE(38, 38, 1, 0x01c0, 0x10, 28, 4),
PIN_FIELD_BASE(39, 39, 1, 0x01c0, 0x10, 28, 4),
PIN_FIELD_BASE(40, 40, 1, 0x01d0, 0x10, 0, 4),
PIN_FIELD_BASE(41, 41, 1, 0x01d0, 0x10, 0, 4),
PIN_FIELD_BASE(42, 42, 2, 0x01a0, 0x10, 16, 4),
PIN_FIELD_BASE(43, 43, 2, 0x01a0, 0x10, 20, 4),
PIN_FIELD_BASE(44, 44, 2, 0x01a0, 0x10, 16, 4),
PIN_FIELD_BASE(45, 45, 2, 0x01a0, 0x10, 20, 4),
PIN_FIELD_BASE(46, 46, 3, 0x0100, 0x10, 8, 4),
PIN_FIELD_BASE(47, 47, 1, 0x01c0, 0x10, 0, 4),
PIN_FIELD_BASE(48, 48, 1, 0x01c0, 0x10, 0, 4),
PIN_FIELD_BASE(49, 49, 1, 0x01c0, 0x10, 0, 4),
PIN_FIELD_BASE(50, 50, 3, 0x0100, 0x10, 8, 4),
PIN_FIELD_BASE(51, 51, 3, 0x0100, 0x10, 12, 4),
PIN_FIELD_BASE(52, 52, 3, 0x0100, 0x10, 12, 4),
PIN_FIELD_BASE(53, 53, 3, 0x0100, 0x10, 12, 4),
PIN_FIELD_BASE(54, 54, 3, 0x0100, 0x10, 12, 4),
PIN_FIELD_BASE(55, 55, 1, 0x01c0, 0x10, 12, 4),
PIN_FIELD_BASE(56, 56, 1, 0x01c0, 0x10, 12, 4),
PIN_FIELD_BASE(57, 57, 2, 0x01a0, 0x10, 24, 4),
PIN_FIELD_BASE(58, 58, 2, 0x01a0, 0x10, 24, 4),
PIN_FIELD_BASE(59, 59, 1, 0x01c0, 0x10, 16, 4),
PIN_FIELD_BASE(60, 60, 1, 0x01c0, 0x10, 12, 4),
PIN_FIELD_BASE(61, 61, 1, 0x01c0, 0x10, 16, 4),
PIN_FIELD_BASE(62, 62, 1, 0x01c0, 0x10, 16, 4),
PIN_FIELD_BASE(63, 63, 2, 0x01a0, 0x10, 20, 4),
PIN_FIELD_BASE(64, 64, 2, 0x01a0, 0x10, 20, 4),
PIN_FIELD_BASE(65, 65, 4, 0x0110, 0x10, 12, 4),
PIN_FIELD_BASE(66, 66, 4, 0x0110, 0x10, 8, 4),
PIN_FIELD_BASE(67, 67, 4, 0x0110, 0x10, 12, 4),
PIN_FIELD_BASE(68, 68, 4, 0x0110, 0x10, 12, 4),
PIN_FIELD_BASE(69, 69, 1, 0x01d0, 0x10, 16, 4),
PIN_FIELD_BASE(70, 70, 1, 0x01d0, 0x10, 12, 4),
PIN_FIELD_BASE(71, 71, 1, 0x01e0, 0x10, 0, 4),
PIN_FIELD_BASE(72, 72, 1, 0x01d0, 0x10, 28, 4),
PIN_FIELD_BASE(73, 73, 1, 0x01d0, 0x10, 20, 4),
PIN_FIELD_BASE(74, 74, 1, 0x01d0, 0x10, 24, 4),
PIN_FIELD_BASE(75, 75, 1, 0x01e0, 0x10, 8, 4),
PIN_FIELD_BASE(76, 76, 1, 0x01e0, 0x10, 4, 4),
PIN_FIELD_BASE(77, 77, 1, 0x01e0, 0x10, 16, 4),
PIN_FIELD_BASE(78, 78, 1, 0x01e0, 0x10, 12, 4),
PIN_FIELD_BASE(79, 79, 4, 0x0110, 0x10, 20, 4),
PIN_FIELD_BASE(80, 80, 4, 0x0110, 0x10, 16, 4),
PIN_FIELD_BASE(81, 81, 4, 0x0110, 0x10, 28, 4),
PIN_FIELD_BASE(82, 82, 4, 0x0110, 0x10, 24, 4),
PIN_FIELD_BASE(83, 83, 2, 0x01b0, 0x10, 8, 4),
PIN_FIELD_BASE(84, 84, 2, 0x01b0, 0x10, 8, 4),
PIN_FIELD_BASE(85, 85, 2, 0x01b0, 0x10, 12, 4),
PIN_FIELD_BASE(86, 86, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(87, 87, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(88, 88, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(89, 89, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(90, 90, 2, 0x01b0, 0x10, 12, 4),
PIN_FIELD_BASE(91, 91, 2, 0x01b0, 0x10, 12, 4),
PIN_FIELD_BASE(92, 92, 2, 0x01a0, 0x10, 4, 4),
PIN_FIELD_BASE(93, 93, 2, 0x01a0, 0x10, 4, 4),
PIN_FIELD_BASE(94, 94, 2, 0x01a0, 0x10, 4, 4),
PIN_FIELD_BASE(95, 95, 2, 0x01a0, 0x10, 4, 4),
PIN_FIELD_BASE(96, 96, 2, 0x01a0, 0x10, 24, 4),
PIN_FIELD_BASE(97, 97, 2, 0x01a0, 0x10, 28, 4),
PIN_FIELD_BASE(98, 98, 2, 0x01b0, 0x10, 0, 4),
PIN_FIELD_BASE(99, 99, 2, 0x01a0, 0x10, 24, 4),
PIN_FIELD_BASE(100, 100, 2, 0x01b0, 0x10, 20, 4),
PIN_FIELD_BASE(101, 101, 2, 0x01a0, 0x10, 28, 4),
PIN_FIELD_BASE(102, 102, 2, 0x01a0, 0x10, 28, 4),
PIN_FIELD_BASE(103, 103, 2, 0x01a0, 0x10, 28, 4),
PIN_FIELD_BASE(104, 104, 2, 0x01b0, 0x10, 0, 4),
PIN_FIELD_BASE(105, 105, 2, 0x01b0, 0x10, 0, 4),
PIN_FIELD_BASE(106, 106, 2, 0x01b0, 0x10, 0, 4),
PIN_FIELD_BASE(107, 107, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(108, 108, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(109, 109, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(110, 110, 2, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(111, 111, 2, 0x01a0, 0x10, 8, 4),
PIN_FIELD_BASE(112, 112, 2, 0x01a0, 0x10, 8, 4),
PIN_FIELD_BASE(113, 113, 2, 0x01a0, 0x10, 8, 4),
PIN_FIELD_BASE(114, 114, 2, 0x01a0, 0x10, 8, 4),
PIN_FIELD_BASE(115, 115, 2, 0x01a0, 0x10, 12, 4),
PIN_FIELD_BASE(116, 116, 2, 0x01a0, 0x10, 12, 4),
PIN_FIELD_BASE(117, 117, 2, 0x01a0, 0x10, 12, 4),
PIN_FIELD_BASE(118, 118, 2, 0x01a0, 0x10, 12, 4),
PIN_FIELD_BASE(119, 119, 2, 0x01a0, 0x10, 16, 4),
PIN_FIELD_BASE(120, 120, 2, 0x01a0, 0x10, 16, 4),
PIN_FIELD_BASE(121, 121, 3, 0x00f0, 0x10, 24, 4),
PIN_FIELD_BASE(122, 122, 3, 0x0100, 0x10, 4, 4),
PIN_FIELD_BASE(123, 123, 3, 0x0100, 0x10, 0, 4),
PIN_FIELD_BASE(124, 124, 3, 0x00f0, 0x10, 28, 4),
PIN_FIELD_BASE(125, 125, 2, 0x01b0, 0x10, 4, 4),
PIN_FIELD_BASE(126, 126, 2, 0x01b0, 0x10, 4, 4),
PIN_FIELD_BASE(127, 127, 2, 0x01b0, 0x10, 4, 4),
PIN_FIELD_BASE(128, 128, 2, 0x01b0, 0x10, 4, 4),
PIN_FIELD_BASE(129, 129, 2, 0x01b0, 0x10, 8, 4),
PIN_FIELD_BASE(130, 130, 2, 0x01b0, 0x10, 8, 4),
PIN_FIELD_BASE(131, 131, 1, 0x01a0, 0x10, 0, 4),
PIN_FIELD_BASE(132, 132, 1, 0x01a0, 0x10, 20, 4),
PIN_FIELD_BASE(133, 133, 1, 0x01a0, 0x10, 24, 4),
PIN_FIELD_BASE(134, 134, 1, 0x01a0, 0x10, 28, 4),
PIN_FIELD_BASE(135, 135, 1, 0x01d0, 0x10, 0, 4),
PIN_FIELD_BASE(136, 136, 1, 0x01d0, 0x10, 0, 4),
PIN_FIELD_BASE(137, 137, 1, 0x01d0, 0x10, 4, 4),
PIN_FIELD_BASE(138, 138, 1, 0x01d0, 0x10, 4, 4),
PIN_FIELD_BASE(139, 139, 1, 0x01d0, 0x10, 4, 4),
PIN_FIELD_BASE(140, 140, 1, 0x01d0, 0x10, 4, 4),
PIN_FIELD_BASE(141, 141, 1, 0x01d0, 0x10, 8, 4),
PIN_FIELD_BASE(142, 142, 1, 0x01d0, 0x10, 8, 4),
PIN_FIELD_BASE(143, 143, 1, 0x01a0, 0x10, 4, 4),
PIN_FIELD_BASE(144, 144, 1, 0x01a0, 0x10, 8, 4),
PIN_FIELD_BASE(145, 145, 1, 0x01a0, 0x10, 12, 4),
PIN_FIELD_BASE(146, 146, 1, 0x01a0, 0x10, 16, 4),
PIN_FIELD_BASE(147, 147, 1, 0x01d0, 0x10, 8, 4),
PIN_FIELD_BASE(148, 148, 1, 0x01d0, 0x10, 8, 4),
PIN_FIELD_BASE(149, 149, 1, 0x01c0, 0x10, 4, 4),
PIN_FIELD_BASE(150, 150, 1, 0x01c0, 0x10, 4, 4),
PIN_FIELD_BASE(151, 151, 2, 0x0190, 0x10, 4, 4),
PIN_FIELD_BASE(152, 152, 2, 0x0190, 0x10, 0, 4),
PIN_FIELD_BASE(153, 153, 2, 0x0180, 0x10, 28, 4),
PIN_FIELD_BASE(154, 154, 2, 0x0180, 0x10, 24, 4),
PIN_FIELD_BASE(155, 155, 2, 0x0190, 0x10, 12, 4),
PIN_FIELD_BASE(156, 156, 2, 0x0180, 0x10, 4, 4),
PIN_FIELD_BASE(157, 157, 2, 0x0180, 0x10, 0, 4),
PIN_FIELD_BASE(158, 158, 2, 0x0180, 0x10, 20, 4),
PIN_FIELD_BASE(159, 159, 2, 0x0180, 0x10, 16, 4),
PIN_FIELD_BASE(160, 160, 2, 0x0180, 0x10, 12, 4),
PIN_FIELD_BASE(161, 161, 2, 0x0180, 0x10, 8, 4),
PIN_FIELD_BASE(162, 162, 2, 0x0190, 0x10, 8, 4),
PIN_FIELD_BASE(163, 163, 4, 0x0100, 0x10, 16, 4),
PIN_FIELD_BASE(164, 164, 4, 0x0100, 0x10, 12, 4),
PIN_FIELD_BASE(165, 165, 4, 0x0100, 0x10, 20, 4),
PIN_FIELD_BASE(166, 166, 4, 0x0100, 0x10, 24, 4),
PIN_FIELD_BASE(167, 167, 4, 0x0100, 0x10, 28, 4),
PIN_FIELD_BASE(168, 168, 4, 0x0110, 0x10, 0, 4),
PIN_FIELD_BASE(169, 169, 3, 0x00f0, 0x10, 4, 4),
PIN_FIELD_BASE(170, 170, 3, 0x00f0, 0x10, 0, 4),
PIN_FIELD_BASE(171, 171, 3, 0x00f0, 0x10, 8, 4),
PIN_FIELD_BASE(172, 172, 3, 0x00f0, 0x10, 12, 4),
PIN_FIELD_BASE(173, 173, 3, 0x00f0, 0x10, 16, 4),
PIN_FIELD_BASE(174, 174, 3, 0x00f0, 0x10, 20, 4),
PIN_FIELD_BASE(175, 175, 2, 0x01b0, 0x10, 16, 4),
PIN_FIELD_BASE(176, 176, 2, 0x01b0, 0x10, 16, 4),
};
static const struct mtk_pin_field_calc mt8188_pin_rdsel_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x0130, 0x10, 18, 2),
PIN_FIELD_BASE(1, 1, 1, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(2, 2, 1, 0x0130, 0x10, 22, 2),
PIN_FIELD_BASE(3, 3, 1, 0x0130, 0x10, 24, 2),
PIN_FIELD_BASE(4, 4, 1, 0x0140, 0x10, 14, 2),
PIN_FIELD_BASE(5, 5, 1, 0x0140, 0x10, 16, 2),
PIN_FIELD_BASE(6, 6, 1, 0x0140, 0x10, 16, 2),
PIN_FIELD_BASE(7, 7, 1, 0x0130, 0x10, 26, 2),
PIN_FIELD_BASE(8, 8, 1, 0x0130, 0x10, 28, 2),
PIN_FIELD_BASE(9, 9, 1, 0x0130, 0x10, 30, 2),
PIN_FIELD_BASE(10, 10, 1, 0x0140, 0x10, 0, 2),
PIN_FIELD_BASE(11, 11, 1, 0x0140, 0x10, 16, 2),
PIN_FIELD_BASE(12, 12, 2, 0x0130, 0x10, 12, 2),
PIN_FIELD_BASE(13, 13, 2, 0x0130, 0x10, 14, 2),
PIN_FIELD_BASE(14, 14, 2, 0x0130, 0x10, 16, 2),
PIN_FIELD_BASE(15, 15, 2, 0x0130, 0x10, 18, 2),
PIN_FIELD_BASE(16, 16, 3, 0x00b0, 0x10, 14, 2),
PIN_FIELD_BASE(17, 17, 3, 0x00b0, 0x10, 14, 2),
PIN_FIELD_BASE(18, 18, 4, 0x00c0, 0x10, 12, 2),
PIN_FIELD_BASE(19, 19, 4, 0x00c0, 0x10, 12, 2),
PIN_FIELD_BASE(20, 20, 4, 0x00c0, 0x10, 12, 2),
PIN_FIELD_BASE(21, 21, 4, 0x00c0, 0x10, 12, 2),
PIN_FIELD_BASE(22, 22, 4, 0x00b0, 0x10, 0, 2),
PIN_FIELD_BASE(23, 23, 4, 0x00b0, 0x10, 2, 2),
PIN_FIELD_BASE(24, 24, 4, 0x00b0, 0x10, 4, 2),
PIN_FIELD_BASE(25, 25, 1, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(26, 26, 1, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(27, 27, 1, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(28, 28, 1, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(29, 29, 1, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(30, 30, 1, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(31, 31, 1, 0x0140, 0x10, 16, 2),
PIN_FIELD_BASE(32, 32, 1, 0x0140, 0x10, 18, 2),
PIN_FIELD_BASE(33, 33, 1, 0x0140, 0x10, 18, 2),
PIN_FIELD_BASE(34, 34, 1, 0x0140, 0x10, 20, 2),
PIN_FIELD_BASE(35, 35, 1, 0x0140, 0x10, 18, 2),
PIN_FIELD_BASE(36, 36, 1, 0x0140, 0x10, 18, 2),
PIN_FIELD_BASE(37, 37, 1, 0x0140, 0x10, 20, 2),
PIN_FIELD_BASE(38, 38, 1, 0x0140, 0x10, 20, 2),
PIN_FIELD_BASE(39, 39, 1, 0x0140, 0x10, 20, 2),
PIN_FIELD_BASE(40, 40, 1, 0x0140, 0x10, 22, 2),
PIN_FIELD_BASE(41, 41, 1, 0x0140, 0x10, 22, 2),
PIN_FIELD_BASE(42, 42, 2, 0x0130, 0x10, 30, 2),
PIN_FIELD_BASE(43, 43, 2, 0x0140, 0x10, 0, 2),
PIN_FIELD_BASE(44, 44, 2, 0x0130, 0x10, 30, 2),
PIN_FIELD_BASE(45, 45, 2, 0x0140, 0x10, 0, 2),
PIN_FIELD_BASE(46, 46, 3, 0x00b0, 0x10, 14, 2),
PIN_FIELD_BASE(47, 47, 1, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(48, 48, 1, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(49, 49, 1, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(50, 50, 3, 0x00b0, 0x10, 14, 2),
PIN_FIELD_BASE(51, 51, 3, 0x00b0, 0x10, 16, 2),
PIN_FIELD_BASE(52, 52, 3, 0x00b0, 0x10, 16, 2),
PIN_FIELD_BASE(53, 53, 3, 0x00b0, 0x10, 16, 2),
PIN_FIELD_BASE(54, 54, 3, 0x00b0, 0x10, 16, 2),
PIN_FIELD_BASE(55, 55, 1, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(56, 56, 1, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(57, 57, 2, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(58, 58, 2, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(59, 59, 1, 0x0140, 0x10, 14, 2),
PIN_FIELD_BASE(60, 60, 1, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(61, 61, 1, 0x0140, 0x10, 14, 2),
PIN_FIELD_BASE(62, 62, 1, 0x0140, 0x10, 14, 2),
PIN_FIELD_BASE(63, 63, 2, 0x0140, 0x10, 0, 2),
PIN_FIELD_BASE(64, 64, 2, 0x0140, 0x10, 0, 2),
PIN_FIELD_BASE(65, 65, 4, 0x00c0, 0x10, 14, 2),
PIN_FIELD_BASE(66, 66, 4, 0x00c0, 0x10, 14, 2),
PIN_FIELD_BASE(67, 67, 4, 0x00c0, 0x10, 14, 2),
PIN_FIELD_BASE(68, 68, 4, 0x00c0, 0x10, 14, 2),
PIN_FIELD_BASE(69, 69, 1, 0x0150, 0x10, 14, 2),
PIN_FIELD_BASE(70, 70, 1, 0x0150, 0x10, 12, 2),
PIN_FIELD_BASE(71, 71, 1, 0x0150, 0x10, 22, 2),
PIN_FIELD_BASE(72, 72, 1, 0x0150, 0x10, 20, 2),
PIN_FIELD_BASE(73, 73, 1, 0x0150, 0x10, 16, 2),
PIN_FIELD_BASE(74, 74, 1, 0x0150, 0x10, 18, 2),
PIN_FIELD_BASE(75, 75, 1, 0x0150, 0x10, 26, 2),
PIN_FIELD_BASE(76, 76, 1, 0x0150, 0x10, 24, 2),
PIN_FIELD_BASE(77, 77, 1, 0x0150, 0x10, 30, 2),
PIN_FIELD_BASE(78, 78, 1, 0x0150, 0x10, 28, 2),
PIN_FIELD_BASE(79, 79, 4, 0x00c0, 0x10, 18, 2),
PIN_FIELD_BASE(80, 80, 4, 0x00c0, 0x10, 16, 2),
PIN_FIELD_BASE(81, 81, 4, 0x00c0, 0x10, 22, 2),
PIN_FIELD_BASE(82, 82, 4, 0x00c0, 0x10, 20, 2),
PIN_FIELD_BASE(83, 83, 2, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(84, 84, 2, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(85, 85, 2, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(86, 86, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(87, 87, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(88, 88, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(89, 89, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(90, 90, 2, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(91, 91, 2, 0x0140, 0x10, 12, 2),
PIN_FIELD_BASE(92, 92, 2, 0x0130, 0x10, 22, 2),
PIN_FIELD_BASE(93, 93, 2, 0x0130, 0x10, 22, 2),
PIN_FIELD_BASE(94, 94, 2, 0x0130, 0x10, 22, 2),
PIN_FIELD_BASE(95, 95, 2, 0x0130, 0x10, 22, 2),
PIN_FIELD_BASE(96, 96, 2, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(97, 97, 2, 0x0140, 0x10, 4, 2),
PIN_FIELD_BASE(98, 98, 2, 0x0140, 0x10, 6, 2),
PIN_FIELD_BASE(99, 99, 2, 0x0140, 0x10, 2, 2),
PIN_FIELD_BASE(100, 100, 2, 0x0140, 0x10, 16, 2),
PIN_FIELD_BASE(101, 101, 2, 0x0140, 0x10, 4, 2),
PIN_FIELD_BASE(102, 102, 2, 0x0140, 0x10, 4, 2),
PIN_FIELD_BASE(103, 103, 2, 0x0140, 0x10, 4, 2),
PIN_FIELD_BASE(104, 104, 2, 0x0140, 0x10, 6, 2),
PIN_FIELD_BASE(105, 105, 2, 0x0140, 0x10, 6, 2),
PIN_FIELD_BASE(106, 106, 2, 0x0140, 0x10, 6, 2),
PIN_FIELD_BASE(107, 107, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(108, 108, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(109, 109, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(110, 110, 2, 0x0130, 0x10, 20, 2),
PIN_FIELD_BASE(111, 111, 2, 0x0130, 0x10, 24, 2),
PIN_FIELD_BASE(112, 112, 2, 0x0130, 0x10, 24, 2),
PIN_FIELD_BASE(113, 113, 2, 0x0130, 0x10, 24, 2),
PIN_FIELD_BASE(114, 114, 2, 0x0130, 0x10, 24, 2),
PIN_FIELD_BASE(115, 115, 2, 0x0130, 0x10, 28, 2),
PIN_FIELD_BASE(116, 116, 2, 0x0130, 0x10, 28, 2),
PIN_FIELD_BASE(117, 117, 2, 0x0130, 0x10, 28, 2),
PIN_FIELD_BASE(118, 118, 2, 0x0130, 0x10, 28, 2),
PIN_FIELD_BASE(119, 119, 2, 0x0130, 0x10, 30, 2),
PIN_FIELD_BASE(120, 120, 2, 0x0130, 0x10, 30, 2),
PIN_FIELD_BASE(121, 121, 3, 0x00b0, 0x10, 6, 2),
PIN_FIELD_BASE(122, 122, 3, 0x00b0, 0x10, 12, 2),
PIN_FIELD_BASE(123, 123, 3, 0x00b0, 0x10, 10, 2),
PIN_FIELD_BASE(124, 124, 3, 0x00b0, 0x10, 8, 2),
PIN_FIELD_BASE(125, 125, 2, 0x0140, 0x10, 8, 2),
PIN_FIELD_BASE(126, 126, 2, 0x0140, 0x10, 8, 2),
PIN_FIELD_BASE(127, 127, 2, 0x0140, 0x10, 8, 2),
PIN_FIELD_BASE(128, 128, 2, 0x0140, 0x10, 8, 2),
PIN_FIELD_BASE(129, 129, 2, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(130, 130, 2, 0x0140, 0x10, 10, 2),
PIN_FIELD_BASE(131, 131, 1, 0x0120, 0x10, 0, 6),
PIN_FIELD_BASE(132, 132, 1, 0x0130, 0x10, 0, 6),
PIN_FIELD_BASE(133, 133, 1, 0x0130, 0x10, 6, 6),
PIN_FIELD_BASE(134, 134, 1, 0x0130, 0x10, 12, 6),
PIN_FIELD_BASE(135, 135, 1, 0x0140, 0x10, 24, 6),
PIN_FIELD_BASE(136, 136, 1, 0x0140, 0x10, 24, 6),
PIN_FIELD_BASE(137, 137, 1, 0x0150, 0x10, 0, 6),
PIN_FIELD_BASE(138, 138, 1, 0x0150, 0x10, 0, 6),
PIN_FIELD_BASE(139, 139, 1, 0x0150, 0x10, 0, 6),
PIN_FIELD_BASE(140, 140, 1, 0x0150, 0x10, 0, 6),
PIN_FIELD_BASE(141, 141, 1, 0x0150, 0x10, 6, 6),
PIN_FIELD_BASE(142, 142, 1, 0x0150, 0x10, 6, 6),
PIN_FIELD_BASE(143, 143, 1, 0x0120, 0x10, 6, 6),
PIN_FIELD_BASE(144, 144, 1, 0x0120, 0x10, 12, 6),
PIN_FIELD_BASE(145, 145, 1, 0x0120, 0x10, 18, 6),
PIN_FIELD_BASE(146, 146, 1, 0x0120, 0x10, 24, 6),
PIN_FIELD_BASE(147, 147, 1, 0x0150, 0x10, 6, 6),
PIN_FIELD_BASE(148, 148, 1, 0x0150, 0x10, 6, 6),
PIN_FIELD_BASE(149, 149, 1, 0x0140, 0x10, 4, 6),
PIN_FIELD_BASE(150, 150, 1, 0x0140, 0x10, 4, 6),
PIN_FIELD_BASE(151, 151, 2, 0x0120, 0x10, 24, 6),
PIN_FIELD_BASE(152, 152, 2, 0x0120, 0x10, 18, 6),
PIN_FIELD_BASE(153, 153, 2, 0x0120, 0x10, 12, 6),
PIN_FIELD_BASE(154, 154, 2, 0x0120, 0x10, 6, 6),
PIN_FIELD_BASE(155, 155, 2, 0x0130, 0x10, 6, 6),
PIN_FIELD_BASE(156, 156, 2, 0x0110, 0x10, 6, 6),
PIN_FIELD_BASE(157, 157, 2, 0x0110, 0x10, 0, 6),
PIN_FIELD_BASE(158, 158, 2, 0x0120, 0x10, 0, 6),
PIN_FIELD_BASE(159, 159, 2, 0x0110, 0x10, 24, 6),
PIN_FIELD_BASE(160, 160, 2, 0x0110, 0x10, 18, 6),
PIN_FIELD_BASE(161, 161, 2, 0x0110, 0x10, 12, 6),
PIN_FIELD_BASE(162, 162, 2, 0x0130, 0x10, 0, 6),
PIN_FIELD_BASE(163, 163, 4, 0x00b0, 0x10, 12, 6),
PIN_FIELD_BASE(164, 164, 4, 0x00b0, 0x10, 6, 6),
PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 18, 6),
PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 24, 6),
PIN_FIELD_BASE(167, 167, 4, 0x00c0, 0x10, 0, 6),
PIN_FIELD_BASE(168, 168, 4, 0x00c0, 0x10, 6, 6),
PIN_FIELD_BASE(169, 169, 3, 0x00a0, 0x10, 6, 6),
PIN_FIELD_BASE(170, 170, 3, 0x00a0, 0x10, 0, 6),
PIN_FIELD_BASE(171, 171, 3, 0x00a0, 0x10, 12, 6),
PIN_FIELD_BASE(172, 172, 3, 0x00a0, 0x10, 18, 6),
PIN_FIELD_BASE(173, 173, 3, 0x00a0, 0x10, 24, 6),
PIN_FIELD_BASE(174, 174, 3, 0x00b0, 0x10, 0, 6),
PIN_FIELD_BASE(175, 175, 2, 0x0140, 0x10, 14, 2),
PIN_FIELD_BASE(176, 176, 2, 0x0140, 0x10, 14, 2),
};
static const struct mtk_pin_field_calc mt8188_pin_pupd_range[] = {
PIN_FIELD_BASE(42, 42, 2, 0x00c0, 0x10, 12, 1),
PIN_FIELD_BASE(43, 43, 2, 0x00c0, 0x10, 13, 1),
PIN_FIELD_BASE(44, 44, 2, 0x00c0, 0x10, 14, 1),
PIN_FIELD_BASE(45, 45, 2, 0x00c0, 0x10, 15, 1),
PIN_FIELD_BASE(131, 131, 1, 0x00d0, 0x10, 1, 1),
PIN_FIELD_BASE(132, 132, 1, 0x00d0, 0x10, 2, 1),
PIN_FIELD_BASE(133, 133, 1, 0x00d0, 0x10, 9, 1),
PIN_FIELD_BASE(134, 134, 1, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(135, 135, 1, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(136, 136, 1, 0x00d0, 0x10, 12, 1),
PIN_FIELD_BASE(137, 137, 1, 0x00d0, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x00d0, 0x10, 14, 1),
PIN_FIELD_BASE(139, 139, 1, 0x00d0, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x00d0, 0x10, 16, 1),
PIN_FIELD_BASE(141, 141, 1, 0x00d0, 0x10, 3, 1),
PIN_FIELD_BASE(142, 142, 1, 0x00d0, 0x10, 4, 1),
PIN_FIELD_BASE(143, 143, 1, 0x00d0, 0x10, 5, 1),
PIN_FIELD_BASE(144, 144, 1, 0x00d0, 0x10, 6, 1),
PIN_FIELD_BASE(145, 145, 1, 0x00d0, 0x10, 7, 1),
PIN_FIELD_BASE(146, 146, 1, 0x00d0, 0x10, 8, 1),
PIN_FIELD_BASE(147, 147, 1, 0x00d0, 0x10, 18, 1),
PIN_FIELD_BASE(148, 148, 1, 0x00d0, 0x10, 19, 1),
PIN_FIELD_BASE(149, 149, 1, 0x00d0, 0x10, 17, 1),
PIN_FIELD_BASE(150, 150, 1, 0x00d0, 0x10, 0, 1),
PIN_FIELD_BASE(151, 151, 2, 0x00c0, 0x10, 9, 1),
PIN_FIELD_BASE(152, 152, 2, 0x00c0, 0x10, 8, 1),
PIN_FIELD_BASE(153, 153, 2, 0x00c0, 0x10, 7, 1),
PIN_FIELD_BASE(154, 154, 2, 0x00c0, 0x10, 6, 1),
PIN_FIELD_BASE(155, 155, 2, 0x00c0, 0x10, 11, 1),
PIN_FIELD_BASE(156, 156, 2, 0x00c0, 0x10, 1, 1),
PIN_FIELD_BASE(157, 157, 2, 0x00c0, 0x10, 0, 1),
PIN_FIELD_BASE(158, 158, 2, 0x00c0, 0x10, 5, 1),
PIN_FIELD_BASE(159, 159, 2, 0x00c0, 0x10, 4, 1),
PIN_FIELD_BASE(160, 160, 2, 0x00c0, 0x10, 3, 1),
PIN_FIELD_BASE(161, 161, 2, 0x00c0, 0x10, 2, 1),
PIN_FIELD_BASE(162, 162, 2, 0x00c0, 0x10, 10, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 3, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(170, 170, 3, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 3, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(172, 172, 3, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 3, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(174, 174, 3, 0x0060, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_r0_range[] = {
PIN_FIELD_BASE(42, 42, 2, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(43, 43, 2, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(44, 44, 2, 0x00f0, 0x10, 14, 1),
PIN_FIELD_BASE(45, 45, 2, 0x00f0, 0x10, 15, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0100, 0x10, 1, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0100, 0x10, 2, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0100, 0x10, 9, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0100, 0x10, 10, 1),
PIN_FIELD_BASE(135, 135, 1, 0x0100, 0x10, 11, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0100, 0x10, 12, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0100, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0100, 0x10, 14, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0100, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0100, 0x10, 16, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0100, 0x10, 3, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0100, 0x10, 4, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0100, 0x10, 5, 1),
PIN_FIELD_BASE(144, 144, 1, 0x0100, 0x10, 6, 1),
PIN_FIELD_BASE(145, 145, 1, 0x0100, 0x10, 7, 1),
PIN_FIELD_BASE(146, 146, 1, 0x0100, 0x10, 8, 1),
PIN_FIELD_BASE(147, 147, 1, 0x0100, 0x10, 18, 1),
PIN_FIELD_BASE(148, 148, 1, 0x0100, 0x10, 19, 1),
PIN_FIELD_BASE(149, 149, 1, 0x0100, 0x10, 17, 1),
PIN_FIELD_BASE(150, 150, 1, 0x0100, 0x10, 0, 1),
PIN_FIELD_BASE(151, 151, 2, 0x00f0, 0x10, 9, 1),
PIN_FIELD_BASE(152, 152, 2, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(153, 153, 2, 0x00f0, 0x10, 7, 1),
PIN_FIELD_BASE(154, 154, 2, 0x00f0, 0x10, 6, 1),
PIN_FIELD_BASE(155, 155, 2, 0x00f0, 0x10, 11, 1),
PIN_FIELD_BASE(156, 156, 2, 0x00f0, 0x10, 1, 1),
PIN_FIELD_BASE(157, 157, 2, 0x00f0, 0x10, 0, 1),
PIN_FIELD_BASE(158, 158, 2, 0x00f0, 0x10, 5, 1),
PIN_FIELD_BASE(159, 159, 2, 0x00f0, 0x10, 4, 1),
PIN_FIELD_BASE(160, 160, 2, 0x00f0, 0x10, 3, 1),
PIN_FIELD_BASE(161, 161, 2, 0x00f0, 0x10, 2, 1),
PIN_FIELD_BASE(162, 162, 2, 0x00f0, 0x10, 10, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 3, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(170, 170, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 3, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(172, 172, 3, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 3, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(174, 174, 3, 0x0080, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_r1_range[] = {
PIN_FIELD_BASE(42, 42, 2, 0x0100, 0x10, 12, 1),
PIN_FIELD_BASE(43, 43, 2, 0x0100, 0x10, 13, 1),
PIN_FIELD_BASE(44, 44, 2, 0x0100, 0x10, 14, 1),
PIN_FIELD_BASE(45, 45, 2, 0x0100, 0x10, 15, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0110, 0x10, 1, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0110, 0x10, 2, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0110, 0x10, 9, 1),
PIN_FIELD_BASE(134, 134, 1, 0x0110, 0x10, 10, 1),
PIN_FIELD_BASE(135, 135, 1, 0x0110, 0x10, 11, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0110, 0x10, 12, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0110, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0110, 0x10, 14, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0110, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0110, 0x10, 16, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0110, 0x10, 3, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0110, 0x10, 4, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0110, 0x10, 5, 1),
PIN_FIELD_BASE(144, 144, 1, 0x0110, 0x10, 6, 1),
PIN_FIELD_BASE(145, 145, 1, 0x0110, 0x10, 7, 1),
PIN_FIELD_BASE(146, 146, 1, 0x0110, 0x10, 8, 1),
PIN_FIELD_BASE(147, 147, 1, 0x0110, 0x10, 18, 1),
PIN_FIELD_BASE(148, 148, 1, 0x0110, 0x10, 19, 1),
PIN_FIELD_BASE(149, 149, 1, 0x0110, 0x10, 17, 1),
PIN_FIELD_BASE(150, 150, 1, 0x0110, 0x10, 0, 1),
PIN_FIELD_BASE(151, 151, 2, 0x0100, 0x10, 9, 1),
PIN_FIELD_BASE(152, 152, 2, 0x0100, 0x10, 8, 1),
PIN_FIELD_BASE(153, 153, 2, 0x0100, 0x10, 7, 1),
PIN_FIELD_BASE(154, 154, 2, 0x0100, 0x10, 6, 1),
PIN_FIELD_BASE(155, 155, 2, 0x0100, 0x10, 11, 1),
PIN_FIELD_BASE(156, 156, 2, 0x0100, 0x10, 1, 1),
PIN_FIELD_BASE(157, 157, 2, 0x0100, 0x10, 0, 1),
PIN_FIELD_BASE(158, 158, 2, 0x0100, 0x10, 5, 1),
PIN_FIELD_BASE(159, 159, 2, 0x0100, 0x10, 4, 1),
PIN_FIELD_BASE(160, 160, 2, 0x0100, 0x10, 3, 1),
PIN_FIELD_BASE(161, 161, 2, 0x0100, 0x10, 2, 1),
PIN_FIELD_BASE(162, 162, 2, 0x0100, 0x10, 10, 1),
PIN_FIELD_BASE(163, 163, 4, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(164, 164, 4, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(165, 165, 4, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x00a0, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 3, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(170, 170, 3, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(171, 171, 3, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(172, 172, 3, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 3, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(174, 174, 3, 0x0090, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_pu_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(1, 1, 1, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(2, 2, 1, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(3, 3, 1, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(4, 4, 1, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(5, 5, 1, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(6, 6, 1, 0x00e0, 0x10, 12, 1),
PIN_FIELD_BASE(7, 7, 1, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(8, 8, 1, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(9, 9, 1, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(10, 10, 1, 0x00e0, 0x10, 16, 1),
PIN_FIELD_BASE(11, 11, 1, 0x00e0, 0x10, 17, 1),
PIN_FIELD_BASE(12, 12, 2, 0x00d0, 0x10, 12, 1),
PIN_FIELD_BASE(13, 13, 2, 0x00d0, 0x10, 13, 1),
PIN_FIELD_BASE(14, 14, 2, 0x00d0, 0x10, 14, 1),
PIN_FIELD_BASE(15, 15, 2, 0x00d0, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 3, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 3, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(18, 18, 4, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(19, 19, 4, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(20, 20, 4, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 4, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 4, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 4, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 4, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 1, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(26, 26, 1, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(27, 27, 1, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(28, 28, 1, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(29, 29, 1, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 1, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 1, 0x00f0, 0x10, 11, 1),
PIN_FIELD_BASE(32, 32, 1, 0x00f0, 0x10, 10, 1),
PIN_FIELD_BASE(33, 33, 1, 0x00f0, 0x10, 13, 1),
PIN_FIELD_BASE(34, 34, 1, 0x00f0, 0x10, 12, 1),
PIN_FIELD_BASE(35, 35, 1, 0x00f0, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x00f0, 0x10, 14, 1),
PIN_FIELD_BASE(37, 37, 1, 0x00e0, 0x10, 21, 1),
PIN_FIELD_BASE(38, 38, 1, 0x00e0, 0x10, 18, 1),
PIN_FIELD_BASE(39, 39, 1, 0x00e0, 0x10, 19, 1),
PIN_FIELD_BASE(40, 40, 1, 0x00e0, 0x10, 20, 1),
PIN_FIELD_BASE(41, 41, 1, 0x00e0, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(47, 47, 1, 0x00e0, 0x10, 25, 1),
PIN_FIELD_BASE(48, 48, 1, 0x00e0, 0x10, 24, 1),
PIN_FIELD_BASE(49, 49, 1, 0x00e0, 0x10, 23, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(55, 55, 1, 0x00e0, 0x10, 26, 1),
PIN_FIELD_BASE(56, 56, 1, 0x00e0, 0x10, 29, 1),
PIN_FIELD_BASE(57, 57, 2, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(58, 58, 2, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(59, 59, 1, 0x00e0, 0x10, 27, 1),
PIN_FIELD_BASE(60, 60, 1, 0x00e0, 0x10, 30, 1),
PIN_FIELD_BASE(61, 61, 1, 0x00e0, 0x10, 28, 1),
PIN_FIELD_BASE(62, 62, 1, 0x00e0, 0x10, 31, 1),
PIN_FIELD_BASE(63, 63, 2, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(64, 64, 2, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(65, 65, 4, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 4, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(67, 67, 4, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(68, 68, 4, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 0, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 4, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 2, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 9, 1),
PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 8, 1),
PIN_FIELD_BASE(79, 79, 4, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(80, 80, 4, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(81, 81, 4, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(82, 82, 4, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(83, 83, 2, 0x00e0, 0x10, 16, 1),
PIN_FIELD_BASE(84, 84, 2, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(85, 85, 2, 0x00e0, 0x10, 17, 1),
PIN_FIELD_BASE(86, 86, 2, 0x00e0, 0x10, 19, 1),
PIN_FIELD_BASE(87, 87, 2, 0x00e0, 0x10, 18, 1),
PIN_FIELD_BASE(88, 88, 2, 0x00e0, 0x10, 20, 1),
PIN_FIELD_BASE(89, 89, 2, 0x00e0, 0x10, 22, 1),
PIN_FIELD_BASE(90, 90, 2, 0x00e0, 0x10, 21, 1),
PIN_FIELD_BASE(91, 91, 2, 0x00e0, 0x10, 23, 1),
PIN_FIELD_BASE(92, 92, 2, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(93, 93, 2, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(94, 94, 2, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(95, 95, 2, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(96, 96, 2, 0x00d0, 0x10, 31, 1),
PIN_FIELD_BASE(97, 97, 2, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 2, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(99, 99, 2, 0x00d0, 0x10, 30, 1),
PIN_FIELD_BASE(100, 100, 2, 0x00e0, 0x10, 1, 1),
PIN_FIELD_BASE(101, 101, 2, 0x00d0, 0x10, 0, 1),
PIN_FIELD_BASE(102, 102, 2, 0x00d0, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x00d0, 0x10, 3, 1),
PIN_FIELD_BASE(104, 104, 2, 0x00d0, 0x10, 4, 1),
PIN_FIELD_BASE(105, 105, 2, 0x00d0, 0x10, 1, 1),
PIN_FIELD_BASE(106, 106, 2, 0x00d0, 0x10, 2, 1),
PIN_FIELD_BASE(107, 107, 2, 0x00d0, 0x10, 21, 1),
PIN_FIELD_BASE(108, 108, 2, 0x00d0, 0x10, 16, 1),
PIN_FIELD_BASE(109, 109, 2, 0x00d0, 0x10, 22, 1),
PIN_FIELD_BASE(110, 110, 2, 0x00d0, 0x10, 17, 1),
PIN_FIELD_BASE(111, 111, 2, 0x00d0, 0x10, 18, 1),
PIN_FIELD_BASE(112, 112, 2, 0x00d0, 0x10, 19, 1),
PIN_FIELD_BASE(113, 113, 2, 0x00d0, 0x10, 20, 1),
PIN_FIELD_BASE(114, 114, 2, 0x00d0, 0x10, 28, 1),
PIN_FIELD_BASE(115, 115, 2, 0x00d0, 0x10, 23, 1),
PIN_FIELD_BASE(116, 116, 2, 0x00d0, 0x10, 29, 1),
PIN_FIELD_BASE(117, 117, 2, 0x00d0, 0x10, 24, 1),
PIN_FIELD_BASE(118, 118, 2, 0x00d0, 0x10, 25, 1),
PIN_FIELD_BASE(119, 119, 2, 0x00d0, 0x10, 26, 1),
PIN_FIELD_BASE(120, 120, 2, 0x00d0, 0x10, 27, 1),
PIN_FIELD_BASE(121, 121, 3, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(122, 122, 3, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(123, 123, 3, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(124, 124, 3, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(125, 125, 2, 0x00d0, 0x10, 6, 1),
PIN_FIELD_BASE(126, 126, 2, 0x00d0, 0x10, 7, 1),
PIN_FIELD_BASE(127, 127, 2, 0x00d0, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 2, 0x00d0, 0x10, 9, 1),
PIN_FIELD_BASE(129, 129, 2, 0x00d0, 0x10, 10, 1),
PIN_FIELD_BASE(130, 130, 2, 0x00d0, 0x10, 11, 1),
PIN_FIELD_BASE(175, 175, 2, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(176, 176, 2, 0x00e0, 0x10, 12, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_pd_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(1, 1, 1, 0x00b0, 0x10, 7, 1),
PIN_FIELD_BASE(2, 2, 1, 0x00b0, 0x10, 8, 1),
PIN_FIELD_BASE(3, 3, 1, 0x00b0, 0x10, 9, 1),
PIN_FIELD_BASE(4, 4, 1, 0x00b0, 0x10, 10, 1),
PIN_FIELD_BASE(5, 5, 1, 0x00b0, 0x10, 11, 1),
PIN_FIELD_BASE(6, 6, 1, 0x00b0, 0x10, 12, 1),
PIN_FIELD_BASE(7, 7, 1, 0x00b0, 0x10, 13, 1),
PIN_FIELD_BASE(8, 8, 1, 0x00b0, 0x10, 14, 1),
PIN_FIELD_BASE(9, 9, 1, 0x00b0, 0x10, 15, 1),
PIN_FIELD_BASE(10, 10, 1, 0x00b0, 0x10, 16, 1),
PIN_FIELD_BASE(11, 11, 1, 0x00b0, 0x10, 17, 1),
PIN_FIELD_BASE(12, 12, 2, 0x00a0, 0x10, 12, 1),
PIN_FIELD_BASE(13, 13, 2, 0x00a0, 0x10, 13, 1),
PIN_FIELD_BASE(14, 14, 2, 0x00a0, 0x10, 14, 1),
PIN_FIELD_BASE(15, 15, 2, 0x00a0, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 3, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 3, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(18, 18, 4, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(19, 19, 4, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(20, 20, 4, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 4, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 4, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 4, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 4, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 1, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(26, 26, 1, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(27, 27, 1, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(28, 28, 1, 0x00b0, 0x10, 4, 1),
PIN_FIELD_BASE(29, 29, 1, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 1, 0x00b0, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 1, 0x00c0, 0x10, 11, 1),
PIN_FIELD_BASE(32, 32, 1, 0x00c0, 0x10, 10, 1),
PIN_FIELD_BASE(33, 33, 1, 0x00c0, 0x10, 13, 1),
PIN_FIELD_BASE(34, 34, 1, 0x00c0, 0x10, 12, 1),
PIN_FIELD_BASE(35, 35, 1, 0x00c0, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x00c0, 0x10, 14, 1),
PIN_FIELD_BASE(37, 37, 1, 0x00b0, 0x10, 21, 1),
PIN_FIELD_BASE(38, 38, 1, 0x00b0, 0x10, 18, 1),
PIN_FIELD_BASE(39, 39, 1, 0x00b0, 0x10, 19, 1),
PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 20, 1),
PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(47, 47, 1, 0x00b0, 0x10, 25, 1),
PIN_FIELD_BASE(48, 48, 1, 0x00b0, 0x10, 24, 1),
PIN_FIELD_BASE(49, 49, 1, 0x00b0, 0x10, 23, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 3, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(54, 54, 3, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(55, 55, 1, 0x00b0, 0x10, 26, 1),
PIN_FIELD_BASE(56, 56, 1, 0x00b0, 0x10, 29, 1),
PIN_FIELD_BASE(57, 57, 2, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(58, 58, 2, 0x00b0, 0x10, 9, 1),
PIN_FIELD_BASE(59, 59, 1, 0x00b0, 0x10, 27, 1),
PIN_FIELD_BASE(60, 60, 1, 0x00b0, 0x10, 30, 1),
PIN_FIELD_BASE(61, 61, 1, 0x00b0, 0x10, 28, 1),
PIN_FIELD_BASE(62, 62, 1, 0x00b0, 0x10, 31, 1),
PIN_FIELD_BASE(63, 63, 2, 0x00b0, 0x10, 7, 1),
PIN_FIELD_BASE(64, 64, 2, 0x00b0, 0x10, 10, 1),
PIN_FIELD_BASE(65, 65, 4, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 4, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(67, 67, 4, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(68, 68, 4, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00c0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00c0, 0x10, 0, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00c0, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00c0, 0x10, 4, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00c0, 0x10, 2, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00c0, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00c0, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00c0, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 1, 0x00c0, 0x10, 9, 1),
PIN_FIELD_BASE(78, 78, 1, 0x00c0, 0x10, 8, 1),
PIN_FIELD_BASE(79, 79, 4, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(80, 80, 4, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(81, 81, 4, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(82, 82, 4, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(83, 83, 2, 0x00b0, 0x10, 16, 1),
PIN_FIELD_BASE(84, 84, 2, 0x00b0, 0x10, 15, 1),
PIN_FIELD_BASE(85, 85, 2, 0x00b0, 0x10, 17, 1),
PIN_FIELD_BASE(86, 86, 2, 0x00b0, 0x10, 19, 1),
PIN_FIELD_BASE(87, 87, 2, 0x00b0, 0x10, 18, 1),
PIN_FIELD_BASE(88, 88, 2, 0x00b0, 0x10, 20, 1),
PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 22, 1),
PIN_FIELD_BASE(90, 90, 2, 0x00b0, 0x10, 21, 1),
PIN_FIELD_BASE(91, 91, 2, 0x00b0, 0x10, 23, 1),
PIN_FIELD_BASE(92, 92, 2, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(93, 93, 2, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(94, 94, 2, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(95, 95, 2, 0x00b0, 0x10, 4, 1),
PIN_FIELD_BASE(96, 96, 2, 0x00a0, 0x10, 31, 1),
PIN_FIELD_BASE(97, 97, 2, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 2, 0x00b0, 0x10, 8, 1),
PIN_FIELD_BASE(99, 99, 2, 0x00a0, 0x10, 30, 1),
PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1),
PIN_FIELD_BASE(101, 101, 2, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(102, 102, 2, 0x00a0, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(104, 104, 2, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(105, 105, 2, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(106, 106, 2, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(107, 107, 2, 0x00a0, 0x10, 21, 1),
PIN_FIELD_BASE(108, 108, 2, 0x00a0, 0x10, 16, 1),
PIN_FIELD_BASE(109, 109, 2, 0x00a0, 0x10, 22, 1),
PIN_FIELD_BASE(110, 110, 2, 0x00a0, 0x10, 17, 1),
PIN_FIELD_BASE(111, 111, 2, 0x00a0, 0x10, 18, 1),
PIN_FIELD_BASE(112, 112, 2, 0x00a0, 0x10, 19, 1),
PIN_FIELD_BASE(113, 113, 2, 0x00a0, 0x10, 20, 1),
PIN_FIELD_BASE(114, 114, 2, 0x00a0, 0x10, 28, 1),
PIN_FIELD_BASE(115, 115, 2, 0x00a0, 0x10, 23, 1),
PIN_FIELD_BASE(116, 116, 2, 0x00a0, 0x10, 29, 1),
PIN_FIELD_BASE(117, 117, 2, 0x00a0, 0x10, 24, 1),
PIN_FIELD_BASE(118, 118, 2, 0x00a0, 0x10, 25, 1),
PIN_FIELD_BASE(119, 119, 2, 0x00a0, 0x10, 26, 1),
PIN_FIELD_BASE(120, 120, 2, 0x00a0, 0x10, 27, 1),
PIN_FIELD_BASE(121, 121, 3, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(122, 122, 3, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(123, 123, 3, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(124, 124, 3, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(125, 125, 2, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(126, 126, 2, 0x00a0, 0x10, 7, 1),
PIN_FIELD_BASE(127, 127, 2, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 2, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(129, 129, 2, 0x00a0, 0x10, 10, 1),
PIN_FIELD_BASE(130, 130, 2, 0x00a0, 0x10, 11, 1),
PIN_FIELD_BASE(175, 175, 2, 0x00b0, 0x10, 11, 1),
PIN_FIELD_BASE(176, 176, 2, 0x00b0, 0x10, 12, 1),
};
static const struct mtk_pin_field_calc mt8188_pin_drv_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(1, 1, 1, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(2, 2, 1, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(3, 3, 1, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(4, 4, 1, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(5, 5, 1, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(6, 6, 1, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(7, 7, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(8, 8, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(9, 9, 1, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(10, 10, 1, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(11, 11, 1, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(12, 12, 2, 0x0010, 0x10, 24, 3),
PIN_FIELD_BASE(13, 13, 2, 0x0010, 0x10, 27, 3),
PIN_FIELD_BASE(14, 14, 2, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(15, 15, 2, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(16, 16, 3, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(17, 17, 3, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(18, 18, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(19, 19, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(20, 20, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(21, 21, 4, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(22, 22, 4, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(23, 23, 4, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(24, 24, 4, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(25, 25, 1, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(26, 26, 1, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(27, 27, 1, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(28, 28, 1, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(29, 29, 1, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(30, 30, 1, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(31, 31, 1, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(32, 32, 1, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(33, 33, 1, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(34, 34, 1, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(35, 35, 1, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(36, 36, 1, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(37, 37, 1, 0x0010, 0x10, 27, 3),
PIN_FIELD_BASE(38, 38, 1, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(39, 39, 1, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(40, 40, 1, 0x0010, 0x10, 24, 3),
PIN_FIELD_BASE(41, 41, 1, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(42, 42, 2, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(43, 43, 2, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(44, 44, 2, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(45, 45, 2, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(46, 46, 3, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(47, 47, 1, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(48, 48, 1, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(49, 49, 1, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(50, 50, 3, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(51, 51, 3, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(52, 52, 3, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(53, 53, 3, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(54, 54, 3, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(55, 55, 1, 0x0020, 0x10, 27, 3),
PIN_FIELD_BASE(56, 56, 1, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(57, 57, 2, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(58, 58, 2, 0x0030, 0x10, 15, 3),
PIN_FIELD_BASE(59, 59, 1, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(60, 60, 1, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(61, 61, 1, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(62, 62, 1, 0x0030, 0x10, 12, 3),
PIN_FIELD_BASE(63, 63, 2, 0x0030, 0x10, 12, 3),
PIN_FIELD_BASE(64, 64, 2, 0x0030, 0x10, 18, 3),
PIN_FIELD_BASE(65, 65, 4, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(66, 66, 4, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(67, 67, 4, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(68, 68, 4, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(69, 69, 1, 0x0030, 0x10, 18, 3),
PIN_FIELD_BASE(70, 70, 1, 0x0030, 0x10, 15, 3),
PIN_FIELD_BASE(71, 71, 1, 0x0040, 0x10, 0, 3),
PIN_FIELD_BASE(72, 72, 1, 0x0030, 0x10, 27, 3),
PIN_FIELD_BASE(73, 73, 1, 0x0030, 0x10, 21, 3),
PIN_FIELD_BASE(74, 74, 1, 0x0030, 0x10, 24, 3),
PIN_FIELD_BASE(75, 75, 1, 0x0040, 0x10, 6, 3),
PIN_FIELD_BASE(76, 76, 1, 0x0040, 0x10, 3, 3),
PIN_FIELD_BASE(77, 77, 1, 0x0040, 0x10, 12, 3),
PIN_FIELD_BASE(78, 78, 1, 0x0040, 0x10, 9, 3),
PIN_FIELD_BASE(79, 79, 4, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(80, 80, 4, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(81, 81, 4, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(82, 82, 4, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(83, 83, 2, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(84, 84, 2, 0x0020, 0x10, 27, 3),
PIN_FIELD_BASE(85, 85, 2, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(86, 86, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(87, 87, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(88, 88, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(89, 89, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(90, 90, 2, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(92, 92, 2, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(93, 93, 2, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(94, 94, 2, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(95, 95, 2, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(98, 98, 2, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(99, 99, 2, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(101, 101, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(102, 102, 2, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(103, 103, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(104, 104, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(105, 105, 2, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(106, 106, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(107, 107, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(108, 108, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(109, 109, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(110, 110, 2, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(111, 111, 2, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(112, 112, 2, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(113, 113, 2, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(114, 114, 2, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(115, 115, 2, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(116, 116, 2, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(117, 117, 2, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(118, 118, 2, 0x0020, 0x10, 12, 3),
PIN_FIELD_BASE(119, 119, 2, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(120, 120, 2, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(121, 121, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(122, 122, 3, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(123, 123, 3, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(124, 124, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(125, 125, 2, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(126, 126, 2, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(127, 127, 2, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(128, 128, 2, 0x0020, 0x10, 27, 3),
PIN_FIELD_BASE(129, 129, 2, 0x0020, 0x10, 27, 3),
PIN_FIELD_BASE(130, 130, 2, 0x0020, 0x10, 27, 3),
PIN_FIELD_BASE(131, 131, 1, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(132, 132, 1, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(133, 133, 1, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(134, 134, 1, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(135, 135, 1, 0x0020, 0x10, 15, 3),
PIN_FIELD_BASE(136, 136, 1, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(137, 137, 1, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(138, 138, 1, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(139, 139, 1, 0x0020, 0x10, 18, 3),
PIN_FIELD_BASE(140, 140, 1, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(141, 141, 1, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(142, 142, 1, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(143, 143, 1, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(144, 144, 1, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(145, 145, 1, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(146, 146, 1, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(147, 147, 1, 0x0020, 0x10, 21, 3),
PIN_FIELD_BASE(148, 148, 1, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(149, 149, 1, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(150, 150, 1, 0x0020, 0x10, 24, 3),
PIN_FIELD_BASE(151, 151, 2, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(152, 152, 2, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(153, 153, 2, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(154, 154, 2, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(155, 155, 2, 0x0010, 0x10, 21, 3),
PIN_FIELD_BASE(156, 156, 2, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(158, 158, 2, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(159, 159, 2, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(162, 162, 2, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(163, 163, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(164, 164, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(165, 165, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(166, 166, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(167, 167, 4, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(168, 168, 4, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(169, 169, 3, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(170, 170, 3, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(171, 171, 3, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(172, 172, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(173, 173, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(174, 174, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(175, 175, 2, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(176, 176, 2, 0x0030, 0x10, 3, 3),
};
static const struct mtk_pin_field_calc mt8188_pin_drv_adv_range[] = {
PIN_FIELD_BASE(53, 53, 3, 0x0020, 0x10, 0, 3),
PIN_FIELD_BASE(54, 54, 3, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 0, 3),
PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 9, 3),
PIN_FIELD_BASE(57, 57, 2, 0x0050, 0x10, 0, 3),
PIN_FIELD_BASE(58, 58, 2, 0x0050, 0x10, 6, 3),
PIN_FIELD_BASE(59, 59, 1, 0x0060, 0x10, 3, 3),
PIN_FIELD_BASE(60, 60, 1, 0x0060, 0x10, 12, 3),
PIN_FIELD_BASE(61, 61, 1, 0x0060, 0x10, 6, 3),
PIN_FIELD_BASE(62, 62, 1, 0x0060, 0x10, 15, 3),
PIN_FIELD_BASE(63, 63, 2, 0x0050, 0x10, 3, 3),
PIN_FIELD_BASE(64, 64, 2, 0x0050, 0x10, 9, 3),
PIN_FIELD_BASE(65, 65, 4, 0x0030, 0x10, 0, 3),
PIN_FIELD_BASE(66, 66, 4, 0x0030, 0x10, 6, 3),
PIN_FIELD_BASE(67, 67, 4, 0x0030, 0x10, 3, 3),
PIN_FIELD_BASE(68, 68, 4, 0x0030, 0x10, 9, 3),
PIN_FIELD_BASE(175, 175, 2, 0x0050, 0x10, 12, 3),
PIN_FIELD_BASE(176, 176, 2, 0x0050, 0x10, 15, 3),
};
static const struct mtk_pin_field_calc mt8188_pin_rsel_range[] = {
PIN_FIELD_BASE(53, 53, 3, 0x00c0, 0x10, 0, 3),
PIN_FIELD_BASE(54, 54, 3, 0x00c0, 0x10, 3, 3),
PIN_FIELD_BASE(55, 55, 1, 0x0160, 0x10, 0, 3),
PIN_FIELD_BASE(56, 56, 1, 0x0160, 0x10, 9, 3),
PIN_FIELD_BASE(57, 57, 2, 0x0150, 0x10, 0, 3),
PIN_FIELD_BASE(58, 58, 2, 0x0150, 0x10, 6, 3),
PIN_FIELD_BASE(59, 59, 1, 0x0160, 0x10, 3, 3),
PIN_FIELD_BASE(60, 60, 1, 0x0160, 0x10, 12, 3),
PIN_FIELD_BASE(61, 61, 1, 0x0160, 0x10, 6, 3),
PIN_FIELD_BASE(62, 62, 1, 0x0160, 0x10, 15, 3),
PIN_FIELD_BASE(63, 63, 2, 0x0150, 0x10, 3, 3),
PIN_FIELD_BASE(64, 64, 2, 0x0150, 0x10, 9, 3),
PIN_FIELD_BASE(65, 65, 4, 0x00d0, 0x10, 0, 3),
PIN_FIELD_BASE(66, 66, 4, 0x00d0, 0x10, 6, 3),
PIN_FIELD_BASE(67, 67, 4, 0x00d0, 0x10, 3, 3),
PIN_FIELD_BASE(68, 68, 4, 0x00d0, 0x10, 9, 3),
PIN_FIELD_BASE(175, 175, 2, 0x0150, 0x10, 12, 3),
PIN_FIELD_BASE(176, 176, 2, 0x0150, 0x10, 15, 3),
};
static const struct mtk_pin_rsel mt8188_pin_rsel_val_range[] = {
PIN_RSEL(53, 68, 0x0, 75000, 75000),
PIN_RSEL(53, 68, 0x1, 10000, 5000),
PIN_RSEL(53, 68, 0x2, 5000, 75000),
PIN_RSEL(53, 68, 0x3, 4000, 5000),
PIN_RSEL(53, 68, 0x4, 3000, 75000),
PIN_RSEL(53, 68, 0x5, 2000, 5000),
PIN_RSEL(53, 68, 0x6, 1500, 75000),
PIN_RSEL(53, 68, 0x7, 1000, 5000),
PIN_RSEL(175, 176, 0x0, 75000, 75000),
PIN_RSEL(175, 176, 0x1, 10000, 5000),
PIN_RSEL(175, 176, 0x2, 5000, 75000),
PIN_RSEL(175, 176, 0x3, 4000, 5000),
PIN_RSEL(175, 176, 0x4, 3000, 75000),
PIN_RSEL(175, 176, 0x5, 2000, 5000),
PIN_RSEL(175, 176, 0x6, 1500, 75000),
PIN_RSEL(175, 176, 0x7, 1000, 5000),
};
static const unsigned int mt8188_pull_type[] = {
MTK_PULL_PU_PD_TYPE, /*0*/
MTK_PULL_PU_PD_TYPE, /*1*/
MTK_PULL_PU_PD_TYPE, /*2*/
MTK_PULL_PU_PD_TYPE, /*3*/
MTK_PULL_PU_PD_TYPE, /*4*/
MTK_PULL_PU_PD_TYPE, /*5*/
MTK_PULL_PU_PD_TYPE, /*6*/
MTK_PULL_PU_PD_TYPE, /*7*/
MTK_PULL_PU_PD_TYPE, /*8*/
MTK_PULL_PU_PD_TYPE, /*9*/
MTK_PULL_PU_PD_TYPE, /*10*/
MTK_PULL_PU_PD_TYPE, /*11*/
MTK_PULL_PU_PD_TYPE, /*12*/
MTK_PULL_PU_PD_TYPE, /*13*/
MTK_PULL_PU_PD_TYPE, /*14*/
MTK_PULL_PU_PD_TYPE, /*15*/
MTK_PULL_PU_PD_TYPE, /*16*/
MTK_PULL_PU_PD_TYPE, /*17*/
MTK_PULL_PU_PD_TYPE, /*18*/
MTK_PULL_PU_PD_TYPE, /*19*/
MTK_PULL_PU_PD_TYPE, /*20*/
MTK_PULL_PU_PD_TYPE, /*21*/
MTK_PULL_PU_PD_TYPE, /*22*/
MTK_PULL_PU_PD_TYPE, /*23*/
MTK_PULL_PU_PD_TYPE, /*24*/
MTK_PULL_PU_PD_TYPE, /*25*/
MTK_PULL_PU_PD_TYPE, /*26*/
MTK_PULL_PU_PD_TYPE, /*27*/
MTK_PULL_PU_PD_TYPE, /*28*/
MTK_PULL_PU_PD_TYPE, /*29*/
MTK_PULL_PU_PD_TYPE, /*30*/
MTK_PULL_PU_PD_TYPE, /*31*/
MTK_PULL_PU_PD_TYPE, /*32*/
MTK_PULL_PU_PD_TYPE, /*33*/
MTK_PULL_PU_PD_TYPE, /*34*/
MTK_PULL_PU_PD_TYPE, /*35*/
MTK_PULL_PU_PD_TYPE, /*36*/
MTK_PULL_PU_PD_TYPE, /*37*/
MTK_PULL_PU_PD_TYPE, /*38*/
MTK_PULL_PU_PD_TYPE, /*39*/
MTK_PULL_PU_PD_TYPE, /*40*/
MTK_PULL_PU_PD_TYPE, /*41*/
MTK_PULL_PUPD_R1R0_TYPE, /*42*/
MTK_PULL_PUPD_R1R0_TYPE, /*43*/
MTK_PULL_PUPD_R1R0_TYPE, /*44*/
MTK_PULL_PUPD_R1R0_TYPE, /*45*/
MTK_PULL_PU_PD_TYPE, /*46*/
MTK_PULL_PU_PD_TYPE, /*47*/
MTK_PULL_PU_PD_TYPE, /*48*/
MTK_PULL_PU_PD_TYPE, /*49*/
MTK_PULL_PU_PD_TYPE, /*50*/
MTK_PULL_PU_PD_TYPE, /*51*/
MTK_PULL_PU_PD_TYPE, /*52*/
MTK_PULL_PU_PD_RSEL_TYPE, /*53*/
MTK_PULL_PU_PD_RSEL_TYPE, /*54*/
MTK_PULL_PU_PD_RSEL_TYPE, /*55*/
MTK_PULL_PU_PD_RSEL_TYPE, /*56*/
MTK_PULL_PU_PD_RSEL_TYPE, /*57*/
MTK_PULL_PU_PD_RSEL_TYPE, /*58*/
MTK_PULL_PU_PD_RSEL_TYPE, /*59*/
MTK_PULL_PU_PD_RSEL_TYPE, /*60*/
MTK_PULL_PU_PD_RSEL_TYPE, /*61*/
MTK_PULL_PU_PD_RSEL_TYPE, /*62*/
MTK_PULL_PU_PD_RSEL_TYPE, /*63*/
MTK_PULL_PU_PD_RSEL_TYPE, /*64*/
MTK_PULL_PU_PD_RSEL_TYPE, /*65*/
MTK_PULL_PU_PD_RSEL_TYPE, /*66*/
MTK_PULL_PU_PD_RSEL_TYPE, /*67*/
MTK_PULL_PU_PD_RSEL_TYPE, /*68*/
MTK_PULL_PU_PD_TYPE, /*69*/
MTK_PULL_PU_PD_TYPE, /*70*/
MTK_PULL_PU_PD_TYPE, /*71*/
MTK_PULL_PU_PD_TYPE, /*72*/
MTK_PULL_PU_PD_TYPE, /*73*/
MTK_PULL_PU_PD_TYPE, /*74*/
MTK_PULL_PU_PD_TYPE, /*75*/
MTK_PULL_PU_PD_TYPE, /*76*/
MTK_PULL_PU_PD_TYPE, /*77*/
MTK_PULL_PU_PD_TYPE, /*78*/
MTK_PULL_PU_PD_TYPE, /*79*/
MTK_PULL_PU_PD_TYPE, /*80*/
MTK_PULL_PU_PD_TYPE, /*81*/
MTK_PULL_PU_PD_TYPE, /*82*/
MTK_PULL_PU_PD_TYPE, /*83*/
MTK_PULL_PU_PD_TYPE, /*84*/
MTK_PULL_PU_PD_TYPE, /*85*/
MTK_PULL_PU_PD_TYPE, /*86*/
MTK_PULL_PU_PD_TYPE, /*87*/
MTK_PULL_PU_PD_TYPE, /*88*/
MTK_PULL_PU_PD_TYPE, /*89*/
MTK_PULL_PU_PD_TYPE, /*90*/
MTK_PULL_PU_PD_TYPE, /*91*/
MTK_PULL_PU_PD_TYPE, /*92*/
MTK_PULL_PU_PD_TYPE, /*93*/
MTK_PULL_PU_PD_TYPE, /*94*/
MTK_PULL_PU_PD_TYPE, /*95*/
MTK_PULL_PU_PD_TYPE, /*96*/
MTK_PULL_PU_PD_TYPE, /*97*/
MTK_PULL_PU_PD_TYPE, /*98*/
MTK_PULL_PU_PD_TYPE, /*99*/
MTK_PULL_PU_PD_TYPE, /*100*/
MTK_PULL_PU_PD_TYPE, /*101*/
MTK_PULL_PU_PD_TYPE, /*102*/
MTK_PULL_PU_PD_TYPE, /*103*/
MTK_PULL_PU_PD_TYPE, /*104*/
MTK_PULL_PU_PD_TYPE, /*105*/
MTK_PULL_PU_PD_TYPE, /*106*/
MTK_PULL_PU_PD_TYPE, /*107*/
MTK_PULL_PU_PD_TYPE, /*108*/
MTK_PULL_PU_PD_TYPE, /*109*/
MTK_PULL_PU_PD_TYPE, /*110*/
MTK_PULL_PU_PD_TYPE, /*111*/
MTK_PULL_PU_PD_TYPE, /*112*/
MTK_PULL_PU_PD_TYPE, /*113*/
MTK_PULL_PU_PD_TYPE, /*114*/
MTK_PULL_PU_PD_TYPE, /*115*/
MTK_PULL_PU_PD_TYPE, /*116*/
MTK_PULL_PU_PD_TYPE, /*117*/
MTK_PULL_PU_PD_TYPE, /*118*/
MTK_PULL_PU_PD_TYPE, /*119*/
MTK_PULL_PU_PD_TYPE, /*120*/
MTK_PULL_PU_PD_TYPE, /*121*/
MTK_PULL_PU_PD_TYPE, /*122*/
MTK_PULL_PU_PD_TYPE, /*123*/
MTK_PULL_PU_PD_TYPE, /*124*/
MTK_PULL_PU_PD_TYPE, /*125*/
MTK_PULL_PU_PD_TYPE, /*126*/
MTK_PULL_PU_PD_TYPE, /*127*/
MTK_PULL_PU_PD_TYPE, /*128*/
MTK_PULL_PU_PD_TYPE, /*129*/
MTK_PULL_PU_PD_TYPE, /*130*/
MTK_PULL_PUPD_R1R0_TYPE, /*131*/
MTK_PULL_PUPD_R1R0_TYPE, /*132*/
MTK_PULL_PUPD_R1R0_TYPE, /*133*/
MTK_PULL_PUPD_R1R0_TYPE, /*134*/
MTK_PULL_PUPD_R1R0_TYPE, /*135*/
MTK_PULL_PUPD_R1R0_TYPE, /*136*/
MTK_PULL_PUPD_R1R0_TYPE, /*137*/
MTK_PULL_PUPD_R1R0_TYPE, /*138*/
MTK_PULL_PUPD_R1R0_TYPE, /*139*/
MTK_PULL_PUPD_R1R0_TYPE, /*140*/
MTK_PULL_PUPD_R1R0_TYPE, /*141*/
MTK_PULL_PUPD_R1R0_TYPE, /*142*/
MTK_PULL_PUPD_R1R0_TYPE, /*143*/
MTK_PULL_PUPD_R1R0_TYPE, /*144*/
MTK_PULL_PUPD_R1R0_TYPE, /*145*/
MTK_PULL_PUPD_R1R0_TYPE, /*146*/
MTK_PULL_PUPD_R1R0_TYPE, /*147*/
MTK_PULL_PUPD_R1R0_TYPE, /*148*/
MTK_PULL_PUPD_R1R0_TYPE, /*149*/
MTK_PULL_PUPD_R1R0_TYPE, /*150*/
MTK_PULL_PUPD_R1R0_TYPE, /*151*/
MTK_PULL_PUPD_R1R0_TYPE, /*152*/
MTK_PULL_PUPD_R1R0_TYPE, /*153*/
MTK_PULL_PUPD_R1R0_TYPE, /*154*/
MTK_PULL_PUPD_R1R0_TYPE, /*155*/
MTK_PULL_PUPD_R1R0_TYPE, /*156*/
MTK_PULL_PUPD_R1R0_TYPE, /*157*/
MTK_PULL_PUPD_R1R0_TYPE, /*158*/
MTK_PULL_PUPD_R1R0_TYPE, /*159*/
MTK_PULL_PUPD_R1R0_TYPE, /*160*/
MTK_PULL_PUPD_R1R0_TYPE, /*161*/
MTK_PULL_PUPD_R1R0_TYPE, /*162*/
MTK_PULL_PUPD_R1R0_TYPE, /*163*/
MTK_PULL_PUPD_R1R0_TYPE, /*164*/
MTK_PULL_PUPD_R1R0_TYPE, /*165*/
MTK_PULL_PUPD_R1R0_TYPE, /*166*/
MTK_PULL_PUPD_R1R0_TYPE, /*167*/
MTK_PULL_PUPD_R1R0_TYPE, /*168*/
MTK_PULL_PUPD_R1R0_TYPE, /*169*/
MTK_PULL_PUPD_R1R0_TYPE, /*170*/
MTK_PULL_PUPD_R1R0_TYPE, /*171*/
MTK_PULL_PUPD_R1R0_TYPE, /*172*/
MTK_PULL_PUPD_R1R0_TYPE, /*173*/
MTK_PULL_PUPD_R1R0_TYPE, /*174*/
MTK_PULL_PU_PD_RSEL_TYPE, /*175*/
MTK_PULL_PU_PD_RSEL_TYPE, /*176*/
};
static const struct mtk_pin_reg_calc mt8188_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8188_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8188_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8188_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8188_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8188_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8188_pin_ies_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt8188_pin_tdsel_range),
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt8188_pin_rdsel_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8188_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8188_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8188_pin_r1_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8188_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8188_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8188_pin_drv_range),
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8188_pin_drv_adv_range),
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8188_pin_rsel_range),
};
static const char * const mt8188_pinctrl_register_base_name[] = {
"iocfg0", "iocfg_rm", "iocfg_lt", "iocfg_lm", "iocfg_rt",
};
static const struct mtk_eint_hw mt8188_eint_hw = {
.port_mask = 0xf,
.ports = 7,
.ap_num = 225,
.db_cnt = 32,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt8188_data = {
.reg_cal = mt8188_reg_cals,
.pins = mtk_pins_mt8188,
.npins = ARRAY_SIZE(mtk_pins_mt8188),
.ngrps = ARRAY_SIZE(mtk_pins_mt8188),
.eint_hw = &mt8188_eint_hw,
.nfuncs = 8,
.gpio_m = 0,
.base_names = mt8188_pinctrl_register_base_name,
.nbase_names = ARRAY_SIZE(mt8188_pinctrl_register_base_name),
.pull_type = mt8188_pull_type,
.pin_rsel = mt8188_pin_rsel_val_range,
.npin_rsel = ARRAY_SIZE(mt8188_pin_rsel_val_range),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
};
static const struct of_device_id mt8188_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8188-pinctrl", .data = &mt8188_data },
{ }
};
static struct platform_driver mt8188_pinctrl_driver = {
.driver = {
.name = "mt8188-pinctrl",
.of_match_table = mt8188_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8188_pinctrl_init(void)
{
return platform_driver_register(&mt8188_pinctrl_driver);
}
arch_initcall(mt8188_pinctrl_init);
MODULE_DESCRIPTION("MediaTek MT8188 Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8188.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
* Copyright (c) 2014 MediaTek Inc.
* Author: Hongzhou.Yang <[email protected]>
*/
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pm.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "mtk-eint.h"
#include "pinctrl-mtk-common.h"
#define GPIO_MODE_BITS 3
#define GPIO_MODE_PREFIX "GPIO"
static const char * const mtk_gpio_functions[] = {
"func0", "func1", "func2", "func3",
"func4", "func5", "func6", "func7",
"func8", "func9", "func10", "func11",
"func12", "func13", "func14", "func15",
};
/*
* There are two base address for pull related configuration
* in mt8135, and different GPIO pins use different base address.
* When pin number greater than type1_start and less than type1_end,
* should use the second base address.
*/
static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
unsigned long pin)
{
if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
return pctl->regmap2;
return pctl->regmap1;
}
static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
{
/* Different SoC has different mask and port shift. */
return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask)
<< pctl->devdata->port_shf;
}
static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset,
bool input)
{
unsigned int reg_addr;
unsigned int bit;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & pctl->devdata->mode_mask);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(®_addr, offset);
if (input)
/* Different SoC has different alignment offset. */
reg_addr = CLR_ADDR(reg_addr, pctl);
else
reg_addr = SET_ADDR(reg_addr, pctl);
regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
return 0;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
unsigned int reg_addr;
unsigned int bit;
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
bit = BIT(offset & pctl->devdata->mode_mask);
if (value)
reg_addr = SET_ADDR(reg_addr, pctl);
else
reg_addr = CLR_ADDR(reg_addr, pctl);
regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
}
static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
int value, enum pin_config_param arg)
{
unsigned int reg_addr, offset;
unsigned int bit;
/**
* Due to some soc are not support ies/smt config, add this special
* control to handle it.
*/
if (!pctl->devdata->spec_ies_smt_set &&
pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
arg == PIN_CONFIG_INPUT_ENABLE)
return -EINVAL;
if (!pctl->devdata->spec_ies_smt_set &&
pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return -EINVAL;
/*
* Due to some pins are irregular, their input enable and smt
* control register are discontinuous, so we need this special handle.
*/
if (pctl->devdata->spec_ies_smt_set) {
return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
pctl->devdata, pin, value, arg);
}
if (arg == PIN_CONFIG_INPUT_ENABLE)
offset = pctl->devdata->ies_offset;
else
offset = pctl->devdata->smt_offset;
bit = BIT(offset & pctl->devdata->mode_mask);
if (value)
reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
else
reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
return 0;
}
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
const struct mtk_pinctrl_devdata *devdata,
unsigned int pin, int value, enum pin_config_param arg)
{
const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
unsigned int i, info_num, reg_addr, bit;
switch (arg) {
case PIN_CONFIG_INPUT_ENABLE:
ies_smt_infos = devdata->spec_ies;
info_num = devdata->n_spec_ies;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
ies_smt_infos = devdata->spec_smt;
info_num = devdata->n_spec_smt;
break;
default:
break;
}
if (!ies_smt_infos)
return -EINVAL;
for (i = 0; i < info_num; i++) {
if (pin >= ies_smt_infos[i].start &&
pin <= ies_smt_infos[i].end) {
break;
}
}
if (i == info_num)
return -EINVAL;
if (value)
reg_addr = ies_smt_infos[i].offset + devdata->port_align;
else
reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
bit = BIT(ies_smt_infos[i].bit);
regmap_write(regmap, reg_addr, bit);
return 0;
}
static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
struct mtk_pinctrl *pctl, unsigned long pin) {
int i;
for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
const struct mtk_pin_drv_grp *pin_drv =
pctl->devdata->pin_drv_grp + i;
if (pin == pin_drv->pin)
return pin_drv;
}
return NULL;
}
static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
unsigned int pin, unsigned char driving)
{
const struct mtk_pin_drv_grp *pin_drv;
unsigned int val;
unsigned int bits, mask, shift;
const struct mtk_drv_group_desc *drv_grp;
if (pin >= pctl->devdata->npins)
return -EINVAL;
pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
return -EINVAL;
drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
&& !(driving % drv_grp->step)) {
val = driving / drv_grp->step - 1;
bits = drv_grp->high_bit - drv_grp->low_bit + 1;
mask = BIT(bits) - 1;
shift = pin_drv->bit + drv_grp->low_bit;
mask <<= shift;
val <<= shift;
return regmap_update_bits(mtk_get_regmap(pctl, pin),
pin_drv->offset, mask, val);
}
return -EINVAL;
}
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
const struct mtk_pinctrl_devdata *devdata,
unsigned int pin, bool isup, unsigned int r1r0)
{
unsigned int i;
unsigned int reg_pupd, reg_set, reg_rst;
unsigned int bit_pupd, bit_r0, bit_r1;
const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
bool find = false;
if (!devdata->spec_pupd)
return -EINVAL;
for (i = 0; i < devdata->n_spec_pupd; i++) {
if (pin == devdata->spec_pupd[i].pin) {
find = true;
break;
}
}
if (!find)
return -EINVAL;
spec_pupd_pin = devdata->spec_pupd + i;
reg_set = spec_pupd_pin->offset + devdata->port_align;
reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
if (isup)
reg_pupd = reg_rst;
else
reg_pupd = reg_set;
bit_pupd = BIT(spec_pupd_pin->pupd_bit);
regmap_write(regmap, reg_pupd, bit_pupd);
bit_r0 = BIT(spec_pupd_pin->r0_bit);
bit_r1 = BIT(spec_pupd_pin->r1_bit);
switch (r1r0) {
case MTK_PUPD_SET_R1R0_00:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_01:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_rst, bit_r1);
break;
case MTK_PUPD_SET_R1R0_10:
regmap_write(regmap, reg_rst, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
case MTK_PUPD_SET_R1R0_11:
regmap_write(regmap, reg_set, bit_r0);
regmap_write(regmap, reg_set, bit_r1);
break;
default:
return -EINVAL;
}
return 0;
}
static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
* they have separate pull up/down bit, R0 and R1
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
/* For special pins, bias-disable is set by R1R0,
* the parameter should be "MTK_PUPD_SET_R1R0_00".
*/
r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
pctl->devdata, pin, isup,
r1r0);
if (!ret)
return 0;
}
/* For generic pull config, default arg value should be 0 or 1. */
if (arg != 0 && arg != 1) {
dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
arg, pin);
return -EINVAL;
}
if (pctl->devdata->mt8365_set_clr_mode) {
bit = pin & pctl->devdata->mode_mask;
reg_pullen = mtk_get_port(pctl, pin) +
pctl->devdata->pullen_offset;
reg_pullsel = mtk_get_port(pctl, pin) +
pctl->devdata->pullsel_offset;
ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
bit, reg_pullen, reg_pullsel,
enable, isup);
if (ret)
return -EINVAL;
return 0;
}
bit = BIT(pin & pctl->devdata->mode_mask);
if (enable)
reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
pctl->devdata->pullen_offset, pctl);
else
reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
pctl->devdata->pullen_offset, pctl);
if (isup)
reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
pctl->devdata->pullsel_offset, pctl);
else
reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
pctl->devdata->pullsel_offset, pctl);
regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
return 0;
}
static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
int ret = 0;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
break;
case PIN_CONFIG_INPUT_ENABLE:
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
break;
case PIN_CONFIG_OUTPUT:
mtk_gpio_set(pctl->chip, pin, arg);
ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = mtk_pconf_set_driving(pctl, pin, arg);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *config)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*config = pctl->groups[group].config;
return 0;
}
static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *g = &pctl->groups[group];
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = mtk_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
g->config = configs[i];
}
return 0;
}
static const struct pinconf_ops mtk_pconf_ops = {
.pin_config_group_get = mtk_pconf_group_get,
.pin_config_group_set = mtk_pconf_group_set,
};
static struct mtk_pinctrl_group *
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
{
int i;
for (i = 0; i < pctl->ngroups; i++) {
struct mtk_pinctrl_group *grp = pctl->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
{
const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
const struct mtk_desc_function *func = pin->functions;
while (func && func->name) {
if (func->muxval == fnum)
return func;
func++;
}
return NULL;
}
static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
u32 pin_num, u32 fnum)
{
int i;
for (i = 0; i < pctl->devdata->npins; i++) {
const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
if (pin->pin.number == pin_num) {
const struct mtk_desc_function *func =
pin->functions;
while (func && func->name) {
if (func->muxval == fnum)
return true;
func++;
}
break;
}
}
return false;
}
static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps)
{
bool ret;
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
if (!ret) {
dev_err(pctl->dev, "invalid function %d on pin %d .\n",
fnum, pin);
return -EINVAL;
}
(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct property *pins;
u32 pinfunc, pin, func;
int num_pins, num_funcs, maps_per_pin;
unsigned long *configs;
unsigned int num_configs;
bool has_config = false;
int i, err;
unsigned reserve = 0;
struct mtk_pinctrl_group *grp;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps, num_maps, reserve);
if (err < 0)
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux",
i, &pinfunc);
if (err)
goto exit;
pin = MTK_GET_PIN_NO(pinfunc);
func = MTK_GET_PIN_FUNC(pinfunc);
if (pin >= pctl->devdata->npins ||
func >= ARRAY_SIZE(mtk_gpio_functions)) {
dev_err(pctl->dev, "invalid pins value.\n");
err = -EINVAL;
goto exit;
}
grp = mtk_pctrl_find_group_by_pin(pctl, pin);
if (!grp) {
dev_err(pctl->dev, "unable to match pin %d to group\n",
pin);
err = -EINVAL;
goto exit;
}
err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
reserved_maps, num_maps);
if (err < 0)
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, grp->name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto exit;
}
}
err = 0;
exit:
kfree(configs);
return err;
}
static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
struct device_node *np;
unsigned reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node(np_config, np) {
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
return 0;
}
static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops mtk_pctrl_ops = {
.dt_node_to_map = mtk_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
.get_groups_count = mtk_pctrl_get_groups_count,
.get_group_name = mtk_pctrl_get_group_name,
.get_group_pins = mtk_pctrl_get_group_pins,
};
static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mtk_gpio_functions);
}
static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return mtk_gpio_functions[selector];
}
static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->grp_names;
*num_groups = pctl->ngroups;
return 0;
}
static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
unsigned long pin, unsigned long mode)
{
unsigned int reg_addr;
unsigned char bit;
unsigned int val;
unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
if (pctl->devdata->spec_pinmux_set)
pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
pin, mode);
reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf)
+ pctl->devdata->pinmux_offset;
mode &= mask;
bit = pin % pctl->devdata->mode_per_reg;
mask <<= (GPIO_MODE_BITS * bit);
val = (mode << (GPIO_MODE_BITS * bit));
return regmap_update_bits(mtk_get_regmap(pctl, pin),
reg_addr, mask, val);
}
static const struct mtk_desc_pin *
mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
{
int i;
const struct mtk_desc_pin *pin;
for (i = 0; i < pctl->devdata->npins; i++) {
pin = pctl->devdata->pins + i;
if (pin->eint.eintnum == eint_num)
return pin;
}
return NULL;
}
static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
bool ret;
const struct mtk_desc_function *desc;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *g = pctl->groups + group;
ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
if (!ret) {
dev_err(pctl->dev, "invalid function %d on group %d .\n",
function, group);
return -EINVAL;
}
desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
if (!desc)
return -EINVAL;
mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
return 0;
}
static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
unsigned offset)
{
const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
const struct mtk_desc_function *func = pin->functions;
while (func && func->name) {
if (!strncmp(func->name, GPIO_MODE_PREFIX,
sizeof(GPIO_MODE_PREFIX)-1))
return func->muxval;
func++;
}
return -EINVAL;
}
static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
int muxval;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
muxval = mtk_pmx_find_gpio_mode(pctl, offset);
if (muxval < 0) {
dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
return -EINVAL;
}
mtk_pmx_set_mode(pctldev, offset, muxval);
mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
return 0;
}
static const struct pinmux_ops mtk_pmx_ops = {
.get_functions_count = mtk_pmx_get_funcs_cnt,
.get_function_name = mtk_pmx_get_func_name,
.get_function_groups = mtk_pmx_get_func_groups,
.set_mux = mtk_pmx_set_mux,
.gpio_set_direction = mtk_pmx_gpio_set_direction,
.gpio_request_enable = mtk_pmx_gpio_request_enable,
};
static int mtk_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
mtk_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
unsigned int reg_addr;
unsigned int bit;
unsigned int read_val = 0;
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & pctl->devdata->mode_mask);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(®_addr, offset);
regmap_read(pctl->regmap1, reg_addr, &read_val);
if (read_val & bit)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
{
unsigned int reg_addr;
unsigned int bit;
unsigned int read_val = 0;
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
reg_addr = mtk_get_port(pctl, offset) +
pctl->devdata->din_offset;
bit = BIT(offset & pctl->devdata->mode_mask);
regmap_read(pctl->regmap1, reg_addr, &read_val);
return !!(read_val & bit);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
const struct mtk_desc_pin *pin;
unsigned long eint_n;
pin = pctl->devdata->pins + offset;
if (pin->eint.eintnum == NO_EINT_SUPPORT)
return -EINVAL;
eint_n = pin->eint.eintnum;
return mtk_eint_find_irq(pctl->eint, eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
unsigned long config)
{
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
const struct mtk_desc_pin *pin;
unsigned long eint_n;
u32 debounce;
if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
return -ENOTSUPP;
pin = pctl->devdata->pins + offset;
if (pin->eint.eintnum == NO_EINT_SUPPORT)
return -EINVAL;
debounce = pinconf_to_config_argument(config);
eint_n = pin->eint.eintnum;
return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
}
static const struct gpio_chip mtk_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = mtk_gpio_get_direction,
.direction_input = mtk_gpio_direction_input,
.direction_output = mtk_gpio_direction_output,
.get = mtk_gpio_get,
.set = mtk_gpio_set,
.to_irq = mtk_gpio_to_irq,
.set_config = mtk_gpio_set_config,
};
static int mtk_eint_suspend(struct device *device)
{
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
return mtk_eint_do_suspend(pctl->eint);
}
static int mtk_eint_resume(struct device *device)
{
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
return mtk_eint_do_resume(pctl->eint);
}
const struct dev_pm_ops mtk_eint_pm_ops = {
.suspend_noirq = mtk_eint_suspend,
.resume_noirq = mtk_eint_resume,
};
static int mtk_pctrl_build_state(struct platform_device *pdev)
{
struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
int i;
pctl->ngroups = pctl->devdata->npins;
/* Allocate groups */
pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->groups), GFP_KERNEL);
if (!pctl->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->grp_names), GFP_KERNEL);
if (!pctl->grp_names)
return -ENOMEM;
for (i = 0; i < pctl->devdata->npins; i++) {
const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
struct mtk_pinctrl_group *group = pctl->groups + i;
group->name = pin->pin.name;
group->pin = pin->pin.number;
pctl->grp_names[i] = pin->pin.name;
}
return 0;
}
static int
mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
{
struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
const struct mtk_desc_pin *pin;
pin = mtk_find_pin_by_eint_num(pctl, eint_n);
if (!pin)
return -EINVAL;
*gpio_chip = pctl->chip;
*gpio_n = pin->pin.number;
return 0;
}
static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
const struct mtk_desc_pin *pin;
pin = mtk_find_pin_by_eint_num(pctl, eint_n);
if (!pin)
return -EINVAL;
return mtk_gpio_get(pctl->chip, pin->pin.number);
}
static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
const struct mtk_desc_pin *pin;
pin = mtk_find_pin_by_eint_num(pctl, eint_n);
if (!pin)
return -EINVAL;
/* set mux to INT mode */
mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
/* set gpio direction to input */
mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
true);
/* set input-enable */
mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
PIN_CONFIG_INPUT_ENABLE);
return 0;
}
static const struct mtk_eint_xt mtk_eint_xt = {
.get_gpio_n = mtk_xt_get_gpio_n,
.get_gpio_state = mtk_xt_get_gpio_state,
.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
};
static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
if (!of_property_read_bool(np, "interrupt-controller"))
return -ENODEV;
pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
if (!pctl->eint)
return -ENOMEM;
pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctl->eint->base))
return PTR_ERR(pctl->eint->base);
pctl->eint->irq = irq_of_parse_and_map(np, 0);
if (!pctl->eint->irq)
return -EINVAL;
pctl->eint->dev = &pdev->dev;
/*
* If pctl->eint->regs == NULL, it would fall back into using a generic
* register map in mtk_eint_do_init calls.
*/
pctl->eint->regs = pctl->devdata->eint_regs;
pctl->eint->hw = &pctl->devdata->eint_hw;
pctl->eint->pctl = pctl;
pctl->eint->gpio_xlate = &mtk_eint_xt;
return mtk_eint_do_init(pctl->eint);
}
/* This is used as a common probe function */
int mtk_pctrl_init(struct platform_device *pdev,
const struct mtk_pinctrl_devdata *data,
struct regmap *regmap)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *pctl;
struct device_node *np = pdev->dev.of_node, *node;
int ret, i;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
if (node) {
pctl->regmap1 = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(pctl->regmap1))
return PTR_ERR(pctl->regmap1);
} else if (regmap) {
pctl->regmap1 = regmap;
} else {
return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
}
/* Only 8135 has two base addr, other SoCs have only one. */
node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
if (node) {
pctl->regmap2 = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(pctl->regmap2))
return PTR_ERR(pctl->regmap2);
}
pctl->devdata = data;
ret = mtk_pctrl_build_state(pdev);
if (ret)
return dev_err_probe(dev, ret, "build state failed\n");
pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < pctl->devdata->npins; i++)
pins[i] = pctl->devdata->pins[i].pin;
pctl->pctl_desc.name = dev_name(&pdev->dev);
pctl->pctl_desc.owner = THIS_MODULE;
pctl->pctl_desc.pins = pins;
pctl->pctl_desc.npins = pctl->devdata->npins;
pctl->pctl_desc.confops = &mtk_pconf_ops;
pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
pctl->pctl_desc.pmxops = &mtk_pmx_ops;
pctl->dev = &pdev->dev;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
pctl);
if (IS_ERR(pctl->pctl_dev))
return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
"Couldn't register pinctrl driver\n");
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
if (!pctl->chip)
return -ENOMEM;
*pctl->chip = mtk_gpio_chip;
pctl->chip->ngpio = pctl->devdata->npins;
pctl->chip->label = dev_name(&pdev->dev);
pctl->chip->parent = &pdev->dev;
pctl->chip->base = -1;
ret = gpiochip_add_data(pctl->chip, pctl);
if (ret)
return -EINVAL;
/* Register the GPIO to pin mappings. */
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
0, 0, pctl->devdata->npins);
if (ret) {
ret = -EINVAL;
goto chip_error;
}
ret = mtk_eint_init(pctl, pdev);
if (ret)
goto chip_error;
return 0;
chip_error:
gpiochip_remove(pctl->chip);
return ret;
}
int mtk_pctrl_common_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
if (!data)
return -ENODEV;
return mtk_pctrl_init(pdev, data, NULL);
}
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 MediaTek Inc.
*
* Author: Zhiyong Tao <[email protected]>
*
*/
#include "pinctrl-mtk-mt8195.h"
#include "pinctrl-paris.h"
/* MT8195 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
* iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
* iocfg[6]:0x11f40000.
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 1)
static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = {
PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = {
PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_di_range[] = {
PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_do_range[] = {
PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x040, 0x10, 5, 1),
PIN_FIELD_BASE(6, 6, 4, 0x040, 0x10, 6, 1),
PIN_FIELD_BASE(7, 7, 4, 0x040, 0x10, 7, 1),
PIN_FIELD_BASE(8, 8, 4, 0x040, 0x10, 13, 1),
PIN_FIELD_BASE(9, 9, 4, 0x040, 0x10, 8, 1),
PIN_FIELD_BASE(10, 10, 4, 0x040, 0x10, 14, 1),
PIN_FIELD_BASE(11, 11, 4, 0x040, 0x10, 9, 1),
PIN_FIELD_BASE(12, 12, 4, 0x040, 0x10, 15, 1),
PIN_FIELD_BASE(13, 13, 4, 0x040, 0x10, 10, 1),
PIN_FIELD_BASE(14, 14, 4, 0x040, 0x10, 16, 1),
PIN_FIELD_BASE(15, 15, 4, 0x040, 0x10, 11, 1),
PIN_FIELD_BASE(16, 16, 4, 0x040, 0x10, 17, 1),
PIN_FIELD_BASE(17, 17, 4, 0x040, 0x10, 12, 1),
PIN_FIELD_BASE(18, 18, 2, 0x040, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x040, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x040, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x040, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x040, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x040, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x040, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x040, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x060, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x060, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x060, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x060, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x070, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x070, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x070, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x070, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x070, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x070, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x070, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x070, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x070, 0x10, 20, 1),
PIN_FIELD_BASE(45, 45, 1, 0x070, 0x10, 21, 1),
PIN_FIELD_BASE(46, 46, 1, 0x060, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x060, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x060, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x060, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x060, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x060, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x060, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x060, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x060, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x060, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x060, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x060, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x060, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x060, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x060, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x060, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x060, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x070, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x060, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x070, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x070, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x060, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x060, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x060, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x060, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x060, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x070, 0x10, 11, 1),
PIN_FIELD_BASE(77, 77, 3, 0x030, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x030, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x030, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x030, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x030, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x030, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x030, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x030, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x030, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x030, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x030, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x030, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x030, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x030, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x030, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x030, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x030, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x030, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x030, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x030, 0x10, 0, 1),
PIN_FIELD_BASE(97, 97, 3, 0x030, 0x10, 20, 1),
PIN_FIELD_BASE(98, 98, 3, 0x030, 0x10, 28, 1),
PIN_FIELD_BASE(99, 99, 3, 0x030, 0x10, 27, 1),
PIN_FIELD_BASE(100, 100, 3, 0x030, 0x10, 30, 1),
PIN_FIELD_BASE(101, 101, 3, 0x030, 0x10, 29, 1),
PIN_FIELD_BASE(102, 102, 3, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(103, 103, 3, 0x030, 0x10, 31, 1),
PIN_FIELD_BASE(104, 104, 3, 0x030, 0x10, 25, 1),
PIN_FIELD_BASE(105, 105, 3, 0x030, 0x10, 26, 1),
PIN_FIELD_BASE(106, 106, 3, 0x030, 0x10, 23, 1),
PIN_FIELD_BASE(107, 107, 3, 0x030, 0x10, 24, 1),
PIN_FIELD_BASE(108, 108, 3, 0x030, 0x10, 22, 1),
PIN_FIELD_BASE(109, 109, 3, 0x030, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x030, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x030, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x030, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x030, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x030, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x030, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x030, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x030, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x030, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x030, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x030, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x030, 0x10, 10, 1),
PIN_FIELD_BASE(128, 128, 3, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(129, 129, 3, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(130, 130, 3, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(131, 131, 3, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(132, 132, 6, 0x030, 0x10, 13, 1),
PIN_FIELD_BASE(133, 133, 6, 0x030, 0x10, 12, 1),
PIN_FIELD_BASE(134, 134, 6, 0x030, 0x10, 15, 1),
PIN_FIELD_BASE(135, 135, 6, 0x030, 0x10, 14, 1),
PIN_FIELD_BASE(136, 136, 1, 0x070, 0x10, 13, 1),
PIN_FIELD_BASE(137, 137, 1, 0x070, 0x10, 12, 1),
PIN_FIELD_BASE(138, 138, 1, 0x070, 0x10, 15, 1),
PIN_FIELD_BASE(139, 139, 1, 0x070, 0x10, 14, 1),
PIN_FIELD_BASE(140, 140, 1, 0x070, 0x10, 17, 1),
PIN_FIELD_BASE(141, 141, 1, 0x070, 0x10, 16, 1),
PIN_FIELD_BASE(142, 142, 1, 0x070, 0x10, 19, 1),
PIN_FIELD_BASE(143, 143, 1, 0x070, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0d0, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0d0, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0d0, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0d0, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0d0, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0d0, 0x10, 5, 1),
PINS_FIELD_BASE(6, 7, 4, 0x0d0, 0x10, 6, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0d0, 0x10, 12, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0d0, 0x10, 7, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0d0, 0x10, 13, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0d0, 0x10, 8, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0d0, 0x10, 14, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0d0, 0x10, 9, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0d0, 0x10, 15, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0d0, 0x10, 10, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0d0, 0x10, 16, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0d0, 0x10, 11, 1),
PIN_FIELD_BASE(18, 18, 2, 0x090, 0x10, 11, 1),
PIN_FIELD_BASE(19, 19, 2, 0x090, 0x10, 10, 1),
PIN_FIELD_BASE(20, 20, 2, 0x090, 0x10, 9, 1),
PIN_FIELD_BASE(21, 21, 2, 0x090, 0x10, 11, 1),
PIN_FIELD_BASE(22, 22, 2, 0x090, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x090, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x090, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x090, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x090, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x090, 0x10, 5, 1),
PIN_FIELD_BASE(28, 28, 2, 0x090, 0x10, 6, 1),
PIN_FIELD_BASE(29, 29, 2, 0x090, 0x10, 7, 1),
PIN_FIELD_BASE(30, 30, 2, 0x090, 0x10, 8, 1),
PINS_FIELD_BASE(31, 33, 1, 0x0f0, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 1, 0x0f0, 0x10, 0, 1),
PIN_FIELD_BASE(35, 35, 1, 0x0f0, 0x10, 1, 1),
PIN_FIELD_BASE(36, 36, 1, 0x0f0, 0x10, 4, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0f0, 0x10, 2, 1),
PINS_FIELD_BASE(38, 39, 1, 0x0f0, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0f0, 0x10, 14, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0f0, 0x10, 13, 1),
PIN_FIELD_BASE(42, 42, 1, 0x0f0, 0x10, 16, 1),
PIN_FIELD_BASE(43, 43, 1, 0x0f0, 0x10, 15, 1),
PIN_FIELD_BASE(44, 44, 1, 0x0f0, 0x10, 25, 1),
PIN_FIELD_BASE(45, 45, 1, 0x0f0, 0x10, 26, 1),
PINS_FIELD_BASE(46, 47, 1, 0x0f0, 0x10, 5, 1),
PINS_FIELD_BASE(48, 51, 1, 0x0f0, 0x10, 6, 1),
PINS_FIELD_BASE(52, 55, 1, 0x0f0, 0x10, 7, 1),
PINS_FIELD_BASE(56, 59, 1, 0x0f0, 0x10, 8, 1),
PINS_FIELD_BASE(60, 63, 1, 0x0f0, 0x10, 9, 1),
PIN_FIELD_BASE(64, 64, 1, 0x0f0, 0x10, 10, 1),
PINS_FIELD_BASE(65, 68, 1, 0x0f0, 0x10, 3, 1),
PINS_FIELD_BASE(69, 71, 1, 0x0f0, 0x10, 10, 1),
PINS_FIELD_BASE(72, 75, 1, 0x0f0, 0x10, 11, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0f0, 0x10, 12, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0e0, 0x10, 0, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0e0, 0x10, 1, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0e0, 0x10, 6, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0e0, 0x10, 7, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0e0, 0x10, 8, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0e0, 0x10, 9, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0e0, 0x10, 10, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0e0, 0x10, 11, 1),
PINS_FIELD_BASE(85, 88, 3, 0x0e0, 0x10, 14, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0e0, 0x10, 2, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0e0, 0x10, 3, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0e0, 0x10, 4, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0e0, 0x10, 5, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0e0, 0x10, 12, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0e0, 0x10, 13, 1),
PINS_FIELD_BASE(95, 98, 3, 0x0e0, 0x10, 15, 1),
PINS_FIELD_BASE(99, 102, 3, 0x0e0, 0x10, 16, 1),
PINS_FIELD_BASE(103, 104, 3, 0x0e0, 0x10, 17, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0e0, 0x10, 18, 1),
PINS_FIELD_BASE(106, 107, 3, 0x0e0, 0x10, 17, 1),
PINS_FIELD_BASE(108, 109, 3, 0x0e0, 0x10, 18, 1),
PIN_FIELD_BASE(110, 110, 5, 0x070, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x070, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x070, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x070, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x070, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x070, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0c0, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0c0, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0c0, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0c0, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0c0, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0c0, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0c0, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0c0, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0c0, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0c0, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0c0, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0c0, 0x10, 10, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0e0, 0x10, 18, 1),
PINS_FIELD_BASE(129, 131, 3, 0x0e0, 0x10, 19, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0c0, 0x10, 13, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0c0, 0x10, 12, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0c0, 0x10, 15, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0c0, 0x10, 14, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0f0, 0x10, 18, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0f0, 0x10, 17, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0f0, 0x10, 20, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0f0, 0x10, 19, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0f0, 0x10, 22, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0f0, 0x10, 21, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0f0, 0x10, 24, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0f0, 0x10, 23, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = {
PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(18, 18, 2, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x00a0, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x00a0, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x00a0, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x00a0, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x00a0, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x00b0, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 21, 1),
PIN_FIELD_BASE(45, 45, 1, 0x00b0, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 1, 0x00a0, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x00a0, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x00a0, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x00a0, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x00a0, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x00a0, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x00a0, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x00a0, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x00a0, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x00a0, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x00a0, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x00a0, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x00a0, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x00a0, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x00a0, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x00a0, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x00a0, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x00b0, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x00a0, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 11, 1),
PIN_FIELD_BASE(97, 97, 3, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 3, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(99, 99, 3, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(100, 100, 3, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(101, 101, 3, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(102, 102, 3, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(103, 103, 3, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(108, 108, 3, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(109, 109, 3, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(129, 129, 3, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(130, 130, 3, 0x0070, 0x10, 12, 1),
PIN_FIELD_BASE(131, 131, 3, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(136, 136, 1, 0x00b0, 0x10, 14, 1),
PIN_FIELD_BASE(137, 137, 1, 0x00b0, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x00b0, 0x10, 16, 1),
PIN_FIELD_BASE(139, 139, 1, 0x00b0, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x00b0, 0x10, 18, 1),
PIN_FIELD_BASE(141, 141, 1, 0x00b0, 0x10, 17, 1),
PIN_FIELD_BASE(142, 142, 1, 0x00b0, 0x10, 20, 1),
PIN_FIELD_BASE(143, 143, 1, 0x00b0, 0x10, 19, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = {
PIN_FIELD_BASE(6, 6, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(18, 18, 2, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x0080, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x0080, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x0080, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x0080, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(97, 97, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 3, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(99, 99, 3, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(100, 100, 3, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(101, 101, 3, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(102, 102, 3, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(103, 103, 3, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(108, 108, 3, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(109, 109, 3, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(129, 129, 3, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(130, 130, 3, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(131, 131, 3, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0090, 0x10, 19, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0050, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0070, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0090, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0090, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0090, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0080, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(1, 1, 4, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(2, 2, 4, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(3, 3, 4, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(4, 4, 4, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(5, 5, 4, 0x000, 0x10, 15, 3),
PINS_FIELD_BASE(6, 7, 4, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(8, 8, 4, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(9, 9, 4, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3),
PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3),
PIN_FIELD_BASE(17, 17, 4, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(18, 18, 2, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(19, 19, 2, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(20, 20, 2, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(21, 21, 2, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(22, 22, 2, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(23, 23, 2, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(24, 24, 2, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(25, 25, 2, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(26, 26, 2, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(27, 27, 2, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(28, 28, 2, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 24, 3),
PINS_FIELD_BASE(31, 33, 1, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(34, 34, 1, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(35, 35, 1, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(36, 36, 1, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(37, 37, 1, 0x010, 0x10, 21, 3),
PINS_FIELD_BASE(38, 39, 1, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(40, 40, 1, 0x010, 0x10, 27, 3),
PIN_FIELD_BASE(41, 41, 1, 0x010, 0x10, 24, 3),
PIN_FIELD_BASE(42, 42, 1, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(43, 43, 1, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(44, 44, 1, 0x030, 0x10, 0, 3),
PIN_FIELD_BASE(45, 45, 1, 0x030, 0x10, 3, 3),
PINS_FIELD_BASE(46, 47, 1, 0x010, 0x10, 3, 3),
PINS_FIELD_BASE(48, 51, 1, 0x010, 0x10, 6, 3),
PINS_FIELD_BASE(52, 55, 1, 0x010, 0x10, 9, 3),
PINS_FIELD_BASE(56, 59, 1, 0x010, 0x10, 12, 3),
PINS_FIELD_BASE(60, 63, 1, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(64, 64, 1, 0x010, 0x10, 18, 3),
PINS_FIELD_BASE(65, 68, 1, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(69, 69, 1, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(70, 70, 1, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(71, 71, 1, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(72, 72, 1, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(73, 73, 1, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(74, 74, 1, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(75, 75, 1, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(76, 76, 1, 0x010, 0x10, 18, 3),
PIN_FIELD_BASE(77, 77, 3, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),
PINS_FIELD_BASE(85, 88, 3, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(89, 89, 3, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(90, 90, 3, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(91, 91, 3, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(92, 92, 3, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(93, 93, 3, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(94, 94, 3, 0x010, 0x10, 9, 3),
PINS_FIELD_BASE(95, 98, 3, 0x010, 0x10, 18, 3),
PINS_FIELD_BASE(99, 102, 3, 0x010, 0x10, 21, 3),
PINS_FIELD_BASE(103, 104, 3, 0x010, 0x10, 24, 3),
PIN_FIELD_BASE(105, 105, 3, 0x010, 0x10, 27, 3),
PINS_FIELD_BASE(106, 107, 3, 0x010, 0x10, 24, 3),
PINS_FIELD_BASE(108, 109, 3, 0x010, 0x10, 27, 3),
PIN_FIELD_BASE(110, 110, 5, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(111, 111, 5, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(112, 112, 5, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(113, 113, 5, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(114, 114, 5, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(115, 115, 5, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(116, 116, 6, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(117, 117, 6, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(118, 118, 6, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(119, 119, 6, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(120, 120, 6, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(121, 121, 6, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(122, 122, 6, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(123, 123, 6, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(124, 124, 6, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(125, 125, 6, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(126, 126, 6, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(127, 127, 6, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(128, 128, 3, 0x010, 0x10, 27, 3),
PINS_FIELD_BASE(129, 130, 3, 0x020, 0x10, 0, 3),
PINS_FIELD_BASE(131, 131, 3, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(132, 132, 6, 0x010, 0x10, 9, 3),
PIN_FIELD_BASE(133, 133, 6, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(134, 134, 6, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(135, 135, 6, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(136, 136, 1, 0x020, 0x10, 9, 3),
PIN_FIELD_BASE(137, 137, 1, 0x020, 0x10, 6, 3),
PIN_FIELD_BASE(138, 138, 1, 0x020, 0x10, 15, 3),
PIN_FIELD_BASE(139, 139, 1, 0x020, 0x10, 12, 3),
PIN_FIELD_BASE(140, 140, 1, 0x020, 0x10, 21, 3),
PIN_FIELD_BASE(141, 141, 1, 0x020, 0x10, 18, 3),
PIN_FIELD_BASE(142, 142, 1, 0x020, 0x10, 27, 3),
PIN_FIELD_BASE(143, 143, 1, 0x020, 0x10, 24, 3),
};
static const struct mtk_pin_field_calc mt8195_pin_drv_adv_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x020, 0x10, 15, 3),
PIN_FIELD_BASE(9, 9, 4, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(10, 10, 4, 0x020, 0x10, 18, 3),
PIN_FIELD_BASE(11, 11, 4, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(12, 12, 4, 0x020, 0x10, 21, 3),
PIN_FIELD_BASE(13, 13, 4, 0x020, 0x10, 6, 3),
PIN_FIELD_BASE(14, 14, 4, 0x020, 0x10, 24, 3),
PIN_FIELD_BASE(15, 15, 4, 0x020, 0x10, 9, 3),
PIN_FIELD_BASE(16, 16, 4, 0x020, 0x10, 27, 3),
PIN_FIELD_BASE(17, 17, 4, 0x020, 0x10, 12, 3),
PIN_FIELD_BASE(29, 29, 2, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(30, 30, 2, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(34, 34, 1, 0x040, 0x10, 0, 3),
PIN_FIELD_BASE(35, 35, 1, 0x040, 0x10, 3, 3),
PIN_FIELD_BASE(44, 44, 1, 0x040, 0x10, 6, 3),
PIN_FIELD_BASE(45, 45, 1, 0x040, 0x10, 9, 3),
};
static const struct mtk_pin_field_calc mt8195_pin_rsel_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x0c0, 0x10, 15, 3),
PIN_FIELD_BASE(9, 9, 4, 0x0c0, 0x10, 0, 3),
PIN_FIELD_BASE(10, 10, 4, 0x0c0, 0x10, 18, 3),
PIN_FIELD_BASE(11, 11, 4, 0x0c0, 0x10, 3, 3),
PIN_FIELD_BASE(12, 12, 4, 0x0c0, 0x10, 21, 3),
PIN_FIELD_BASE(13, 13, 4, 0x0c0, 0x10, 6, 3),
PIN_FIELD_BASE(14, 14, 4, 0x0c0, 0x10, 24, 3),
PIN_FIELD_BASE(15, 15, 4, 0x0c0, 0x10, 9, 3),
PIN_FIELD_BASE(16, 16, 4, 0x0c0, 0x10, 27, 3),
PIN_FIELD_BASE(17, 17, 4, 0x0c0, 0x10, 12, 3),
PIN_FIELD_BASE(29, 29, 2, 0x080, 0x10, 0, 3),
PIN_FIELD_BASE(30, 30, 2, 0x080, 0x10, 3, 3),
PIN_FIELD_BASE(34, 34, 1, 0x0e0, 0x10, 0, 3),
PIN_FIELD_BASE(35, 35, 1, 0x0e0, 0x10, 3, 3),
PIN_FIELD_BASE(44, 44, 1, 0x0e0, 0x10, 6, 3),
PIN_FIELD_BASE(45, 45, 1, 0x0e0, 0x10, 9, 3),
};
static const struct mtk_pin_rsel mt8195_pin_rsel_val_range[] = {
PIN_RSEL(8, 17, 0x0, 75000, 75000),
PIN_RSEL(8, 17, 0x1, 10000, 5000),
PIN_RSEL(8, 17, 0x2, 5000, 75000),
PIN_RSEL(8, 17, 0x3, 4000, 5000),
PIN_RSEL(8, 17, 0x4, 3000, 75000),
PIN_RSEL(8, 17, 0x5, 2000, 5000),
PIN_RSEL(8, 17, 0x6, 1500, 75000),
PIN_RSEL(8, 17, 0x7, 1000, 5000),
PIN_RSEL(29, 30, 0x0, 75000, 75000),
PIN_RSEL(29, 30, 0x1, 10000, 5000),
PIN_RSEL(29, 30, 0x2, 5000, 75000),
PIN_RSEL(29, 30, 0x3, 4000, 5000),
PIN_RSEL(29, 30, 0x4, 3000, 75000),
PIN_RSEL(29, 30, 0x5, 2000, 5000),
PIN_RSEL(29, 30, 0x6, 1500, 75000),
PIN_RSEL(29, 30, 0x7, 1000, 5000),
PIN_RSEL(34, 35, 0x0, 75000, 75000),
PIN_RSEL(34, 35, 0x1, 10000, 5000),
PIN_RSEL(34, 35, 0x2, 5000, 75000),
PIN_RSEL(34, 35, 0x3, 4000, 5000),
PIN_RSEL(34, 35, 0x4, 3000, 75000),
PIN_RSEL(34, 35, 0x5, 2000, 5000),
PIN_RSEL(34, 35, 0x6, 1500, 75000),
PIN_RSEL(34, 35, 0x7, 1000, 5000),
PIN_RSEL(44, 45, 0x0, 75000, 75000),
PIN_RSEL(44, 45, 0x1, 10000, 5000),
PIN_RSEL(44, 45, 0x2, 5000, 75000),
PIN_RSEL(44, 45, 0x3, 4000, 5000),
PIN_RSEL(44, 45, 0x4, 3000, 75000),
PIN_RSEL(44, 45, 0x5, 2000, 5000),
PIN_RSEL(44, 45, 0x6, 1500, 75000),
PIN_RSEL(44, 45, 0x7, 1000, 5000),
};
static const unsigned int mt8195_pull_type[] = {
MTK_PULL_PUPD_R1R0_TYPE /* 0 */, MTK_PULL_PUPD_R1R0_TYPE /* 1 */,
MTK_PULL_PUPD_R1R0_TYPE /* 2 */, MTK_PULL_PUPD_R1R0_TYPE /* 3 */,
MTK_PULL_PUPD_R1R0_TYPE /* 4 */, MTK_PULL_PUPD_R1R0_TYPE /* 5 */,
MTK_PULL_PU_PD_TYPE /* 6 */, MTK_PULL_PU_PD_TYPE /* 7 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 8 */, MTK_PULL_PU_PD_RSEL_TYPE /* 9 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 10 */, MTK_PULL_PU_PD_RSEL_TYPE /* 11 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 12 */, MTK_PULL_PU_PD_RSEL_TYPE /* 13 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 14 */, MTK_PULL_PU_PD_RSEL_TYPE /* 15 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 16 */, MTK_PULL_PU_PD_RSEL_TYPE /* 17 */,
MTK_PULL_PU_PD_TYPE /* 18 */, MTK_PULL_PU_PD_TYPE /* 19 */,
MTK_PULL_PU_PD_TYPE /* 20 */, MTK_PULL_PU_PD_TYPE /* 21 */,
MTK_PULL_PU_PD_TYPE /* 22 */, MTK_PULL_PU_PD_TYPE /* 23 */,
MTK_PULL_PU_PD_TYPE /* 24 */, MTK_PULL_PU_PD_TYPE /* 25 */,
MTK_PULL_PU_PD_TYPE /* 26 */, MTK_PULL_PU_PD_TYPE /* 27 */,
MTK_PULL_PU_PD_TYPE /* 28 */, MTK_PULL_PU_PD_RSEL_TYPE /* 29 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 30 */, MTK_PULL_PU_PD_TYPE /* 31 */,
MTK_PULL_PU_PD_TYPE /* 32 */, MTK_PULL_PU_PD_TYPE /* 33 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 34 */, MTK_PULL_PU_PD_RSEL_TYPE /* 35 */,
MTK_PULL_PU_PD_TYPE /* 36 */, MTK_PULL_PU_PD_TYPE /* 37 */,
MTK_PULL_PU_PD_TYPE /* 38 */, MTK_PULL_PU_PD_TYPE /* 39 */,
MTK_PULL_PU_PD_TYPE /* 40 */, MTK_PULL_PU_PD_TYPE /* 41 */,
MTK_PULL_PU_PD_TYPE /* 42 */, MTK_PULL_PU_PD_TYPE /* 43 */,
MTK_PULL_PU_PD_RSEL_TYPE /* 44 */, MTK_PULL_PU_PD_RSEL_TYPE /* 45 */,
MTK_PULL_PU_PD_TYPE /* 46 */, MTK_PULL_PU_PD_TYPE /* 47 */,
MTK_PULL_PU_PD_TYPE /* 48 */, MTK_PULL_PU_PD_TYPE /* 49 */,
MTK_PULL_PU_PD_TYPE /* 50 */, MTK_PULL_PU_PD_TYPE /* 51 */,
MTK_PULL_PU_PD_TYPE /* 52 */, MTK_PULL_PU_PD_TYPE /* 53 */,
MTK_PULL_PU_PD_TYPE /* 54 */, MTK_PULL_PU_PD_TYPE /* 55 */,
MTK_PULL_PU_PD_TYPE /* 56 */, MTK_PULL_PU_PD_TYPE /* 57 */,
MTK_PULL_PU_PD_TYPE /* 58 */, MTK_PULL_PU_PD_TYPE /* 59 */,
MTK_PULL_PU_PD_TYPE /* 60 */, MTK_PULL_PU_PD_TYPE /* 61 */,
MTK_PULL_PU_PD_TYPE /* 62 */, MTK_PULL_PU_PD_TYPE /* 63 */,
MTK_PULL_PU_PD_TYPE /* 64 */, MTK_PULL_PU_PD_TYPE /* 65 */,
MTK_PULL_PU_PD_TYPE /* 66 */, MTK_PULL_PU_PD_TYPE /* 67 */,
MTK_PULL_PU_PD_TYPE /* 68 */, MTK_PULL_PU_PD_TYPE /* 69 */,
MTK_PULL_PU_PD_TYPE /* 70 */, MTK_PULL_PU_PD_TYPE /* 71 */,
MTK_PULL_PU_PD_TYPE /* 72 */, MTK_PULL_PU_PD_TYPE /* 73 */,
MTK_PULL_PU_PD_TYPE /* 74 */, MTK_PULL_PU_PD_TYPE /* 75 */,
MTK_PULL_PU_PD_TYPE /* 76 */, MTK_PULL_PUPD_R1R0_TYPE /* 77 */,
MTK_PULL_PUPD_R1R0_TYPE /* 78 */, MTK_PULL_PUPD_R1R0_TYPE /* 79 */,
MTK_PULL_PUPD_R1R0_TYPE /* 80 */, MTK_PULL_PUPD_R1R0_TYPE /* 81 */,
MTK_PULL_PUPD_R1R0_TYPE /* 82 */, MTK_PULL_PUPD_R1R0_TYPE /* 83 */,
MTK_PULL_PUPD_R1R0_TYPE /* 84 */, MTK_PULL_PUPD_R1R0_TYPE /* 85 */,
MTK_PULL_PUPD_R1R0_TYPE /* 86 */, MTK_PULL_PUPD_R1R0_TYPE /* 87 */,
MTK_PULL_PUPD_R1R0_TYPE /* 88 */, MTK_PULL_PUPD_R1R0_TYPE /* 89 */,
MTK_PULL_PUPD_R1R0_TYPE /* 90 */, MTK_PULL_PUPD_R1R0_TYPE /* 91 */,
MTK_PULL_PUPD_R1R0_TYPE /* 92 */, MTK_PULL_PUPD_R1R0_TYPE /* 93 */,
MTK_PULL_PUPD_R1R0_TYPE /* 94 */, MTK_PULL_PUPD_R1R0_TYPE /* 95 */,
MTK_PULL_PUPD_R1R0_TYPE /* 96 */, MTK_PULL_PU_PD_TYPE /* 97 */,
MTK_PULL_PU_PD_TYPE /* 98 */, MTK_PULL_PU_PD_TYPE /* 99 */,
MTK_PULL_PU_PD_TYPE /* 100 */, MTK_PULL_PU_PD_TYPE /* 101 */,
MTK_PULL_PU_PD_TYPE /* 102 */, MTK_PULL_PU_PD_TYPE /* 103 */,
MTK_PULL_PUPD_R1R0_TYPE /* 104 */, MTK_PULL_PUPD_R1R0_TYPE /* 105 */,
MTK_PULL_PUPD_R1R0_TYPE /* 106 */, MTK_PULL_PUPD_R1R0_TYPE /* 107 */,
MTK_PULL_PU_PD_TYPE /* 108 */, MTK_PULL_PU_PD_TYPE /* 109 */,
MTK_PULL_PUPD_R1R0_TYPE /* 110 */, MTK_PULL_PUPD_R1R0_TYPE /* 111 */,
MTK_PULL_PUPD_R1R0_TYPE /* 112 */, MTK_PULL_PUPD_R1R0_TYPE /* 113 */,
MTK_PULL_PUPD_R1R0_TYPE /* 114 */, MTK_PULL_PUPD_R1R0_TYPE /* 115 */,
MTK_PULL_PUPD_R1R0_TYPE /* 116 */, MTK_PULL_PUPD_R1R0_TYPE /* 117 */,
MTK_PULL_PUPD_R1R0_TYPE /* 118 */, MTK_PULL_PUPD_R1R0_TYPE /* 119 */,
MTK_PULL_PUPD_R1R0_TYPE /* 120 */, MTK_PULL_PUPD_R1R0_TYPE /* 121 */,
MTK_PULL_PUPD_R1R0_TYPE /* 122 */, MTK_PULL_PUPD_R1R0_TYPE /* 123 */,
MTK_PULL_PUPD_R1R0_TYPE /* 124 */, MTK_PULL_PUPD_R1R0_TYPE /* 125 */,
MTK_PULL_PUPD_R1R0_TYPE /* 126 */, MTK_PULL_PUPD_R1R0_TYPE /* 127 */,
MTK_PULL_PU_PD_TYPE /* 128 */, MTK_PULL_PU_PD_TYPE /* 129 */,
MTK_PULL_PU_PD_TYPE /* 130 */, MTK_PULL_PU_PD_TYPE /* 131 */,
MTK_PULL_PU_PD_TYPE /* 132 */, MTK_PULL_PU_PD_TYPE /* 133 */,
MTK_PULL_PU_PD_TYPE /* 134 */, MTK_PULL_PU_PD_TYPE /* 135 */,
MTK_PULL_PU_PD_TYPE /* 136 */, MTK_PULL_PU_PD_TYPE /* 137 */,
MTK_PULL_PU_PD_TYPE /* 138 */, MTK_PULL_PU_PD_TYPE /* 139 */,
MTK_PULL_PU_PD_TYPE /* 140 */, MTK_PULL_PU_PD_TYPE /* 141 */,
MTK_PULL_PU_PD_TYPE /* 142 */, MTK_PULL_PU_PD_TYPE /* 143 */,
};
static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range),
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8195_pin_drv_adv_range),
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8195_pin_rsel_range),
};
static const char * const mt8195_pinctrl_register_base_names[] = {
"iocfg0", "iocfg_bm", "iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_rb", "iocfg_tl",
};
static const struct mtk_eint_hw mt8195_eint_hw = {
.port_mask = 0xf,
.ports = 7,
.ap_num = 225,
.db_cnt = 32,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt8195_data = {
.reg_cal = mt8195_reg_cals,
.pins = mtk_pins_mt8195,
.npins = ARRAY_SIZE(mtk_pins_mt8195),
.ngrps = ARRAY_SIZE(mtk_pins_mt8195),
.eint_hw = &mt8195_eint_hw,
.nfuncs = 8,
.gpio_m = 0,
.base_names = mt8195_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names),
.pull_type = mt8195_pull_type,
.pin_rsel = mt8195_pin_rsel_val_range,
.npin_rsel = ARRAY_SIZE(mt8195_pin_rsel_val_range),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
};
static const struct of_device_id mt8195_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data },
{ }
};
static struct platform_driver mt8195_pinctrl_driver = {
.driver = {
.name = "mt8195-pinctrl",
.of_match_table = mt8195_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8195_pinctrl_init(void)
{
return platform_driver_register(&mt8195_pinctrl_driver);
}
arch_initcall(mt8195_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8195.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* The MT7981 driver based on Linux generic pinctrl binding.
*
* Copyright (C) 2020 MediaTek Inc.
* Author: Sam Shih <[email protected]>
*/
#include "pinctrl-moore.h"
#define MT7981_PIN(_number, _name) \
MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 0)
#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 1)
static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
};
static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
};
static const unsigned int mt7981_pull_type[] = {
MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
MTK_PULL_PU_PD_TYPE,/*56*/
};
static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
};
static const struct mtk_pin_desc mt7981_pins[] = {
MT7981_PIN(0, "GPIO_WPS"),
MT7981_PIN(1, "GPIO_RESET"),
MT7981_PIN(2, "SYS_WATCHDOG"),
MT7981_PIN(3, "PCIE_PERESET_N"),
MT7981_PIN(4, "JTAG_JTDO"),
MT7981_PIN(5, "JTAG_JTDI"),
MT7981_PIN(6, "JTAG_JTMS"),
MT7981_PIN(7, "JTAG_JTCLK"),
MT7981_PIN(8, "JTAG_JTRST_N"),
MT7981_PIN(9, "WO_JTAG_JTDO"),
MT7981_PIN(10, "WO_JTAG_JTDI"),
MT7981_PIN(11, "WO_JTAG_JTMS"),
MT7981_PIN(12, "WO_JTAG_JTCLK"),
MT7981_PIN(13, "WO_JTAG_JTRST_N"),
MT7981_PIN(14, "USB_VBUS"),
MT7981_PIN(15, "PWM0"),
MT7981_PIN(16, "SPI0_CLK"),
MT7981_PIN(17, "SPI0_MOSI"),
MT7981_PIN(18, "SPI0_MISO"),
MT7981_PIN(19, "SPI0_CS"),
MT7981_PIN(20, "SPI0_HOLD"),
MT7981_PIN(21, "SPI0_WP"),
MT7981_PIN(22, "SPI1_CLK"),
MT7981_PIN(23, "SPI1_MOSI"),
MT7981_PIN(24, "SPI1_MISO"),
MT7981_PIN(25, "SPI1_CS"),
MT7981_PIN(26, "SPI2_CLK"),
MT7981_PIN(27, "SPI2_MOSI"),
MT7981_PIN(28, "SPI2_MISO"),
MT7981_PIN(29, "SPI2_CS"),
MT7981_PIN(30, "SPI2_HOLD"),
MT7981_PIN(31, "SPI2_WP"),
MT7981_PIN(32, "UART0_RXD"),
MT7981_PIN(33, "UART0_TXD"),
MT7981_PIN(34, "PCIE_CLK_REQ"),
MT7981_PIN(35, "PCIE_WAKE_N"),
MT7981_PIN(36, "SMI_MDC"),
MT7981_PIN(37, "SMI_MDIO"),
MT7981_PIN(38, "GBE_INT"),
MT7981_PIN(39, "GBE_RESET"),
MT7981_PIN(40, "WF_DIG_RESETB"),
MT7981_PIN(41, "WF_CBA_RESETB"),
MT7981_PIN(42, "WF_XO_REQ"),
MT7981_PIN(43, "WF_TOP_CLK"),
MT7981_PIN(44, "WF_TOP_DATA"),
MT7981_PIN(45, "WF_HB1"),
MT7981_PIN(46, "WF_HB2"),
MT7981_PIN(47, "WF_HB3"),
MT7981_PIN(48, "WF_HB4"),
MT7981_PIN(49, "WF_HB0"),
MT7981_PIN(50, "WF_HB0_B"),
MT7981_PIN(51, "WF_HB5"),
MT7981_PIN(52, "WF_HB6"),
MT7981_PIN(53, "WF_HB7"),
MT7981_PIN(54, "WF_HB8"),
MT7981_PIN(55, "WF_HB9"),
MT7981_PIN(56, "WF_HB10"),
};
/* List all groups consisting of these pins dedicated to the enablement of
* certain hardware block and the corresponding mode for all of the pins.
* The hardware probably has multiple combinations of these pinouts.
*/
/* WA_AICE */
static int mt7981_wa_aice1_pins[] = { 0, 1, };
static int mt7981_wa_aice1_funcs[] = { 2, 2, };
static int mt7981_wa_aice2_pins[] = { 0, 1, };
static int mt7981_wa_aice2_funcs[] = { 3, 3, };
static int mt7981_wa_aice3_pins[] = { 28, 29, };
static int mt7981_wa_aice3_funcs[] = { 3, 3, };
static int mt7981_wm_aice1_pins[] = { 9, 10, };
static int mt7981_wm_aice1_funcs[] = { 2, 2, };
static int mt7981_wm_aice2_pins[] = { 30, 31, };
static int mt7981_wm_aice2_funcs[] = { 5, 5, };
/* WM_UART */
static int mt7981_wm_uart_0_pins[] = { 0, 1, };
static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
static int mt7981_wm_uart_1_pins[] = { 20, 21, };
static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
static int mt7981_wm_uart_2_pins[] = { 30, 31, };
static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
/* DFD */
static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
/* SYS_WATCHDOG */
static int mt7981_watchdog_pins[] = { 2, };
static int mt7981_watchdog_funcs[] = { 1, };
static int mt7981_watchdog1_pins[] = { 13, };
static int mt7981_watchdog1_funcs[] = { 5, };
/* PCIE_PERESET_N */
static int mt7981_pcie_pereset_pins[] = { 3, };
static int mt7981_pcie_pereset_funcs[] = { 1, };
/* JTAG */
static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
/* WM_JTAG */
static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
/* WO0_JTAG */
static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
/* UART2 */
static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
/* GBE_LED0 */
static int mt7981_gbe_led0_pins[] = { 8, };
static int mt7981_gbe_led0_funcs[] = { 3, };
/* PTA_EXT */
static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
/* PWM2 */
static int mt7981_pwm2_pins[] = { 7, };
static int mt7981_pwm2_funcs[] = { 4, };
/* NET_WO0_UART_TXD */
static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
/* SPI1 */
static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
/* I2C */
static int mt7981_i2c0_0_pins[] = { 6, 7, };
static int mt7981_i2c0_0_funcs[] = { 6, 6, };
static int mt7981_i2c0_1_pins[] = { 30, 31, };
static int mt7981_i2c0_1_funcs[] = { 4, 4, };
static int mt7981_i2c0_2_pins[] = { 36, 37, };
static int mt7981_i2c0_2_funcs[] = { 2, 2, };
static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
/* DFD_NTRST */
static int mt7981_dfd_ntrst_pins[] = { 8, };
static int mt7981_dfd_ntrst_funcs[] = { 6, };
/* PWM0 */
static int mt7981_pwm0_0_pins[] = { 13, };
static int mt7981_pwm0_0_funcs[] = { 2, };
static int mt7981_pwm0_1_pins[] = { 15, };
static int mt7981_pwm0_1_funcs[] = { 1, };
/* PWM1 */
static int mt7981_pwm1_0_pins[] = { 14, };
static int mt7981_pwm1_0_funcs[] = { 2, };
static int mt7981_pwm1_1_pins[] = { 15, };
static int mt7981_pwm1_1_funcs[] = { 3, };
/* GBE_LED1 */
static int mt7981_gbe_led1_pins[] = { 13, };
static int mt7981_gbe_led1_funcs[] = { 3, };
/* PCM */
static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
/* UDI */
static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
/* DRV_VBUS */
static int mt7981_drv_vbus_pins[] = { 14, };
static int mt7981_drv_vbus_funcs[] = { 1, };
/* EMMC */
static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
/* SNFI */
static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
/* SPI0 */
static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
/* SPI0 */
static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
/* SPI1 */
static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
/* SPI2 */
static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
/* SPI2 */
static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
/* UART1 */
static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
/* UART2 */
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
/* UART0 */
static int mt7981_uart0_pins[] = { 32, 33, };
static int mt7981_uart0_funcs[] = { 1, 1, };
/* PCIE_CLK_REQ */
static int mt7981_pcie_clk_pins[] = { 34, };
static int mt7981_pcie_clk_funcs[] = { 2, };
/* PCIE_WAKE_N */
static int mt7981_pcie_wake_pins[] = { 35, };
static int mt7981_pcie_wake_funcs[] = { 2, };
/* MDC_MDIO */
static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
/* WF0_MODE1 */
static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
/* WF0_MODE3 */
static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
/* WF2G_LED */
static int mt7981_wf2g_led0_pins[] = { 30, };
static int mt7981_wf2g_led0_funcs[] = { 2, };
static int mt7981_wf2g_led1_pins[] = { 34, };
static int mt7981_wf2g_led1_funcs[] = { 1, };
/* WF5G_LED */
static int mt7981_wf5g_led0_pins[] = { 31, };
static int mt7981_wf5g_led0_funcs[] = { 2, };
static int mt7981_wf5g_led1_pins[] = { 35, };
static int mt7981_wf5g_led1_funcs[] = { 1, };
/* MT7531_INT */
static int mt7981_mt7531_int_pins[] = { 38, };
static int mt7981_mt7531_int_funcs[] = { 1, };
/* ANT_SEL */
static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
static const struct group_desc mt7981_groups[] = {
/* @GPIO(0,1): WA_AICE(2) */
PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
/* @GPIO(0,1): WA_AICE(3) */
PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
/* @GPIO(0,1): WM_UART(5) */
PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
/* @GPIO(0,1,4,5): DFD(6) */
PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
/* @GPIO(2): SYS_WATCHDOG(1) */
PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
/* @GPIO(3): PCIE_PERESET_N(1) */
PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
/* @GPIO(4,8) JTAG(1) */
PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
/* @GPIO(4,8) WM_JTAG(2) */
PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
/* @GPIO(9,13) WO0_JTAG(1) */
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
/* @GPIO(4,7) WM_JTAG(3) */
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
/* @GPIO(8) GBE_LED0(3) */
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
/* @GPIO(4,6) PTA_EXT(4) */
PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
/* @GPIO(7) PWM2(4) */
PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
/* @GPIO(8) NET_WO0_UART_TXD(4) */
PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
/* @GPIO(4,7) SPI1(5) */
PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
/* @GPIO(6,7) I2C(5) */
PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
/* @GPIO(0,1,4,5): DFD_NTRST(6) */
PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
/* @GPIO(9,10): WM_AICE(2) */
PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
/* @GPIO(13): PWM0(2) */
PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
/* @GPIO(15): PWM0(1) */
PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
/* @GPIO(14): PWM1(2) */
PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
/* @GPIO(15): PWM1(3) */
PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
/* @GPIO(14) NET_WO0_UART_TXD(3) */
PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
/* @GPIO(15) NET_WO0_UART_TXD(4) */
PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
/* @GPIO(13) GBE_LED0(3) */
PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
/* @GPIO(9,13) PCM(4) */
PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
/* @GPIO(13): SYS_WATCHDOG1(5) */
PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
/* @GPIO(9,13) UDI(4) */
PINCTRL_PIN_GROUP("udi", mt7981_udi),
/* @GPIO(14) DRV_VBUS(1) */
PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
/* @GPIO(15,25): EMMC(2) */
PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
/* @GPIO(16,21): SNFI(3) */
PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
/* @GPIO(16,19): SPI0(1) */
PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
/* @GPIO(20,21): SPI0(1) */
PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
/* @GPIO(22,25) SPI1(1) */
PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
/* @GPIO(26,29): SPI2(1) */
PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
/* @GPIO(30,31): SPI0(1) */
PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
/* @GPIO(16,19): UART1(4) */
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
/* @GPIO(26,29): UART1(2) */
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
/* @GPIO(22,25): UART1(3) */
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
/* @GPIO(22,24) PTA_EXT(4) */
PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
/* @GPIO(20,21): WM_UART(4) */
PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
/* @GPIO(30,31): WM_UART(3) */
PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
/* @GPIO(20,24) WM_JTAG(5) */
PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
/* @GPIO(25,29) WO0_JTAG(5) */
PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
/* @GPIO(28,29): WA_AICE(3) */
PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
/* @GPIO(30,31): WM_AICE(5) */
PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
/* @GPIO(30,31): I2C(4) */
PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
/* @GPIO(30,31): I2C(6) */
PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
/* @GPIO(32,33): I2C(1) */
PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
/* @GPIO(32,33): I2C(2) */
PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
/* @GPIO(32,33): I2C(3) */
PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
/* @GPIO(32,33): I2C(5) */
PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
/* @GPIO(34): PCIE_CLK_REQ(2) */
PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
/* @GPIO(35): PCIE_WAKE_N(2) */
PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
/* @GPIO(36,37): I2C(2) */
PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
/* @GPIO(36,37): MDC_MDIO(1) */
PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
/* @GPIO(36,37): MDC_MDIO(3) */
PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
/* @GPIO(69,85): WF0_MODE1(1) */
PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
/* @GPIO(74,80): WF0_MODE3(3) */
PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
/* @GPIO(30): WF2G_LED(2) */
PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
/* @GPIO(34): WF2G_LED(1) */
PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
/* @GPIO(31): WF5G_LED(2) */
PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
/* @GPIO(35): WF5G_LED(1) */
PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
/* @GPIO(38): MT7531_INT(1) */
PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
};
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
"wa_aice3", "wm_aice1_2", };
static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
"wo0_jtag_1", "wm_jtag_1", };
static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
"wf2g_led1", "wf5g_led0", "wf5g_led1", };
static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
"pwm1_0", "pwm1_1", };
static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
"spi2_wp_hold", };
static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
static const char *mt7981_pcm_groups[] = { "pcm", };
static const char *mt7981_udi_groups[] = { "udi", };
static const char *mt7981_usb_groups[] = { "drv_vbus", };
static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
"wf0_mode1", "wf0_mode3", "mt7531_int", };
static const char *mt7981_ant_groups[] = { "ant_sel", };
static const struct function_desc mt7981_functions[] = {
{"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
{"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
{"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
{"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
{"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
{"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
};
static const struct mtk_eint_hw mt7981_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = ARRAY_SIZE(mt7981_pins),
.db_cnt = 16,
};
static const char * const mt7981_pinctrl_register_base_names[] = {
"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
};
static struct mtk_pin_soc mt7981_data = {
.reg_cal = mt7981_reg_cals,
.pins = mt7981_pins,
.npins = ARRAY_SIZE(mt7981_pins),
.grps = mt7981_groups,
.ngrps = ARRAY_SIZE(mt7981_groups),
.funcs = mt7981_functions,
.nfuncs = ARRAY_SIZE(mt7981_functions),
.eint_hw = &mt7981_eint_hw,
.gpio_m = 0,
.ies_present = false,
.base_names = mt7981_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
.bias_disable_get = mtk_pinconf_bias_disable_get,
.bias_set = mtk_pinconf_bias_set,
.bias_get = mtk_pinconf_bias_get,
.pull_type = mt7981_pull_type,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt7981_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt7981-pinctrl", },
{}
};
static int mt7981_pinctrl_probe(struct platform_device *pdev)
{
return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
}
static struct platform_driver mt7981_pinctrl_driver = {
.driver = {
.name = "mt7981-pinctrl",
.of_match_table = mt7981_pinctrl_of_match,
},
.probe = mt7981_pinctrl_probe,
};
static int __init mt7981_pinctrl_init(void)
{
return platform_driver_register(&mt7981_pinctrl_driver);
}
arch_initcall(mt7981_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Sean Wang <[email protected]>
*
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include "mtk-eint.h"
#include "pinctrl-mtk-common-v2.h"
/**
* struct mtk_drive_desc - the structure that holds the information
* of the driving current
* @min: the minimum current of this group
* @max: the maximum current of this group
* @step: the step current of this group
* @scal: the weight factor
*
* formula: output = ((input) / step - 1) * scal
*/
struct mtk_drive_desc {
u8 min;
u8 max;
u8 step;
u8 scal;
};
/* The groups of drive strength */
static const struct mtk_drive_desc mtk_drive[] = {
[DRV_GRP0] = { 4, 16, 4, 1 },
[DRV_GRP1] = { 4, 16, 4, 2 },
[DRV_GRP2] = { 2, 8, 2, 1 },
[DRV_GRP3] = { 2, 8, 2, 2 },
[DRV_GRP4] = { 2, 16, 2, 1 },
};
static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
{
writel_relaxed(val, pctl->base[i] + reg);
}
static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
{
return readl_relaxed(pctl->base[i] + reg);
}
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&pctl->lock, flags);
val = mtk_r32(pctl, i, reg);
val &= ~mask;
val |= set;
mtk_w32(pctl, i, reg, val);
spin_unlock_irqrestore(&pctl->lock, flags);
}
static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
int field, struct mtk_pin_field *pfd)
{
const struct mtk_pin_field_calc *c;
const struct mtk_pin_reg_calc *rc;
int start = 0, end, check;
bool found = false;
u32 bits;
if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
rc = &hw->soc->reg_cal[field];
} else {
dev_dbg(hw->dev,
"Not support field %d for this soc\n", field);
return -ENOTSUPP;
}
end = rc->nranges - 1;
while (start <= end) {
check = (start + end) >> 1;
if (desc->number >= rc->range[check].s_pin
&& desc->number <= rc->range[check].e_pin) {
found = true;
break;
} else if (start == end)
break;
else if (desc->number < rc->range[check].s_pin)
end = check - 1;
else
start = check + 1;
}
if (!found) {
dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
field, desc->number, desc->name);
return -ENOTSUPP;
}
c = rc->range + check;
if (c->i_base > hw->nbase - 1) {
dev_err(hw->dev,
"Invalid base for field %d for pin = %d (%s)\n",
field, desc->number, desc->name);
return -EINVAL;
}
/* Calculated bits as the overall offset the pin is located at,
* if c->fixed is held, that determines the all the pins in the
* range use the same field with the s_pin.
*/
bits = c->fixed ? c->s_bit : c->s_bit +
(desc->number - c->s_pin) * (c->x_bits);
/* Fill pfd from bits. For example 32-bit register applied is assumed
* when c->sz_reg is equal to 32.
*/
pfd->index = c->i_base;
pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
pfd->bitpos = bits % c->sz_reg;
pfd->mask = (1 << c->x_bits) - 1;
/* pfd->next is used for indicating that bit wrapping-around happens
* which requires the manipulation for bit 0 starting in the next
* register to form the complete field read/write.
*/
pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
return 0;
}
static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
int field, struct mtk_pin_field *pfd)
{
if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
dev_err(hw->dev, "Invalid Field %d\n", field);
return -EINVAL;
}
return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
}
static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
{
*l = 32 - pf->bitpos;
*h = get_count_order(pf->mask) - *l;
}
static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
struct mtk_pin_field *pf, int value)
{
int nbits_l, nbits_h;
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
(value & pf->mask) << pf->bitpos);
mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
(value & pf->mask) >> nbits_l);
}
static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
struct mtk_pin_field *pf, int *value)
{
int nbits_l, nbits_h, h, l;
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
l = (mtk_r32(hw, pf->index, pf->offset)
>> pf->bitpos) & (BIT(nbits_l) - 1);
h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
& (BIT(nbits_h) - 1);
*value = (h << nbits_l) | l;
}
int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int value)
{
struct mtk_pin_field pf;
int err;
err = mtk_hw_pin_field_get(hw, desc, field, &pf);
if (err)
return err;
if (value < 0 || value > pf.mask)
return -EINVAL;
if (!pf.next)
mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
(value & pf.mask) << pf.bitpos);
else
mtk_hw_write_cross_field(hw, &pf, value);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_hw_set_value);
int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
int field, int *value)
{
struct mtk_pin_field pf;
int err;
err = mtk_hw_pin_field_get(hw, desc, field, &pf);
if (err)
return err;
if (!pf.next)
*value = (mtk_r32(hw, pf.index, pf.offset)
>> pf.bitpos) & pf.mask;
else
mtk_hw_read_cross_field(hw, &pf, value);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_hw_get_value);
static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
{
const struct mtk_pin_desc *desc;
int i = 0;
desc = (const struct mtk_pin_desc *)hw->soc->pins;
while (i < hw->soc->npins) {
if (desc[i].eint.eint_n == eint_n)
return desc[i].number;
i++;
}
return EINT_NA;
}
/*
* Virtual GPIO only used inside SOC and not being exported to outside SOC.
* Some modules use virtual GPIO as eint (e.g. pmif or usb).
* In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
* and we can set GPIO as eint.
* But some modules use specific eint which doesn't have real GPIO pin.
* So we use virtual GPIO to map it.
*/
bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
{
const struct mtk_pin_desc *desc;
bool virt_gpio = false;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
/* if the GPIO is not supported for eint mode */
if (desc->eint.eint_m == NO_EINT_SUPPORT)
return virt_gpio;
if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
virt_gpio = true;
return virt_gpio;
}
EXPORT_SYMBOL_GPL(mtk_is_virt_gpio);
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)hw->soc->pins;
*gpio_chip = &hw->chip;
/*
* Be greedy to guess first gpio_n is equal to eint_n.
* Only eint virtual eint number is greater than gpio number.
*/
if (hw->soc->npins > eint_n &&
desc[eint_n].eint.eint_n == eint_n)
*gpio_n = eint_n;
else
*gpio_n = mtk_xt_find_eint_num(hw, eint_n);
return *gpio_n == EINT_NA ? -EINVAL : 0;
}
static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
struct gpio_chip *gpio_chip;
unsigned int gpio_n;
int value, err;
err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
if (err)
return err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
{
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
const struct mtk_pin_desc *desc;
struct gpio_chip *gpio_chip;
unsigned int gpio_n;
int err;
err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
if (err)
return err;
if (mtk_is_virt_gpio(hw, gpio_n))
return 0;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
desc->eint.eint_m);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
/* SMT is supposed to be supported by every real GPIO and doesn't
* support virtual GPIOs, so the extra condition err != -ENOTSUPP
* is just for adding EINT support to these virtual GPIOs. It should
* add an extra flag in the pin descriptor when more pins with
* distinctive characteristic come out.
*/
if (err && err != -ENOTSUPP)
return err;
return 0;
}
static const struct mtk_eint_xt mtk_eint_xt = {
.get_gpio_n = mtk_xt_get_gpio_n,
.get_gpio_state = mtk_xt_get_gpio_state,
.set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
};
int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
int ret;
if (!IS_ENABLED(CONFIG_EINT_MTK))
return 0;
if (!of_property_read_bool(np, "interrupt-controller"))
return -ENODEV;
hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
if (!hw->eint)
return -ENOMEM;
hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint");
if (IS_ERR(hw->eint->base)) {
ret = PTR_ERR(hw->eint->base);
goto err_free_eint;
}
hw->eint->irq = irq_of_parse_and_map(np, 0);
if (!hw->eint->irq) {
ret = -EINVAL;
goto err_free_eint;
}
if (!hw->soc->eint_hw) {
ret = -ENODEV;
goto err_free_eint;
}
hw->eint->dev = &pdev->dev;
hw->eint->hw = hw->soc->eint_hw;
hw->eint->pctl = hw;
hw->eint->gpio_xlate = &mtk_eint_xt;
return mtk_eint_do_init(hw->eint);
err_free_eint:
devm_kfree(hw->dev, hw->eint);
hw->eint = NULL;
return ret;
}
EXPORT_SYMBOL_GPL(mtk_build_eint);
/* Revision 0 */
int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc)
{
int err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
MTK_DISABLE);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
MTK_DISABLE);
if (err)
return err;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res)
{
int v, v2;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
if (err)
return err;
if (v == MTK_ENABLE || v2 == MTK_ENABLE)
return -EINVAL;
*res = 1;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup)
{
int err, arg;
arg = pullup ? 1 : 2;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
!!(arg & 2));
if (err)
return err;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup, int *res)
{
int reg, err, v;
reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
err = mtk_hw_get_value(hw, desc, reg, &v);
if (err)
return err;
if (!v)
return -EINVAL;
*res = 1;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
/* Revision 1 */
int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc)
{
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
MTK_DISABLE);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *res)
{
int v, err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
if (err)
return err;
if (v == MTK_ENABLE)
return -EINVAL;
*res = 1;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup)
{
int err, arg;
arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
MTK_ENABLE);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
if (err)
return err;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
int *res)
{
int err, v;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
if (err)
return err;
if (v == MTK_DISABLE)
return -EINVAL;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
if (err)
return err;
if (pullup ^ (v == MTK_PULLUP))
return -EINVAL;
*res = 1;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
/* Combo for the following pull register type:
* 1. PU + PD
* 2. PULLSEL + PULLEN
* 3. PUPD + R0 + R1
*/
static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
{
int err, pu, pd;
if (arg == MTK_DISABLE) {
pu = 0;
pd = 0;
} else if ((arg == MTK_ENABLE) && pullup) {
pu = 1;
pd = 0;
} else if ((arg == MTK_ENABLE) && !pullup) {
pu = 0;
pd = 1;
} else {
err = -EINVAL;
goto out;
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
if (err)
goto out;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
out:
return err;
}
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
{
int err, enable;
if (arg == MTK_DISABLE)
enable = 0;
else if (arg == MTK_ENABLE)
enable = 1;
else {
err = -EINVAL;
goto out;
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
if (err)
goto out;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
out:
return err;
}
static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
{
int err, r0, r1;
if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
pullup = 0;
r0 = 0;
r1 = 0;
} else if (arg == MTK_PUPD_SET_R1R0_01) {
r0 = 1;
r1 = 0;
} else if (arg == MTK_PUPD_SET_R1R0_10) {
r0 = 0;
r1 = 1;
} else if (arg == MTK_PUPD_SET_R1R0_11) {
r0 = 1;
r1 = 1;
} else {
err = -EINVAL;
goto out;
}
/* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
if (err)
goto out;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
if (err)
goto out;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
out:
return err;
}
static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg, u32 *rsel_val)
{
const struct mtk_pin_rsel *rsel;
int check;
bool found = false;
rsel = hw->soc->pin_rsel;
for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
if (desc->number >= rsel[check].s_pin &&
desc->number <= rsel[check].e_pin) {
if (pullup) {
if (rsel[check].up_rsel == arg) {
found = true;
*rsel_val = rsel[check].rsel_index;
break;
}
} else {
if (rsel[check].down_rsel == arg) {
found = true;
*rsel_val = rsel[check].rsel_index;
break;
}
}
}
}
if (!found) {
dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n",
arg, desc->number, desc->name);
return -ENOTSUPP;
}
return 0;
}
static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
{
int err, rsel_val;
if (!pullup && arg == MTK_DISABLE)
return 0;
if (hw->rsel_si_unit) {
/* find pin rsel_index from pin_rsel array*/
err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val);
if (err)
goto out;
} else {
if (arg < MTK_PULL_SET_RSEL_000 ||
arg > MTK_PULL_SET_RSEL_111) {
err = -EINVAL;
goto out;
}
rsel_val = arg - MTK_PULL_SET_RSEL_000;
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val);
if (err)
goto out;
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE);
out:
return err;
}
int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)
{
int err = -ENOTSUPP;
u32 try_all_type;
if (hw->soc->pull_type)
try_all_type = hw->soc->pull_type[desc->number];
else
try_all_type = MTK_PULL_TYPE_MASK;
if (try_all_type & MTK_PULL_RSEL_TYPE) {
err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc,
pullup, arg);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
if (err)
dev_err(hw->dev, "Invalid pull argument\n");
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 rsel_val, u32 *si_unit)
{
const struct mtk_pin_rsel *rsel;
int check;
rsel = hw->soc->pin_rsel;
for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
if (desc->number >= rsel[check].s_pin &&
desc->number <= rsel[check].e_pin) {
if (rsel_val == rsel[check].rsel_index) {
if (pullup)
*si_unit = rsel[check].up_rsel;
else
*si_unit = rsel[check].down_rsel;
break;
}
}
}
return 0;
}
static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
{
int pu, pd, rsel, err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel);
if (err)
goto out;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
if (err)
goto out;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
if (err)
goto out;
if (pu == 0 && pd == 0) {
*pullup = 0;
*enable = MTK_DISABLE;
} else if (pu == 1 && pd == 0) {
*pullup = 1;
if (hw->rsel_si_unit)
mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
else
*enable = rsel + MTK_PULL_SET_RSEL_000;
} else if (pu == 0 && pd == 1) {
*pullup = 0;
if (hw->rsel_si_unit)
mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
else
*enable = rsel + MTK_PULL_SET_RSEL_000;
} else {
err = -EINVAL;
goto out;
}
out:
return err;
}
static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
{
int err, pu, pd;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
if (err)
goto out;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
if (err)
goto out;
if (pu == 0 && pd == 0) {
*pullup = 0;
*enable = MTK_DISABLE;
} else if (pu == 1 && pd == 0) {
*pullup = 1;
*enable = MTK_ENABLE;
} else if (pu == 0 && pd == 1) {
*pullup = 0;
*enable = MTK_ENABLE;
} else
err = -EINVAL;
out:
return err;
}
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
{
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
if (err)
goto out;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
out:
return err;
}
static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
{
int err, r0, r1;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
if (err)
goto out;
/* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
*pullup = !(*pullup);
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
if (err)
goto out;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
if (err)
goto out;
if ((r1 == 0) && (r0 == 0))
*enable = MTK_PUPD_SET_R1R0_00;
else if ((r1 == 0) && (r0 == 1))
*enable = MTK_PUPD_SET_R1R0_01;
else if ((r1 == 1) && (r0 == 0))
*enable = MTK_PUPD_SET_R1R0_10;
else if ((r1 == 1) && (r0 == 1))
*enable = MTK_PUPD_SET_R1R0_11;
else
err = -EINVAL;
out:
return err;
}
int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
{
int err = -ENOTSUPP;
u32 try_all_type;
if (hw->soc->pull_type)
try_all_type = hw->soc->pull_type[desc->number];
else
try_all_type = MTK_PULL_TYPE_MASK;
if (try_all_type & MTK_PULL_RSEL_TYPE) {
err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc,
pullup, enable);
if (!err)
return err;
}
if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
/* Revision 0 */
int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
const struct mtk_drive_desc *tb;
int err = -ENOTSUPP;
tb = &mtk_drive[desc->drv_n];
/* 4mA when (e8, e4) = (0, 0)
* 8mA when (e8, e4) = (0, 1)
* 12mA when (e8, e4) = (1, 0)
* 16mA when (e8, e4) = (1, 1)
*/
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
arg & 0x1);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
(arg & 0x2) >> 1);
if (err)
return err;
}
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val)
{
const struct mtk_drive_desc *tb;
int err, val1, val2;
tb = &mtk_drive[desc->drv_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
if (err)
return err;
/* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
* 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
*/
*val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
/* Revision 1 */
int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
const struct mtk_drive_desc *tb;
int err = -ENOTSUPP;
tb = &mtk_drive[desc->drv_n];
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
arg);
if (err)
return err;
}
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val)
{
const struct mtk_drive_desc *tb;
int err, val1;
tb = &mtk_drive[desc->drv_n];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
if (err)
return err;
*val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, int *val)
{
return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 arg)
{
int err;
/* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
* 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
* 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
* 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
*/
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
if (err)
return 0;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
!!(arg & 2));
if (err)
return 0;
arg = pullup ? 0 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
/* If PUPD register is not supported for that pin, let's fallback to
* general bias control.
*/
if (err == -ENOTSUPP) {
if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, pullup);
if (err)
return err;
} else {
err = mtk_pinconf_bias_set_rev1(hw, desc, pullup);
if (err)
err = mtk_pinconf_bias_set(hw, desc, pullup);
}
}
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val)
{
u32 t, t2;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
/* If PUPD register is not supported for that pin, let's fallback to
* general bias control.
*/
if (err == -ENOTSUPP) {
if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, pullup, val);
if (err)
return err;
} else {
return -ENOTSUPP;
}
} else {
/* t == 0 supposes PULLUP for the customized PULL setup */
if (err)
return err;
if (pullup ^ !t)
return -EINVAL;
}
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
if (err)
return err;
*val = (t | t2 << 1) & 0x7;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
int err;
int en = arg & 1;
int e0 = !!(arg & 2);
int e1 = !!(arg & 4);
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
if (err)
return err;
if (!en)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
if (err)
return err;
return err;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val)
{
u32 en, e0, e1;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
if (err)
return err;
*val = (en | e0 << 1 | e1 << 2) & 0x7;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw);
int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val)
{
return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sean Wang <[email protected]>");
MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
* Author: Andy Teng <[email protected]>
*
*/
#include <linux/module.h>
#include "pinctrl-mtk-mt6779.h"
#include "pinctrl-paris.h"
/* MT6779 have multiple bases to program pin configuration listed as the below:
* gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
* iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
* iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 1)
static const struct mtk_pin_field_calc mt6779_pin_mode_range[] = {
PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
PIN_FIELD_BASE(80, 87, 0, 0x03A0, 0x10, 0, 4),
PIN_FIELD_BASE(88, 95, 0, 0x03B0, 0x10, 0, 4),
PIN_FIELD_BASE(96, 103, 0, 0x03C0, 0x10, 0, 4),
PIN_FIELD_BASE(104, 111, 0, 0x03D0, 0x10, 0, 4),
PIN_FIELD_BASE(112, 119, 0, 0x03E0, 0x10, 0, 4),
PIN_FIELD_BASE(120, 127, 0, 0x03F0, 0x10, 0, 4),
PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
PIN_FIELD_BASE(192, 199, 0, 0x0480, 0x10, 0, 4),
PIN_FIELD_BASE(200, 202, 0, 0x0490, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt6779_pin_dir_range[] = {
PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1),
PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(160, 191, 0, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(192, 202, 0, 0x0060, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_di_range[] = {
PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1),
PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1),
PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1),
PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1),
PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1),
PIN_FIELD_BASE(160, 191, 0, 0x0250, 0x10, 0, 1),
PIN_FIELD_BASE(192, 202, 0, 0x0260, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_do_range[] = {
PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1),
PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1),
PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1),
PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1),
PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1),
PIN_FIELD_BASE(160, 191, 0, 0x0150, 0x10, 0, 1),
PIN_FIELD_BASE(192, 202, 0, 0x0160, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_ies_range[] = {
PIN_FIELD_BASE(0, 9, 6, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(10, 16, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(17, 18, 6, 0x0030, 0x10, 28, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0030, 0x10, 27, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0030, 0x10, 26, 1),
PIN_FIELD_BASE(21, 24, 6, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0030, 0x10, 30, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0030, 0x10, 23, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(28, 29, 6, 0x0030, 0x10, 24, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0030, 0x10, 31, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(38, 41, 6, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(42, 43, 6, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(44, 44, 6, 0x0030, 0x10, 18, 1),
PIN_FIELD_BASE(45, 45, 3, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0050, 0x10, 22, 1),
PIN_FIELD_BASE(47, 47, 3, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(53, 54, 3, 0x0050, 0x10, 27, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(56, 56, 3, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(57, 57, 3, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(58, 58, 3, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(59, 60, 3, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(67, 67, 2, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(68, 68, 2, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(69, 69, 2, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(70, 71, 2, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 4, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 4, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(74, 74, 4, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(76, 76, 4, 0x0020, 0x10, 12, 1),
PIN_FIELD_BASE(77, 77, 4, 0x0020, 0x10, 11, 1),
PIN_FIELD_BASE(78, 78, 2, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(79, 79, 2, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(80, 81, 2, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(82, 88, 2, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 4, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(95, 95, 4, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(96, 96, 4, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(97, 97, 4, 0x0020, 0x10, 8, 1),
PIN_FIELD_BASE(98, 98, 4, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(107, 108, 2, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(109, 109, 2, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(110, 110, 2, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(111, 111, 2, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(112, 112, 2, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(113, 113, 2, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(114, 115, 2, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(116, 117, 2, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(118, 118, 2, 0x0050, 0x10, 31, 1),
PIN_FIELD_BASE(119, 119, 2, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(120, 121, 2, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(122, 123, 2, 0x0050, 0x10, 28, 1),
PIN_FIELD_BASE(124, 125, 2, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(126, 127, 1, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(128, 129, 1, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(130, 130, 1, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0030, 0x10, 21, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 20, 1),
PIN_FIELD_BASE(134, 135, 1, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(140, 141, 1, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 15, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 17, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 16, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 12, 1),
PIN_FIELD_BASE(147, 155, 5, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(156, 157, 5, 0x0020, 0x10, 22, 1),
PIN_FIELD_BASE(158, 158, 5, 0x0020, 0x10, 21, 1),
PIN_FIELD_BASE(159, 159, 5, 0x0020, 0x10, 24, 1),
PIN_FIELD_BASE(160, 161, 5, 0x0020, 0x10, 19, 1),
PIN_FIELD_BASE(162, 166, 5, 0x0020, 0x10, 25, 1),
PIN_FIELD_BASE(167, 168, 7, 0x0010, 0x10, 1, 1),
PIN_FIELD_BASE(169, 169, 7, 0x0010, 0x10, 4, 1),
PIN_FIELD_BASE(170, 170, 7, 0x0010, 0x10, 6, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0010, 0x10, 8, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0010, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0010, 0x10, 7, 1),
PIN_FIELD_BASE(174, 175, 7, 0x0010, 0x10, 9, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0010, 0x10, 0, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0010, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 7, 0x0010, 0x10, 11, 1),
PIN_FIELD_BASE(179, 179, 4, 0x0020, 0x10, 13, 1),
PIN_FIELD_BASE(180, 180, 4, 0x0020, 0x10, 10, 1),
PIN_FIELD_BASE(181, 183, 1, 0x0030, 0x10, 22, 1),
PIN_FIELD_BASE(184, 184, 1, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(185, 185, 1, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(186, 186, 1, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(187, 187, 1, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(188, 188, 1, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(189, 189, 5, 0x0020, 0x10, 9, 1),
PIN_FIELD_BASE(190, 190, 5, 0x0020, 0x10, 18, 1),
PIN_FIELD_BASE(191, 192, 5, 0x0020, 0x10, 13, 1),
PIN_FIELD_BASE(193, 194, 5, 0x0020, 0x10, 10, 1),
PIN_FIELD_BASE(195, 195, 2, 0x0050, 0x10, 30, 1),
PIN_FIELD_BASE(196, 196, 2, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(197, 197, 2, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(198, 199, 4, 0x0020, 0x10, 14, 1),
PIN_FIELD_BASE(200, 201, 6, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(202, 202, 4, 0x0020, 0x10, 9, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_smt_range[] = {
PINS_FIELD_BASE(0, 9, 6, 0x00c0, 0x10, 3, 1),
PIN_FIELD_BASE(10, 11, 3, 0x00e0, 0x10, 0, 1),
PINS_FIELD_BASE(12, 15, 3, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(16, 16, 3, 0x00e0, 0x10, 3, 1),
PINS_FIELD_BASE(17, 20, 6, 0x00c0, 0x10, 11, 1),
PINS_FIELD_BASE(21, 24, 6, 0x00c0, 0x10, 7, 1),
PIN_FIELD_BASE(25, 25, 6, 0x00c0, 0x10, 12, 1),
PIN_FIELD_BASE(26, 26, 6, 0x00c0, 0x10, 8, 1),
PIN_FIELD_BASE(27, 27, 6, 0x00c0, 0x10, 0, 1),
PIN_FIELD_BASE(28, 29, 6, 0x00c0, 0x10, 9, 1),
PINS_FIELD_BASE(30, 32, 6, 0x00c0, 0x10, 4, 1),
PIN_FIELD_BASE(33, 33, 6, 0x00c0, 0x10, 5, 1),
PIN_FIELD_BASE(34, 34, 6, 0x00c0, 0x10, 4, 1),
PINS_FIELD_BASE(35, 41, 6, 0x00c0, 0x10, 13, 1),
PIN_FIELD_BASE(42, 43, 6, 0x00c0, 0x10, 1, 1),
PIN_FIELD_BASE(44, 44, 6, 0x00c0, 0x10, 6, 1),
PIN_FIELD_BASE(45, 45, 3, 0x00e0, 0x10, 8, 1),
PIN_FIELD_BASE(46, 46, 3, 0x00e0, 0x10, 13, 1),
PINS_FIELD_BASE(47, 50, 3, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(51, 51, 3, 0x00e0, 0x10, 5, 1),
PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 10, 1),
PIN_FIELD_BASE(53, 54, 3, 0x00e0, 0x10, 15, 1),
PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 7, 1),
PIN_FIELD_BASE(56, 56, 3, 0x00e0, 0x10, 12, 1),
PINS_FIELD_BASE(57, 60, 3, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 11, 1),
PINS_FIELD_BASE(63, 66, 3, 0x00e0, 0x10, 9, 1),
PINS_FIELD_BASE(67, 69, 2, 0x00e0, 0x10, 11, 1),
PIN_FIELD_BASE(70, 71, 2, 0x00e0, 0x10, 10, 1),
PINS_FIELD_BASE(72, 75, 4, 0x0070, 0x10, 1, 1),
PINS_FIELD_BASE(76, 77, 4, 0x0070, 0x10, 4, 1),
PINS_FIELD_BASE(78, 86, 2, 0x00e0, 0x10, 1, 1),
PINS_FIELD_BASE(87, 92, 2, 0x00e0, 0x10, 2, 1),
PIN_FIELD_BASE(93, 93, 4, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(94, 94, 2, 0x00e0, 0x10, 2, 1),
PINS_FIELD_BASE(95, 98, 4, 0x0070, 0x10, 2, 1),
PINS_FIELD_BASE(99, 104, 2, 0x00e0, 0x10, 12, 1),
PINS_FIELD_BASE(105, 109, 2, 0x00e0, 0x10, 0, 1),
PIN_FIELD_BASE(110, 110, 2, 0x00e0, 0x10, 14, 1),
PIN_FIELD_BASE(111, 111, 2, 0x00e0, 0x10, 16, 1),
PIN_FIELD_BASE(112, 112, 2, 0x00e0, 0x10, 13, 1),
PIN_FIELD_BASE(113, 113, 2, 0x00e0, 0x10, 15, 1),
PINS_FIELD_BASE(114, 115, 2, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(116, 117, 2, 0x00e0, 0x10, 5, 1),
PINS_FIELD_BASE(118, 119, 2, 0x00e0, 0x10, 4, 1),
PIN_FIELD_BASE(120, 121, 2, 0x00e0, 0x10, 7, 1),
PINS_FIELD_BASE(122, 125, 2, 0x00e0, 0x10, 3, 1),
PINS_FIELD_BASE(126, 127, 1, 0x00c0, 0x10, 5, 1),
PINS_FIELD_BASE(128, 130, 1, 0x00c0, 0x10, 9, 1),
PINS_FIELD_BASE(131, 133, 1, 0x00c0, 0x10, 10, 1),
PIN_FIELD_BASE(134, 135, 1, 0x00c0, 0x10, 2, 1),
PINS_FIELD_BASE(136, 139, 1, 0x00c0, 0x10, 4, 1),
PIN_FIELD_BASE(140, 141, 1, 0x00c0, 0x10, 0, 1),
PIN_FIELD_BASE(142, 142, 1, 0x00c0, 0x10, 8, 1),
PINS_FIELD_BASE(143, 146, 5, 0x0060, 0x10, 1, 1),
PINS_FIELD_BASE(147, 155, 5, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(156, 157, 5, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(158, 158, 5, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(159, 159, 5, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(160, 161, 5, 0x0060, 0x10, 3, 1),
PINS_FIELD_BASE(162, 166, 5, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(167, 167, 7, 0x0060, 0x10, 1, 1),
PINS_FIELD_BASE(168, 174, 7, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 0, 1),
PINS_FIELD_BASE(177, 178, 7, 0x0060, 0x10, 2, 1),
PINS_FIELD_BASE(179, 180, 4, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(181, 183, 1, 0x00c0, 0x10, 11, 1),
PINS_FIELD_BASE(184, 187, 1, 0x00c0, 0x10, 6, 1),
PIN_FIELD_BASE(188, 188, 1, 0x00c0, 0x10, 7, 1),
PINS_FIELD_BASE(189, 194, 5, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(195, 195, 2, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(196, 196, 2, 0x00e0, 0x10, 9, 1),
PIN_FIELD_BASE(197, 197, 2, 0x00e0, 0x10, 3, 1),
PIN_FIELD_BASE(198, 199, 4, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(200, 201, 6, 0x00c0, 0x10, 14, 1),
PIN_FIELD_BASE(202, 202, 4, 0x0070, 0x10, 3, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_pu_range[] = {
PIN_FIELD_BASE(0, 9, 6, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(16, 16, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(17, 18, 6, 0x0070, 0x10, 28, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0070, 0x10, 27, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0070, 0x10, 26, 1),
PIN_FIELD_BASE(21, 24, 6, 0x0070, 0x10, 19, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0070, 0x10, 30, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0070, 0x10, 23, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(28, 29, 6, 0x0070, 0x10, 24, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 16, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 15, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 17, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(38, 41, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(42, 43, 6, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(44, 44, 6, 0x0070, 0x10, 18, 1),
PIN_FIELD_BASE(45, 45, 3, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(47, 47, 3, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(53, 54, 3, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(56, 56, 3, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(67, 67, 2, 0x00a0, 0x10, 7, 1),
PIN_FIELD_BASE(68, 68, 2, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(69, 69, 2, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(70, 71, 2, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 4, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 4, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(74, 74, 4, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(76, 76, 4, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(77, 77, 4, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(78, 78, 2, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(79, 79, 2, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(80, 81, 2, 0x0090, 0x10, 19, 1),
PIN_FIELD_BASE(82, 88, 2, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 4, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(95, 95, 4, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(96, 96, 4, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(97, 97, 4, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(98, 98, 4, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(99, 99, 2, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(100, 100, 2, 0x00a0, 0x10, 12, 1),
PIN_FIELD_BASE(101, 101, 2, 0x00a0, 0x10, 10, 1),
PIN_FIELD_BASE(102, 102, 2, 0x00a0, 0x10, 13, 1),
PIN_FIELD_BASE(103, 103, 2, 0x00a0, 0x10, 11, 1),
PIN_FIELD_BASE(104, 104, 2, 0x00a0, 0x10, 14, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(107, 108, 2, 0x0090, 0x10, 12, 1),
PIN_FIELD_BASE(109, 109, 2, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(110, 110, 2, 0x00a0, 0x10, 16, 1),
PIN_FIELD_BASE(111, 111, 2, 0x00a0, 0x10, 18, 1),
PIN_FIELD_BASE(112, 112, 2, 0x00a0, 0x10, 15, 1),
PIN_FIELD_BASE(113, 113, 2, 0x00a0, 0x10, 17, 1),
PIN_FIELD_BASE(114, 115, 2, 0x0090, 0x10, 26, 1),
PIN_FIELD_BASE(116, 117, 2, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(118, 118, 2, 0x0090, 0x10, 31, 1),
PIN_FIELD_BASE(119, 119, 2, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(120, 121, 2, 0x0090, 0x10, 23, 1),
PIN_FIELD_BASE(122, 123, 2, 0x0090, 0x10, 28, 1),
PIN_FIELD_BASE(124, 125, 2, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(126, 127, 1, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(140, 141, 1, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(147, 155, 5, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(156, 157, 5, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(158, 158, 5, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(159, 159, 5, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(160, 161, 5, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(162, 166, 5, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(179, 179, 4, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(180, 180, 4, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(181, 183, 1, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(184, 184, 1, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(185, 185, 1, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(186, 186, 1, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(187, 187, 1, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(188, 188, 1, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(189, 189, 5, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(190, 190, 5, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(191, 192, 5, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(193, 194, 5, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(195, 195, 2, 0x0090, 0x10, 30, 1),
PIN_FIELD_BASE(196, 196, 2, 0x0090, 0x10, 25, 1),
PIN_FIELD_BASE(197, 197, 2, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(198, 199, 4, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(200, 201, 6, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(202, 202, 4, 0x0040, 0x10, 9, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_pd_range[] = {
PIN_FIELD_BASE(0, 9, 6, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(16, 16, 3, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(17, 18, 6, 0x0050, 0x10, 28, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0050, 0x10, 27, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(21, 24, 6, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0050, 0x10, 30, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(28, 29, 6, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(38, 41, 6, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(42, 43, 6, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(44, 44, 6, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(45, 45, 3, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(46, 46, 3, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(47, 47, 3, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(50, 50, 3, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(51, 51, 3, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(53, 54, 3, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(56, 56, 3, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(67, 67, 2, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(68, 68, 2, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(69, 69, 2, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(70, 71, 2, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 4, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(73, 73, 4, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(74, 74, 4, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(76, 76, 4, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(77, 77, 4, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(78, 78, 2, 0x0070, 0x10, 18, 1),
PIN_FIELD_BASE(79, 79, 2, 0x0070, 0x10, 17, 1),
PIN_FIELD_BASE(80, 81, 2, 0x0070, 0x10, 19, 1),
PIN_FIELD_BASE(82, 88, 2, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0070, 0x10, 16, 1),
PIN_FIELD_BASE(90, 90, 2, 0x0070, 0x10, 15, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 14, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 4, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(95, 95, 4, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(96, 96, 4, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(97, 97, 4, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(98, 98, 4, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(107, 108, 2, 0x0070, 0x10, 12, 1),
PIN_FIELD_BASE(109, 109, 2, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(110, 110, 2, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(111, 111, 2, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(112, 112, 2, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(113, 113, 2, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(114, 115, 2, 0x0070, 0x10, 26, 1),
PIN_FIELD_BASE(116, 117, 2, 0x0070, 0x10, 21, 1),
PIN_FIELD_BASE(118, 118, 2, 0x0070, 0x10, 31, 1),
PIN_FIELD_BASE(119, 119, 2, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(120, 121, 2, 0x0070, 0x10, 23, 1),
PIN_FIELD_BASE(122, 123, 2, 0x0070, 0x10, 28, 1),
PIN_FIELD_BASE(124, 125, 2, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(126, 127, 1, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(140, 141, 1, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(147, 155, 5, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(156, 157, 5, 0x0030, 0x10, 22, 1),
PIN_FIELD_BASE(158, 158, 5, 0x0030, 0x10, 21, 1),
PIN_FIELD_BASE(159, 159, 5, 0x0030, 0x10, 24, 1),
PIN_FIELD_BASE(160, 161, 5, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(162, 166, 5, 0x0030, 0x10, 25, 1),
PIN_FIELD_BASE(179, 179, 4, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(180, 180, 4, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(181, 183, 1, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(184, 184, 1, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(185, 185, 1, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(186, 186, 1, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(187, 187, 1, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(188, 188, 1, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(189, 189, 5, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(190, 190, 5, 0x0030, 0x10, 18, 1),
PIN_FIELD_BASE(191, 192, 5, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(193, 194, 5, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(195, 195, 2, 0x0070, 0x10, 30, 1),
PIN_FIELD_BASE(196, 196, 2, 0x0070, 0x10, 25, 1),
PIN_FIELD_BASE(197, 197, 2, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(198, 199, 4, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(200, 201, 6, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(202, 202, 4, 0x0030, 0x10, 9, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_drv_range[] = {
PINS_FIELD_BASE(0, 9, 6, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(10, 16, 3, 0x0000, 0x10, 0, 3),
PINS_FIELD_BASE(17, 19, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(20, 20, 6, 0x0010, 0x10, 6, 3),
PINS_FIELD_BASE(21, 24, 6, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(25, 25, 6, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(26, 26, 6, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(27, 27, 6, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(30, 32, 6, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(33, 33, 6, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(34, 34, 6, 0x0000, 0x10, 12, 3),
PINS_FIELD_BASE(35, 41, 6, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(42, 43, 6, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(44, 44, 6, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(45, 45, 3, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(46, 46, 3, 0x0020, 0x10, 0, 3),
PINS_FIELD_BASE(47, 49, 3, 0x0020, 0x10, 3, 3),
PIN_FIELD_BASE(50, 50, 3, 0x0020, 0x10, 6, 3),
PIN_FIELD_BASE(51, 51, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 21, 3),
PINS_FIELD_BASE(53, 54, 3, 0x0020, 0x10, 9, 3),
PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(56, 56, 3, 0x0010, 0x10, 27, 3),
PIN_FIELD_BASE(57, 57, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(58, 58, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(59, 60, 3, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(61, 61, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(62, 62, 3, 0x0010, 0x10, 24, 3),
PINS_FIELD_BASE(63, 65, 3, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(66, 66, 3, 0x0010, 0x10, 18, 3),
PINS_FIELD_BASE(67, 69, 2, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(70, 71, 2, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(72, 75, 4, 0x0000, 0x10, 0, 3),
PINS_FIELD_BASE(76, 77, 4, 0x0000, 0x10, 15, 3),
PINS_FIELD_BASE(78, 86, 2, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(87, 92, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(93, 93, 4, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(94, 94, 2, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(95, 96, 4, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(97, 98, 4, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(99, 100, 2, 0x0010, 0x10, 6, 3),
PINS_FIELD_BASE(101, 102, 2, 0x0010, 0x10, 9, 3),
PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 12, 3),
PINS_FIELD_BASE(105, 109, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(110, 110, 2, 0x0010, 0x10, 18, 3),
PIN_FIELD_BASE(111, 111, 2, 0x0010, 0x10, 24, 3),
PIN_FIELD_BASE(112, 112, 2, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(113, 113, 2, 0x0010, 0x10, 21, 3),
PINS_FIELD_BASE(114, 115, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(116, 117, 2, 0x0000, 0x10, 15, 3),
PINS_FIELD_BASE(118, 119, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(120, 121, 2, 0x0000, 0x10, 21, 3),
PINS_FIELD_BASE(122, 125, 2, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(126, 127, 1, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(128, 128, 1, 0x0000, 0x10, 29, 2),
PIN_FIELD_BASE(129, 129, 1, 0x0010, 0x10, 0, 2),
PIN_FIELD_BASE(130, 130, 1, 0x0000, 0x10, 27, 2),
PIN_FIELD_BASE(131, 131, 1, 0x0010, 0x10, 2, 2),
PIN_FIELD_BASE(132, 132, 1, 0x0010, 0x10, 6, 2),
PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 4, 2),
PIN_FIELD_BASE(134, 135, 1, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(136, 139, 1, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(140, 141, 1, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(142, 142, 1, 0x0000, 0x10, 24, 3),
PINS_FIELD_BASE(143, 146, 5, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(147, 155, 5, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(156, 157, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(158, 158, 5, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(159, 159, 5, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(160, 161, 5, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(162, 166, 5, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(167, 167, 7, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(168, 174, 7, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(175, 175, 7, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(176, 176, 7, 0x0000, 0x10, 0, 3),
PINS_FIELD_BASE(177, 178, 7, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(179, 180, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(181, 183, 1, 0x0010, 0x10, 8, 3),
PINS_FIELD_BASE(184, 186, 1, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(187, 188, 1, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(189, 189, 5, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(190, 194, 5, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(195, 195, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(196, 196, 2, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(197, 197, 2, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(198, 199, 4, 0x0000, 0x10, 21, 3),
PINS_FIELD_BASE(200, 201, 6, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(202, 202, 4, 0x0000, 0x10, 12, 3),
};
static const struct mtk_pin_field_calc mt6779_pin_pupd_range[] = {
PIN_FIELD_BASE(10, 15, 3, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(57, 57, 3, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(58, 58, 3, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(59, 60, 3, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(128, 129, 1, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 1, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(134, 135, 1, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(167, 168, 7, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(169, 169, 7, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(170, 170, 7, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0020, 0x10, 8, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(174, 175, 7, 0x0020, 0x10, 9, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 7, 0x0020, 0x10, 11, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_r0_range[] = {
PIN_FIELD_BASE(10, 15, 3, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(57, 57, 3, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(58, 58, 3, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(59, 60, 3, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(128, 129, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(134, 135, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(167, 168, 7, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(169, 169, 7, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(170, 170, 7, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(174, 175, 7, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 7, 0x0030, 0x10, 11, 1),
};
static const struct mtk_pin_field_calc mt6779_pin_r1_range[] = {
PIN_FIELD_BASE(10, 15, 3, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(57, 57, 3, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(59, 60, 3, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(128, 129, 1, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 1, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(131, 131, 1, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(132, 132, 1, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(133, 133, 1, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(134, 135, 1, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(167, 168, 7, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(169, 169, 7, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(170, 170, 7, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(174, 175, 7, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(178, 178, 7, 0x0040, 0x10, 11, 1),
};
static const struct mtk_pin_reg_calc mt6779_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6779_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6779_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6779_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6779_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6779_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6779_pin_ies_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6779_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6779_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6779_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6779_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6779_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6779_pin_r1_range),
};
static const char * const mt6779_pinctrl_register_base_names[] = {
"gpio", "iocfg_rm", "iocfg_br", "iocfg_lm", "iocfg_lb",
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
static const struct mtk_eint_hw mt6779_eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 195,
.db_cnt = 13,
.db_time = debounce_time_mt2701,
};
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
.eint_hw = &mt6779_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt6779_pinctrl_register_base_names),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_raw,
.drive_get = mtk_pinconf_drive_get_raw,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt6779_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data },
{ }
};
static struct platform_driver mt6779_pinctrl_driver = {
.driver = {
.name = "mt6779-pinctrl",
.of_match_table = mt6779_pinctrl_of_match,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt6779_pinctrl_init(void)
{
return platform_driver_register(&mt6779_pinctrl_driver);
}
arch_initcall(mt6779_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT6779 Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt6779.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
* pinctrl-bindings.txt for MediaTek SoC.
*
* Copyright (C) 2017-2018 MediaTek Inc.
* Author: Sean Wang <[email protected]>
*
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/consumer.h>
#include "pinctrl-moore.h"
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
/* Custom pinconf parameters */
#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
};
#endif
static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
int i;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
func->name, grp->name);
for (i = 0; i < grp->num_pins; i++) {
const struct mtk_pin_desc *desc;
int *pin_modes = grp->data;
int pin = grp->pins[i];
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
pin_modes[i]);
}
return 0;
}
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
hw->soc->gpio_m);
}
static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
/* hardware would take 0 as input direction */
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
}
static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, val2, err, pullup, reg, ret = 1;
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
return -EINVAL;
} else if (hw->soc->bias_disable_get) {
err = hw->soc->bias_disable_get(hw, desc, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
return -EINVAL;
if (!pullup)
return -EINVAL;
} else if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 1, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_get_combo) {
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
return err;
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
return -EINVAL;
if (pullup)
return -EINVAL;
} else if (hw->soc->bias_get) {
err = hw->soc->bias_get(hw, desc, 0, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
if (err)
return err;
if (!val)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
/* HW takes input mode as zero; output mode as non-zero */
if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
(!val && param == PIN_CONFIG_OUTPUT_ENABLE))
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
if (err)
return err;
if (val || !val2)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_get) {
err = hw->soc->drive_get(hw, desc, &ret);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_get_value(hw, desc, reg, &val);
if (err)
return err;
ret = val;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_get) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, ret);
return 0;
}
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
u32 reg, param, arg;
int cfg, err = 0;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
if (!desc->name)
return -ENOTSUPP;
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
if (err)
return err;
} else if (hw->soc->bias_disable_set) {
err = hw->soc->bias_disable_set(hw, desc);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
if (err)
return err;
} else if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 1);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (hw->soc->bias_set_combo) {
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
if (err)
return err;
} else if (hw->soc->bias_set) {
err = hw->soc->bias_set(hw, desc, 0);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (hw->soc->ies_present) {
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
MTK_ENABLE);
}
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
if (err)
goto err;
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
/* arg = 1: Input mode & SMT enable ;
* arg = 0: Output mode & SMT disable
*/
arg = arg ? 2 : 1;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
arg & 1);
if (err)
goto err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
!!(arg & 2));
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
} else {
err = -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_set_value(hw, desc, reg, arg);
if (err)
goto err;
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_set) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_set(hw, desc, pullup,
arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
err = -ENOTSUPP;
}
}
err:
return err;
}
static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *config)
{
const unsigned int *pins;
unsigned int i, npins, old = 0;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (mtk_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && old != *config)
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinctrl_ops mtk_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static const struct pinmux_ops mtk_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = mtk_pinmux_set_mux,
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
.strict = true,
};
static const struct pinconf_ops mtk_confops = {
.is_generic = true,
.pin_config_get = mtk_pinconf_get,
.pin_config_set = mtk_pinconf_set,
.pin_config_group_get = mtk_pinconf_group_get,
.pin_config_group_set = mtk_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static struct pinctrl_desc mtk_desc = {
.name = PINCTRL_PINCTRL_DEV,
.pctlops = &mtk_pctlops,
.pmxops = &mtk_pmxops,
.confops = &mtk_confops,
.owner = THIS_MODULE,
};
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
if (!desc->name)
return -ENOTSUPP;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
if (!desc->name) {
dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
return;
}
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
{
return pinctrl_gpio_direction_input(chip->base + gpio);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
mtk_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip->base + gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (!hw->eint)
return -ENOTSUPP;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (desc->eint.eint_n == (u16)EINT_NA)
return -ENOTSUPP;
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!desc->name)
return -ENOTSUPP;
if (!hw->eint ||
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
desc->eint.eint_n == (u16)EINT_NA)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
}
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
{
struct gpio_chip *chip = &hw->chip;
int ret;
chip->label = PINCTRL_PINCTRL_DEV;
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->direction_input = mtk_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
chip->to_irq = mtk_gpio_to_irq;
chip->set_config = mtk_gpio_set_config;
chip->base = -1;
chip->ngpio = hw->soc->npins;
ret = gpiochip_add_data(chip, hw);
if (ret < 0)
return ret;
/* Just for backward compatible for these old pinctrl nodes without
* "gpio-ranges" property. Otherwise, called directly from a
* DeviceTree-supported pinctrl driver is DEPRECATED.
* Please see Section 2.1 of
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
*/
if (!of_property_present(hw->dev->of_node, "gpio-ranges")) {
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
chip->ngpio);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
}
}
return 0;
}
static int mtk_build_groups(struct mtk_pinctrl *hw)
{
int err, i;
for (i = 0; i < hw->soc->ngrps; i++) {
const struct group_desc *group = hw->soc->grps + i;
err = pinctrl_generic_add_group(hw->pctrl, group->name,
group->pins, group->num_pins,
group->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register group %s\n",
group->name);
return err;
}
}
return 0;
}
static int mtk_build_functions(struct mtk_pinctrl *hw)
{
int i, err;
for (i = 0; i < hw->soc->nfuncs ; i++) {
const struct function_desc *func = hw->soc->funcs + i;
err = pinmux_generic_add_function(hw->pctrl, func->name,
func->group_names,
func->num_group_names,
func->data);
if (err < 0) {
dev_err(hw->dev, "Failed to register function %s\n",
func->name);
return err;
}
}
return 0;
}
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
hw->soc = soc;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names)
return dev_err_probe(dev, -EINVAL,
"SoC should be assigned at least one register base\n");
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
if (!hw->base)
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
hw->nbase = hw->soc->nbase_names;
spin_lock_init(&hw->lock);
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < hw->soc->npins; i++) {
pins[i].number = hw->soc->pins[i].number;
pins[i].name = hw->soc->pins[i].name;
}
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
mtk_desc.npins = hw->soc->npins;
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
mtk_desc.custom_params = mtk_custom_bindings;
#ifdef CONFIG_DEBUG_FS
mtk_desc.custom_conf_items = mtk_conf_items;
#endif
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;
/* Setup groups descriptions per SoC types */
err = mtk_build_groups(hw);
if (err)
return dev_err_probe(dev, err, "Failed to build groups\n");
/* Setup functions descriptions per SoC types */
err = mtk_build_functions(hw);
if (err)
return dev_err_probe(dev, err, "Failed to build functions\n");
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
* until all groups and functions are being added one.
*/
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw);
if (err)
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
platform_set_drvdata(pdev, hw);
return 0;
}
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-moore.c
|
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2014-2018 MediaTek Inc.
/*
* Library for MediaTek External Interrupt Support
*
* Author: Maoguang Meng <[email protected]>
* Sean Wang <[email protected]>
*
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include "mtk-eint.h"
#define MTK_EINT_EDGE_SENSITIVE 0
#define MTK_EINT_LEVEL_SENSITIVE 1
#define MTK_EINT_DBNC_SET_DBNC_BITS 4
#define MTK_EINT_DBNC_MAX 16
#define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
#define MTK_EINT_DBNC_SET_EN (0x1 << 0)
static const struct mtk_eint_regs mtk_generic_eint_regs = {
.stat = 0x000,
.ack = 0x040,
.mask = 0x080,
.mask_set = 0x0c0,
.mask_clr = 0x100,
.sens = 0x140,
.sens_set = 0x180,
.sens_clr = 0x1c0,
.soft = 0x200,
.soft_set = 0x240,
.soft_clr = 0x280,
.pol = 0x300,
.pol_set = 0x340,
.pol_clr = 0x380,
.dom_en = 0x400,
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
};
const unsigned int debounce_time_mt2701[] = {
500, 1000, 16000, 32000, 64000, 128000, 256000, 0
};
EXPORT_SYMBOL_GPL(debounce_time_mt2701);
const unsigned int debounce_time_mt6765[] = {
125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
};
EXPORT_SYMBOL_GPL(debounce_time_mt6765);
const unsigned int debounce_time_mt6795[] = {
500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
};
EXPORT_SYMBOL_GPL(debounce_time_mt6795);
static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
unsigned int eint_num,
unsigned int offset)
{
unsigned int eint_base = 0;
void __iomem *reg;
if (eint_num >= eint->hw->ap_num)
eint_base = eint->hw->ap_num;
reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
return reg;
}
static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
unsigned int eint_num)
{
unsigned int sens;
unsigned int bit = BIT(eint_num % 32);
void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
eint->regs->sens);
if (readl(reg) & bit)
sens = MTK_EINT_LEVEL_SENSITIVE;
else
sens = MTK_EINT_EDGE_SENSITIVE;
if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
return 1;
else
return 0;
}
static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
{
int start_level, curr_level;
unsigned int reg_offset;
u32 mask = BIT(hwirq & 0x1f);
u32 port = (hwirq >> 5) & eint->hw->port_mask;
void __iomem *reg = eint->base + (port << 2);
curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
do {
start_level = curr_level;
if (start_level)
reg_offset = eint->regs->pol_clr;
else
reg_offset = eint->regs->pol_set;
writel(mask, reg + reg_offset);
curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
hwirq);
} while (start_level != curr_level);
return start_level;
}
static void mtk_eint_mask(struct irq_data *d)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
u32 mask = BIT(d->hwirq & 0x1f);
void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
eint->regs->mask_set);
eint->cur_mask[d->hwirq >> 5] &= ~mask;
writel(mask, reg);
}
static void mtk_eint_unmask(struct irq_data *d)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
u32 mask = BIT(d->hwirq & 0x1f);
void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
eint->regs->mask_clr);
eint->cur_mask[d->hwirq >> 5] |= mask;
writel(mask, reg);
if (eint->dual_edge[d->hwirq])
mtk_eint_flip_edge(eint, d->hwirq);
}
static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
unsigned int eint_num)
{
unsigned int bit = BIT(eint_num % 32);
void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
eint->regs->mask);
return !!(readl(reg) & bit);
}
static void mtk_eint_ack(struct irq_data *d)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
u32 mask = BIT(d->hwirq & 0x1f);
void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
eint->regs->ack);
writel(mask, reg);
}
static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
bool masked;
u32 mask = BIT(d->hwirq & 0x1f);
void __iomem *reg;
if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
dev_err(eint->dev,
"Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
d->irq, d->hwirq, type);
return -EINVAL;
}
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
eint->dual_edge[d->hwirq] = 1;
else
eint->dual_edge[d->hwirq] = 0;
if (!mtk_eint_get_mask(eint, d->hwirq)) {
mtk_eint_mask(d);
masked = false;
} else {
masked = true;
}
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
writel(mask, reg);
} else {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
writel(mask, reg);
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
writel(mask, reg);
} else {
reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
writel(mask, reg);
}
mtk_eint_ack(d);
if (!masked)
mtk_eint_unmask(d);
return 0;
}
static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
int shift = d->hwirq & 0x1f;
int reg = d->hwirq >> 5;
if (on)
eint->wake_mask[reg] |= BIT(shift);
else
eint->wake_mask[reg] &= ~BIT(shift);
return 0;
}
static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
void __iomem *base, u32 *buf)
{
int port;
void __iomem *reg;
for (port = 0; port < eint->hw->ports; port++) {
reg = base + (port << 2);
writel_relaxed(~buf[port], reg + eint->regs->mask_set);
writel_relaxed(buf[port], reg + eint->regs->mask_clr);
}
}
static int mtk_eint_irq_request_resources(struct irq_data *d)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
struct gpio_chip *gpio_c;
unsigned int gpio_n;
int err;
err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
&gpio_n, &gpio_c);
if (err < 0) {
dev_err(eint->dev, "Can not find pin\n");
return err;
}
err = gpiochip_lock_as_irq(gpio_c, gpio_n);
if (err < 0) {
dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
irqd_to_hwirq(d));
return err;
}
err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
if (err < 0) {
dev_err(eint->dev, "Can not eint mode\n");
return err;
}
return 0;
}
static void mtk_eint_irq_release_resources(struct irq_data *d)
{
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
struct gpio_chip *gpio_c;
unsigned int gpio_n;
eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
&gpio_c);
gpiochip_unlock_as_irq(gpio_c, gpio_n);
}
static struct irq_chip mtk_eint_irq_chip = {
.name = "mt-eint",
.irq_disable = mtk_eint_mask,
.irq_mask = mtk_eint_mask,
.irq_unmask = mtk_eint_unmask,
.irq_ack = mtk_eint_ack,
.irq_set_type = mtk_eint_set_type,
.irq_set_wake = mtk_eint_irq_set_wake,
.irq_request_resources = mtk_eint_irq_request_resources,
.irq_release_resources = mtk_eint_irq_release_resources,
};
static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
{
void __iomem *dom_en = eint->base + eint->regs->dom_en;
void __iomem *mask_set = eint->base + eint->regs->mask_set;
unsigned int i;
for (i = 0; i < eint->hw->ap_num; i += 32) {
writel(0xffffffff, dom_en);
writel(0xffffffff, mask_set);
dom_en += 4;
mask_set += 4;
}
return 0;
}
static inline void
mtk_eint_debounce_process(struct mtk_eint *eint, int index)
{
unsigned int rst, ctrl_offset;
unsigned int bit, dbnc;
ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
dbnc = readl(eint->base + ctrl_offset);
bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
if ((bit & dbnc) > 0) {
ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
writel(rst, eint->base + ctrl_offset);
}
}
static void mtk_eint_irq_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct mtk_eint *eint = irq_desc_get_handler_data(desc);
unsigned int status, eint_num;
int offset, mask_offset, index;
void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
int dual_edge, start_level, curr_level;
chained_irq_enter(chip, desc);
for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
reg += 4) {
status = readl(reg);
while (status) {
offset = __ffs(status);
mask_offset = eint_num >> 5;
index = eint_num + offset;
status &= ~BIT(offset);
/*
* If we get an interrupt on pin that was only required
* for wake (but no real interrupt requested), mask the
* interrupt (as would mtk_eint_resume do anyway later
* in the resume sequence).
*/
if (eint->wake_mask[mask_offset] & BIT(offset) &&
!(eint->cur_mask[mask_offset] & BIT(offset))) {
writel_relaxed(BIT(offset), reg -
eint->regs->stat +
eint->regs->mask_set);
}
dual_edge = eint->dual_edge[index];
if (dual_edge) {
/*
* Clear soft-irq in case we raised it last
* time.
*/
writel(BIT(offset), reg - eint->regs->stat +
eint->regs->soft_clr);
start_level =
eint->gpio_xlate->get_gpio_state(eint->pctl,
index);
}
generic_handle_domain_irq(eint->domain, index);
if (dual_edge) {
curr_level = mtk_eint_flip_edge(eint, index);
/*
* If level changed, we might lost one edge
* interrupt, raised it through soft-irq.
*/
if (start_level != curr_level)
writel(BIT(offset), reg -
eint->regs->stat +
eint->regs->soft_set);
}
if (index < eint->hw->db_cnt)
mtk_eint_debounce_process(eint, index);
}
}
chained_irq_exit(chip, desc);
}
int mtk_eint_do_suspend(struct mtk_eint *eint)
{
mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
int mtk_eint_do_resume(struct mtk_eint *eint)
{
mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
unsigned int debounce)
{
int virq, eint_offset;
unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
dbnc;
struct irq_data *d;
if (!eint->hw->db_time)
return -EOPNOTSUPP;
virq = irq_find_mapping(eint->domain, eint_num);
eint_offset = (eint_num % 4) * 8;
d = irq_get_irq_data(virq);
set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
if (!mtk_eint_can_en_debounce(eint, eint_num))
return -EINVAL;
dbnc = eint->num_db_time;
for (i = 0; i < eint->num_db_time; i++) {
if (debounce <= eint->hw->db_time[i]) {
dbnc = i;
break;
}
}
if (!mtk_eint_get_mask(eint, eint_num)) {
mtk_eint_mask(d);
unmask = 1;
} else {
unmask = 0;
}
clr_bit = 0xff << eint_offset;
writel(clr_bit, eint->base + clr_offset);
bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
eint_offset;
rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
writel(rst | bit, eint->base + set_offset);
/*
* Delay a while (more than 2T) to wait for hw debounce counter reset
* work correctly.
*/
udelay(1);
if (unmask == 1)
mtk_eint_unmask(d);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
{
int irq;
irq = irq_find_mapping(eint->domain, eint_n);
if (!irq)
return -EINVAL;
return irq;
}
EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
int mtk_eint_do_init(struct mtk_eint *eint)
{
int i;
/* If clients don't assign a specific regs, let's use generic one */
if (!eint->regs)
eint->regs = &mtk_generic_eint_regs;
eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
sizeof(*eint->wake_mask), GFP_KERNEL);
if (!eint->wake_mask)
return -ENOMEM;
eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
sizeof(*eint->cur_mask), GFP_KERNEL);
if (!eint->cur_mask)
return -ENOMEM;
eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
sizeof(int), GFP_KERNEL);
if (!eint->dual_edge)
return -ENOMEM;
eint->domain = irq_domain_add_linear(eint->dev->of_node,
eint->hw->ap_num,
&irq_domain_simple_ops, NULL);
if (!eint->domain)
return -ENOMEM;
if (eint->hw->db_time) {
for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
if (eint->hw->db_time[i] == 0)
break;
eint->num_db_time = i;
}
mtk_eint_hw_init(eint);
for (i = 0; i < eint->hw->ap_num; i++) {
int virq = irq_create_mapping(eint->domain, i);
irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
handle_level_irq);
irq_set_chip_data(virq, eint);
}
irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
eint);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_eint_do_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek EINT Driver");
|
linux-master
|
drivers/pinctrl/mediatek/mtk-eint.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* The MT7623 driver based on Linux generic pinctrl binding.
*
* Copyright (C) 2015 - 2018 MediaTek Inc.
* Author: Biao Huang <[email protected]>
* Ryder Lee <[email protected]>
* Sean Wang <[email protected]>
*/
#include "pinctrl-moore.h"
#define PIN_BOND_REG0 0xb10
#define PIN_BOND_REG1 0xf20
#define PIN_BOND_REG2 0xef0
#define BOND_PCIE_CLR (0x77 << 3)
#define BOND_I2S_CLR 0x3
#define BOND_MSDC0E_CLR 0x1
#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 15, false)
#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 0)
#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 1)
#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
MTK_PIN(_number, _name, 0, _eint_n, _drv_grp)
static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
};
static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
};
static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = {
PINS_FIELD16(262, 276, 0x4c0, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
/* MSDC0 */
PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
/* MSDC1 */
PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
/* MSDC1 */
PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
/* MSDC0E */
PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
/* MSDC0 */
PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
/* MSDC1 */
PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
/* MSDC2 */
PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
/* MSDC0E */
PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
};
static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
/* MSDC0 */
PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
/* MSDC1 */
PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
/* MSDC2 */
PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
/* MSDC0E */
PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
};
static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7623_pin_tdsel_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
};
static const struct mtk_pin_desc mt7623_pins[] = {
MT7623_PIN(0, "PWRAP_SPI0_MI", 148, DRV_GRP3),
MT7623_PIN(1, "PWRAP_SPI0_MO", 149, DRV_GRP3),
MT7623_PIN(2, "PWRAP_INT", 150, DRV_GRP3),
MT7623_PIN(3, "PWRAP_SPI0_CK", 151, DRV_GRP3),
MT7623_PIN(4, "PWRAP_SPI0_CSN", 152, DRV_GRP3),
MT7623_PIN(5, "PWRAP_SPI0_CK2", 153, DRV_GRP3),
MT7623_PIN(6, "PWRAP_SPI0_CSN2", 154, DRV_GRP3),
MT7623_PIN(7, "SPI1_CSN", 155, DRV_GRP3),
MT7623_PIN(8, "SPI1_MI", 156, DRV_GRP3),
MT7623_PIN(9, "SPI1_MO", 157, DRV_GRP3),
MT7623_PIN(10, "RTC32K_CK", 158, DRV_GRP3),
MT7623_PIN(11, "WATCHDOG", 159, DRV_GRP3),
MT7623_PIN(12, "SRCLKENA", 160, DRV_GRP3),
MT7623_PIN(13, "SRCLKENAI", 161, DRV_GRP3),
MT7623_PIN(14, "URXD2", 162, DRV_GRP1),
MT7623_PIN(15, "UTXD2", 163, DRV_GRP1),
MT7623_PIN(16, "I2S5_DATA_IN", 164, DRV_GRP1),
MT7623_PIN(17, "I2S5_BCK", 165, DRV_GRP1),
MT7623_PIN(18, "PCM_CLK", 166, DRV_GRP1),
MT7623_PIN(19, "PCM_SYNC", 167, DRV_GRP1),
MT7623_PIN(20, "PCM_RX", EINT_NA, DRV_GRP1),
MT7623_PIN(21, "PCM_TX", EINT_NA, DRV_GRP1),
MT7623_PIN(22, "EINT0", 0, DRV_GRP1),
MT7623_PIN(23, "EINT1", 1, DRV_GRP1),
MT7623_PIN(24, "EINT2", 2, DRV_GRP1),
MT7623_PIN(25, "EINT3", 3, DRV_GRP1),
MT7623_PIN(26, "EINT4", 4, DRV_GRP1),
MT7623_PIN(27, "EINT5", 5, DRV_GRP1),
MT7623_PIN(28, "EINT6", 6, DRV_GRP1),
MT7623_PIN(29, "EINT7", 7, DRV_GRP1),
MT7623_PIN(30, "I2S5_LRCK", 12, DRV_GRP1),
MT7623_PIN(31, "I2S5_MCLK", 13, DRV_GRP1),
MT7623_PIN(32, "I2S5_DATA", 14, DRV_GRP1),
MT7623_PIN(33, "I2S1_DATA", 15, DRV_GRP1),
MT7623_PIN(34, "I2S1_DATA_IN", 16, DRV_GRP1),
MT7623_PIN(35, "I2S1_BCK", 17, DRV_GRP1),
MT7623_PIN(36, "I2S1_LRCK", 18, DRV_GRP1),
MT7623_PIN(37, "I2S1_MCLK", 19, DRV_GRP1),
MT7623_PIN(38, "I2S2_DATA", 20, DRV_GRP1),
MT7623_PIN(39, "JTMS", 21, DRV_GRP3),
MT7623_PIN(40, "JTCK", 22, DRV_GRP3),
MT7623_PIN(41, "JTDI", 23, DRV_GRP3),
MT7623_PIN(42, "JTDO", 24, DRV_GRP3),
MT7623_PIN(43, "NCLE", 25, DRV_GRP1),
MT7623_PIN(44, "NCEB1", 26, DRV_GRP1),
MT7623_PIN(45, "NCEB0", 27, DRV_GRP1),
MT7623_PIN(46, "IR", 28, DRV_FIXED),
MT7623_PIN(47, "NREB", 29, DRV_GRP1),
MT7623_PIN(48, "NRNB", 30, DRV_GRP1),
MT7623_PIN(49, "I2S0_DATA", 31, DRV_GRP1),
MT7623_PIN(50, "I2S2_BCK", 32, DRV_GRP1),
MT7623_PIN(51, "I2S2_DATA_IN", 33, DRV_GRP1),
MT7623_PIN(52, "I2S2_LRCK", 34, DRV_GRP1),
MT7623_PIN(53, "SPI0_CSN", 35, DRV_GRP1),
MT7623_PIN(54, "SPI0_CK", 36, DRV_GRP1),
MT7623_PIN(55, "SPI0_MI", 37, DRV_GRP1),
MT7623_PIN(56, "SPI0_MO", 38, DRV_GRP1),
MT7623_PIN(57, "SDA1", 39, DRV_FIXED),
MT7623_PIN(58, "SCL1", 40, DRV_FIXED),
MT7623_PIN(59, "RAMBUF_I_CLK", EINT_NA, DRV_FIXED),
MT7623_PIN(60, "WB_RSTB", 41, DRV_GRP3),
MT7623_PIN(61, "F2W_DATA", 42, DRV_GRP3),
MT7623_PIN(62, "F2W_CLK", 43, DRV_GRP3),
MT7623_PIN(63, "WB_SCLK", 44, DRV_GRP3),
MT7623_PIN(64, "WB_SDATA", 45, DRV_GRP3),
MT7623_PIN(65, "WB_SEN", 46, DRV_GRP3),
MT7623_PIN(66, "WB_CRTL0", 47, DRV_GRP3),
MT7623_PIN(67, "WB_CRTL1", 48, DRV_GRP3),
MT7623_PIN(68, "WB_CRTL2", 49, DRV_GRP3),
MT7623_PIN(69, "WB_CRTL3", 50, DRV_GRP3),
MT7623_PIN(70, "WB_CRTL4", 51, DRV_GRP3),
MT7623_PIN(71, "WB_CRTL5", 52, DRV_GRP3),
MT7623_PIN(72, "I2S0_DATA_IN", 53, DRV_GRP1),
MT7623_PIN(73, "I2S0_LRCK", 54, DRV_GRP1),
MT7623_PIN(74, "I2S0_BCK", 55, DRV_GRP1),
MT7623_PIN(75, "SDA0", 56, DRV_FIXED),
MT7623_PIN(76, "SCL0", 57, DRV_FIXED),
MT7623_PIN(77, "SDA2", 58, DRV_FIXED),
MT7623_PIN(78, "SCL2", 59, DRV_FIXED),
MT7623_PIN(79, "URXD0", 60, DRV_FIXED),
MT7623_PIN(80, "UTXD0", 61, DRV_FIXED),
MT7623_PIN(81, "URXD1", 62, DRV_FIXED),
MT7623_PIN(82, "UTXD1", 63, DRV_FIXED),
MT7623_PIN(83, "LCM_RST", 64, DRV_FIXED),
MT7623_PIN(84, "DSI_TE", 65, DRV_FIXED),
MT7623_PIN(85, "MSDC2_CMD", 66, DRV_GRP4),
MT7623_PIN(86, "MSDC2_CLK", 67, DRV_GRP4),
MT7623_PIN(87, "MSDC2_DAT0", 68, DRV_GRP4),
MT7623_PIN(88, "MSDC2_DAT1", 69, DRV_GRP4),
MT7623_PIN(89, "MSDC2_DAT2", 70, DRV_GRP4),
MT7623_PIN(90, "MSDC2_DAT3", 71, DRV_GRP4),
MT7623_PIN(91, "TDN3", EINT_NA, DRV_FIXED),
MT7623_PIN(92, "TDP3", EINT_NA, DRV_FIXED),
MT7623_PIN(93, "TDN2", EINT_NA, DRV_FIXED),
MT7623_PIN(94, "TDP2", EINT_NA, DRV_FIXED),
MT7623_PIN(95, "TCN", EINT_NA, DRV_FIXED),
MT7623_PIN(96, "TCP", EINT_NA, DRV_FIXED),
MT7623_PIN(97, "TDN1", EINT_NA, DRV_FIXED),
MT7623_PIN(98, "TDP1", EINT_NA, DRV_FIXED),
MT7623_PIN(99, "TDN0", EINT_NA, DRV_FIXED),
MT7623_PIN(100, "TDP0", EINT_NA, DRV_FIXED),
MT7623_PIN(101, "SPI2_CSN", 74, DRV_FIXED),
MT7623_PIN(102, "SPI2_MI", 75, DRV_FIXED),
MT7623_PIN(103, "SPI2_MO", 76, DRV_FIXED),
MT7623_PIN(104, "SPI2_CLK", 77, DRV_FIXED),
MT7623_PIN(105, "MSDC1_CMD", 78, DRV_GRP4),
MT7623_PIN(106, "MSDC1_CLK", 79, DRV_GRP4),
MT7623_PIN(107, "MSDC1_DAT0", 80, DRV_GRP4),
MT7623_PIN(108, "MSDC1_DAT1", 81, DRV_GRP4),
MT7623_PIN(109, "MSDC1_DAT2", 82, DRV_GRP4),
MT7623_PIN(110, "MSDC1_DAT3", 83, DRV_GRP4),
MT7623_PIN(111, "MSDC0_DAT7", 84, DRV_GRP4),
MT7623_PIN(112, "MSDC0_DAT6", 85, DRV_GRP4),
MT7623_PIN(113, "MSDC0_DAT5", 86, DRV_GRP4),
MT7623_PIN(114, "MSDC0_DAT4", 87, DRV_GRP4),
MT7623_PIN(115, "MSDC0_RSTB", 88, DRV_GRP4),
MT7623_PIN(116, "MSDC0_CMD", 89, DRV_GRP4),
MT7623_PIN(117, "MSDC0_CLK", 90, DRV_GRP4),
MT7623_PIN(118, "MSDC0_DAT3", 91, DRV_GRP4),
MT7623_PIN(119, "MSDC0_DAT2", 92, DRV_GRP4),
MT7623_PIN(120, "MSDC0_DAT1", 93, DRV_GRP4),
MT7623_PIN(121, "MSDC0_DAT0", 94, DRV_GRP4),
MT7623_PIN(122, "CEC", 95, DRV_FIXED),
MT7623_PIN(123, "HTPLG", 96, DRV_FIXED),
MT7623_PIN(124, "HDMISCK", 97, DRV_FIXED),
MT7623_PIN(125, "HDMISD", 98, DRV_FIXED),
MT7623_PIN(126, "I2S0_MCLK", 99, DRV_GRP1),
MT7623_PIN(127, "RAMBUF_IDATA0", EINT_NA, DRV_FIXED),
MT7623_PIN(128, "RAMBUF_IDATA1", EINT_NA, DRV_FIXED),
MT7623_PIN(129, "RAMBUF_IDATA2", EINT_NA, DRV_FIXED),
MT7623_PIN(130, "RAMBUF_IDATA3", EINT_NA, DRV_FIXED),
MT7623_PIN(131, "RAMBUF_IDATA4", EINT_NA, DRV_FIXED),
MT7623_PIN(132, "RAMBUF_IDATA5", EINT_NA, DRV_FIXED),
MT7623_PIN(133, "RAMBUF_IDATA6", EINT_NA, DRV_FIXED),
MT7623_PIN(134, "RAMBUF_IDATA7", EINT_NA, DRV_FIXED),
MT7623_PIN(135, "RAMBUF_IDATA8", EINT_NA, DRV_FIXED),
MT7623_PIN(136, "RAMBUF_IDATA9", EINT_NA, DRV_FIXED),
MT7623_PIN(137, "RAMBUF_IDATA10", EINT_NA, DRV_FIXED),
MT7623_PIN(138, "RAMBUF_IDATA11", EINT_NA, DRV_FIXED),
MT7623_PIN(139, "RAMBUF_IDATA12", EINT_NA, DRV_FIXED),
MT7623_PIN(140, "RAMBUF_IDATA13", EINT_NA, DRV_FIXED),
MT7623_PIN(141, "RAMBUF_IDATA14", EINT_NA, DRV_FIXED),
MT7623_PIN(142, "RAMBUF_IDATA15", EINT_NA, DRV_FIXED),
MT7623_PIN(143, "RAMBUF_ODATA0", EINT_NA, DRV_FIXED),
MT7623_PIN(144, "RAMBUF_ODATA1", EINT_NA, DRV_FIXED),
MT7623_PIN(145, "RAMBUF_ODATA2", EINT_NA, DRV_FIXED),
MT7623_PIN(146, "RAMBUF_ODATA3", EINT_NA, DRV_FIXED),
MT7623_PIN(147, "RAMBUF_ODATA4", EINT_NA, DRV_FIXED),
MT7623_PIN(148, "RAMBUF_ODATA5", EINT_NA, DRV_FIXED),
MT7623_PIN(149, "RAMBUF_ODATA6", EINT_NA, DRV_FIXED),
MT7623_PIN(150, "RAMBUF_ODATA7", EINT_NA, DRV_FIXED),
MT7623_PIN(151, "RAMBUF_ODATA8", EINT_NA, DRV_FIXED),
MT7623_PIN(152, "RAMBUF_ODATA9", EINT_NA, DRV_FIXED),
MT7623_PIN(153, "RAMBUF_ODATA10", EINT_NA, DRV_FIXED),
MT7623_PIN(154, "RAMBUF_ODATA11", EINT_NA, DRV_FIXED),
MT7623_PIN(155, "RAMBUF_ODATA12", EINT_NA, DRV_FIXED),
MT7623_PIN(156, "RAMBUF_ODATA13", EINT_NA, DRV_FIXED),
MT7623_PIN(157, "RAMBUF_ODATA14", EINT_NA, DRV_FIXED),
MT7623_PIN(158, "RAMBUF_ODATA15", EINT_NA, DRV_FIXED),
MT7623_PIN(159, "RAMBUF_BE0", EINT_NA, DRV_FIXED),
MT7623_PIN(160, "RAMBUF_BE1", EINT_NA, DRV_FIXED),
MT7623_PIN(161, "AP2PT_INT", EINT_NA, DRV_FIXED),
MT7623_PIN(162, "AP2PT_INT_CLR", EINT_NA, DRV_FIXED),
MT7623_PIN(163, "PT2AP_INT", EINT_NA, DRV_FIXED),
MT7623_PIN(164, "PT2AP_INT_CLR", EINT_NA, DRV_FIXED),
MT7623_PIN(165, "AP2UP_INT", EINT_NA, DRV_FIXED),
MT7623_PIN(166, "AP2UP_INT_CLR", EINT_NA, DRV_FIXED),
MT7623_PIN(167, "UP2AP_INT", EINT_NA, DRV_FIXED),
MT7623_PIN(168, "UP2AP_INT_CLR", EINT_NA, DRV_FIXED),
MT7623_PIN(169, "RAMBUF_ADDR0", EINT_NA, DRV_FIXED),
MT7623_PIN(170, "RAMBUF_ADDR1", EINT_NA, DRV_FIXED),
MT7623_PIN(171, "RAMBUF_ADDR2", EINT_NA, DRV_FIXED),
MT7623_PIN(172, "RAMBUF_ADDR3", EINT_NA, DRV_FIXED),
MT7623_PIN(173, "RAMBUF_ADDR4", EINT_NA, DRV_FIXED),
MT7623_PIN(174, "RAMBUF_ADDR5", EINT_NA, DRV_FIXED),
MT7623_PIN(175, "RAMBUF_ADDR6", EINT_NA, DRV_FIXED),
MT7623_PIN(176, "RAMBUF_ADDR7", EINT_NA, DRV_FIXED),
MT7623_PIN(177, "RAMBUF_ADDR8", EINT_NA, DRV_FIXED),
MT7623_PIN(178, "RAMBUF_ADDR9", EINT_NA, DRV_FIXED),
MT7623_PIN(179, "RAMBUF_ADDR10", EINT_NA, DRV_FIXED),
MT7623_PIN(180, "RAMBUF_RW", EINT_NA, DRV_FIXED),
MT7623_PIN(181, "RAMBUF_LAST", EINT_NA, DRV_FIXED),
MT7623_PIN(182, "RAMBUF_HP", EINT_NA, DRV_FIXED),
MT7623_PIN(183, "RAMBUF_REQ", EINT_NA, DRV_FIXED),
MT7623_PIN(184, "RAMBUF_ALE", EINT_NA, DRV_FIXED),
MT7623_PIN(185, "RAMBUF_DLE", EINT_NA, DRV_FIXED),
MT7623_PIN(186, "RAMBUF_WDLE", EINT_NA, DRV_FIXED),
MT7623_PIN(187, "RAMBUF_O_CLK", EINT_NA, DRV_FIXED),
MT7623_PIN(188, "I2S2_MCLK", 100, DRV_GRP1),
MT7623_PIN(189, "I2S3_DATA", 101, DRV_GRP1),
MT7623_PIN(190, "I2S3_DATA_IN", 102, DRV_GRP1),
MT7623_PIN(191, "I2S3_BCK", 103, DRV_GRP1),
MT7623_PIN(192, "I2S3_LRCK", 104, DRV_GRP1),
MT7623_PIN(193, "I2S3_MCLK", 105, DRV_GRP1),
MT7623_PIN(194, "I2S4_DATA", 106, DRV_GRP1),
MT7623_PIN(195, "I2S4_DATA_IN", 107, DRV_GRP1),
MT7623_PIN(196, "I2S4_BCK", 108, DRV_GRP1),
MT7623_PIN(197, "I2S4_LRCK", 109, DRV_GRP1),
MT7623_PIN(198, "I2S4_MCLK", 110, DRV_GRP1),
MT7623_PIN(199, "SPI1_CLK", 111, DRV_GRP3),
MT7623_PIN(200, "SPDIF_OUT", 112, DRV_GRP1),
MT7623_PIN(201, "SPDIF_IN0", 113, DRV_GRP1),
MT7623_PIN(202, "SPDIF_IN1", 114, DRV_GRP1),
MT7623_PIN(203, "PWM0", 115, DRV_GRP1),
MT7623_PIN(204, "PWM1", 116, DRV_GRP1),
MT7623_PIN(205, "PWM2", 117, DRV_GRP1),
MT7623_PIN(206, "PWM3", 118, DRV_GRP1),
MT7623_PIN(207, "PWM4", 119, DRV_GRP1),
MT7623_PIN(208, "AUD_EXT_CK1", 120, DRV_GRP1),
MT7623_PIN(209, "AUD_EXT_CK2", 121, DRV_GRP1),
MT7623_PIN(210, "AUD_CLOCK", EINT_NA, DRV_GRP3),
MT7623_PIN(211, "DVP_RESET", EINT_NA, DRV_GRP3),
MT7623_PIN(212, "DVP_CLOCK", EINT_NA, DRV_GRP3),
MT7623_PIN(213, "DVP_CS", EINT_NA, DRV_GRP3),
MT7623_PIN(214, "DVP_CK", EINT_NA, DRV_GRP3),
MT7623_PIN(215, "DVP_DI", EINT_NA, DRV_GRP3),
MT7623_PIN(216, "DVP_DO", EINT_NA, DRV_GRP3),
MT7623_PIN(217, "AP_CS", EINT_NA, DRV_GRP3),
MT7623_PIN(218, "AP_CK", EINT_NA, DRV_GRP3),
MT7623_PIN(219, "AP_DI", EINT_NA, DRV_GRP3),
MT7623_PIN(220, "AP_DO", EINT_NA, DRV_GRP3),
MT7623_PIN(221, "DVD_BCLK", EINT_NA, DRV_GRP3),
MT7623_PIN(222, "T8032_CLK", EINT_NA, DRV_GRP3),
MT7623_PIN(223, "AP_BCLK", EINT_NA, DRV_GRP3),
MT7623_PIN(224, "HOST_CS", EINT_NA, DRV_GRP3),
MT7623_PIN(225, "HOST_CK", EINT_NA, DRV_GRP3),
MT7623_PIN(226, "HOST_DO0", EINT_NA, DRV_GRP3),
MT7623_PIN(227, "HOST_DO1", EINT_NA, DRV_GRP3),
MT7623_PIN(228, "SLV_CS", EINT_NA, DRV_GRP3),
MT7623_PIN(229, "SLV_CK", EINT_NA, DRV_GRP3),
MT7623_PIN(230, "SLV_DI0", EINT_NA, DRV_GRP3),
MT7623_PIN(231, "SLV_DI1", EINT_NA, DRV_GRP3),
MT7623_PIN(232, "AP2DSP_INT", EINT_NA, DRV_GRP3),
MT7623_PIN(233, "AP2DSP_INT_CLR", EINT_NA, DRV_GRP3),
MT7623_PIN(234, "DSP2AP_INT", EINT_NA, DRV_GRP3),
MT7623_PIN(235, "DSP2AP_INT_CLR", EINT_NA, DRV_GRP3),
MT7623_PIN(236, "EXT_SDIO3", 122, DRV_GRP1),
MT7623_PIN(237, "EXT_SDIO2", 123, DRV_GRP1),
MT7623_PIN(238, "EXT_SDIO1", 124, DRV_GRP1),
MT7623_PIN(239, "EXT_SDIO0", 125, DRV_GRP1),
MT7623_PIN(240, "EXT_XCS", 126, DRV_GRP1),
MT7623_PIN(241, "EXT_SCK", 127, DRV_GRP1),
MT7623_PIN(242, "URTS2", 128, DRV_GRP1),
MT7623_PIN(243, "UCTS2", 129, DRV_GRP1),
MT7623_PIN(244, "HDMI_SDA_RX", 130, DRV_FIXED),
MT7623_PIN(245, "HDMI_SCL_RX", 131, DRV_FIXED),
MT7623_PIN(246, "MHL_SENCE", 132, DRV_FIXED),
MT7623_PIN(247, "HDMI_HPD_CBUS_RX", 69, DRV_FIXED),
MT7623_PIN(248, "HDMI_TESTOUTP_RX", 133, DRV_GRP1),
MT7623_PIN(249, "MSDC0E_RSTB", 134, DRV_GRP4),
MT7623_PIN(250, "MSDC0E_DAT7", 135, DRV_GRP4),
MT7623_PIN(251, "MSDC0E_DAT6", 136, DRV_GRP4),
MT7623_PIN(252, "MSDC0E_DAT5", 137, DRV_GRP4),
MT7623_PIN(253, "MSDC0E_DAT4", 138, DRV_GRP4),
MT7623_PIN(254, "MSDC0E_DAT3", 139, DRV_GRP4),
MT7623_PIN(255, "MSDC0E_DAT2", 140, DRV_GRP4),
MT7623_PIN(256, "MSDC0E_DAT1", 141, DRV_GRP4),
MT7623_PIN(257, "MSDC0E_DAT0", 142, DRV_GRP4),
MT7623_PIN(258, "MSDC0E_CMD", 143, DRV_GRP4),
MT7623_PIN(259, "MSDC0E_CLK", 144, DRV_GRP4),
MT7623_PIN(260, "MSDC0E_DSL", 145, DRV_GRP4),
MT7623_PIN(261, "MSDC1_INS", 146, DRV_GRP4),
MT7623_PIN(262, "G2_TXEN", 8, DRV_GRP1),
MT7623_PIN(263, "G2_TXD3", 9, DRV_GRP1),
MT7623_PIN(264, "G2_TXD2", 10, DRV_GRP1),
MT7623_PIN(265, "G2_TXD1", 11, DRV_GRP1),
MT7623_PIN(266, "G2_TXD0", EINT_NA, DRV_GRP1),
MT7623_PIN(267, "G2_TXC", EINT_NA, DRV_GRP1),
MT7623_PIN(268, "G2_RXC", EINT_NA, DRV_GRP1),
MT7623_PIN(269, "G2_RXD0", EINT_NA, DRV_GRP1),
MT7623_PIN(270, "G2_RXD1", EINT_NA, DRV_GRP1),
MT7623_PIN(271, "G2_RXD2", EINT_NA, DRV_GRP1),
MT7623_PIN(272, "G2_RXD3", EINT_NA, DRV_GRP1),
MT7623_PIN(273, "ESW_INT", 168, DRV_GRP1),
MT7623_PIN(274, "G2_RXDV", EINT_NA, DRV_GRP1),
MT7623_PIN(275, "MDC", EINT_NA, DRV_GRP1),
MT7623_PIN(276, "MDIO", EINT_NA, DRV_GRP1),
MT7623_PIN(277, "ESW_RST", EINT_NA, DRV_GRP1),
MT7623_PIN(278, "JTAG_RESET", 147, DRV_GRP3),
MT7623_PIN(279, "USB3_RES_BOND", EINT_NA, DRV_GRP1),
};
/* List all groups consisting of these pins dedicated to the enablement of
* certain hardware block and the corresponding mode for all of the pins.
* The hardware probably has multiple combinations of these pinouts.
*/
/* AUDIO EXT CLK */
static int mt7623_aud_ext_clk0_pins[] = { 208, };
static int mt7623_aud_ext_clk0_funcs[] = { 1, };
static int mt7623_aud_ext_clk1_pins[] = { 209, };
static int mt7623_aud_ext_clk1_funcs[] = { 1, };
/* DISP PWM */
static int mt7623_disp_pwm_0_pins[] = { 72, };
static int mt7623_disp_pwm_0_funcs[] = { 5, };
static int mt7623_disp_pwm_1_pins[] = { 203, };
static int mt7623_disp_pwm_1_funcs[] = { 2, };
static int mt7623_disp_pwm_2_pins[] = { 208, };
static int mt7623_disp_pwm_2_funcs[] = { 5, };
/* ESW */
static int mt7623_esw_int_pins[] = { 273, };
static int mt7623_esw_int_funcs[] = { 1, };
static int mt7623_esw_rst_pins[] = { 277, };
static int mt7623_esw_rst_funcs[] = { 1, };
/* EPHY */
static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
269, 270, 271, 272, 274, };
static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* EXT_SDIO */
static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
/* HDMI RX */
static int mt7623_hdmi_rx_pins[] = { 247, 248, };
static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
/* HDMI TX */
static int mt7623_hdmi_cec_pins[] = { 122, };
static int mt7623_hdmi_cec_funcs[] = { 1, };
static int mt7623_hdmi_htplg_pins[] = { 123, };
static int mt7623_hdmi_htplg_funcs[] = { 1, };
static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
/* I2C */
static int mt7623_i2c0_pins[] = { 75, 76, };
static int mt7623_i2c0_funcs[] = { 1, 1, };
static int mt7623_i2c1_0_pins[] = { 57, 58, };
static int mt7623_i2c1_0_funcs[] = { 1, 1, };
static int mt7623_i2c1_1_pins[] = { 242, 243, };
static int mt7623_i2c1_1_funcs[] = { 4, 4, };
static int mt7623_i2c1_2_pins[] = { 85, 86, };
static int mt7623_i2c1_2_funcs[] = { 3, 3, };
static int mt7623_i2c1_3_pins[] = { 105, 106, };
static int mt7623_i2c1_3_funcs[] = { 3, 3, };
static int mt7623_i2c1_4_pins[] = { 124, 125, };
static int mt7623_i2c1_4_funcs[] = { 4, 4, };
static int mt7623_i2c2_0_pins[] = { 77, 78, };
static int mt7623_i2c2_0_funcs[] = { 1, 1, };
static int mt7623_i2c2_1_pins[] = { 89, 90, };
static int mt7623_i2c2_1_funcs[] = { 3, 3, };
static int mt7623_i2c2_2_pins[] = { 109, 110, };
static int mt7623_i2c2_2_funcs[] = { 3, 3, };
static int mt7623_i2c2_3_pins[] = { 122, 123, };
static int mt7623_i2c2_3_funcs[] = { 4, 4, };
/* I2S */
static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
static int mt7623_i2s2_data_in_pins[] = { 51, };
static int mt7623_i2s2_data_in_funcs[] = { 1, };
static int mt7623_i2s2_data_0_pins[] = { 203, };
static int mt7623_i2s2_data_0_funcs[] = { 9, };
static int mt7623_i2s2_data_1_pins[] = { 38, };
static int mt7623_i2s2_data_1_funcs[] = { 4, };
static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
static int mt7623_i2s3_data_in_pins[] = { 190, };
static int mt7623_i2s3_data_in_funcs[] = { 1, };
static int mt7623_i2s3_data_0_pins[] = { 204, };
static int mt7623_i2s3_data_0_funcs[] = { 9, };
static int mt7623_i2s3_data_1_pins[] = { 2, };
static int mt7623_i2s3_data_1_funcs[] = { 0, };
static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
/* IR */
static int mt7623_ir_pins[] = { 46, };
static int mt7623_ir_funcs[] = { 1, };
/* LCD */
static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
99, 100, };
static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static int mt7623_dsi_te_pins[] = { 84, };
static int mt7623_dsi_te_funcs[] = { 1, };
static int mt7623_lcm_rst_pins[] = { 83, };
static int mt7623_lcm_rst_funcs[] = { 1, };
/* MDC/MDIO */
static int mt7623_mdc_mdio_pins[] = { 275, 276, };
static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
/* MSDC */
static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
119, 120, 121, };
static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
static int mt7623_msdc1_ins_pins[] = { 261, };
static int mt7623_msdc1_ins_funcs[] = { 1, };
static int mt7623_msdc1_wp_0_pins[] = { 29, };
static int mt7623_msdc1_wp_0_funcs[] = { 1, };
static int mt7623_msdc1_wp_1_pins[] = { 55, };
static int mt7623_msdc1_wp_1_funcs[] = { 3, };
static int mt7623_msdc1_wp_2_pins[] = { 209, };
static int mt7623_msdc1_wp_2_funcs[] = { 2, };
static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
257, 258, 259, 260, };
static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* NAND */
static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
116, 117, 118, 119, 120, 121, };
static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, };
static int mt7623_nandc_ceb0_pins[] = { 45, };
static int mt7623_nandc_ceb0_funcs[] = { 1, };
static int mt7623_nandc_ceb1_pins[] = { 44, };
static int mt7623_nandc_ceb1_funcs[] = { 1, };
/* RTC */
static int mt7623_rtc_pins[] = { 10, };
static int mt7623_rtc_funcs[] = { 1, };
/* OTG */
static int mt7623_otg_iddig0_0_pins[] = { 29, };
static int mt7623_otg_iddig0_0_funcs[] = { 1, };
static int mt7623_otg_iddig0_1_pins[] = { 44, };
static int mt7623_otg_iddig0_1_funcs[] = { 2, };
static int mt7623_otg_iddig0_2_pins[] = { 236, };
static int mt7623_otg_iddig0_2_funcs[] = { 2, };
static int mt7623_otg_iddig1_0_pins[] = { 27, };
static int mt7623_otg_iddig1_0_funcs[] = { 2, };
static int mt7623_otg_iddig1_1_pins[] = { 47, };
static int mt7623_otg_iddig1_1_funcs[] = { 2, };
static int mt7623_otg_iddig1_2_pins[] = { 238, };
static int mt7623_otg_iddig1_2_funcs[] = { 2, };
static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
/* PCIE */
static int mt7623_pcie0_0_perst_pins[] = { 208, };
static int mt7623_pcie0_0_perst_funcs[] = { 3, };
static int mt7623_pcie0_1_perst_pins[] = { 22, };
static int mt7623_pcie0_1_perst_funcs[] = { 2, };
static int mt7623_pcie1_0_perst_pins[] = { 209, };
static int mt7623_pcie1_0_perst_funcs[] = { 3, };
static int mt7623_pcie1_1_perst_pins[] = { 23, };
static int mt7623_pcie1_1_perst_funcs[] = { 2, };
static int mt7623_pcie2_0_perst_pins[] = { 24, };
static int mt7623_pcie2_0_perst_funcs[] = { 2, };
static int mt7623_pcie2_1_perst_pins[] = { 29, };
static int mt7623_pcie2_1_perst_funcs[] = { 6, };
static int mt7623_pcie0_0_wake_pins[] = { 28, };
static int mt7623_pcie0_0_wake_funcs[] = { 6, };
static int mt7623_pcie0_1_wake_pins[] = { 251, };
static int mt7623_pcie0_1_wake_funcs[] = { 6, };
static int mt7623_pcie1_0_wake_pins[] = { 27, };
static int mt7623_pcie1_0_wake_funcs[] = { 6, };
static int mt7623_pcie1_1_wake_pins[] = { 253, };
static int mt7623_pcie1_1_wake_funcs[] = { 6, };
static int mt7623_pcie2_0_wake_pins[] = { 26, };
static int mt7623_pcie2_0_wake_funcs[] = { 6, };
static int mt7623_pcie2_1_wake_pins[] = { 255, };
static int mt7623_pcie2_1_wake_funcs[] = { 6, };
static int mt7623_pcie0_clkreq_pins[] = { 250, };
static int mt7623_pcie0_clkreq_funcs[] = { 6, };
static int mt7623_pcie1_clkreq_pins[] = { 252, };
static int mt7623_pcie1_clkreq_funcs[] = { 6, };
static int mt7623_pcie2_clkreq_pins[] = { 254, };
static int mt7623_pcie2_clkreq_funcs[] = { 6, };
/* the pcie_*_rev are only used for MT7623 */
static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
/* PCM */
static int mt7623_pcm_clk_0_pins[] = { 18, };
static int mt7623_pcm_clk_0_funcs[] = { 1, };
static int mt7623_pcm_clk_1_pins[] = { 17, };
static int mt7623_pcm_clk_1_funcs[] = { 3, };
static int mt7623_pcm_clk_2_pins[] = { 35, };
static int mt7623_pcm_clk_2_funcs[] = { 3, };
static int mt7623_pcm_clk_3_pins[] = { 50, };
static int mt7623_pcm_clk_3_funcs[] = { 3, };
static int mt7623_pcm_clk_4_pins[] = { 74, };
static int mt7623_pcm_clk_4_funcs[] = { 3, };
static int mt7623_pcm_clk_5_pins[] = { 191, };
static int mt7623_pcm_clk_5_funcs[] = { 3, };
static int mt7623_pcm_clk_6_pins[] = { 196, };
static int mt7623_pcm_clk_6_funcs[] = { 3, };
static int mt7623_pcm_sync_0_pins[] = { 19, };
static int mt7623_pcm_sync_0_funcs[] = { 1, };
static int mt7623_pcm_sync_1_pins[] = { 30, };
static int mt7623_pcm_sync_1_funcs[] = { 3, };
static int mt7623_pcm_sync_2_pins[] = { 36, };
static int mt7623_pcm_sync_2_funcs[] = { 3, };
static int mt7623_pcm_sync_3_pins[] = { 52, };
static int mt7623_pcm_sync_3_funcs[] = { 31, };
static int mt7623_pcm_sync_4_pins[] = { 73, };
static int mt7623_pcm_sync_4_funcs[] = { 3, };
static int mt7623_pcm_sync_5_pins[] = { 192, };
static int mt7623_pcm_sync_5_funcs[] = { 3, };
static int mt7623_pcm_sync_6_pins[] = { 197, };
static int mt7623_pcm_sync_6_funcs[] = { 3, };
static int mt7623_pcm_rx_0_pins[] = { 20, };
static int mt7623_pcm_rx_0_funcs[] = { 1, };
static int mt7623_pcm_rx_1_pins[] = { 16, };
static int mt7623_pcm_rx_1_funcs[] = { 3, };
static int mt7623_pcm_rx_2_pins[] = { 34, };
static int mt7623_pcm_rx_2_funcs[] = { 3, };
static int mt7623_pcm_rx_3_pins[] = { 51, };
static int mt7623_pcm_rx_3_funcs[] = { 3, };
static int mt7623_pcm_rx_4_pins[] = { 72, };
static int mt7623_pcm_rx_4_funcs[] = { 3, };
static int mt7623_pcm_rx_5_pins[] = { 190, };
static int mt7623_pcm_rx_5_funcs[] = { 3, };
static int mt7623_pcm_rx_6_pins[] = { 195, };
static int mt7623_pcm_rx_6_funcs[] = { 3, };
static int mt7623_pcm_tx_0_pins[] = { 21, };
static int mt7623_pcm_tx_0_funcs[] = { 1, };
static int mt7623_pcm_tx_1_pins[] = { 32, };
static int mt7623_pcm_tx_1_funcs[] = { 3, };
static int mt7623_pcm_tx_2_pins[] = { 33, };
static int mt7623_pcm_tx_2_funcs[] = { 3, };
static int mt7623_pcm_tx_3_pins[] = { 38, };
static int mt7623_pcm_tx_3_funcs[] = { 3, };
static int mt7623_pcm_tx_4_pins[] = { 49, };
static int mt7623_pcm_tx_4_funcs[] = { 3, };
static int mt7623_pcm_tx_5_pins[] = { 189, };
static int mt7623_pcm_tx_5_funcs[] = { 3, };
static int mt7623_pcm_tx_6_pins[] = { 194, };
static int mt7623_pcm_tx_6_funcs[] = { 3, };
/* PWM */
static int mt7623_pwm_ch1_0_pins[] = { 203, };
static int mt7623_pwm_ch1_0_funcs[] = { 1, };
static int mt7623_pwm_ch1_1_pins[] = { 208, };
static int mt7623_pwm_ch1_1_funcs[] = { 2, };
static int mt7623_pwm_ch1_2_pins[] = { 72, };
static int mt7623_pwm_ch1_2_funcs[] = { 4, };
static int mt7623_pwm_ch1_3_pins[] = { 88, };
static int mt7623_pwm_ch1_3_funcs[] = { 3, };
static int mt7623_pwm_ch1_4_pins[] = { 108, };
static int mt7623_pwm_ch1_4_funcs[] = { 3, };
static int mt7623_pwm_ch2_0_pins[] = { 204, };
static int mt7623_pwm_ch2_0_funcs[] = { 1, };
static int mt7623_pwm_ch2_1_pins[] = { 53, };
static int mt7623_pwm_ch2_1_funcs[] = { 5, };
static int mt7623_pwm_ch2_2_pins[] = { 88, };
static int mt7623_pwm_ch2_2_funcs[] = { 6, };
static int mt7623_pwm_ch2_3_pins[] = { 108, };
static int mt7623_pwm_ch2_3_funcs[] = { 6, };
static int mt7623_pwm_ch2_4_pins[] = { 209, };
static int mt7623_pwm_ch2_4_funcs[] = { 5, };
static int mt7623_pwm_ch3_0_pins[] = { 205, };
static int mt7623_pwm_ch3_0_funcs[] = { 1, };
static int mt7623_pwm_ch3_1_pins[] = { 55, };
static int mt7623_pwm_ch3_1_funcs[] = { 5, };
static int mt7623_pwm_ch3_2_pins[] = { 89, };
static int mt7623_pwm_ch3_2_funcs[] = { 6, };
static int mt7623_pwm_ch3_3_pins[] = { 109, };
static int mt7623_pwm_ch3_3_funcs[] = { 6, };
static int mt7623_pwm_ch4_0_pins[] = { 206, };
static int mt7623_pwm_ch4_0_funcs[] = { 1, };
static int mt7623_pwm_ch4_1_pins[] = { 90, };
static int mt7623_pwm_ch4_1_funcs[] = { 6, };
static int mt7623_pwm_ch4_2_pins[] = { 110, };
static int mt7623_pwm_ch4_2_funcs[] = { 6, };
static int mt7623_pwm_ch4_3_pins[] = { 124, };
static int mt7623_pwm_ch4_3_funcs[] = { 5, };
static int mt7623_pwm_ch5_0_pins[] = { 207, };
static int mt7623_pwm_ch5_0_funcs[] = { 1, };
static int mt7623_pwm_ch5_1_pins[] = { 125, };
static int mt7623_pwm_ch5_1_funcs[] = { 5, };
/* PWRAP */
static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
/* SPDIF */
static int mt7623_spdif_in0_0_pins[] = { 56, };
static int mt7623_spdif_in0_0_funcs[] = { 3, };
static int mt7623_spdif_in0_1_pins[] = { 201, };
static int mt7623_spdif_in0_1_funcs[] = { 1, };
static int mt7623_spdif_in1_0_pins[] = { 54, };
static int mt7623_spdif_in1_0_funcs[] = { 3, };
static int mt7623_spdif_in1_1_pins[] = { 202, };
static int mt7623_spdif_in1_1_funcs[] = { 1, };
static int mt7623_spdif_out_pins[] = { 202, };
static int mt7623_spdif_out_funcs[] = { 1, };
/* SPI */
static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
/* UART */
static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
/* Watchdog */
static int mt7623_watchdog_0_pins[] = { 11, };
static int mt7623_watchdog_0_funcs[] = { 1, };
static int mt7623_watchdog_1_pins[] = { 121, };
static int mt7623_watchdog_1_funcs[] = { 5, };
static const struct group_desc mt7623_groups[] = {
PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
PINCTRL_PIN_GROUP("ir", mt7623_ir),
PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
};
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0",
"aud_ext_clk1", };
static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0", "disp_pwm_1",
"disp_pwm_2", };
static const char *mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
"ephy", "mdc_mdio", };
static const char *mt7623_ext_sdio_groups[] = { "ext_sdio", };
static const char *mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
"hdmi_i2c", "hdmi_rx",
"hdmi_rx_i2c", };
static const char *mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
"i2c1_2", "i2c1_3", "i2c1_4",
"i2c2_0", "i2c2_1", "i2c2_2",
"i2c2_3", };
static const char *mt7623_i2s_groups[] = { "i2s0", "i2s1",
"i2s2_bclk_lrclk_mclk",
"i2s3_bclk_lrclk_mclk",
"i2s4", "i2s5",
"i2s2_data_in", "i2s3_data_in",
"i2s2_data_0", "i2s2_data_1",
"i2s3_data_0", "i2s3_data_1", };
static const char *mt7623_ir_groups[] = { "ir", };
static const char *mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", "mipi_tx", };
static const char *mt7623_msdc_groups[] = { "msdc0", "msdc1", "msdc1_ins",
"msdc1_wp_0", "msdc1_wp_1",
"msdc1_wp_2", "msdc2",
"msdc3", };
static const char *mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
"nandc_ceb1", };
static const char *mt7623_otg_groups[] = { "otg_iddig0_0", "otg_iddig0_1",
"otg_iddig0_2", "otg_iddig1_0",
"otg_iddig1_1", "otg_iddig1_2",
"otg_drv_vbus0_0",
"otg_drv_vbus0_1",
"otg_drv_vbus0_2",
"otg_drv_vbus1_0",
"otg_drv_vbus1_1",
"otg_drv_vbus1_2", };
static const char *mt7623_pcie_groups[] = { "pcie0_0_perst", "pcie0_1_perst",
"pcie1_0_perst", "pcie1_1_perst",
"pcie2_0_perst", "pcie2_1_perst",
"pcie0_0_rev_perst",
"pcie0_1_rev_perst",
"pcie1_0_rev_perst",
"pcie1_1_rev_perst",
"pcie2_0_rev_perst",
"pcie2_1_rev_perst",
"pcie0_0_wake", "pcie0_1_wake",
"pcie2_0_wake", "pcie2_1_wake",
"pcie0_clkreq", "pcie1_clkreq",
"pcie2_clkreq", };
static const char *mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
"pcm_clk_2", "pcm_clk_3",
"pcm_clk_4", "pcm_clk_5",
"pcm_clk_6", "pcm_sync_0",
"pcm_sync_1", "pcm_sync_2",
"pcm_sync_3", "pcm_sync_4",
"pcm_sync_5", "pcm_sync_6",
"pcm_rx_0", "pcm_rx_1",
"pcm_rx_2", "pcm_rx_3",
"pcm_rx_4", "pcm_rx_5",
"pcm_rx_6", "pcm_tx_0",
"pcm_tx_1", "pcm_tx_2",
"pcm_tx_3", "pcm_tx_4",
"pcm_tx_5", "pcm_tx_6", };
static const char *mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
"pwm_ch1_2", "pwm_ch2_0",
"pwm_ch2_1", "pwm_ch2_2",
"pwm_ch3_0", "pwm_ch3_1",
"pwm_ch3_2", "pwm_ch4_0",
"pwm_ch4_1", "pwm_ch4_2",
"pwm_ch4_3", "pwm_ch5_0",
"pwm_ch5_1", "pwm_ch5_2",
"pwm_ch6_0", "pwm_ch6_1",
"pwm_ch6_2", "pwm_ch6_3",
"pwm_ch7_0", "pwm_ch7_1",
"pwm_ch7_2", };
static const char *mt7623_pwrap_groups[] = { "pwrap", };
static const char *mt7623_rtc_groups[] = { "rtc", };
static const char *mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
static const char *mt7623_spdif_groups[] = { "spdif_in0_0", "spdif_in0_1",
"spdif_in1_0", "spdif_in1_1",
"spdif_out", };
static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd",
"uart0_1_txd_rxd",
"uart0_2_txd_rxd",
"uart0_3_txd_rxd",
"uart1_0_txd_rxd",
"uart1_1_txd_rxd",
"uart1_2_txd_rxd",
"uart2_0_txd_rxd",
"uart2_1_txd_rxd",
"uart3_txd_rxd",
"uart0_rts_cts",
"uart1_rts_cts",
"uart2_rts_cts",
"uart3_rts_cts", };
static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
static const struct function_desc mt7623_functions[] = {
{"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
{"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
{"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
{"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
{"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
{"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
{"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
{"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
{"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
{"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
{"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
{"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
{"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
{"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
{"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
{"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
{"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
{"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
{"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
{"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
};
static const struct mtk_eint_hw mt7623_eint_hw = {
.port_mask = 6,
.ports = 6,
.ap_num = 169,
.db_cnt = 20,
.db_time = debounce_time_mt2701,
};
static struct mtk_pin_soc mt7623_data = {
.reg_cal = mt7623_reg_cals,
.pins = mt7623_pins,
.npins = ARRAY_SIZE(mt7623_pins),
.grps = mt7623_groups,
.ngrps = ARRAY_SIZE(mt7623_groups),
.funcs = mt7623_functions,
.nfuncs = ARRAY_SIZE(mt7623_functions),
.eint_hw = &mt7623_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
/*
* There are some specific pins have mux functions greater than 8,
* and if we want to switch thees high modes we need to disable
* bonding constraints firstly.
*/
static void mt7623_bonding_disable(struct platform_device *pdev)
{
struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
}
static const struct of_device_id mt7623_pctrl_match[] = {
{ .compatible = "mediatek,mt7623-moore-pinctrl", },
{}
};
static int mt7623_pinctrl_probe(struct platform_device *pdev)
{
int err;
err = mtk_moore_pinctrl_probe(pdev, &mt7623_data);
if (err)
return err;
mt7623_bonding_disable(pdev);
return 0;
}
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt7623_pinctrl_probe,
.driver = {
.name = "mt7623-moore-pinctrl",
.of_match_table = mt7623_pctrl_match,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7623.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* The MT7629 driver based on Linux generic pinctrl binding.
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <[email protected]>
*/
#include "pinctrl-moore.h"
#define MT7629_PIN(_number, _name, _eint_n) \
MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
};
static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
};
static const struct mtk_pin_desc mt7629_pins[] = {
MT7629_PIN(0, "TOP_5G_CLK", 53),
MT7629_PIN(1, "TOP_5G_DATA", 54),
MT7629_PIN(2, "WF0_5G_HB0", 55),
MT7629_PIN(3, "WF0_5G_HB1", 56),
MT7629_PIN(4, "WF0_5G_HB2", 57),
MT7629_PIN(5, "WF0_5G_HB3", 58),
MT7629_PIN(6, "WF0_5G_HB4", 59),
MT7629_PIN(7, "WF0_5G_HB5", 60),
MT7629_PIN(8, "WF0_5G_HB6", 61),
MT7629_PIN(9, "XO_REQ", 9),
MT7629_PIN(10, "TOP_RST_N", 10),
MT7629_PIN(11, "SYS_WATCHDOG", 11),
MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
MT7629_PIN(17, "WF2G_LED_N", 17),
MT7629_PIN(18, "WF5G_LED_N", 18),
MT7629_PIN(19, "I2C_SDA", 19),
MT7629_PIN(20, "I2C_SCL", 20),
MT7629_PIN(21, "GPIO_9", 21),
MT7629_PIN(22, "GPIO_10", 22),
MT7629_PIN(23, "GPIO_11", 23),
MT7629_PIN(24, "GPIO_12", 24),
MT7629_PIN(25, "UART1_TXD", 25),
MT7629_PIN(26, "UART1_RXD", 26),
MT7629_PIN(27, "UART1_CTS", 27),
MT7629_PIN(28, "UART1_RTS", 28),
MT7629_PIN(29, "UART2_TXD", 29),
MT7629_PIN(30, "UART2_RXD", 30),
MT7629_PIN(31, "UART2_CTS", 31),
MT7629_PIN(32, "UART2_RTS", 32),
MT7629_PIN(33, "MDI_TP_P1", 33),
MT7629_PIN(34, "MDI_TN_P1", 34),
MT7629_PIN(35, "MDI_RP_P1", 35),
MT7629_PIN(36, "MDI_RN_P1", 36),
MT7629_PIN(37, "MDI_RP_P2", 37),
MT7629_PIN(38, "MDI_RN_P2", 38),
MT7629_PIN(39, "MDI_TP_P2", 39),
MT7629_PIN(40, "MDI_TN_P2", 40),
MT7629_PIN(41, "MDI_TP_P3", 41),
MT7629_PIN(42, "MDI_TN_P3", 42),
MT7629_PIN(43, "MDI_RP_P3", 43),
MT7629_PIN(44, "MDI_RN_P3", 44),
MT7629_PIN(45, "MDI_RP_P4", 45),
MT7629_PIN(46, "MDI_RN_P4", 46),
MT7629_PIN(47, "MDI_TP_P4", 47),
MT7629_PIN(48, "MDI_TN_P4", 48),
MT7629_PIN(49, "SMI_MDC", 49),
MT7629_PIN(50, "SMI_MDIO", 50),
MT7629_PIN(51, "PCIE_PERESET_N", 51),
MT7629_PIN(52, "PWM_0", 52),
MT7629_PIN(53, "GPIO_0", 0),
MT7629_PIN(54, "GPIO_1", 1),
MT7629_PIN(55, "GPIO_2", 2),
MT7629_PIN(56, "GPIO_3", 3),
MT7629_PIN(57, "GPIO_4", 4),
MT7629_PIN(58, "GPIO_5", 5),
MT7629_PIN(59, "GPIO_6", 6),
MT7629_PIN(60, "GPIO_7", 7),
MT7629_PIN(61, "GPIO_8", 8),
MT7629_PIN(62, "SPI_CLK", 62),
MT7629_PIN(63, "SPI_CS", 63),
MT7629_PIN(64, "SPI_MOSI", 64),
MT7629_PIN(65, "SPI_MISO", 65),
MT7629_PIN(66, "SPI_WP", 66),
MT7629_PIN(67, "SPI_HOLD", 67),
MT7629_PIN(68, "UART0_TXD", 68),
MT7629_PIN(69, "UART0_RXD", 69),
MT7629_PIN(70, "TOP_2G_CLK", 70),
MT7629_PIN(71, "TOP_2G_DATA", 71),
MT7629_PIN(72, "WF0_2G_HB0", 72),
MT7629_PIN(73, "WF0_2G_HB1", 73),
MT7629_PIN(74, "WF0_2G_HB2", 74),
MT7629_PIN(75, "WF0_2G_HB3", 75),
MT7629_PIN(76, "WF0_2G_HB4", 76),
MT7629_PIN(77, "WF0_2G_HB5", 77),
MT7629_PIN(78, "WF0_2G_HB6", 78),
};
/* List all groups consisting of these pins dedicated to the enablement of
* certain hardware block and the corresponding mode for all of the pins.
* The hardware probably has multiple combinations of these pinouts.
*/
/* LED for EPHY */
static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
static int mt7629_ephy_led0_pins[] = { 12, };
static int mt7629_ephy_led0_funcs[] = { 1, };
static int mt7629_ephy_led1_pins[] = { 13, };
static int mt7629_ephy_led1_funcs[] = { 1, };
static int mt7629_ephy_led2_pins[] = { 14, };
static int mt7629_ephy_led2_funcs[] = { 1, };
static int mt7629_ephy_led3_pins[] = { 15, };
static int mt7629_ephy_led3_funcs[] = { 1, };
static int mt7629_ephy_led4_pins[] = { 16, };
static int mt7629_ephy_led4_funcs[] = { 1, };
static int mt7629_wf2g_led_pins[] = { 17, };
static int mt7629_wf2g_led_funcs[] = { 1, };
static int mt7629_wf5g_led_pins[] = { 18, };
static int mt7629_wf5g_led_funcs[] = { 1, };
/* Watchdog */
static int mt7629_watchdog_pins[] = { 11, };
static int mt7629_watchdog_funcs[] = { 1, };
/* LED for GPHY */
static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
static int mt7629_gphy_led1_0_pins[] = { 21, };
static int mt7629_gphy_led1_0_funcs[] = { 2, };
static int mt7629_gphy_led2_0_pins[] = { 22, };
static int mt7629_gphy_led2_0_funcs[] = { 2, };
static int mt7629_gphy_led3_0_pins[] = { 23, };
static int mt7629_gphy_led3_0_funcs[] = { 2, };
static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
static int mt7629_gphy_led1_1_pins[] = { 57, };
static int mt7629_gphy_led1_1_funcs[] = { 1, };
static int mt7629_gphy_led2_1_pins[] = { 58, };
static int mt7629_gphy_led2_1_funcs[] = { 1, };
static int mt7629_gphy_led3_1_pins[] = { 59, };
static int mt7629_gphy_led3_1_funcs[] = { 1, };
/* I2C */
static int mt7629_i2c_0_pins[] = { 19, 20, };
static int mt7629_i2c_0_funcs[] = { 1, 1, };
static int mt7629_i2c_1_pins[] = { 53, 54, };
static int mt7629_i2c_1_funcs[] = { 1, 1, };
/* SPI */
static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
static int mt7629_spi_wp_pins[] = { 66, };
static int mt7629_spi_wp_funcs[] = { 1, };
static int mt7629_spi_hold_pins[] = { 67, };
static int mt7629_spi_hold_funcs[] = { 1, };
/* UART */
static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
/* MDC/MDIO */
static int mt7629_mdc_mdio_pins[] = { 49, 50, };
static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
/* PCIE */
static int mt7629_pcie_pereset_pins[] = { 51, };
static int mt7629_pcie_pereset_funcs[] = { 1, };
static int mt7629_pcie_wake_pins[] = { 55, };
static int mt7629_pcie_wake_funcs[] = { 1, };
static int mt7629_pcie_clkreq_pins[] = { 56, };
static int mt7629_pcie_clkreq_funcs[] = { 1, };
/* PWM */
static int mt7629_pwm_0_pins[] = { 52, };
static int mt7629_pwm_0_funcs[] = { 1, };
static int mt7629_pwm_1_pins[] = { 61, };
static int mt7629_pwm_1_funcs[] = { 2, };
/* WF 2G */
static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
/* WF 5G */
static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* SNFI */
static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
/* SPI NOR */
static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
static const struct group_desc mt7629_groups[] = {
PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
};
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
"ephy_led1", "ephy_led2",
"ephy_led3", "ephy_led4",
"wf2g_led", "wf5g_led",
"gphy_leds_0", "gphy_led1_0",
"gphy_led2_0", "gphy_led3_0",
"gphy_leds_1", "gphy_led1_1",
"gphy_led2_1", "gphy_led3_1",};
static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
"pcie_clkreq", };
static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
"spi_hold", };
static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
"uart1_1_txd_rxd",
"uart2_0_txd_rxd",
"uart2_1_txd_rxd",
"uart1_0_cts_rts",
"uart1_1_cts_rts",
"uart2_0_cts_rts",
"uart2_1_cts_rts",
"uart0_txd_rxd", };
static const char *mt7629_wdt_groups[] = { "watchdog", };
static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
static const struct function_desc mt7629_functions[] = {
{"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
{"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
{"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
{"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
{"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
{"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
{"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
{"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
{"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
{"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
};
static const struct mtk_eint_hw mt7629_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = ARRAY_SIZE(mt7629_pins),
.db_cnt = 16,
.db_time = debounce_time_mt2701,
};
static struct mtk_pin_soc mt7629_data = {
.reg_cal = mt7629_reg_cals,
.pins = mt7629_pins,
.npins = ARRAY_SIZE(mt7629_pins),
.grps = mt7629_groups,
.ngrps = ARRAY_SIZE(mt7629_groups),
.funcs = mt7629_functions,
.nfuncs = ARRAY_SIZE(mt7629_functions),
.eint_hw = &mt7629_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
};
static const struct of_device_id mt7629_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt7629-pinctrl", },
{}
};
static int mt7629_pinctrl_probe(struct platform_device *pdev)
{
return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
}
static struct platform_driver mt7629_pinctrl_driver = {
.driver = {
.name = "mt7629-pinctrl",
.of_match_table = mt7629_pinctrl_of_match,
},
.probe = mt7629_pinctrl_probe,
};
static int __init mt7629_pinctrl_init(void)
{
return platform_driver_register(&mt7629_pinctrl_driver);
}
arch_initcall(mt7629_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7629.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define RT3883_GPIO_MODE_UART0_SHIFT 2
#define RT3883_GPIO_MODE_UART0_MASK 0x7
#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
#define RT3883_GPIO_MODE_UARTF 0x0
#define RT3883_GPIO_MODE_PCM_UARTF 0x1
#define RT3883_GPIO_MODE_PCM_I2S 0x2
#define RT3883_GPIO_MODE_I2S_UARTF 0x3
#define RT3883_GPIO_MODE_PCM_GPIO 0x4
#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
#define RT3883_GPIO_MODE_GPIO_I2S 0x6
#define RT3883_GPIO_MODE_GPIO 0x7
#define RT3883_GPIO_MODE_I2C 0
#define RT3883_GPIO_MODE_SPI 1
#define RT3883_GPIO_MODE_UART1 5
#define RT3883_GPIO_MODE_JTAG 6
#define RT3883_GPIO_MODE_MDIO 7
#define RT3883_GPIO_MODE_GE1 9
#define RT3883_GPIO_MODE_GE2 10
#define RT3883_GPIO_MODE_PCI_SHIFT 11
#define RT3883_GPIO_MODE_PCI_MASK 0x7
#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
static struct mtmips_pmx_func uartf_grp[] = {
FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) };
static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
static struct mtmips_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) };
static struct mtmips_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) };
static struct mtmips_pmx_func pci_grp[] = {
FUNC("pci-dev", 0, 40, 32),
FUNC("pci-host2", 1, 40, 32),
FUNC("pci-host1", 2, 40, 32),
FUNC("pci-fnc", 3, 40, 32)
};
static struct mtmips_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) };
static struct mtmips_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) };
static struct mtmips_pmx_group rt3883_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C),
GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI),
GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK,
RT3883_GPIO_MODE_UART0_SHIFT),
GRP("uartlite", uartlite_grp, 1, RT3883_GPIO_MODE_UART1),
GRP("jtag", jtag_grp, 1, RT3883_GPIO_MODE_JTAG),
GRP("mdio", mdio_grp, 1, RT3883_GPIO_MODE_MDIO),
GRP("lna a", lna_a_grp, 1, RT3883_GPIO_MODE_LNA_A),
GRP("lna g", lna_g_grp, 1, RT3883_GPIO_MODE_LNA_G),
GRP("pci", pci_grp, RT3883_GPIO_MODE_PCI_MASK,
RT3883_GPIO_MODE_PCI_SHIFT),
GRP("ge1", ge1_grp, 1, RT3883_GPIO_MODE_GE1),
GRP("ge2", ge2_grp, 1, RT3883_GPIO_MODE_GE2),
{ 0 }
};
static int rt3883_pinctrl_probe(struct platform_device *pdev)
{
return mtmips_pinctrl_init(pdev, rt3883_pinmux_data);
}
static const struct of_device_id rt3883_pinctrl_match[] = {
{ .compatible = "ralink,rt3883-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match);
static struct platform_driver rt3883_pinctrl_driver = {
.probe = rt3883_pinctrl_probe,
.driver = {
.name = "rt3883-pinctrl",
.of_match_table = rt3883_pinctrl_match,
},
};
static int __init rt3883_pinctrl_init(void)
{
return platform_driver_register(&rt3883_pinctrl_driver);
}
core_initcall_sync(rt3883_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-rt3883.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
* bindings for MediaTek SoC.
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Sean Wang <[email protected]>
* Zhiyong Tao <[email protected]>
* Hongzhou.Yang <[email protected]>
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/consumer.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-paris.h"
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
/* Custom pinconf parameters */
#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
{"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
};
#endif
static const char * const mtk_gpio_functions[] = {
"func0", "func1", "func2", "func3",
"func4", "func5", "func6", "func7",
"func8", "func9", "func10", "func11",
"func12", "func13", "func14", "func15",
};
/*
* This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
* and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
*
* The custom value encodes three hardware bits as follows:
*
* | Bits |
* | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
* ------------------------------------------------
* | x | x | 0 | disabled, use standard drive strength
* -------------------------------------
* | 0 | 0 | 1 | 125 uA
* | 0 | 1 | 1 | 250 uA
* | 1 | 0 | 1 | 500 uA
* | 1 | 1 | 1 | 1000 uA
*/
static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
static int mtk_drv_adv_to_uA(int val)
{
/* This should never happen. */
if (WARN_ON_ONCE(val < 0 || val > 7))
return -EINVAL;
/* Bit 0 simply enables this hardware part */
if (!(val & BIT(0)))
return -EINVAL;
return mtk_drv_adv_uA[(val >> 1)];
}
static int mtk_drv_uA_to_adv(int val)
{
switch (val) {
case 125:
return 0x1;
case 250:
return 0x3;
case 500:
return 0x5;
case 1000:
return 0x7;
}
return -EINVAL;
}
static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
hw->soc->gpio_m);
}
static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
/* hardware would take 0 as input direction */
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
}
static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int pullup, reg, err = -ENOTSUPP, ret = 1;
const struct mtk_pin_desc *desc;
if (pin >= hw->soc->npins)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!hw->soc->bias_get_combo)
break;
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
if (err)
break;
if (ret == MTK_PUPD_SET_R1R0_00)
ret = MTK_DISABLE;
if (param == PIN_CONFIG_BIAS_DISABLE) {
if (ret != MTK_DISABLE)
err = -EINVAL;
} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
if (!pullup || ret == MTK_DISABLE)
err = -EINVAL;
} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
if (pullup || ret == MTK_DISABLE)
err = -EINVAL;
}
break;
case PIN_CONFIG_SLEW_RATE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
if (err)
break;
/* CONFIG Current direction return value
* ------------- ----------------- ----------------------
* OUTPUT_ENABLE output 1 (= HW value)
* input 0 (= HW value)
* INPUT_ENABLE output 0 (= reverse HW value)
* input 1 (= reverse HW value)
*/
if (param == PIN_CONFIG_INPUT_ENABLE)
ret = !ret;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
if (err)
break;
/* return error when in output mode
* because schmitt trigger only work in input mode
*/
if (ret) {
err = -EINVAL;
break;
}
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (!hw->soc->drive_get)
break;
if (hw->soc->adv_drive_get) {
err = hw->soc->adv_drive_get(hw, desc, &ret);
if (!err) {
err = mtk_drv_adv_to_uA(ret);
if (err > 0) {
/* PIN_CONFIG_DRIVE_STRENGTH_UA used */
err = -EINVAL;
break;
}
}
}
err = hw->soc->drive_get(hw, desc, &ret);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
if (!hw->soc->adv_drive_get)
break;
err = hw->soc->adv_drive_get(hw, desc, &ret);
if (err)
break;
err = mtk_drv_adv_to_uA(ret);
if (err < 0)
break;
ret = err;
err = 0;
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_get_value(hw, desc, reg, &ret);
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (!hw->soc->adv_pull_get)
break;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
break;
case MTK_PIN_CONFIG_DRV_ADV:
if (!hw->soc->adv_drive_get)
break;
err = hw->soc->adv_drive_get(hw, desc, &ret);
break;
}
if (!err)
*config = pinconf_to_config_packed(param, ret);
return err;
}
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
enum pin_config_param param, u32 arg)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
int err = -ENOTSUPP;
u32 reg;
if (pin >= hw->soc->npins)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
switch ((u32)param) {
case PIN_CONFIG_BIAS_DISABLE:
if (!hw->soc->bias_set_combo)
break;
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (!hw->soc->bias_set_combo)
break;
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!hw->soc->bias_set_combo)
break;
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
MTK_DISABLE);
/* Keep set direction to consider the case that a GPIO pin
* does not have SMT control
*/
if (err != -ENOTSUPP)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
break;
case PIN_CONFIG_INPUT_ENABLE:
/* regard all non-zero value as enable */
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
if (err)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_INPUT);
break;
case PIN_CONFIG_SLEW_RATE:
/* regard all non-zero value as enable */
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
break;
case PIN_CONFIG_OUTPUT:
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
arg);
if (err)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
MTK_OUTPUT);
break;
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
/* arg = 1: Input mode & SMT enable ;
* arg = 0: Output mode & SMT disable
*/
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
if (err)
break;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (!hw->soc->drive_set)
break;
err = hw->soc->drive_set(hw, desc, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
if (!hw->soc->adv_drive_set)
break;
err = mtk_drv_uA_to_adv(arg);
if (err < 0)
break;
err = hw->soc->adv_drive_set(hw, desc, err);
break;
case MTK_PIN_CONFIG_TDSEL:
case MTK_PIN_CONFIG_RDSEL:
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
err = mtk_hw_set_value(hw, desc, reg, arg);
break;
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (!hw->soc->adv_pull_set)
break;
err = hw->soc->adv_pull_set(hw, desc,
(param == MTK_PIN_CONFIG_PU_ADV),
arg);
break;
case MTK_PIN_CONFIG_DRV_ADV:
if (!hw->soc->adv_drive_set)
break;
err = hw->soc->adv_drive_set(hw, desc, arg);
break;
}
return err;
}
static struct mtk_pinctrl_group *
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
{
int i;
for (i = 0; i < hw->soc->ngrps; i++) {
struct mtk_pinctrl_group *grp = hw->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static const struct mtk_func_desc *
mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
{
const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
const struct mtk_func_desc *func = pin->funcs;
while (func && func->name) {
if (func->muxval == fnum)
return func;
func++;
}
return NULL;
}
static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
u32 fnum)
{
int i;
for (i = 0; i < hw->soc->npins; i++) {
const struct mtk_pin_desc *pin = hw->soc->pins + i;
if (pin->number == pin_num) {
const struct mtk_func_desc *func = pin->funcs;
while (func && func->name) {
if (func->muxval == fnum)
return true;
func++;
}
break;
}
}
return false;
}
static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
u32 pin, u32 fnum,
struct mtk_pinctrl_group *grp,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
bool ret;
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
if (!ret) {
dev_err(pctl->dev, "invalid function %d on pin %d .\n",
fnum, pin);
return -EINVAL;
}
(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
int num_pins, num_funcs, maps_per_pin, i, err;
struct mtk_pinctrl_group *grp;
unsigned int num_configs;
bool has_config = false;
unsigned long *configs;
u32 pinfunc, pin, func;
struct property *pins;
unsigned reserve = 0;
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(hw->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (err < 0)
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
if (err)
goto exit;
pin = MTK_GET_PIN_NO(pinfunc);
func = MTK_GET_PIN_FUNC(pinfunc);
if (pin >= hw->soc->npins ||
func >= ARRAY_SIZE(mtk_gpio_functions)) {
dev_err(hw->dev, "invalid pins value.\n");
err = -EINVAL;
goto exit;
}
grp = mtk_pctrl_find_group_by_pin(hw, pin);
if (!grp) {
dev_err(hw->dev, "unable to match pin %d to group\n",
pin);
err = -EINVAL;
goto exit;
}
err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
reserved_maps, num_maps);
if (err < 0)
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps,
num_maps,
grp->name,
configs,
num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto exit;
}
}
err = 0;
exit:
kfree(configs);
return err;
}
static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct device_node *np;
unsigned reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node(np_config, np) {
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps,
num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
return 0;
}
static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
return hw->soc->ngrps;
}
static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
return hw->groups[group].name;
}
static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&hw->groups[group].pin;
*num_pins = 1;
return 0;
}
static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
{
const struct mtk_pin_desc *desc;
int value, err;
if (gpio >= hw->soc->npins)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, field, &value);
if (err)
return err;
return value;
}
#define mtk_pctrl_get_pinmux(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
#define mtk_pctrl_get_direction(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
#define mtk_pctrl_get_out(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
#define mtk_pctrl_get_in(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
#define mtk_pctrl_get_smt(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
#define mtk_pctrl_get_ies(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
#define mtk_pctrl_get_driving(hw, gpio) \
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
unsigned int gpio, char *buf, unsigned int buf_len)
{
int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
const struct mtk_pin_desc *desc;
u32 try_all_type = 0;
if (gpio >= hw->soc->npins)
return -EINVAL;
if (mtk_is_virt_gpio(hw, gpio))
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
pinmux = mtk_pctrl_get_pinmux(hw, gpio);
if (pinmux >= hw->soc->nfuncs)
pinmux -= hw->soc->nfuncs;
mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
if (hw->soc->pull_type)
try_all_type = hw->soc->pull_type[desc->number];
if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
rsel = pullen;
pullen = 1;
} else {
/* Case for: R1R0 */
if (pullen == MTK_PUPD_SET_R1R0_00) {
pullen = 0;
r1 = 0;
r0 = 0;
} else if (pullen == MTK_PUPD_SET_R1R0_01) {
pullen = 1;
r1 = 0;
r0 = 1;
} else if (pullen == MTK_PUPD_SET_R1R0_10) {
pullen = 1;
r1 = 1;
r0 = 0;
} else if (pullen == MTK_PUPD_SET_R1R0_11) {
pullen = 1;
r1 = 1;
r0 = 1;
}
/* Case for: RSEL */
if (pullen >= MTK_PULL_SET_RSEL_000 &&
pullen <= MTK_PULL_SET_RSEL_111) {
rsel = pullen - MTK_PULL_SET_RSEL_000;
pullen = 1;
}
}
len += scnprintf(buf + len, buf_len - len,
"%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
gpio,
pinmux,
mtk_pctrl_get_direction(hw, gpio),
mtk_pctrl_get_out(hw, gpio),
mtk_pctrl_get_in(hw, gpio),
mtk_pctrl_get_driving(hw, gpio),
mtk_pctrl_get_smt(hw, gpio),
mtk_pctrl_get_ies(hw, gpio),
pullen,
pullup);
if (r1 != -1)
len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
else if (rsel != -1)
len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
return len;
}
EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
#define PIN_DBG_BUF_SZ 96
static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int gpio)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
char buf[PIN_DBG_BUF_SZ] = { 0 };
(void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
seq_printf(s, "%s", buf);
}
static const struct pinctrl_ops mtk_pctlops = {
.dt_node_to_map = mtk_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
.get_groups_count = mtk_pctrl_get_groups_count,
.get_group_name = mtk_pctrl_get_group_name,
.get_group_pins = mtk_pctrl_get_group_pins,
.pin_dbg_show = mtk_pctrl_dbg_show,
};
static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mtk_gpio_functions);
}
static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return mtk_gpio_functions[selector];
}
static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
*groups = hw->grp_names;
*num_groups = hw->soc->ngrps;
return 0;
}
static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *grp = hw->groups + group;
const struct mtk_func_desc *desc_func;
const struct mtk_pin_desc *desc;
bool ret;
ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
if (!ret) {
dev_err(hw->dev, "invalid function %d on group %d .\n",
function, group);
return -EINVAL;
}
desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
if (!desc_func)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
return 0;
}
static const struct pinmux_ops mtk_pmxops = {
.get_functions_count = mtk_pmx_get_funcs_cnt,
.get_function_name = mtk_pmx_get_func_name,
.get_function_groups = mtk_pmx_get_func_groups,
.set_mux = mtk_pmx_set_mux,
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
};
static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *config)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *grp = &hw->groups[group];
/* One pin per group only */
return mtk_pinconf_get(pctldev, grp->pin, config);
}
static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
struct mtk_pinctrl_group *grp = &hw->groups[group];
bool drive_strength_uA_found = false;
bool adv_drve_strength_found = false;
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = mtk_pinconf_set(pctldev, grp->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
drive_strength_uA_found = true;
if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
adv_drve_strength_found = true;
}
/*
* Disable advanced drive strength mode if drive-strength-microamp
* is not set. However, mediatek,drive-strength-adv takes precedence
* as its value can explicitly request the mode be enabled or not.
*/
if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
!adv_drve_strength_found)
hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
return 0;
}
static const struct pinconf_ops mtk_confops = {
.pin_config_get = mtk_pinconf_get,
.pin_config_group_get = mtk_pconf_group_get,
.pin_config_group_set = mtk_pconf_group_set,
.is_generic = true,
};
static struct pinctrl_desc mtk_desc = {
.name = PINCTRL_PINCTRL_DEV,
.pctlops = &mtk_pctlops,
.pmxops = &mtk_pmxops,
.confops = &mtk_confops,
.owner = THIS_MODULE,
};
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
if (gpio >= hw->soc->npins)
return -EINVAL;
/*
* "Virtual" GPIOs are always and only used for interrupts
* Since they are only used for interrupts, they are always inputs
*/
if (mtk_is_virt_gpio(hw, gpio))
return 1;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
if (err)
return err;
if (value)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
int value, err;
if (gpio >= hw->soc->npins)
return -EINVAL;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
if (err)
return err;
return !!value;
}
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (gpio >= hw->soc->npins)
return;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
}
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
if (gpio >= hw->soc->npins)
return -EINVAL;
return pinctrl_gpio_direction_input(chip->base + gpio);
}
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
if (gpio >= hw->soc->npins)
return -EINVAL;
mtk_gpio_set(chip, gpio, value);
return pinctrl_gpio_direction_output(chip->base + gpio);
}
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
if (!hw->eint)
return -ENOTSUPP;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
}
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
if (!hw->eint ||
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
desc->eint.eint_n == EINT_NA)
return -ENOTSUPP;
debounce = pinconf_to_config_argument(config);
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
}
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
{
struct gpio_chip *chip = &hw->chip;
int ret;
chip->label = PINCTRL_PINCTRL_DEV;
chip->parent = hw->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->get_direction = mtk_gpio_get_direction;
chip->direction_input = mtk_gpio_direction_input;
chip->direction_output = mtk_gpio_direction_output;
chip->get = mtk_gpio_get;
chip->set = mtk_gpio_set;
chip->to_irq = mtk_gpio_to_irq;
chip->set_config = mtk_gpio_set_config;
chip->base = -1;
chip->ngpio = hw->soc->npins;
ret = gpiochip_add_data(chip, hw);
if (ret < 0)
return ret;
return 0;
}
static int mtk_pctrl_build_state(struct platform_device *pdev)
{
struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
int i;
/* Allocate groups */
hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
sizeof(*hw->groups), GFP_KERNEL);
if (!hw->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
sizeof(*hw->grp_names), GFP_KERNEL);
if (!hw->grp_names)
return -ENOMEM;
for (i = 0; i < hw->soc->npins; i++) {
const struct mtk_pin_desc *pin = hw->soc->pins + i;
struct mtk_pinctrl_group *group = hw->groups + i;
group->name = pin->name;
group->pin = pin->number;
hw->grp_names[i] = pin->name;
}
return 0;
}
int mtk_paris_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
platform_set_drvdata(pdev, hw);
hw->soc = device_get_match_data(dev);
if (!hw->soc)
return -ENOENT;
hw->dev = &pdev->dev;
if (!hw->soc->nbase_names)
return dev_err_probe(dev, -EINVAL,
"SoC should be assigned at least one register base\n");
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
sizeof(*hw->base), GFP_KERNEL);
if (!hw->base)
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}
hw->nbase = hw->soc->nbase_names;
if (of_find_property(hw->dev->of_node,
"mediatek,rsel-resistance-in-si-unit", NULL))
hw->rsel_si_unit = true;
else
hw->rsel_si_unit = false;
spin_lock_init(&hw->lock);
err = mtk_pctrl_build_state(pdev);
if (err)
return dev_err_probe(dev, err, "build state failed\n");
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < hw->soc->npins; i++) {
pins[i].number = hw->soc->pins[i].number;
pins[i].name = hw->soc->pins[i].name;
}
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
mtk_desc.npins = hw->soc->npins;
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
mtk_desc.custom_params = mtk_custom_bindings;
#ifdef CONFIG_DEBUG_FS
mtk_desc.custom_conf_items = mtk_conf_items;
#endif
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");
/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw);
if (err)
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
platform_set_drvdata(pdev, hw);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
static int mtk_paris_pinctrl_suspend(struct device *device)
{
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
return mtk_eint_do_suspend(pctl->eint);
}
static int mtk_paris_pinctrl_resume(struct device *device)
{
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
return mtk_eint_do_resume(pctl->eint);
}
const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
.suspend_noirq = mtk_paris_pinctrl_suspend,
.resume_noirq = mtk_paris_pinctrl_resume,
};
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-paris.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Biao Huang <[email protected]>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt2701.h"
/**
* struct mtk_spec_pinmux_set
* - For special pins' mode setting
* @pin: The pin number.
* @offset: The offset of extra setting register.
* @bit: The bit of extra setting register.
*/
struct mtk_spec_pinmux_set {
unsigned short pin;
unsigned short offset;
unsigned char bit;
};
#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
{ \
.pin = _pin, \
.offset = _offset, \
.bit = _bit, \
}
static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
};
static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
};
static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
};
static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
};
static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
MTK_PINMUX_SPEC(22, 0xb10, 3),
MTK_PINMUX_SPEC(23, 0xb10, 4),
MTK_PINMUX_SPEC(24, 0xb10, 5),
MTK_PINMUX_SPEC(29, 0xb10, 9),
MTK_PINMUX_SPEC(208, 0xb10, 7),
MTK_PINMUX_SPEC(209, 0xb10, 8),
MTK_PINMUX_SPEC(203, 0xf20, 0),
MTK_PINMUX_SPEC(204, 0xf20, 1),
MTK_PINMUX_SPEC(249, 0xef0, 0),
MTK_PINMUX_SPEC(250, 0xef0, 0),
MTK_PINMUX_SPEC(251, 0xef0, 0),
MTK_PINMUX_SPEC(252, 0xef0, 0),
MTK_PINMUX_SPEC(253, 0xef0, 0),
MTK_PINMUX_SPEC(254, 0xef0, 0),
MTK_PINMUX_SPEC(255, 0xef0, 0),
MTK_PINMUX_SPEC(256, 0xef0, 0),
MTK_PINMUX_SPEC(257, 0xef0, 0),
MTK_PINMUX_SPEC(258, 0xef0, 0),
MTK_PINMUX_SPEC(259, 0xef0, 0),
MTK_PINMUX_SPEC(260, 0xef0, 0),
};
static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
unsigned int mode)
{
unsigned int i, value, mask;
unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
unsigned int spec_flag;
for (i = 0; i < info_num; i++) {
if (pin == mt2701_spec_pinmux[i].pin)
break;
}
if (i == info_num)
return;
spec_flag = (mode >> 3);
mask = BIT(mt2701_spec_pinmux[i].bit);
if (!spec_flag)
value = mask;
else
value = 0;
regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
}
static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
{
if (pin > 175)
*reg_addr += 0x10;
}
static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
.pins = mtk_pins_mt2701,
.npins = ARRAY_SIZE(mtk_pins_mt2701),
.grp_desc = mt2701_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
.pin_drv_grp = mt2701_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
.spec_ies = mt2701_ies_set,
.n_spec_ies = ARRAY_SIZE(mt2701_ies_set),
.spec_pupd = mt2701_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd),
.spec_smt = mt2701_smt_set,
.n_spec_smt = ARRAY_SIZE(mt2701_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.spec_pinmux_set = mt2701_spec_pinmux_set,
.spec_dir_set = mt2701_spec_dir_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0150,
.pullsel_offset = 0x0280,
.dout_offset = 0x0500,
.din_offset = 0x0630,
.pinmux_offset = 0x0760,
.type1_start = 280,
.type1_end = 280,
.port_shf = 4,
.port_mask = 0x1f,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 6,
.ports = 6,
.ap_num = 169,
.db_cnt = 16,
.db_time = debounce_time_mt2701,
},
};
static const struct of_device_id mt2701_pctrl_match[] = {
{ .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data },
{ .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt2701-pinctrl",
.of_match_table = mt2701_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt2701.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014-2015 MediaTek Inc.
* Author: Hongzhou.Yang <[email protected]>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8173.h"
#define DRV_BASE 0xb00
static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
};
static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
};
static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
};
static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
};
static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
.pins = mtk_pins_mt8173,
.npins = ARRAY_SIZE(mtk_pins_mt8173),
.grp_desc = mt8173_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
.pin_drv_grp = mt8173_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
.spec_ies = mt8173_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
.spec_pupd = mt8173_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
.spec_smt = mt8173_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
.dout_offset = 0x0400,
.din_offset = 0x0500,
.pinmux_offset = 0x0600,
.type1_start = 135,
.type1_end = 135,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 224,
.db_cnt = 16,
.db_time = debounce_time_mt2701,
},
};
static int mt8173_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
}
static const struct of_device_id mt8173_pctrl_match[] = {
{
.compatible = "mediatek,mt8173-pinctrl",
},
{ }
};
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8173_pinctrl_probe,
.driver = {
.name = "mediatek-mt8173-pinctrl",
.of_match_table = mt8173_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8173.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define MT76X8_GPIO_MODE_MASK 0x3
#define MT76X8_GPIO_MODE_P4LED_KN 58
#define MT76X8_GPIO_MODE_P3LED_KN 56
#define MT76X8_GPIO_MODE_P2LED_KN 54
#define MT76X8_GPIO_MODE_P1LED_KN 52
#define MT76X8_GPIO_MODE_P0LED_KN 50
#define MT76X8_GPIO_MODE_WLED_KN 48
#define MT76X8_GPIO_MODE_P4LED_AN 42
#define MT76X8_GPIO_MODE_P3LED_AN 40
#define MT76X8_GPIO_MODE_P2LED_AN 38
#define MT76X8_GPIO_MODE_P1LED_AN 36
#define MT76X8_GPIO_MODE_P0LED_AN 34
#define MT76X8_GPIO_MODE_WLED_AN 32
#define MT76X8_GPIO_MODE_PWM1 30
#define MT76X8_GPIO_MODE_PWM0 28
#define MT76X8_GPIO_MODE_UART2 26
#define MT76X8_GPIO_MODE_UART1 24
#define MT76X8_GPIO_MODE_I2C 20
#define MT76X8_GPIO_MODE_REFCLK 18
#define MT76X8_GPIO_MODE_PERST 16
#define MT76X8_GPIO_MODE_WDT 14
#define MT76X8_GPIO_MODE_SPI 12
#define MT76X8_GPIO_MODE_SDMODE 10
#define MT76X8_GPIO_MODE_UART0 8
#define MT76X8_GPIO_MODE_I2S 6
#define MT76X8_GPIO_MODE_CS1 4
#define MT76X8_GPIO_MODE_SPIS 2
#define MT76X8_GPIO_MODE_GPIO 0
static struct mtmips_pmx_func pwm1_grp[] = {
FUNC("sdxc d6", 3, 19, 1),
FUNC("utif", 2, 19, 1),
FUNC("gpio", 1, 19, 1),
FUNC("pwm1", 0, 19, 1),
};
static struct mtmips_pmx_func pwm0_grp[] = {
FUNC("sdxc d7", 3, 18, 1),
FUNC("utif", 2, 18, 1),
FUNC("gpio", 1, 18, 1),
FUNC("pwm0", 0, 18, 1),
};
static struct mtmips_pmx_func uart2_grp[] = {
FUNC("sdxc d5 d4", 3, 20, 2),
FUNC("pwm", 2, 20, 2),
FUNC("gpio", 1, 20, 2),
FUNC("uart2", 0, 20, 2),
};
static struct mtmips_pmx_func uart1_grp[] = {
FUNC("sw_r", 3, 45, 2),
FUNC("pwm", 2, 45, 2),
FUNC("gpio", 1, 45, 2),
FUNC("uart1", 0, 45, 2),
};
static struct mtmips_pmx_func i2c_grp[] = {
FUNC("-", 3, 4, 2),
FUNC("debug", 2, 4, 2),
FUNC("gpio", 1, 4, 2),
FUNC("i2c", 0, 4, 2),
};
static struct mtmips_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) };
static struct mtmips_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) };
static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) };
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) };
static struct mtmips_pmx_func sd_mode_grp[] = {
FUNC("jtag", 3, 22, 8),
FUNC("utif", 2, 22, 8),
FUNC("gpio", 1, 22, 8),
FUNC("sdxc", 0, 22, 8),
};
static struct mtmips_pmx_func uart0_grp[] = {
FUNC("-", 3, 12, 2),
FUNC("-", 2, 12, 2),
FUNC("gpio", 1, 12, 2),
FUNC("uart0", 0, 12, 2),
};
static struct mtmips_pmx_func i2s_grp[] = {
FUNC("antenna", 3, 0, 4),
FUNC("pcm", 2, 0, 4),
FUNC("gpio", 1, 0, 4),
FUNC("i2s", 0, 0, 4),
};
static struct mtmips_pmx_func spi_cs1_grp[] = {
FUNC("-", 3, 6, 1),
FUNC("refclk", 2, 6, 1),
FUNC("gpio", 1, 6, 1),
FUNC("spi cs1", 0, 6, 1),
};
static struct mtmips_pmx_func spis_grp[] = {
FUNC("pwm_uart2", 3, 14, 4),
FUNC("utif", 2, 14, 4),
FUNC("gpio", 1, 14, 4),
FUNC("spis", 0, 14, 4),
};
static struct mtmips_pmx_func gpio_grp[] = {
FUNC("pcie", 3, 11, 1),
FUNC("refclk", 2, 11, 1),
FUNC("gpio", 1, 11, 1),
FUNC("gpio", 0, 11, 1),
};
static struct mtmips_pmx_func p4led_kn_grp[] = {
FUNC("jtag", 3, 30, 1),
FUNC("utif", 2, 30, 1),
FUNC("gpio", 1, 30, 1),
FUNC("p4led_kn", 0, 30, 1),
};
static struct mtmips_pmx_func p3led_kn_grp[] = {
FUNC("jtag", 3, 31, 1),
FUNC("utif", 2, 31, 1),
FUNC("gpio", 1, 31, 1),
FUNC("p3led_kn", 0, 31, 1),
};
static struct mtmips_pmx_func p2led_kn_grp[] = {
FUNC("jtag", 3, 32, 1),
FUNC("utif", 2, 32, 1),
FUNC("gpio", 1, 32, 1),
FUNC("p2led_kn", 0, 32, 1),
};
static struct mtmips_pmx_func p1led_kn_grp[] = {
FUNC("jtag", 3, 33, 1),
FUNC("utif", 2, 33, 1),
FUNC("gpio", 1, 33, 1),
FUNC("p1led_kn", 0, 33, 1),
};
static struct mtmips_pmx_func p0led_kn_grp[] = {
FUNC("jtag", 3, 34, 1),
FUNC("rsvd", 2, 34, 1),
FUNC("gpio", 1, 34, 1),
FUNC("p0led_kn", 0, 34, 1),
};
static struct mtmips_pmx_func wled_kn_grp[] = {
FUNC("rsvd", 3, 35, 1),
FUNC("rsvd", 2, 35, 1),
FUNC("gpio", 1, 35, 1),
FUNC("wled_kn", 0, 35, 1),
};
static struct mtmips_pmx_func p4led_an_grp[] = {
FUNC("jtag", 3, 39, 1),
FUNC("utif", 2, 39, 1),
FUNC("gpio", 1, 39, 1),
FUNC("p4led_an", 0, 39, 1),
};
static struct mtmips_pmx_func p3led_an_grp[] = {
FUNC("jtag", 3, 40, 1),
FUNC("utif", 2, 40, 1),
FUNC("gpio", 1, 40, 1),
FUNC("p3led_an", 0, 40, 1),
};
static struct mtmips_pmx_func p2led_an_grp[] = {
FUNC("jtag", 3, 41, 1),
FUNC("utif", 2, 41, 1),
FUNC("gpio", 1, 41, 1),
FUNC("p2led_an", 0, 41, 1),
};
static struct mtmips_pmx_func p1led_an_grp[] = {
FUNC("jtag", 3, 42, 1),
FUNC("utif", 2, 42, 1),
FUNC("gpio", 1, 42, 1),
FUNC("p1led_an", 0, 42, 1),
};
static struct mtmips_pmx_func p0led_an_grp[] = {
FUNC("jtag", 3, 43, 1),
FUNC("rsvd", 2, 43, 1),
FUNC("gpio", 1, 43, 1),
FUNC("p0led_an", 0, 43, 1),
};
static struct mtmips_pmx_func wled_an_grp[] = {
FUNC("rsvd", 3, 44, 1),
FUNC("rsvd", 2, 44, 1),
FUNC("gpio", 1, 44, 1),
FUNC("wled_an", 0, 44, 1),
};
static struct mtmips_pmx_group mt76x8_pinmux_data[] = {
GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_PWM1),
GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_PWM0),
GRP_G("uart2", uart2_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART2),
GRP_G("uart1", uart1_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART1),
GRP_G("i2c", i2c_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_I2C),
GRP("refclk", refclk_grp, 1, MT76X8_GPIO_MODE_REFCLK),
GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST),
GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT),
GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI),
GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_SDMODE),
GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_UART0),
GRP_G("i2s", i2s_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_I2S),
GRP_G("spi cs1", spi_cs1_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_CS1),
GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_SPIS),
GRP_G("gpio", gpio_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_GPIO),
GRP_G("wled_an", wled_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_WLED_AN),
GRP_G("p0led_an", p0led_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P0LED_AN),
GRP_G("p1led_an", p1led_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P1LED_AN),
GRP_G("p2led_an", p2led_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P2LED_AN),
GRP_G("p3led_an", p3led_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P3LED_AN),
GRP_G("p4led_an", p4led_an_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P4LED_AN),
GRP_G("wled_kn", wled_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_WLED_KN),
GRP_G("p0led_kn", p0led_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P0LED_KN),
GRP_G("p1led_kn", p1led_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P1LED_KN),
GRP_G("p2led_kn", p2led_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P2LED_KN),
GRP_G("p3led_kn", p3led_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P3LED_KN),
GRP_G("p4led_kn", p4led_kn_grp, MT76X8_GPIO_MODE_MASK,
1, MT76X8_GPIO_MODE_P4LED_KN),
{ 0 }
};
static int mt76x8_pinctrl_probe(struct platform_device *pdev)
{
return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data);
}
static const struct of_device_id mt76x8_pinctrl_match[] = {
{ .compatible = "ralink,mt76x8-pinctrl" },
{ .compatible = "ralink,mt7620-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, mt76x8_pinctrl_match);
static struct platform_driver mt76x8_pinctrl_driver = {
.probe = mt76x8_pinctrl_probe,
.driver = {
.name = "mt76x8-pinctrl",
.of_match_table = mt76x8_pinctrl_match,
},
};
static int __init mt76x8_pinctrl_init(void)
{
return platform_driver_register(&mt76x8_pinctrl_driver);
}
core_initcall_sync(mt76x8_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt76x8.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/rt305x.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define RT305X_GPIO_MODE_UART0_SHIFT 2
#define RT305X_GPIO_MODE_UART0_MASK 0x7
#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
#define RT305X_GPIO_MODE_UARTF 0
#define RT305X_GPIO_MODE_PCM_UARTF 1
#define RT305X_GPIO_MODE_PCM_I2S 2
#define RT305X_GPIO_MODE_I2S_UARTF 3
#define RT305X_GPIO_MODE_PCM_GPIO 4
#define RT305X_GPIO_MODE_GPIO_UARTF 5
#define RT305X_GPIO_MODE_GPIO_I2S 6
#define RT305X_GPIO_MODE_GPIO 7
#define RT305X_GPIO_MODE_I2C 0
#define RT305X_GPIO_MODE_SPI 1
#define RT305X_GPIO_MODE_UART1 5
#define RT305X_GPIO_MODE_JTAG 6
#define RT305X_GPIO_MODE_MDIO 7
#define RT305X_GPIO_MODE_SDRAM 8
#define RT305X_GPIO_MODE_RGMII 9
#define RT5350_GPIO_MODE_PHY_LED 14
#define RT5350_GPIO_MODE_SPI_CS1 21
#define RT3352_GPIO_MODE_LNA 18
#define RT3352_GPIO_MODE_PA 20
static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
static struct mtmips_pmx_func uartf_grp[] = {
FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
};
static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) };
static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
static struct mtmips_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) };
static struct mtmips_pmx_func rt5350_cs1_grp[] = {
FUNC("spi_cs1", 0, 27, 1),
FUNC("wdg_cs1", 1, 27, 1),
};
static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) };
static struct mtmips_pmx_func rt3352_rgmii_grp[] = {
FUNC("rgmii", 0, 24, 12)
};
static struct mtmips_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) };
static struct mtmips_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) };
static struct mtmips_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) };
static struct mtmips_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) };
static struct mtmips_pmx_func rt3352_cs1_grp[] = {
FUNC("spi_cs1", 0, 45, 1),
FUNC("wdg_cs1", 1, 45, 1),
};
static struct mtmips_pmx_group rt3050_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK,
RT305X_GPIO_MODE_UART0_SHIFT),
GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1),
GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
GRP("mdio", mdio_grp, 1, RT305X_GPIO_MODE_MDIO),
GRP("rgmii", rgmii_grp, 1, RT305X_GPIO_MODE_RGMII),
GRP("sdram", sdram_grp, 1, RT305X_GPIO_MODE_SDRAM),
{ 0 }
};
static struct mtmips_pmx_group rt3352_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK,
RT305X_GPIO_MODE_UART0_SHIFT),
GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1),
GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
GRP("mdio", mdio_grp, 1, RT305X_GPIO_MODE_MDIO),
GRP("rgmii", rt3352_rgmii_grp, 1, RT305X_GPIO_MODE_RGMII),
GRP("lna", rt3352_lna_grp, 1, RT3352_GPIO_MODE_LNA),
GRP("pa", rt3352_pa_grp, 1, RT3352_GPIO_MODE_PA),
GRP("led", rt3352_led_grp, 1, RT5350_GPIO_MODE_PHY_LED),
GRP("spi_cs1", rt3352_cs1_grp, 2, RT5350_GPIO_MODE_SPI_CS1),
{ 0 }
};
static struct mtmips_pmx_group rt5350_pinmux_data[] = {
GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C),
GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI),
GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK,
RT305X_GPIO_MODE_UART0_SHIFT),
GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1),
GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG),
GRP("led", rt5350_led_grp, 1, RT5350_GPIO_MODE_PHY_LED),
GRP("spi_cs1", rt5350_cs1_grp, 2, RT5350_GPIO_MODE_SPI_CS1),
{ 0 }
};
static int rt305x_pinctrl_probe(struct platform_device *pdev)
{
if (soc_is_rt5350())
return mtmips_pinctrl_init(pdev, rt5350_pinmux_data);
else if (soc_is_rt305x() || soc_is_rt3350())
return mtmips_pinctrl_init(pdev, rt3050_pinmux_data);
else if (soc_is_rt3352())
return mtmips_pinctrl_init(pdev, rt3352_pinmux_data);
else
return -EINVAL;
}
static const struct of_device_id rt305x_pinctrl_match[] = {
{ .compatible = "ralink,rt305x-pinctrl" },
{ .compatible = "ralink,rt3352-pinctrl" },
{ .compatible = "ralink,rt5350-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match);
static struct platform_driver rt305x_pinctrl_driver = {
.probe = rt305x_pinctrl_probe,
.driver = {
.name = "rt305x-pinctrl",
.of_match_table = rt305x_pinctrl_match,
},
};
static int __init rt305x_pinctrl_init(void)
{
return platform_driver_register(&rt305x_pinctrl_driver);
}
core_initcall_sync(rt305x_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-rt305x.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2013 John Crispin <[email protected]>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>
#include "pinctrl-mtmips.h"
#include "../core.h"
#include "../pinctrl-utils.h"
#define SYSC_REG_GPIO_MODE 0x60
#define SYSC_REG_GPIO_MODE2 0x64
struct mtmips_priv {
struct device *dev;
struct pinctrl_pin_desc *pads;
struct pinctrl_desc *desc;
struct mtmips_pmx_func **func;
int func_count;
struct mtmips_pmx_group *groups;
const char **group_names;
int group_count;
u8 *gpio;
int max_pins;
};
static int mtmips_get_group_count(struct pinctrl_dev *pctrldev)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->group_count;
}
static const char *mtmips_get_group_name(struct pinctrl_dev *pctrldev,
unsigned int group)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return (group >= p->group_count) ? NULL : p->group_names[group];
}
static int mtmips_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (group >= p->group_count)
return -EINVAL;
*pins = p->groups[group].func[0].pins;
*num_pins = p->groups[group].func[0].pin_count;
return 0;
}
static const struct pinctrl_ops mtmips_pctrl_ops = {
.get_groups_count = mtmips_get_group_count,
.get_group_name = mtmips_get_group_name,
.get_group_pins = mtmips_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int mtmips_pmx_func_count(struct pinctrl_dev *pctrldev)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func_count;
}
static const char *mtmips_pmx_func_name(struct pinctrl_dev *pctrldev,
unsigned int func)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
return p->func[func]->name;
}
static int mtmips_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
unsigned int func,
const char * const **groups,
unsigned int * const num_groups)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (p->func[func]->group_count == 1)
*groups = &p->group_names[p->func[func]->groups[0]];
else
*groups = p->group_names;
*num_groups = p->func[func]->group_count;
return 0;
}
static int mtmips_pmx_group_enable(struct pinctrl_dev *pctrldev,
unsigned int func, unsigned int group)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
u32 mode = 0;
u32 reg = SYSC_REG_GPIO_MODE;
int i;
int shift;
/* dont allow double use */
if (p->groups[group].enabled) {
dev_err(p->dev, "%s is already enabled\n",
p->groups[group].name);
return 0;
}
p->groups[group].enabled = 1;
p->func[func]->enabled = 1;
shift = p->groups[group].shift;
if (shift >= 32) {
shift -= 32;
reg = SYSC_REG_GPIO_MODE2;
}
mode = rt_sysc_r32(reg);
mode &= ~(p->groups[group].mask << shift);
/* mark the pins as gpio */
for (i = 0; i < p->groups[group].func[0].pin_count; i++)
p->gpio[p->groups[group].func[0].pins[i]] = 1;
/* function 0 is gpio and needs special handling */
if (func == 0) {
mode |= p->groups[group].gpio << shift;
} else {
for (i = 0; i < p->func[func]->pin_count; i++)
p->gpio[p->func[func]->pins[i]] = 0;
mode |= p->func[func]->value << shift;
}
rt_sysc_w32(mode, reg);
return 0;
}
static int mtmips_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev);
if (!p->gpio[pin]) {
dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
return -EINVAL;
}
return 0;
}
static const struct pinmux_ops mtmips_pmx_group_ops = {
.get_functions_count = mtmips_pmx_func_count,
.get_function_name = mtmips_pmx_func_name,
.get_function_groups = mtmips_pmx_group_get_groups,
.set_mux = mtmips_pmx_group_enable,
.gpio_request_enable = mtmips_pmx_group_gpio_request_enable,
};
static struct pinctrl_desc mtmips_pctrl_desc = {
.owner = THIS_MODULE,
.name = "mtmips-pinctrl",
.pctlops = &mtmips_pctrl_ops,
.pmxops = &mtmips_pmx_group_ops,
};
static struct mtmips_pmx_func gpio_func = {
.name = "gpio",
};
static int mtmips_pinctrl_index(struct mtmips_priv *p)
{
struct mtmips_pmx_group *mux = p->groups;
int i, j, c = 0;
/* count the mux functions */
while (mux->name) {
p->group_count++;
mux++;
}
/* allocate the group names array needed by the gpio function */
p->group_names = devm_kcalloc(p->dev, p->group_count,
sizeof(char *), GFP_KERNEL);
if (!p->group_names)
return -ENOMEM;
for (i = 0; i < p->group_count; i++) {
p->group_names[i] = p->groups[i].name;
p->func_count += p->groups[i].func_count;
}
/* we have a dummy function[0] for gpio */
p->func_count++;
/* allocate our function and group mapping index buffers */
p->func = devm_kcalloc(p->dev, p->func_count,
sizeof(*p->func), GFP_KERNEL);
gpio_func.groups = devm_kcalloc(p->dev, p->group_count, sizeof(int),
GFP_KERNEL);
if (!p->func || !gpio_func.groups)
return -ENOMEM;
/* add a backpointer to the function so it knows its group */
gpio_func.group_count = p->group_count;
for (i = 0; i < gpio_func.group_count; i++)
gpio_func.groups[i] = i;
p->func[c] = &gpio_func;
c++;
/* add remaining functions */
for (i = 0; i < p->group_count; i++) {
for (j = 0; j < p->groups[i].func_count; j++) {
p->func[c] = &p->groups[i].func[j];
p->func[c]->groups = devm_kzalloc(p->dev, sizeof(int),
GFP_KERNEL);
if (!p->func[c]->groups)
return -ENOMEM;
p->func[c]->groups[0] = i;
p->func[c]->group_count = 1;
c++;
}
}
return 0;
}
static int mtmips_pinctrl_pins(struct mtmips_priv *p)
{
int i, j;
/*
* loop over the functions and initialize the pins array.
* also work out the highest pin used.
*/
for (i = 0; i < p->func_count; i++) {
int pin;
if (!p->func[i]->pin_count)
continue;
p->func[i]->pins = devm_kcalloc(p->dev,
p->func[i]->pin_count,
sizeof(int),
GFP_KERNEL);
if (!p->func[i]->pins)
return -ENOMEM;
for (j = 0; j < p->func[i]->pin_count; j++)
p->func[i]->pins[j] = p->func[i]->pin_first + j;
pin = p->func[i]->pin_first + p->func[i]->pin_count;
if (pin > p->max_pins)
p->max_pins = pin;
}
/* the buffer that tells us which pins are gpio */
p->gpio = devm_kcalloc(p->dev, p->max_pins, sizeof(u8), GFP_KERNEL);
/* the pads needed to tell pinctrl about our pins */
p->pads = devm_kcalloc(p->dev, p->max_pins,
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
if (!p->pads || !p->gpio)
return -ENOMEM;
memset(p->gpio, 1, sizeof(u8) * p->max_pins);
for (i = 0; i < p->func_count; i++) {
if (!p->func[i]->pin_count)
continue;
for (j = 0; j < p->func[i]->pin_count; j++)
p->gpio[p->func[i]->pins[j]] = 0;
}
/* pin 0 is always a gpio */
p->gpio[0] = 1;
/* set the pads */
for (i = 0; i < p->max_pins; i++) {
/* strlen("ioXY") + 1 = 5 */
char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, 5, "io%d", i);
p->pads[i].number = i;
p->pads[i].name = name;
}
p->desc->pins = p->pads;
p->desc->npins = p->max_pins;
return 0;
}
int mtmips_pinctrl_init(struct platform_device *pdev,
struct mtmips_pmx_group *data)
{
struct mtmips_priv *p;
struct pinctrl_dev *dev;
int err;
if (!data)
return -ENOTSUPP;
/* setup the private data */
p = devm_kzalloc(&pdev->dev, sizeof(struct mtmips_priv), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->dev = &pdev->dev;
p->desc = &mtmips_pctrl_desc;
p->groups = data;
platform_set_drvdata(pdev, p);
/* init the device */
err = mtmips_pinctrl_index(p);
if (err) {
dev_err(&pdev->dev, "failed to load index\n");
return err;
}
err = mtmips_pinctrl_pins(p);
if (err) {
dev_err(&pdev->dev, "failed to load pins\n");
return err;
}
dev = pinctrl_register(p->desc, &pdev->dev, p);
return PTR_ERR_OR_ZERO(dev);
}
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mtmips.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Hongzhou.Yang <[email protected]>
* Yingjoe Chen <[email protected]>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8127.h"
static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */
MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */
MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */
MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */
MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */
MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */
MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */
MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */
MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */
MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */
MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */
MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */
MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */
MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */
MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */
MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */
MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */
MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */
MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */
MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */
MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */
MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */
MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */
MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */
MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */
MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */
MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
};
static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
};
static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
};
static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
.pins = mtk_pins_mt8127,
.npins = ARRAY_SIZE(mtk_pins_mt8127),
.grp_desc = mt8127_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
.pin_drv_grp = mt8127_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
.spec_ies = mt8127_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
.spec_pupd = mt8127_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
.spec_smt = mt8127_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
.dout_offset = 0x0400,
.din_offset = 0x0500,
.pinmux_offset = 0x0600,
.type1_start = 143,
.type1_end = 143,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 143,
.db_cnt = 16,
.db_time = debounce_time_mt2701,
},
};
static const struct of_device_id mt8127_pctrl_match[] = {
{ .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
{ }
};
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8127-pinctrl",
.of_match_table = mt8127_pctrl_match,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8127.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include "pinctrl-mtk-mt6795.h"
#include "pinctrl-paris.h"
#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 15, 0)
#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 0)
#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
_x_bits, 16, 1)
static const struct mtk_pin_field_calc mt6795_pin_dir_range[] = {
PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pullen_range[] = {
PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pullsel_range[] = {
PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_do_range[] = {
PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_di_range[] = {
PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_mode_range[] = {
PIN_FIELD15(0, 196, 0x600, 0x10, 0, 3),
};
static const struct mtk_pin_field_calc mt6795_pin_ies_range[] = {
PINS_FIELD16(0, 4, 0x900, 0x10, 1, 1),
PINS_FIELD16(5, 9, 0x900, 0x10, 2, 1),
PINS_FIELD16(10, 15, 0x900, 0x10, 10, 1),
PINS_FIELD16(16, 16, 0x900, 0x10, 2, 1),
PINS_FIELD16(17, 19, 0x910, 0x10, 3, 1),
PINS_FIELD16(20, 22, 0x910, 0x10, 4, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 14, 1),
PINS_FIELD16(27, 27, 0xcc0, 0x10, 14, 1),
PINS_FIELD16(28, 28, 0xcd0, 0x10, 14, 1),
PINS_FIELD16(29, 32, 0x900, 0x10, 3, 1),
PINS_FIELD16(33, 33, 0x900, 0x10, 4, 1),
PINS_FIELD16(34, 36, 0x900, 0x10, 5, 1),
PINS_FIELD16(37, 38, 0x900, 0x10, 6, 1),
PINS_FIELD16(39, 39, 0x900, 0x10, 7, 1),
PINS_FIELD16(40, 40, 0x900, 0x10, 8, 1),
PINS_FIELD16(41, 42, 0x900, 0x10, 9, 1),
PINS_FIELD16(43, 46, 0x900, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0x920, 0x10, 3, 1),
PINS_FIELD16(62, 66, 0x920, 0x10, 4, 1),
PINS_FIELD16(67, 67, 0x920, 0x10, 3, 1),
PINS_FIELD16(68, 72, 0x920, 0x10, 5, 1),
PINS_FIELD16(73, 77, 0x920, 0x10, 6, 1),
PINS_FIELD16(78, 91, 0x920, 0x10, 7, 1),
PINS_FIELD16(92, 92, 0x900, 0x10, 13, 1),
PINS_FIELD16(93, 95, 0x900, 0x10, 14, 1),
PINS_FIELD16(96, 99, 0x900, 0x10, 15, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 14, 1),
PINS_FIELD16(104, 104, 0xc80, 0x10, 14, 1),
PINS_FIELD16(105, 105, 0xc90, 0x10, 14, 1),
PINS_FIELD16(106, 107, 0x910, 0x10, 0, 1),
PINS_FIELD16(108, 112, 0x910, 0x10, 1, 1),
PINS_FIELD16(113, 116, 0x910, 0x10, 2, 1),
PINS_FIELD16(117, 118, 0x910, 0x10, 5, 1),
PINS_FIELD16(119, 124, 0x910, 0x10, 6, 1),
PINS_FIELD16(125, 126, 0x910, 0x10, 7, 1),
PINS_FIELD16(129, 129, 0x910, 0x10, 8, 1),
PINS_FIELD16(130, 131, 0x910, 0x10, 9, 1),
PINS_FIELD16(132, 135, 0x910, 0x10, 8, 1),
PINS_FIELD16(136, 137, 0x910, 0x10, 7, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 14, 1),
PINS_FIELD16(162, 162, 0xc10, 0x10, 14, 1),
PINS_FIELD16(163, 163, 0xc00, 0x10, 14, 1),
PINS_FIELD16(164, 164, 0xd10, 0x10, 14, 1),
PINS_FIELD16(165, 165, 0xd00, 0x10, 14, 1),
PINS_FIELD16(166, 169, 0x910, 0x10, 14, 1),
PINS_FIELD16(176, 179, 0x910, 0x10, 15, 1),
PINS_FIELD16(180, 180, 0x920, 0x10, 0, 1),
PINS_FIELD16(181, 184, 0x920, 0x10, 1, 1),
PINS_FIELD16(185, 191, 0x920, 0x10, 2, 1),
PINS_FIELD16(192, 192, 0x920, 0x10, 8, 1),
PINS_FIELD16(193, 194, 0x920, 0x10, 9, 1),
PINS_FIELD16(195, 196, 0x920, 0x10, 8, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_smt_range[] = {
PINS_FIELD16(0, 4, 0x930, 0x10, 1, 1),
PINS_FIELD16(5, 9, 0x930, 0x10, 2, 1),
PINS_FIELD16(10, 15, 0x930, 0x10, 10, 1),
PINS_FIELD16(16, 16, 0x930, 0x10, 2, 1),
PINS_FIELD16(17, 19, 0x940, 0x10, 3, 1),
PINS_FIELD16(20, 22, 0x940, 0x10, 4, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 13, 1),
PINS_FIELD16(27, 27, 0xcc0, 0x10, 13, 1),
PINS_FIELD16(28, 28, 0xcd0, 0x10, 13, 1),
PINS_FIELD16(29, 32, 0x930, 0x10, 3, 1),
PINS_FIELD16(33, 33, 0x930, 0x10, 4, 1),
PINS_FIELD16(34, 36, 0x930, 0x10, 5, 1),
PINS_FIELD16(37, 38, 0x930, 0x10, 6, 1),
PINS_FIELD16(39, 39, 0x930, 0x10, 7, 1),
PINS_FIELD16(40, 40, 0x930, 0x10, 8, 1),
PINS_FIELD16(41, 42, 0x930, 0x10, 9, 1),
PINS_FIELD16(43, 46, 0x930, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0x950, 0x10, 3, 1),
PINS_FIELD16(62, 66, 0x950, 0x10, 4, 1),
PINS_FIELD16(67, 67, 0x950, 0x10, 3, 1),
PINS_FIELD16(68, 72, 0x950, 0x10, 5, 1),
PINS_FIELD16(73, 77, 0x950, 0x10, 6, 1),
PINS_FIELD16(78, 91, 0x950, 0x10, 7, 1),
PINS_FIELD16(92, 92, 0x930, 0x10, 13, 1),
PINS_FIELD16(93, 95, 0x930, 0x10, 14, 1),
PINS_FIELD16(96, 99, 0x930, 0x10, 15, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 13, 1),
PINS_FIELD16(104, 104, 0xc80, 0x10, 13, 1),
PINS_FIELD16(105, 105, 0xc90, 0x10, 13, 1),
PINS_FIELD16(106, 107, 0x940, 0x10, 0, 1),
PINS_FIELD16(108, 112, 0x940, 0x10, 1, 1),
PINS_FIELD16(113, 116, 0x940, 0x10, 2, 1),
PINS_FIELD16(117, 118, 0x940, 0x10, 5, 1),
PINS_FIELD16(119, 124, 0x940, 0x10, 6, 1),
PINS_FIELD16(125, 126, 0x940, 0x10, 7, 1),
PINS_FIELD16(129, 129, 0x940, 0x10, 8, 1),
PINS_FIELD16(130, 131, 0x940, 0x10, 9, 1),
PINS_FIELD16(132, 135, 0x940, 0x10, 8, 1),
PINS_FIELD16(136, 137, 0x940, 0x10, 7, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 13, 1),
PINS_FIELD16(162, 162, 0xc10, 0x10, 13, 1),
PINS_FIELD16(163, 163, 0xc00, 0x10, 13, 1),
PINS_FIELD16(164, 164, 0xd10, 0x10, 13, 1),
PINS_FIELD16(165, 165, 0xd00, 0x10, 13, 1),
PINS_FIELD16(166, 169, 0x940, 0x10, 14, 1),
PINS_FIELD16(176, 179, 0x940, 0x10, 15, 1),
PINS_FIELD16(180, 180, 0x950, 0x10, 0, 1),
PINS_FIELD16(181, 184, 0x950, 0x10, 1, 1),
PINS_FIELD16(185, 191, 0x950, 0x10, 2, 1),
PINS_FIELD16(192, 192, 0x950, 0x10, 8, 1),
PINS_FIELD16(193, 194, 0x950, 0x10, 9, 1),
PINS_FIELD16(195, 196, 0x950, 0x10, 8, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_pupd_range[] = {
/* KROW */
PIN_FIELD16(119, 119, 0xe00, 0x10, 2, 1), /* KROW0 */
PIN_FIELD16(120, 120, 0xe00, 0x10, 6, 1), /* KROW1 */
PIN_FIELD16(121, 121, 0xe00, 0x10, 10, 1), /* KROW2 */
PIN_FIELD16(122, 122, 0xe10, 0x10, 2, 1), /* KCOL0 */
PIN_FIELD16(123, 123, 0xe10, 0x10, 6, 1), /* KCOL1 */
PIN_FIELD16(124, 124, 0xe10, 0x10, 10, 1), /* KCOL2 */
/* DPI */
PIN_FIELD16(138, 138, 0xd50, 0x10, 2, 1), /* CK */
PIN_FIELD16(139, 139, 0xd60, 0x10, 1, 1), /* DE */
PIN_FIELD16(140, 140, 0xd70, 0x10, 1, 1), /* data0 */
PIN_FIELD16(141, 141, 0xd70, 0x10, 3, 1), /* data1 */
PIN_FIELD16(142, 142, 0xd70, 0x10, 5, 1), /* data2 */
PIN_FIELD16(143, 143, 0xd70, 0x10, 7, 1), /* data3 */
PIN_FIELD16(144, 144, 0xd50, 0x10, 5, 1), /* data4 */
PIN_FIELD16(145, 145, 0xd50, 0x10, 7, 1), /* data5 */
PIN_FIELD16(146, 146, 0xd60, 0x10, 7, 1), /* data6 */
PIN_FIELD16(147, 147, 0xed0, 0x10, 6, 1), /* data7 */
PIN_FIELD16(148, 148, 0xed0, 0x10, 8, 1), /* data8 */
PIN_FIELD16(149, 149, 0xed0, 0x10, 10, 1), /* data9 */
PIN_FIELD16(150, 150, 0xed0, 0x10, 12, 1), /* data10 */
PIN_FIELD16(151, 151, 0xed0, 0x10, 14, 1), /* data11 */
PIN_FIELD16(152, 152, 0xd60, 0x10, 3, 1), /* hsync */
PIN_FIELD16(153, 153, 0xd60, 0x10, 5, 1), /* vsync */
/* MSDC0 */
PIN_FIELD16(154, 154, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(155, 155, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(156, 156, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(157, 157, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(158, 158, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(159, 159, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(160, 160, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(161, 161, 0xc20, 0x10, 2, 1), /* DATA 0-7 */
PIN_FIELD16(162, 162, 0xc10, 0x10, 2, 1), /* CMD */
PIN_FIELD16(163, 163, 0xc00, 0x10, 2, 1), /* CLK */
PIN_FIELD16(164, 164, 0xd10, 0x10, 2, 1), /* DS */
PIN_FIELD16(165, 165, 0xd00, 0x10, 2, 1), /* RST */
/* MSDC1 */
PIN_FIELD16(170, 170, 0xc50, 0x10, 2, 1), /* CMD */
PIN_FIELD16(171, 171, 0xd20, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(172, 172, 0xd20, 0x10, 6, 1), /* DAT1 */
PIN_FIELD16(173, 173, 0xd20, 0x10, 10, 1), /* DAT2 */
PIN_FIELD16(174, 174, 0xd20, 0x10, 14, 1), /* DAT3 */
PIN_FIELD16(175, 175, 0xc40, 0x10, 2, 1), /* CLK */
/* MSDC2 */
PIN_FIELD16(100, 100, 0xd30, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(101, 101, 0xd30, 0x10, 6, 1), /* DAT1 */
PIN_FIELD16(102, 102, 0xd30, 0x10, 10, 1), /* DAT2 */
PIN_FIELD16(103, 103, 0xd30, 0x10, 14, 1), /* DAT3 */
PIN_FIELD16(104, 104, 0xc80, 0x10, 2, 1), /* CLK */
PIN_FIELD16(105, 105, 0xc90, 0x10, 2, 1), /* CMD */
/* MSDC3 */
PIN_FIELD16(23, 23, 0xd40, 0x10, 2, 1), /* DAT0 */
PIN_FIELD16(24, 24, 0xd40, 0x10, 6, 5), /* DAT1 */
PIN_FIELD16(25, 25, 0xd40, 0x10, 10, 9), /* DAT2 */
PIN_FIELD16(26, 26, 0xd40, 0x10, 14, 13), /* DAT3 */
PIN_FIELD16(27, 27, 0xcc0, 0x10, 2, 1), /* CLK */
PIN_FIELD16(28, 28, 0xcd0, 0x10, 2, 1) /* CMD */
};
static const struct mtk_pin_field_calc mt6795_pin_r0_range[] = {
PIN_FIELD16(23, 23, 0xd40, 0x10, 0, 1),
PIN_FIELD16(24, 24, 0xd40, 0x10, 4, 1),
PIN_FIELD16(25, 25, 0xd40, 0x10, 8, 1),
PIN_FIELD16(26, 26, 0xd40, 0x10, 12, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 0, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 0, 1),
PIN_FIELD16(100, 100, 0xd30, 0x10, 0, 1),
PIN_FIELD16(101, 101, 0xd30, 0x10, 4, 1),
PIN_FIELD16(102, 102, 0xd30, 0x10, 8, 1),
PIN_FIELD16(103, 103, 0xd30, 0x10, 12, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 0, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 0, 1),
PIN_FIELD16(119, 119, 0xe00, 0x10, 0, 1),
PIN_FIELD16(120, 120, 0xe00, 0x10, 4, 1),
PIN_FIELD16(121, 121, 0xe00, 0x10, 8, 1),
PIN_FIELD16(122, 122, 0xe10, 0x10, 0, 1),
PIN_FIELD16(123, 123, 0xe10, 0x10, 4, 1),
PIN_FIELD16(124, 124, 0xe10, 0x10, 8, 1),
PIN_FIELD16(138, 138, 0xd50, 0x10, 0, 1),
PIN_FIELD16(139, 139, 0xd60, 0x10, 0, 1),
PIN_FIELD16(140, 140, 0xd70, 0x10, 0, 1),
PIN_FIELD16(141, 141, 0xd70, 0x10, 1, 1),
PIN_FIELD16(142, 142, 0xd70, 0x10, 3, 1),
PIN_FIELD16(143, 143, 0xd70, 0x10, 5, 1),
PIN_FIELD16(144, 144, 0xd50, 0x10, 3, 1),
PIN_FIELD16(145, 145, 0xd50, 0x10, 5, 1),
PIN_FIELD16(146, 146, 0xd60, 0x10, 5, 1),
PIN_FIELD16(147, 147, 0xed0, 0x10, 4, 1),
PIN_FIELD16(148, 148, 0xed0, 0x10, 6, 1),
PIN_FIELD16(149, 149, 0xed0, 0x10, 8, 1),
PIN_FIELD16(150, 150, 0xed0, 0x10, 10, 1),
PIN_FIELD16(151, 151, 0xed0, 0x10, 12, 1),
PIN_FIELD16(152, 152, 0xd60, 0x10, 1, 1),
PIN_FIELD16(153, 153, 0xd60, 0x10, 3, 1),
PIN_FIELD16(154, 155, 0xc20, 0x10, 0, 1),
PIN_FIELD16(155, 156, 0xc20, 0x10, 0, 1),
PIN_FIELD16(156, 157, 0xc20, 0x10, 0, 1),
PIN_FIELD16(157, 158, 0xc20, 0x10, 0, 1),
PIN_FIELD16(158, 159, 0xc20, 0x10, 0, 1),
PIN_FIELD16(159, 160, 0xc20, 0x10, 0, 1),
PIN_FIELD16(160, 161, 0xc20, 0x10, 0, 1),
PIN_FIELD16(161, 161, 0xc20, 0x10, 0, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 0, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 0, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 0, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 0, 1),
PIN_FIELD16(170, 170, 0xc50, 0x10, 0, 1),
PIN_FIELD16(171, 171, 0xd20, 0x10, 0, 1),
PIN_FIELD16(172, 172, 0xd20, 0x10, 4, 1),
PIN_FIELD16(173, 173, 0xd20, 0x10, 8, 1),
PIN_FIELD16(174, 174, 0xd20, 0x10, 12, 1),
PIN_FIELD16(175, 175, 0xc40, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_r1_range[] = {
PIN_FIELD16(23, 23, 0xd40, 0x10, 1, 1),
PIN_FIELD16(24, 24, 0xd40, 0x10, 5, 1),
PIN_FIELD16(25, 25, 0xd40, 0x10, 9, 1),
PIN_FIELD16(26, 26, 0xd40, 0x10, 13, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 1, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 1, 1),
PIN_FIELD16(100, 100, 0xd30, 0x10, 1, 1),
PIN_FIELD16(101, 101, 0xd30, 0x10, 5, 1),
PIN_FIELD16(102, 102, 0xd30, 0x10, 9, 1),
PIN_FIELD16(103, 103, 0xd30, 0x10, 13, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 1, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 1, 1),
PIN_FIELD16(119, 119, 0xe00, 0x10, 1, 1),
PIN_FIELD16(120, 120, 0xe00, 0x10, 5, 1),
PIN_FIELD16(121, 121, 0xe00, 0x10, 9, 1),
PIN_FIELD16(122, 122, 0xe10, 0x10, 1, 1),
PIN_FIELD16(123, 123, 0xe10, 0x10, 5, 1),
PIN_FIELD16(124, 124, 0xe10, 0x10, 9, 1),
PIN_FIELD16(138, 138, 0xd50, 0x10, 1, 1),
PIN_FIELD16(139, 139, 0xd60, 0x10, 0, 1),
PIN_FIELD16(140, 140, 0xd70, 0x10, 0, 1),
PIN_FIELD16(141, 141, 0xd70, 0x10, 2, 1),
PIN_FIELD16(142, 142, 0xd70, 0x10, 4, 1),
PIN_FIELD16(143, 143, 0xd70, 0x10, 6, 1),
PIN_FIELD16(144, 144, 0xd50, 0x10, 4, 1),
PIN_FIELD16(145, 145, 0xd50, 0x10, 6, 1),
PIN_FIELD16(146, 146, 0xd60, 0x10, 6, 1),
PIN_FIELD16(147, 147, 0xed0, 0x10, 5, 1),
PIN_FIELD16(148, 148, 0xed0, 0x10, 7, 1),
PIN_FIELD16(149, 149, 0xed0, 0x10, 9, 1),
PIN_FIELD16(150, 150, 0xed0, 0x10, 11, 1),
PIN_FIELD16(151, 151, 0xed0, 0x10, 13, 1),
PIN_FIELD16(152, 152, 0xd60, 0x10, 2, 1),
PIN_FIELD16(153, 153, 0xd60, 0x10, 4, 1),
PIN_FIELD16(154, 155, 0xc20, 0x10, 1, 1),
PIN_FIELD16(155, 156, 0xc20, 0x10, 1, 1),
PIN_FIELD16(156, 157, 0xc20, 0x10, 1, 1),
PIN_FIELD16(157, 158, 0xc20, 0x10, 1, 1),
PIN_FIELD16(158, 159, 0xc20, 0x10, 1, 1),
PIN_FIELD16(159, 160, 0xc20, 0x10, 1, 1),
PIN_FIELD16(160, 161, 0xc20, 0x10, 1, 1),
PIN_FIELD16(161, 161, 0xc20, 0x10, 1, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 1, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 1, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 1, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 1, 1),
PIN_FIELD16(170, 170, 0xc50, 0x10, 1, 1),
PIN_FIELD16(171, 171, 0xd20, 0x10, 1, 1),
PIN_FIELD16(172, 172, 0xd20, 0x10, 5, 1),
PIN_FIELD16(173, 173, 0xd20, 0x10, 9, 1),
PIN_FIELD16(174, 174, 0xd20, 0x10, 13, 1),
PIN_FIELD16(175, 175, 0xc40, 0x10, 1, 1),
};
static const struct mtk_pin_field_calc mt6795_pin_drv_range[] = {
PINS_FIELD16(0, 4, 0xb30, 0x10, 13, 2),
PINS_FIELD16(5, 9, 0xb30, 0x10, 1, 2),
PINS_FIELD16(10, 15, 0xb30, 0x10, 5, 2),
PIN_FIELD16(16, 16, 0xb30, 0x10, 1, 2),
PINS_FIELD16(17, 19, 0xb70, 0x10, 5, 2),
PINS_FIELD16(20, 22, 0xb70, 0x10, 9, 2),
PINS_FIELD16(23, 26, 0xce0, 0x10, 8, 2),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 8, 2),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 8, 2),
PINS_FIELD16(29, 32, 0xb80, 0x10, 13, 2),
PIN_FIELD16(33, 33, 0xb10, 0x10, 13, 2),
PINS_FIELD16(34, 36, 0xb10, 0x10, 9, 2),
PINS_FIELD16(37, 38, 0xb10, 0x10, 5, 2),
PIN_FIELD16(39, 39, 0xb20, 0x10, 1, 2),
PIN_FIELD16(40, 40, 0xb20, 0x10, 5, 2),
PINS_FIELD16(41, 42, 0xb20, 0x10, 9, 2),
PINS_FIELD16(47, 61, 0xb00, 0x10, 9, 2),
PINS_FIELD16(62, 66, 0xb70, 0x10, 1, 2),
PINS_FIELD16(67, 67, 0xb00, 0x10, 9, 2),
PINS_FIELD16(68, 72, 0xb60, 0x10, 13, 2),
PINS_FIELD16(73, 77, 0xb40, 0x10, 13, 2),
PIN_FIELD16(78, 78, 0xb00, 0x10, 12, 3),
PINS_FIELD16(79, 91, 0xb00, 0x10, 13, 2),
PIN_FIELD16(92, 92, 0xb60, 0x10, 5, 2),
PINS_FIELD16(93, 95, 0xb60, 0x10, 1, 2),
PINS_FIELD16(96, 99, 0xb80, 0x10, 9, 2),
PINS_FIELD16(100, 103, 0xca0, 0x10, 8, 2),
PIN_FIELD16(104, 104, 0xc80, 0x10, 8, 2),
PIN_FIELD16(105, 105, 0xc90, 0x10, 8, 2),
PINS_FIELD16(106, 107, 0xb50, 0x10, 9, 2),
PINS_FIELD16(108, 112, 0xb50, 0x10, 1, 2),
PINS_FIELD16(113, 116, 0xb80, 0x10, 5, 2),
PINS_FIELD16(117, 118, 0xb90, 0x10, 1, 2),
PINS_FIELD16(119, 124, 0xb50, 0x10, 5, 2),
PIN_FIELD16(127, 127, 0xb70, 0x10, 5, 2),
PIN_FIELD16(128, 128, 0xb70, 0x10, 9, 2),
PIN_FIELD16(129, 129, 0xb40, 0x10, 9, 2),
PINS_FIELD16(130, 131, 0xb40, 0x10, 13, 2),
PINS_FIELD16(132, 135, 0xb40, 0x10, 9, 2),
PIN_FIELD16(138, 138, 0xb50, 0x10, 8, 2),
PIN_FIELD16(139, 139, 0xb60, 0x10, 8, 2),
PINS_FIELD16(140, 151, 0xb70, 0x10, 8, 2),
PINS_FIELD16(152, 153, 0xb60, 0x10, 8, 2),
PINS_FIELD16(153, 153, 0xb60, 0x10, 8, 2),
PINS_FIELD16(154, 161, 0xc20, 0x10, 8, 2),
PIN_FIELD16(162, 162, 0xc10, 0x10, 8, 2),
PIN_FIELD16(163, 163, 0xc00, 0x10, 8, 2),
PIN_FIELD16(164, 164, 0xd10, 0x10, 8, 2),
PIN_FIELD16(165, 165, 0xd00, 0x10, 8, 2),
PINS_FIELD16(166, 169, 0xb80, 0x10, 1, 2),
PINS_FIELD16(170, 173, 0xc60, 0x10, 8, 2),
PIN_FIELD16(174, 174, 0xc40, 0x10, 8, 2),
PIN_FIELD16(175, 175, 0xc50, 0x10, 8, 2),
PINS_FIELD16(176, 179, 0xb70, 0x10, 13, 2),
PIN_FIELD16(180, 180, 0xb00, 0x10, 5, 2),
PINS_FIELD16(181, 184, 0xb00, 0x10, 1, 2),
PINS_FIELD16(185, 191, 0xb60, 0x10, 9, 2),
PIN_FIELD16(192, 192, 0xb40, 0x10, 1, 2),
PINS_FIELD16(193, 194, 0xb40, 0x10, 5, 2),
PINS_FIELD16(195, 196, 0xb40, 0x10, 1, 2),
};
static const struct mtk_pin_field_calc mt6795_pin_sr_range[] = {
PINS_FIELD16(0, 4, 0xb30, 0x10, 15, 1),
PINS_FIELD16(5, 9, 0xb30, 0x10, 3, 1),
PINS_FIELD16(10, 15, 0xb30, 0x10, 7, 1),
PIN_FIELD16(16, 16, 0xb30, 0x10, 5, 1),
PINS_FIELD16(23, 26, 0xce0, 0x10, 12, 1),
PIN_FIELD16(27, 27, 0xcc0, 0x10, 12, 1),
PIN_FIELD16(28, 28, 0xcd0, 0x10, 12, 1),
PINS_FIELD16(29, 32, 0xb80, 0x10, 15, 1),
PIN_FIELD16(33, 33, 0xb10, 0x10, 15, 1),
PINS_FIELD16(34, 36, 0xb10, 0x10, 11, 1),
PINS_FIELD16(37, 38, 0xb10, 0x10, 7, 1),
PIN_FIELD16(39, 39, 0xb20, 0x10, 3, 1),
PIN_FIELD16(40, 40, 0xb20, 0x10, 7, 1),
PINS_FIELD16(41, 42, 0xb20, 0x10, 11, 1),
PINS_FIELD16(47, 61, 0xb00, 0x10, 11, 1),
PINS_FIELD16(62, 66, 0xb70, 0x10, 3, 1),
PINS_FIELD16(67, 67, 0xb00, 0x10, 11, 1),
PINS_FIELD16(68, 72, 0xb60, 0x10, 15, 1),
PINS_FIELD16(73, 77, 0xb40, 0x10, 15, 1),
PIN_FIELD16(78, 78, 0xb00, 0x10, 15, 3),
PINS_FIELD16(79, 91, 0xb00, 0x10, 15, 1),
PIN_FIELD16(92, 92, 0xb60, 0x10, 7, 1),
PINS_FIELD16(93, 95, 0xb60, 0x10, 3, 1),
PINS_FIELD16(96, 99, 0xb80, 0x10, 11, 1),
PINS_FIELD16(100, 103, 0xca0, 0x10, 12, 1),
PIN_FIELD16(104, 104, 0xc80, 0x10, 12, 1),
PIN_FIELD16(105, 105, 0xc90, 0x10, 12, 1),
PINS_FIELD16(106, 107, 0xb50, 0x10, 11, 1),
PINS_FIELD16(108, 112, 0xb50, 0x10, 3, 1),
PINS_FIELD16(113, 116, 0xb80, 0x10, 7, 1),
PINS_FIELD16(117, 118, 0xb90, 0x10, 3, 1),
PINS_FIELD16(119, 124, 0xb50, 0x10, 7, 1),
PIN_FIELD16(127, 127, 0xb70, 0x10, 7, 1),
PIN_FIELD16(128, 128, 0xb70, 0x10, 11, 1),
PIN_FIELD16(129, 129, 0xb40, 0x10, 11, 1),
PINS_FIELD16(130, 131, 0xb40, 0x10, 15, 1),
PINS_FIELD16(132, 135, 0xb40, 0x10, 11, 1),
PIN_FIELD16(138, 138, 0xb50, 0x10, 12, 1),
PIN_FIELD16(139, 139, 0xb60, 0x10, 12, 1),
PINS_FIELD16(140, 151, 0xb70, 0x10, 12, 1),
PINS_FIELD16(152, 153, 0xb60, 0x10, 12, 1),
PINS_FIELD16(153, 153, 0xb60, 0x10, 12, 1),
PINS_FIELD16(154, 161, 0xc20, 0x10, 12, 1),
PIN_FIELD16(162, 162, 0xc10, 0x10, 12, 1),
PIN_FIELD16(163, 163, 0xc00, 0x10, 12, 1),
PIN_FIELD16(164, 164, 0xd10, 0x10, 12, 1),
PIN_FIELD16(165, 165, 0xd00, 0x10, 12, 1),
PINS_FIELD16(166, 169, 0xb80, 0x10, 3, 1),
PINS_FIELD16(170, 173, 0xc60, 0x10, 12, 1),
PIN_FIELD16(174, 174, 0xc40, 0x10, 12, 1),
PIN_FIELD16(175, 175, 0xc50, 0x10, 12, 1),
PINS_FIELD16(176, 179, 0xb70, 0x10, 15, 1),
PIN_FIELD16(180, 180, 0xb00, 0x10, 7, 1),
PINS_FIELD16(181, 184, 0xb00, 0x10, 3, 1),
PINS_FIELD16(185, 191, 0xb60, 0x10, 11, 1),
PIN_FIELD16(192, 192, 0xb40, 0x10, 3, 1),
PINS_FIELD16(193, 194, 0xb40, 0x10, 7, 1),
PINS_FIELD16(195, 196, 0xb40, 0x10, 3, 1),
};
static const struct mtk_pin_reg_calc mt6795_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6795_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6795_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6795_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6795_pin_do_range),
[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6795_pin_sr_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6795_pin_smt_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6795_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6795_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6795_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6795_pin_r1_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6795_pin_ies_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6795_pin_pullen_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6795_pin_pullsel_range),
};
static const struct mtk_eint_hw mt6795_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = 224,
.db_cnt = 32,
.db_time = debounce_time_mt6795,
};
static const unsigned int mt6795_pull_type[] = {
MTK_PULL_PULLSEL_TYPE,/*0*/ MTK_PULL_PULLSEL_TYPE,/*1*/
MTK_PULL_PULLSEL_TYPE,/*2*/ MTK_PULL_PULLSEL_TYPE,/*3*/
MTK_PULL_PULLSEL_TYPE,/*4*/ MTK_PULL_PULLSEL_TYPE,/*5*/
MTK_PULL_PULLSEL_TYPE,/*6*/ MTK_PULL_PULLSEL_TYPE,/*7*/
MTK_PULL_PULLSEL_TYPE,/*8*/ MTK_PULL_PULLSEL_TYPE,/*9*/
MTK_PULL_PULLSEL_TYPE,/*10*/ MTK_PULL_PULLSEL_TYPE,/*11*/
MTK_PULL_PULLSEL_TYPE,/*12*/ MTK_PULL_PULLSEL_TYPE,/*13*/
MTK_PULL_PULLSEL_TYPE,/*14*/ MTK_PULL_PULLSEL_TYPE,/*15*/
MTK_PULL_PULLSEL_TYPE,/*16*/ MTK_PULL_PULLSEL_TYPE,/*17*/
MTK_PULL_PULLSEL_TYPE,/*18*/ MTK_PULL_PULLSEL_TYPE,/*19*/
MTK_PULL_PULLSEL_TYPE,/*20*/ MTK_PULL_PULLSEL_TYPE,/*21*/
MTK_PULL_PULLSEL_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PULLSEL_TYPE,/*29*/
MTK_PULL_PULLSEL_TYPE,/*30*/ MTK_PULL_PULLSEL_TYPE,/*31*/
MTK_PULL_PULLSEL_TYPE,/*32*/ MTK_PULL_PULLSEL_TYPE,/*33*/
MTK_PULL_PULLSEL_TYPE,/*34*/ MTK_PULL_PULLSEL_TYPE,/*35*/
MTK_PULL_PULLSEL_TYPE,/*36*/ MTK_PULL_PULLSEL_TYPE,/*37*/
MTK_PULL_PULLSEL_TYPE,/*38*/ MTK_PULL_PULLSEL_TYPE,/*39*/
MTK_PULL_PULLSEL_TYPE,/*40*/ MTK_PULL_PULLSEL_TYPE,/*41*/
MTK_PULL_PULLSEL_TYPE,/*42*/ MTK_PULL_PULLSEL_TYPE,/*43*/
MTK_PULL_PULLSEL_TYPE,/*44*/ MTK_PULL_PULLSEL_TYPE,/*45*/
MTK_PULL_PULLSEL_TYPE,/*46*/ MTK_PULL_PULLSEL_TYPE,/*47*/
MTK_PULL_PULLSEL_TYPE,/*48*/ MTK_PULL_PULLSEL_TYPE,/*49*/
MTK_PULL_PULLSEL_TYPE,/*50*/ MTK_PULL_PULLSEL_TYPE,/*51*/
MTK_PULL_PULLSEL_TYPE,/*52*/ MTK_PULL_PULLSEL_TYPE,/*53*/
MTK_PULL_PULLSEL_TYPE,/*54*/ MTK_PULL_PULLSEL_TYPE,/*55*/
MTK_PULL_PULLSEL_TYPE,/*56*/ MTK_PULL_PULLSEL_TYPE,/*57*/
MTK_PULL_PULLSEL_TYPE,/*58*/ MTK_PULL_PULLSEL_TYPE,/*59*/
MTK_PULL_PULLSEL_TYPE,/*60*/ MTK_PULL_PULLSEL_TYPE,/*61*/
MTK_PULL_PULLSEL_TYPE,/*62*/ MTK_PULL_PULLSEL_TYPE,/*63*/
MTK_PULL_PULLSEL_TYPE,/*64*/ MTK_PULL_PULLSEL_TYPE,/*65*/
MTK_PULL_PULLSEL_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PULLSEL_TYPE,/*83*/
MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
MTK_PULL_PULLSEL_TYPE,/*90*/ MTK_PULL_PULLSEL_TYPE,/*91*/
MTK_PULL_PULLSEL_TYPE,/*92*/ MTK_PULL_PULLSEL_TYPE,/*93*/
MTK_PULL_PULLSEL_TYPE,/*94*/ MTK_PULL_PULLSEL_TYPE,/*95*/
MTK_PULL_PULLSEL_TYPE,/*96*/ MTK_PULL_PULLSEL_TYPE,/*97*/
MTK_PULL_PULLSEL_TYPE,/*98*/ MTK_PULL_PULLSEL_TYPE,/*99*/
MTK_PULL_PUPD_R1R0_TYPE,/*100*/ MTK_PULL_PUPD_R1R0_TYPE,/*101*/
MTK_PULL_PUPD_R1R0_TYPE,/*102*/ MTK_PULL_PUPD_R1R0_TYPE,/*103*/
MTK_PULL_PUPD_R1R0_TYPE,/*104*/ MTK_PULL_PUPD_R1R0_TYPE,/*105*/
MTK_PULL_PULLSEL_TYPE,/*106*/ MTK_PULL_PULLSEL_TYPE,/*107*/
MTK_PULL_PULLSEL_TYPE,/*108*/ MTK_PULL_PULLSEL_TYPE,/*109*/
MTK_PULL_PULLSEL_TYPE,/*110*/ MTK_PULL_PULLSEL_TYPE,/*111*/
MTK_PULL_PULLSEL_TYPE,/*112*/ MTK_PULL_PULLSEL_TYPE,/*113*/
MTK_PULL_PULLSEL_TYPE,/*114*/ MTK_PULL_PULLSEL_TYPE,/*115*/
MTK_PULL_PULLSEL_TYPE,/*116*/ MTK_PULL_PULLSEL_TYPE,/*117*/
MTK_PULL_PULLSEL_TYPE,/*118*/ MTK_PULL_PUPD_R1R0_TYPE,/*119*/
MTK_PULL_PUPD_R1R0_TYPE,/*120*/ MTK_PULL_PUPD_R1R0_TYPE,/*121*/
MTK_PULL_PUPD_R1R0_TYPE,/*122*/ MTK_PULL_PUPD_R1R0_TYPE,/*123*/
MTK_PULL_PUPD_R1R0_TYPE,/*124*/ MTK_PULL_PULLSEL_TYPE,/*125*/
MTK_PULL_PULLSEL_TYPE,/*126*/ MTK_PULL_PULLSEL_TYPE,/*127*/
MTK_PULL_PULLSEL_TYPE,/*128*/ MTK_PULL_PULLSEL_TYPE,/*129*/
MTK_PULL_PULLSEL_TYPE,/*130*/ MTK_PULL_PULLSEL_TYPE,/*131*/
MTK_PULL_PULLSEL_TYPE,/*132*/ MTK_PULL_PULLSEL_TYPE,/*133*/
MTK_PULL_PULLSEL_TYPE,/*134*/ MTK_PULL_PULLSEL_TYPE,/*135*/
MTK_PULL_PULLSEL_TYPE,/*136*/ MTK_PULL_PULLSEL_TYPE,/*137*/
MTK_PULL_PUPD_R1R0_TYPE,/*138*/ MTK_PULL_PUPD_R1R0_TYPE,/*139*/
MTK_PULL_PUPD_R1R0_TYPE,/*140*/ MTK_PULL_PUPD_R1R0_TYPE,/*141*/
MTK_PULL_PUPD_R1R0_TYPE,/*142*/ MTK_PULL_PUPD_R1R0_TYPE,/*143*/
MTK_PULL_PUPD_R1R0_TYPE,/*144*/ MTK_PULL_PUPD_R1R0_TYPE,/*145*/
MTK_PULL_PUPD_R1R0_TYPE,/*146*/ MTK_PULL_PUPD_R1R0_TYPE,/*147*/
MTK_PULL_PUPD_R1R0_TYPE,/*148*/ MTK_PULL_PUPD_R1R0_TYPE,/*149*/
MTK_PULL_PUPD_R1R0_TYPE,/*150*/ MTK_PULL_PUPD_R1R0_TYPE,/*151*/
MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/
MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/
MTK_PULL_PUPD_R1R0_TYPE,/*156*/ MTK_PULL_PUPD_R1R0_TYPE,/*157*/
MTK_PULL_PUPD_R1R0_TYPE,/*158*/ MTK_PULL_PUPD_R1R0_TYPE,/*159*/
MTK_PULL_PUPD_R1R0_TYPE,/*160*/ MTK_PULL_PUPD_R1R0_TYPE,/*161*/
MTK_PULL_PUPD_R1R0_TYPE,/*162*/ MTK_PULL_PUPD_R1R0_TYPE,/*163*/
MTK_PULL_PUPD_R1R0_TYPE,/*164*/ MTK_PULL_PUPD_R1R0_TYPE,/*165*/
MTK_PULL_PULLSEL_TYPE,/*166*/ MTK_PULL_PULLSEL_TYPE,/*167*/
MTK_PULL_PULLSEL_TYPE,/*168*/ MTK_PULL_PULLSEL_TYPE,/*169*/
MTK_PULL_PUPD_R1R0_TYPE,/*170*/ MTK_PULL_PUPD_R1R0_TYPE,/*171*/
MTK_PULL_PUPD_R1R0_TYPE,/*172*/ MTK_PULL_PUPD_R1R0_TYPE,/*173*/
MTK_PULL_PUPD_R1R0_TYPE,/*174*/ MTK_PULL_PUPD_R1R0_TYPE,/*175*/
MTK_PULL_PULLSEL_TYPE,/*176*/ MTK_PULL_PULLSEL_TYPE,/*177*/
MTK_PULL_PULLSEL_TYPE,/*178*/ MTK_PULL_PULLSEL_TYPE,/*179*/
MTK_PULL_PULLSEL_TYPE,/*180*/ MTK_PULL_PULLSEL_TYPE,/*181*/
MTK_PULL_PULLSEL_TYPE,/*182*/ MTK_PULL_PULLSEL_TYPE,/*183*/
MTK_PULL_PULLSEL_TYPE,/*184*/ MTK_PULL_PULLSEL_TYPE,/*185*/
MTK_PULL_PULLSEL_TYPE,/*186*/ MTK_PULL_PULLSEL_TYPE,/*187*/
MTK_PULL_PULLSEL_TYPE,/*188*/ MTK_PULL_PULLSEL_TYPE,/*189*/
MTK_PULL_PULLSEL_TYPE,/*190*/ MTK_PULL_PULLSEL_TYPE,/*191*/
MTK_PULL_PULLSEL_TYPE,/*192*/ MTK_PULL_PULLSEL_TYPE,/*193*/
MTK_PULL_PULLSEL_TYPE,/*194*/ MTK_PULL_PULLSEL_TYPE,/*195*/
MTK_PULL_PULLSEL_TYPE,/*196*/
};
static const struct mtk_pin_soc mt6795_data = {
.reg_cal = mt6795_reg_cals,
.pins = mtk_pins_mt6795,
.npins = ARRAY_SIZE(mtk_pins_mt6795),
.ngrps = ARRAY_SIZE(mtk_pins_mt6795),
.nfuncs = 8,
.eint_hw = &mt6795_eint_hw,
.gpio_m = 0,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.pull_type = mt6795_pull_type,
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt6795_pctrl_match[] = {
{ .compatible = "mediatek,mt6795-pinctrl", .data = &mt6795_data },
{ }
};
static struct platform_driver mt6795_pinctrl_driver = {
.driver = {
.name = "mt6795-pinctrl",
.of_match_table = mt6795_pctrl_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mt6795_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt6795.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Min.Guo <[email protected]>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8516.h"
static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
};
static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
};
static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
};
static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
.pins = mtk_pins_mt8516,
.npins = ARRAY_SIZE(mtk_pins_mt8516),
.grp_desc = mt8516_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
.pin_drv_grp = mt8516_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
.spec_ies = mt8516_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
.spec_pupd = mt8516_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
.spec_smt = mt8516_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0500,
.pullsel_offset = 0x0600,
.dout_offset = 0x0100,
.din_offset = 0x0200,
.pinmux_offset = 0x0300,
.type1_start = 125,
.type1_end = 125,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 169,
.db_cnt = 64,
.db_time = debounce_time_mt6795,
},
};
static const struct of_device_id mt8516_pctrl_match[] = {
{ .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8516-pinctrl",
.of_match_table = mt8516_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8516.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Min.Guo <[email protected]>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8167.h"
static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
};
static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
};
static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
};
static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
.pins = mtk_pins_mt8167,
.npins = ARRAY_SIZE(mtk_pins_mt8167),
.grp_desc = mt8167_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
.pin_drv_grp = mt8167_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
.spec_ies = mt8167_ies_set,
.n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
.spec_pupd = mt8167_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
.spec_smt = mt8167_smt_set,
.n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0500,
.pullsel_offset = 0x0600,
.dout_offset = 0x0100,
.din_offset = 0x0200,
.pinmux_offset = 0x0300,
.type1_start = 125,
.type1_end = 125,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 169,
.db_cnt = 64,
.db_time = debounce_time_mt6795,
},
};
static const struct of_device_id mt8167_pctrl_match[] = {
{ .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
{}
};
MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt8167-pinctrl",
.of_match_table = mt8167_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8167.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017-2018 MediaTek Inc.
*
* Author: Sean Wang <[email protected]>
*
*/
#include "pinctrl-moore.h"
#define MT7622_PIN(_number, _name) \
MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
};
static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
};
static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
[PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
[PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
};
static const struct mtk_pin_desc mt7622_pins[] = {
MT7622_PIN(0, "GPIO_A"),
MT7622_PIN(1, "I2S1_IN"),
MT7622_PIN(2, "I2S1_OUT"),
MT7622_PIN(3, "I2S_BCLK"),
MT7622_PIN(4, "I2S_WS"),
MT7622_PIN(5, "I2S_MCLK"),
MT7622_PIN(6, "TXD0"),
MT7622_PIN(7, "RXD0"),
MT7622_PIN(8, "SPI_WP"),
MT7622_PIN(9, "SPI_HOLD"),
MT7622_PIN(10, "SPI_CLK"),
MT7622_PIN(11, "SPI_MOSI"),
MT7622_PIN(12, "SPI_MISO"),
MT7622_PIN(13, "SPI_CS"),
MT7622_PIN(14, "I2C_SDA"),
MT7622_PIN(15, "I2C_SCL"),
MT7622_PIN(16, "I2S2_IN"),
MT7622_PIN(17, "I2S3_IN"),
MT7622_PIN(18, "I2S4_IN"),
MT7622_PIN(19, "I2S2_OUT"),
MT7622_PIN(20, "I2S3_OUT"),
MT7622_PIN(21, "I2S4_OUT"),
MT7622_PIN(22, "GPIO_B"),
MT7622_PIN(23, "MDC"),
MT7622_PIN(24, "MDIO"),
MT7622_PIN(25, "G2_TXD0"),
MT7622_PIN(26, "G2_TXD1"),
MT7622_PIN(27, "G2_TXD2"),
MT7622_PIN(28, "G2_TXD3"),
MT7622_PIN(29, "G2_TXEN"),
MT7622_PIN(30, "G2_TXC"),
MT7622_PIN(31, "G2_RXD0"),
MT7622_PIN(32, "G2_RXD1"),
MT7622_PIN(33, "G2_RXD2"),
MT7622_PIN(34, "G2_RXD3"),
MT7622_PIN(35, "G2_RXDV"),
MT7622_PIN(36, "G2_RXC"),
MT7622_PIN(37, "NCEB"),
MT7622_PIN(38, "NWEB"),
MT7622_PIN(39, "NREB"),
MT7622_PIN(40, "NDL4"),
MT7622_PIN(41, "NDL5"),
MT7622_PIN(42, "NDL6"),
MT7622_PIN(43, "NDL7"),
MT7622_PIN(44, "NRB"),
MT7622_PIN(45, "NCLE"),
MT7622_PIN(46, "NALE"),
MT7622_PIN(47, "NDL0"),
MT7622_PIN(48, "NDL1"),
MT7622_PIN(49, "NDL2"),
MT7622_PIN(50, "NDL3"),
MT7622_PIN(51, "MDI_TP_P0"),
MT7622_PIN(52, "MDI_TN_P0"),
MT7622_PIN(53, "MDI_RP_P0"),
MT7622_PIN(54, "MDI_RN_P0"),
MT7622_PIN(55, "MDI_TP_P1"),
MT7622_PIN(56, "MDI_TN_P1"),
MT7622_PIN(57, "MDI_RP_P1"),
MT7622_PIN(58, "MDI_RN_P1"),
MT7622_PIN(59, "MDI_RP_P2"),
MT7622_PIN(60, "MDI_RN_P2"),
MT7622_PIN(61, "MDI_TP_P2"),
MT7622_PIN(62, "MDI_TN_P2"),
MT7622_PIN(63, "MDI_TP_P3"),
MT7622_PIN(64, "MDI_TN_P3"),
MT7622_PIN(65, "MDI_RP_P3"),
MT7622_PIN(66, "MDI_RN_P3"),
MT7622_PIN(67, "MDI_RP_P4"),
MT7622_PIN(68, "MDI_RN_P4"),
MT7622_PIN(69, "MDI_TP_P4"),
MT7622_PIN(70, "MDI_TN_P4"),
MT7622_PIN(71, "PMIC_SCL"),
MT7622_PIN(72, "PMIC_SDA"),
MT7622_PIN(73, "SPIC1_CLK"),
MT7622_PIN(74, "SPIC1_MOSI"),
MT7622_PIN(75, "SPIC1_MISO"),
MT7622_PIN(76, "SPIC1_CS"),
MT7622_PIN(77, "GPIO_D"),
MT7622_PIN(78, "WATCHDOG"),
MT7622_PIN(79, "RTS3_N"),
MT7622_PIN(80, "CTS3_N"),
MT7622_PIN(81, "TXD3"),
MT7622_PIN(82, "RXD3"),
MT7622_PIN(83, "PERST0_N"),
MT7622_PIN(84, "PERST1_N"),
MT7622_PIN(85, "WLED_N"),
MT7622_PIN(86, "EPHY_LED0_N"),
MT7622_PIN(87, "AUXIN0"),
MT7622_PIN(88, "AUXIN1"),
MT7622_PIN(89, "AUXIN2"),
MT7622_PIN(90, "AUXIN3"),
MT7622_PIN(91, "TXD4"),
MT7622_PIN(92, "RXD4"),
MT7622_PIN(93, "RTS4_N"),
MT7622_PIN(94, "CTS4_N"),
MT7622_PIN(95, "PWM1"),
MT7622_PIN(96, "PWM2"),
MT7622_PIN(97, "PWM3"),
MT7622_PIN(98, "PWM4"),
MT7622_PIN(99, "PWM5"),
MT7622_PIN(100, "PWM6"),
MT7622_PIN(101, "PWM7"),
MT7622_PIN(102, "GPIO_E"),
};
/* List all groups consisting of these pins dedicated to the enablement of
* certain hardware block and the corresponding mode for all of the pins. The
* hardware probably has multiple combinations of these pinouts.
*/
/* ANTSEL */
static int mt7622_antsel0_pins[] = { 91, };
static int mt7622_antsel0_funcs[] = { 5, };
static int mt7622_antsel1_pins[] = { 92, };
static int mt7622_antsel1_funcs[] = { 5, };
static int mt7622_antsel2_pins[] = { 93, };
static int mt7622_antsel2_funcs[] = { 5, };
static int mt7622_antsel3_pins[] = { 94, };
static int mt7622_antsel3_funcs[] = { 5, };
static int mt7622_antsel4_pins[] = { 95, };
static int mt7622_antsel4_funcs[] = { 5, };
static int mt7622_antsel5_pins[] = { 96, };
static int mt7622_antsel5_funcs[] = { 5, };
static int mt7622_antsel6_pins[] = { 97, };
static int mt7622_antsel6_funcs[] = { 5, };
static int mt7622_antsel7_pins[] = { 98, };
static int mt7622_antsel7_funcs[] = { 5, };
static int mt7622_antsel8_pins[] = { 99, };
static int mt7622_antsel8_funcs[] = { 5, };
static int mt7622_antsel9_pins[] = { 100, };
static int mt7622_antsel9_funcs[] = { 5, };
static int mt7622_antsel10_pins[] = { 101, };
static int mt7622_antsel10_funcs[] = { 5, };
static int mt7622_antsel11_pins[] = { 102, };
static int mt7622_antsel11_funcs[] = { 5, };
static int mt7622_antsel12_pins[] = { 73, };
static int mt7622_antsel12_funcs[] = { 5, };
static int mt7622_antsel13_pins[] = { 74, };
static int mt7622_antsel13_funcs[] = { 5, };
static int mt7622_antsel14_pins[] = { 75, };
static int mt7622_antsel14_funcs[] = { 5, };
static int mt7622_antsel15_pins[] = { 76, };
static int mt7622_antsel15_funcs[] = { 5, };
static int mt7622_antsel16_pins[] = { 77, };
static int mt7622_antsel16_funcs[] = { 5, };
static int mt7622_antsel17_pins[] = { 22, };
static int mt7622_antsel17_funcs[] = { 5, };
static int mt7622_antsel18_pins[] = { 79, };
static int mt7622_antsel18_funcs[] = { 5, };
static int mt7622_antsel19_pins[] = { 80, };
static int mt7622_antsel19_funcs[] = { 5, };
static int mt7622_antsel20_pins[] = { 81, };
static int mt7622_antsel20_funcs[] = { 5, };
static int mt7622_antsel21_pins[] = { 82, };
static int mt7622_antsel21_funcs[] = { 5, };
static int mt7622_antsel22_pins[] = { 14, };
static int mt7622_antsel22_funcs[] = { 5, };
static int mt7622_antsel23_pins[] = { 15, };
static int mt7622_antsel23_funcs[] = { 5, };
static int mt7622_antsel24_pins[] = { 16, };
static int mt7622_antsel24_funcs[] = { 5, };
static int mt7622_antsel25_pins[] = { 17, };
static int mt7622_antsel25_funcs[] = { 5, };
static int mt7622_antsel26_pins[] = { 18, };
static int mt7622_antsel26_funcs[] = { 5, };
static int mt7622_antsel27_pins[] = { 19, };
static int mt7622_antsel27_funcs[] = { 5, };
static int mt7622_antsel28_pins[] = { 20, };
static int mt7622_antsel28_funcs[] = { 5, };
static int mt7622_antsel29_pins[] = { 21, };
static int mt7622_antsel29_funcs[] = { 5, };
/* EMMC */
static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
static int mt7622_emmc_rst_pins[] = { 37, };
static int mt7622_emmc_rst_funcs[] = { 1, };
/* LED for EPHY */
static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
static int mt7622_ephy0_led_pins[] = { 86, };
static int mt7622_ephy0_led_funcs[] = { 0, };
static int mt7622_ephy1_led_pins[] = { 91, };
static int mt7622_ephy1_led_funcs[] = { 2, };
static int mt7622_ephy2_led_pins[] = { 92, };
static int mt7622_ephy2_led_funcs[] = { 2, };
static int mt7622_ephy3_led_pins[] = { 93, };
static int mt7622_ephy3_led_funcs[] = { 2, };
static int mt7622_ephy4_led_pins[] = { 94, };
static int mt7622_ephy4_led_funcs[] = { 2, };
/* Embedded Switch */
static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
62, 63, 64, 65, 66, 67, 68, 69, 70, };
static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, };
static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
68, 69, 70, };
static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, };
/* RGMII via ESW */
static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
67, 68, 69, 70, };
static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, };
/* RGMII via GMAC1 */
static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
67, 68, 69, 70, };
static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, };
/* RGMII via GMAC2 */
static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, };
static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, };
/* I2C */
static int mt7622_i2c0_pins[] = { 14, 15, };
static int mt7622_i2c0_funcs[] = { 0, 0, };
static int mt7622_i2c1_0_pins[] = { 55, 56, };
static int mt7622_i2c1_0_funcs[] = { 0, 0, };
static int mt7622_i2c1_1_pins[] = { 73, 74, };
static int mt7622_i2c1_1_funcs[] = { 3, 3, };
static int mt7622_i2c1_2_pins[] = { 87, 88, };
static int mt7622_i2c1_2_funcs[] = { 0, 0, };
static int mt7622_i2c2_0_pins[] = { 57, 58, };
static int mt7622_i2c2_0_funcs[] = { 0, 0, };
static int mt7622_i2c2_1_pins[] = { 75, 76, };
static int mt7622_i2c2_1_funcs[] = { 3, 3, };
static int mt7622_i2c2_2_pins[] = { 89, 90, };
static int mt7622_i2c2_2_funcs[] = { 0, 0, };
/* I2S */
static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
static int mt7622_i2s1_in_data_pins[] = { 1, };
static int mt7622_i2s1_in_data_funcs[] = { 0, };
static int mt7622_i2s2_in_data_pins[] = { 16, };
static int mt7622_i2s2_in_data_funcs[] = { 0, };
static int mt7622_i2s3_in_data_pins[] = { 17, };
static int mt7622_i2s3_in_data_funcs[] = { 0, };
static int mt7622_i2s4_in_data_pins[] = { 18, };
static int mt7622_i2s4_in_data_funcs[] = { 0, };
static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
static int mt7622_i2s1_out_data_pins[] = { 2, };
static int mt7622_i2s1_out_data_funcs[] = { 0, };
static int mt7622_i2s2_out_data_pins[] = { 19, };
static int mt7622_i2s2_out_data_funcs[] = { 0, };
static int mt7622_i2s3_out_data_pins[] = { 20, };
static int mt7622_i2s3_out_data_funcs[] = { 0, };
static int mt7622_i2s4_out_data_pins[] = { 21, };
static int mt7622_i2s4_out_data_funcs[] = { 0, };
/* IR */
static int mt7622_ir_0_tx_pins[] = { 16, };
static int mt7622_ir_0_tx_funcs[] = { 4, };
static int mt7622_ir_1_tx_pins[] = { 59, };
static int mt7622_ir_1_tx_funcs[] = { 5, };
static int mt7622_ir_2_tx_pins[] = { 99, };
static int mt7622_ir_2_tx_funcs[] = { 3, };
static int mt7622_ir_0_rx_pins[] = { 17, };
static int mt7622_ir_0_rx_funcs[] = { 4, };
static int mt7622_ir_1_rx_pins[] = { 60, };
static int mt7622_ir_1_rx_funcs[] = { 5, };
static int mt7622_ir_2_rx_pins[] = { 100, };
static int mt7622_ir_2_rx_funcs[] = { 3, };
/* MDIO */
static int mt7622_mdc_mdio_pins[] = { 23, 24, };
static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
/* PCIE */
static int mt7622_pcie0_0_waken_pins[] = { 14, };
static int mt7622_pcie0_0_waken_funcs[] = { 2, };
static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
static int mt7622_pcie0_1_waken_pins[] = { 79, };
static int mt7622_pcie0_1_waken_funcs[] = { 4, };
static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
static int mt7622_pcie1_0_waken_pins[] = { 14, };
static int mt7622_pcie1_0_waken_funcs[] = { 3, };
static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
static int mt7622_pcie0_pad_perst_pins[] = { 83, };
static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
static int mt7622_pcie1_pad_perst_pins[] = { 84, };
static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
/* PMIC bus */
static int mt7622_pmic_bus_pins[] = { 71, 72, };
static int mt7622_pmic_bus_funcs[] = { 0, 0, };
/* Parallel NAND */
static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
48, 49, 50, };
static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, };
/* PWM */
static int mt7622_pwm_ch1_0_pins[] = { 51, };
static int mt7622_pwm_ch1_0_funcs[] = { 3, };
static int mt7622_pwm_ch1_1_pins[] = { 73, };
static int mt7622_pwm_ch1_1_funcs[] = { 4, };
static int mt7622_pwm_ch1_2_pins[] = { 95, };
static int mt7622_pwm_ch1_2_funcs[] = { 0, };
static int mt7622_pwm_ch2_0_pins[] = { 52, };
static int mt7622_pwm_ch2_0_funcs[] = { 3, };
static int mt7622_pwm_ch2_1_pins[] = { 74, };
static int mt7622_pwm_ch2_1_funcs[] = { 4, };
static int mt7622_pwm_ch2_2_pins[] = { 96, };
static int mt7622_pwm_ch2_2_funcs[] = { 0, };
static int mt7622_pwm_ch3_0_pins[] = { 53, };
static int mt7622_pwm_ch3_0_funcs[] = { 3, };
static int mt7622_pwm_ch3_1_pins[] = { 75, };
static int mt7622_pwm_ch3_1_funcs[] = { 4, };
static int mt7622_pwm_ch3_2_pins[] = { 97, };
static int mt7622_pwm_ch3_2_funcs[] = { 0, };
static int mt7622_pwm_ch4_0_pins[] = { 54, };
static int mt7622_pwm_ch4_0_funcs[] = { 3, };
static int mt7622_pwm_ch4_1_pins[] = { 67, };
static int mt7622_pwm_ch4_1_funcs[] = { 3, };
static int mt7622_pwm_ch4_2_pins[] = { 76, };
static int mt7622_pwm_ch4_2_funcs[] = { 4, };
static int mt7622_pwm_ch4_3_pins[] = { 98, };
static int mt7622_pwm_ch4_3_funcs[] = { 0, };
static int mt7622_pwm_ch5_0_pins[] = { 68, };
static int mt7622_pwm_ch5_0_funcs[] = { 3, };
static int mt7622_pwm_ch5_1_pins[] = { 77, };
static int mt7622_pwm_ch5_1_funcs[] = { 4, };
static int mt7622_pwm_ch5_2_pins[] = { 99, };
static int mt7622_pwm_ch5_2_funcs[] = { 0, };
static int mt7622_pwm_ch6_0_pins[] = { 69, };
static int mt7622_pwm_ch6_0_funcs[] = { 3, };
static int mt7622_pwm_ch6_1_pins[] = { 78, };
static int mt7622_pwm_ch6_1_funcs[] = { 4, };
static int mt7622_pwm_ch6_2_pins[] = { 81, };
static int mt7622_pwm_ch6_2_funcs[] = { 4, };
static int mt7622_pwm_ch6_3_pins[] = { 100, };
static int mt7622_pwm_ch6_3_funcs[] = { 0, };
/* SD */
static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
/* Serial NAND */
static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
/* SPI NOR */
static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
/* SPIC */
static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
/* TDM */
static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
static int mt7622_tdm_0_out_data_pins[] = { 20, };
static int mt7622_tdm_0_out_data_funcs[] = { 3, };
static int mt7622_tdm_0_in_data_pins[] = { 21, };
static int mt7622_tdm_0_in_data_funcs[] = { 3, };
static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
static int mt7622_tdm_1_out_data_pins[] = { 55, };
static int mt7622_tdm_1_out_data_funcs[] = { 3, };
static int mt7622_tdm_1_in_data_pins[] = { 56, };
static int mt7622_tdm_1_in_data_funcs[] = { 3, };
/* UART */
static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
/* Watchdog */
static int mt7622_watchdog_pins[] = { 78, };
static int mt7622_watchdog_funcs[] = { 0, };
/* WLAN LED */
static int mt7622_wled_pins[] = { 85, };
static int mt7622_wled_funcs[] = { 0, };
static const struct group_desc mt7622_groups[] = {
PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
PINCTRL_PIN_GROUP("esw", mt7622_esw),
PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
mt7622_tdm_0_out_mclk_bclk_ws),
PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
mt7622_tdm_0_in_mclk_bclk_ws),
PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
mt7622_tdm_1_out_mclk_bclk_ws),
PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
mt7622_tdm_1_in_mclk_bclk_ws),
PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
PINCTRL_PIN_GROUP("wled", mt7622_wled),
};
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
"antsel3", "antsel4", "antsel5",
"antsel6", "antsel7", "antsel8",
"antsel9", "antsel10", "antsel11",
"antsel12", "antsel13", "antsel14",
"antsel15", "antsel16", "antsel17",
"antsel18", "antsel19", "antsel20",
"antsel21", "antsel22", "antsel23",
"antsel24", "antsel25", "antsel26",
"antsel27", "antsel28", "antsel29",};
static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
"esw_p2_p3_p4", "mdc_mdio",
"rgmii_via_gmac1",
"rgmii_via_gmac2",
"rgmii_via_esw", };
static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
"i2c1_2", "i2c2_0", "i2c2_1",
"i2c2_2", };
static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
"i2s_in_mclk_bclk_ws",
"i2s1_in_data", "i2s2_in_data",
"i2s3_in_data", "i2s4_in_data",
"i2s1_out_data", "i2s2_out_data",
"i2s3_out_data", "i2s4_out_data", };
static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
"ir_0_rx", "ir_1_rx", "ir_2_rx"};
static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
"ephy1_led", "ephy2_led",
"ephy3_led", "ephy4_led",
"wled", };
static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
"pcie0_1_waken", "pcie0_1_clkreq",
"pcie1_0_waken", "pcie1_0_clkreq",
"pcie0_pad_perst",
"pcie1_pad_perst", };
static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
"pwm_ch1_2", "pwm_ch2_0",
"pwm_ch2_1", "pwm_ch2_2",
"pwm_ch3_0", "pwm_ch3_1",
"pwm_ch3_2", "pwm_ch4_0",
"pwm_ch4_1", "pwm_ch4_2",
"pwm_ch4_3", "pwm_ch5_0",
"pwm_ch5_1", "pwm_ch5_2",
"pwm_ch6_0", "pwm_ch6_1",
"pwm_ch6_2", "pwm_ch6_3", };
static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
"spic1_1", "spic2_0",
"spic2_0_wp_hold", };
static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
"tdm_0_in_mclk_bclk_ws",
"tdm_0_out_data",
"tdm_0_in_data",
"tdm_1_out_mclk_bclk_ws",
"tdm_1_in_mclk_bclk_ws",
"tdm_1_out_data",
"tdm_1_in_data", };
static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
"uart1_0_tx_rx", "uart1_0_rts_cts",
"uart1_1_tx_rx", "uart1_1_rts_cts",
"uart2_0_tx_rx", "uart2_0_rts_cts",
"uart2_1_tx_rx", "uart2_1_rts_cts",
"uart2_2_tx_rx", "uart2_2_rts_cts",
"uart2_3_tx_rx",
"uart3_0_tx_rx",
"uart3_1_tx_rx", "uart3_1_rts_cts",
"uart4_0_tx_rx",
"uart4_1_tx_rx", "uart4_1_rts_cts",
"uart4_2_tx_rx",
"uart4_2_rts_cts",};
static const char *mt7622_wdt_groups[] = { "watchdog", };
static const struct function_desc mt7622_functions[] = {
{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
{"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
{"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
{"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
{"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
{"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
};
static const struct mtk_eint_hw mt7622_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = ARRAY_SIZE(mt7622_pins),
.db_cnt = 20,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt7622_data = {
.reg_cal = mt7622_reg_cals,
.pins = mt7622_pins,
.npins = ARRAY_SIZE(mt7622_pins),
.grps = mt7622_groups,
.ngrps = ARRAY_SIZE(mt7622_groups),
.funcs = mt7622_functions,
.nfuncs = ARRAY_SIZE(mt7622_functions),
.eint_hw = &mt7622_eint_hw,
.gpio_m = 1,
.ies_present = false,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
.bias_disable_get = mtk_pinconf_bias_disable_get,
.bias_set = mtk_pinconf_bias_set,
.bias_get = mtk_pinconf_bias_get,
.drive_set = mtk_pinconf_drive_set,
.drive_get = mtk_pinconf_drive_get,
};
static const struct of_device_id mt7622_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt7622-pinctrl", },
{ }
};
static int mt7622_pinctrl_probe(struct platform_device *pdev)
{
return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
}
static struct platform_driver mt7622_pinctrl_driver = {
.driver = {
.name = "mt7622-pinctrl",
.of_match_table = mt7622_pinctrl_of_match,
},
.probe = mt7622_pinctrl_probe,
};
static int __init mt7622_pinctrl_init(void)
{
return platform_driver_register(&mt7622_pinctrl_driver);
}
arch_initcall(mt7622_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7622.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: ZH Chen <[email protected]>
*
*/
#include <linux/module.h>
#include "pinctrl-mtk-mt6765.h"
#include "pinctrl-paris.h"
/* MT6765 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
* iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
* iocfg[6]:0x10002500, iocfg[7]:0x10002600.
* _i_base could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 0)
#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 1)
static const struct mtk_pin_field_calc mt6765_pin_mode_range[] = {
PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt6765_pin_dir_range[] = {
PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_di_range[] = {
PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_do_range[] = {
PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_smt_range[] = {
PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1),
PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1),
PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1),
PINS_FIELD_BASE(17, 20, 6, 0x00b0, 0x10, 8, 1),
PINS_FIELD_BASE(21, 24, 6, 0x00b0, 0x10, 9, 1),
PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 1, 1),
PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1),
PINS_FIELD_BASE(35, 36, 6, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(37, 37, 6, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 6, 0x00b0, 0x10, 4, 1),
PINS_FIELD_BASE(39, 40, 6, 0x00b0, 0x10, 3, 1),
PINS_FIELD_BASE(41, 42, 7, 0x00c0, 0x10, 6, 1),
PIN_FIELD_BASE(43, 43, 7, 0x00c0, 0x10, 3, 1),
PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 4, 1),
PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 8, 1),
PINS_FIELD_BASE(46, 47, 7, 0x00c0, 0x10, 7, 1),
PIN_FIELD_BASE(48, 48, 7, 0x00c0, 0x10, 15, 1),
PIN_FIELD_BASE(49, 49, 7, 0x00c0, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 7, 0x00c0, 0x10, 14, 1),
PIN_FIELD_BASE(51, 51, 7, 0x00c0, 0x10, 16, 1),
PINS_FIELD_BASE(52, 57, 7, 0x00c0, 0x10, 0, 1),
PINS_FIELD_BASE(58, 60, 7, 0x00c0, 0x10, 12, 1),
PINS_FIELD_BASE(61, 62, 3, 0x0080, 0x10, 5, 1),
PINS_FIELD_BASE(63, 64, 3, 0x0080, 0x10, 4, 1),
PINS_FIELD_BASE(65, 66, 3, 0x0080, 0x10, 7, 1),
PINS_FIELD_BASE(67, 68, 3, 0x0080, 0x10, 6, 1),
PINS_FIELD_BASE(69, 73, 3, 0x0080, 0x10, 1, 1),
PINS_FIELD_BASE(74, 78, 3, 0x0080, 0x10, 2, 1),
PINS_FIELD_BASE(79, 80, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(85, 85, 7, 0x00c0, 0x10, 12, 1),
PIN_FIELD_BASE(86, 86, 7, 0x00c0, 0x10, 13, 1),
PIN_FIELD_BASE(87, 87, 7, 0x00c0, 0x10, 2, 1),
PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 1, 1),
PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 13, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 8, 1),
PINS_FIELD_BASE(91, 92, 2, 0x00b0, 0x10, 8, 1),
PINS_FIELD_BASE(93, 94, 2, 0x00b0, 0x10, 7, 1),
PINS_FIELD_BASE(95, 96, 2, 0x00b0, 0x10, 14, 1),
PINS_FIELD_BASE(97, 98, 2, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(99, 99, 2, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1),
PINS_FIELD_BASE(101, 102, 2, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 9, 1),
PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 11, 1),
PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 10, 1),
PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 12, 1),
PIN_FIELD_BASE(107, 107, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(108, 108, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(109, 109, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(110, 110, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 1, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(112, 112, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(114, 114, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(115, 115, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 1, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(118, 118, 1, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(126, 126, 4, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(127, 127, 4, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(128, 128, 4, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(129, 129, 4, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(130, 130, 4, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(131, 131, 4, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(132, 132, 4, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(133, 133, 4, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(134, 134, 5, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(135, 135, 5, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(136, 136, 5, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(137, 137, 5, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(138, 138, 5, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 5, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(140, 140, 5, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(141, 141, 5, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(142, 142, 5, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0060, 0x10, 3, 1),
PINS_FIELD_BASE(144, 147, 5, 0x0060, 0x10, 10, 1),
PINS_FIELD_BASE(148, 149, 5, 0x0060, 0x10, 12, 1),
PINS_FIELD_BASE(150, 151, 7, 0x00c0, 0x10, 9, 1),
PINS_FIELD_BASE(152, 153, 7, 0x00c0, 0x10, 10, 1),
PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 11, 1),
PINS_FIELD_BASE(155, 158, 3, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(159, 159, 7, 0x00c0, 0x10, 11, 1),
PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(161, 161, 1, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(162, 162, 1, 0x0080, 0x10, 16, 1),
PINS_FIELD_BASE(163, 170, 4, 0x0080, 0x10, 0, 1),
PINS_FIELD_BASE(171, 179, 7, 0x00c0, 0x10, 5, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_pd_range[] = {
PIN_FIELD_BASE(0, 0, 2, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(1, 1, 2, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(2, 2, 2, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(3, 3, 2, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(4, 4, 2, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(5, 5, 2, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(6, 6, 2, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(7, 7, 2, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(8, 8, 3, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(9, 9, 2, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(10, 10, 2, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 2, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(12, 12, 5, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(17, 17, 6, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(18, 18, 6, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(21, 21, 6, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 6, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(23, 23, 6, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(24, 24, 6, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0040, 0x10, 3, 1),
PINS_FIELD_BASE(28, 40, 6, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 7, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(42, 42, 7, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 7, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(45, 45, 7, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 7, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(47, 47, 7, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(48, 48, 7, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 7, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(50, 50, 7, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(51, 51, 7, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 7, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(53, 53, 7, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(54, 54, 7, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 7, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(56, 56, 7, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(57, 57, 7, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(58, 58, 7, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(59, 59, 7, 0x0060, 0x10, 31, 1),
PIN_FIELD_BASE(60, 60, 7, 0x0060, 0x10, 30, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(68, 68, 3, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(69, 69, 3, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(70, 70, 3, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 3, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 3, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 3, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(76, 76, 3, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 7, 0x0060, 0x10, 29, 1),
PIN_FIELD_BASE(87, 87, 7, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(88, 88, 7, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 21, 1),
PINS_FIELD_BASE(90, 94, 3, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(95, 95, 2, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 1, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(108, 108, 1, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(109, 109, 1, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(110, 110, 1, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 1, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(112, 112, 1, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 1, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(114, 114, 1, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(115, 115, 1, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 1, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 1, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(118, 118, 1, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(119, 119, 1, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(120, 120, 1, 0x0040, 0x10, 11, 1),
PINS_FIELD_BASE(121, 133, 1, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(134, 134, 5, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(135, 135, 5, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(136, 136, 5, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(137, 137, 5, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(138, 138, 5, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 5, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(140, 140, 5, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(141, 141, 5, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(142, 142, 5, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(147, 147, 5, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(148, 148, 5, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(150, 150, 7, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(151, 151, 7, 0x0060, 0x10, 24, 1),
PIN_FIELD_BASE(152, 152, 7, 0x0060, 0x10, 25, 1),
PIN_FIELD_BASE(153, 153, 7, 0x0060, 0x10, 26, 1),
PIN_FIELD_BASE(154, 154, 7, 0x0060, 0x10, 28, 1),
PIN_FIELD_BASE(155, 155, 3, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(156, 156, 3, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(157, 157, 3, 0x0040, 0x10, 29, 1),
PIN_FIELD_BASE(158, 158, 3, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 27, 1),
PIN_FIELD_BASE(160, 160, 5, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(161, 161, 1, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(162, 162, 1, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 4, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(170, 170, 4, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(174, 174, 7, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0060, 0x10, 15, 1),
PINS_FIELD_BASE(178, 179, 7, 0x0060, 0x10, 16, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_pu_range[] = {
PIN_FIELD_BASE(0, 0, 2, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(1, 1, 2, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(2, 2, 2, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(3, 3, 2, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(4, 4, 2, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(5, 5, 2, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(6, 6, 2, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(7, 7, 2, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(8, 8, 3, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(9, 9, 2, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(10, 10, 2, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 2, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(12, 12, 5, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(14, 14, 6, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(21, 21, 6, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 6, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(23, 23, 6, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(24, 24, 6, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0060, 0x10, 3, 1),
PINS_FIELD_BASE(28, 40, 6, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 7, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(42, 42, 7, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 7, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(45, 45, 7, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 7, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(47, 47, 7, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(48, 48, 7, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 7, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(50, 50, 7, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(51, 51, 7, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 7, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(53, 53, 7, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(54, 54, 7, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 7, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(56, 56, 7, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(57, 57, 7, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(58, 58, 7, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(59, 59, 7, 0x0080, 0x10, 31, 1),
PIN_FIELD_BASE(60, 60, 7, 0x0080, 0x10, 30, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 20, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 19, 1),
PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 25, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 24, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 22, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 23, 1),
PIN_FIELD_BASE(85, 85, 7, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 29, 1),
PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(88, 88, 7, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0060, 0x10, 21, 1),
PINS_FIELD_BASE(90, 94, 3, 0x0050, 0x10, 21, 1),
PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 1, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(108, 108, 1, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(109, 109, 1, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(110, 110, 1, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 1, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(112, 112, 1, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 1, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(114, 114, 1, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(115, 115, 1, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 1, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 1, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(118, 118, 1, 0x0050, 0x10, 13, 1),
PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 14, 1),
PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 11, 1),
PINS_FIELD_BASE(121, 133, 1, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(134, 134, 5, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(135, 135, 5, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(136, 136, 5, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(137, 137, 5, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(138, 138, 5, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 5, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(140, 140, 5, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(141, 141, 5, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(142, 142, 5, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(147, 147, 5, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(148, 148, 5, 0x0040, 0x10, 15, 1),
PIN_FIELD_BASE(149, 149, 5, 0x0040, 0x10, 16, 1),
PIN_FIELD_BASE(150, 150, 7, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(151, 151, 7, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(152, 152, 7, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(153, 153, 7, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(154, 154, 7, 0x0080, 0x10, 28, 1),
PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 28, 1),
PIN_FIELD_BASE(156, 156, 3, 0x0050, 0x10, 27, 1),
PIN_FIELD_BASE(157, 157, 3, 0x0050, 0x10, 29, 1),
PIN_FIELD_BASE(158, 158, 3, 0x0050, 0x10, 26, 1),
PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 27, 1),
PIN_FIELD_BASE(160, 160, 5, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(161, 161, 1, 0x0050, 0x10, 15, 1),
PIN_FIELD_BASE(162, 162, 1, 0x0050, 0x10, 16, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 4, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(170, 170, 4, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(174, 174, 7, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(175, 175, 7, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0080, 0x10, 15, 1),
PINS_FIELD_BASE(178, 179, 7, 0x0080, 0x10, 16, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_tdsel_range[] = {
PINS_FIELD_BASE(0, 3, 2, 0x00c0, 0x10, 16, 4),
PINS_FIELD_BASE(4, 7, 2, 0x00c0, 0x10, 20, 4),
PIN_FIELD_BASE(8, 8, 3, 0x0090, 0x10, 12, 4),
PINS_FIELD_BASE(9, 11, 2, 0x00c0, 0x10, 24, 4),
PIN_FIELD_BASE(12, 12, 5, 0x0080, 0x10, 4, 4),
PINS_FIELD_BASE(13, 16, 6, 0x00e0, 0x10, 8, 4),
PINS_FIELD_BASE(17, 20, 6, 0x00e0, 0x10, 0, 4),
PINS_FIELD_BASE(21, 24, 6, 0x00e0, 0x10, 4, 4),
PINS_FIELD_BASE(25, 28, 6, 0x00d0, 0x10, 28, 4),
PIN_FIELD_BASE(29, 29, 6, 0x00d0, 0x10, 0, 4),
PIN_FIELD_BASE(30, 30, 6, 0x00d0, 0x10, 4, 4),
PINS_FIELD_BASE(31, 34, 6, 0x00d0, 0x10, 8, 4),
PINS_FIELD_BASE(35, 36, 6, 0x00d0, 0x10, 20, 4),
PIN_FIELD_BASE(37, 37, 6, 0x00d0, 0x10, 24, 4),
PIN_FIELD_BASE(38, 38, 6, 0x00d0, 0x10, 16, 4),
PINS_FIELD_BASE(39, 40, 6, 0x00d0, 0x10, 12, 4),
PINS_FIELD_BASE(41, 42, 7, 0x00d0, 0x10, 24, 4),
PIN_FIELD_BASE(43, 43, 7, 0x00d0, 0x10, 12, 4),
PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 16, 4),
PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 0, 4),
PINS_FIELD_BASE(46, 47, 7, 0x00d0, 0x10, 28, 4),
PINS_FIELD_BASE(48, 49, 7, 0x00e0, 0x10, 28, 4),
PINS_FIELD_BASE(50, 51, 7, 0x00e0, 0x10, 24, 4),
PINS_FIELD_BASE(52, 57, 7, 0x00d0, 0x10, 0, 4),
PINS_FIELD_BASE(58, 60, 7, 0x00e0, 0x10, 16, 4),
PINS_FIELD_BASE(61, 62, 3, 0x0090, 0x10, 20, 4),
PINS_FIELD_BASE(63, 64, 3, 0x0090, 0x10, 16, 4),
PINS_FIELD_BASE(65, 66, 3, 0x0090, 0x10, 28, 4),
PINS_FIELD_BASE(67, 68, 3, 0x0090, 0x10, 24, 4),
PINS_FIELD_BASE(69, 73, 3, 0x0090, 0x10, 4, 4),
PINS_FIELD_BASE(74, 78, 3, 0x0090, 0x10, 8, 4),
PINS_FIELD_BASE(79, 80, 3, 0x0090, 0x10, 0, 4),
PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 8, 4),
PINS_FIELD_BASE(82, 83, 3, 0x00a0, 0x10, 4, 4),
PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 8, 4),
PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 16, 4),
PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 20, 4),
PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 8, 4),
PIN_FIELD_BASE(88, 88, 7, 0x00d0, 0x10, 4, 4),
PIN_FIELD_BASE(89, 89, 2, 0x00d0, 0x10, 12, 4),
PIN_FIELD_BASE(90, 90, 3, 0x00a0, 0x10, 0, 4),
PINS_FIELD_BASE(91, 92, 2, 0x00d0, 0x10, 0, 4),
PINS_FIELD_BASE(93, 94, 2, 0x00c0, 0x10, 28, 4),
PINS_FIELD_BASE(95, 96, 2, 0x00d0, 0x10, 16, 4),
PINS_FIELD_BASE(97, 98, 2, 0x00c0, 0x10, 8, 4),
PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 0, 4),
PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 4, 4),
PINS_FIELD_BASE(101, 102, 2, 0x00c0, 0x10, 12, 4),
PINS_FIELD_BASE(103, 104, 2, 0x00d0, 0x10, 4, 4),
PINS_FIELD_BASE(105, 106, 2, 0x00d0, 0x10, 8, 4),
PIN_FIELD_BASE(107, 107, 1, 0x0090, 0x10, 16, 4),
PIN_FIELD_BASE(108, 108, 1, 0x0090, 0x10, 12, 4),
PIN_FIELD_BASE(109, 109, 1, 0x0090, 0x10, 20, 4),
PIN_FIELD_BASE(110, 110, 1, 0x0090, 0x10, 0, 4),
PIN_FIELD_BASE(111, 111, 1, 0x0090, 0x10, 4, 4),
PIN_FIELD_BASE(112, 112, 1, 0x0090, 0x10, 8, 4),
PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 4, 4),
PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 8, 4),
PIN_FIELD_BASE(115, 115, 1, 0x0090, 0x10, 24, 4),
PIN_FIELD_BASE(116, 116, 1, 0x0090, 0x10, 28, 4),
PIN_FIELD_BASE(117, 117, 1, 0x00a0, 0x10, 16, 4),
PIN_FIELD_BASE(118, 118, 1, 0x00a0, 0x10, 20, 4),
PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 24, 4),
PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 12, 4),
PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 0, 4),
PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 8, 4),
PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 12, 4),
PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 4, 4),
PINS_FIELD_BASE(125, 130, 4, 0x0090, 0x10, 12, 4),
PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 16, 4),
PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 12, 4),
PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 20, 4),
PIN_FIELD_BASE(134, 134, 5, 0x0080, 0x10, 12, 4),
PIN_FIELD_BASE(135, 135, 5, 0x0080, 0x10, 20, 4),
PIN_FIELD_BASE(136, 136, 5, 0x0070, 0x10, 4, 4),
PIN_FIELD_BASE(137, 137, 5, 0x0070, 0x10, 28, 4),
PIN_FIELD_BASE(138, 138, 5, 0x0070, 0x10, 16, 4),
PIN_FIELD_BASE(139, 139, 5, 0x0070, 0x10, 20, 4),
PIN_FIELD_BASE(140, 140, 5, 0x0070, 0x10, 0, 4),
PIN_FIELD_BASE(141, 141, 5, 0x0070, 0x10, 24, 4),
PIN_FIELD_BASE(142, 142, 5, 0x0070, 0x10, 8, 4),
PIN_FIELD_BASE(143, 143, 5, 0x0070, 0x10, 12, 4),
PINS_FIELD_BASE(144, 147, 5, 0x0080, 0x10, 8, 4),
PINS_FIELD_BASE(148, 149, 5, 0x0080, 0x10, 16, 4),
PINS_FIELD_BASE(150, 151, 7, 0x00e0, 0x10, 4, 4),
PINS_FIELD_BASE(152, 153, 7, 0x00e0, 0x10, 8, 4),
PIN_FIELD_BASE(154, 154, 7, 0x00e0, 0x10, 12, 4),
PINS_FIELD_BASE(155, 158, 3, 0x00a0, 0x10, 12, 4),
PIN_FIELD_BASE(159, 159, 7, 0x00e0, 0x10, 12, 4),
PIN_FIELD_BASE(160, 160, 5, 0x0080, 0x10, 0, 4),
PINS_FIELD_BASE(161, 162, 1, 0x00a0, 0x10, 28, 4),
PINS_FIELD_BASE(163, 170, 4, 0x0090, 0x10, 0, 4),
PINS_FIELD_BASE(171, 179, 7, 0x00d0, 0x10, 20, 4),
};
static const struct mtk_pin_field_calc mt6765_pin_rdsel_range[] = {
PINS_FIELD_BASE(0, 3, 2, 0x0090, 0x10, 8, 2),
PINS_FIELD_BASE(4, 7, 2, 0x0090, 0x10, 10, 2),
PIN_FIELD_BASE(8, 8, 3, 0x0060, 0x10, 6, 2),
PINS_FIELD_BASE(9, 11, 2, 0x0090, 0x10, 12, 2),
PIN_FIELD_BASE(12, 12, 5, 0x0050, 0x10, 18, 2),
PINS_FIELD_BASE(13, 16, 6, 0x00a0, 0x10, 18, 2),
PINS_FIELD_BASE(17, 20, 6, 0x00a0, 0x10, 14, 2),
PINS_FIELD_BASE(21, 24, 6, 0x00a0, 0x10, 16, 2),
PINS_FIELD_BASE(25, 28, 6, 0x00a0, 0x10, 12, 2),
PIN_FIELD_BASE(29, 29, 6, 0x0090, 0x10, 0, 6),
PIN_FIELD_BASE(30, 30, 6, 0x0090, 0x10, 6, 6),
PINS_FIELD_BASE(31, 34, 6, 0x0090, 0x10, 12, 6),
PINS_FIELD_BASE(35, 36, 6, 0x00a0, 0x10, 0, 6),
PIN_FIELD_BASE(37, 37, 6, 0x00a0, 0x10, 6, 6),
PIN_FIELD_BASE(38, 38, 6, 0x0090, 0x10, 24, 6),
PINS_FIELD_BASE(39, 40, 6, 0x0090, 0x10, 18, 6),
PINS_FIELD_BASE(41, 42, 7, 0x00a0, 0x10, 12, 2),
PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 6, 2),
PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 8, 2),
PIN_FIELD_BASE(45, 45, 7, 0x00a0, 0x10, 16, 2),
PINS_FIELD_BASE(46, 47, 7, 0x00a0, 0x10, 14, 2),
PINS_FIELD_BASE(48, 49, 7, 0x00a0, 0x10, 30, 2),
PINS_FIELD_BASE(50, 51, 7, 0x00a0, 0x10, 28, 2),
PINS_FIELD_BASE(52, 57, 7, 0x00a0, 0x10, 0, 2),
PINS_FIELD_BASE(58, 60, 7, 0x00a0, 0x10, 24, 2),
PINS_FIELD_BASE(61, 62, 3, 0x0060, 0x10, 10, 2),
PINS_FIELD_BASE(63, 64, 3, 0x0060, 0x10, 8, 2),
PINS_FIELD_BASE(65, 66, 3, 0x0060, 0x10, 14, 2),
PINS_FIELD_BASE(67, 68, 3, 0x0060, 0x10, 12, 2),
PINS_FIELD_BASE(69, 73, 3, 0x0060, 0x10, 2, 2),
PINS_FIELD_BASE(74, 78, 3, 0x0060, 0x10, 4, 2),
PINS_FIELD_BASE(79, 80, 3, 0x0060, 0x10, 0, 2),
PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 20, 2),
PINS_FIELD_BASE(82, 83, 3, 0x0060, 0x10, 18, 2),
PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 20, 2),
PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 24, 2),
PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 26, 2),
PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 4, 2),
PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 2, 2),
PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 22, 2),
PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 16, 2),
PINS_FIELD_BASE(91, 92, 2, 0x0090, 0x10, 16, 2),
PINS_FIELD_BASE(93, 94, 2, 0x0090, 0x10, 14, 2),
PINS_FIELD_BASE(95, 96, 2, 0x0090, 0x10, 24, 2),
PINS_FIELD_BASE(97, 98, 2, 0x0090, 0x10, 4, 2),
PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 0, 2),
PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 2, 2),
PINS_FIELD_BASE(101, 102, 2, 0x0090, 0x10, 6, 2),
PINS_FIELD_BASE(103, 104, 2, 0x0090, 0x10, 18, 2),
PINS_FIELD_BASE(105, 106, 2, 0x0090, 0x10, 20, 2),
PIN_FIELD_BASE(107, 107, 1, 0x0060, 0x10, 8, 2),
PIN_FIELD_BASE(108, 108, 1, 0x0060, 0x10, 6, 2),
PIN_FIELD_BASE(109, 109, 1, 0x0060, 0x10, 10, 2),
PIN_FIELD_BASE(110, 110, 1, 0x0060, 0x10, 0, 2),
PIN_FIELD_BASE(111, 111, 1, 0x0060, 0x10, 2, 2),
PIN_FIELD_BASE(112, 112, 1, 0x0060, 0x10, 4, 2),
PIN_FIELD_BASE(113, 113, 1, 0x0060, 0x10, 18, 2),
PIN_FIELD_BASE(114, 114, 1, 0x0060, 0x10, 20, 2),
PIN_FIELD_BASE(115, 115, 1, 0x0060, 0x10, 12, 2),
PIN_FIELD_BASE(116, 116, 1, 0x0060, 0x10, 14, 2),
PIN_FIELD_BASE(117, 117, 1, 0x0060, 0x10, 24, 2),
PIN_FIELD_BASE(118, 118, 1, 0x0060, 0x10, 26, 2),
PIN_FIELD_BASE(119, 119, 1, 0x0060, 0x10, 28, 2),
PIN_FIELD_BASE(120, 120, 1, 0x0060, 0x10, 22, 2),
PIN_FIELD_BASE(121, 121, 1, 0x0060, 0x10, 16, 2),
PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 8, 6),
PIN_FIELD_BASE(123, 123, 4, 0x0070, 0x10, 14, 6),
PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 2, 6),
PINS_FIELD_BASE(125, 130, 4, 0x0070, 0x10, 14, 6),
PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 20, 6),
PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 14, 6),
PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 26, 6),
PIN_FIELD_BASE(134, 134, 5, 0x0050, 0x10, 22, 2),
PIN_FIELD_BASE(135, 135, 5, 0x0050, 0x10, 30, 2),
PIN_FIELD_BASE(136, 136, 5, 0x0050, 0x10, 2, 2),
PIN_FIELD_BASE(137, 137, 5, 0x0050, 0x10, 14, 2),
PIN_FIELD_BASE(138, 138, 5, 0x0050, 0x10, 8, 2),
PIN_FIELD_BASE(139, 139, 5, 0x0050, 0x10, 10, 2),
PIN_FIELD_BASE(140, 140, 5, 0x0050, 0x10, 0, 2),
PIN_FIELD_BASE(141, 141, 5, 0x0050, 0x10, 12, 2),
PIN_FIELD_BASE(142, 142, 5, 0x0050, 0x10, 4, 2),
PIN_FIELD_BASE(143, 143, 5, 0x0050, 0x10, 6, 2),
PINS_FIELD_BASE(144, 147, 5, 0x0050, 0x10, 20, 2),
PINS_FIELD_BASE(148, 149, 5, 0x0050, 0x10, 24, 2),
PINS_FIELD_BASE(150, 151, 7, 0x00a0, 0x10, 18, 2),
PINS_FIELD_BASE(152, 153, 7, 0x00a0, 0x10, 20, 2),
PIN_FIELD_BASE(154, 154, 7, 0x00a0, 0x10, 22, 2),
PINS_FIELD_BASE(155, 158, 3, 0x0060, 0x10, 22, 2),
PIN_FIELD_BASE(159, 159, 7, 0x00a0, 0x10, 22, 2),
PIN_FIELD_BASE(160, 160, 5, 0x0050, 0x10, 16, 2),
PINS_FIELD_BASE(161, 162, 1, 0x0060, 0x10, 30, 2),
PINS_FIELD_BASE(163, 170, 4, 0x0070, 0x10, 0, 2),
PINS_FIELD_BASE(171, 179, 7, 0x00a0, 0x10, 10, 2),
};
static const struct mtk_pin_field_calc mt6765_pin_drv_range[] = {
PINS_FIELD_BASE(0, 2, 2, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(3, 3, 2, 0x0000, 0x10, 15, 3),
PINS_FIELD_BASE(4, 6, 2, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(7, 7, 2, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(8, 8, 3, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(9, 11, 2, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(12, 12, 5, 0x0000, 0x10, 27, 3),
PINS_FIELD_BASE(13, 15, 6, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 23, 3),
PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 26, 3),
PINS_FIELD_BASE(19, 20, 6, 0x0000, 0x10, 23, 3),
PINS_FIELD_BASE(21, 23, 6, 0x0000, 0x10, 29, 3),
PIN_FIELD_BASE(24, 24, 6, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(25, 27, 6, 0x0000, 0x10, 17, 3),
PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 20, 3),
PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(30, 30, 6, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(31, 34, 6, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(35, 36, 6, 0x0000, 0x10, 13, 2),
PIN_FIELD_BASE(37, 37, 6, 0x0000, 0x10, 15, 2),
PIN_FIELD_BASE(38, 38, 6, 0x0000, 0x10, 11, 2),
PINS_FIELD_BASE(39, 40, 6, 0x0000, 0x10, 9, 2),
PINS_FIELD_BASE(41, 42, 7, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(43, 43, 7, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(44, 44, 7, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(45, 45, 7, 0x0000, 0x10, 27, 3),
PINS_FIELD_BASE(46, 47, 7, 0x0000, 0x10, 24, 3),
PINS_FIELD_BASE(48, 49, 7, 0x0010, 0x10, 18, 3),
PINS_FIELD_BASE(50, 51, 7, 0x0010, 0x10, 15, 3),
PINS_FIELD_BASE(52, 57, 7, 0x0000, 0x10, 0, 3),
PINS_FIELD_BASE(58, 60, 7, 0x0010, 0x10, 9, 3),
PINS_FIELD_BASE(61, 62, 3, 0x0000, 0x10, 15, 3),
PINS_FIELD_BASE(63, 64, 3, 0x0000, 0x10, 12, 3),
PINS_FIELD_BASE(65, 66, 3, 0x0000, 0x10, 21, 3),
PINS_FIELD_BASE(67, 68, 3, 0x0000, 0x10, 18, 3),
PINS_FIELD_BASE(69, 73, 3, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(74, 78, 3, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(79, 80, 3, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(82, 83, 3, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(87, 87, 7, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(88, 88, 7, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(89, 89, 2, 0x0010, 0x10, 15, 3),
PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(93, 93, 2, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(95, 96, 2, 0x0010, 0x10, 18, 3),
PINS_FIELD_BASE(97, 98, 2, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(99, 99, 2, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(100, 100, 2, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(101, 102, 2, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 9, 3),
PINS_FIELD_BASE(105, 106, 2, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(107, 107, 1, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(108, 108, 1, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 27, 3),
PIN_FIELD_BASE(114, 114, 1, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 9, 3),
PIN_FIELD_BASE(119, 119, 1, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(120, 120, 1, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(121, 121, 1, 0x0000, 0x10, 24, 3),
PIN_FIELD_BASE(122, 122, 4, 0x0000, 0x10, 9, 3),
PIN_FIELD_BASE(123, 123, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(124, 124, 4, 0x0000, 0x10, 6, 3),
PINS_FIELD_BASE(125, 130, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(133, 133, 4, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(134, 134, 5, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(135, 135, 5, 0x0010, 0x10, 12, 3),
PIN_FIELD_BASE(136, 136, 5, 0x0000, 0x10, 3, 3),
PIN_FIELD_BASE(137, 137, 5, 0x0000, 0x10, 21, 3),
PIN_FIELD_BASE(138, 138, 5, 0x0000, 0x10, 12, 3),
PIN_FIELD_BASE(139, 139, 5, 0x0000, 0x10, 15, 3),
PIN_FIELD_BASE(140, 140, 5, 0x0000, 0x10, 0, 3),
PIN_FIELD_BASE(141, 141, 5, 0x0000, 0x10, 18, 3),
PIN_FIELD_BASE(142, 142, 5, 0x0000, 0x10, 6, 3),
PIN_FIELD_BASE(143, 143, 5, 0x0000, 0x10, 9, 3),
PINS_FIELD_BASE(144, 146, 5, 0x0010, 0x10, 0, 3),
PIN_FIELD_BASE(147, 147, 5, 0x0010, 0x10, 3, 3),
PINS_FIELD_BASE(148, 149, 5, 0x0010, 0x10, 9, 3),
PINS_FIELD_BASE(150, 151, 7, 0x0010, 0x10, 0, 3),
PINS_FIELD_BASE(152, 153, 7, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 6, 3),
PINS_FIELD_BASE(155, 157, 3, 0x0010, 0x10, 3, 3),
PIN_FIELD_BASE(158, 158, 3, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(159, 159, 7, 0x0010, 0x10, 6, 3),
PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 24, 3),
PINS_FIELD_BASE(161, 162, 1, 0x0010, 0x10, 15, 3),
PINS_FIELD_BASE(163, 166, 4, 0x0000, 0x10, 0, 3),
PINS_FIELD_BASE(167, 170, 4, 0x0000, 0x10, 3, 3),
PINS_FIELD_BASE(171, 174, 7, 0x0000, 0x10, 18, 3),
PINS_FIELD_BASE(175, 179, 7, 0x0000, 0x10, 15, 3),
};
static const struct mtk_pin_field_calc mt6765_pin_pupd_range[] = {
PINS_FIELD_BASE(0, 28, 0, 0x0050, 0x10, 18, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 6, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(39, 39, 6, 0x0050, 0x10, 8, 1),
PINS_FIELD_BASE(40, 90, 6, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0050, 0x10, 0, 1),
PINS_FIELD_BASE(94, 121, 2, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(126, 126, 4, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(127, 127, 4, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 4, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(129, 129, 4, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 4, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(131, 131, 4, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 4, 0x0030, 0x10, 5, 1),
PINS_FIELD_BASE(133, 179, 4, 0x0030, 0x10, 11, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_r0_range[] = {
PINS_FIELD_BASE(0, 28, 4, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 6, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(39, 39, 6, 0x0070, 0x10, 8, 1),
PINS_FIELD_BASE(40, 90, 6, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 0, 1),
PINS_FIELD_BASE(94, 121, 2, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(126, 126, 4, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(127, 127, 4, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 4, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(129, 129, 4, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 4, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(131, 131, 4, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 4, 0x0050, 0x10, 5, 1),
PINS_FIELD_BASE(133, 179, 4, 0x0050, 0x10, 11, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_r1_range[] = {
PINS_FIELD_BASE(0, 28, 4, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 6, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(39, 39, 6, 0x0080, 0x10, 8, 1),
PINS_FIELD_BASE(40, 90, 6, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 0, 1),
PINS_FIELD_BASE(94, 121, 2, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(126, 126, 4, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(127, 127, 4, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(128, 128, 4, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(129, 129, 4, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 5, 1),
PINS_FIELD_BASE(133, 179, 4, 0x0060, 0x10, 11, 1),
};
static const struct mtk_pin_field_calc mt6765_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 2, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(1, 1, 2, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(2, 2, 2, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(3, 3, 2, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(4, 4, 2, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(5, 5, 2, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(6, 6, 2, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(7, 7, 2, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(8, 8, 3, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(12, 12, 5, 0x0020, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 26, 1),
PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 25, 1),
PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 27, 1),
PIN_FIELD_BASE(16, 16, 6, 0x0020, 0x10, 24, 1),
PIN_FIELD_BASE(17, 17, 6, 0x0020, 0x10, 19, 1),
PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 16, 1),
PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 18, 1),
PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 17, 1),
PIN_FIELD_BASE(21, 21, 6, 0x0020, 0x10, 22, 1),
PIN_FIELD_BASE(22, 22, 6, 0x0020, 0x10, 21, 1),
PIN_FIELD_BASE(23, 23, 6, 0x0020, 0x10, 23, 1),
PIN_FIELD_BASE(24, 24, 6, 0x0020, 0x10, 20, 1),
PIN_FIELD_BASE(25, 25, 6, 0x0020, 0x10, 14, 1),
PIN_FIELD_BASE(26, 26, 6, 0x0020, 0x10, 13, 1),
PIN_FIELD_BASE(27, 27, 6, 0x0020, 0x10, 15, 1),
PIN_FIELD_BASE(28, 28, 6, 0x0020, 0x10, 12, 1),
PIN_FIELD_BASE(29, 29, 6, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 6, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(31, 31, 6, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(32, 32, 6, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(33, 33, 6, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 6, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(35, 35, 6, 0x0020, 0x10, 10, 1),
PIN_FIELD_BASE(36, 36, 6, 0x0020, 0x10, 11, 1),
PIN_FIELD_BASE(37, 37, 6, 0x0020, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 6, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(39, 39, 6, 0x0020, 0x10, 8, 1),
PIN_FIELD_BASE(40, 40, 6, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(41, 41, 7, 0x0040, 0x10, 19, 1),
PIN_FIELD_BASE(42, 42, 7, 0x0040, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x0040, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 7, 0x0040, 0x10, 10, 1),
PIN_FIELD_BASE(45, 45, 7, 0x0040, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 7, 0x0040, 0x10, 21, 1),
PIN_FIELD_BASE(47, 47, 7, 0x0040, 0x10, 20, 1),
PIN_FIELD_BASE(48, 48, 7, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 7, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(50, 50, 7, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(51, 51, 7, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(52, 52, 7, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(53, 53, 7, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(54, 54, 7, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(55, 55, 7, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(56, 56, 7, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(57, 57, 7, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(58, 58, 7, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(59, 59, 7, 0x0040, 0x10, 31, 1),
PIN_FIELD_BASE(60, 60, 7, 0x0040, 0x10, 30, 1),
PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 18, 1),
PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 20, 1),
PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 25, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 24, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 22, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 23, 1),
PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(86, 86, 7, 0x0040, 0x10, 29, 1),
PIN_FIELD_BASE(87, 87, 7, 0x0040, 0x10, 7, 1),
PIN_FIELD_BASE(88, 88, 7, 0x0040, 0x10, 6, 1),
PIN_FIELD_BASE(89, 89, 2, 0x0030, 0x10, 25, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0030, 0x10, 21, 1),
PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 20, 1),
PIN_FIELD_BASE(92, 92, 2, 0x0030, 0x10, 19, 1),
PIN_FIELD_BASE(93, 93, 2, 0x0030, 0x10, 17, 1),
PIN_FIELD_BASE(94, 94, 2, 0x0030, 0x10, 18, 1),
PIN_FIELD_BASE(95, 95, 2, 0x0030, 0x10, 26, 1),
PIN_FIELD_BASE(96, 96, 2, 0x0030, 0x10, 27, 1),
PIN_FIELD_BASE(97, 97, 2, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(99, 99, 2, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(101, 101, 2, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(102, 102, 2, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(103, 103, 2, 0x0030, 0x10, 21, 1),
PIN_FIELD_BASE(104, 104, 2, 0x0030, 0x10, 23, 1),
PIN_FIELD_BASE(105, 105, 2, 0x0030, 0x10, 22, 1),
PIN_FIELD_BASE(106, 106, 2, 0x0030, 0x10, 24, 1),
PIN_FIELD_BASE(107, 107, 1, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(108, 108, 1, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(109, 109, 1, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(110, 110, 1, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 1, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(112, 112, 1, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 1, 0x0030, 0x10, 9, 1),
PIN_FIELD_BASE(114, 114, 1, 0x0030, 0x10, 10, 1),
PIN_FIELD_BASE(115, 115, 1, 0x0030, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 1, 0x0030, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 1, 0x0030, 0x10, 12, 1),
PIN_FIELD_BASE(118, 118, 1, 0x0030, 0x10, 13, 1),
PIN_FIELD_BASE(119, 119, 1, 0x0030, 0x10, 14, 1),
PIN_FIELD_BASE(120, 120, 1, 0x0030, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 1, 0x0030, 0x10, 8, 1),
PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 1),
PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 10, 1),
PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 8, 1),
PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 12, 1),
PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 14, 1),
PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 16, 1),
PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 11, 1),
PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 15, 1),
PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 17, 1),
PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 18, 1),
PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 13, 1),
PIN_FIELD_BASE(133, 133, 4, 0x0010, 0x10, 19, 1),
PIN_FIELD_BASE(134, 134, 5, 0x0020, 0x10, 14, 1),
PIN_FIELD_BASE(135, 135, 5, 0x0020, 0x10, 17, 1),
PIN_FIELD_BASE(136, 136, 5, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(137, 137, 5, 0x0020, 0x10, 7, 1),
PIN_FIELD_BASE(138, 138, 5, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(139, 139, 5, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(140, 140, 5, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(141, 141, 5, 0x0020, 0x10, 6, 1),
PIN_FIELD_BASE(142, 142, 5, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 12, 1),
PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 11, 1),
PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 13, 1),
PIN_FIELD_BASE(147, 147, 5, 0x0020, 0x10, 10, 1),
PIN_FIELD_BASE(148, 148, 5, 0x0020, 0x10, 15, 1),
PIN_FIELD_BASE(149, 149, 5, 0x0020, 0x10, 16, 1),
PIN_FIELD_BASE(150, 150, 7, 0x0040, 0x10, 23, 1),
PIN_FIELD_BASE(151, 151, 7, 0x0040, 0x10, 24, 1),
PIN_FIELD_BASE(152, 152, 7, 0x0040, 0x10, 25, 1),
PIN_FIELD_BASE(153, 153, 7, 0x0040, 0x10, 26, 1),
PIN_FIELD_BASE(154, 154, 7, 0x0040, 0x10, 28, 1),
PIN_FIELD_BASE(155, 155, 3, 0x0030, 0x10, 28, 1),
PIN_FIELD_BASE(156, 156, 3, 0x0030, 0x10, 27, 1),
PIN_FIELD_BASE(157, 157, 3, 0x0030, 0x10, 29, 1),
PIN_FIELD_BASE(158, 158, 3, 0x0030, 0x10, 26, 1),
PIN_FIELD_BASE(159, 159, 7, 0x0040, 0x10, 27, 1),
PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 8, 1),
PIN_FIELD_BASE(161, 161, 1, 0x0030, 0x10, 15, 1),
PIN_FIELD_BASE(162, 162, 1, 0x0030, 0x10, 16, 1),
PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 0, 1),
PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 1, 1),
PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 2, 1),
PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 1),
PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 4, 1),
PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 5, 1),
PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 6, 1),
PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 7, 1),
PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 17, 1),
PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 18, 1),
PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 11, 1),
PIN_FIELD_BASE(174, 174, 7, 0x0040, 0x10, 12, 1),
PIN_FIELD_BASE(175, 175, 7, 0x0040, 0x10, 13, 1),
PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 14, 1),
PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 15, 1),
PINS_FIELD_BASE(178, 179, 7, 0x0040, 0x10, 16, 1),
};
static const struct mtk_pin_reg_calc mt6765_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6765_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6765_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6765_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6765_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6765_pin_smt_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6765_pin_pd_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6765_pin_pu_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6765_pin_tdsel_range),
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6765_pin_rdsel_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6765_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6765_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6765_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6765_pin_r1_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6765_pin_ies_range),
};
static const char * const mt6765_pinctrl_register_base_names[] = {
"iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7",
};
static const struct mtk_eint_hw mt6765_eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 160,
.db_cnt = 13,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt6765_data = {
.reg_cal = mt6765_reg_cals,
.pins = mtk_pins_mt6765,
.npins = ARRAY_SIZE(mtk_pins_mt6765),
.ngrps = ARRAY_SIZE(mtk_pins_mt6765),
.eint_hw = &mt6765_eint_hw,
.gpio_m = 0,
.base_names = mt6765_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_raw,
.drive_get = mtk_pinconf_drive_get_raw,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
};
static const struct of_device_id mt6765_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data },
{ }
};
static struct platform_driver mt6765_pinctrl_driver = {
.driver = {
.name = "mt6765-pinctrl",
.of_match_table = mt6765_pinctrl_of_match,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt6765_pinctrl_init(void)
{
return platform_driver_register(&mt6765_pinctrl_driver);
}
arch_initcall(mt6765_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT6765 Pinctrl Driver");
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt6765.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Zhiyong Tao <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt2712.h"
static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
};
static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
};
static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
};
static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
};
static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
.pins = mtk_pins_mt2712,
.npins = ARRAY_SIZE(mtk_pins_mt2712),
.grp_desc = mt2712_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
.pin_drv_grp = mt2712_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
.spec_ies = mt2712_ies_set,
.n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
.spec_pupd = mt2712_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
.spec_smt = mt2712_smt_set,
.n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
.dout_offset = 0x0300,
.din_offset = 0x0400,
.pinmux_offset = 0x0500,
.type1_start = 210,
.type1_end = 210,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 0xf,
.ports = 8,
.ap_num = 229,
.db_cnt = 40,
.db_time = debounce_time_mt2701,
},
};
static const struct of_device_id mt2712_pctrl_match[] = {
{ .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data },
{ }
};
MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt2712-pinctrl",
.of_match_table = mt2712_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt2712.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: Zhiyong Tao <[email protected]>
*
*/
#include "pinctrl-mtk-mt8183.h"
#include "pinctrl-paris.h"
/* MT8183 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
* iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
* iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 0)
#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
_x_bits, 32, 1)
static const struct mtk_pin_field_calc mt8183_pin_mode_range[] = {
PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8183_pin_dir_range[] = {
PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_di_range[] = {
PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_do_range[] = {
PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_ies_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1),
PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1),
PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(31, 31, 2, 0x000, 0x10, 8, 1),
PINS_FIELD_BASE(32, 34, 2, 0x000, 0x10, 7, 1),
PINS_FIELD_BASE(35, 37, 3, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(38, 40, 3, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(41, 42, 3, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(43, 45, 3, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(46, 47, 3, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(48, 49, 3, 0x000, 0x10, 5, 1),
PINS_FIELD_BASE(50, 51, 4, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(52, 57, 4, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(58, 60, 4, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(61, 64, 5, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(65, 66, 5, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(67, 68, 5, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(69, 71, 5, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(72, 76, 5, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(77, 80, 5, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(82, 83, 5, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(84, 84, 5, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(85, 88, 5, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(89, 89, 6, 0x000, 0x10, 11, 1),
PIN_FIELD_BASE(90, 90, 6, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(91, 94, 6, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(95, 96, 6, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(97, 98, 6, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(99, 99, 6, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(100, 100, 6, 0x000, 0x10, 9, 1),
PINS_FIELD_BASE(101, 102, 6, 0x000, 0x10, 10, 1),
PINS_FIELD_BASE(103, 104, 6, 0x000, 0x10, 13, 1),
PINS_FIELD_BASE(105, 106, 6, 0x000, 0x10, 14, 1),
PIN_FIELD_BASE(107, 107, 7, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(108, 108, 7, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(109, 109, 7, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(110, 110, 7, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 7, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(112, 112, 7, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 7, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(114, 114, 7, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(115, 115, 7, 0x000, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 7, 0x000, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 7, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 7, 0x000, 0x10, 9, 1),
PIN_FIELD_BASE(119, 119, 7, 0x000, 0x10, 10, 1),
PIN_FIELD_BASE(120, 120, 7, 0x000, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 7, 0x000, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(124, 124, 8, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(125, 130, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x000, 0x10, 3, 1),
PIN_FIELD_BASE(132, 132, 8, 0x000, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 8, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(134, 134, 1, 0x000, 0x10, 0, 1),
PIN_FIELD_BASE(135, 135, 1, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(136, 143, 1, 0x000, 0x10, 2, 1),
PINS_FIELD_BASE(144, 147, 1, 0x000, 0x10, 4, 1),
PIN_FIELD_BASE(148, 148, 1, 0x000, 0x10, 5, 1),
PIN_FIELD_BASE(149, 149, 1, 0x000, 0x10, 6, 1),
PINS_FIELD_BASE(150, 153, 1, 0x000, 0x10, 8, 1),
PIN_FIELD_BASE(154, 154, 1, 0x000, 0x10, 9, 1),
PINS_FIELD_BASE(155, 157, 1, 0x000, 0x10, 10, 1),
PINS_FIELD_BASE(158, 160, 1, 0x000, 0x10, 8, 1),
PINS_FIELD_BASE(161, 164, 2, 0x000, 0x10, 0, 1),
PINS_FIELD_BASE(165, 166, 2, 0x000, 0x10, 1, 1),
PINS_FIELD_BASE(167, 168, 4, 0x000, 0x10, 2, 1),
PIN_FIELD_BASE(169, 169, 4, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(170, 174, 4, 0x000, 0x10, 4, 1),
PINS_FIELD_BASE(175, 176, 4, 0x000, 0x10, 3, 1),
PINS_FIELD_BASE(177, 179, 6, 0x000, 0x10, 4, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_smt_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(4, 7, 6, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(8, 8, 6, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(9, 10, 6, 0x010, 0x10, 12, 1),
PIN_FIELD_BASE(11, 11, 1, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 1, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(13, 16, 2, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(17, 20, 2, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(21, 24, 2, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(25, 28, 2, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(29, 29, 2, 0x010, 0x10, 6, 1),
PIN_FIELD_BASE(30, 30, 2, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(31, 31, 2, 0x010, 0x10, 8, 1),
PINS_FIELD_BASE(32, 34, 2, 0x010, 0x10, 7, 1),
PINS_FIELD_BASE(35, 37, 3, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(38, 40, 3, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(41, 42, 3, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(43, 45, 3, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(46, 47, 3, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(48, 49, 3, 0x010, 0x10, 5, 1),
PINS_FIELD_BASE(50, 51, 4, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(52, 57, 4, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(58, 60, 4, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(61, 64, 5, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(65, 66, 5, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(67, 68, 5, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(69, 71, 5, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(72, 76, 5, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(77, 80, 5, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(82, 83, 5, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(84, 84, 5, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(85, 88, 5, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(89, 89, 6, 0x010, 0x10, 11, 1),
PIN_FIELD_BASE(90, 90, 6, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(91, 94, 6, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(95, 96, 6, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(97, 98, 6, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(99, 99, 6, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(100, 100, 6, 0x010, 0x10, 9, 1),
PINS_FIELD_BASE(101, 102, 6, 0x010, 0x10, 10, 1),
PINS_FIELD_BASE(103, 104, 6, 0x010, 0x10, 13, 1),
PINS_FIELD_BASE(105, 106, 6, 0x010, 0x10, 14, 1),
PIN_FIELD_BASE(107, 107, 7, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(108, 108, 7, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(109, 109, 7, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(110, 110, 7, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(111, 111, 7, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(112, 112, 7, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 7, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(114, 114, 7, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(115, 115, 7, 0x010, 0x10, 6, 1),
PIN_FIELD_BASE(116, 116, 7, 0x010, 0x10, 7, 1),
PIN_FIELD_BASE(117, 117, 7, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 7, 0x010, 0x10, 9, 1),
PIN_FIELD_BASE(119, 119, 7, 0x010, 0x10, 10, 1),
PIN_FIELD_BASE(120, 120, 7, 0x010, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 7, 0x010, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(124, 124, 8, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(125, 130, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(132, 132, 8, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 8, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(134, 134, 1, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(135, 135, 1, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(136, 143, 1, 0x010, 0x10, 2, 1),
PINS_FIELD_BASE(144, 147, 1, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(148, 148, 1, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(149, 149, 1, 0x010, 0x10, 6, 1),
PINS_FIELD_BASE(150, 153, 1, 0x010, 0x10, 8, 1),
PIN_FIELD_BASE(154, 154, 1, 0x010, 0x10, 9, 1),
PINS_FIELD_BASE(155, 157, 1, 0x010, 0x10, 10, 1),
PINS_FIELD_BASE(158, 160, 1, 0x010, 0x10, 8, 1),
PINS_FIELD_BASE(161, 164, 2, 0x010, 0x10, 0, 1),
PINS_FIELD_BASE(165, 166, 2, 0x010, 0x10, 1, 1),
PINS_FIELD_BASE(167, 168, 4, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(169, 169, 4, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(170, 174, 4, 0x010, 0x10, 4, 1),
PINS_FIELD_BASE(175, 176, 4, 0x010, 0x10, 3, 1),
PINS_FIELD_BASE(177, 179, 6, 0x010, 0x10, 4, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_pullen_range[] = {
PIN_FIELD_BASE(0, 3, 6, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(4, 7, 6, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(8, 8, 6, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(9, 10, 6, 0x060, 0x10, 26, 1),
PIN_FIELD_BASE(11, 11, 1, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 1, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(13, 28, 2, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(43, 49, 3, 0x060, 0x10, 8, 1),
PIN_FIELD_BASE(50, 60, 4, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(61, 88, 5, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(89, 89, 6, 0x060, 0x10, 24, 1),
PIN_FIELD_BASE(90, 90, 6, 0x060, 0x10, 1, 1),
PIN_FIELD_BASE(95, 95, 6, 0x060, 0x10, 15, 1),
PIN_FIELD_BASE(96, 102, 6, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(103, 106, 6, 0x060, 0x10, 28, 1),
PIN_FIELD_BASE(107, 121, 7, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(134, 143, 1, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(144, 149, 1, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(150, 160, 1, 0x060, 0x10, 18, 1),
PIN_FIELD_BASE(161, 166, 2, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(167, 176, 4, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(177, 177, 6, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(178, 178, 6, 0x060, 0x10, 16, 1),
PIN_FIELD_BASE(179, 179, 6, 0x060, 0x10, 25, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_pullsel_range[] = {
PIN_FIELD_BASE(0, 3, 6, 0x080, 0x10, 6, 1),
PIN_FIELD_BASE(4, 7, 6, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(8, 8, 6, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(9, 10, 6, 0x080, 0x10, 26, 1),
PIN_FIELD_BASE(11, 11, 1, 0x080, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 1, 0x080, 0x10, 17, 1),
PIN_FIELD_BASE(13, 28, 2, 0x080, 0x10, 6, 1),
PIN_FIELD_BASE(43, 49, 3, 0x080, 0x10, 8, 1),
PIN_FIELD_BASE(50, 60, 4, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(61, 88, 5, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(89, 89, 6, 0x080, 0x10, 24, 1),
PIN_FIELD_BASE(90, 90, 6, 0x080, 0x10, 1, 1),
PIN_FIELD_BASE(95, 95, 6, 0x080, 0x10, 15, 1),
PIN_FIELD_BASE(96, 102, 6, 0x080, 0x10, 17, 1),
PIN_FIELD_BASE(103, 106, 6, 0x080, 0x10, 28, 1),
PIN_FIELD_BASE(107, 121, 7, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(134, 143, 1, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(144, 149, 1, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(150, 160, 1, 0x080, 0x10, 18, 1),
PIN_FIELD_BASE(161, 166, 2, 0x080, 0x10, 0, 1),
PIN_FIELD_BASE(167, 176, 4, 0x080, 0x10, 11, 1),
PIN_FIELD_BASE(177, 177, 6, 0x080, 0x10, 10, 1),
PIN_FIELD_BASE(178, 178, 6, 0x080, 0x10, 16, 1),
PIN_FIELD_BASE(179, 179, 6, 0x080, 0x10, 25, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_drv_range[] = {
PINS_FIELD_BASE(0, 3, 6, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(4, 7, 6, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(8, 8, 6, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(9, 10, 6, 0x0B0, 0x10, 16, 3),
PIN_FIELD_BASE(11, 11, 1, 0x0A0, 0x10, 12, 3),
PIN_FIELD_BASE(12, 12, 1, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(13, 16, 2, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(17, 20, 2, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(21, 24, 2, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(25, 28, 2, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(29, 29, 2, 0x0A0, 0x10, 24, 3),
PIN_FIELD_BASE(30, 30, 2, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(31, 31, 2, 0x0B0, 0x10, 0, 3),
PINS_FIELD_BASE(32, 34, 2, 0x0A0, 0x10, 28, 3),
PINS_FIELD_BASE(35, 37, 3, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(38, 40, 3, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(41, 42, 3, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(43, 45, 3, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(46, 47, 3, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(48, 49, 3, 0x0A0, 0x10, 20, 3),
PINS_FIELD_BASE(50, 51, 4, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(52, 57, 4, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(58, 60, 4, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(61, 64, 5, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(65, 66, 5, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(67, 68, 5, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(69, 71, 5, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(72, 76, 5, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(77, 80, 5, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(81, 81, 5, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(82, 83, 5, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(84, 84, 5, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(85, 88, 5, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(89, 89, 6, 0x0B0, 0x10, 12, 3),
PIN_FIELD_BASE(90, 90, 6, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(91, 94, 6, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(95, 96, 6, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(97, 98, 6, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(99, 99, 6, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(100, 100, 6, 0x0B0, 0x10, 4, 3),
PINS_FIELD_BASE(101, 102, 6, 0x0B0, 0x10, 8, 3),
PINS_FIELD_BASE(103, 104, 6, 0x0B0, 0x10, 20, 3),
PINS_FIELD_BASE(105, 106, 6, 0x0B0, 0x10, 24, 3),
PIN_FIELD_BASE(107, 107, 7, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(108, 108, 7, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(109, 109, 7, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(110, 110, 7, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(111, 111, 7, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(112, 112, 7, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(113, 113, 7, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(114, 114, 7, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(115, 115, 7, 0x0A0, 0x10, 24, 3),
PIN_FIELD_BASE(116, 116, 7, 0x0A0, 0x10, 28, 3),
PIN_FIELD_BASE(117, 117, 7, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(118, 118, 7, 0x0B0, 0x10, 4, 3),
PIN_FIELD_BASE(119, 119, 7, 0x0B0, 0x10, 8, 3),
PIN_FIELD_BASE(120, 120, 7, 0x0B0, 0x10, 12, 3),
PIN_FIELD_BASE(121, 121, 7, 0x0B0, 0x10, 16, 3),
PIN_FIELD_BASE(122, 122, 8, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(123, 123, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(124, 124, 8, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(125, 130, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(131, 131, 8, 0x0A0, 0x10, 12, 3),
PIN_FIELD_BASE(132, 132, 8, 0x0A0, 0x10, 4, 3),
PIN_FIELD_BASE(133, 133, 8, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(134, 134, 1, 0x0A0, 0x10, 0, 3),
PIN_FIELD_BASE(135, 135, 1, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(136, 143, 1, 0x0A0, 0x10, 8, 3),
PINS_FIELD_BASE(144, 147, 1, 0x0A0, 0x10, 16, 3),
PIN_FIELD_BASE(148, 148, 1, 0x0A0, 0x10, 20, 3),
PIN_FIELD_BASE(149, 149, 1, 0x0A0, 0x10, 24, 3),
PINS_FIELD_BASE(150, 153, 1, 0x0B0, 0x10, 0, 3),
PIN_FIELD_BASE(154, 154, 1, 0x0B0, 0x10, 4, 3),
PINS_FIELD_BASE(155, 157, 1, 0x0B0, 0x10, 8, 3),
PINS_FIELD_BASE(158, 160, 1, 0x0B0, 0x10, 0, 3),
PINS_FIELD_BASE(161, 164, 2, 0x0A0, 0x10, 0, 3),
PINS_FIELD_BASE(165, 166, 2, 0x0A0, 0x10, 4, 3),
PINS_FIELD_BASE(167, 168, 4, 0x0A0, 0x10, 8, 3),
PIN_FIELD_BASE(169, 169, 4, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(170, 174, 4, 0x0A0, 0x10, 16, 3),
PINS_FIELD_BASE(175, 176, 4, 0x0A0, 0x10, 12, 3),
PINS_FIELD_BASE(177, 179, 6, 0x0A0, 0x10, 16, 3),
};
static const struct mtk_pin_field_calc mt8183_pin_pupd_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 26, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 30, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 2, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 6, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 10, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 14, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 18, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 22, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 26, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 30, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 2, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 6, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 10, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 14, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_r0_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 24, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 28, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 18, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 5, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 7, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 5, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 17, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 4, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 8, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 12, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 16, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 20, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 24, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 28, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 0, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 4, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 8, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 12, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 25, 1),
PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 29, 1),
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 6, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 8, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 6, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 18, 1),
PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 1, 1),
PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 9, 1),
PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 13, 1),
PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 17, 1),
PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 21, 1),
PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 25, 1),
PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 29, 1),
PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 1, 1),
PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 5, 1),
PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 9, 1),
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1),
};
static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8183_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8183_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8183_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8183_pin_ies_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8183_pin_pullen_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8183_pin_pullsel_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8183_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
[PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range),
[PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range),
[PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range),
};
static const char * const mt8183_pinctrl_register_base_names[] = {
"iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
};
static const struct mtk_eint_hw mt8183_eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 212,
.db_cnt = 13,
.db_time = debounce_time_mt6765,
};
static const struct mtk_pin_soc mt8183_data = {
.reg_cal = mt8183_reg_cals,
.pins = mtk_pins_mt8183,
.npins = ARRAY_SIZE(mtk_pins_mt8183),
.ngrps = ARRAY_SIZE(mtk_pins_mt8183),
.eint_hw = &mt8183_eint_hw,
.gpio_m = 0,
.base_names = mt8183_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8183_pinctrl_register_base_names),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
.adv_drive_get = mtk_pinconf_adv_drive_get,
.adv_drive_set = mtk_pinconf_adv_drive_set,
};
static const struct of_device_id mt8183_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data },
{ }
};
static struct platform_driver mt8183_pinctrl_driver = {
.driver = {
.name = "mt8183-pinctrl",
.of_match_table = mt8183_pinctrl_of_match,
.pm = &mtk_paris_pinctrl_pm_ops,
},
.probe = mtk_paris_pinctrl_probe,
};
static int __init mt8183_pinctrl_init(void)
{
return platform_driver_register(&mt8183_pinctrl_driver);
}
arch_initcall(mt8183_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt8183.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define MT7621_GPIO_MODE_UART1 1
#define MT7621_GPIO_MODE_I2C 2
#define MT7621_GPIO_MODE_UART3_MASK 0x3
#define MT7621_GPIO_MODE_UART3_SHIFT 3
#define MT7621_GPIO_MODE_UART3_GPIO 1
#define MT7621_GPIO_MODE_UART2_MASK 0x3
#define MT7621_GPIO_MODE_UART2_SHIFT 5
#define MT7621_GPIO_MODE_UART2_GPIO 1
#define MT7621_GPIO_MODE_JTAG 7
#define MT7621_GPIO_MODE_WDT_MASK 0x3
#define MT7621_GPIO_MODE_WDT_SHIFT 8
#define MT7621_GPIO_MODE_WDT_GPIO 1
#define MT7621_GPIO_MODE_PCIE_RST 0
#define MT7621_GPIO_MODE_PCIE_REF 2
#define MT7621_GPIO_MODE_PCIE_MASK 0x3
#define MT7621_GPIO_MODE_PCIE_SHIFT 10
#define MT7621_GPIO_MODE_PCIE_GPIO 1
#define MT7621_GPIO_MODE_MDIO_MASK 0x3
#define MT7621_GPIO_MODE_MDIO_SHIFT 12
#define MT7621_GPIO_MODE_MDIO_GPIO 1
#define MT7621_GPIO_MODE_RGMII1 14
#define MT7621_GPIO_MODE_RGMII2 15
#define MT7621_GPIO_MODE_SPI_MASK 0x3
#define MT7621_GPIO_MODE_SPI_SHIFT 16
#define MT7621_GPIO_MODE_SPI_GPIO 1
#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
static struct mtmips_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
static struct mtmips_pmx_func uart3_grp[] = {
FUNC("uart3", 0, 5, 4),
FUNC("i2s", 2, 5, 4),
FUNC("spdif3", 3, 5, 4),
};
static struct mtmips_pmx_func uart2_grp[] = {
FUNC("uart2", 0, 9, 4),
FUNC("pcm", 2, 9, 4),
FUNC("spdif2", 3, 9, 4),
};
static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
static struct mtmips_pmx_func wdt_grp[] = {
FUNC("wdt rst", 0, 18, 1),
FUNC("wdt refclk", 2, 18, 1),
};
static struct mtmips_pmx_func pcie_rst_grp[] = {
FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
};
static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
static struct mtmips_pmx_func spi_grp[] = {
FUNC("spi", 0, 34, 7),
FUNC("nand1", 2, 34, 7),
};
static struct mtmips_pmx_func sdhci_grp[] = {
FUNC("sdhci", 0, 41, 8),
FUNC("nand2", 2, 41, 8),
};
static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
static struct mtmips_pmx_group mt7621_pinmux_data[] = {
GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
{ 0 }
};
static int mt7621_pinctrl_probe(struct platform_device *pdev)
{
return mtmips_pinctrl_init(pdev, mt7621_pinmux_data);
}
static const struct of_device_id mt7621_pinctrl_match[] = {
{ .compatible = "ralink,mt7621-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match);
static struct platform_driver mt7621_pinctrl_driver = {
.probe = mt7621_pinctrl_probe,
.driver = {
.name = "mt7621-pinctrl",
.of_match_table = mt7621_pinctrl_match,
},
};
static int __init mt7621_pinctrl_init(void)
{
return platform_driver_register(&mt7621_pinctrl_driver);
}
core_initcall_sync(mt7621_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-mt7621.c
|
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "pinctrl-mtmips.h"
#define RT2880_GPIO_MODE_I2C BIT(0)
#define RT2880_GPIO_MODE_UART0 BIT(1)
#define RT2880_GPIO_MODE_SPI BIT(2)
#define RT2880_GPIO_MODE_UART1 BIT(3)
#define RT2880_GPIO_MODE_JTAG BIT(4)
#define RT2880_GPIO_MODE_MDIO BIT(5)
#define RT2880_GPIO_MODE_SDRAM BIT(6)
#define RT2880_GPIO_MODE_PCI BIT(7)
static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) };
static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) };
static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) };
static struct mtmips_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) };
static struct mtmips_pmx_group rt2880_pinmux_data_act[] = {
GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C),
GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI),
GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0),
GRP("jtag", jtag_grp, 1, RT2880_GPIO_MODE_JTAG),
GRP("mdio", mdio_grp, 1, RT2880_GPIO_MODE_MDIO),
GRP("sdram", sdram_grp, 1, RT2880_GPIO_MODE_SDRAM),
GRP("pci", pci_grp, 1, RT2880_GPIO_MODE_PCI),
{ 0 }
};
static int rt2880_pinctrl_probe(struct platform_device *pdev)
{
return mtmips_pinctrl_init(pdev, rt2880_pinmux_data_act);
}
static const struct of_device_id rt2880_pinctrl_match[] = {
{ .compatible = "ralink,rt2880-pinctrl" },
{ .compatible = "ralink,rt2880-pinmux" },
{}
};
MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match);
static struct platform_driver rt2880_pinctrl_driver = {
.probe = rt2880_pinctrl_probe,
.driver = {
.name = "rt2880-pinctrl",
.of_match_table = rt2880_pinctrl_match,
},
};
static int __init rt2880_pinctrl_init(void)
{
return platform_driver_register(&rt2880_pinctrl_driver);
}
core_initcall_sync(rt2880_pinctrl_init);
|
linux-master
|
drivers/pinctrl/mediatek/pinctrl-rt2880.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* SP7021 Pin Controller Driver.
* Copyright (C) Sunplus Tech / Tibbo Tech.
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/overflow.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/sppctl-sp7021.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "sppctl.h"
struct sppctl_gpio_chip {
void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
void __iomem *first_base; /* GPIO_FIRST */
struct gpio_chip chip;
spinlock_t lock; /* lock for accessing OE register */
};
static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
}
static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
}
static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
}
static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
}
static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
}
static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
}
static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off);
}
static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off);
}
static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
}
static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
}
static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
}
static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
}
static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
}
static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
}
static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
{
u32 bit_off;
/* Each register has 32 bits. */
*reg_off = (offset / 32) * 4;
bit_off = offset % 32;
return bit_off;
}
static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
{
u32 bit_off;
/*
* Each MOON register has 32 bits. Upper 16-bit word are mask-fields.
* The lower 16-bit word are the control-fields. The corresponding
* bits in mask-field should be set then you can write something to
* control-field.
*/
*reg_off = (offset / 16) * 4;
bit_off = offset % 16;
return bit_off;
}
static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val)
{
u32 bit_off;
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off);
if (val)
return SPPCTL_SET_MOON_REG_BIT(bit_off);
else
return SPPCTL_CLR_MOON_REG_BIT(bit_off);
}
/**
* sppctl_func_set() - Set pin of fully-pinmux function.
*
* Mask-fields and control-fields of fully-pinmux function of SP7021 are
* arranged as shown below:
*
* func# | register | mask-field | control-field
* -------+----------+--------------+---------------
* 0 | base[0] | (22 : 16) | ( 6 : 0)
* 1 | base[0] | (30 : 24) | (14 : 8)
* 2 | base[1] | (22 : 16) | ( 6 : 0)
* 3 | baeg[1] | (30 : 24) | (14 : 8)
* : | : | : | :
*
* where mask-fields are used to protect control-fields from write-in
* accidentally. Set the corresponding bits in the mask-field before
* you write a value into a control-field.
*
* Control-fields are used to set where the function pin is going to
* be routed to.
*
* Note that mask-fields and control-fields of even number of 'func'
* are located at bits (22:16) and (6:0), while odd number of 'func's
* are located at bits (30:24) and (14:8).
*/
static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val)
{
u32 reg, offset;
/*
* Note that upper 16-bit word are mask-fields and lower 16-bit
* word are the control-fields. Set corresponding bits in mask-
* field before write to a control-field.
*/
reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val;
/*
* MUXF_L2SW_CLK_OUT is the first fully-pinmux pin
* and its register offset is 0.
*/
func -= MUXF_L2SW_CLK_OUT;
/*
* Check if 'func' is an odd number or not. Mask and control-
* fields of odd number 'func' is located at upper portion of
* a register. Extra shift is needed.
*/
if (func & BIT(0))
reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT;
/* Convert func# to register offset w.r.t. base register. */
offset = func * 2;
offset &= GENMASK(31, 2);
writel(reg, pctl->moon2_base + offset);
}
/**
* sppctl_gmx_set() - Set pin of group-pinmux.
*
* Mask-fields and control-fields of group-pinmux function of SP7021 are
* arranged as shown below:
*
* register | mask-fields | control-fields
* ----------+--------------+----------------
* base[0] | (31 : 16) | (15 : 0)
* base[1] | (31 : 24) | (15 : 0)
* base[2] | (31 : 24) | (15 : 0)
* : | : | :
*
* where mask-fields are used to protect control-fields from write-in
* accidentally. Set the corresponding bits in the mask-field before
* you write a value into a control-field.
*
* Control-fields are used to set where the function pin is going to
* be routed to. A control-field consists of one or more bits.
*/
static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz,
u8 val)
{
u32 mask, reg;
/*
* Note that upper 16-bit word are mask-fields and lower 16-bit
* word are the control-fields. Set corresponding bits in mask-
* field before write to a control-field.
*/
mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT;
reg = (mask | val) << bit_off;
writel(reg, pctl->moon1_base + reg_off * 4);
}
/**
* sppctl_first_get() - get bit of FIRST register.
*
* There are 4 FIRST registers. Each has 32 control-bits.
* Totally, there are 4 * 32 = 128 control-bits.
* Control-bits are arranged as shown below:
*
* registers | control-bits
* -----------+--------------
* first[0] | (31 : 0)
* first[1] | (63 : 32)
* first[2] | (95 : 64)
* first[3] | (127 : 96)
*
* Each control-bit sets type of a GPIO pin.
* 0: a fully-pinmux pin
* 1: a GPIO or IOP pin
*/
static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
reg = sppctl_first_readl(spp_gchip, reg_off);
return (reg & BIT(bit_off)) ? 1 : 0;
}
/**
* sppctl_master_get() - get bit of MASTER register.
*
* There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits.
* Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are
* control-bits. Totally, there are 128 mask-bits and 128 control-bits.
* They are arranged as shown below:
*
* register | mask-bits | control-bits
* -----------+-------------+--------------
* master[0] | (15 : 0) | (15 : 0)
* master[1] | (31 : 16) | (31 : 16)
* master[2] | (47 : 32) | (47 : 32)
* : | : | :
* master[7] | (127 : 112) | (127 : 112)
*
* where mask-bits are used to protect control-bits from write-in
* accidentally. Set the corresponding mask-bit before you write
* a value into a control-bit.
*
* Each control-bit sets type of a GPIO pin when FIRST bit is 1.
* 0: a IOP pin
* 1: a GPIO pin
*/
static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
reg = sppctl_gpio_master_readl(spp_gchip, reg_off);
return (reg & BIT(bit_off)) ? 1 : 0;
}
static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset,
enum mux_first_reg first, enum mux_master_reg master)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
enum mux_first_reg val;
/* FIRST register */
if (first != mux_f_keep) {
bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
reg = sppctl_first_readl(spp_gchip, reg_off);
val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux;
if (first != val)
switch (first) {
case mux_f_gpio:
reg |= BIT(bit_off);
sppctl_first_writel(spp_gchip, reg, reg_off);
break;
case mux_f_mux:
reg &= ~BIT(bit_off);
sppctl_first_writel(spp_gchip, reg, reg_off);
break;
case mux_f_keep:
break;
}
}
/* MASTER register */
if (master != mux_m_keep) {
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio));
sppctl_gpio_master_writel(spp_gchip, reg, reg_off);
}
}
static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off);
}
static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off);
}
static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
reg = sppctl_gpio_od_readl(spp_gchip, reg_off);
return (reg & BIT(bit_off)) ? 1 : 0;
}
static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset,
unsigned int val)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
}
static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
reg = sppctl_gpio_oe_readl(spp_gchip, reg_off);
return (reg & BIT(bit_off)) ? 0 : 1;
}
static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
unsigned long flags;
bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
spin_lock_irqsave(&spp_gchip->lock, flags);
if (sppctl_gpio_get_direction(chip, offset))
reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off);
else
reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off);
spin_unlock_irqrestore(&spp_gchip->lock, flags);
return (reg & BIT(bit_off)) ? 1 : 0;
}
static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
unsigned long flags;
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0);
spin_lock_irqsave(&spp_gchip->lock, flags);
sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
spin_unlock_irqrestore(&spp_gchip->lock, flags);
return 0;
}
static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
unsigned long flags;
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
spin_lock_irqsave(&spp_gchip->lock, flags);
sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
if (val < 0) {
spin_unlock_irqrestore(&spp_gchip->lock, flags);
return 0;
}
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
spin_unlock_irqrestore(&spp_gchip->lock, flags);
return 0;
}
static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, bit_off, reg;
bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
reg = sppctl_gpio_in_readl(spp_gchip, reg_off);
return (reg & BIT(bit_off)) ? 1 : 0;
}
static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
}
static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
switch (param) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
break;
case PIN_CONFIG_INPUT_ENABLE:
break;
case PIN_CONFIG_OUTPUT:
return sppctl_gpio_direction_output(chip, offset, 0);
case PIN_CONFIG_PERSIST_STATE:
return -ENOTSUPP;
default:
return -EINVAL;
}
return 0;
}
static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
const char *label;
int i;
for (i = 0; i < chip->ngpio; i++) {
label = gpiochip_is_requested(chip, i);
if (!label)
label = "";
seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base,
chip->names[i], label);
seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O');
seq_printf(s, ":%d", sppctl_gpio_get(chip, i));
seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux");
seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop");
seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " ");
seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : "");
seq_puts(s, "\n");
}
}
static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl)
{
struct sppctl_gpio_chip *spp_gchip;
struct gpio_chip *gchip;
int err;
spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL);
if (!spp_gchip)
return -ENOMEM;
pctl->spp_gchip = spp_gchip;
spp_gchip->gpioxt_base = pctl->gpioxt_base;
spp_gchip->first_base = pctl->first_base;
spin_lock_init(&spp_gchip->lock);
gchip = &spp_gchip->chip;
gchip->label = SPPCTL_MODULE_NAME;
gchip->parent = &pdev->dev;
gchip->owner = THIS_MODULE;
gchip->request = gpiochip_generic_request;
gchip->free = gpiochip_generic_free;
gchip->get_direction = sppctl_gpio_get_direction;
gchip->direction_input = sppctl_gpio_direction_input;
gchip->direction_output = sppctl_gpio_direction_output;
gchip->get = sppctl_gpio_get;
gchip->set = sppctl_gpio_set;
gchip->set_config = sppctl_gpio_set_config;
gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ?
sppctl_gpio_dbg_show : NULL;
gchip->base = -1;
gchip->ngpio = sppctl_gpio_list_sz;
gchip->names = sppctl_gpio_list_s;
pctl->pctl_grange.npins = gchip->ngpio;
pctl->pctl_grange.name = gchip->label;
pctl->pctl_grange.gc = gchip;
err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip);
if (err)
return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n");
return 0;
}
static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
unsigned int arg;
switch (param) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin))
return -EINVAL;
arg = 0;
break;
case PIN_CONFIG_OUTPUT:
if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
return -EINVAL;
if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
return -EINVAL;
if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin))
return -EINVAL;
arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin);
break;
default:
return -EOPNOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
int i;
/* Special handling for IOP pins */
if (configs[0] == SPPCTL_IOP_CONFIGS) {
sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop);
return 0;
}
for (i = 0; i < num_configs; i++) {
if (configs[i] & SPPCTL_PCTL_L_OUT)
sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0);
if (configs[i] & SPPCTL_PCTL_L_OU1)
sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1);
if (configs[i] & SPPCTL_PCTL_L_INV)
sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin);
if (configs[i] & SPPCTL_PCTL_L_ONV)
sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin);
if (configs[i] & SPPCTL_PCTL_L_ODR)
sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1);
}
return 0;
}
static const struct pinconf_ops sppctl_pconf_ops = {
.is_generic = true,
.pin_config_get = sppctl_pin_config_get,
.pin_config_set = sppctl_pin_config_set,
};
static int sppctl_get_functions_count(struct pinctrl_dev *pctldev)
{
return sppctl_list_funcs_sz;
}
static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return sppctl_list_funcs[selector].name;
}
static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
const char * const **groups, unsigned int *num_groups)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct sppctl_func *f = &sppctl_list_funcs[selector];
int i;
*num_groups = 0;
switch (f->type) {
case pinmux_type_fpmx:
*num_groups = sppctl_pmux_list_sz;
*groups = sppctl_pmux_list_s;
break;
case pinmux_type_grp:
if (!f->grps)
break;
*num_groups = f->gnum;
for (i = 0; i < pctl->unq_grps_sz; i++)
if (pctl->g2fp_maps[i].f_idx == selector)
break;
*groups = &pctl->unq_grps[i];
break;
default:
dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n",
selector, f->type);
break;
}
return 0;
}
/**
* sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting
*
* Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by
* settings its control-field. Refer to following table:
*
* control-field | GPIO
* --------------+--------
* 0 | No map
* 1 | 8
* 2 | 9
* 3 | 10
* : | :
* 65 | 71
*/
static inline int sppctl_fully_pinmux_conv(unsigned int offset)
{
return (offset < 8) ? 0 : offset - 7;
}
static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
unsigned int group_selector)
{
const struct sppctl_func *f = &sppctl_list_funcs[func_selector];
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector];
int i;
switch (f->type) {
case pinmux_type_fpmx:
sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector,
mux_f_mux, mux_m_keep);
sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector));
break;
case pinmux_type_grp:
for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++)
sppctl_first_master_set(&pctl->spp_gchip->chip,
f->grps[g2fpm.g_idx].pins[i],
mux_f_mux, mux_m_keep);
sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval);
break;
default:
dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n",
func_selector, f->type);
break;
}
return 0;
}
static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned int offset)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
int g_f, g_m;
g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset);
g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset);
if (g_f == mux_f_gpio && g_m == mux_m_gpio)
return 0;
sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio);
return 0;
}
static const struct pinmux_ops sppctl_pinmux_ops = {
.get_functions_count = sppctl_get_functions_count,
.get_function_name = sppctl_get_function_name,
.get_function_groups = sppctl_get_function_groups,
.set_mux = sppctl_set_mux,
.gpio_request_enable = sppctl_gpio_request_enable,
.strict = true,
};
static int sppctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->unq_grps_sz;
}
static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->unq_grps[selector];
}
static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
const unsigned int **pins, unsigned int *num_pins)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
struct grp2fp_map g2fpm = pctl->g2fp_maps[selector];
const struct sppctl_func *f;
f = &sppctl_list_funcs[g2fpm.f_idx];
*num_pins = 0;
/* Except group-pinmux, each group has 1 pin. */
if (f->type != pinmux_type_grp) {
*num_pins = 1;
*pins = &sppctl_pins_gpio[selector];
return 0;
}
/* Group-pinmux may have more than one pin. */
if (!f->grps)
return 0;
if (f->gnum < 1)
return 0;
*num_pins = f->grps[g2fpm.g_idx].pnum;
*pins = f->grps[g2fpm.g_idx].pins;
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
const char *pin_type;
u8 first, master;
first = sppctl_first_get(&pctl->spp_gchip->chip, offset);
master = sppctl_master_get(&pctl->spp_gchip->chip, offset);
if (first)
if (master)
pin_type = "GPIO";
else
pin_type = " IOP";
else
pin_type = " MUX";
seq_printf(s, " %s", pin_type);
}
#endif
static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config,
struct pinctrl_map **map, unsigned int *num_maps)
{
struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
int nmG = of_property_count_strings(np_config, "groups");
const struct sppctl_func *f = NULL;
u8 pin_num, pin_type, pin_func;
struct device_node *parent;
unsigned long *configs;
struct property *prop;
const char *s_f, *s_g;
const __be32 *list;
u32 dt_pin, dt_fun;
int i, size = 0;
list = of_get_property(np_config, "sunplus,pins", &size);
*num_maps = size / sizeof(*list);
/*
* Process property:
* sunplus,pins = < u32 u32 u32 ... >;
*
* Each 32-bit integer defines a individual pin in which:
*
* Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98.
* Bit 23~16: defines types: (1) fully-pinmux pins
* (2) IO processor pins
* (3) digital GPIO pins
* Bit 15~8: defines pins of peripherals (which are defined in
* 'include/dt-binging/pinctrl/sppctl.h').
* Bit 7~0: defines types or initial-state of digital GPIO pins.
*/
for (i = 0; i < (*num_maps); i++) {
dt_pin = be32_to_cpu(list[i]);
pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
if (pin_num >= sppctl_pins_all_sz) {
dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n",
i, dt_pin);
return -EINVAL;
}
}
if (nmG <= 0)
nmG = 0;
*map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL);
if (!(*map))
return -ENOMEM;
parent = of_get_parent(np_config);
for (i = 0; i < (*num_maps); i++) {
dt_pin = be32_to_cpu(list[i]);
pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
pin_type = FIELD_GET(GENMASK(23, 16), dt_pin);
pin_func = FIELD_GET(GENMASK(15, 8), dt_pin);
(*map)[i].name = parent->name;
if (pin_type == SPPCTL_PCTL_G_GPIO) {
/* A digital GPIO pin */
(*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
(*map)[i].data.configs.num_configs = 1;
(*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
configs = kmalloc(sizeof(*configs), GFP_KERNEL);
if (!configs)
goto sppctl_map_err;
*configs = FIELD_GET(GENMASK(7, 0), dt_pin);
(*map)[i].data.configs.configs = configs;
dev_dbg(pctldev->dev, "%s: GPIO (%s)\n",
(*map)[i].data.configs.group_or_pin,
(*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ?
"OUT" : "IN");
} else if (pin_type == SPPCTL_PCTL_G_IOPP) {
/* A IO Processor (IOP) pin */
(*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
(*map)[i].data.configs.num_configs = 1;
(*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
configs = kmalloc(sizeof(*configs), GFP_KERNEL);
if (!configs)
goto sppctl_map_err;
*configs = SPPCTL_IOP_CONFIGS;
(*map)[i].data.configs.configs = configs;
dev_dbg(pctldev->dev, "%s: IOP\n",
(*map)[i].data.configs.group_or_pin);
} else {
/* A fully-pinmux pin */
(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name;
(*map)[i].data.mux.group = pin_get_name(pctldev, pin_num);
dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group,
(*map)[i].data.mux.function);
}
}
/*
* Process properties:
* function = "xxx";
* groups = "yyy";
*/
if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) {
of_property_for_each_string(np_config, "groups", prop, s_g) {
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.function = s_f;
(*map)[*num_maps].data.mux.group = s_g;
(*num_maps)++;
dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g);
}
}
/*
* Process property:
* sunplus,zerofunc = < u32 u32 u32 ...>
*/
list = of_get_property(np_config, "sunplus,zerofunc", &size);
if (list) {
for (i = 0; i < (size / sizeof(*list)); i++) {
dt_fun = be32_to_cpu(list[i]);
if (dt_fun >= sppctl_list_funcs_sz) {
dev_err(pctldev->dev, "Zero-func %d out of range!\n",
dt_fun);
continue;
}
f = &sppctl_list_funcs[dt_fun];
switch (f->type) {
case pinmux_type_fpmx:
sppctl_func_set(pctl, dt_fun, 0);
dev_dbg(pctldev->dev, "%s: No map\n", f->name);
break;
case pinmux_type_grp:
sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0);
dev_dbg(pctldev->dev, "%s: No map\n", f->name);
break;
default:
dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n",
dt_fun, f->name);
break;
}
}
}
of_node_put(parent);
dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps);
return 0;
sppctl_map_err:
for (i = 0; i < (*num_maps); i++)
if ((*map)[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree((*map)[i].data.configs.configs);
kfree(*map);
of_node_put(parent);
return -ENOMEM;
}
static const struct pinctrl_ops sppctl_pctl_ops = {
.get_groups_count = sppctl_get_groups_count,
.get_group_name = sppctl_get_group_name,
.get_group_pins = sppctl_get_group_pins,
#ifdef CONFIG_DEBUG_FS
.pin_dbg_show = sppctl_pin_dbg_show,
#endif
.dt_node_to_map = sppctl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int sppctl_group_groups(struct platform_device *pdev)
{
struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
int i, k, j;
/* Calculate number of total group (GPIO + group-pinmux group). */
sppctl->unq_grps_sz = sppctl_gpio_list_sz;
for (i = 0; i < sppctl_list_funcs_sz; i++)
if (sppctl_list_funcs[i].type == pinmux_type_grp)
sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum;
sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
sizeof(*sppctl->unq_grps), GFP_KERNEL);
if (!sppctl->unq_grps)
return -ENOMEM;
sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
sizeof(*sppctl->g2fp_maps), GFP_KERNEL);
if (!sppctl->g2fp_maps)
return -ENOMEM;
/* Add GPIO pins. */
for (i = 0; i < sppctl_gpio_list_sz; i++) {
sppctl->unq_grps[i] = sppctl_gpio_list_s[i];
sppctl->g2fp_maps[i].f_idx = 0;
sppctl->g2fp_maps[i].g_idx = i;
}
/* Add group-pinmux to end of GPIO pins. */
j = sppctl_gpio_list_sz;
for (i = 0; i < sppctl_list_funcs_sz; i++) {
if (sppctl_list_funcs[i].type != pinmux_type_grp)
continue;
for (k = 0; k < sppctl_list_funcs[i].gnum; k++) {
sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name;
sppctl->g2fp_maps[j].f_idx = i;
sppctl->g2fp_maps[j].g_idx = k;
j++;
}
}
return 0;
}
static int sppctl_pinctrl_init(struct platform_device *pdev)
{
struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
int err;
sppctl->pctl_desc.owner = THIS_MODULE;
sppctl->pctl_desc.name = dev_name(&pdev->dev);
sppctl->pctl_desc.pins = sppctl_pins_all;
sppctl->pctl_desc.npins = sppctl_pins_all_sz;
sppctl->pctl_desc.pctlops = &sppctl_pctl_ops;
sppctl->pctl_desc.confops = &sppctl_pconf_ops;
sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops;
err = sppctl_group_groups(pdev);
if (err)
return err;
err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc,
sppctl, &sppctl->pctl_dev);
if (err)
return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n");
pinctrl_enable(sppctl->pctl_dev);
return 0;
}
static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl)
{
sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2");
if (IS_ERR(sppctl->moon2_base))
return PTR_ERR(sppctl->moon2_base);
sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt");
if (IS_ERR(sppctl->gpioxt_base))
return PTR_ERR(sppctl->gpioxt_base);
sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first");
if (IS_ERR(sppctl->first_base))
return PTR_ERR(sppctl->first_base);
sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1");
if (IS_ERR(sppctl->moon1_base))
return PTR_ERR(sppctl->moon1_base);
return 0;
}
static int sppctl_probe(struct platform_device *pdev)
{
struct sppctl_pdata *sppctl;
int ret;
sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL);
if (!sppctl)
return -ENOMEM;
platform_set_drvdata(pdev, sppctl);
ret = sppctl_resource_map(pdev, sppctl);
if (ret)
return ret;
ret = sppctl_gpio_new(pdev, sppctl);
if (ret)
return ret;
ret = sppctl_pinctrl_init(pdev);
if (ret)
return ret;
pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange);
return 0;
}
static const struct of_device_id sppctl_match_table[] = {
{ .compatible = "sunplus,sp7021-pctl" },
{ /* sentinel */ }
};
static struct platform_driver sppctl_pinctrl_driver = {
.driver = {
.name = SPPCTL_MODULE_NAME,
.of_match_table = sppctl_match_table,
},
.probe = sppctl_probe,
};
builtin_platform_driver(sppctl_pinctrl_driver)
MODULE_AUTHOR("Dvorkin Dmitry <[email protected]>");
MODULE_AUTHOR("Wells Lu <[email protected]>");
MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/sunplus/sppctl.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* SP7021 Pin Controller Driver.
* Copyright (C) Sunplus Tech / Tibbo Tech.
*/
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinctrl.h>
#include "sppctl.h"
#define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y)
#define D(x, y) ((x) * 8 + (y))
#define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y))
const char * const sppctl_gpio_list_s[] = {
D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3),
D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7),
D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3),
D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3),
D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3),
D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3),
D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7),
D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3),
D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7),
D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3),
D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7),
D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3),
D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7),
D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3),
D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7),
D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3),
D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7),
D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3),
D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7),
D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3),
D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7),
D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2),
};
const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s);
const unsigned int sppctl_pins_gpio[] = {
D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7),
D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7),
D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7),
D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7),
D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7),
D(12, 0), D(12, 1), D(12, 2),
};
const struct pinctrl_pin_desc sppctl_pins_all[] = {
/* gpio and iop only */
P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7),
/* gpio, iop, muxable */
P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7),
P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7),
P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7),
P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7),
P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7),
P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7),
P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7),
P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7),
/* gpio and iop only */
P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7),
P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7),
P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7),
P(12, 0), P(12, 1), P(12, 2),
};
const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all);
const char * const sppctl_pmux_list_s[] = {
D_PIS(0, 0),
D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3),
D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3),
D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3),
D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3),
D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7),
D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3),
D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7),
D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3),
D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7),
D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3),
D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7),
D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3),
D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7),
};
const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s);
static const unsigned int pins_spif1[] = {
D(10, 3), D(10, 4), D(10, 6), D(10, 7),
};
static const unsigned int pins_spif2[] = {
D(9, 4), D(9, 6), D(9, 7), D(10, 1),
};
static const struct sppctl_grp sp7021grps_spif[] = {
EGRP("SPI_FLASH1", 1, pins_spif1),
EGRP("SPI_FLASH2", 2, pins_spif2),
};
static const unsigned int pins_spi41[] = {
D(10, 2), D(10, 5),
};
static const unsigned int pins_spi42[] = {
D(9, 5), D(9, 8),
};
static const struct sppctl_grp sp7021grps_spi4[] = {
EGRP("SPI_FLASH_4BIT1", 1, pins_spi41),
EGRP("SPI_FLASH_4BIT2", 2, pins_spi42),
};
static const unsigned int pins_snan[] = {
D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1),
};
static const struct sppctl_grp sp7021grps_snan[] = {
EGRP("SPI_NAND", 1, pins_snan),
};
static const unsigned int pins_emmc[] = {
D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5),
D(9, 6), D(9, 7), D(10, 0), D(10, 1),
};
static const struct sppctl_grp sp7021grps_emmc[] = {
EGRP("CARD0_EMMC", 1, pins_emmc),
};
static const unsigned int pins_sdsd[] = {
D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6),
};
static const struct sppctl_grp sp7021grps_sdsd[] = {
EGRP("SD_CARD", 1, pins_sdsd),
};
static const unsigned int pins_uar0[] = {
D(11, 0), D(11, 1),
};
static const struct sppctl_grp sp7021grps_uar0[] = {
EGRP("UA0", 1, pins_uar0),
};
static const unsigned int pins_adbg1[] = {
D(10, 2), D(10, 3),
};
static const unsigned int pins_adbg2[] = {
D(7, 1), D(7, 2),
};
static const struct sppctl_grp sp7021grps_adbg[] = {
EGRP("ACHIP_DEBUG1", 1, pins_adbg1),
EGRP("ACHIP_DEBUG2", 2, pins_adbg2),
};
static const unsigned int pins_aua2axi1[] = {
D(2, 0), D(2, 1), D(2, 2),
};
static const unsigned int pins_aua2axi2[] = {
D(1, 0), D(1, 1), D(1, 2),
};
static const struct sppctl_grp sp7021grps_au2x[] = {
EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1),
EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2),
};
static const unsigned int pins_fpga[] = {
D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5),
D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1),
D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5),
D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2),
};
static const struct sppctl_grp sp7021grps_fpga[] = {
EGRP("FPGA_IFX", 1, pins_fpga),
};
static const unsigned int pins_hdmi1[] = {
D(10, 6), D(12, 2), D(12, 1),
};
static const unsigned int pins_hdmi2[] = {
D(8, 3), D(8, 5), D(8, 6),
};
static const unsigned int pins_hdmi3[] = {
D(7, 4), D(7, 6), D(7, 7),
};
static const struct sppctl_grp sp7021grps_hdmi[] = {
EGRP("HDMI_TX1", 1, pins_hdmi1),
EGRP("HDMI_TX2", 2, pins_hdmi2),
EGRP("HDMI_TX3", 3, pins_hdmi3),
};
static const unsigned int pins_eadc[] = {
D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6),
};
static const struct sppctl_grp sp7021grps_eadc[] = {
EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc),
};
static const unsigned int pins_edac[] = {
D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4),
};
static const struct sppctl_grp sp7021grps_edac[] = {
EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac),
};
static const unsigned int pins_spdi[] = {
D(2, 4),
};
static const struct sppctl_grp sp7021grps_spdi[] = {
EGRP("AUD_IEC_RX0", 1, pins_spdi),
};
static const unsigned int pins_spdo[] = {
D(3, 6),
};
static const struct sppctl_grp sp7021grps_spdo[] = {
EGRP("AUD_IEC_TX0", 1, pins_spdo),
};
static const unsigned int pins_tdmt[] = {
D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2),
};
static const struct sppctl_grp sp7021grps_tdmt[] = {
EGRP("TDMTX_IFX0", 1, pins_tdmt),
};
static const unsigned int pins_tdmr[] = {
D(1, 7), D(2, 0), D(2, 1), D(2, 2),
};
static const struct sppctl_grp sp7021grps_tdmr[] = {
EGRP("TDMRX_IFX0", 1, pins_tdmr),
};
static const unsigned int pins_pdmr[] = {
D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
};
static const struct sppctl_grp sp7021grps_pdmr[] = {
EGRP("PDMRX_IFX0", 1, pins_pdmr),
};
static const unsigned int pins_pcmt[] = {
D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4),
};
static const struct sppctl_grp sp7021grps_pcmt[] = {
EGRP("PCM_IEC_TX", 1, pins_pcmt),
};
static const unsigned int pins_lcdi[] = {
D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3),
D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3),
D(4, 4), D(4, 5), D(4, 6), D(4, 7),
};
static const struct sppctl_grp sp7021grps_lcdi[] = {
EGRP("LCDIF", 1, pins_lcdi),
};
static const unsigned int pins_dvdd[] = {
D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5),
};
static const struct sppctl_grp sp7021grps_dvdd[] = {
EGRP("DVD_DSP_DEBUG", 1, pins_dvdd),
};
static const unsigned int pins_i2cd[] = {
D(1, 0), D(1, 1),
};
static const struct sppctl_grp sp7021grps_i2cd[] = {
EGRP("I2C_DEBUG", 1, pins_i2cd),
};
static const unsigned int pins_i2cs[] = {
D(0, 0), D(0, 1),
};
static const struct sppctl_grp sp7021grps_i2cs[] = {
EGRP("I2C_SLAVE", 1, pins_i2cs),
};
static const unsigned int pins_wakp[] = {
D(10, 5),
};
static const struct sppctl_grp sp7021grps_wakp[] = {
EGRP("WAKEUP", 1, pins_wakp),
};
static const unsigned int pins_u2ax[] = {
D(2, 0), D(2, 1), D(3, 0), D(3, 1),
};
static const struct sppctl_grp sp7021grps_u2ax[] = {
EGRP("UART2AXI", 1, pins_u2ax),
};
static const unsigned int pins_u0ic[] = {
D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1),
};
static const struct sppctl_grp sp7021grps_u0ic[] = {
EGRP("USB0_I2C", 1, pins_u0ic),
};
static const unsigned int pins_u1ic[] = {
D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3),
};
static const struct sppctl_grp sp7021grps_u1ic[] = {
EGRP("USB1_I2C", 1, pins_u1ic),
};
static const unsigned int pins_u0ot[] = {
D(11, 2),
};
static const struct sppctl_grp sp7021grps_u0ot[] = {
EGRP("USB0_OTG", 1, pins_u0ot),
};
static const unsigned int pins_u1ot[] = {
D(11, 3),
};
static const struct sppctl_grp sp7021grps_u1ot[] = {
EGRP("USB1_OTG", 1, pins_u1ot),
};
static const unsigned int pins_uphd[] = {
D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6),
D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3),
D(9, 7), D(10, 2), D(10, 3), D(10, 4),
};
static const struct sppctl_grp sp7021grps_up0d[] = {
EGRP("UPHY0_DEBUG", 1, pins_uphd),
};
static const struct sppctl_grp sp7021grps_up1d[] = {
EGRP("UPHY1_DEBUG", 1, pins_uphd),
};
static const unsigned int pins_upex[] = {
D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7),
D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7),
D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7),
D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7),
};
static const struct sppctl_grp sp7021grps_upex[] = {
EGRP("UPHY0_EXT", 1, pins_upex),
};
static const unsigned int pins_prp1[] = {
D(0, 6), D(0, 7),
D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
D(3, 0), D(3, 1), D(3, 2),
};
static const unsigned int pins_prp2[] = {
D(3, 4), D(3, 6), D(3, 7),
D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
D(6, 4),
};
static const struct sppctl_grp sp7021grps_prbp[] = {
EGRP("PROBE_PORT1", 1, pins_prp1),
EGRP("PROBE_PORT2", 2, pins_prp2),
};
/*
* Due to compatible reason, the first valid item should start at the third
* position of the array. Please keep the first two items of the table
* no use (dummy).
*/
const struct sppctl_func sppctl_list_funcs[] = {
FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7),
FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7),
FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7),
FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7),
FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7),
FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7),
FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7),
FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7),
FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7),
FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7),
FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7),
FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7),
FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7),
FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7),
FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7),
FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7),
FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7),
FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7),
FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7),
FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7),
FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7),
FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7),
FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */
FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7),
FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7),
FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7),
FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7),
FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7),
FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */
FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7),
FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7),
FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7),
FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7),
FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7),
FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7),
FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7),
FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */
FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7),
FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7),
FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7),
FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7),
FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7),
FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7),
FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7),
FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */
FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7),
FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7),
FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7),
FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7),
FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7),
FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7),
FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7),
FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7),
FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7),
FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7),
FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7),
FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7),
FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7),
FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7),
FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7),
FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7),
FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7),
FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7),
FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7),
FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */
FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7),
FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7),
FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7),
FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7),
FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7),
FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7),
FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7),
FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7),
FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7),
FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7),
FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7),
FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7),
FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7),
FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7),
FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7),
FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7),
FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7),
FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7),
FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7),
FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */
FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7),
FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7),
FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7),
FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7),
FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7),
FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7),
FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7),
FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */
FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7),
FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7),
FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7),
FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7),
FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7),
FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7),
FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7),
FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7),
FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7),
FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7),
FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7),
FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7),
FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7),
FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7),
FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7),
FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */
FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7),
FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7),
FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7),
FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */
FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7),
FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7),
FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7),
FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7),
FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7),
FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7),
FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7),
/* MOON1 register */
FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif),
FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4),
FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan),
FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc),
FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd),
FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0),
FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg),
FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x),
FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga),
FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi),
FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc),
FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac),
FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi),
FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo),
FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt),
FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr),
FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr),
FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt),
FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi),
FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd),
FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd),
FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs),
FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp),
FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax),
FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic),
FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic),
FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot),
FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot),
FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d),
FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d),
FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex),
FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp),
};
const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs);
|
linux-master
|
drivers/pinctrl/sunplus/sppctl_sp7021.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for the NVIDIA Tegra114 pinmux
*
* Author: Pritesh Raithatha <[email protected]>
*
* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
#define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
#define TEGRA_PIN_PU0 _GPIO(160)
#define TEGRA_PIN_PU1 _GPIO(161)
#define TEGRA_PIN_PU2 _GPIO(162)
#define TEGRA_PIN_PU3 _GPIO(163)
#define TEGRA_PIN_PU4 _GPIO(164)
#define TEGRA_PIN_PU5 _GPIO(165)
#define TEGRA_PIN_PU6 _GPIO(166)
#define TEGRA_PIN_PV0 _GPIO(168)
#define TEGRA_PIN_PV1 _GPIO(169)
#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
#define TEGRA_PIN_PBB0 _GPIO(216)
#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
#define TEGRA_PIN_PBB3 _GPIO(219)
#define TEGRA_PIN_PBB4 _GPIO(220)
#define TEGRA_PIN_PBB5 _GPIO(221)
#define TEGRA_PIN_PBB6 _GPIO(222)
#define TEGRA_PIN_PBB7 _GPIO(223)
#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
#define TEGRA_PIN_PCC1 _GPIO(225)
#define TEGRA_PIN_PCC2 _GPIO(226)
#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
/* Non-GPIO pins */
#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
#define TEGRA_PIN_PWR_INT_N _PIN(2)
#define TEGRA_PIN_RESET_OUT_N _PIN(3)
#define TEGRA_PIN_OWR _PIN(4)
#define TEGRA_PIN_JTAG_RTCK _PIN(5)
#define TEGRA_PIN_CLK_32K_IN _PIN(6)
#define TEGRA_PIN_GMI_CLK_LB _PIN(7)
static const struct pinctrl_pin_desc tegra114_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
};
static const unsigned clk_32k_out_pa0_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
};
static const unsigned uart3_cts_n_pa1_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
};
static const unsigned dap2_fs_pa2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
};
static const unsigned dap2_sclk_pa3_pins[] = {
TEGRA_PIN_DAP2_SCLK_PA3,
};
static const unsigned dap2_din_pa4_pins[] = {
TEGRA_PIN_DAP2_DIN_PA4,
};
static const unsigned dap2_dout_pa5_pins[] = {
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned sdmmc3_clk_pa6_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
};
static const unsigned sdmmc3_cmd_pa7_pins[] = {
TEGRA_PIN_SDMMC3_CMD_PA7,
};
static const unsigned gmi_a17_pb0_pins[] = {
TEGRA_PIN_GMI_A17_PB0,
};
static const unsigned gmi_a18_pb1_pins[] = {
TEGRA_PIN_GMI_A18_PB1,
};
static const unsigned sdmmc3_dat3_pb4_pins[] = {
TEGRA_PIN_SDMMC3_DAT3_PB4,
};
static const unsigned sdmmc3_dat2_pb5_pins[] = {
TEGRA_PIN_SDMMC3_DAT2_PB5,
};
static const unsigned sdmmc3_dat1_pb6_pins[] = {
TEGRA_PIN_SDMMC3_DAT1_PB6,
};
static const unsigned sdmmc3_dat0_pb7_pins[] = {
TEGRA_PIN_SDMMC3_DAT0_PB7,
};
static const unsigned uart3_rts_n_pc0_pins[] = {
TEGRA_PIN_UART3_RTS_N_PC0,
};
static const unsigned uart2_txd_pc2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
};
static const unsigned uart2_rxd_pc3_pins[] = {
TEGRA_PIN_UART2_RXD_PC3,
};
static const unsigned gen1_i2c_scl_pc4_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
};
static const unsigned gen1_i2c_sda_pc5_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PC5,
};
static const unsigned gmi_wp_n_pc7_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
};
static const unsigned gmi_ad0_pg0_pins[] = {
TEGRA_PIN_GMI_AD0_PG0,
};
static const unsigned gmi_ad1_pg1_pins[] = {
TEGRA_PIN_GMI_AD1_PG1,
};
static const unsigned gmi_ad2_pg2_pins[] = {
TEGRA_PIN_GMI_AD2_PG2,
};
static const unsigned gmi_ad3_pg3_pins[] = {
TEGRA_PIN_GMI_AD3_PG3,
};
static const unsigned gmi_ad4_pg4_pins[] = {
TEGRA_PIN_GMI_AD4_PG4,
};
static const unsigned gmi_ad5_pg5_pins[] = {
TEGRA_PIN_GMI_AD5_PG5,
};
static const unsigned gmi_ad6_pg6_pins[] = {
TEGRA_PIN_GMI_AD6_PG6,
};
static const unsigned gmi_ad7_pg7_pins[] = {
TEGRA_PIN_GMI_AD7_PG7,
};
static const unsigned gmi_ad8_ph0_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
};
static const unsigned gmi_ad9_ph1_pins[] = {
TEGRA_PIN_GMI_AD9_PH1,
};
static const unsigned gmi_ad10_ph2_pins[] = {
TEGRA_PIN_GMI_AD10_PH2,
};
static const unsigned gmi_ad11_ph3_pins[] = {
TEGRA_PIN_GMI_AD11_PH3,
};
static const unsigned gmi_ad12_ph4_pins[] = {
TEGRA_PIN_GMI_AD12_PH4,
};
static const unsigned gmi_ad13_ph5_pins[] = {
TEGRA_PIN_GMI_AD13_PH5,
};
static const unsigned gmi_ad14_ph6_pins[] = {
TEGRA_PIN_GMI_AD14_PH6,
};
static const unsigned gmi_ad15_ph7_pins[] = {
TEGRA_PIN_GMI_AD15_PH7,
};
static const unsigned gmi_wr_n_pi0_pins[] = {
TEGRA_PIN_GMI_WR_N_PI0,
};
static const unsigned gmi_oe_n_pi1_pins[] = {
TEGRA_PIN_GMI_OE_N_PI1,
};
static const unsigned gmi_cs6_n_pi3_pins[] = {
TEGRA_PIN_GMI_CS6_N_PI3,
};
static const unsigned gmi_rst_n_pi4_pins[] = {
TEGRA_PIN_GMI_RST_N_PI4,
};
static const unsigned gmi_iordy_pi5_pins[] = {
TEGRA_PIN_GMI_IORDY_PI5,
};
static const unsigned gmi_cs7_n_pi6_pins[] = {
TEGRA_PIN_GMI_CS7_N_PI6,
};
static const unsigned gmi_wait_pi7_pins[] = {
TEGRA_PIN_GMI_WAIT_PI7,
};
static const unsigned gmi_cs0_n_pj0_pins[] = {
TEGRA_PIN_GMI_CS0_N_PJ0,
};
static const unsigned gmi_cs1_n_pj2_pins[] = {
TEGRA_PIN_GMI_CS1_N_PJ2,
};
static const unsigned gmi_dqs_p_pj3_pins[] = {
TEGRA_PIN_GMI_DQS_P_PJ3,
};
static const unsigned uart2_cts_n_pj5_pins[] = {
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned uart2_rts_n_pj6_pins[] = {
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned gmi_a16_pj7_pins[] = {
TEGRA_PIN_GMI_A16_PJ7,
};
static const unsigned gmi_adv_n_pk0_pins[] = {
TEGRA_PIN_GMI_ADV_N_PK0,
};
static const unsigned gmi_clk_pk1_pins[] = {
TEGRA_PIN_GMI_CLK_PK1,
};
static const unsigned gmi_cs4_n_pk2_pins[] = {
TEGRA_PIN_GMI_CS4_N_PK2,
};
static const unsigned gmi_cs2_n_pk3_pins[] = {
TEGRA_PIN_GMI_CS2_N_PK3,
};
static const unsigned gmi_cs3_n_pk4_pins[] = {
TEGRA_PIN_GMI_CS3_N_PK4,
};
static const unsigned spdif_out_pk5_pins[] = {
TEGRA_PIN_SPDIF_OUT_PK5,
};
static const unsigned spdif_in_pk6_pins[] = {
TEGRA_PIN_SPDIF_IN_PK6,
};
static const unsigned gmi_a19_pk7_pins[] = {
TEGRA_PIN_GMI_A19_PK7,
};
static const unsigned dap1_fs_pn0_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
};
static const unsigned dap1_din_pn1_pins[] = {
TEGRA_PIN_DAP1_DIN_PN1,
};
static const unsigned dap1_dout_pn2_pins[] = {
TEGRA_PIN_DAP1_DOUT_PN2,
};
static const unsigned dap1_sclk_pn3_pins[] = {
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned usb_vbus_en0_pn4_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PN4,
};
static const unsigned usb_vbus_en1_pn5_pins[] = {
TEGRA_PIN_USB_VBUS_EN1_PN5,
};
static const unsigned hdmi_int_pn7_pins[] = {
TEGRA_PIN_HDMI_INT_PN7,
};
static const unsigned ulpi_data7_po0_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
};
static const unsigned ulpi_data0_po1_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
};
static const unsigned ulpi_data1_po2_pins[] = {
TEGRA_PIN_ULPI_DATA1_PO2,
};
static const unsigned ulpi_data2_po3_pins[] = {
TEGRA_PIN_ULPI_DATA2_PO3,
};
static const unsigned ulpi_data3_po4_pins[] = {
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned ulpi_data4_po5_pins[] = {
TEGRA_PIN_ULPI_DATA4_PO5,
};
static const unsigned ulpi_data5_po6_pins[] = {
TEGRA_PIN_ULPI_DATA5_PO6,
};
static const unsigned ulpi_data6_po7_pins[] = {
TEGRA_PIN_ULPI_DATA6_PO7,
};
static const unsigned dap3_fs_pp0_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
};
static const unsigned dap3_din_pp1_pins[] = {
TEGRA_PIN_DAP3_DIN_PP1,
};
static const unsigned dap3_dout_pp2_pins[] = {
TEGRA_PIN_DAP3_DOUT_PP2,
};
static const unsigned dap3_sclk_pp3_pins[] = {
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned dap4_fs_pp4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
};
static const unsigned dap4_din_pp5_pins[] = {
TEGRA_PIN_DAP4_DIN_PP5,
};
static const unsigned dap4_dout_pp6_pins[] = {
TEGRA_PIN_DAP4_DOUT_PP6,
};
static const unsigned dap4_sclk_pp7_pins[] = {
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned kb_col0_pq0_pins[] = {
TEGRA_PIN_KB_COL0_PQ0,
};
static const unsigned kb_col1_pq1_pins[] = {
TEGRA_PIN_KB_COL1_PQ1,
};
static const unsigned kb_col2_pq2_pins[] = {
TEGRA_PIN_KB_COL2_PQ2,
};
static const unsigned kb_col3_pq3_pins[] = {
TEGRA_PIN_KB_COL3_PQ3,
};
static const unsigned kb_col4_pq4_pins[] = {
TEGRA_PIN_KB_COL4_PQ4,
};
static const unsigned kb_col5_pq5_pins[] = {
TEGRA_PIN_KB_COL5_PQ5,
};
static const unsigned kb_col6_pq6_pins[] = {
TEGRA_PIN_KB_COL6_PQ6,
};
static const unsigned kb_col7_pq7_pins[] = {
TEGRA_PIN_KB_COL7_PQ7,
};
static const unsigned kb_row0_pr0_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
};
static const unsigned kb_row1_pr1_pins[] = {
TEGRA_PIN_KB_ROW1_PR1,
};
static const unsigned kb_row2_pr2_pins[] = {
TEGRA_PIN_KB_ROW2_PR2,
};
static const unsigned kb_row3_pr3_pins[] = {
TEGRA_PIN_KB_ROW3_PR3,
};
static const unsigned kb_row4_pr4_pins[] = {
TEGRA_PIN_KB_ROW4_PR4,
};
static const unsigned kb_row5_pr5_pins[] = {
TEGRA_PIN_KB_ROW5_PR5,
};
static const unsigned kb_row6_pr6_pins[] = {
TEGRA_PIN_KB_ROW6_PR6,
};
static const unsigned kb_row7_pr7_pins[] = {
TEGRA_PIN_KB_ROW7_PR7,
};
static const unsigned kb_row8_ps0_pins[] = {
TEGRA_PIN_KB_ROW8_PS0,
};
static const unsigned kb_row9_ps1_pins[] = {
TEGRA_PIN_KB_ROW9_PS1,
};
static const unsigned kb_row10_ps2_pins[] = {
TEGRA_PIN_KB_ROW10_PS2,
};
static const unsigned gen2_i2c_scl_pt5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
};
static const unsigned gen2_i2c_sda_pt6_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned sdmmc4_cmd_pt7_pins[] = {
TEGRA_PIN_SDMMC4_CMD_PT7,
};
static const unsigned pu0_pins[] = {
TEGRA_PIN_PU0,
};
static const unsigned pu1_pins[] = {
TEGRA_PIN_PU1,
};
static const unsigned pu2_pins[] = {
TEGRA_PIN_PU2,
};
static const unsigned pu3_pins[] = {
TEGRA_PIN_PU3,
};
static const unsigned pu4_pins[] = {
TEGRA_PIN_PU4,
};
static const unsigned pu5_pins[] = {
TEGRA_PIN_PU5,
};
static const unsigned pu6_pins[] = {
TEGRA_PIN_PU6,
};
static const unsigned pv0_pins[] = {
TEGRA_PIN_PV0,
};
static const unsigned pv1_pins[] = {
TEGRA_PIN_PV1,
};
static const unsigned sdmmc3_cd_n_pv2_pins[] = {
TEGRA_PIN_SDMMC3_CD_N_PV2,
};
static const unsigned sdmmc1_wp_n_pv3_pins[] = {
TEGRA_PIN_SDMMC1_WP_N_PV3,
};
static const unsigned ddc_scl_pv4_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
};
static const unsigned ddc_sda_pv5_pins[] = {
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned gpio_w2_aud_pw2_pins[] = {
TEGRA_PIN_GPIO_W2_AUD_PW2,
};
static const unsigned gpio_w3_aud_pw3_pins[] = {
TEGRA_PIN_GPIO_W3_AUD_PW3,
};
static const unsigned clk1_out_pw4_pins[] = {
TEGRA_PIN_CLK1_OUT_PW4,
};
static const unsigned clk2_out_pw5_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
};
static const unsigned uart3_txd_pw6_pins[] = {
TEGRA_PIN_UART3_TXD_PW6,
};
static const unsigned uart3_rxd_pw7_pins[] = {
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned dvfs_pwm_px0_pins[] = {
TEGRA_PIN_DVFS_PWM_PX0,
};
static const unsigned gpio_x1_aud_px1_pins[] = {
TEGRA_PIN_GPIO_X1_AUD_PX1,
};
static const unsigned dvfs_clk_px2_pins[] = {
TEGRA_PIN_DVFS_CLK_PX2,
};
static const unsigned gpio_x3_aud_px3_pins[] = {
TEGRA_PIN_GPIO_X3_AUD_PX3,
};
static const unsigned gpio_x4_aud_px4_pins[] = {
TEGRA_PIN_GPIO_X4_AUD_PX4,
};
static const unsigned gpio_x5_aud_px5_pins[] = {
TEGRA_PIN_GPIO_X5_AUD_PX5,
};
static const unsigned gpio_x6_aud_px6_pins[] = {
TEGRA_PIN_GPIO_X6_AUD_PX6,
};
static const unsigned gpio_x7_aud_px7_pins[] = {
TEGRA_PIN_GPIO_X7_AUD_PX7,
};
static const unsigned ulpi_clk_py0_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
};
static const unsigned ulpi_dir_py1_pins[] = {
TEGRA_PIN_ULPI_DIR_PY1,
};
static const unsigned ulpi_nxt_py2_pins[] = {
TEGRA_PIN_ULPI_NXT_PY2,
};
static const unsigned ulpi_stp_py3_pins[] = {
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned sdmmc1_dat3_py4_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
};
static const unsigned sdmmc1_dat2_py5_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PY5,
};
static const unsigned sdmmc1_dat1_py6_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PY6,
};
static const unsigned sdmmc1_dat0_py7_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PY7,
};
static const unsigned sdmmc1_clk_pz0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PZ0,
};
static const unsigned sdmmc1_cmd_pz1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned sys_clk_req_pz5_pins[] = {
TEGRA_PIN_SYS_CLK_REQ_PZ5,
};
static const unsigned pwr_i2c_scl_pz6_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PZ6,
};
static const unsigned pwr_i2c_sda_pz7_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned sdmmc4_dat0_paa0_pins[] = {
TEGRA_PIN_SDMMC4_DAT0_PAA0,
};
static const unsigned sdmmc4_dat1_paa1_pins[] = {
TEGRA_PIN_SDMMC4_DAT1_PAA1,
};
static const unsigned sdmmc4_dat2_paa2_pins[] = {
TEGRA_PIN_SDMMC4_DAT2_PAA2,
};
static const unsigned sdmmc4_dat3_paa3_pins[] = {
TEGRA_PIN_SDMMC4_DAT3_PAA3,
};
static const unsigned sdmmc4_dat4_paa4_pins[] = {
TEGRA_PIN_SDMMC4_DAT4_PAA4,
};
static const unsigned sdmmc4_dat5_paa5_pins[] = {
TEGRA_PIN_SDMMC4_DAT5_PAA5,
};
static const unsigned sdmmc4_dat6_paa6_pins[] = {
TEGRA_PIN_SDMMC4_DAT6_PAA6,
};
static const unsigned sdmmc4_dat7_paa7_pins[] = {
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned pbb0_pins[] = {
TEGRA_PIN_PBB0,
};
static const unsigned cam_i2c_scl_pbb1_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PBB1,
};
static const unsigned cam_i2c_sda_pbb2_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PBB2,
};
static const unsigned pbb3_pins[] = {
TEGRA_PIN_PBB3,
};
static const unsigned pbb4_pins[] = {
TEGRA_PIN_PBB4,
};
static const unsigned pbb5_pins[] = {
TEGRA_PIN_PBB5,
};
static const unsigned pbb6_pins[] = {
TEGRA_PIN_PBB6,
};
static const unsigned pbb7_pins[] = {
TEGRA_PIN_PBB7,
};
static const unsigned cam_mclk_pcc0_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned pcc1_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned pcc2_pins[] = {
TEGRA_PIN_PCC2,
};
static const unsigned sdmmc4_clk_pcc4_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
};
static const unsigned clk2_req_pcc5_pins[] = {
TEGRA_PIN_CLK2_REQ_PCC5,
};
static const unsigned clk3_out_pee0_pins[] = {
TEGRA_PIN_CLK3_OUT_PEE0,
};
static const unsigned clk3_req_pee1_pins[] = {
TEGRA_PIN_CLK3_REQ_PEE1,
};
static const unsigned clk1_req_pee2_pins[] = {
TEGRA_PIN_CLK1_REQ_PEE2,
};
static const unsigned hdmi_cec_pee3_pins[] = {
TEGRA_PIN_HDMI_CEC_PEE3,
};
static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
};
static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
};
static const unsigned core_pwr_req_pins[] = {
TEGRA_PIN_CORE_PWR_REQ,
};
static const unsigned cpu_pwr_req_pins[] = {
TEGRA_PIN_CPU_PWR_REQ,
};
static const unsigned pwr_int_n_pins[] = {
TEGRA_PIN_PWR_INT_N,
};
static const unsigned reset_out_n_pins[] = {
TEGRA_PIN_RESET_OUT_N,
};
static const unsigned owr_pins[] = {
TEGRA_PIN_OWR,
};
static const unsigned jtag_rtck_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned clk_32k_in_pins[] = {
TEGRA_PIN_CLK_32K_IN,
};
static const unsigned gmi_clk_lb_pins[] = {
TEGRA_PIN_GMI_CLK_LB,
};
static const unsigned drive_ao1_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
TEGRA_PIN_KB_ROW7_PR7,
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned drive_ao2_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
TEGRA_PIN_KB_COL7_PQ7,
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_SYS_CLK_REQ_PZ5,
TEGRA_PIN_CORE_PWR_REQ,
TEGRA_PIN_CPU_PWR_REQ,
TEGRA_PIN_RESET_OUT_N,
};
static const unsigned drive_at1_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
TEGRA_PIN_GMI_AD9_PH1,
TEGRA_PIN_GMI_AD10_PH2,
TEGRA_PIN_GMI_AD11_PH3,
TEGRA_PIN_GMI_AD12_PH4,
TEGRA_PIN_GMI_AD13_PH5,
TEGRA_PIN_GMI_AD14_PH6,
TEGRA_PIN_GMI_AD15_PH7,
TEGRA_PIN_GMI_IORDY_PI5,
TEGRA_PIN_GMI_CS7_N_PI6,
};
static const unsigned drive_at2_pins[] = {
TEGRA_PIN_GMI_AD0_PG0,
TEGRA_PIN_GMI_AD1_PG1,
TEGRA_PIN_GMI_AD2_PG2,
TEGRA_PIN_GMI_AD3_PG3,
TEGRA_PIN_GMI_AD4_PG4,
TEGRA_PIN_GMI_AD5_PG5,
TEGRA_PIN_GMI_AD6_PG6,
TEGRA_PIN_GMI_AD7_PG7,
TEGRA_PIN_GMI_WR_N_PI0,
TEGRA_PIN_GMI_OE_N_PI1,
TEGRA_PIN_GMI_CS6_N_PI3,
TEGRA_PIN_GMI_RST_N_PI4,
TEGRA_PIN_GMI_WAIT_PI7,
TEGRA_PIN_GMI_DQS_P_PJ3,
TEGRA_PIN_GMI_ADV_N_PK0,
TEGRA_PIN_GMI_CLK_PK1,
TEGRA_PIN_GMI_CS4_N_PK2,
TEGRA_PIN_GMI_CS2_N_PK3,
TEGRA_PIN_GMI_CS3_N_PK4,
};
static const unsigned drive_at3_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
TEGRA_PIN_GMI_CS0_N_PJ0,
};
static const unsigned drive_at4_pins[] = {
TEGRA_PIN_GMI_A17_PB0,
TEGRA_PIN_GMI_A18_PB1,
TEGRA_PIN_GMI_CS1_N_PJ2,
TEGRA_PIN_GMI_A16_PJ7,
TEGRA_PIN_GMI_A19_PK7,
};
static const unsigned drive_at5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned drive_cdev1_pins[] = {
TEGRA_PIN_CLK1_OUT_PW4,
TEGRA_PIN_CLK1_REQ_PEE2,
};
static const unsigned drive_cdev2_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
TEGRA_PIN_CLK2_REQ_PCC5,
TEGRA_PIN_SDMMC1_WP_N_PV3,
};
static const unsigned drive_dap1_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned drive_dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned drive_dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned drive_dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned drive_dbg_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
TEGRA_PIN_GEN1_I2C_SDA_PC5,
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
};
static const unsigned drive_sdio3_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
TEGRA_PIN_SDMMC3_CMD_PA7,
TEGRA_PIN_SDMMC3_DAT3_PB4,
TEGRA_PIN_SDMMC3_DAT2_PB5,
TEGRA_PIN_SDMMC3_DAT1_PB6,
TEGRA_PIN_SDMMC3_DAT0_PB7,
TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
};
static const unsigned drive_spi_pins[] = {
TEGRA_PIN_DVFS_PWM_PX0,
TEGRA_PIN_GPIO_X1_AUD_PX1,
TEGRA_PIN_DVFS_CLK_PX2,
TEGRA_PIN_GPIO_X3_AUD_PX3,
TEGRA_PIN_GPIO_X4_AUD_PX4,
TEGRA_PIN_GPIO_X5_AUD_PX5,
TEGRA_PIN_GPIO_X6_AUD_PX6,
TEGRA_PIN_GPIO_X7_AUD_PX7,
TEGRA_PIN_GPIO_W2_AUD_PW2,
TEGRA_PIN_GPIO_W3_AUD_PW3,
};
static const unsigned drive_uaa_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
TEGRA_PIN_ULPI_DATA1_PO2,
TEGRA_PIN_ULPI_DATA2_PO3,
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned drive_uab_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
TEGRA_PIN_ULPI_DATA4_PO5,
TEGRA_PIN_ULPI_DATA5_PO6,
TEGRA_PIN_ULPI_DATA6_PO7,
TEGRA_PIN_PV0,
TEGRA_PIN_PV1,
};
static const unsigned drive_uart2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
TEGRA_PIN_UART2_RXD_PC3,
TEGRA_PIN_UART2_CTS_N_PJ5,
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned drive_uart3_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
TEGRA_PIN_UART3_RTS_N_PC0,
TEGRA_PIN_UART3_TXD_PW6,
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned drive_sdio1_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
TEGRA_PIN_SDMMC1_DAT2_PY5,
TEGRA_PIN_SDMMC1_DAT1_PY6,
TEGRA_PIN_SDMMC1_DAT0_PY7,
TEGRA_PIN_SDMMC1_CLK_PZ0,
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned drive_ddc_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned drive_gma_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
TEGRA_PIN_SDMMC4_CMD_PT7,
TEGRA_PIN_SDMMC4_DAT0_PAA0,
TEGRA_PIN_SDMMC4_DAT1_PAA1,
TEGRA_PIN_SDMMC4_DAT2_PAA2,
TEGRA_PIN_SDMMC4_DAT3_PAA3,
TEGRA_PIN_SDMMC4_DAT4_PAA4,
TEGRA_PIN_SDMMC4_DAT5_PAA5,
TEGRA_PIN_SDMMC4_DAT6_PAA6,
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned drive_gme_pins[] = {
TEGRA_PIN_PBB0,
TEGRA_PIN_CAM_I2C_SCL_PBB1,
TEGRA_PIN_CAM_I2C_SDA_PBB2,
TEGRA_PIN_PBB3,
TEGRA_PIN_PCC2,
};
static const unsigned drive_gmf_pins[] = {
TEGRA_PIN_PBB4,
TEGRA_PIN_PBB5,
TEGRA_PIN_PBB6,
TEGRA_PIN_PBB7,
};
static const unsigned drive_gmg_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned drive_gmh_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned drive_owr_pins[] = {
TEGRA_PIN_SDMMC3_CD_N_PV2,
};
static const unsigned drive_uda_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
TEGRA_PIN_ULPI_DIR_PY1,
TEGRA_PIN_ULPI_NXT_PY2,
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned drive_dev3_pins[] = {
};
static const unsigned drive_cec_pins[] = {
};
static const unsigned drive_at6_pins[] = {
};
static const unsigned drive_dap5_pins[] = {
};
static const unsigned drive_usb_vbus_en_pins[] = {
};
static const unsigned drive_ao3_pins[] = {
};
static const unsigned drive_hv0_pins[] = {
};
static const unsigned drive_sdio4_pins[] = {
};
static const unsigned drive_ao0_pins[] = {
};
enum tegra_mux {
TEGRA_MUX_BLINK,
TEGRA_MUX_CEC,
TEGRA_MUX_CLDVFS,
TEGRA_MUX_CLK,
TEGRA_MUX_CLK12,
TEGRA_MUX_CPU,
TEGRA_MUX_DAP,
TEGRA_MUX_DAP1,
TEGRA_MUX_DAP2,
TEGRA_MUX_DEV3,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYA_ALT,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DTV,
TEGRA_MUX_EMC_DLL,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_IRDA,
TEGRA_MUX_KBC,
TEGRA_MUX_NAND,
TEGRA_MUX_NAND_ALT,
TEGRA_MUX_OWR,
TEGRA_MUX_PMI,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_PWRON,
TEGRA_MUX_RESET_OUT_N,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_RSVD4,
TEGRA_MUX_RTCK,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_SDMMC2,
TEGRA_MUX_SDMMC3,
TEGRA_MUX_SDMMC4,
TEGRA_MUX_SOC,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYSCLK,
TEGRA_MUX_TRACE,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_ULPI,
TEGRA_MUX_USB,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_VI,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT3,
};
#define FUNCTION(fname) #fname
static const char * const tegra114_functions[] = {
FUNCTION(blink),
FUNCTION(cec),
FUNCTION(cldvfs),
FUNCTION(clk),
FUNCTION(clk12),
FUNCTION(cpu),
FUNCTION(dap),
FUNCTION(dap1),
FUNCTION(dap2),
FUNCTION(dev3),
FUNCTION(displaya),
FUNCTION(displaya_alt),
FUNCTION(displayb),
FUNCTION(dtv),
FUNCTION(emc_dll),
FUNCTION(extperiph1),
FUNCTION(extperiph2),
FUNCTION(extperiph3),
FUNCTION(gmi),
FUNCTION(gmi_alt),
FUNCTION(hda),
FUNCTION(hsi),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2c4),
FUNCTION(i2cpwr),
FUNCTION(i2s0),
FUNCTION(i2s1),
FUNCTION(i2s2),
FUNCTION(i2s3),
FUNCTION(i2s4),
FUNCTION(irda),
FUNCTION(kbc),
FUNCTION(nand),
FUNCTION(nand_alt),
FUNCTION(owr),
FUNCTION(pmi),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(pwron),
FUNCTION(reset_out_n),
FUNCTION(rsvd1),
FUNCTION(rsvd2),
FUNCTION(rsvd3),
FUNCTION(rsvd4),
FUNCTION(rtck),
FUNCTION(sdmmc1),
FUNCTION(sdmmc2),
FUNCTION(sdmmc3),
FUNCTION(sdmmc4),
FUNCTION(soc),
FUNCTION(spdif),
FUNCTION(spi1),
FUNCTION(spi2),
FUNCTION(spi3),
FUNCTION(spi4),
FUNCTION(spi5),
FUNCTION(spi6),
FUNCTION(sysclk),
FUNCTION(trace),
FUNCTION(uarta),
FUNCTION(uartb),
FUNCTION(uartc),
FUNCTION(uartd),
FUNCTION(ulpi),
FUNCTION(usb),
FUNCTION(vgp1),
FUNCTION(vgp2),
FUNCTION(vgp3),
FUNCTION(vgp4),
FUNCTION(vgp5),
FUNCTION(vgp6),
FUNCTION(vi),
FUNCTION(vi_alt1),
FUNCTION(vi_alt3),
};
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
#define PINGROUP_BIT_Y(b) (b)
#define PINGROUP_BIT_N(b) (-1)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
.mux_reg = PINGROUP_REG(r), \
.mux_bank = 1, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG(r), \
.pupd_bank = 1, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG(r), \
.tri_bank = 1, \
.tri_bit = 4, \
.einput_bit = 5, \
.odrain_bit = PINGROUP_BIT_##od(6), \
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
.drv_reg = -1, \
.parked_bitmask = 0, \
}
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
slwf_b, slwf_w, drvtype) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \
.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
.parked_bitmask = 0, \
}
static const struct tegra_pingroup tegra114_groups[] = {
/* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3038, N, N, N),
PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x303c, N, N, N),
PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, 0x316c, N, N, N),
PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, 0x3170, N, N, N),
PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, 0x3174, N, N, N),
PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, 0x3178, N, N, N),
PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, 0x317c, N, N, N),
PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, 0x3184, N, N, N),
PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, 0x3188, N, N, N),
PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, 0x318c, N, N, N),
PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, 0x3194, N, N, N),
PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, 0x3198, N, N, N),
PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, 0x319c, N, N, N),
PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, 0x31a8, N, N, N),
PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, 0x31ac, N, N, N),
PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, 0x31b0, N, N, N),
PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, 0x31b4, N, N, N),
PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N, N),
PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, 0x31c4, N, N, N),
PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, 0x31c8, N, N, N),
PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, 0x31cc, N, N, N),
PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, 0x31d0, N, N, N),
PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, 0x31d4, N, N, N),
PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, 0x31d8, N, N, N),
PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, 0x31dc, N, N, N),
PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, 0x31e0, N, N, N),
PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, 0x31e4, N, N, N),
PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, 0x31e8, N, N, N),
PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, 0x31ec, N, N, N),
PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N, N),
PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N, N),
PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N, N),
PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N, N),
PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N, N),
PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, 0x3204, N, N, N),
PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, 0x3208, N, N, N),
PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, 0x320c, N, N, N),
PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, 0x3214, N, N, N),
PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, 0x3218, N, N, N),
PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, 0x321c, N, N, N),
PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, 0x3220, N, N, N),
PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, 0x3224, N, N, N),
PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, 0x3228, N, N, N),
PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, 0x322c, N, N, N),
PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, 0x3230, N, N, N),
PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, 0x3234, N, N, N),
PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, 0x3238, N, N, N),
PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, 0x323c, N, N, N),
PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, 0x3240, N, N, N),
PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, 0x3244, N, N, N),
PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, 0x3248, N, N, N),
PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N, N),
PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, 0x3274, N, Y, N),
PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, 0x3284, N, N, N),
PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, 0x3288, N, N, N),
PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, 0x328c, N, N, N),
PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, 0x3290, Y, N, N),
PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, 0x3294, Y, N, N),
PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, 0x3298, N, N, N),
PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, 0x329c, N, N, N),
PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, 0x32a0, N, N, N),
PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, 0x32a4, N, N, N),
PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, 0x32a8, N, N, N),
PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N, N),
PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32c8, N, N, N),
PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32cc, N, N, N),
PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, 0x32d0, N, N, N),
PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, 0x32fc, N, N, N),
PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, 0x3300, N, N, N),
PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, 0x3310, N, N, N),
PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, 0x3314, N, N, N),
PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, 0x3318, N, N, N),
PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N, N),
PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, 0x3340, N, N, N),
PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, 0x3348, N, N, N),
PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, 0x3350, N, N, N),
PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, 0x3354, N, N, N),
PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, 0x3358, N, N, N),
PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, 0x335c, N, N, N),
PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, 0x3360, N, N, N),
PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, 0x3364, N, N, N),
PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, 0x3368, N, N, N),
PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, 0x336c, N, N, N),
PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, 0x3370, N, N, N),
PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, 0x3374, N, N, N),
PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, 0x3378, N, N, N),
PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, 0x3380, N, N, N),
PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, 0x33e0, Y, N, N),
PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
PINGROUP(gmi_clk_lb, SDMMC2, NAND, GMI, RSVD4, 0x3404, N, N, N),
PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(at1, 0x870, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at2, 0x874, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at3, 0x878, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at4, 0x87c, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gma, 0x900, 2, 3, -1, 14, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, Y),
DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao3, 0x9a0, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(hv0, 0x9a4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(sdio4, 0x9a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao0, 0x9ac, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
};
static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra114-gpio",
.pins = tegra114_pins,
.npins = ARRAY_SIZE(tegra114_pins),
.functions = tegra114_functions,
.nfunctions = ARRAY_SIZE(tegra114_functions),
.groups = tegra114_groups,
.ngroups = ARRAY_SIZE(tegra114_groups),
.hsm_in_mux = false,
.schmitt_in_mux = false,
.drvtype_in_mux = false,
};
static int tegra114_pinctrl_probe(struct platform_device *pdev)
{
return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
}
static const struct of_device_id tegra114_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra114-pinmux", },
{ },
};
static struct platform_driver tegra114_pinctrl_driver = {
.driver = {
.name = "tegra114-pinctrl",
.of_match_table = tegra114_pinctrl_of_match,
},
.probe = tegra114_pinctrl_probe,
};
static int __init tegra114_pinctrl_init(void)
{
return platform_driver_register(&tegra114_pinctrl_driver);
}
arch_initcall(tegra114_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra114.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for the NVIDIA Tegra210 pinmux
*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
#define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
#define TEGRA_PIN_PA6 _GPIO(6)
#define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
#define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
#define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
#define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
#define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
#define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
#define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
#define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
#define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
#define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
#define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
#define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
#define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
#define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
#define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
#define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
#define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
#define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
#define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
#define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
#define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
#define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
#define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
#define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
#define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
#define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
#define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
#define TEGRA_PIN_PE6 _GPIO(38)
#define TEGRA_PIN_PE7 _GPIO(39)
#define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
#define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
#define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
#define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
#define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
#define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
#define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
#define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
#define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
#define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
#define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
#define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
#define TEGRA_PIN_PH6 _GPIO(62)
#define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
#define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
#define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
#define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
#define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
#define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
#define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
#define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
#define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
#define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
#define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
#define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
#define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
#define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
#define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
#define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
#define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
#define TEGRA_PIN_PK0 _GPIO(80)
#define TEGRA_PIN_PK1 _GPIO(81)
#define TEGRA_PIN_PK2 _GPIO(82)
#define TEGRA_PIN_PK3 _GPIO(83)
#define TEGRA_PIN_PK4 _GPIO(84)
#define TEGRA_PIN_PK5 _GPIO(85)
#define TEGRA_PIN_PK6 _GPIO(86)
#define TEGRA_PIN_PK7 _GPIO(87)
#define TEGRA_PIN_PL0 _GPIO(88)
#define TEGRA_PIN_PL1 _GPIO(89)
#define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
#define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
#define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
#define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
#define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
#define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
#define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
#define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
#define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
#define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
#define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
#define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
#define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
#define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
#define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
#define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
#define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
#define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
#define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
#define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
#define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
#define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
#define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
#define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
#define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
#define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
#define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
#define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
#define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
#define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
#define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
#define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
#define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
#define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
#define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
#define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
#define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
#define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
#define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
#define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
#define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
#define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
#define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
#define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
#define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
#define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
#define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
#define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
#define TEGRA_PIN_PZ0 _GPIO(200)
#define TEGRA_PIN_PZ1 _GPIO(201)
#define TEGRA_PIN_PZ2 _GPIO(202)
#define TEGRA_PIN_PZ3 _GPIO(203)
#define TEGRA_PIN_PZ4 _GPIO(204)
#define TEGRA_PIN_PZ5 _GPIO(205)
#define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
#define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
#define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
#define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
#define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
#define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
#define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
#define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
#define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
#define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
#define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
#define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
#define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
#define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
#define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
#define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
#define TEGRA_PIN_PCC7 _GPIO(231)
#define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
#define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
#define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
#define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
#define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
#define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
#define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
/* Non-GPIO pins */
#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
#define TEGRA_PIN_PWR_INT_N _PIN(2)
#define TEGRA_PIN_CLK_32K_IN _PIN(3)
#define TEGRA_PIN_JTAG_RTCK _PIN(4)
#define TEGRA_PIN_BATT_BCL _PIN(5)
#define TEGRA_PIN_CLK_REQ _PIN(6)
#define TEGRA_PIN_SHUTDOWN _PIN(7)
static const struct pinctrl_pin_desc tegra210_pins[] = {
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
};
static const unsigned pex_l0_rst_n_pa0_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PA0,
};
static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
};
static const unsigned pex_wake_n_pa2_pins[] = {
TEGRA_PIN_PEX_WAKE_N_PA2,
};
static const unsigned pex_l1_rst_n_pa3_pins[] = {
TEGRA_PIN_PEX_L1_RST_N_PA3,
};
static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
};
static const unsigned sata_led_active_pa5_pins[] = {
TEGRA_PIN_SATA_LED_ACTIVE_PA5,
};
static const unsigned pa6_pins[] = {
TEGRA_PIN_PA6,
};
static const unsigned dap1_fs_pb0_pins[] = {
TEGRA_PIN_DAP1_FS_PB0,
};
static const unsigned dap1_din_pb1_pins[] = {
TEGRA_PIN_DAP1_DIN_PB1,
};
static const unsigned dap1_dout_pb2_pins[] = {
TEGRA_PIN_DAP1_DOUT_PB2,
};
static const unsigned dap1_sclk_pb3_pins[] = {
TEGRA_PIN_DAP1_SCLK_PB3,
};
static const unsigned spi2_mosi_pb4_pins[] = {
TEGRA_PIN_SPI2_MOSI_PB4,
};
static const unsigned spi2_miso_pb5_pins[] = {
TEGRA_PIN_SPI2_MISO_PB5,
};
static const unsigned spi2_sck_pb6_pins[] = {
TEGRA_PIN_SPI2_SCK_PB6,
};
static const unsigned spi2_cs0_pb7_pins[] = {
TEGRA_PIN_SPI2_CS0_PB7,
};
static const unsigned spi1_mosi_pc0_pins[] = {
TEGRA_PIN_SPI1_MOSI_PC0,
};
static const unsigned spi1_miso_pc1_pins[] = {
TEGRA_PIN_SPI1_MISO_PC1,
};
static const unsigned spi1_sck_pc2_pins[] = {
TEGRA_PIN_SPI1_SCK_PC2,
};
static const unsigned spi1_cs0_pc3_pins[] = {
TEGRA_PIN_SPI1_CS0_PC3,
};
static const unsigned spi1_cs1_pc4_pins[] = {
TEGRA_PIN_SPI1_CS1_PC4,
};
static const unsigned spi4_sck_pc5_pins[] = {
TEGRA_PIN_SPI4_SCK_PC5,
};
static const unsigned spi4_cs0_pc6_pins[] = {
TEGRA_PIN_SPI4_CS0_PC6,
};
static const unsigned spi4_mosi_pc7_pins[] = {
TEGRA_PIN_SPI4_MOSI_PC7,
};
static const unsigned spi4_miso_pd0_pins[] = {
TEGRA_PIN_SPI4_MISO_PD0,
};
static const unsigned uart3_tx_pd1_pins[] = {
TEGRA_PIN_UART3_TX_PD1,
};
static const unsigned uart3_rx_pd2_pins[] = {
TEGRA_PIN_UART3_RX_PD2,
};
static const unsigned uart3_rts_pd3_pins[] = {
TEGRA_PIN_UART3_RTS_PD3,
};
static const unsigned uart3_cts_pd4_pins[] = {
TEGRA_PIN_UART3_CTS_PD4,
};
static const unsigned dmic1_clk_pe0_pins[] = {
TEGRA_PIN_DMIC1_CLK_PE0,
};
static const unsigned dmic1_dat_pe1_pins[] = {
TEGRA_PIN_DMIC1_DAT_PE1,
};
static const unsigned dmic2_clk_pe2_pins[] = {
TEGRA_PIN_DMIC2_CLK_PE2,
};
static const unsigned dmic2_dat_pe3_pins[] = {
TEGRA_PIN_DMIC2_DAT_PE3,
};
static const unsigned dmic3_clk_pe4_pins[] = {
TEGRA_PIN_DMIC3_CLK_PE4,
};
static const unsigned dmic3_dat_pe5_pins[] = {
TEGRA_PIN_DMIC3_DAT_PE5,
};
static const unsigned pe6_pins[] = {
TEGRA_PIN_PE6,
};
static const unsigned pe7_pins[] = {
TEGRA_PIN_PE7,
};
static const unsigned gen3_i2c_scl_pf0_pins[] = {
TEGRA_PIN_GEN3_I2C_SCL_PF0,
};
static const unsigned gen3_i2c_sda_pf1_pins[] = {
TEGRA_PIN_GEN3_I2C_SDA_PF1,
};
static const unsigned uart2_tx_pg0_pins[] = {
TEGRA_PIN_UART2_TX_PG0,
};
static const unsigned uart2_rx_pg1_pins[] = {
TEGRA_PIN_UART2_RX_PG1,
};
static const unsigned uart2_rts_pg2_pins[] = {
TEGRA_PIN_UART2_RTS_PG2,
};
static const unsigned uart2_cts_pg3_pins[] = {
TEGRA_PIN_UART2_CTS_PG3,
};
static const unsigned wifi_en_ph0_pins[] = {
TEGRA_PIN_WIFI_EN_PH0,
};
static const unsigned wifi_rst_ph1_pins[] = {
TEGRA_PIN_WIFI_RST_PH1,
};
static const unsigned wifi_wake_ap_ph2_pins[] = {
TEGRA_PIN_WIFI_WAKE_AP_PH2,
};
static const unsigned ap_wake_bt_ph3_pins[] = {
TEGRA_PIN_AP_WAKE_BT_PH3,
};
static const unsigned bt_rst_ph4_pins[] = {
TEGRA_PIN_BT_RST_PH4,
};
static const unsigned bt_wake_ap_ph5_pins[] = {
TEGRA_PIN_BT_WAKE_AP_PH5,
};
static const unsigned ph6_pins[] = {
TEGRA_PIN_PH6,
};
static const unsigned ap_wake_nfc_ph7_pins[] = {
TEGRA_PIN_AP_WAKE_NFC_PH7,
};
static const unsigned nfc_en_pi0_pins[] = {
TEGRA_PIN_NFC_EN_PI0,
};
static const unsigned nfc_int_pi1_pins[] = {
TEGRA_PIN_NFC_INT_PI1,
};
static const unsigned gps_en_pi2_pins[] = {
TEGRA_PIN_GPS_EN_PI2,
};
static const unsigned gps_rst_pi3_pins[] = {
TEGRA_PIN_GPS_RST_PI3,
};
static const unsigned uart4_tx_pi4_pins[] = {
TEGRA_PIN_UART4_TX_PI4,
};
static const unsigned uart4_rx_pi5_pins[] = {
TEGRA_PIN_UART4_RX_PI5,
};
static const unsigned uart4_rts_pi6_pins[] = {
TEGRA_PIN_UART4_RTS_PI6,
};
static const unsigned uart4_cts_pi7_pins[] = {
TEGRA_PIN_UART4_CTS_PI7,
};
static const unsigned gen1_i2c_sda_pj0_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PJ0,
};
static const unsigned gen1_i2c_scl_pj1_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PJ1,
};
static const unsigned gen2_i2c_scl_pj2_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PJ2,
};
static const unsigned gen2_i2c_sda_pj3_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PJ3,
};
static const unsigned dap4_fs_pj4_pins[] = {
TEGRA_PIN_DAP4_FS_PJ4,
};
static const unsigned dap4_din_pj5_pins[] = {
TEGRA_PIN_DAP4_DIN_PJ5,
};
static const unsigned dap4_dout_pj6_pins[] = {
TEGRA_PIN_DAP4_DOUT_PJ6,
};
static const unsigned dap4_sclk_pj7_pins[] = {
TEGRA_PIN_DAP4_SCLK_PJ7,
};
static const unsigned pk0_pins[] = {
TEGRA_PIN_PK0,
};
static const unsigned pk1_pins[] = {
TEGRA_PIN_PK1,
};
static const unsigned pk2_pins[] = {
TEGRA_PIN_PK2,
};
static const unsigned pk3_pins[] = {
TEGRA_PIN_PK3,
};
static const unsigned pk4_pins[] = {
TEGRA_PIN_PK4,
};
static const unsigned pk5_pins[] = {
TEGRA_PIN_PK5,
};
static const unsigned pk6_pins[] = {
TEGRA_PIN_PK6,
};
static const unsigned pk7_pins[] = {
TEGRA_PIN_PK7,
};
static const unsigned pl0_pins[] = {
TEGRA_PIN_PL0,
};
static const unsigned pl1_pins[] = {
TEGRA_PIN_PL1,
};
static const unsigned sdmmc1_clk_pm0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PM0,
};
static const unsigned sdmmc1_cmd_pm1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PM1,
};
static const unsigned sdmmc1_dat3_pm2_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PM2,
};
static const unsigned sdmmc1_dat2_pm3_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PM3,
};
static const unsigned sdmmc1_dat1_pm4_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PM4,
};
static const unsigned sdmmc1_dat0_pm5_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PM5,
};
static const unsigned sdmmc3_clk_pp0_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PP0,
};
static const unsigned sdmmc3_cmd_pp1_pins[] = {
TEGRA_PIN_SDMMC3_CMD_PP1,
};
static const unsigned sdmmc3_dat3_pp2_pins[] = {
TEGRA_PIN_SDMMC3_DAT3_PP2,
};
static const unsigned sdmmc3_dat2_pp3_pins[] = {
TEGRA_PIN_SDMMC3_DAT2_PP3,
};
static const unsigned sdmmc3_dat1_pp4_pins[] = {
TEGRA_PIN_SDMMC3_DAT1_PP4,
};
static const unsigned sdmmc3_dat0_pp5_pins[] = {
TEGRA_PIN_SDMMC3_DAT0_PP5,
};
static const unsigned cam1_mclk_ps0_pins[] = {
TEGRA_PIN_CAM1_MCLK_PS0,
};
static const unsigned cam2_mclk_ps1_pins[] = {
TEGRA_PIN_CAM2_MCLK_PS1,
};
static const unsigned cam_i2c_scl_ps2_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PS2,
};
static const unsigned cam_i2c_sda_ps3_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PS3,
};
static const unsigned cam_rst_ps4_pins[] = {
TEGRA_PIN_CAM_RST_PS4,
};
static const unsigned cam_af_en_ps5_pins[] = {
TEGRA_PIN_CAM_AF_EN_PS5,
};
static const unsigned cam_flash_en_ps6_pins[] = {
TEGRA_PIN_CAM_FLASH_EN_PS6,
};
static const unsigned cam1_pwdn_ps7_pins[] = {
TEGRA_PIN_CAM1_PWDN_PS7,
};
static const unsigned cam2_pwdn_pt0_pins[] = {
TEGRA_PIN_CAM2_PWDN_PT0,
};
static const unsigned cam1_strobe_pt1_pins[] = {
TEGRA_PIN_CAM1_STROBE_PT1,
};
static const unsigned uart1_tx_pu0_pins[] = {
TEGRA_PIN_UART1_TX_PU0,
};
static const unsigned uart1_rx_pu1_pins[] = {
TEGRA_PIN_UART1_RX_PU1,
};
static const unsigned uart1_rts_pu2_pins[] = {
TEGRA_PIN_UART1_RTS_PU2,
};
static const unsigned uart1_cts_pu3_pins[] = {
TEGRA_PIN_UART1_CTS_PU3,
};
static const unsigned lcd_bl_pwm_pv0_pins[] = {
TEGRA_PIN_LCD_BL_PWM_PV0,
};
static const unsigned lcd_bl_en_pv1_pins[] = {
TEGRA_PIN_LCD_BL_EN_PV1,
};
static const unsigned lcd_rst_pv2_pins[] = {
TEGRA_PIN_LCD_RST_PV2,
};
static const unsigned lcd_gpio1_pv3_pins[] = {
TEGRA_PIN_LCD_GPIO1_PV3,
};
static const unsigned lcd_gpio2_pv4_pins[] = {
TEGRA_PIN_LCD_GPIO2_PV4,
};
static const unsigned ap_ready_pv5_pins[] = {
TEGRA_PIN_AP_READY_PV5,
};
static const unsigned touch_rst_pv6_pins[] = {
TEGRA_PIN_TOUCH_RST_PV6,
};
static const unsigned touch_clk_pv7_pins[] = {
TEGRA_PIN_TOUCH_CLK_PV7,
};
static const unsigned modem_wake_ap_px0_pins[] = {
TEGRA_PIN_MODEM_WAKE_AP_PX0,
};
static const unsigned touch_int_px1_pins[] = {
TEGRA_PIN_TOUCH_INT_PX1,
};
static const unsigned motion_int_px2_pins[] = {
TEGRA_PIN_MOTION_INT_PX2,
};
static const unsigned als_prox_int_px3_pins[] = {
TEGRA_PIN_ALS_PROX_INT_PX3,
};
static const unsigned temp_alert_px4_pins[] = {
TEGRA_PIN_TEMP_ALERT_PX4,
};
static const unsigned button_power_on_px5_pins[] = {
TEGRA_PIN_BUTTON_POWER_ON_PX5,
};
static const unsigned button_vol_up_px6_pins[] = {
TEGRA_PIN_BUTTON_VOL_UP_PX6,
};
static const unsigned button_vol_down_px7_pins[] = {
TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
};
static const unsigned button_slide_sw_py0_pins[] = {
TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
};
static const unsigned button_home_py1_pins[] = {
TEGRA_PIN_BUTTON_HOME_PY1,
};
static const unsigned lcd_te_py2_pins[] = {
TEGRA_PIN_LCD_TE_PY2,
};
static const unsigned pwr_i2c_scl_py3_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PY3,
};
static const unsigned pwr_i2c_sda_py4_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PY4,
};
static const unsigned clk_32k_out_py5_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PY5,
};
static const unsigned pz0_pins[] = {
TEGRA_PIN_PZ0,
};
static const unsigned pz1_pins[] = {
TEGRA_PIN_PZ1,
};
static const unsigned pz2_pins[] = {
TEGRA_PIN_PZ2,
};
static const unsigned pz3_pins[] = {
TEGRA_PIN_PZ3,
};
static const unsigned pz4_pins[] = {
TEGRA_PIN_PZ4,
};
static const unsigned pz5_pins[] = {
TEGRA_PIN_PZ5,
};
static const unsigned dap2_fs_paa0_pins[] = {
TEGRA_PIN_DAP2_FS_PAA0,
};
static const unsigned dap2_sclk_paa1_pins[] = {
TEGRA_PIN_DAP2_SCLK_PAA1,
};
static const unsigned dap2_din_paa2_pins[] = {
TEGRA_PIN_DAP2_DIN_PAA2,
};
static const unsigned dap2_dout_paa3_pins[] = {
TEGRA_PIN_DAP2_DOUT_PAA3,
};
static const unsigned aud_mclk_pbb0_pins[] = {
TEGRA_PIN_AUD_MCLK_PBB0,
};
static const unsigned dvfs_pwm_pbb1_pins[] = {
TEGRA_PIN_DVFS_PWM_PBB1,
};
static const unsigned dvfs_clk_pbb2_pins[] = {
TEGRA_PIN_DVFS_CLK_PBB2,
};
static const unsigned gpio_x1_aud_pbb3_pins[] = {
TEGRA_PIN_GPIO_X1_AUD_PBB3,
};
static const unsigned gpio_x3_aud_pbb4_pins[] = {
TEGRA_PIN_GPIO_X3_AUD_PBB4,
};
static const unsigned hdmi_cec_pcc0_pins[] = {
TEGRA_PIN_HDMI_CEC_PCC0,
};
static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
};
static const unsigned spdif_out_pcc2_pins[] = {
TEGRA_PIN_SPDIF_OUT_PCC2,
};
static const unsigned spdif_in_pcc3_pins[] = {
TEGRA_PIN_SPDIF_IN_PCC3,
};
static const unsigned usb_vbus_en0_pcc4_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PCC4,
};
static const unsigned usb_vbus_en1_pcc5_pins[] = {
TEGRA_PIN_USB_VBUS_EN1_PCC5,
};
static const unsigned dp_hpd0_pcc6_pins[] = {
TEGRA_PIN_DP_HPD0_PCC6,
};
static const unsigned pcc7_pins[] = {
TEGRA_PIN_PCC7,
};
static const unsigned spi2_cs1_pdd0_pins[] = {
TEGRA_PIN_SPI2_CS1_PDD0,
};
static const unsigned qspi_sck_pee0_pins[] = {
TEGRA_PIN_QSPI_SCK_PEE0,
};
static const unsigned qspi_cs_n_pee1_pins[] = {
TEGRA_PIN_QSPI_CS_N_PEE1,
};
static const unsigned qspi_io0_pee2_pins[] = {
TEGRA_PIN_QSPI_IO0_PEE2,
};
static const unsigned qspi_io1_pee3_pins[] = {
TEGRA_PIN_QSPI_IO1_PEE3,
};
static const unsigned qspi_io2_pee4_pins[] = {
TEGRA_PIN_QSPI_IO2_PEE4,
};
static const unsigned qspi_io3_pee5_pins[] = {
TEGRA_PIN_QSPI_IO3_PEE5,
};
static const unsigned core_pwr_req_pins[] = {
TEGRA_PIN_CORE_PWR_REQ,
};
static const unsigned cpu_pwr_req_pins[] = {
TEGRA_PIN_CPU_PWR_REQ,
};
static const unsigned pwr_int_n_pins[] = {
TEGRA_PIN_PWR_INT_N,
};
static const unsigned clk_32k_in_pins[] = {
TEGRA_PIN_CLK_32K_IN,
};
static const unsigned jtag_rtck_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned batt_bcl_pins[] = {
TEGRA_PIN_BATT_BCL,
};
static const unsigned clk_req_pins[] = {
TEGRA_PIN_CLK_REQ,
};
static const unsigned shutdown_pins[] = {
TEGRA_PIN_SHUTDOWN,
};
static const unsigned drive_pa6_pins[] = {
TEGRA_PIN_PA6,
};
static const unsigned drive_pcc7_pins[] = {
TEGRA_PIN_PCC7,
};
static const unsigned drive_pe6_pins[] = {
TEGRA_PIN_PE6,
};
static const unsigned drive_pe7_pins[] = {
TEGRA_PIN_PE7,
};
static const unsigned drive_ph6_pins[] = {
TEGRA_PIN_PH6,
};
static const unsigned drive_pk0_pins[] = {
TEGRA_PIN_PK0,
};
static const unsigned drive_pk1_pins[] = {
TEGRA_PIN_PK1,
};
static const unsigned drive_pk2_pins[] = {
TEGRA_PIN_PK2,
};
static const unsigned drive_pk3_pins[] = {
TEGRA_PIN_PK3,
};
static const unsigned drive_pk4_pins[] = {
TEGRA_PIN_PK4,
};
static const unsigned drive_pk5_pins[] = {
TEGRA_PIN_PK5,
};
static const unsigned drive_pk6_pins[] = {
TEGRA_PIN_PK6,
};
static const unsigned drive_pk7_pins[] = {
TEGRA_PIN_PK7,
};
static const unsigned drive_pl0_pins[] = {
TEGRA_PIN_PL0,
};
static const unsigned drive_pl1_pins[] = {
TEGRA_PIN_PL1,
};
static const unsigned drive_pz0_pins[] = {
TEGRA_PIN_PZ0,
};
static const unsigned drive_pz1_pins[] = {
TEGRA_PIN_PZ1,
};
static const unsigned drive_pz2_pins[] = {
TEGRA_PIN_PZ2,
};
static const unsigned drive_pz3_pins[] = {
TEGRA_PIN_PZ3,
};
static const unsigned drive_pz4_pins[] = {
TEGRA_PIN_PZ4,
};
static const unsigned drive_pz5_pins[] = {
TEGRA_PIN_PZ5,
};
static const unsigned drive_sdmmc1_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PM0,
TEGRA_PIN_SDMMC1_CMD_PM1,
TEGRA_PIN_SDMMC1_DAT3_PM2,
TEGRA_PIN_SDMMC1_DAT2_PM3,
TEGRA_PIN_SDMMC1_DAT1_PM4,
TEGRA_PIN_SDMMC1_DAT0_PM5,
};
static const unsigned drive_sdmmc2_pins[] = {
};
static const unsigned drive_sdmmc3_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PP0,
TEGRA_PIN_SDMMC3_CMD_PP1,
TEGRA_PIN_SDMMC3_DAT3_PP2,
TEGRA_PIN_SDMMC3_DAT2_PP3,
TEGRA_PIN_SDMMC3_DAT1_PP4,
TEGRA_PIN_SDMMC3_DAT0_PP5,
};
static const unsigned drive_sdmmc4_pins[] = {
};
enum tegra_mux {
TEGRA_MUX_AUD,
TEGRA_MUX_BCL,
TEGRA_MUX_BLINK,
TEGRA_MUX_CCLA,
TEGRA_MUX_CEC,
TEGRA_MUX_CLDVFS,
TEGRA_MUX_CLK,
TEGRA_MUX_CORE,
TEGRA_MUX_CPU,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DMIC1,
TEGRA_MUX_DMIC2,
TEGRA_MUX_DMIC3,
TEGRA_MUX_DP,
TEGRA_MUX_DTV,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_I2CPMU,
TEGRA_MUX_I2CVI,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4A,
TEGRA_MUX_I2S4B,
TEGRA_MUX_I2S5A,
TEGRA_MUX_I2S5B,
TEGRA_MUX_IQC0,
TEGRA_MUX_IQC1,
TEGRA_MUX_JTAG,
TEGRA_MUX_PE,
TEGRA_MUX_PE0,
TEGRA_MUX_PE1,
TEGRA_MUX_PMI,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_QSPI,
TEGRA_MUX_RSVD0,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_SATA,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_SDMMC3,
TEGRA_MUX_SHUTDOWN,
TEGRA_MUX_SOC,
TEGRA_MUX_SOR0,
TEGRA_MUX_SOR1,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_SYS,
TEGRA_MUX_TOUCH,
TEGRA_MUX_UART,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_USB,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_VIMCLK,
TEGRA_MUX_VIMCLK2,
};
#define FUNCTION(fname) #fname
static const char * const tegra210_functions[] = {
FUNCTION(aud),
FUNCTION(bcl),
FUNCTION(blink),
FUNCTION(ccla),
FUNCTION(cec),
FUNCTION(cldvfs),
FUNCTION(clk),
FUNCTION(core),
FUNCTION(cpu),
FUNCTION(displaya),
FUNCTION(displayb),
FUNCTION(dmic1),
FUNCTION(dmic2),
FUNCTION(dmic3),
FUNCTION(dp),
FUNCTION(dtv),
FUNCTION(extperiph3),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2cpmu),
FUNCTION(i2cvi),
FUNCTION(i2s1),
FUNCTION(i2s2),
FUNCTION(i2s3),
FUNCTION(i2s4a),
FUNCTION(i2s4b),
FUNCTION(i2s5a),
FUNCTION(i2s5b),
FUNCTION(iqc0),
FUNCTION(iqc1),
FUNCTION(jtag),
FUNCTION(pe),
FUNCTION(pe0),
FUNCTION(pe1),
FUNCTION(pmi),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(qspi),
FUNCTION(rsvd0),
FUNCTION(rsvd1),
FUNCTION(rsvd2),
FUNCTION(rsvd3),
FUNCTION(sata),
FUNCTION(sdmmc1),
FUNCTION(sdmmc3),
FUNCTION(shutdown),
FUNCTION(soc),
FUNCTION(sor0),
FUNCTION(sor1),
FUNCTION(spdif),
FUNCTION(spi1),
FUNCTION(spi2),
FUNCTION(spi3),
FUNCTION(spi4),
FUNCTION(sys),
FUNCTION(touch),
FUNCTION(uart),
FUNCTION(uarta),
FUNCTION(uartb),
FUNCTION(uartc),
FUNCTION(uartd),
FUNCTION(usb),
FUNCTION(vgp1),
FUNCTION(vgp2),
FUNCTION(vgp3),
FUNCTION(vgp4),
FUNCTION(vgp5),
FUNCTION(vgp6),
FUNCTION(vimclk),
FUNCTION(vimclk2),
};
#define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
#define PINGROUP_BIT_Y(b) (b)
#define PINGROUP_BIT_N(b) (-1)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
lpdr, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b,\
slwr_w, slwf_b, slwf_w) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
.mux_reg = PINGROUP_REG(r), \
.mux_bank = 1, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG(r), \
.pupd_bank = 1, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG(r), \
.tri_bank = 1, \
.tri_bit = 4, \
.einput_bit = 6, \
.odrain_bit = 11, \
.lock_bit = 7, \
.ioreset_bit = -1, \
.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
.hsm_bit = PINGROUP_BIT_##hsm(9), \
.schmitt_bit = 12, \
.drvtype_bit = PINGROUP_BIT_##drvtype(13), \
.drv_reg = DRV_PINGROUP_REG(rdrv), \
.drv_bank = 0, \
.lpmd_bit = -1, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.parked_bitmask = BIT(5), \
.lpdr_bit = PINGROUP_BIT_##lpdr(8), \
}
#define DRV_PINGROUP(pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, \
drvup_w, slwr_b, slwr_w, slwf_b, slwf_w) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \
.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
.hsm_bit = -1, \
.schmitt_bit = -1, \
.lpdr_bit = -1, \
.lpmd_bit = -1, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = -1, \
.parked_bitmask = prk_mask, \
}
static const struct tegra_pingroup tegra210_groups[] = {
/* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, lpdr, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, Y, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, Y, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, Y, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, Y, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, Y, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, Y, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, Y, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, Y, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, Y, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, Y, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, Y, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, Y, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, Y, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, Y, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, Y, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, Y, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, Y, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, Y, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, Y, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, Y, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, Y, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, Y, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, Y, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, Y, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, Y, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, Y, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, Y, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, Y, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, Y, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, Y, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, Y, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, Y, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, Y, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, Y, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, Y, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, Y, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, Y, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, Y, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, Y, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, Y, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, Y, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, Y, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, Y, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, Y, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, Y, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, Y, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, Y, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, Y, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, Y, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, Y, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, Y, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, Y, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, Y, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, Y, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, Y, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, Y, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, Y, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, Y, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, Y, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, Y, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, Y, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, Y, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, Y, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, Y, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, Y, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, Y, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, Y, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, Y, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, Y, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, Y, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, Y, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, Y, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, Y, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, Y, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, Y, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, Y, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, Y, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, Y, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, Y, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, Y, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, Y, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, Y, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
/* pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
DRV_PINGROUP(pa6, 0x9c0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
DRV_PINGROUP(pcc7, 0x9c4, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
DRV_PINGROUP(pe6, 0x9c8, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
DRV_PINGROUP(pe7, 0x9cc, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
DRV_PINGROUP(ph6, 0x9d0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
DRV_PINGROUP(pk0, 0x9d4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk1, 0x9d8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk2, 0x9dc, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk3, 0x9e0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk4, 0x9e4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk5, 0x9e8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk6, 0x9ec, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pk7, 0x9f0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pl0, 0x9f4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
DRV_PINGROUP(pz0, 0x9fc, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(pz1, 0xa00, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(pz2, 0xa04, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(pz3, 0xa08, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(pz4, 0xa0c, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(pz5, 0xa10, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
DRV_PINGROUP(sdmmc1, 0xa98, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
DRV_PINGROUP(sdmmc2, 0xa9c, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
DRV_PINGROUP(sdmmc3, 0xab0, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
DRV_PINGROUP(sdmmc4, 0xab4, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
};
static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra210-gpio",
.pins = tegra210_pins,
.npins = ARRAY_SIZE(tegra210_pins),
.functions = tegra210_functions,
.nfunctions = ARRAY_SIZE(tegra210_functions),
.groups = tegra210_groups,
.ngroups = ARRAY_SIZE(tegra210_groups),
.hsm_in_mux = true,
.schmitt_in_mux = true,
.drvtype_in_mux = true,
};
static int tegra210_pinctrl_probe(struct platform_device *pdev)
{
return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
}
static const struct of_device_id tegra210_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra210-pinmux", },
{ },
};
static struct platform_driver tegra210_pinctrl_driver = {
.driver = {
.name = "tegra210-pinctrl",
.of_match_table = tegra210_pinctrl_of_match,
.pm = pm_sleep_ptr(&tegra_pinctrl_pm),
},
.probe = tegra210_pinctrl_probe,
};
static int __init tegra210_pinctrl_init(void)
{
return platform_driver_register(&tegra210_pinctrl_driver);
}
arch_initcall(tegra210_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra210.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
struct tegra_xusb_padctl_function {
const char *name;
const char * const *groups;
unsigned int num_groups;
};
struct tegra_xusb_padctl_soc {
const struct pinctrl_pin_desc *pins;
unsigned int num_pins;
const struct tegra_xusb_padctl_function *functions;
unsigned int num_functions;
const struct tegra_xusb_padctl_lane *lanes;
unsigned int num_lanes;
};
struct tegra_xusb_padctl_lane {
const char *name;
unsigned int offset;
unsigned int shift;
unsigned int mask;
unsigned int iddq;
const unsigned int *funcs;
unsigned int num_funcs;
};
struct tegra_xusb_padctl {
struct device *dev;
void __iomem *regs;
struct mutex lock;
struct reset_control *rst;
const struct tegra_xusb_padctl_soc *soc;
struct pinctrl_dev *pinctrl;
struct pinctrl_desc desc;
struct phy_provider *provider;
struct phy *phys[2];
unsigned int enable;
};
static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
unsigned long offset)
{
writel(value, padctl->regs + offset);
}
static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
unsigned long offset)
{
return readl(padctl->regs + offset);
}
static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
return padctl->soc->num_pins;
}
static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
unsigned int group)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
return padctl->soc->pins[group].name;
}
static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
/*
* For the tegra-xusb pad controller groups are synonymous
* with lanes/pins and there is always one lane/pin per group.
*/
*pins = &pinctrl->desc->pins[group].number;
*num_pins = 1;
return 0;
}
enum tegra_xusb_padctl_param {
TEGRA_XUSB_PADCTL_IDDQ,
};
static const struct tegra_xusb_padctl_property {
const char *name;
enum tegra_xusb_padctl_param param;
} properties[] = {
{ "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
};
#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
struct device_node *np,
struct pinctrl_map **maps,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
unsigned int i, reserve = 0, num_configs = 0;
unsigned long config, *configs = NULL;
const char *function, *group;
struct property *prop;
int err = 0;
u32 value;
err = of_property_read_string(np, "nvidia,function", &function);
if (err < 0) {
if (err != -EINVAL)
return err;
function = NULL;
}
for (i = 0; i < ARRAY_SIZE(properties); i++) {
err = of_property_read_u32(np, properties[i].name, &value);
if (err < 0) {
if (err == -EINVAL)
continue;
goto out;
}
config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
&num_configs, config);
if (err < 0)
goto out;
}
if (function)
reserve++;
if (num_configs)
reserve++;
err = of_property_count_strings(np, "nvidia,lanes");
if (err < 0)
goto out;
reserve *= err;
err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
num_maps, reserve);
if (err < 0)
goto out;
of_property_for_each_string(np, "nvidia,lanes", prop, group) {
if (function) {
err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
reserved_maps, num_maps, group,
function);
if (err < 0)
goto out;
}
if (num_configs) {
err = pinctrl_utils_add_map_configs(padctl->pinctrl,
maps, reserved_maps, num_maps, group,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err < 0)
goto out;
}
}
err = 0;
out:
kfree(configs);
return err;
}
static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
struct device_node *parent,
struct pinctrl_map **maps,
unsigned int *num_maps)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
unsigned int reserved_maps = 0;
struct device_node *np;
int err;
*num_maps = 0;
*maps = NULL;
for_each_child_of_node(parent, np) {
err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
&reserved_maps,
num_maps);
if (err < 0) {
of_node_put(np);
return err;
}
}
return 0;
}
static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
.get_groups_count = tegra_xusb_padctl_get_groups_count,
.get_group_name = tegra_xusb_padctl_get_group_name,
.get_group_pins = tegra_xusb_padctl_get_group_pins,
.dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
return padctl->soc->num_functions;
}
static const char *
tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
unsigned int function)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
return padctl->soc->functions[function].name;
}
static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
unsigned int function,
const char * const **groups,
unsigned * const num_groups)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
*num_groups = padctl->soc->functions[function].num_groups;
*groups = padctl->soc->functions[function].groups;
return 0;
}
static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
unsigned int function,
unsigned int group)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
const struct tegra_xusb_padctl_lane *lane;
unsigned int i;
u32 value;
lane = &padctl->soc->lanes[group];
for (i = 0; i < lane->num_funcs; i++)
if (lane->funcs[i] == function)
break;
if (i >= lane->num_funcs)
return -EINVAL;
value = padctl_readl(padctl, lane->offset);
value &= ~(lane->mask << lane->shift);
value |= i << lane->shift;
padctl_writel(padctl, value, lane->offset);
return 0;
}
static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
.get_functions_count = tegra_xusb_padctl_get_functions_count,
.get_function_name = tegra_xusb_padctl_get_function_name,
.get_function_groups = tegra_xusb_padctl_get_function_groups,
.set_mux = tegra_xusb_padctl_pinmux_set,
};
static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
unsigned int group,
unsigned long *config)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
const struct tegra_xusb_padctl_lane *lane;
enum tegra_xusb_padctl_param param;
u32 value;
param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
lane = &padctl->soc->lanes[group];
switch (param) {
case TEGRA_XUSB_PADCTL_IDDQ:
/* lanes with iddq == 0 don't support this parameter */
if (lane->iddq == 0)
return -EINVAL;
value = padctl_readl(padctl, lane->offset);
if (value & BIT(lane->iddq))
value = 0;
else
value = 1;
*config = TEGRA_XUSB_PADCTL_PACK(param, value);
break;
default:
dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
param);
return -ENOTSUPP;
}
return 0;
}
static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
unsigned int group,
unsigned long *configs,
unsigned int num_configs)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
const struct tegra_xusb_padctl_lane *lane;
enum tegra_xusb_padctl_param param;
unsigned long value;
unsigned int i;
u32 regval;
lane = &padctl->soc->lanes[group];
for (i = 0; i < num_configs; i++) {
param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
switch (param) {
case TEGRA_XUSB_PADCTL_IDDQ:
/* lanes with iddq == 0 don't support this parameter */
if (lane->iddq == 0)
return -EINVAL;
regval = padctl_readl(padctl, lane->offset);
if (value)
regval &= ~BIT(lane->iddq);
else
regval |= BIT(lane->iddq);
padctl_writel(padctl, regval, lane->offset);
break;
default:
dev_err(padctl->dev,
"invalid configuration parameter: %04x\n",
param);
return -ENOTSUPP;
}
}
return 0;
}
#ifdef CONFIG_DEBUG_FS
static const char *strip_prefix(const char *s)
{
const char *comma = strchr(s, ',');
if (!comma)
return s;
return comma + 1;
}
static void
tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
struct seq_file *s,
unsigned int group)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(properties); i++) {
unsigned long config, value;
int err;
config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
&config);
if (err < 0)
continue;
value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
value);
}
}
static void
tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
struct seq_file *s,
unsigned long config)
{
enum tegra_xusb_padctl_param param;
const char *name = "unknown";
unsigned long value;
unsigned int i;
param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
for (i = 0; i < ARRAY_SIZE(properties); i++) {
if (properties[i].param == param) {
name = properties[i].name;
break;
}
}
seq_printf(s, "%s=%lu", strip_prefix(name), value);
}
#endif
static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
.pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
.pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
#ifdef CONFIG_DEBUG_FS
.pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
.pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
#endif
};
static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
{
u32 value;
mutex_lock(&padctl->lock);
if (padctl->enable++ > 0)
goto out;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
usleep_range(100, 200);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
usleep_range(100, 200);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
out:
mutex_unlock(&padctl->lock);
return 0;
}
static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
{
u32 value;
mutex_lock(&padctl->lock);
if (WARN_ON(padctl->enable == 0))
goto out;
if (--padctl->enable > 0)
goto out;
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
usleep_range(100, 200);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
usleep_range(100, 200);
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
out:
mutex_unlock(&padctl->lock);
return 0;
}
static int tegra_xusb_phy_init(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
return tegra_xusb_padctl_enable(padctl);
}
static int tegra_xusb_phy_exit(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
return tegra_xusb_padctl_disable(padctl);
}
static int pcie_phy_power_on(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
unsigned long timeout;
int err = -ETIMEDOUT;
u32 value;
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
timeout = jiffies + msecs_to_jiffies(50);
while (time_before(jiffies, timeout)) {
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
err = 0;
break;
}
usleep_range(100, 200);
}
return err;
}
static int pcie_phy_power_off(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
u32 value;
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
return 0;
}
static const struct phy_ops pcie_phy_ops = {
.init = tegra_xusb_phy_init,
.exit = tegra_xusb_phy_exit,
.power_on = pcie_phy_power_on,
.power_off = pcie_phy_power_off,
.owner = THIS_MODULE,
};
static int sata_phy_power_on(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
unsigned long timeout;
int err = -ETIMEDOUT;
u32 value;
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
timeout = jiffies + msecs_to_jiffies(50);
while (time_before(jiffies, timeout)) {
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
err = 0;
break;
}
usleep_range(100, 200);
}
return err;
}
static int sata_phy_power_off(struct phy *phy)
{
struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
u32 value;
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
return 0;
}
static const struct phy_ops sata_phy_ops = {
.init = tegra_xusb_phy_init,
.exit = tegra_xusb_phy_exit,
.power_on = sata_phy_power_on,
.power_off = sata_phy_power_off,
.owner = THIS_MODULE,
};
static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
unsigned int index = args->args[0];
if (args->args_count <= 0)
return ERR_PTR(-EINVAL);
if (index >= ARRAY_SIZE(padctl->phys))
return ERR_PTR(-EINVAL);
return padctl->phys[index];
}
#define PIN_OTG_0 0
#define PIN_OTG_1 1
#define PIN_OTG_2 2
#define PIN_ULPI_0 3
#define PIN_HSIC_0 4
#define PIN_HSIC_1 5
#define PIN_PCIE_0 6
#define PIN_PCIE_1 7
#define PIN_PCIE_2 8
#define PIN_PCIE_3 9
#define PIN_PCIE_4 10
#define PIN_SATA_0 11
static const struct pinctrl_pin_desc tegra124_pins[] = {
PINCTRL_PIN(PIN_OTG_0, "otg-0"),
PINCTRL_PIN(PIN_OTG_1, "otg-1"),
PINCTRL_PIN(PIN_OTG_2, "otg-2"),
PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
PINCTRL_PIN(PIN_SATA_0, "sata-0"),
};
static const char * const tegra124_snps_groups[] = {
"otg-0",
"otg-1",
"otg-2",
"ulpi-0",
"hsic-0",
"hsic-1",
};
static const char * const tegra124_xusb_groups[] = {
"otg-0",
"otg-1",
"otg-2",
"ulpi-0",
"hsic-0",
"hsic-1",
};
static const char * const tegra124_uart_groups[] = {
"otg-0",
"otg-1",
"otg-2",
};
static const char * const tegra124_pcie_groups[] = {
"pcie-0",
"pcie-1",
"pcie-2",
"pcie-3",
"pcie-4",
};
static const char * const tegra124_usb3_groups[] = {
"pcie-0",
"pcie-1",
"sata-0",
};
static const char * const tegra124_sata_groups[] = {
"sata-0",
};
static const char * const tegra124_rsvd_groups[] = {
"otg-0",
"otg-1",
"otg-2",
"pcie-0",
"pcie-1",
"pcie-2",
"pcie-3",
"pcie-4",
"sata-0",
};
#define TEGRA124_FUNCTION(_name) \
{ \
.name = #_name, \
.num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
.groups = tegra124_##_name##_groups, \
}
static struct tegra_xusb_padctl_function tegra124_functions[] = {
TEGRA124_FUNCTION(snps),
TEGRA124_FUNCTION(xusb),
TEGRA124_FUNCTION(uart),
TEGRA124_FUNCTION(pcie),
TEGRA124_FUNCTION(usb3),
TEGRA124_FUNCTION(sata),
TEGRA124_FUNCTION(rsvd),
};
enum tegra124_function {
TEGRA124_FUNC_SNPS,
TEGRA124_FUNC_XUSB,
TEGRA124_FUNC_UART,
TEGRA124_FUNC_PCIE,
TEGRA124_FUNC_USB3,
TEGRA124_FUNC_SATA,
TEGRA124_FUNC_RSVD,
};
static const unsigned int tegra124_otg_functions[] = {
TEGRA124_FUNC_SNPS,
TEGRA124_FUNC_XUSB,
TEGRA124_FUNC_UART,
TEGRA124_FUNC_RSVD,
};
static const unsigned int tegra124_usb_functions[] = {
TEGRA124_FUNC_SNPS,
TEGRA124_FUNC_XUSB,
};
static const unsigned int tegra124_pci_functions[] = {
TEGRA124_FUNC_PCIE,
TEGRA124_FUNC_USB3,
TEGRA124_FUNC_SATA,
TEGRA124_FUNC_RSVD,
};
#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
{ \
.name = _name, \
.offset = _offset, \
.shift = _shift, \
.mask = _mask, \
.iddq = _iddq, \
.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
.funcs = tegra124_##_funcs##_functions, \
}
static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
};
static const struct tegra_xusb_padctl_soc tegra124_soc = {
.num_pins = ARRAY_SIZE(tegra124_pins),
.pins = tegra124_pins,
.num_functions = ARRAY_SIZE(tegra124_functions),
.functions = tegra124_functions,
.num_lanes = ARRAY_SIZE(tegra124_lanes),
.lanes = tegra124_lanes,
};
static const struct of_device_id tegra_xusb_padctl_of_match[] = {
{ .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
{ }
};
MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
/* predeclare these in order to silence sparse */
int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
{
struct tegra_xusb_padctl *padctl;
const struct of_device_id *match;
struct phy *phy;
int err;
padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
if (!padctl)
return -ENOMEM;
platform_set_drvdata(pdev, padctl);
mutex_init(&padctl->lock);
padctl->dev = &pdev->dev;
/*
* Note that we can't replace this by of_device_get_match_data()
* because we need the separate matching table for this legacy code on
* Tegra124. of_device_get_match_data() would attempt to use the table
* from the updated driver and fail.
*/
match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
padctl->soc = match->data;
padctl->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(padctl->regs))
return PTR_ERR(padctl->regs);
padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(padctl->rst))
return PTR_ERR(padctl->rst);
err = reset_control_deassert(padctl->rst);
if (err < 0)
return err;
memset(&padctl->desc, 0, sizeof(padctl->desc));
padctl->desc.name = dev_name(padctl->dev);
padctl->desc.pins = tegra124_pins;
padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
padctl->desc.owner = THIS_MODULE;
padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
padctl);
if (IS_ERR(padctl->pinctrl)) {
dev_err(&pdev->dev, "failed to register pincontrol\n");
err = PTR_ERR(padctl->pinctrl);
goto reset;
}
phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
if (IS_ERR(phy)) {
err = PTR_ERR(phy);
goto reset;
}
padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
phy_set_drvdata(phy, padctl);
phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
if (IS_ERR(phy)) {
err = PTR_ERR(phy);
goto reset;
}
padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
phy_set_drvdata(phy, padctl);
padctl->provider = devm_of_phy_provider_register(&pdev->dev,
tegra_xusb_padctl_xlate);
if (IS_ERR(padctl->provider)) {
err = PTR_ERR(padctl->provider);
dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
goto reset;
}
return 0;
reset:
reset_control_assert(padctl->rst);
return err;
}
EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
{
struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
int err;
err = reset_control_assert(padctl->rst);
if (err < 0)
dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
return err;
}
EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Pinctrl data for the NVIDIA Tegra194 pinmux
*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/* Define unique ID for each pins */
enum {
TEGRA_PIN_DAP6_SCLK_PA0,
TEGRA_PIN_DAP6_DOUT_PA1,
TEGRA_PIN_DAP6_DIN_PA2,
TEGRA_PIN_DAP6_FS_PA3,
TEGRA_PIN_DAP4_SCLK_PA4,
TEGRA_PIN_DAP4_DOUT_PA5,
TEGRA_PIN_DAP4_DIN_PA6,
TEGRA_PIN_DAP4_FS_PA7,
TEGRA_PIN_CPU_PWR_REQ_0_PB0,
TEGRA_PIN_CPU_PWR_REQ_1_PB1,
TEGRA_PIN_QSPI0_SCK_PC0,
TEGRA_PIN_QSPI0_CS_N_PC1,
TEGRA_PIN_QSPI0_IO0_PC2,
TEGRA_PIN_QSPI0_IO1_PC3,
TEGRA_PIN_QSPI0_IO2_PC4,
TEGRA_PIN_QSPI0_IO3_PC5,
TEGRA_PIN_QSPI1_SCK_PC6,
TEGRA_PIN_QSPI1_CS_N_PC7,
TEGRA_PIN_QSPI1_IO0_PD0,
TEGRA_PIN_QSPI1_IO1_PD1,
TEGRA_PIN_QSPI1_IO2_PD2,
TEGRA_PIN_QSPI1_IO3_PD3,
TEGRA_PIN_EQOS_TXC_PE0,
TEGRA_PIN_EQOS_TD0_PE1,
TEGRA_PIN_EQOS_TD1_PE2,
TEGRA_PIN_EQOS_TD2_PE3,
TEGRA_PIN_EQOS_TD3_PE4,
TEGRA_PIN_EQOS_TX_CTL_PE5,
TEGRA_PIN_EQOS_RD0_PE6,
TEGRA_PIN_EQOS_RD1_PE7,
TEGRA_PIN_EQOS_RD2_PF0,
TEGRA_PIN_EQOS_RD3_PF1,
TEGRA_PIN_EQOS_RX_CTL_PF2,
TEGRA_PIN_EQOS_RXC_PF3,
TEGRA_PIN_EQOS_SMA_MDIO_PF4,
TEGRA_PIN_EQOS_SMA_MDC_PF5,
TEGRA_PIN_SOC_GPIO00_PG0,
TEGRA_PIN_SOC_GPIO01_PG1,
TEGRA_PIN_SOC_GPIO02_PG2,
TEGRA_PIN_SOC_GPIO03_PG3,
TEGRA_PIN_SOC_GPIO08_PG4,
TEGRA_PIN_SOC_GPIO09_PG5,
TEGRA_PIN_SOC_GPIO10_PG6,
TEGRA_PIN_SOC_GPIO11_PG7,
TEGRA_PIN_SOC_GPIO12_PH0,
TEGRA_PIN_SOC_GPIO13_PH1,
TEGRA_PIN_SOC_GPIO14_PH2,
TEGRA_PIN_UART4_TX_PH3,
TEGRA_PIN_UART4_RX_PH4,
TEGRA_PIN_UART4_RTS_PH5,
TEGRA_PIN_UART4_CTS_PH6,
TEGRA_PIN_DAP2_SCLK_PH7,
TEGRA_PIN_DAP2_DOUT_PI0,
TEGRA_PIN_DAP2_DIN_PI1,
TEGRA_PIN_DAP2_FS_PI2,
TEGRA_PIN_GEN1_I2C_SCL_PI3,
TEGRA_PIN_GEN1_I2C_SDA_PI4,
TEGRA_PIN_SDMMC1_CLK_PJ0,
TEGRA_PIN_SDMMC1_CMD_PJ1,
TEGRA_PIN_SDMMC1_DAT0_PJ2,
TEGRA_PIN_SDMMC1_DAT1_PJ3,
TEGRA_PIN_SDMMC1_DAT2_PJ4,
TEGRA_PIN_SDMMC1_DAT3_PJ5,
TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
TEGRA_PIN_PEX_L0_RST_N_PK1,
TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
TEGRA_PIN_PEX_L1_RST_N_PK3,
TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
TEGRA_PIN_PEX_L2_RST_N_PK5,
TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
TEGRA_PIN_PEX_L3_RST_N_PK7,
TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
TEGRA_PIN_PEX_L4_RST_N_PL1,
TEGRA_PIN_PEX_WAKE_N_PL2,
TEGRA_PIN_SATA_DEV_SLP_PL3,
TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
TEGRA_PIN_HDMI_CEC_PM4,
TEGRA_PIN_SOC_GPIO50_PM5,
TEGRA_PIN_SOC_GPIO51_PM6,
TEGRA_PIN_SOC_GPIO52_PM7,
TEGRA_PIN_SOC_GPIO53_PN0,
TEGRA_PIN_SOC_GPIO54_PN1,
TEGRA_PIN_SOC_GPIO55_PN2,
TEGRA_PIN_SDMMC3_CLK_PO0,
TEGRA_PIN_SDMMC3_CMD_PO1,
TEGRA_PIN_SDMMC3_DAT0_PO2,
TEGRA_PIN_SDMMC3_DAT1_PO3,
TEGRA_PIN_SDMMC3_DAT2_PO4,
TEGRA_PIN_SDMMC3_DAT3_PO5,
TEGRA_PIN_EXTPERIPH1_CLK_PP0,
TEGRA_PIN_EXTPERIPH2_CLK_PP1,
TEGRA_PIN_CAM_I2C_SCL_PP2,
TEGRA_PIN_CAM_I2C_SDA_PP3,
TEGRA_PIN_SOC_GPIO04_PP4,
TEGRA_PIN_SOC_GPIO05_PP5,
TEGRA_PIN_SOC_GPIO06_PP6,
TEGRA_PIN_SOC_GPIO07_PP7,
TEGRA_PIN_SOC_GPIO20_PQ0,
TEGRA_PIN_SOC_GPIO21_PQ1,
TEGRA_PIN_SOC_GPIO22_PQ2,
TEGRA_PIN_SOC_GPIO23_PQ3,
TEGRA_PIN_SOC_GPIO40_PQ4,
TEGRA_PIN_SOC_GPIO41_PQ5,
TEGRA_PIN_SOC_GPIO42_PQ6,
TEGRA_PIN_SOC_GPIO43_PQ7,
TEGRA_PIN_SOC_GPIO44_PR0,
TEGRA_PIN_SOC_GPIO45_PR1,
TEGRA_PIN_UART1_TX_PR2,
TEGRA_PIN_UART1_RX_PR3,
TEGRA_PIN_UART1_RTS_PR4,
TEGRA_PIN_UART1_CTS_PR5,
TEGRA_PIN_DAP1_SCLK_PS0,
TEGRA_PIN_DAP1_DOUT_PS1,
TEGRA_PIN_DAP1_DIN_PS2,
TEGRA_PIN_DAP1_FS_PS3,
TEGRA_PIN_AUD_MCLK_PS4,
TEGRA_PIN_SOC_GPIO30_PS5,
TEGRA_PIN_SOC_GPIO31_PS6,
TEGRA_PIN_SOC_GPIO32_PS7,
TEGRA_PIN_SOC_GPIO33_PT0,
TEGRA_PIN_DAP3_SCLK_PT1,
TEGRA_PIN_DAP3_DOUT_PT2,
TEGRA_PIN_DAP3_DIN_PT3,
TEGRA_PIN_DAP3_FS_PT4,
TEGRA_PIN_DAP5_SCLK_PT5,
TEGRA_PIN_DAP5_DOUT_PT6,
TEGRA_PIN_DAP5_DIN_PT7,
TEGRA_PIN_DAP5_FS_PU0,
TEGRA_PIN_DIRECTDC1_CLK_PV0,
TEGRA_PIN_DIRECTDC1_IN_PV1,
TEGRA_PIN_DIRECTDC1_OUT0_PV2,
TEGRA_PIN_DIRECTDC1_OUT1_PV3,
TEGRA_PIN_DIRECTDC1_OUT2_PV4,
TEGRA_PIN_DIRECTDC1_OUT3_PV5,
TEGRA_PIN_DIRECTDC1_OUT4_PV6,
TEGRA_PIN_DIRECTDC1_OUT5_PV7,
TEGRA_PIN_DIRECTDC1_OUT6_PW0,
TEGRA_PIN_DIRECTDC1_OUT7_PW1,
TEGRA_PIN_GPU_PWR_REQ_PX0,
TEGRA_PIN_CV_PWR_REQ_PX1,
TEGRA_PIN_GP_PWM2_PX2,
TEGRA_PIN_GP_PWM3_PX3,
TEGRA_PIN_UART2_TX_PX4,
TEGRA_PIN_UART2_RX_PX5,
TEGRA_PIN_UART2_RTS_PX6,
TEGRA_PIN_UART2_CTS_PX7,
TEGRA_PIN_SPI3_SCK_PY0,
TEGRA_PIN_SPI3_MISO_PY1,
TEGRA_PIN_SPI3_MOSI_PY2,
TEGRA_PIN_SPI3_CS0_PY3,
TEGRA_PIN_SPI3_CS1_PY4,
TEGRA_PIN_UART5_TX_PY5,
TEGRA_PIN_UART5_RX_PY6,
TEGRA_PIN_UART5_RTS_PY7,
TEGRA_PIN_UART5_CTS_PZ0,
TEGRA_PIN_USB_VBUS_EN0_PZ1,
TEGRA_PIN_USB_VBUS_EN1_PZ2,
TEGRA_PIN_SPI1_SCK_PZ3,
TEGRA_PIN_SPI1_MISO_PZ4,
TEGRA_PIN_SPI1_MOSI_PZ5,
TEGRA_PIN_SPI1_CS0_PZ6,
TEGRA_PIN_SPI1_CS1_PZ7,
TEGRA_PIN_UFS0_REF_CLK_PFF0,
TEGRA_PIN_UFS0_RST_PFF1,
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
TEGRA_PIN_PEX_L5_RST_N_PGG1,
TEGRA_PIN_DIRECTDC_COMP,
TEGRA_PIN_SDMMC4_CLK,
TEGRA_PIN_SDMMC4_CMD,
TEGRA_PIN_SDMMC4_DQS,
TEGRA_PIN_SDMMC4_DAT7,
TEGRA_PIN_SDMMC4_DAT6,
TEGRA_PIN_SDMMC4_DAT5,
TEGRA_PIN_SDMMC4_DAT4,
TEGRA_PIN_SDMMC4_DAT3,
TEGRA_PIN_SDMMC4_DAT2,
TEGRA_PIN_SDMMC4_DAT1,
TEGRA_PIN_SDMMC4_DAT0,
TEGRA_PIN_SDMMC1_COMP,
TEGRA_PIN_SDMMC1_HV_TRIM,
TEGRA_PIN_SDMMC3_COMP,
TEGRA_PIN_SDMMC3_HV_TRIM,
TEGRA_PIN_EQOS_COMP,
TEGRA_PIN_QSPI_COMP,
};
enum {
TEGRA_PIN_CAN1_DOUT_PAA0,
TEGRA_PIN_CAN1_DIN_PAA1,
TEGRA_PIN_CAN0_DOUT_PAA2,
TEGRA_PIN_CAN0_DIN_PAA3,
TEGRA_PIN_CAN0_STB_PAA4,
TEGRA_PIN_CAN0_EN_PAA5,
TEGRA_PIN_CAN0_WAKE_PAA6,
TEGRA_PIN_CAN0_ERR_PAA7,
TEGRA_PIN_CAN1_STB_PBB0,
TEGRA_PIN_CAN1_EN_PBB1,
TEGRA_PIN_CAN1_WAKE_PBB2,
TEGRA_PIN_CAN1_ERR_PBB3,
TEGRA_PIN_SPI2_SCK_PCC0,
TEGRA_PIN_SPI2_MISO_PCC1,
TEGRA_PIN_SPI2_MOSI_PCC2,
TEGRA_PIN_SPI2_CS0_PCC3,
TEGRA_PIN_TOUCH_CLK_PCC4,
TEGRA_PIN_UART3_TX_PCC5,
TEGRA_PIN_UART3_RX_PCC6,
TEGRA_PIN_GEN2_I2C_SCL_PCC7,
TEGRA_PIN_GEN2_I2C_SDA_PDD0,
TEGRA_PIN_GEN8_I2C_SCL_PDD1,
TEGRA_PIN_GEN8_I2C_SDA_PDD2,
TEGRA_PIN_SAFE_STATE_PEE0,
TEGRA_PIN_VCOMP_ALERT_PEE1,
TEGRA_PIN_AO_RETENTION_N_PEE2,
TEGRA_PIN_BATT_OC_PEE3,
TEGRA_PIN_POWER_ON_PEE4,
TEGRA_PIN_PWR_I2C_SCL_PEE5,
TEGRA_PIN_PWR_I2C_SDA_PEE6,
TEGRA_PIN_SYS_RESET_N,
TEGRA_PIN_SHUTDOWN_N,
TEGRA_PIN_PMU_INT_N,
TEGRA_PIN_SOC_PWR_REQ,
TEGRA_PIN_CLK_32K_IN,
};
/* Table for pin descriptor */
static const struct pinctrl_pin_desc tegra194_pins[] = {
PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),
PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_0_PB0, "CPU_PWR_REQ_0_PB0"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_1_PB1, "CPU_PWR_REQ_1_PB1"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),
PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PG0, "SOC_GPIO00_PG0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO01_PG1, "SOC_GPIO01_PG1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO02_PG2, "SOC_GPIO02_PG2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO03_PG3, "SOC_GPIO03_PG3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PG4, "SOC_GPIO08_PG4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PG5, "SOC_GPIO09_PG5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO10_PG6, "SOC_GPIO10_PG6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO11_PG7, "SOC_GPIO11_PG7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO12_PH0, "SOC_GPIO12_PH0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PH1, "SOC_GPIO13_PH1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PH2, "SOC_GPIO14_PH2"),
PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),
PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),
PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),
PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PH7, "DAP2_SCLK_PH7"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PI0, "DAP2_DOUT_PI0"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PI1, "DAP2_DIN_PI1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PI2, "DAP2_FS_PI2"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),
PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),
PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),
PINCTRL_PIN(TEGRA_PIN_SATA_DEV_SLP_PL3, "SATA_DEV_SLP_PL3"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PM4, "HDMI_CEC_PM4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PM5, "SOC_GPIO50_PM5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO51_PM6, "SOC_GPIO51_PM6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO52_PM7, "SOC_GPIO52_PM7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PN0, "SOC_GPIO53_PN0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO54_PN1, "SOC_GPIO54_PN1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PN2, "SOC_GPIO55_PN2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PO0, "SDMMC3_CLK_PO0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PO1, "SDMMC3_CMD_PO1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PO2, "SDMMC3_DAT0_PO2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PO3, "SDMMC3_DAT1_PO3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PO4, "SDMMC3_DAT2_PO4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PO5, "SDMMC3_DAT3_PO5"),
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PP4, "SOC_GPIO04_PP4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO05_PP5, "SOC_GPIO05_PP5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PP6, "SOC_GPIO06_PP6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PP7, "SOC_GPIO07_PP7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PQ0, "SOC_GPIO20_PQ0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PQ1, "SOC_GPIO21_PQ1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PQ2, "SOC_GPIO22_PQ2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PQ3, "SOC_GPIO23_PQ3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PQ4, "SOC_GPIO40_PQ4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PQ5, "SOC_GPIO41_PQ5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PQ6, "SOC_GPIO42_PQ6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PQ7, "SOC_GPIO43_PQ7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PR0, "SOC_GPIO44_PR0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PR1, "SOC_GPIO45_PR1"),
PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),
PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),
PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),
PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PS0, "DAP1_SCLK_PS0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PS1, "DAP1_DOUT_PS1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PS2, "DAP1_DIN_PS2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PS3, "DAP1_FS_PS3"),
PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PS4, "AUD_MCLK_PS4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PS5, "SOC_GPIO30_PS5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PS6, "SOC_GPIO31_PS6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PS7, "SOC_GPIO32_PS7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PT0, "SOC_GPIO33_PT0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PT1, "DAP3_SCLK_PT1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PT2, "DAP3_DOUT_PT2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PT3, "DAP3_DIN_PT3"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PT4, "DAP3_FS_PT4"),
PINCTRL_PIN(TEGRA_PIN_DAP5_SCLK_PT5, "DAP5_SCLK_PT5"),
PINCTRL_PIN(TEGRA_PIN_DAP5_DOUT_PT6, "DAP5_DOUT_PT6"),
PINCTRL_PIN(TEGRA_PIN_DAP5_DIN_PT7, "DAP5_DIN_PT7"),
PINCTRL_PIN(TEGRA_PIN_DAP5_FS_PU0, "DAP5_FS_PU0"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PV0, "DIRECTDC1_CLK_PV0"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PV1, "DIRECTDC1_IN_PV1"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PV2, "DIRECTDC1_OUT0_PV2"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PV3, "DIRECTDC1_OUT1_PV3"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PV4, "DIRECTDC1_OUT2_PV4"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PV5, "DIRECTDC1_OUT3_PV5"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT4_PV6, "DIRECTDC1_OUT4_PV6"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT5_PV7, "DIRECTDC1_OUT5_PV7"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT6_PW0, "DIRECTDC1_OUT6_PW0"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT7_PW1, "DIRECTDC1_OUT7_PW1"),
PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),
PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),
PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),
PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),
PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),
PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),
PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),
PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),
PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),
PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),
PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),
PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),
PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),
PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),
PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),
PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK, "SDMMC4_CLK"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD, "SDMMC4_CMD"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DQS, "SDMMC4_DQS"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7, "SDMMC4_DAT7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6, "SDMMC4_DAT6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5, "SDMMC4_DAT5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4, "SDMMC4_DAT4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3, "SDMMC4_DAT3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2, "SDMMC4_DAT2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1, "SDMMC4_DAT1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0, "SDMMC4_DAT0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_HV_TRIM, "SDMMC1_HV_TRIM"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),
PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
};
static const unsigned int dap6_sclk_pa0_pins[] = {
TEGRA_PIN_DAP6_SCLK_PA0,
};
static const unsigned int dap6_dout_pa1_pins[] = {
TEGRA_PIN_DAP6_DOUT_PA1,
};
static const unsigned int dap6_din_pa2_pins[] = {
TEGRA_PIN_DAP6_DIN_PA2,
};
static const unsigned int dap6_fs_pa3_pins[] = {
TEGRA_PIN_DAP6_FS_PA3,
};
static const unsigned int dap4_sclk_pa4_pins[] = {
TEGRA_PIN_DAP4_SCLK_PA4,
};
static const unsigned int dap4_dout_pa5_pins[] = {
TEGRA_PIN_DAP4_DOUT_PA5,
};
static const unsigned int dap4_din_pa6_pins[] = {
TEGRA_PIN_DAP4_DIN_PA6,
};
static const unsigned int dap4_fs_pa7_pins[] = {
TEGRA_PIN_DAP4_FS_PA7,
};
static const unsigned int cpu_pwr_req_0_pb0_pins[] = {
TEGRA_PIN_CPU_PWR_REQ_0_PB0,
};
static const unsigned int cpu_pwr_req_1_pb1_pins[] = {
TEGRA_PIN_CPU_PWR_REQ_1_PB1,
};
static const unsigned int qspi0_sck_pc0_pins[] = {
TEGRA_PIN_QSPI0_SCK_PC0,
};
static const unsigned int qspi0_cs_n_pc1_pins[] = {
TEGRA_PIN_QSPI0_CS_N_PC1,
};
static const unsigned int qspi0_io0_pc2_pins[] = {
TEGRA_PIN_QSPI0_IO0_PC2,
};
static const unsigned int qspi0_io1_pc3_pins[] = {
TEGRA_PIN_QSPI0_IO1_PC3,
};
static const unsigned int qspi0_io2_pc4_pins[] = {
TEGRA_PIN_QSPI0_IO2_PC4,
};
static const unsigned int qspi0_io3_pc5_pins[] = {
TEGRA_PIN_QSPI0_IO3_PC5,
};
static const unsigned int qspi1_sck_pc6_pins[] = {
TEGRA_PIN_QSPI1_SCK_PC6,
};
static const unsigned int qspi1_cs_n_pc7_pins[] = {
TEGRA_PIN_QSPI1_CS_N_PC7,
};
static const unsigned int qspi1_io0_pd0_pins[] = {
TEGRA_PIN_QSPI1_IO0_PD0,
};
static const unsigned int qspi1_io1_pd1_pins[] = {
TEGRA_PIN_QSPI1_IO1_PD1,
};
static const unsigned int qspi1_io2_pd2_pins[] = {
TEGRA_PIN_QSPI1_IO2_PD2,
};
static const unsigned int qspi1_io3_pd3_pins[] = {
TEGRA_PIN_QSPI1_IO3_PD3,
};
static const unsigned int eqos_txc_pe0_pins[] = {
TEGRA_PIN_EQOS_TXC_PE0,
};
static const unsigned int eqos_td0_pe1_pins[] = {
TEGRA_PIN_EQOS_TD0_PE1,
};
static const unsigned int eqos_td1_pe2_pins[] = {
TEGRA_PIN_EQOS_TD1_PE2,
};
static const unsigned int eqos_td2_pe3_pins[] = {
TEGRA_PIN_EQOS_TD2_PE3,
};
static const unsigned int eqos_td3_pe4_pins[] = {
TEGRA_PIN_EQOS_TD3_PE4,
};
static const unsigned int eqos_tx_ctl_pe5_pins[] = {
TEGRA_PIN_EQOS_TX_CTL_PE5,
};
static const unsigned int eqos_rd0_pe6_pins[] = {
TEGRA_PIN_EQOS_RD0_PE6,
};
static const unsigned int eqos_rd1_pe7_pins[] = {
TEGRA_PIN_EQOS_RD1_PE7,
};
static const unsigned int eqos_rd2_pf0_pins[] = {
TEGRA_PIN_EQOS_RD2_PF0,
};
static const unsigned int eqos_rd3_pf1_pins[] = {
TEGRA_PIN_EQOS_RD3_PF1,
};
static const unsigned int eqos_rx_ctl_pf2_pins[] = {
TEGRA_PIN_EQOS_RX_CTL_PF2,
};
static const unsigned int eqos_rxc_pf3_pins[] = {
TEGRA_PIN_EQOS_RXC_PF3,
};
static const unsigned int eqos_sma_mdio_pf4_pins[] = {
TEGRA_PIN_EQOS_SMA_MDIO_PF4,
};
static const unsigned int eqos_sma_mdc_pf5_pins[] = {
TEGRA_PIN_EQOS_SMA_MDC_PF5,
};
static const unsigned int soc_gpio00_pg0_pins[] = {
TEGRA_PIN_SOC_GPIO00_PG0,
};
static const unsigned int soc_gpio01_pg1_pins[] = {
TEGRA_PIN_SOC_GPIO01_PG1,
};
static const unsigned int soc_gpio02_pg2_pins[] = {
TEGRA_PIN_SOC_GPIO02_PG2,
};
static const unsigned int soc_gpio03_pg3_pins[] = {
TEGRA_PIN_SOC_GPIO03_PG3,
};
static const unsigned int soc_gpio08_pg4_pins[] = {
TEGRA_PIN_SOC_GPIO08_PG4,
};
static const unsigned int soc_gpio09_pg5_pins[] = {
TEGRA_PIN_SOC_GPIO09_PG5,
};
static const unsigned int soc_gpio10_pg6_pins[] = {
TEGRA_PIN_SOC_GPIO10_PG6,
};
static const unsigned int soc_gpio11_pg7_pins[] = {
TEGRA_PIN_SOC_GPIO11_PG7,
};
static const unsigned int soc_gpio12_ph0_pins[] = {
TEGRA_PIN_SOC_GPIO12_PH0,
};
static const unsigned int soc_gpio13_ph1_pins[] = {
TEGRA_PIN_SOC_GPIO13_PH1,
};
static const unsigned int soc_gpio14_ph2_pins[] = {
TEGRA_PIN_SOC_GPIO14_PH2,
};
static const unsigned int uart4_tx_ph3_pins[] = {
TEGRA_PIN_UART4_TX_PH3,
};
static const unsigned int uart4_rx_ph4_pins[] = {
TEGRA_PIN_UART4_RX_PH4,
};
static const unsigned int uart4_rts_ph5_pins[] = {
TEGRA_PIN_UART4_RTS_PH5,
};
static const unsigned int uart4_cts_ph6_pins[] = {
TEGRA_PIN_UART4_CTS_PH6,
};
static const unsigned int dap2_sclk_ph7_pins[] = {
TEGRA_PIN_DAP2_SCLK_PH7,
};
static const unsigned int dap2_dout_pi0_pins[] = {
TEGRA_PIN_DAP2_DOUT_PI0,
};
static const unsigned int dap2_din_pi1_pins[] = {
TEGRA_PIN_DAP2_DIN_PI1,
};
static const unsigned int dap2_fs_pi2_pins[] = {
TEGRA_PIN_DAP2_FS_PI2,
};
static const unsigned int gen1_i2c_scl_pi3_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PI3,
};
static const unsigned int gen1_i2c_sda_pi4_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PI4,
};
static const unsigned int sdmmc1_clk_pj0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PJ0,
};
static const unsigned int sdmmc1_cmd_pj1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PJ1,
};
static const unsigned int sdmmc1_dat0_pj2_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PJ2,
};
static const unsigned int sdmmc1_dat1_pj3_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PJ3,
};
static const unsigned int sdmmc1_dat2_pj4_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PJ4,
};
static const unsigned int sdmmc1_dat3_pj5_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PJ5,
};
static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {
TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
};
static const unsigned int pex_l0_rst_n_pk1_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PK1,
};
static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {
TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
};
static const unsigned int pex_l1_rst_n_pk3_pins[] = {
TEGRA_PIN_PEX_L1_RST_N_PK3,
};
static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {
TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
};
static const unsigned int pex_l2_rst_n_pk5_pins[] = {
TEGRA_PIN_PEX_L2_RST_N_PK5,
};
static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {
TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
};
static const unsigned int pex_l3_rst_n_pk7_pins[] = {
TEGRA_PIN_PEX_L3_RST_N_PK7,
};
static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {
TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
};
static const unsigned int pex_l4_rst_n_pl1_pins[] = {
TEGRA_PIN_PEX_L4_RST_N_PL1,
};
static const unsigned int pex_wake_n_pl2_pins[] = {
TEGRA_PIN_PEX_WAKE_N_PL2,
};
static const unsigned int sata_dev_slp_pl3_pins[] = {
TEGRA_PIN_SATA_DEV_SLP_PL3,
};
static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {
TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
};
static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {
TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
};
static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {
TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
};
static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {
TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
};
static const unsigned int hdmi_cec_pm4_pins[] = {
TEGRA_PIN_HDMI_CEC_PM4,
};
static const unsigned int soc_gpio50_pm5_pins[] = {
TEGRA_PIN_SOC_GPIO50_PM5,
};
static const unsigned int soc_gpio51_pm6_pins[] = {
TEGRA_PIN_SOC_GPIO51_PM6,
};
static const unsigned int soc_gpio52_pm7_pins[] = {
TEGRA_PIN_SOC_GPIO52_PM7,
};
static const unsigned int soc_gpio53_pn0_pins[] = {
TEGRA_PIN_SOC_GPIO53_PN0,
};
static const unsigned int soc_gpio54_pn1_pins[] = {
TEGRA_PIN_SOC_GPIO54_PN1,
};
static const unsigned int soc_gpio55_pn2_pins[] = {
TEGRA_PIN_SOC_GPIO55_PN2,
};
static const unsigned int sdmmc3_clk_po0_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PO0,
};
static const unsigned int sdmmc3_cmd_po1_pins[] = {
TEGRA_PIN_SDMMC3_CMD_PO1,
};
static const unsigned int sdmmc3_dat0_po2_pins[] = {
TEGRA_PIN_SDMMC3_DAT0_PO2,
};
static const unsigned int sdmmc3_dat1_po3_pins[] = {
TEGRA_PIN_SDMMC3_DAT1_PO3,
};
static const unsigned int sdmmc3_dat2_po4_pins[] = {
TEGRA_PIN_SDMMC3_DAT2_PO4,
};
static const unsigned int sdmmc3_dat3_po5_pins[] = {
TEGRA_PIN_SDMMC3_DAT3_PO5,
};
static const unsigned int extperiph1_clk_pp0_pins[] = {
TEGRA_PIN_EXTPERIPH1_CLK_PP0,
};
static const unsigned int extperiph2_clk_pp1_pins[] = {
TEGRA_PIN_EXTPERIPH2_CLK_PP1,
};
static const unsigned int cam_i2c_scl_pp2_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PP2,
};
static const unsigned int cam_i2c_sda_pp3_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PP3,
};
static const unsigned int soc_gpio04_pp4_pins[] = {
TEGRA_PIN_SOC_GPIO04_PP4,
};
static const unsigned int soc_gpio05_pp5_pins[] = {
TEGRA_PIN_SOC_GPIO05_PP5,
};
static const unsigned int soc_gpio06_pp6_pins[] = {
TEGRA_PIN_SOC_GPIO06_PP6,
};
static const unsigned int soc_gpio07_pp7_pins[] = {
TEGRA_PIN_SOC_GPIO07_PP7,
};
static const unsigned int soc_gpio20_pq0_pins[] = {
TEGRA_PIN_SOC_GPIO20_PQ0,
};
static const unsigned int soc_gpio21_pq1_pins[] = {
TEGRA_PIN_SOC_GPIO21_PQ1,
};
static const unsigned int soc_gpio22_pq2_pins[] = {
TEGRA_PIN_SOC_GPIO22_PQ2,
};
static const unsigned int soc_gpio23_pq3_pins[] = {
TEGRA_PIN_SOC_GPIO23_PQ3,
};
static const unsigned int soc_gpio40_pq4_pins[] = {
TEGRA_PIN_SOC_GPIO40_PQ4,
};
static const unsigned int soc_gpio41_pq5_pins[] = {
TEGRA_PIN_SOC_GPIO41_PQ5,
};
static const unsigned int soc_gpio42_pq6_pins[] = {
TEGRA_PIN_SOC_GPIO42_PQ6,
};
static const unsigned int soc_gpio43_pq7_pins[] = {
TEGRA_PIN_SOC_GPIO43_PQ7,
};
static const unsigned int soc_gpio44_pr0_pins[] = {
TEGRA_PIN_SOC_GPIO44_PR0,
};
static const unsigned int soc_gpio45_pr1_pins[] = {
TEGRA_PIN_SOC_GPIO45_PR1,
};
static const unsigned int uart1_tx_pr2_pins[] = {
TEGRA_PIN_UART1_TX_PR2,
};
static const unsigned int uart1_rx_pr3_pins[] = {
TEGRA_PIN_UART1_RX_PR3,
};
static const unsigned int uart1_rts_pr4_pins[] = {
TEGRA_PIN_UART1_RTS_PR4,
};
static const unsigned int uart1_cts_pr5_pins[] = {
TEGRA_PIN_UART1_CTS_PR5,
};
static const unsigned int dap1_sclk_ps0_pins[] = {
TEGRA_PIN_DAP1_SCLK_PS0,
};
static const unsigned int dap1_dout_ps1_pins[] = {
TEGRA_PIN_DAP1_DOUT_PS1,
};
static const unsigned int dap1_din_ps2_pins[] = {
TEGRA_PIN_DAP1_DIN_PS2,
};
static const unsigned int dap1_fs_ps3_pins[] = {
TEGRA_PIN_DAP1_FS_PS3,
};
static const unsigned int aud_mclk_ps4_pins[] = {
TEGRA_PIN_AUD_MCLK_PS4,
};
static const unsigned int soc_gpio30_ps5_pins[] = {
TEGRA_PIN_SOC_GPIO30_PS5,
};
static const unsigned int soc_gpio31_ps6_pins[] = {
TEGRA_PIN_SOC_GPIO31_PS6,
};
static const unsigned int soc_gpio32_ps7_pins[] = {
TEGRA_PIN_SOC_GPIO32_PS7,
};
static const unsigned int soc_gpio33_pt0_pins[] = {
TEGRA_PIN_SOC_GPIO33_PT0,
};
static const unsigned int dap3_sclk_pt1_pins[] = {
TEGRA_PIN_DAP3_SCLK_PT1,
};
static const unsigned int dap3_dout_pt2_pins[] = {
TEGRA_PIN_DAP3_DOUT_PT2,
};
static const unsigned int dap3_din_pt3_pins[] = {
TEGRA_PIN_DAP3_DIN_PT3,
};
static const unsigned int dap3_fs_pt4_pins[] = {
TEGRA_PIN_DAP3_FS_PT4,
};
static const unsigned int dap5_sclk_pt5_pins[] = {
TEGRA_PIN_DAP5_SCLK_PT5,
};
static const unsigned int dap5_dout_pt6_pins[] = {
TEGRA_PIN_DAP5_DOUT_PT6,
};
static const unsigned int dap5_din_pt7_pins[] = {
TEGRA_PIN_DAP5_DIN_PT7,
};
static const unsigned int dap5_fs_pu0_pins[] = {
TEGRA_PIN_DAP5_FS_PU0,
};
static const unsigned int directdc1_clk_pv0_pins[] = {
TEGRA_PIN_DIRECTDC1_CLK_PV0,
};
static const unsigned int directdc1_in_pv1_pins[] = {
TEGRA_PIN_DIRECTDC1_IN_PV1,
};
static const unsigned int directdc1_out0_pv2_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT0_PV2,
};
static const unsigned int directdc1_out1_pv3_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT1_PV3,
};
static const unsigned int directdc1_out2_pv4_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT2_PV4,
};
static const unsigned int directdc1_out3_pv5_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT3_PV5,
};
static const unsigned int directdc1_out4_pv6_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT4_PV6,
};
static const unsigned int directdc1_out5_pv7_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT5_PV7,
};
static const unsigned int directdc1_out6_pw0_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT6_PW0,
};
static const unsigned int directdc1_out7_pw1_pins[] = {
TEGRA_PIN_DIRECTDC1_OUT7_PW1,
};
static const unsigned int gpu_pwr_req_px0_pins[] = {
TEGRA_PIN_GPU_PWR_REQ_PX0,
};
static const unsigned int cv_pwr_req_px1_pins[] = {
TEGRA_PIN_CV_PWR_REQ_PX1,
};
static const unsigned int gp_pwm2_px2_pins[] = {
TEGRA_PIN_GP_PWM2_PX2,
};
static const unsigned int gp_pwm3_px3_pins[] = {
TEGRA_PIN_GP_PWM3_PX3,
};
static const unsigned int uart2_tx_px4_pins[] = {
TEGRA_PIN_UART2_TX_PX4,
};
static const unsigned int uart2_rx_px5_pins[] = {
TEGRA_PIN_UART2_RX_PX5,
};
static const unsigned int uart2_rts_px6_pins[] = {
TEGRA_PIN_UART2_RTS_PX6,
};
static const unsigned int uart2_cts_px7_pins[] = {
TEGRA_PIN_UART2_CTS_PX7,
};
static const unsigned int spi3_sck_py0_pins[] = {
TEGRA_PIN_SPI3_SCK_PY0,
};
static const unsigned int spi3_miso_py1_pins[] = {
TEGRA_PIN_SPI3_MISO_PY1,
};
static const unsigned int spi3_mosi_py2_pins[] = {
TEGRA_PIN_SPI3_MOSI_PY2,
};
static const unsigned int spi3_cs0_py3_pins[] = {
TEGRA_PIN_SPI3_CS0_PY3,
};
static const unsigned int spi3_cs1_py4_pins[] = {
TEGRA_PIN_SPI3_CS1_PY4,
};
static const unsigned int uart5_tx_py5_pins[] = {
TEGRA_PIN_UART5_TX_PY5,
};
static const unsigned int uart5_rx_py6_pins[] = {
TEGRA_PIN_UART5_RX_PY6,
};
static const unsigned int uart5_rts_py7_pins[] = {
TEGRA_PIN_UART5_RTS_PY7,
};
static const unsigned int uart5_cts_pz0_pins[] = {
TEGRA_PIN_UART5_CTS_PZ0,
};
static const unsigned int usb_vbus_en0_pz1_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PZ1,
};
static const unsigned int usb_vbus_en1_pz2_pins[] = {
TEGRA_PIN_USB_VBUS_EN1_PZ2,
};
static const unsigned int spi1_sck_pz3_pins[] = {
TEGRA_PIN_SPI1_SCK_PZ3,
};
static const unsigned int spi1_miso_pz4_pins[] = {
TEGRA_PIN_SPI1_MISO_PZ4,
};
static const unsigned int spi1_mosi_pz5_pins[] = {
TEGRA_PIN_SPI1_MOSI_PZ5,
};
static const unsigned int spi1_cs0_pz6_pins[] = {
TEGRA_PIN_SPI1_CS0_PZ6,
};
static const unsigned int spi1_cs1_pz7_pins[] = {
TEGRA_PIN_SPI1_CS1_PZ7,
};
static const unsigned int can1_dout_paa0_pins[] = {
TEGRA_PIN_CAN1_DOUT_PAA0,
};
static const unsigned int can1_din_paa1_pins[] = {
TEGRA_PIN_CAN1_DIN_PAA1,
};
static const unsigned int can0_dout_paa2_pins[] = {
TEGRA_PIN_CAN0_DOUT_PAA2,
};
static const unsigned int can0_din_paa3_pins[] = {
TEGRA_PIN_CAN0_DIN_PAA3,
};
static const unsigned int can0_stb_paa4_pins[] = {
TEGRA_PIN_CAN0_STB_PAA4,
};
static const unsigned int can0_en_paa5_pins[] = {
TEGRA_PIN_CAN0_EN_PAA5,
};
static const unsigned int can0_wake_paa6_pins[] = {
TEGRA_PIN_CAN0_WAKE_PAA6,
};
static const unsigned int can0_err_paa7_pins[] = {
TEGRA_PIN_CAN0_ERR_PAA7,
};
static const unsigned int can1_stb_pbb0_pins[] = {
TEGRA_PIN_CAN1_STB_PBB0,
};
static const unsigned int can1_en_pbb1_pins[] = {
TEGRA_PIN_CAN1_EN_PBB1,
};
static const unsigned int can1_wake_pbb2_pins[] = {
TEGRA_PIN_CAN1_WAKE_PBB2,
};
static const unsigned int can1_err_pbb3_pins[] = {
TEGRA_PIN_CAN1_ERR_PBB3,
};
static const unsigned int spi2_sck_pcc0_pins[] = {
TEGRA_PIN_SPI2_SCK_PCC0,
};
static const unsigned int spi2_miso_pcc1_pins[] = {
TEGRA_PIN_SPI2_MISO_PCC1,
};
static const unsigned int spi2_mosi_pcc2_pins[] = {
TEGRA_PIN_SPI2_MOSI_PCC2,
};
static const unsigned int spi2_cs0_pcc3_pins[] = {
TEGRA_PIN_SPI2_CS0_PCC3,
};
static const unsigned int touch_clk_pcc4_pins[] = {
TEGRA_PIN_TOUCH_CLK_PCC4,
};
static const unsigned int uart3_tx_pcc5_pins[] = {
TEGRA_PIN_UART3_TX_PCC5,
};
static const unsigned int uart3_rx_pcc6_pins[] = {
TEGRA_PIN_UART3_RX_PCC6,
};
static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PCC7,
};
static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PDD0,
};
static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
TEGRA_PIN_GEN8_I2C_SCL_PDD1,
};
static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
TEGRA_PIN_GEN8_I2C_SDA_PDD2,
};
static const unsigned int safe_state_pee0_pins[] = {
TEGRA_PIN_SAFE_STATE_PEE0,
};
static const unsigned int vcomp_alert_pee1_pins[] = {
TEGRA_PIN_VCOMP_ALERT_PEE1,
};
static const unsigned int ao_retention_n_pee2_pins[] = {
TEGRA_PIN_AO_RETENTION_N_PEE2,
};
static const unsigned int batt_oc_pee3_pins[] = {
TEGRA_PIN_BATT_OC_PEE3,
};
static const unsigned int power_on_pee4_pins[] = {
TEGRA_PIN_POWER_ON_PEE4,
};
static const unsigned int pwr_i2c_scl_pee5_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PEE5,
};
static const unsigned int pwr_i2c_sda_pee6_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PEE6,
};
static const unsigned int ufs0_ref_clk_pff0_pins[] = {
TEGRA_PIN_UFS0_REF_CLK_PFF0,
};
static const unsigned int ufs0_rst_pff1_pins[] = {
TEGRA_PIN_UFS0_RST_PFF1,
};
static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
};
static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
TEGRA_PIN_PEX_L5_RST_N_PGG1,
};
static const unsigned int directdc_comp_pins[] = {
TEGRA_PIN_DIRECTDC_COMP,
};
static const unsigned int sdmmc4_clk_pins[] = {
TEGRA_PIN_SDMMC4_CLK,
};
static const unsigned int sdmmc4_cmd_pins[] = {
TEGRA_PIN_SDMMC4_CMD,
};
static const unsigned int sdmmc4_dqs_pins[] = {
TEGRA_PIN_SDMMC4_DQS,
};
static const unsigned int sdmmc4_dat7_pins[] = {
TEGRA_PIN_SDMMC4_DAT7,
};
static const unsigned int sdmmc4_dat6_pins[] = {
TEGRA_PIN_SDMMC4_DAT6,
};
static const unsigned int sdmmc4_dat5_pins[] = {
TEGRA_PIN_SDMMC4_DAT5,
};
static const unsigned int sdmmc4_dat4_pins[] = {
TEGRA_PIN_SDMMC4_DAT4,
};
static const unsigned int sdmmc4_dat3_pins[] = {
TEGRA_PIN_SDMMC4_DAT3,
};
static const unsigned int sdmmc4_dat2_pins[] = {
TEGRA_PIN_SDMMC4_DAT2,
};
static const unsigned int sdmmc4_dat1_pins[] = {
TEGRA_PIN_SDMMC4_DAT1,
};
static const unsigned int sdmmc4_dat0_pins[] = {
TEGRA_PIN_SDMMC4_DAT0,
};
static const unsigned int sdmmc1_comp_pins[] = {
TEGRA_PIN_SDMMC1_COMP,
};
static const unsigned int sdmmc3_comp_pins[] = {
TEGRA_PIN_SDMMC3_COMP,
};
static const unsigned int eqos_comp_pins[] = {
TEGRA_PIN_EQOS_COMP,
};
static const unsigned int qspi_comp_pins[] = {
TEGRA_PIN_QSPI_COMP,
};
static const unsigned int shutdown_n_pins[] = {
TEGRA_PIN_SHUTDOWN_N,
};
static const unsigned int pmu_int_n_pins[] = {
TEGRA_PIN_PMU_INT_N,
};
static const unsigned int soc_pwr_req_pins[] = {
TEGRA_PIN_SOC_PWR_REQ,
};
static const unsigned int clk_32k_in_pins[] = {
TEGRA_PIN_CLK_32K_IN,
};
/* Define unique ID for each function */
enum tegra_mux_dt {
TEGRA_MUX_RSVD0,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_TOUCH,
TEGRA_MUX_UARTC,
TEGRA_MUX_I2C8,
TEGRA_MUX_UARTG,
TEGRA_MUX_SPI2,
TEGRA_MUX_GP,
TEGRA_MUX_DCA,
TEGRA_MUX_WDT,
TEGRA_MUX_I2C2,
TEGRA_MUX_CAN1,
TEGRA_MUX_CAN0,
TEGRA_MUX_DMIC3,
TEGRA_MUX_DMIC5,
TEGRA_MUX_GPIO,
TEGRA_MUX_DSPK1,
TEGRA_MUX_DSPK0,
TEGRA_MUX_SPDIF,
TEGRA_MUX_AUD,
TEGRA_MUX_I2S1,
TEGRA_MUX_DMIC1,
TEGRA_MUX_DMIC2,
TEGRA_MUX_I2S3,
TEGRA_MUX_DMIC4,
TEGRA_MUX_I2S4,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_I2C3,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_SLVS,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_EXTPERIPH4,
TEGRA_MUX_I2S2,
TEGRA_MUX_UARTD,
TEGRA_MUX_I2C1,
TEGRA_MUX_UARTA,
TEGRA_MUX_DIRECTDC1,
TEGRA_MUX_DIRECTDC,
TEGRA_MUX_IQC1,
TEGRA_MUX_IQC2,
TEGRA_MUX_I2S6,
TEGRA_MUX_SDMMC3,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_DP,
TEGRA_MUX_HDMI,
TEGRA_MUX_PE2,
TEGRA_MUX_IGPU,
TEGRA_MUX_SATA,
TEGRA_MUX_PE1,
TEGRA_MUX_PE0,
TEGRA_MUX_PE3,
TEGRA_MUX_PE4,
TEGRA_MUX_PE5,
TEGRA_MUX_SOC,
TEGRA_MUX_EQOS,
TEGRA_MUX_QSPI,
TEGRA_MUX_QSPI0,
TEGRA_MUX_QSPI1,
TEGRA_MUX_MIPI,
TEGRA_MUX_SCE,
TEGRA_MUX_I2C5,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DCB,
TEGRA_MUX_SPI1,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTE,
TEGRA_MUX_SPI3,
TEGRA_MUX_NV,
TEGRA_MUX_CCLA,
TEGRA_MUX_I2S5,
TEGRA_MUX_USB,
TEGRA_MUX_UFS0,
TEGRA_MUX_DGPU,
TEGRA_MUX_SDMMC4,
};
/* Make list of each function name */
#define TEGRA_PIN_FUNCTION(lid) #lid
static const char * const tegra194_functions[] = {
TEGRA_PIN_FUNCTION(rsvd0),
TEGRA_PIN_FUNCTION(rsvd1),
TEGRA_PIN_FUNCTION(rsvd2),
TEGRA_PIN_FUNCTION(rsvd3),
TEGRA_PIN_FUNCTION(touch),
TEGRA_PIN_FUNCTION(uartc),
TEGRA_PIN_FUNCTION(i2c8),
TEGRA_PIN_FUNCTION(uartg),
TEGRA_PIN_FUNCTION(spi2),
TEGRA_PIN_FUNCTION(gp),
TEGRA_PIN_FUNCTION(dca),
TEGRA_PIN_FUNCTION(wdt),
TEGRA_PIN_FUNCTION(i2c2),
TEGRA_PIN_FUNCTION(can1),
TEGRA_PIN_FUNCTION(can0),
TEGRA_PIN_FUNCTION(dmic3),
TEGRA_PIN_FUNCTION(dmic5),
TEGRA_PIN_FUNCTION(gpio),
TEGRA_PIN_FUNCTION(dspk1),
TEGRA_PIN_FUNCTION(dspk0),
TEGRA_PIN_FUNCTION(spdif),
TEGRA_PIN_FUNCTION(aud),
TEGRA_PIN_FUNCTION(i2s1),
TEGRA_PIN_FUNCTION(dmic1),
TEGRA_PIN_FUNCTION(dmic2),
TEGRA_PIN_FUNCTION(i2s3),
TEGRA_PIN_FUNCTION(dmic4),
TEGRA_PIN_FUNCTION(i2s4),
TEGRA_PIN_FUNCTION(extperiph2),
TEGRA_PIN_FUNCTION(extperiph1),
TEGRA_PIN_FUNCTION(i2c3),
TEGRA_PIN_FUNCTION(vgp1),
TEGRA_PIN_FUNCTION(vgp2),
TEGRA_PIN_FUNCTION(vgp3),
TEGRA_PIN_FUNCTION(vgp4),
TEGRA_PIN_FUNCTION(vgp5),
TEGRA_PIN_FUNCTION(vgp6),
TEGRA_PIN_FUNCTION(slvs),
TEGRA_PIN_FUNCTION(extperiph3),
TEGRA_PIN_FUNCTION(extperiph4),
TEGRA_PIN_FUNCTION(i2s2),
TEGRA_PIN_FUNCTION(uartd),
TEGRA_PIN_FUNCTION(i2c1),
TEGRA_PIN_FUNCTION(uarta),
TEGRA_PIN_FUNCTION(directdc1),
TEGRA_PIN_FUNCTION(directdc),
TEGRA_PIN_FUNCTION(iqc1),
TEGRA_PIN_FUNCTION(iqc2),
TEGRA_PIN_FUNCTION(i2s6),
TEGRA_PIN_FUNCTION(sdmmc3),
TEGRA_PIN_FUNCTION(sdmmc1),
TEGRA_PIN_FUNCTION(dp),
TEGRA_PIN_FUNCTION(hdmi),
TEGRA_PIN_FUNCTION(pe2),
TEGRA_PIN_FUNCTION(igpu),
TEGRA_PIN_FUNCTION(sata),
TEGRA_PIN_FUNCTION(pe1),
TEGRA_PIN_FUNCTION(pe0),
TEGRA_PIN_FUNCTION(pe3),
TEGRA_PIN_FUNCTION(pe4),
TEGRA_PIN_FUNCTION(pe5),
TEGRA_PIN_FUNCTION(soc),
TEGRA_PIN_FUNCTION(eqos),
TEGRA_PIN_FUNCTION(qspi),
TEGRA_PIN_FUNCTION(qspi0),
TEGRA_PIN_FUNCTION(qspi1),
TEGRA_PIN_FUNCTION(mipi),
TEGRA_PIN_FUNCTION(sce),
TEGRA_PIN_FUNCTION(i2c5),
TEGRA_PIN_FUNCTION(displaya),
TEGRA_PIN_FUNCTION(displayb),
TEGRA_PIN_FUNCTION(dcb),
TEGRA_PIN_FUNCTION(spi1),
TEGRA_PIN_FUNCTION(uartb),
TEGRA_PIN_FUNCTION(uarte),
TEGRA_PIN_FUNCTION(spi3),
TEGRA_PIN_FUNCTION(nv),
TEGRA_PIN_FUNCTION(ccla),
TEGRA_PIN_FUNCTION(i2s5),
TEGRA_PIN_FUNCTION(usb),
TEGRA_PIN_FUNCTION(ufs0),
TEGRA_PIN_FUNCTION(dgpu),
TEGRA_PIN_FUNCTION(sdmmc4),
};
#define PINGROUP_REG_Y(r) ((r))
#define PINGROUP_REG_N(r) -1
#define DRV_PINGROUP_Y(r) ((r))
#define DRV_PINGROUP_N(r) -1
#define DRV_PINGROUP_ENTRY_N(pg_name) \
.drv_reg = -1, \
.drv_bank = -1, \
.drvdn_bit = -1, \
.drvup_bit = -1, \
.slwr_bit = -1, \
.slwf_bit = -1
#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
drvup_w, slwr_b, slwr_w, slwf_b, \
slwf_w, bank) \
.drv_reg = ((r)), \
.drv_bank = bank, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w
#define PIN_PINGROUP_ENTRY_N(pg_name) \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.e_io_hv_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.parked_bit = -1, \
.lpmd_bit = -1, \
.drvtype_bit = -1, \
.lpdr_bit = -1, \
.pbias_buf_bit = -1, \
.preemp_bit = -1, \
.rfu_in_bit = -1
#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
e_lpdr, e_pbias_buf, gpio_sfio_sel, \
e_od, schmitt_b, drvtype, epreemp, \
io_reset, rfu_in, io_rail) \
.mux_reg = PINGROUP_REG_Y(r), \
.lpmd_bit = -1, \
.lock_bit = -1, \
.hsm_bit = -1, \
.mux_bank = bank, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG_##pupd(r), \
.pupd_bank = bank, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG_Y(r), \
.tri_bank = bank, \
.tri_bit = 4, \
.einput_bit = e_input, \
.sfsel_bit = gpio_sfio_sel, \
.odrain_bit = e_od, \
.schmitt_bit = schmitt_b, \
.drvtype_bit = 13, \
.lpdr_bit = e_lpdr, \
/* main drive pin groups */
#define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap3_fs_pt4 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap3_din_pt3 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap3_dout_pt2 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap3_sclk_pt1 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap5_fs_pu0 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap5_din_pt7 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap5_dout_pt6 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap5_sclk_pt5 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap6_fs_pa3 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap6_din_pa2 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap6_dout_pa1 DRV_PINGROUP_ENTRY_Y(0x2014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap6_sclk_pa0 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap4_fs_pa7 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap4_din_pa6 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap4_dout_pa5 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_dap4_sclk_pa4 DRV_PINGROUP_ENTRY_Y(0x203c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_extperiph2_clk_pp1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_extperiph1_clk_pp0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cam_i2c_sda_pp3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cam_i2c_scl_pp2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio40_pq4 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio41_pq5 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio42_pq6 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio43_pq7 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio44_pr0 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio45_pr1 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio20_pq0 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio21_pq1 DRV_PINGROUP_ENTRY_Y(0x005c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio22_pq2 DRV_PINGROUP_ENTRY_Y(0x0064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio23_pq3 DRV_PINGROUP_ENTRY_Y(0x006c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio04_pp4 DRV_PINGROUP_ENTRY_Y(0x0074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio05_pp5 DRV_PINGROUP_ENTRY_Y(0x007c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio06_pp6 DRV_PINGROUP_ENTRY_Y(0x0084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio07_pp7 DRV_PINGROUP_ENTRY_Y(0x008c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_cts_pr5 DRV_PINGROUP_ENTRY_Y(0x0094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_rts_pr4 DRV_PINGROUP_ENTRY_Y(0x009c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_rx_pr3 DRV_PINGROUP_ENTRY_Y(0x00a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_tx_pr2 DRV_PINGROUP_ENTRY_Y(0x00ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap2_din_pi1 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap2_dout_pi0 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap2_fs_pi2 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap2_sclk_ph7 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_cts_ph6 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_rts_ph5 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_rx_ph4 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_tx_ph3 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio03_pg3 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio02_pg2 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio01_pg1 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio00_pg0 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen1_i2c_scl_pi3 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen1_i2c_sda_pi4 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio08_pg4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio09_pg5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio10_pg6 DRV_PINGROUP_ENTRY_Y(0x4084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio11_pg7 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio12_ph0 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio13_ph1 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio14_ph2 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio50_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio51_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio52_pm7 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio53_pn0 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio54_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio55_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch2_hpd_pm2 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch3_hpd_pm3 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_hdmi_cec_pm4 DRV_PINGROUP_ENTRY_Y(0x10054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l2_clkreq_n_pk4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_wake_n_pl2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l1_clkreq_n_pk2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l1_rst_n_pk3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l0_clkreq_n_pk0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l0_rst_n_pk1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l2_rst_n_pk5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l3_clkreq_n_pk6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l3_rst_n_pk7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l4_clkreq_n_pl0 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l4_rst_n_pl1 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_sata_dev_slp_pl3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l5_clkreq_n_pgg0 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l5_rst_n_pgg1 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cpu_pwr_req_1_pb1 DRV_PINGROUP_ENTRY_Y(0x16004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cpu_pwr_req_0_pb0 DRV_PINGROUP_ENTRY_Y(0x1600c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_sdmmc1_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x8004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc1_cmd_pj1 DRV_PINGROUP_ENTRY_Y(0x800c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc1_dat3_pj5 DRV_PINGROUP_ENTRY_Y(0x801c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc1_dat2_pj4 DRV_PINGROUP_ENTRY_Y(0x8024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc1_dat1_pj3 DRV_PINGROUP_ENTRY_Y(0x802c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc1_dat0_pj2 DRV_PINGROUP_ENTRY_Y(0x8034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_dat3_po5 DRV_PINGROUP_ENTRY_Y(0xa004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_dat2_po4 DRV_PINGROUP_ENTRY_Y(0xa00c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_dat1_po3 DRV_PINGROUP_ENTRY_Y(0xa014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_cs0_py3 DRV_PINGROUP_ENTRY_Y(0xD01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_miso_pz4 DRV_PINGROUP_ENTRY_Y(0xD024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_cs1_py4 DRV_PINGROUP_ENTRY_Y(0xD02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gp_pwm3_px3 DRV_PINGROUP_ENTRY_Y(0xD034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gp_pwm2_px2 DRV_PINGROUP_ENTRY_Y(0xD03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_sck_pz3 DRV_PINGROUP_ENTRY_Y(0xD044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_sck_py0 DRV_PINGROUP_ENTRY_Y(0xD04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_cs1_pz7 DRV_PINGROUP_ENTRY_Y(0xD054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_mosi_pz5 DRV_PINGROUP_ENTRY_Y(0xD05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_mosi_py2 DRV_PINGROUP_ENTRY_Y(0xD064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cv_pwr_req_px1 DRV_PINGROUP_ENTRY_Y(0xD06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_tx_px4 DRV_PINGROUP_ENTRY_Y(0xD074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_rx_px5 DRV_PINGROUP_ENTRY_Y(0xD07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_rts_px6 DRV_PINGROUP_ENTRY_Y(0xD084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_cts_px7 DRV_PINGROUP_ENTRY_Y(0xD08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_rx_py6 DRV_PINGROUP_ENTRY_Y(0xD094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_tx_py5 DRV_PINGROUP_ENTRY_Y(0xD09c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_rts_py7 DRV_PINGROUP_ENTRY_Y(0xD0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_cts_pz0 DRV_PINGROUP_ENTRY_Y(0xD0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_usb_vbus_en0_pz1 DRV_PINGROUP_ENTRY_Y(0xD0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_usb_vbus_en1_pz2 DRV_PINGROUP_ENTRY_Y(0xD0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_ufs0_rst_pff1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 9, 24, 8, -1, -1, -1, -1, 0)
#define drive_ufs0_ref_clk_pff0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
#define drive_directdc_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc3_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_clk DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_cmd DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dqs DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc4_dat0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_cs_n_pc7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_sck_pc6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io0_pd0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io1_pd1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io2_pd2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io3_pd3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io0_pc2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io1_pc3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io2_pc4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io3_pc5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_cs_n_pc1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_sck_pc0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_sma_mdc_pf5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_sma_mdio_pf4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out7_pw1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out6_pw0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out5_pv7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out4_pv6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out3_pv5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out2_pv4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out1_pv3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_out0_pv2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry)
/* AON drive pin groups */
#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
e_input, e_lpdr, e_pbias_buf, \
gpio_sfio_sel, e_od, \
schmitt_b, drvtype, \
epreemp, io_reset, \
rfu_in, io_rail) \
drive_##pg_name, \
}
static const struct tegra_pingroup tegra194_groups[] = {
PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(soc_gpio30_ps5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(aud_mclk_ps4, AUD, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap1_fs_ps3, I2S1, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap1_din_ps2, I2S1, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap1_dout_ps1, I2S1, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap1_sclk_ps0, I2S1, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap3_fs_pt4, I2S3, DMIC2, RSVD2, RSVD3, 0x1048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap3_din_pt3, I2S3, DMIC2, RSVD2, RSVD3, 0x1050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap3_dout_pt2, I2S3, DMIC1, RSVD2, RSVD3, 0x1058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap3_sclk_pt1, I2S3, DMIC1, RSVD2, RSVD3, 0x1060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap5_fs_pu0, I2S5, DMIC4, DSPK1, RSVD3, 0x1068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap5_din_pt7, I2S5, DMIC4, DSPK1, RSVD3, 0x1070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap5_dout_pt6, I2S5, DSPK0, RSVD2, RSVD3, 0x1078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap5_sclk_pt5, I2S5, DSPK0, RSVD2, RSVD3, 0x1080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(dap6_fs_pa3, I2S6, IQC1, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap6_din_pa2, I2S6, IQC1, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap6_dout_pa1, I2S6, IQC1, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap6_sclk_pa0, I2S6, IQC1, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap4_fs_pa7, I2S4, IQC2, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap4_din_pa6, I2S4, IQC2, RSVD2, RSVD3, 0x2028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap4_dout_pa5, I2S4, IQC2, RSVD2, RSVD3, 0x2030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(dap4_sclk_pa4, I2S4, IQC2, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_audio_hv"),
PINGROUP(extperiph2_clk_pp1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(extperiph1_clk_pp0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(cam_i2c_sda_pp3, I2C3, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(cam_i2c_scl_pp2, I2C3, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio40_pq4, VGP1, SLVS, RSVD2, RSVD3, 0x0020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio41_pq5, VGP2, EXTPERIPH3, RSVD2, RSVD3, 0x0028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio42_pq6, VGP3, EXTPERIPH4, RSVD2, RSVD3, 0x0030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio43_pq7, VGP4, SLVS, RSVD2, RSVD3, 0x0038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio44_pr0, VGP5, GP, RSVD2, RSVD3, 0x0040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio45_pr1, VGP6, RSVD1, RSVD2, RSVD3, 0x0048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio20_pq0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio21_pq1, RSVD0, RSVD1, RSVD2, RSVD3, 0x0058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio22_pq2, RSVD0, NV, RSVD2, RSVD3, 0x0060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio23_pq3, RSVD0, WDT, RSVD2, RSVD3, 0x0068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio04_pp4, RSVD0, RSVD1, RSVD2, RSVD3, 0x0070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio05_pp5, RSVD0, IGPU, RSVD2, RSVD3, 0x0078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio06_pp6, RSVD0, RSVD1, RSVD2, RSVD3, 0x0080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(soc_gpio07_pp7, RSVD0, SATA, SOC, RSVD3, 0x0088, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(uart1_cts_pr5, UARTA, RSVD1, RSVD2, RSVD3, 0x0090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(uart1_rts_pr4, UARTA, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(uart1_rx_pr3, UARTA, RSVD1, RSVD2, RSVD3, 0x00a0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(uart1_tx_pr2, UARTA, RSVD1, RSVD2, RSVD3, 0x00a8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_cam"),
PINGROUP(dap2_din_pi1, I2S2, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(dap2_dout_pi0, I2S2, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(dap2_fs_pi2, I2S2, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(dap2_sclk_ph7, I2S2, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(uart4_cts_ph6, UARTD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(uart4_rts_ph5, UARTD, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(uart4_rx_ph4, UARTD, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(uart4_tx_ph3, UARTD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio03_pg3, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio02_pg2, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio01_pg1, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio00_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(gen1_i2c_scl_pi3, I2C1, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(gen1_i2c_sda_pi4, I2C1, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio08_pg4, RSVD0, CCLA, RSVD2, RSVD3, 0x4070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio09_pg5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio10_pg6, GP, RSVD1, RSVD2, RSVD3, 0x4080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio11_pg7, RSVD0, SDMMC1, RSVD2, RSVD3, 0x4088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio12_ph0, RSVD0, GP, RSVD2, RSVD3, 0x4090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio13_ph1, RSVD0, GP, RSVD2, RSVD3, 0x4098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(soc_gpio14_ph2, RSVD0, SDMMC1, RSVD2, RSVD3, 0x40a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_conn"),
PINGROUP(directdc1_out7_pw1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out6_pw0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out5_pv7, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out4_pv6, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out3_pv5, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out2_pv4, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out1_pv3, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_out0_pv2, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_in_pv1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc1_clk_pv0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_debug"),
PINGROUP(directdc_comp, DIRECTDC, RSVD1, RSVD2, RSVD3, 0x5058, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_debug"),
PINGROUP(soc_gpio50_pm5, RSVD0, DCA, RSVD2, RSVD3, 0x10000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(soc_gpio51_pm6, RSVD0, DCA, RSVD2, RSVD3, 0x10008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(soc_gpio52_pm7, RSVD0, DCB, DGPU, RSVD3, 0x10010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(soc_gpio53_pn0, RSVD0, DCB, RSVD2, RSVD3, 0x10018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(soc_gpio54_pn1, RSVD0, SDMMC3, GP, RSVD3, 0x10020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(soc_gpio55_pn2, RSVD0, SDMMC3, RSVD2, RSVD3, 0x10028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(dp_aux_ch0_hpd_pm0, DP, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(dp_aux_ch1_hpd_pm1, DP, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(dp_aux_ch2_hpd_pm2, DP, DISPLAYA, RSVD2, RSVD3, 0x10040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(dp_aux_ch3_hpd_pm3, DP, DISPLAYB, RSVD2, RSVD3, 0x10048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(hdmi_cec_pm4, HDMI, RSVD1, RSVD2, RSVD3, 0x10050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_edp"),
PINGROUP(eqos_td3_pe4, EQOS, RSVD1, RSVD2, RSVD3, 0x15000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_td2_pe3, EQOS, RSVD1, RSVD2, RSVD3, 0x15008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_td1_pe2, EQOS, RSVD1, RSVD2, RSVD3, 0x15010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_td0_pe1, EQOS, RSVD1, RSVD2, RSVD3, 0x15018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rd3_pf1, EQOS, RSVD1, RSVD2, RSVD3, 0x15020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rd2_pf0, EQOS, RSVD1, RSVD2, RSVD3, 0x15028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rd1_pe7, EQOS, RSVD1, RSVD2, RSVD3, 0x15030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_sma_mdio_pf4, EQOS, RSVD1, RSVD2, RSVD3, 0x15038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rd0_pe6, EQOS, RSVD1, RSVD2, RSVD3, 0x15040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_sma_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x15048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_comp, EQOS, RSVD1, RSVD2, RSVD3, 0x15050, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_eqos"),
PINGROUP(eqos_txc_pe0, EQOS, RSVD1, RSVD2, RSVD3, 0x15058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rxc_pf3, EQOS, RSVD1, RSVD2, RSVD3, 0x15060, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_tx_ctl_pe5, EQOS, RSVD1, RSVD2, RSVD3, 0x15068, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(eqos_rx_ctl_pf2, EQOS, RSVD1, RSVD2, RSVD3, 0x15070, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_eqos"),
PINGROUP(pex_l2_clkreq_n_pk4, PE2, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_wake_n_pl2, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l1_clkreq_n_pk2, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l1_rst_n_pk3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l0_clkreq_n_pk0, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l0_rst_n_pk1, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l2_rst_n_pk5, PE2, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l3_clkreq_n_pk6, PE3, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l3_rst_n_pk7, PE3, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l4_clkreq_n_pl0, PE4, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l4_rst_n_pl1, PE4, RSVD1, RSVD2, RSVD3, 0x7050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(sata_dev_slp_pl3, SATA, RSVD1, RSVD2, RSVD3, 0x7058, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl"),
PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl_2"),
PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pex_ctl_2"),
PINGROUP(cpu_pwr_req_1_pb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x16000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pwr_ctl"),
PINGROUP(cpu_pwr_req_0_pb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x16008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_pwr_ctl"),
PINGROUP(qspi0_io3_pc5, QSPI0, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi0_io2_pc4, QSPI0, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi0_io1_pc3, QSPI0, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi0_io0_pc2, QSPI0, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi0_sck_pc0, QSPI0, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi0_cs_n_pc1, QSPI0, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_io3_pd3, QSPI1, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_io2_pd2, QSPI1, RSVD1, RSVD2, RSVD3, 0xB038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_io1_pd1, QSPI1, RSVD1, RSVD2, RSVD3, 0xB040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_io0_pd0, QSPI1, RSVD1, RSVD2, RSVD3, 0xB048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_sck_pc6, QSPI1, RSVD1, RSVD2, RSVD3, 0xB050, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi1_cs_n_pc7, QSPI1, RSVD1, RSVD2, RSVD3, 0xB058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_qspi"),
PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB060, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y, "vddio_qspi"),
PINGROUP(sdmmc1_clk_pj0, SDMMC1, RSVD1, MIPI, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_cmd_pj1, SDMMC1, RSVD1, MIPI, RSVD3, 0x8008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_dat3_pj5, SDMMC1, RSVD1, MIPI, RSVD3, 0x8018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_dat2_pj4, SDMMC1, RSVD1, MIPI, RSVD3, 0x8020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_dat1_pj3, SDMMC1, RSVD1, MIPI, RSVD3, 0x8028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc1_dat0_pj2, SDMMC1, RSVD1, MIPI, RSVD3, 0x8030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc1_hv"),
PINGROUP(sdmmc3_dat3_po5, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_dat2_po4, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_dat1_po3, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_dat0_po2, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_comp, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA020, 0, N, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_cmd_po1, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc3_clk_po0, SDMMC3, RSVD1, RSVD2, RSVD3, 0xA030, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_sdmmc3_hv"),
PINGROUP(sdmmc4_clk, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, -1, 5, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_cmd, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dqs, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, N, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat7, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6020, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat6, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6028, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat5, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6030, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat4, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6038, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat3, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_cs0_py3, SPI3, RSVD1, RSVD2, RSVD3, 0xD018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_miso_pz4, SPI1, RSVD1, RSVD2, RSVD3, 0xD020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_cs1_py4, SPI3, RSVD1, RSVD2, RSVD3, 0xD028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(gp_pwm3_px3, GP, RSVD1, RSVD2, RSVD3, 0xD030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(gp_pwm2_px2, GP, RSVD1, RSVD2, RSVD3, 0xD038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_sck_pz3, SPI1, RSVD1, RSVD2, RSVD3, 0xD040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_sck_py0, SPI3, RSVD1, RSVD2, RSVD3, 0xD048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_cs1_pz7, SPI1, RSVD1, RSVD2, RSVD3, 0xD050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_mosi_pz5, SPI1, RSVD1, RSVD2, RSVD3, 0xD058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_mosi_py2, SPI3, RSVD1, RSVD2, RSVD3, 0xD060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(cv_pwr_req_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0xD068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart2_tx_px4, UARTB, RSVD1, RSVD2, RSVD3, 0xD070, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart2_rx_px5, UARTB, RSVD1, RSVD2, RSVD3, 0xD078, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart2_rts_px6, UARTB, RSVD1, RSVD2, RSVD3, 0xD080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart2_cts_px7, UARTB, RSVD1, RSVD2, RSVD3, 0xD088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart5_rx_py6, UARTE, RSVD1, RSVD2, RSVD3, 0xD090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart5_tx_py5, UARTE, RSVD1, RSVD2, RSVD3, 0xD098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart5_rts_py7, UARTE, RSVD1, RSVD2, RSVD3, 0xD0a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(uart5_cts_pz0, UARTE, RSVD1, RSVD2, RSVD3, 0xD0a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(usb_vbus_en0_pz1, USB, RSVD1, RSVD2, RSVD3, 0xD0b0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(usb_vbus_en1_pz2, USB, RSVD1, RSVD2, RSVD3, 0xD0b8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(ufs0_rst_pff1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_ufs"),
PINGROUP(ufs0_ref_clk_pff0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y, "vddio_ufs"),
};
static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
.pins = tegra194_pins,
.npins = ARRAY_SIZE(tegra194_pins),
.functions = tegra194_functions,
.nfunctions = ARRAY_SIZE(tegra194_functions),
.groups = tegra194_groups,
.ngroups = ARRAY_SIZE(tegra194_groups),
.hsm_in_mux = true,
.schmitt_in_mux = true,
.drvtype_in_mux = true,
.sfsel_in_mux = true,
};
static const struct pinctrl_pin_desc tegra194_aon_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
};
static const struct tegra_pingroup tegra194_aon_groups[] = {
PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
};
static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = {
.pins = tegra194_aon_pins,
.npins = ARRAY_SIZE(tegra194_aon_pins),
.functions = tegra194_functions,
.nfunctions = ARRAY_SIZE(tegra194_functions),
.groups = tegra194_aon_groups,
.ngroups = ARRAY_SIZE(tegra194_aon_groups),
.hsm_in_mux = true,
.schmitt_in_mux = true,
.drvtype_in_mux = true,
.sfsel_in_mux = true,
};
static int tegra194_pinctrl_probe(struct platform_device *pdev)
{
const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
return tegra_pinctrl_probe(pdev, soc);
}
static const struct of_device_id tegra194_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl },
{ .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon },
{ },
};
static struct platform_driver tegra194_pinctrl_driver = {
.driver = {
.name = "tegra194-pinctrl",
.of_match_table = tegra194_pinctrl_of_match,
},
.probe = tegra194_pinctrl_probe,
};
static int __init tegra194_pinctrl_init(void)
{
return platform_driver_register(&tegra194_pinctrl_driver);
}
arch_initcall(tegra194_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra194.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for the NVIDIA Tegra20 pinmux
*
* Author: Stephen Warren <[email protected]>
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
*/
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
#define TEGRA_PIN_PU0 _GPIO(160)
#define TEGRA_PIN_PU1 _GPIO(161)
#define TEGRA_PIN_PU2 _GPIO(162)
#define TEGRA_PIN_PU3 _GPIO(163)
#define TEGRA_PIN_PU4 _GPIO(164)
#define TEGRA_PIN_PU5 _GPIO(165)
#define TEGRA_PIN_PU6 _GPIO(166)
#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
#define TEGRA_PIN_PV0 _GPIO(168)
#define TEGRA_PIN_PV1 _GPIO(169)
#define TEGRA_PIN_PV2 _GPIO(170)
#define TEGRA_PIN_PV3 _GPIO(171)
#define TEGRA_PIN_PV4 _GPIO(172)
#define TEGRA_PIN_PV5 _GPIO(173)
#define TEGRA_PIN_PV6 _GPIO(174)
#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
#define TEGRA_PIN_PBB6 _GPIO(222)
#define TEGRA_PIN_PBB7 _GPIO(223)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
#define TEGRA_PIN_CRT_HSYNC _PIN(30)
#define TEGRA_PIN_CRT_VSYNC _PIN(31)
#define TEGRA_PIN_DDC_SCL _PIN(32)
#define TEGRA_PIN_DDC_SDA _PIN(33)
#define TEGRA_PIN_OWC _PIN(34)
#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
#define TEGRA_PIN_PWR_INT_N _PIN(37)
#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
#define TEGRA_PIN_DDR_A0 _PIN(41)
#define TEGRA_PIN_DDR_A1 _PIN(42)
#define TEGRA_PIN_DDR_A2 _PIN(43)
#define TEGRA_PIN_DDR_A3 _PIN(44)
#define TEGRA_PIN_DDR_A4 _PIN(45)
#define TEGRA_PIN_DDR_A5 _PIN(46)
#define TEGRA_PIN_DDR_A6 _PIN(47)
#define TEGRA_PIN_DDR_A7 _PIN(48)
#define TEGRA_PIN_DDR_A8 _PIN(49)
#define TEGRA_PIN_DDR_A9 _PIN(50)
#define TEGRA_PIN_DDR_A10 _PIN(51)
#define TEGRA_PIN_DDR_A11 _PIN(52)
#define TEGRA_PIN_DDR_A12 _PIN(53)
#define TEGRA_PIN_DDR_A13 _PIN(54)
#define TEGRA_PIN_DDR_A14 _PIN(55)
#define TEGRA_PIN_DDR_CAS_N _PIN(56)
#define TEGRA_PIN_DDR_BA0 _PIN(57)
#define TEGRA_PIN_DDR_BA1 _PIN(58)
#define TEGRA_PIN_DDR_BA2 _PIN(59)
#define TEGRA_PIN_DDR_DQS0P _PIN(60)
#define TEGRA_PIN_DDR_DQS0N _PIN(61)
#define TEGRA_PIN_DDR_DQS1P _PIN(62)
#define TEGRA_PIN_DDR_DQS1N _PIN(63)
#define TEGRA_PIN_DDR_DQS2P _PIN(64)
#define TEGRA_PIN_DDR_DQS2N _PIN(65)
#define TEGRA_PIN_DDR_DQS3P _PIN(66)
#define TEGRA_PIN_DDR_DQS3N _PIN(67)
#define TEGRA_PIN_DDR_CKE0 _PIN(68)
#define TEGRA_PIN_DDR_CKE1 _PIN(69)
#define TEGRA_PIN_DDR_CLK _PIN(70)
#define TEGRA_PIN_DDR_CLK_N _PIN(71)
#define TEGRA_PIN_DDR_DM0 _PIN(72)
#define TEGRA_PIN_DDR_DM1 _PIN(73)
#define TEGRA_PIN_DDR_DM2 _PIN(74)
#define TEGRA_PIN_DDR_DM3 _PIN(75)
#define TEGRA_PIN_DDR_ODT _PIN(76)
#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
#define TEGRA_PIN_DDR_RAS_N _PIN(81)
#define TEGRA_PIN_DDR_WE_N _PIN(82)
#define TEGRA_PIN_DDR_DQ0 _PIN(83)
#define TEGRA_PIN_DDR_DQ1 _PIN(84)
#define TEGRA_PIN_DDR_DQ2 _PIN(85)
#define TEGRA_PIN_DDR_DQ3 _PIN(86)
#define TEGRA_PIN_DDR_DQ4 _PIN(87)
#define TEGRA_PIN_DDR_DQ5 _PIN(88)
#define TEGRA_PIN_DDR_DQ6 _PIN(89)
#define TEGRA_PIN_DDR_DQ7 _PIN(90)
#define TEGRA_PIN_DDR_DQ8 _PIN(91)
#define TEGRA_PIN_DDR_DQ9 _PIN(92)
#define TEGRA_PIN_DDR_DQ10 _PIN(93)
#define TEGRA_PIN_DDR_DQ11 _PIN(94)
#define TEGRA_PIN_DDR_DQ12 _PIN(95)
#define TEGRA_PIN_DDR_DQ13 _PIN(96)
#define TEGRA_PIN_DDR_DQ14 _PIN(97)
#define TEGRA_PIN_DDR_DQ15 _PIN(98)
#define TEGRA_PIN_DDR_DQ16 _PIN(99)
#define TEGRA_PIN_DDR_DQ17 _PIN(100)
#define TEGRA_PIN_DDR_DQ18 _PIN(101)
#define TEGRA_PIN_DDR_DQ19 _PIN(102)
#define TEGRA_PIN_DDR_DQ20 _PIN(103)
#define TEGRA_PIN_DDR_DQ21 _PIN(104)
#define TEGRA_PIN_DDR_DQ22 _PIN(105)
#define TEGRA_PIN_DDR_DQ23 _PIN(106)
#define TEGRA_PIN_DDR_DQ24 _PIN(107)
#define TEGRA_PIN_DDR_DQ25 _PIN(108)
#define TEGRA_PIN_DDR_DQ26 _PIN(109)
#define TEGRA_PIN_DDR_DQ27 _PIN(110)
#define TEGRA_PIN_DDR_DQ28 _PIN(111)
#define TEGRA_PIN_DDR_DQ29 _PIN(112)
#define TEGRA_PIN_DDR_DQ30 _PIN(113)
#define TEGRA_PIN_DDR_DQ31 _PIN(114)
#define TEGRA_PIN_DDR_CS0_N _PIN(115)
#define TEGRA_PIN_DDR_CS1_N _PIN(116)
#define TEGRA_PIN_SYS_RESET _PIN(117)
#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
#define TEGRA_PIN_JTAG_TDO _PIN(119)
#define TEGRA_PIN_JTAG_TMS _PIN(120)
#define TEGRA_PIN_JTAG_TCK _PIN(121)
#define TEGRA_PIN_JTAG_TDI _PIN(122)
#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
static const struct pinctrl_pin_desc tegra20_pins[] = {
PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
/* PU0..6: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
/* PV0..1: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
/* PV2..3: Balls are named after GPIO not function */
PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
/* PV4..6: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
};
static const unsigned ata_pins[] = {
TEGRA_PIN_GMI_CS6_N_PI3,
TEGRA_PIN_GMI_CS7_N_PI6,
TEGRA_PIN_GMI_RST_N_PI4,
};
static const unsigned atb_pins[] = {
TEGRA_PIN_GMI_CS5_N_PI2,
TEGRA_PIN_GMI_DPD_PT7,
};
static const unsigned atc_pins[] = {
TEGRA_PIN_GMI_IORDY_PI5,
TEGRA_PIN_GMI_WAIT_PI7,
TEGRA_PIN_GMI_ADV_N_PK0,
TEGRA_PIN_GMI_CLK_PK1,
TEGRA_PIN_GMI_CS2_N_PK3,
TEGRA_PIN_GMI_CS3_N_PK4,
TEGRA_PIN_GMI_CS4_N_PK2,
TEGRA_PIN_GMI_AD0_PG0,
TEGRA_PIN_GMI_AD1_PG1,
TEGRA_PIN_GMI_AD2_PG2,
TEGRA_PIN_GMI_AD3_PG3,
TEGRA_PIN_GMI_AD4_PG4,
TEGRA_PIN_GMI_AD5_PG5,
TEGRA_PIN_GMI_AD6_PG6,
TEGRA_PIN_GMI_AD7_PG7,
TEGRA_PIN_GMI_HIOW_N_PI0,
TEGRA_PIN_GMI_HIOR_N_PI1,
};
static const unsigned atd_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
TEGRA_PIN_GMI_AD9_PH1,
TEGRA_PIN_GMI_AD10_PH2,
TEGRA_PIN_GMI_AD11_PH3,
};
static const unsigned ate_pins[] = {
TEGRA_PIN_GMI_AD12_PH4,
TEGRA_PIN_GMI_AD13_PH5,
TEGRA_PIN_GMI_AD14_PH6,
TEGRA_PIN_GMI_AD15_PH7,
};
static const unsigned cdev1_pins[] = {
TEGRA_PIN_DAP_MCLK1_PW4,
};
static const unsigned cdev2_pins[] = {
TEGRA_PIN_DAP_MCLK2_PW5,
};
static const unsigned crtp_pins[] = {
TEGRA_PIN_CRT_HSYNC,
TEGRA_PIN_CRT_VSYNC,
};
static const unsigned csus_pins[] = {
TEGRA_PIN_VI_MCLK_PT1,
};
static const unsigned dap1_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned ddc_pins[] = {
TEGRA_PIN_DDC_SCL,
TEGRA_PIN_DDC_SDA,
};
static const unsigned dta_pins[] = {
TEGRA_PIN_VI_D0_PT4,
TEGRA_PIN_VI_D1_PD5,
};
static const unsigned dtb_pins[] = {
TEGRA_PIN_VI_D10_PT2,
TEGRA_PIN_VI_D11_PT3,
};
static const unsigned dtc_pins[] = {
TEGRA_PIN_VI_HSYNC_PD7,
TEGRA_PIN_VI_VSYNC_PD6,
};
static const unsigned dtd_pins[] = {
TEGRA_PIN_VI_PCLK_PT0,
TEGRA_PIN_VI_D2_PL0,
TEGRA_PIN_VI_D3_PL1,
TEGRA_PIN_VI_D4_PL2,
TEGRA_PIN_VI_D5_PL3,
TEGRA_PIN_VI_D6_PL4,
TEGRA_PIN_VI_D7_PL5,
TEGRA_PIN_VI_D8_PL6,
TEGRA_PIN_VI_D9_PL7,
};
static const unsigned dte_pins[] = {
TEGRA_PIN_VI_GP0_PBB1,
TEGRA_PIN_VI_GP3_PBB4,
TEGRA_PIN_VI_GP4_PBB5,
TEGRA_PIN_VI_GP5_PD2,
TEGRA_PIN_VI_GP6_PA0,
};
static const unsigned dtf_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PBB2,
TEGRA_PIN_CAM_I2C_SDA_PBB3,
};
static const unsigned gma_pins[] = {
TEGRA_PIN_GMI_AD20_PAA0,
TEGRA_PIN_GMI_AD21_PAA1,
TEGRA_PIN_GMI_AD22_PAA2,
TEGRA_PIN_GMI_AD23_PAA3,
};
static const unsigned gmb_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
};
static const unsigned gmc_pins[] = {
TEGRA_PIN_GMI_AD16_PJ7,
TEGRA_PIN_GMI_AD17_PB0,
TEGRA_PIN_GMI_AD18_PB1,
TEGRA_PIN_GMI_AD19_PK7,
};
static const unsigned gmd_pins[] = {
TEGRA_PIN_GMI_CS0_N_PJ0,
TEGRA_PIN_GMI_CS1_N_PJ2,
};
static const unsigned gme_pins[] = {
TEGRA_PIN_GMI_AD24_PAA4,
TEGRA_PIN_GMI_AD25_PAA5,
TEGRA_PIN_GMI_AD26_PAA6,
TEGRA_PIN_GMI_AD27_PAA7,
};
static const unsigned gpu_pins[] = {
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
};
static const unsigned gpu7_pins[] = {
TEGRA_PIN_JTAG_RTCK_PU7,
};
static const unsigned gpv_pins[] = {
TEGRA_PIN_PV4,
TEGRA_PIN_PV5,
TEGRA_PIN_PV6,
};
static const unsigned hdint_pins[] = {
TEGRA_PIN_HDMI_INT_N_PN7,
};
static const unsigned i2cp_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned irrx_pins[] = {
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned irtx_pins[] = {
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned kbca_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
};
static const unsigned kbcb_pins[] = {
TEGRA_PIN_KB_ROW7_PR7,
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_KB_ROW11_PS3,
TEGRA_PIN_KB_ROW12_PS4,
TEGRA_PIN_KB_ROW13_PS5,
TEGRA_PIN_KB_ROW14_PS6,
TEGRA_PIN_KB_ROW15_PS7,
};
static const unsigned kbcc_pins[] = {
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
};
static const unsigned kbcd_pins[] = {
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
};
static const unsigned kbce_pins[] = {
TEGRA_PIN_KB_COL7_PQ7,
};
static const unsigned kbcf_pins[] = {
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
};
static const unsigned lcsn_pins[] = {
TEGRA_PIN_LCD_CS0_N_PN4,
};
static const unsigned ld0_pins[] = {
TEGRA_PIN_LCD_D0_PE0,
};
static const unsigned ld1_pins[] = {
TEGRA_PIN_LCD_D1_PE1,
};
static const unsigned ld2_pins[] = {
TEGRA_PIN_LCD_D2_PE2,
};
static const unsigned ld3_pins[] = {
TEGRA_PIN_LCD_D3_PE3,
};
static const unsigned ld4_pins[] = {
TEGRA_PIN_LCD_D4_PE4,
};
static const unsigned ld5_pins[] = {
TEGRA_PIN_LCD_D5_PE5,
};
static const unsigned ld6_pins[] = {
TEGRA_PIN_LCD_D6_PE6,
};
static const unsigned ld7_pins[] = {
TEGRA_PIN_LCD_D7_PE7,
};
static const unsigned ld8_pins[] = {
TEGRA_PIN_LCD_D8_PF0,
};
static const unsigned ld9_pins[] = {
TEGRA_PIN_LCD_D9_PF1,
};
static const unsigned ld10_pins[] = {
TEGRA_PIN_LCD_D10_PF2,
};
static const unsigned ld11_pins[] = {
TEGRA_PIN_LCD_D11_PF3,
};
static const unsigned ld12_pins[] = {
TEGRA_PIN_LCD_D12_PF4,
};
static const unsigned ld13_pins[] = {
TEGRA_PIN_LCD_D13_PF5,
};
static const unsigned ld14_pins[] = {
TEGRA_PIN_LCD_D14_PF6,
};
static const unsigned ld15_pins[] = {
TEGRA_PIN_LCD_D15_PF7,
};
static const unsigned ld16_pins[] = {
TEGRA_PIN_LCD_D16_PM0,
};
static const unsigned ld17_pins[] = {
TEGRA_PIN_LCD_D17_PM1,
};
static const unsigned ldc_pins[] = {
TEGRA_PIN_LCD_DC0_PN6,
};
static const unsigned ldi_pins[] = {
TEGRA_PIN_LCD_D22_PM6,
};
static const unsigned lhp0_pins[] = {
TEGRA_PIN_LCD_D21_PM5,
};
static const unsigned lhp1_pins[] = {
TEGRA_PIN_LCD_D18_PM2,
};
static const unsigned lhp2_pins[] = {
TEGRA_PIN_LCD_D19_PM3,
};
static const unsigned lhs_pins[] = {
TEGRA_PIN_LCD_HSYNC_PJ3,
};
static const unsigned lm0_pins[] = {
TEGRA_PIN_LCD_CS1_N_PW0,
};
static const unsigned lm1_pins[] = {
TEGRA_PIN_LCD_M1_PW1,
};
static const unsigned lpp_pins[] = {
TEGRA_PIN_LCD_D23_PM7,
};
static const unsigned lpw0_pins[] = {
TEGRA_PIN_LCD_PWR0_PB2,
};
static const unsigned lpw1_pins[] = {
TEGRA_PIN_LCD_PWR1_PC1,
};
static const unsigned lpw2_pins[] = {
TEGRA_PIN_LCD_PWR2_PC6,
};
static const unsigned lsc0_pins[] = {
TEGRA_PIN_LCD_PCLK_PB3,
};
static const unsigned lsc1_pins[] = {
TEGRA_PIN_LCD_WR_N_PZ3,
};
static const unsigned lsck_pins[] = {
TEGRA_PIN_LCD_SCK_PZ4,
};
static const unsigned lsda_pins[] = {
TEGRA_PIN_LCD_SDOUT_PN5,
};
static const unsigned lsdi_pins[] = {
TEGRA_PIN_LCD_SDIN_PZ2,
};
static const unsigned lspi_pins[] = {
TEGRA_PIN_LCD_DE_PJ1,
};
static const unsigned lvp0_pins[] = {
TEGRA_PIN_LCD_DC1_PV7,
};
static const unsigned lvp1_pins[] = {
TEGRA_PIN_LCD_D20_PM4,
};
static const unsigned lvs_pins[] = {
TEGRA_PIN_LCD_VSYNC_PJ4,
};
static const unsigned ls_pins[] = {
TEGRA_PIN_LCD_PWR0_PB2,
TEGRA_PIN_LCD_PWR1_PC1,
TEGRA_PIN_LCD_PWR2_PC6,
TEGRA_PIN_LCD_SDIN_PZ2,
TEGRA_PIN_LCD_SDOUT_PN5,
TEGRA_PIN_LCD_WR_N_PZ3,
TEGRA_PIN_LCD_CS0_N_PN4,
TEGRA_PIN_LCD_DC0_PN6,
TEGRA_PIN_LCD_SCK_PZ4,
};
static const unsigned lc_pins[] = {
TEGRA_PIN_LCD_PCLK_PB3,
TEGRA_PIN_LCD_DE_PJ1,
TEGRA_PIN_LCD_HSYNC_PJ3,
TEGRA_PIN_LCD_VSYNC_PJ4,
TEGRA_PIN_LCD_CS1_N_PW0,
TEGRA_PIN_LCD_M1_PW1,
TEGRA_PIN_LCD_DC1_PV7,
TEGRA_PIN_HDMI_INT_N_PN7,
};
static const unsigned ld17_0_pins[] = {
TEGRA_PIN_LCD_D0_PE0,
TEGRA_PIN_LCD_D1_PE1,
TEGRA_PIN_LCD_D2_PE2,
TEGRA_PIN_LCD_D3_PE3,
TEGRA_PIN_LCD_D4_PE4,
TEGRA_PIN_LCD_D5_PE5,
TEGRA_PIN_LCD_D6_PE6,
TEGRA_PIN_LCD_D7_PE7,
TEGRA_PIN_LCD_D8_PF0,
TEGRA_PIN_LCD_D9_PF1,
TEGRA_PIN_LCD_D10_PF2,
TEGRA_PIN_LCD_D11_PF3,
TEGRA_PIN_LCD_D12_PF4,
TEGRA_PIN_LCD_D13_PF5,
TEGRA_PIN_LCD_D14_PF6,
TEGRA_PIN_LCD_D15_PF7,
TEGRA_PIN_LCD_D16_PM0,
TEGRA_PIN_LCD_D17_PM1,
};
static const unsigned ld19_18_pins[] = {
TEGRA_PIN_LCD_D18_PM2,
TEGRA_PIN_LCD_D19_PM3,
};
static const unsigned ld21_20_pins[] = {
TEGRA_PIN_LCD_D20_PM4,
TEGRA_PIN_LCD_D21_PM5,
};
static const unsigned ld23_22_pins[] = {
TEGRA_PIN_LCD_D22_PM6,
TEGRA_PIN_LCD_D23_PM7,
};
static const unsigned owc_pins[] = {
TEGRA_PIN_OWC,
};
static const unsigned pmc_pins[] = {
TEGRA_PIN_LED_BLINK_PBB0,
TEGRA_PIN_SYS_CLK_REQ_PZ5,
TEGRA_PIN_CORE_PWR_REQ,
TEGRA_PIN_CPU_PWR_REQ,
TEGRA_PIN_PWR_INT_N,
};
static const unsigned pta_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned rm_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
TEGRA_PIN_GEN1_I2C_SDA_PC5,
};
static const unsigned sdb_pins[] = {
TEGRA_PIN_SDIO3_CMD_PA7,
};
static const unsigned sdc_pins[] = {
TEGRA_PIN_SDIO3_DAT0_PB7,
TEGRA_PIN_SDIO3_DAT1_PB6,
TEGRA_PIN_SDIO3_DAT2_PB5,
TEGRA_PIN_SDIO3_DAT3_PB4,
};
static const unsigned sdd_pins[] = {
TEGRA_PIN_SDIO3_CLK_PA6,
};
static const unsigned sdio1_pins[] = {
TEGRA_PIN_SDIO1_CLK_PZ0,
TEGRA_PIN_SDIO1_CMD_PZ1,
TEGRA_PIN_SDIO1_DAT0_PY7,
TEGRA_PIN_SDIO1_DAT1_PY6,
TEGRA_PIN_SDIO1_DAT2_PY5,
TEGRA_PIN_SDIO1_DAT3_PY4,
};
static const unsigned slxa_pins[] = {
TEGRA_PIN_SDIO3_DAT4_PD1,
};
static const unsigned slxc_pins[] = {
TEGRA_PIN_SDIO3_DAT6_PD3,
};
static const unsigned slxd_pins[] = {
TEGRA_PIN_SDIO3_DAT7_PD4,
};
static const unsigned slxk_pins[] = {
TEGRA_PIN_SDIO3_DAT5_PD0,
};
static const unsigned spdi_pins[] = {
TEGRA_PIN_SPDIF_IN_PK6,
};
static const unsigned spdo_pins[] = {
TEGRA_PIN_SPDIF_OUT_PK5,
};
static const unsigned spia_pins[] = {
TEGRA_PIN_SPI2_MOSI_PX0,
};
static const unsigned spib_pins[] = {
TEGRA_PIN_SPI2_MISO_PX1,
};
static const unsigned spic_pins[] = {
TEGRA_PIN_SPI2_CS0_N_PX3,
TEGRA_PIN_SPI2_SCK_PX2,
};
static const unsigned spid_pins[] = {
TEGRA_PIN_SPI1_MOSI_PX4,
};
static const unsigned spie_pins[] = {
TEGRA_PIN_SPI1_CS0_N_PX6,
TEGRA_PIN_SPI1_SCK_PX5,
};
static const unsigned spif_pins[] = {
TEGRA_PIN_SPI1_MISO_PX7,
};
static const unsigned spig_pins[] = {
TEGRA_PIN_SPI2_CS1_N_PW2,
};
static const unsigned spih_pins[] = {
TEGRA_PIN_SPI2_CS2_N_PW3,
};
static const unsigned uaa_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
TEGRA_PIN_ULPI_DATA1_PO2,
TEGRA_PIN_ULPI_DATA2_PO3,
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned uab_pins[] = {
TEGRA_PIN_ULPI_DATA4_PO5,
TEGRA_PIN_ULPI_DATA5_PO6,
TEGRA_PIN_ULPI_DATA6_PO7,
TEGRA_PIN_ULPI_DATA7_PO0,
};
static const unsigned uac_pins[] = {
TEGRA_PIN_PV0,
TEGRA_PIN_PV1,
TEGRA_PIN_PV2,
TEGRA_PIN_PV3,
};
static const unsigned ck32_pins[] = {
TEGRA_PIN_CLK_32_K_IN,
};
static const unsigned uad_pins[] = {
TEGRA_PIN_UART2_RXD_PC3,
TEGRA_PIN_UART2_TXD_PC2,
};
static const unsigned uca_pins[] = {
TEGRA_PIN_UART3_RXD_PW7,
TEGRA_PIN_UART3_TXD_PW6,
};
static const unsigned ucb_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
TEGRA_PIN_UART3_RTS_N_PC0,
};
static const unsigned uda_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
TEGRA_PIN_ULPI_DIR_PY1,
TEGRA_PIN_ULPI_NXT_PY2,
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned ddrc_pins[] = {
TEGRA_PIN_DDR_COMP_PD,
TEGRA_PIN_DDR_COMP_PU,
};
static const unsigned pmca_pins[] = {
TEGRA_PIN_LED_BLINK_PBB0,
};
static const unsigned pmcb_pins[] = {
TEGRA_PIN_SYS_CLK_REQ_PZ5,
};
static const unsigned pmcc_pins[] = {
TEGRA_PIN_CORE_PWR_REQ,
};
static const unsigned pmcd_pins[] = {
TEGRA_PIN_CPU_PWR_REQ,
};
static const unsigned pmce_pins[] = {
TEGRA_PIN_PWR_INT_N,
};
static const unsigned xm2c_pins[] = {
TEGRA_PIN_DDR_A0,
TEGRA_PIN_DDR_A1,
TEGRA_PIN_DDR_A2,
TEGRA_PIN_DDR_A3,
TEGRA_PIN_DDR_A4,
TEGRA_PIN_DDR_A5,
TEGRA_PIN_DDR_A6,
TEGRA_PIN_DDR_A7,
TEGRA_PIN_DDR_A8,
TEGRA_PIN_DDR_A9,
TEGRA_PIN_DDR_A10,
TEGRA_PIN_DDR_A11,
TEGRA_PIN_DDR_A12,
TEGRA_PIN_DDR_A13,
TEGRA_PIN_DDR_A14,
TEGRA_PIN_DDR_CAS_N,
TEGRA_PIN_DDR_BA0,
TEGRA_PIN_DDR_BA1,
TEGRA_PIN_DDR_BA2,
TEGRA_PIN_DDR_DQS0P,
TEGRA_PIN_DDR_DQS0N,
TEGRA_PIN_DDR_DQS1P,
TEGRA_PIN_DDR_DQS1N,
TEGRA_PIN_DDR_DQS2P,
TEGRA_PIN_DDR_DQS2N,
TEGRA_PIN_DDR_DQS3P,
TEGRA_PIN_DDR_DQS3N,
TEGRA_PIN_DDR_CS0_N,
TEGRA_PIN_DDR_CS1_N,
TEGRA_PIN_DDR_CKE0,
TEGRA_PIN_DDR_CKE1,
TEGRA_PIN_DDR_CLK,
TEGRA_PIN_DDR_CLK_N,
TEGRA_PIN_DDR_DM0,
TEGRA_PIN_DDR_DM1,
TEGRA_PIN_DDR_DM2,
TEGRA_PIN_DDR_DM3,
TEGRA_PIN_DDR_ODT,
TEGRA_PIN_DDR_RAS_N,
TEGRA_PIN_DDR_WE_N,
TEGRA_PIN_DDR_QUSE0,
TEGRA_PIN_DDR_QUSE1,
TEGRA_PIN_DDR_QUSE2,
TEGRA_PIN_DDR_QUSE3,
};
static const unsigned xm2d_pins[] = {
TEGRA_PIN_DDR_DQ0,
TEGRA_PIN_DDR_DQ1,
TEGRA_PIN_DDR_DQ2,
TEGRA_PIN_DDR_DQ3,
TEGRA_PIN_DDR_DQ4,
TEGRA_PIN_DDR_DQ5,
TEGRA_PIN_DDR_DQ6,
TEGRA_PIN_DDR_DQ7,
TEGRA_PIN_DDR_DQ8,
TEGRA_PIN_DDR_DQ9,
TEGRA_PIN_DDR_DQ10,
TEGRA_PIN_DDR_DQ11,
TEGRA_PIN_DDR_DQ12,
TEGRA_PIN_DDR_DQ13,
TEGRA_PIN_DDR_DQ14,
TEGRA_PIN_DDR_DQ15,
TEGRA_PIN_DDR_DQ16,
TEGRA_PIN_DDR_DQ17,
TEGRA_PIN_DDR_DQ18,
TEGRA_PIN_DDR_DQ19,
TEGRA_PIN_DDR_DQ20,
TEGRA_PIN_DDR_DQ21,
TEGRA_PIN_DDR_DQ22,
TEGRA_PIN_DDR_DQ23,
TEGRA_PIN_DDR_DQ24,
TEGRA_PIN_DDR_DQ25,
TEGRA_PIN_DDR_DQ26,
TEGRA_PIN_DDR_DQ27,
TEGRA_PIN_DDR_DQ28,
TEGRA_PIN_DDR_DQ29,
TEGRA_PIN_DDR_DQ30,
TEGRA_PIN_DDR_DQ31,
};
static const unsigned drive_ao1_pins[] = {
TEGRA_PIN_SYS_RESET,
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
TEGRA_PIN_KB_ROW7_PR7,
};
static const unsigned drive_ao2_pins[] = {
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_KB_ROW11_PS3,
TEGRA_PIN_KB_ROW12_PS4,
TEGRA_PIN_KB_ROW13_PS5,
TEGRA_PIN_KB_ROW14_PS6,
TEGRA_PIN_KB_ROW15_PS7,
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
TEGRA_PIN_KB_COL7_PQ7,
TEGRA_PIN_LED_BLINK_PBB0,
TEGRA_PIN_SYS_CLK_REQ_PZ5,
TEGRA_PIN_CORE_PWR_REQ,
TEGRA_PIN_CPU_PWR_REQ,
TEGRA_PIN_PWR_INT_N,
TEGRA_PIN_CLK_32_K_IN,
};
static const unsigned drive_at1_pins[] = {
TEGRA_PIN_GMI_IORDY_PI5,
TEGRA_PIN_GMI_AD8_PH0,
TEGRA_PIN_GMI_AD9_PH1,
TEGRA_PIN_GMI_AD10_PH2,
TEGRA_PIN_GMI_AD11_PH3,
TEGRA_PIN_GMI_AD12_PH4,
TEGRA_PIN_GMI_AD13_PH5,
TEGRA_PIN_GMI_AD14_PH6,
TEGRA_PIN_GMI_AD15_PH7,
TEGRA_PIN_GMI_CS7_N_PI6,
TEGRA_PIN_GMI_DPD_PT7,
TEGRA_PIN_GEN2_I2C_SCL_PT5,
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned drive_at2_pins[] = {
TEGRA_PIN_GMI_WAIT_PI7,
TEGRA_PIN_GMI_ADV_N_PK0,
TEGRA_PIN_GMI_CLK_PK1,
TEGRA_PIN_GMI_CS6_N_PI3,
TEGRA_PIN_GMI_CS5_N_PI2,
TEGRA_PIN_GMI_CS4_N_PK2,
TEGRA_PIN_GMI_CS3_N_PK4,
TEGRA_PIN_GMI_CS2_N_PK3,
TEGRA_PIN_GMI_AD0_PG0,
TEGRA_PIN_GMI_AD1_PG1,
TEGRA_PIN_GMI_AD2_PG2,
TEGRA_PIN_GMI_AD3_PG3,
TEGRA_PIN_GMI_AD4_PG4,
TEGRA_PIN_GMI_AD5_PG5,
TEGRA_PIN_GMI_AD6_PG6,
TEGRA_PIN_GMI_AD7_PG7,
TEGRA_PIN_GMI_HIOW_N_PI0,
TEGRA_PIN_GMI_HIOR_N_PI1,
TEGRA_PIN_GMI_RST_N_PI4,
};
static const unsigned drive_cdev1_pins[] = {
TEGRA_PIN_DAP_MCLK1_PW4,
};
static const unsigned drive_cdev2_pins[] = {
TEGRA_PIN_DAP_MCLK2_PW5,
};
static const unsigned drive_csus_pins[] = {
TEGRA_PIN_VI_MCLK_PT1,
};
static const unsigned drive_dap1_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
TEGRA_PIN_SPDIF_OUT_PK5,
TEGRA_PIN_SPDIF_IN_PK6,
};
static const unsigned drive_dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned drive_dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned drive_dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned drive_dbg_pins[] = {
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
TEGRA_PIN_JTAG_RTCK_PU7,
TEGRA_PIN_GEN1_I2C_SDA_PC5,
TEGRA_PIN_GEN1_I2C_SCL_PC4,
TEGRA_PIN_JTAG_TRST_N,
TEGRA_PIN_JTAG_TDO,
TEGRA_PIN_JTAG_TMS,
TEGRA_PIN_JTAG_TCK,
TEGRA_PIN_JTAG_TDI,
TEGRA_PIN_TEST_MODE_EN,
};
static const unsigned drive_lcd1_pins[] = {
TEGRA_PIN_LCD_PWR1_PC1,
TEGRA_PIN_LCD_PWR2_PC6,
TEGRA_PIN_LCD_SDIN_PZ2,
TEGRA_PIN_LCD_SDOUT_PN5,
TEGRA_PIN_LCD_WR_N_PZ3,
TEGRA_PIN_LCD_CS0_N_PN4,
TEGRA_PIN_LCD_DC0_PN6,
TEGRA_PIN_LCD_SCK_PZ4,
};
static const unsigned drive_lcd2_pins[] = {
TEGRA_PIN_LCD_PWR0_PB2,
TEGRA_PIN_LCD_PCLK_PB3,
TEGRA_PIN_LCD_DE_PJ1,
TEGRA_PIN_LCD_HSYNC_PJ3,
TEGRA_PIN_LCD_VSYNC_PJ4,
TEGRA_PIN_LCD_D0_PE0,
TEGRA_PIN_LCD_D1_PE1,
TEGRA_PIN_LCD_D2_PE2,
TEGRA_PIN_LCD_D3_PE3,
TEGRA_PIN_LCD_D4_PE4,
TEGRA_PIN_LCD_D5_PE5,
TEGRA_PIN_LCD_D6_PE6,
TEGRA_PIN_LCD_D7_PE7,
TEGRA_PIN_LCD_D8_PF0,
TEGRA_PIN_LCD_D9_PF1,
TEGRA_PIN_LCD_D10_PF2,
TEGRA_PIN_LCD_D11_PF3,
TEGRA_PIN_LCD_D12_PF4,
TEGRA_PIN_LCD_D13_PF5,
TEGRA_PIN_LCD_D14_PF6,
TEGRA_PIN_LCD_D15_PF7,
TEGRA_PIN_LCD_D16_PM0,
TEGRA_PIN_LCD_D17_PM1,
TEGRA_PIN_LCD_D18_PM2,
TEGRA_PIN_LCD_D19_PM3,
TEGRA_PIN_LCD_D20_PM4,
TEGRA_PIN_LCD_D21_PM5,
TEGRA_PIN_LCD_D22_PM6,
TEGRA_PIN_LCD_D23_PM7,
TEGRA_PIN_LCD_CS1_N_PW0,
TEGRA_PIN_LCD_M1_PW1,
TEGRA_PIN_LCD_DC1_PV7,
TEGRA_PIN_HDMI_INT_N_PN7,
};
static const unsigned drive_sdmmc2_pins[] = {
TEGRA_PIN_SDIO3_DAT4_PD1,
TEGRA_PIN_SDIO3_DAT5_PD0,
TEGRA_PIN_SDIO3_DAT6_PD3,
TEGRA_PIN_SDIO3_DAT7_PD4,
};
static const unsigned drive_sdmmc3_pins[] = {
TEGRA_PIN_SDIO3_CLK_PA6,
TEGRA_PIN_SDIO3_CMD_PA7,
TEGRA_PIN_SDIO3_DAT0_PB7,
TEGRA_PIN_SDIO3_DAT1_PB6,
TEGRA_PIN_SDIO3_DAT2_PB5,
TEGRA_PIN_SDIO3_DAT3_PB4,
TEGRA_PIN_PV4,
TEGRA_PIN_PV5,
TEGRA_PIN_PV6,
};
static const unsigned drive_spi_pins[] = {
TEGRA_PIN_SPI2_MOSI_PX0,
TEGRA_PIN_SPI2_MISO_PX1,
TEGRA_PIN_SPI2_SCK_PX2,
TEGRA_PIN_SPI2_CS0_N_PX3,
TEGRA_PIN_SPI1_MOSI_PX4,
TEGRA_PIN_SPI1_SCK_PX5,
TEGRA_PIN_SPI1_CS0_N_PX6,
TEGRA_PIN_SPI1_MISO_PX7,
TEGRA_PIN_SPI2_CS1_N_PW2,
TEGRA_PIN_SPI2_CS2_N_PW3,
};
static const unsigned drive_uaa_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
TEGRA_PIN_ULPI_DATA1_PO2,
TEGRA_PIN_ULPI_DATA2_PO3,
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned drive_uab_pins[] = {
TEGRA_PIN_ULPI_DATA4_PO5,
TEGRA_PIN_ULPI_DATA5_PO6,
TEGRA_PIN_ULPI_DATA6_PO7,
TEGRA_PIN_ULPI_DATA7_PO0,
TEGRA_PIN_PV0,
TEGRA_PIN_PV1,
TEGRA_PIN_PV2,
TEGRA_PIN_PV3,
};
static const unsigned drive_uart2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
TEGRA_PIN_UART2_RXD_PC3,
TEGRA_PIN_UART2_RTS_N_PJ6,
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned drive_uart3_pins[] = {
TEGRA_PIN_UART3_TXD_PW6,
TEGRA_PIN_UART3_RXD_PW7,
TEGRA_PIN_UART3_RTS_N_PC0,
TEGRA_PIN_UART3_CTS_N_PA1,
};
static const unsigned drive_vi1_pins[] = {
TEGRA_PIN_VI_D0_PT4,
TEGRA_PIN_VI_D1_PD5,
TEGRA_PIN_VI_D2_PL0,
TEGRA_PIN_VI_D3_PL1,
TEGRA_PIN_VI_D4_PL2,
TEGRA_PIN_VI_D5_PL3,
TEGRA_PIN_VI_D6_PL4,
TEGRA_PIN_VI_D7_PL5,
TEGRA_PIN_VI_D8_PL6,
TEGRA_PIN_VI_D9_PL7,
TEGRA_PIN_VI_D10_PT2,
TEGRA_PIN_VI_D11_PT3,
TEGRA_PIN_VI_PCLK_PT0,
TEGRA_PIN_VI_VSYNC_PD6,
TEGRA_PIN_VI_HSYNC_PD7,
};
static const unsigned drive_vi2_pins[] = {
TEGRA_PIN_VI_GP0_PBB1,
TEGRA_PIN_CAM_I2C_SCL_PBB2,
TEGRA_PIN_CAM_I2C_SDA_PBB3,
TEGRA_PIN_VI_GP3_PBB4,
TEGRA_PIN_VI_GP4_PBB5,
TEGRA_PIN_VI_GP5_PD2,
TEGRA_PIN_VI_GP6_PA0,
};
static const unsigned drive_xm2a_pins[] = {
TEGRA_PIN_DDR_A0,
TEGRA_PIN_DDR_A1,
TEGRA_PIN_DDR_A2,
TEGRA_PIN_DDR_A3,
TEGRA_PIN_DDR_A4,
TEGRA_PIN_DDR_A5,
TEGRA_PIN_DDR_A6,
TEGRA_PIN_DDR_A7,
TEGRA_PIN_DDR_A8,
TEGRA_PIN_DDR_A9,
TEGRA_PIN_DDR_A10,
TEGRA_PIN_DDR_A11,
TEGRA_PIN_DDR_A12,
TEGRA_PIN_DDR_A13,
TEGRA_PIN_DDR_A14,
TEGRA_PIN_DDR_BA0,
TEGRA_PIN_DDR_BA1,
TEGRA_PIN_DDR_BA2,
TEGRA_PIN_DDR_CS0_N,
TEGRA_PIN_DDR_CS1_N,
TEGRA_PIN_DDR_ODT,
TEGRA_PIN_DDR_RAS_N,
TEGRA_PIN_DDR_CAS_N,
TEGRA_PIN_DDR_WE_N,
TEGRA_PIN_DDR_CKE0,
TEGRA_PIN_DDR_CKE1,
};
static const unsigned drive_xm2c_pins[] = {
TEGRA_PIN_DDR_DQS0P,
TEGRA_PIN_DDR_DQS0N,
TEGRA_PIN_DDR_DQS1P,
TEGRA_PIN_DDR_DQS1N,
TEGRA_PIN_DDR_DQS2P,
TEGRA_PIN_DDR_DQS2N,
TEGRA_PIN_DDR_DQS3P,
TEGRA_PIN_DDR_DQS3N,
TEGRA_PIN_DDR_QUSE0,
TEGRA_PIN_DDR_QUSE1,
TEGRA_PIN_DDR_QUSE2,
TEGRA_PIN_DDR_QUSE3,
};
static const unsigned drive_xm2d_pins[] = {
TEGRA_PIN_DDR_DQ0,
TEGRA_PIN_DDR_DQ1,
TEGRA_PIN_DDR_DQ2,
TEGRA_PIN_DDR_DQ3,
TEGRA_PIN_DDR_DQ4,
TEGRA_PIN_DDR_DQ5,
TEGRA_PIN_DDR_DQ6,
TEGRA_PIN_DDR_DQ7,
TEGRA_PIN_DDR_DQ8,
TEGRA_PIN_DDR_DQ9,
TEGRA_PIN_DDR_DQ10,
TEGRA_PIN_DDR_DQ11,
TEGRA_PIN_DDR_DQ12,
TEGRA_PIN_DDR_DQ13,
TEGRA_PIN_DDR_DQ14,
TEGRA_PIN_DDR_DQ15,
TEGRA_PIN_DDR_DQ16,
TEGRA_PIN_DDR_DQ17,
TEGRA_PIN_DDR_DQ18,
TEGRA_PIN_DDR_DQ19,
TEGRA_PIN_DDR_DQ20,
TEGRA_PIN_DDR_DQ21,
TEGRA_PIN_DDR_DQ22,
TEGRA_PIN_DDR_DQ23,
TEGRA_PIN_DDR_DQ24,
TEGRA_PIN_DDR_DQ25,
TEGRA_PIN_DDR_DQ26,
TEGRA_PIN_DDR_DQ27,
TEGRA_PIN_DDR_DQ28,
TEGRA_PIN_DDR_DQ29,
TEGRA_PIN_DDR_DQ30,
TEGRA_PIN_DDR_DQ31,
TEGRA_PIN_DDR_DM0,
TEGRA_PIN_DDR_DM1,
TEGRA_PIN_DDR_DM2,
TEGRA_PIN_DDR_DM3,
};
static const unsigned drive_xm2clk_pins[] = {
TEGRA_PIN_DDR_CLK,
TEGRA_PIN_DDR_CLK_N,
};
static const unsigned drive_sdio1_pins[] = {
TEGRA_PIN_SDIO1_CLK_PZ0,
TEGRA_PIN_SDIO1_CMD_PZ1,
TEGRA_PIN_SDIO1_DAT0_PY7,
TEGRA_PIN_SDIO1_DAT1_PY6,
TEGRA_PIN_SDIO1_DAT2_PY5,
TEGRA_PIN_SDIO1_DAT3_PY4,
};
static const unsigned drive_crt_pins[] = {
TEGRA_PIN_CRT_HSYNC,
TEGRA_PIN_CRT_VSYNC,
};
static const unsigned drive_ddc_pins[] = {
TEGRA_PIN_DDC_SCL,
TEGRA_PIN_DDC_SDA,
};
static const unsigned drive_gma_pins[] = {
TEGRA_PIN_GMI_AD20_PAA0,
TEGRA_PIN_GMI_AD21_PAA1,
TEGRA_PIN_GMI_AD22_PAA2,
TEGRA_PIN_GMI_AD23_PAA3,
};
static const unsigned drive_gmb_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
};
static const unsigned drive_gmc_pins[] = {
TEGRA_PIN_GMI_AD16_PJ7,
TEGRA_PIN_GMI_AD17_PB0,
TEGRA_PIN_GMI_AD18_PB1,
TEGRA_PIN_GMI_AD19_PK7,
};
static const unsigned drive_gmd_pins[] = {
TEGRA_PIN_GMI_CS0_N_PJ0,
TEGRA_PIN_GMI_CS1_N_PJ2,
};
static const unsigned drive_gme_pins[] = {
TEGRA_PIN_GMI_AD24_PAA4,
TEGRA_PIN_GMI_AD25_PAA5,
TEGRA_PIN_GMI_AD26_PAA6,
TEGRA_PIN_GMI_AD27_PAA7,
};
static const unsigned drive_owr_pins[] = {
TEGRA_PIN_OWC,
};
static const unsigned drive_uda_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
TEGRA_PIN_ULPI_DIR_PY1,
TEGRA_PIN_ULPI_NXT_PY2,
TEGRA_PIN_ULPI_STP_PY3,
};
enum tegra_mux {
TEGRA_MUX_AHB_CLK,
TEGRA_MUX_APB_CLK,
TEGRA_MUX_AUDIO_SYNC,
TEGRA_MUX_CRT,
TEGRA_MUX_DAP1,
TEGRA_MUX_DAP2,
TEGRA_MUX_DAP3,
TEGRA_MUX_DAP4,
TEGRA_MUX_DAP5,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_EMC_TEST0_DLL,
TEGRA_MUX_EMC_TEST1_DLL,
TEGRA_MUX_GMI,
TEGRA_MUX_GMI_INT,
TEGRA_MUX_HDMI,
TEGRA_MUX_I2CP,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_IDE,
TEGRA_MUX_IRDA,
TEGRA_MUX_KBC,
TEGRA_MUX_MIO,
TEGRA_MUX_MIPI_HS,
TEGRA_MUX_NAND,
TEGRA_MUX_OSC,
TEGRA_MUX_OWR,
TEGRA_MUX_PCIE,
TEGRA_MUX_PLLA_OUT,
TEGRA_MUX_PLLC_OUT1,
TEGRA_MUX_PLLM_OUT1,
TEGRA_MUX_PLLP_OUT2,
TEGRA_MUX_PLLP_OUT3,
TEGRA_MUX_PLLP_OUT4,
TEGRA_MUX_PWM,
TEGRA_MUX_PWR_INTR,
TEGRA_MUX_PWR_ON,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_RSVD4,
TEGRA_MUX_RTCK,
TEGRA_MUX_SDIO1,
TEGRA_MUX_SDIO2,
TEGRA_MUX_SDIO3,
TEGRA_MUX_SDIO4,
TEGRA_MUX_SFLASH,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI2_ALT,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_TRACE,
TEGRA_MUX_TWC,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_UARTE,
TEGRA_MUX_ULPI,
TEGRA_MUX_VI,
TEGRA_MUX_VI_SENSOR_CLK,
TEGRA_MUX_XIO,
};
#define FUNCTION(fname) #fname
static const char * const tegra20_functions[] = {
FUNCTION(ahb_clk),
FUNCTION(apb_clk),
FUNCTION(audio_sync),
FUNCTION(crt),
FUNCTION(dap1),
FUNCTION(dap2),
FUNCTION(dap3),
FUNCTION(dap4),
FUNCTION(dap5),
FUNCTION(displaya),
FUNCTION(displayb),
FUNCTION(emc_test0_dll),
FUNCTION(emc_test1_dll),
FUNCTION(gmi),
FUNCTION(gmi_int),
FUNCTION(hdmi),
FUNCTION(i2cp),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(ide),
FUNCTION(irda),
FUNCTION(kbc),
FUNCTION(mio),
FUNCTION(mipi_hs),
FUNCTION(nand),
FUNCTION(osc),
FUNCTION(owr),
FUNCTION(pcie),
FUNCTION(plla_out),
FUNCTION(pllc_out1),
FUNCTION(pllm_out1),
FUNCTION(pllp_out2),
FUNCTION(pllp_out3),
FUNCTION(pllp_out4),
FUNCTION(pwm),
FUNCTION(pwr_intr),
FUNCTION(pwr_on),
FUNCTION(rsvd1),
FUNCTION(rsvd2),
FUNCTION(rsvd3),
FUNCTION(rsvd4),
FUNCTION(rtck),
FUNCTION(sdio1),
FUNCTION(sdio2),
FUNCTION(sdio3),
FUNCTION(sdio4),
FUNCTION(sflash),
FUNCTION(spdif),
FUNCTION(spi1),
FUNCTION(spi2),
FUNCTION(spi2_alt),
FUNCTION(spi3),
FUNCTION(spi4),
FUNCTION(trace),
FUNCTION(twc),
FUNCTION(uarta),
FUNCTION(uartb),
FUNCTION(uartc),
FUNCTION(uartd),
FUNCTION(uarte),
FUNCTION(ulpi),
FUNCTION(vi),
FUNCTION(vi_sensor_clk),
FUNCTION(xio),
};
#define TRISTATE_REG_A 0x14
#define PIN_MUX_CTL_REG_A 0x80
#define PULLUPDOWN_REG_A 0xa0
#define PINGROUP_REG_A 0x868
/* Pin group with mux control, and typically tri-state and pull-up/down too */
#define MUX_PG(pg_name, f0, f1, f2, f3, \
tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_ ## f0, \
TEGRA_MUX_ ## f1, \
TEGRA_MUX_ ## f2, \
TEGRA_MUX_ ## f3, \
}, \
.mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
.mux_bank = 1, \
.mux_bit = mux_b, \
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
.pupd_bank = 2, \
.pupd_bit = pupd_b, \
.tri_reg = ((tri_r) - TRISTATE_REG_A), \
.tri_bank = 0, \
.tri_bit = tri_b, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = -1, \
.parked_bitmask = 0, \
}
/* Pin groups with only pull up and pull down control */
#define PULL_PG(pg_name, pupd_r, pupd_b) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
.pupd_bank = 2, \
.pupd_bit = pupd_b, \
.drv_reg = -1, \
.parked_bitmask = 0, \
}
/* Pin groups for drive strength registers (configurable version) */
#define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
drvdn_b, drvup_b, \
slwr_b, slwr_w, slwf_b, slwf_w) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \
.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.drv_reg = ((r) - PINGROUP_REG_A), \
.drv_bank = 3, \
.parked_bitmask = 0, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
.drvdn_bit = drvdn_b, \
.drvdn_width = 5, \
.drvup_bit = drvup_b, \
.drvup_width = 5, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = -1, \
}
/* Pin groups for drive strength registers (simple version) */
#define DRV_PG(pg_name, r) \
DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
static const struct tegra_pingroup tegra20_groups[] = {
/* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
/* pg_name, pupd_r/b */
PULL_PG(ck32, 0xb0, 14),
PULL_PG(ddrc, 0xac, 26),
PULL_PG(pmca, 0xb0, 4),
PULL_PG(pmcb, 0xb0, 6),
PULL_PG(pmcc, 0xb0, 8),
PULL_PG(pmcd, 0xb0, 10),
PULL_PG(pmce, 0xb0, 12),
PULL_PG(xm2c, 0xa8, 30),
PULL_PG(xm2d, 0xa8, 28),
PULL_PG(ls, 0xac, 20),
PULL_PG(lc, 0xac, 22),
PULL_PG(ld17_0, 0xac, 12),
PULL_PG(ld19_18, 0xac, 14),
PULL_PG(ld21_20, 0xac, 16),
PULL_PG(ld23_22, 0xac, 18),
/* pg_name, r */
DRV_PG(ao1, 0x868),
DRV_PG(ao2, 0x86c),
DRV_PG(at1, 0x870),
DRV_PG(at2, 0x874),
DRV_PG(cdev1, 0x878),
DRV_PG(cdev2, 0x87c),
DRV_PG(csus, 0x880),
DRV_PG(dap1, 0x884),
DRV_PG(dap2, 0x888),
DRV_PG(dap3, 0x88c),
DRV_PG(dap4, 0x890),
DRV_PG(dbg, 0x894),
DRV_PG(lcd1, 0x898),
DRV_PG(lcd2, 0x89c),
DRV_PG(sdmmc2, 0x8a0),
DRV_PG(sdmmc3, 0x8a4),
DRV_PG(spi, 0x8a8),
DRV_PG(uaa, 0x8ac),
DRV_PG(uab, 0x8b0),
DRV_PG(uart2, 0x8b4),
DRV_PG(uart3, 0x8b8),
DRV_PG(vi1, 0x8bc),
DRV_PG(vi2, 0x8c0),
/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
/* pg_name, r */
DRV_PG(sdio1, 0x8e0),
DRV_PG(crt, 0x8ec),
DRV_PG(ddc, 0x8f0),
DRV_PG(gma, 0x8f4),
DRV_PG(gmb, 0x8f8),
DRV_PG(gmc, 0x8fc),
DRV_PG(gmd, 0x900),
DRV_PG(gme, 0x904),
DRV_PG(owr, 0x908),
DRV_PG(uda, 0x90c),
};
static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra20-gpio",
.pins = tegra20_pins,
.npins = ARRAY_SIZE(tegra20_pins),
.functions = tegra20_functions,
.nfunctions = ARRAY_SIZE(tegra20_functions),
.groups = tegra20_groups,
.ngroups = ARRAY_SIZE(tegra20_groups),
.hsm_in_mux = false,
.schmitt_in_mux = false,
.drvtype_in_mux = false,
};
static const char *cdev1_parents[] = {
"dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
};
static const char *cdev2_parents[] = {
"dev2_osc_div", "hclk", "pclk", "pll_p_out4",
};
static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
{
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
}
static int tegra20_pinctrl_probe(struct platform_device *pdev)
{
int err;
err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
if (err)
return err;
tegra20_pinctrl_register_clock_muxes(pdev);
return 0;
}
static const struct of_device_id tegra20_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra20-pinmux", },
{ },
};
static struct platform_driver tegra20_pinctrl_driver = {
.driver = {
.name = "tegra20-pinctrl",
.of_match_table = tegra20_pinctrl_of_match,
},
.probe = tegra20_pinctrl_probe,
};
static int __init tegra20_pinctrl_init(void)
{
return platform_driver_register(&tegra20_pinctrl_driver);
}
arch_initcall(tegra20_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra20.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for the NVIDIA Tegra124 pinmux
*
* Author: Ashwini Ghuge <[email protected]>
*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
#define TEGRA_PIN_PB0 _GPIO(8)
#define TEGRA_PIN_PB1 _GPIO(9)
#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
#define TEGRA_PIN_PC7 _GPIO(23)
#define TEGRA_PIN_PG0 _GPIO(48)
#define TEGRA_PIN_PG1 _GPIO(49)
#define TEGRA_PIN_PG2 _GPIO(50)
#define TEGRA_PIN_PG3 _GPIO(51)
#define TEGRA_PIN_PG4 _GPIO(52)
#define TEGRA_PIN_PG5 _GPIO(53)
#define TEGRA_PIN_PG6 _GPIO(54)
#define TEGRA_PIN_PG7 _GPIO(55)
#define TEGRA_PIN_PH0 _GPIO(56)
#define TEGRA_PIN_PH1 _GPIO(57)
#define TEGRA_PIN_PH2 _GPIO(58)
#define TEGRA_PIN_PH3 _GPIO(59)
#define TEGRA_PIN_PH4 _GPIO(60)
#define TEGRA_PIN_PH5 _GPIO(61)
#define TEGRA_PIN_PH6 _GPIO(62)
#define TEGRA_PIN_PH7 _GPIO(63)
#define TEGRA_PIN_PI0 _GPIO(64)
#define TEGRA_PIN_PI1 _GPIO(65)
#define TEGRA_PIN_PI2 _GPIO(66)
#define TEGRA_PIN_PI3 _GPIO(67)
#define TEGRA_PIN_PI4 _GPIO(68)
#define TEGRA_PIN_PI5 _GPIO(69)
#define TEGRA_PIN_PI6 _GPIO(70)
#define TEGRA_PIN_PI7 _GPIO(71)
#define TEGRA_PIN_PJ0 _GPIO(72)
#define TEGRA_PIN_PJ2 _GPIO(74)
#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
#define TEGRA_PIN_PJ7 _GPIO(79)
#define TEGRA_PIN_PK0 _GPIO(80)
#define TEGRA_PIN_PK1 _GPIO(81)
#define TEGRA_PIN_PK2 _GPIO(82)
#define TEGRA_PIN_PK3 _GPIO(83)
#define TEGRA_PIN_PK4 _GPIO(84)
#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
#define TEGRA_PIN_PK7 _GPIO(87)
#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
#define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
#define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
#define TEGRA_PIN_PU0 _GPIO(160)
#define TEGRA_PIN_PU1 _GPIO(161)
#define TEGRA_PIN_PU2 _GPIO(162)
#define TEGRA_PIN_PU3 _GPIO(163)
#define TEGRA_PIN_PU4 _GPIO(164)
#define TEGRA_PIN_PU5 _GPIO(165)
#define TEGRA_PIN_PU6 _GPIO(166)
#define TEGRA_PIN_PV0 _GPIO(168)
#define TEGRA_PIN_PV1 _GPIO(169)
#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
#define TEGRA_PIN_PBB0 _GPIO(216)
#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
#define TEGRA_PIN_PBB3 _GPIO(219)
#define TEGRA_PIN_PBB4 _GPIO(220)
#define TEGRA_PIN_PBB5 _GPIO(221)
#define TEGRA_PIN_PBB6 _GPIO(222)
#define TEGRA_PIN_PBB7 _GPIO(223)
#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
#define TEGRA_PIN_PCC1 _GPIO(225)
#define TEGRA_PIN_PCC2 _GPIO(226)
#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
#define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
#define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
#define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
#define TEGRA_PIN_PFF2 _GPIO(250)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
/* Non-GPIO pins */
#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
#define TEGRA_PIN_PWR_INT_N _PIN(2)
#define TEGRA_PIN_GMI_CLK_LB _PIN(3)
#define TEGRA_PIN_RESET_OUT_N _PIN(4)
#define TEGRA_PIN_OWR _PIN(5)
#define TEGRA_PIN_CLK_32K_IN _PIN(6)
#define TEGRA_PIN_JTAG_RTCK _PIN(7)
#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
static const struct pinctrl_pin_desc tegra124_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
};
static const unsigned clk_32k_out_pa0_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
};
static const unsigned uart3_cts_n_pa1_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
};
static const unsigned dap2_fs_pa2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
};
static const unsigned dap2_sclk_pa3_pins[] = {
TEGRA_PIN_DAP2_SCLK_PA3,
};
static const unsigned dap2_din_pa4_pins[] = {
TEGRA_PIN_DAP2_DIN_PA4,
};
static const unsigned dap2_dout_pa5_pins[] = {
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned sdmmc3_clk_pa6_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
};
static const unsigned sdmmc3_cmd_pa7_pins[] = {
TEGRA_PIN_SDMMC3_CMD_PA7,
};
static const unsigned pb0_pins[] = {
TEGRA_PIN_PB0,
};
static const unsigned pb1_pins[] = {
TEGRA_PIN_PB1,
};
static const unsigned sdmmc3_dat3_pb4_pins[] = {
TEGRA_PIN_SDMMC3_DAT3_PB4,
};
static const unsigned sdmmc3_dat2_pb5_pins[] = {
TEGRA_PIN_SDMMC3_DAT2_PB5,
};
static const unsigned sdmmc3_dat1_pb6_pins[] = {
TEGRA_PIN_SDMMC3_DAT1_PB6,
};
static const unsigned sdmmc3_dat0_pb7_pins[] = {
TEGRA_PIN_SDMMC3_DAT0_PB7,
};
static const unsigned uart3_rts_n_pc0_pins[] = {
TEGRA_PIN_UART3_RTS_N_PC0,
};
static const unsigned uart2_txd_pc2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
};
static const unsigned uart2_rxd_pc3_pins[] = {
TEGRA_PIN_UART2_RXD_PC3,
};
static const unsigned gen1_i2c_scl_pc4_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
};
static const unsigned gen1_i2c_sda_pc5_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PC5,
};
static const unsigned pc7_pins[] = {
TEGRA_PIN_PC7,
};
static const unsigned pg0_pins[] = {
TEGRA_PIN_PG0,
};
static const unsigned pg1_pins[] = {
TEGRA_PIN_PG1,
};
static const unsigned pg2_pins[] = {
TEGRA_PIN_PG2,
};
static const unsigned pg3_pins[] = {
TEGRA_PIN_PG3,
};
static const unsigned pg4_pins[] = {
TEGRA_PIN_PG4,
};
static const unsigned pg5_pins[] = {
TEGRA_PIN_PG5,
};
static const unsigned pg6_pins[] = {
TEGRA_PIN_PG6,
};
static const unsigned pg7_pins[] = {
TEGRA_PIN_PG7,
};
static const unsigned ph0_pins[] = {
TEGRA_PIN_PH0,
};
static const unsigned ph1_pins[] = {
TEGRA_PIN_PH1,
};
static const unsigned ph2_pins[] = {
TEGRA_PIN_PH2,
};
static const unsigned ph3_pins[] = {
TEGRA_PIN_PH3,
};
static const unsigned ph4_pins[] = {
TEGRA_PIN_PH4,
};
static const unsigned ph5_pins[] = {
TEGRA_PIN_PH5,
};
static const unsigned ph6_pins[] = {
TEGRA_PIN_PH6,
};
static const unsigned ph7_pins[] = {
TEGRA_PIN_PH7,
};
static const unsigned pi0_pins[] = {
TEGRA_PIN_PI0,
};
static const unsigned pi1_pins[] = {
TEGRA_PIN_PI1,
};
static const unsigned pi2_pins[] = {
TEGRA_PIN_PI2,
};
static const unsigned pi3_pins[] = {
TEGRA_PIN_PI3,
};
static const unsigned pi4_pins[] = {
TEGRA_PIN_PI4,
};
static const unsigned pi5_pins[] = {
TEGRA_PIN_PI5,
};
static const unsigned pi6_pins[] = {
TEGRA_PIN_PI6,
};
static const unsigned pi7_pins[] = {
TEGRA_PIN_PI7,
};
static const unsigned pj0_pins[] = {
TEGRA_PIN_PJ0,
};
static const unsigned pj2_pins[] = {
TEGRA_PIN_PJ2,
};
static const unsigned uart2_cts_n_pj5_pins[] = {
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned uart2_rts_n_pj6_pins[] = {
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned pj7_pins[] = {
TEGRA_PIN_PJ7,
};
static const unsigned pk0_pins[] = {
TEGRA_PIN_PK0,
};
static const unsigned pk1_pins[] = {
TEGRA_PIN_PK1,
};
static const unsigned pk2_pins[] = {
TEGRA_PIN_PK2,
};
static const unsigned pk3_pins[] = {
TEGRA_PIN_PK3,
};
static const unsigned pk4_pins[] = {
TEGRA_PIN_PK4,
};
static const unsigned spdif_out_pk5_pins[] = {
TEGRA_PIN_SPDIF_OUT_PK5,
};
static const unsigned spdif_in_pk6_pins[] = {
TEGRA_PIN_SPDIF_IN_PK6,
};
static const unsigned pk7_pins[] = {
TEGRA_PIN_PK7,
};
static const unsigned dap1_fs_pn0_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
};
static const unsigned dap1_din_pn1_pins[] = {
TEGRA_PIN_DAP1_DIN_PN1,
};
static const unsigned dap1_dout_pn2_pins[] = {
TEGRA_PIN_DAP1_DOUT_PN2,
};
static const unsigned dap1_sclk_pn3_pins[] = {
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned usb_vbus_en0_pn4_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PN4,
};
static const unsigned usb_vbus_en1_pn5_pins[] = {
TEGRA_PIN_USB_VBUS_EN1_PN5,
};
static const unsigned hdmi_int_pn7_pins[] = {
TEGRA_PIN_HDMI_INT_PN7,
};
static const unsigned ulpi_data7_po0_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
};
static const unsigned ulpi_data0_po1_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
};
static const unsigned ulpi_data1_po2_pins[] = {
TEGRA_PIN_ULPI_DATA1_PO2,
};
static const unsigned ulpi_data2_po3_pins[] = {
TEGRA_PIN_ULPI_DATA2_PO3,
};
static const unsigned ulpi_data3_po4_pins[] = {
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned ulpi_data4_po5_pins[] = {
TEGRA_PIN_ULPI_DATA4_PO5,
};
static const unsigned ulpi_data5_po6_pins[] = {
TEGRA_PIN_ULPI_DATA5_PO6,
};
static const unsigned ulpi_data6_po7_pins[] = {
TEGRA_PIN_ULPI_DATA6_PO7,
};
static const unsigned dap3_fs_pp0_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
};
static const unsigned dap3_din_pp1_pins[] = {
TEGRA_PIN_DAP3_DIN_PP1,
};
static const unsigned dap3_dout_pp2_pins[] = {
TEGRA_PIN_DAP3_DOUT_PP2,
};
static const unsigned dap3_sclk_pp3_pins[] = {
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned dap4_fs_pp4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
};
static const unsigned dap4_din_pp5_pins[] = {
TEGRA_PIN_DAP4_DIN_PP5,
};
static const unsigned dap4_dout_pp6_pins[] = {
TEGRA_PIN_DAP4_DOUT_PP6,
};
static const unsigned dap4_sclk_pp7_pins[] = {
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned kb_col0_pq0_pins[] = {
TEGRA_PIN_KB_COL0_PQ0,
};
static const unsigned kb_col1_pq1_pins[] = {
TEGRA_PIN_KB_COL1_PQ1,
};
static const unsigned kb_col2_pq2_pins[] = {
TEGRA_PIN_KB_COL2_PQ2,
};
static const unsigned kb_col3_pq3_pins[] = {
TEGRA_PIN_KB_COL3_PQ3,
};
static const unsigned kb_col4_pq4_pins[] = {
TEGRA_PIN_KB_COL4_PQ4,
};
static const unsigned kb_col5_pq5_pins[] = {
TEGRA_PIN_KB_COL5_PQ5,
};
static const unsigned kb_col6_pq6_pins[] = {
TEGRA_PIN_KB_COL6_PQ6,
};
static const unsigned kb_col7_pq7_pins[] = {
TEGRA_PIN_KB_COL7_PQ7,
};
static const unsigned kb_row0_pr0_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
};
static const unsigned kb_row1_pr1_pins[] = {
TEGRA_PIN_KB_ROW1_PR1,
};
static const unsigned kb_row2_pr2_pins[] = {
TEGRA_PIN_KB_ROW2_PR2,
};
static const unsigned kb_row3_pr3_pins[] = {
TEGRA_PIN_KB_ROW3_PR3,
};
static const unsigned kb_row4_pr4_pins[] = {
TEGRA_PIN_KB_ROW4_PR4,
};
static const unsigned kb_row5_pr5_pins[] = {
TEGRA_PIN_KB_ROW5_PR5,
};
static const unsigned kb_row6_pr6_pins[] = {
TEGRA_PIN_KB_ROW6_PR6,
};
static const unsigned kb_row7_pr7_pins[] = {
TEGRA_PIN_KB_ROW7_PR7,
};
static const unsigned kb_row8_ps0_pins[] = {
TEGRA_PIN_KB_ROW8_PS0,
};
static const unsigned kb_row9_ps1_pins[] = {
TEGRA_PIN_KB_ROW9_PS1,
};
static const unsigned kb_row10_ps2_pins[] = {
TEGRA_PIN_KB_ROW10_PS2,
};
static const unsigned kb_row11_ps3_pins[] = {
TEGRA_PIN_KB_ROW11_PS3,
};
static const unsigned kb_row12_ps4_pins[] = {
TEGRA_PIN_KB_ROW12_PS4,
};
static const unsigned kb_row13_ps5_pins[] = {
TEGRA_PIN_KB_ROW13_PS5,
};
static const unsigned kb_row14_ps6_pins[] = {
TEGRA_PIN_KB_ROW14_PS6,
};
static const unsigned kb_row15_ps7_pins[] = {
TEGRA_PIN_KB_ROW15_PS7,
};
static const unsigned kb_row16_pt0_pins[] = {
TEGRA_PIN_KB_ROW16_PT0,
};
static const unsigned kb_row17_pt1_pins[] = {
TEGRA_PIN_KB_ROW17_PT1,
};
static const unsigned gen2_i2c_scl_pt5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
};
static const unsigned gen2_i2c_sda_pt6_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned sdmmc4_cmd_pt7_pins[] = {
TEGRA_PIN_SDMMC4_CMD_PT7,
};
static const unsigned pu0_pins[] = {
TEGRA_PIN_PU0,
};
static const unsigned pu1_pins[] = {
TEGRA_PIN_PU1,
};
static const unsigned pu2_pins[] = {
TEGRA_PIN_PU2,
};
static const unsigned pu3_pins[] = {
TEGRA_PIN_PU3,
};
static const unsigned pu4_pins[] = {
TEGRA_PIN_PU4,
};
static const unsigned pu5_pins[] = {
TEGRA_PIN_PU5,
};
static const unsigned pu6_pins[] = {
TEGRA_PIN_PU6,
};
static const unsigned pv0_pins[] = {
TEGRA_PIN_PV0,
};
static const unsigned pv1_pins[] = {
TEGRA_PIN_PV1,
};
static const unsigned sdmmc3_cd_n_pv2_pins[] = {
TEGRA_PIN_SDMMC3_CD_N_PV2,
};
static const unsigned sdmmc1_wp_n_pv3_pins[] = {
TEGRA_PIN_SDMMC1_WP_N_PV3,
};
static const unsigned ddc_scl_pv4_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
};
static const unsigned ddc_sda_pv5_pins[] = {
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned gpio_w2_aud_pw2_pins[] = {
TEGRA_PIN_GPIO_W2_AUD_PW2,
};
static const unsigned gpio_w3_aud_pw3_pins[] = {
TEGRA_PIN_GPIO_W3_AUD_PW3,
};
static const unsigned dap_mclk1_pw4_pins[] = {
TEGRA_PIN_DAP_MCLK1_PW4,
};
static const unsigned clk2_out_pw5_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
};
static const unsigned uart3_txd_pw6_pins[] = {
TEGRA_PIN_UART3_TXD_PW6,
};
static const unsigned uart3_rxd_pw7_pins[] = {
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned dvfs_pwm_px0_pins[] = {
TEGRA_PIN_DVFS_PWM_PX0,
};
static const unsigned gpio_x1_aud_px1_pins[] = {
TEGRA_PIN_GPIO_X1_AUD_PX1,
};
static const unsigned dvfs_clk_px2_pins[] = {
TEGRA_PIN_DVFS_CLK_PX2,
};
static const unsigned gpio_x3_aud_px3_pins[] = {
TEGRA_PIN_GPIO_X3_AUD_PX3,
};
static const unsigned gpio_x4_aud_px4_pins[] = {
TEGRA_PIN_GPIO_X4_AUD_PX4,
};
static const unsigned gpio_x5_aud_px5_pins[] = {
TEGRA_PIN_GPIO_X5_AUD_PX5,
};
static const unsigned gpio_x6_aud_px6_pins[] = {
TEGRA_PIN_GPIO_X6_AUD_PX6,
};
static const unsigned gpio_x7_aud_px7_pins[] = {
TEGRA_PIN_GPIO_X7_AUD_PX7,
};
static const unsigned ulpi_clk_py0_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
};
static const unsigned ulpi_dir_py1_pins[] = {
TEGRA_PIN_ULPI_DIR_PY1,
};
static const unsigned ulpi_nxt_py2_pins[] = {
TEGRA_PIN_ULPI_NXT_PY2,
};
static const unsigned ulpi_stp_py3_pins[] = {
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned sdmmc1_dat3_py4_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
};
static const unsigned sdmmc1_dat2_py5_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PY5,
};
static const unsigned sdmmc1_dat1_py6_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PY6,
};
static const unsigned sdmmc1_dat0_py7_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PY7,
};
static const unsigned sdmmc1_clk_pz0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PZ0,
};
static const unsigned sdmmc1_cmd_pz1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned pwr_i2c_scl_pz6_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PZ6,
};
static const unsigned pwr_i2c_sda_pz7_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned sdmmc4_dat0_paa0_pins[] = {
TEGRA_PIN_SDMMC4_DAT0_PAA0,
};
static const unsigned sdmmc4_dat1_paa1_pins[] = {
TEGRA_PIN_SDMMC4_DAT1_PAA1,
};
static const unsigned sdmmc4_dat2_paa2_pins[] = {
TEGRA_PIN_SDMMC4_DAT2_PAA2,
};
static const unsigned sdmmc4_dat3_paa3_pins[] = {
TEGRA_PIN_SDMMC4_DAT3_PAA3,
};
static const unsigned sdmmc4_dat4_paa4_pins[] = {
TEGRA_PIN_SDMMC4_DAT4_PAA4,
};
static const unsigned sdmmc4_dat5_paa5_pins[] = {
TEGRA_PIN_SDMMC4_DAT5_PAA5,
};
static const unsigned sdmmc4_dat6_paa6_pins[] = {
TEGRA_PIN_SDMMC4_DAT6_PAA6,
};
static const unsigned sdmmc4_dat7_paa7_pins[] = {
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned pbb0_pins[] = {
TEGRA_PIN_PBB0,
};
static const unsigned cam_i2c_scl_pbb1_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PBB1,
};
static const unsigned cam_i2c_sda_pbb2_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PBB2,
};
static const unsigned pbb3_pins[] = {
TEGRA_PIN_PBB3,
};
static const unsigned pbb4_pins[] = {
TEGRA_PIN_PBB4,
};
static const unsigned pbb5_pins[] = {
TEGRA_PIN_PBB5,
};
static const unsigned pbb6_pins[] = {
TEGRA_PIN_PBB6,
};
static const unsigned pbb7_pins[] = {
TEGRA_PIN_PBB7,
};
static const unsigned cam_mclk_pcc0_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned pcc1_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned pcc2_pins[] = {
TEGRA_PIN_PCC2,
};
static const unsigned sdmmc4_clk_pcc4_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
};
static const unsigned clk2_req_pcc5_pins[] = {
TEGRA_PIN_CLK2_REQ_PCC5,
};
static const unsigned pex_l0_rst_n_pdd1_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PDD1,
};
static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
};
static const unsigned pex_wake_n_pdd3_pins[] = {
TEGRA_PIN_PEX_WAKE_N_PDD3,
};
static const unsigned pex_l1_rst_n_pdd5_pins[] = {
TEGRA_PIN_PEX_L1_RST_N_PDD5,
};
static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
};
static const unsigned clk3_out_pee0_pins[] = {
TEGRA_PIN_CLK3_OUT_PEE0,
};
static const unsigned clk3_req_pee1_pins[] = {
TEGRA_PIN_CLK3_REQ_PEE1,
};
static const unsigned dap_mclk1_req_pee2_pins[] = {
TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
};
static const unsigned hdmi_cec_pee3_pins[] = {
TEGRA_PIN_HDMI_CEC_PEE3,
};
static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
};
static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
};
static const unsigned dp_hpd_pff0_pins[] = {
TEGRA_PIN_DP_HPD_PFF0,
};
static const unsigned usb_vbus_en2_pff1_pins[] = {
TEGRA_PIN_USB_VBUS_EN2_PFF1,
};
static const unsigned pff2_pins[] = {
TEGRA_PIN_PFF2,
};
static const unsigned core_pwr_req_pins[] = {
TEGRA_PIN_CORE_PWR_REQ,
};
static const unsigned cpu_pwr_req_pins[] = {
TEGRA_PIN_CPU_PWR_REQ,
};
static const unsigned pwr_int_n_pins[] = {
TEGRA_PIN_PWR_INT_N,
};
static const unsigned gmi_clk_lb_pins[] = {
TEGRA_PIN_GMI_CLK_LB,
};
static const unsigned reset_out_n_pins[] = {
TEGRA_PIN_RESET_OUT_N,
};
static const unsigned owr_pins[] = {
TEGRA_PIN_OWR,
};
static const unsigned clk_32k_in_pins[] = {
TEGRA_PIN_CLK_32K_IN,
};
static const unsigned jtag_rtck_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned drive_ao1_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
TEGRA_PIN_KB_ROW7_PR7,
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned drive_ao2_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
TEGRA_PIN_CLK_32K_IN,
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
TEGRA_PIN_KB_COL7_PQ7,
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_KB_ROW11_PS3,
TEGRA_PIN_KB_ROW12_PS4,
TEGRA_PIN_KB_ROW13_PS5,
TEGRA_PIN_KB_ROW14_PS6,
TEGRA_PIN_KB_ROW15_PS7,
TEGRA_PIN_KB_ROW16_PT0,
TEGRA_PIN_KB_ROW17_PT1,
TEGRA_PIN_SDMMC3_CD_N_PV2,
TEGRA_PIN_CORE_PWR_REQ,
TEGRA_PIN_CPU_PWR_REQ,
TEGRA_PIN_PWR_INT_N,
};
static const unsigned drive_at1_pins[] = {
TEGRA_PIN_PH0,
TEGRA_PIN_PH1,
TEGRA_PIN_PH2,
TEGRA_PIN_PH3,
};
static const unsigned drive_at2_pins[] = {
TEGRA_PIN_PG0,
TEGRA_PIN_PG1,
TEGRA_PIN_PG2,
TEGRA_PIN_PG3,
TEGRA_PIN_PG4,
TEGRA_PIN_PG5,
TEGRA_PIN_PG6,
TEGRA_PIN_PG7,
TEGRA_PIN_PI0,
TEGRA_PIN_PI1,
TEGRA_PIN_PI3,
TEGRA_PIN_PI4,
TEGRA_PIN_PI7,
TEGRA_PIN_PK0,
TEGRA_PIN_PK2,
};
static const unsigned drive_at3_pins[] = {
TEGRA_PIN_PC7,
TEGRA_PIN_PJ0,
};
static const unsigned drive_at4_pins[] = {
TEGRA_PIN_PB0,
TEGRA_PIN_PB1,
TEGRA_PIN_PJ0,
TEGRA_PIN_PJ7,
TEGRA_PIN_PK7,
};
static const unsigned drive_at5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned drive_cdev1_pins[] = {
TEGRA_PIN_DAP_MCLK1_PW4,
TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
};
static const unsigned drive_cdev2_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
TEGRA_PIN_CLK2_REQ_PCC5,
};
static const unsigned drive_dap1_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned drive_dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned drive_dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned drive_dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned drive_dbg_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
TEGRA_PIN_GEN1_I2C_SDA_PC5,
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
};
static const unsigned drive_sdio3_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
TEGRA_PIN_SDMMC3_CMD_PA7,
TEGRA_PIN_SDMMC3_DAT3_PB4,
TEGRA_PIN_SDMMC3_DAT2_PB5,
TEGRA_PIN_SDMMC3_DAT1_PB6,
TEGRA_PIN_SDMMC3_DAT0_PB7,
TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
};
static const unsigned drive_spi_pins[] = {
TEGRA_PIN_DVFS_PWM_PX0,
TEGRA_PIN_GPIO_X1_AUD_PX1,
TEGRA_PIN_DVFS_CLK_PX2,
TEGRA_PIN_GPIO_X3_AUD_PX3,
TEGRA_PIN_GPIO_X4_AUD_PX4,
TEGRA_PIN_GPIO_X5_AUD_PX5,
TEGRA_PIN_GPIO_X6_AUD_PX6,
TEGRA_PIN_GPIO_X7_AUD_PX7,
TEGRA_PIN_GPIO_W2_AUD_PW2,
TEGRA_PIN_GPIO_W3_AUD_PW3,
};
static const unsigned drive_uaa_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
TEGRA_PIN_ULPI_DATA1_PO2,
TEGRA_PIN_ULPI_DATA2_PO3,
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned drive_uab_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
TEGRA_PIN_ULPI_DATA4_PO5,
TEGRA_PIN_ULPI_DATA5_PO6,
TEGRA_PIN_ULPI_DATA6_PO7,
TEGRA_PIN_PV0,
TEGRA_PIN_PV1,
};
static const unsigned drive_uart2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
TEGRA_PIN_UART2_RXD_PC3,
TEGRA_PIN_UART2_CTS_N_PJ5,
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned drive_uart3_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
TEGRA_PIN_UART3_RTS_N_PC0,
TEGRA_PIN_UART3_TXD_PW6,
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned drive_sdio1_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
TEGRA_PIN_SDMMC1_DAT2_PY5,
TEGRA_PIN_SDMMC1_DAT1_PY6,
TEGRA_PIN_SDMMC1_DAT0_PY7,
TEGRA_PIN_SDMMC1_CLK_PZ0,
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned drive_ddc_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned drive_gma_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
TEGRA_PIN_SDMMC4_CMD_PT7,
TEGRA_PIN_SDMMC4_DAT0_PAA0,
TEGRA_PIN_SDMMC4_DAT1_PAA1,
TEGRA_PIN_SDMMC4_DAT2_PAA2,
TEGRA_PIN_SDMMC4_DAT3_PAA3,
TEGRA_PIN_SDMMC4_DAT4_PAA4,
TEGRA_PIN_SDMMC4_DAT5_PAA5,
TEGRA_PIN_SDMMC4_DAT6_PAA6,
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned drive_gme_pins[] = {
TEGRA_PIN_PBB0,
TEGRA_PIN_CAM_I2C_SCL_PBB1,
TEGRA_PIN_CAM_I2C_SDA_PBB2,
TEGRA_PIN_PBB3,
TEGRA_PIN_PCC2,
};
static const unsigned drive_gmf_pins[] = {
TEGRA_PIN_PBB4,
TEGRA_PIN_PBB5,
TEGRA_PIN_PBB6,
TEGRA_PIN_PBB7,
};
static const unsigned drive_gmg_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned drive_gmh_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned drive_owr_pins[] = {
TEGRA_PIN_SDMMC3_CD_N_PV2,
TEGRA_PIN_OWR,
};
static const unsigned drive_uda_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
TEGRA_PIN_ULPI_DIR_PY1,
TEGRA_PIN_ULPI_NXT_PY2,
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned drive_gpv_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PDD1,
TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
TEGRA_PIN_PEX_WAKE_N_PDD3,
TEGRA_PIN_PEX_L1_RST_N_PDD5,
TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
TEGRA_PIN_USB_VBUS_EN2_PFF1,
TEGRA_PIN_PFF2,
};
static const unsigned drive_dev3_pins[] = {
TEGRA_PIN_CLK3_OUT_PEE0,
TEGRA_PIN_CLK3_REQ_PEE1,
};
static const unsigned drive_cec_pins[] = {
TEGRA_PIN_HDMI_CEC_PEE3,
};
static const unsigned drive_at6_pins[] = {
TEGRA_PIN_PK1,
TEGRA_PIN_PK3,
TEGRA_PIN_PK4,
TEGRA_PIN_PI2,
TEGRA_PIN_PI5,
TEGRA_PIN_PI6,
TEGRA_PIN_PH4,
TEGRA_PIN_PH5,
TEGRA_PIN_PH6,
TEGRA_PIN_PH7,
};
static const unsigned drive_dap5_pins[] = {
TEGRA_PIN_SPDIF_IN_PK6,
TEGRA_PIN_SPDIF_OUT_PK5,
TEGRA_PIN_DP_HPD_PFF0,
};
static const unsigned drive_usb_vbus_en_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PN4,
TEGRA_PIN_USB_VBUS_EN1_PN5,
};
static const unsigned drive_ao3_pins[] = {
TEGRA_PIN_RESET_OUT_N,
};
static const unsigned drive_ao0_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned drive_hv0_pins[] = {
TEGRA_PIN_HDMI_INT_PN7,
};
static const unsigned drive_sdio4_pins[] = {
TEGRA_PIN_SDMMC1_WP_N_PV3,
};
static const unsigned drive_ao4_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
TEGRA_PIN_DSI_B_CLK_P,
TEGRA_PIN_DSI_B_CLK_N,
TEGRA_PIN_DSI_B_D0_P,
TEGRA_PIN_DSI_B_D0_N,
TEGRA_PIN_DSI_B_D1_P,
TEGRA_PIN_DSI_B_D1_N,
TEGRA_PIN_DSI_B_D2_P,
TEGRA_PIN_DSI_B_D2_N,
TEGRA_PIN_DSI_B_D3_P,
TEGRA_PIN_DSI_B_D3_N,
};
enum tegra_mux {
TEGRA_MUX_BLINK,
TEGRA_MUX_CCLA,
TEGRA_MUX_CEC,
TEGRA_MUX_CLDVFS,
TEGRA_MUX_CLK,
TEGRA_MUX_CLK12,
TEGRA_MUX_CPU,
TEGRA_MUX_CSI,
TEGRA_MUX_DAP,
TEGRA_MUX_DAP1,
TEGRA_MUX_DAP2,
TEGRA_MUX_DEV3,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYA_ALT,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DP,
TEGRA_MUX_DSI_B,
TEGRA_MUX_DTV,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_IRDA,
TEGRA_MUX_KBC,
TEGRA_MUX_OWR,
TEGRA_MUX_PE,
TEGRA_MUX_PE0,
TEGRA_MUX_PE1,
TEGRA_MUX_PMI,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_PWRON,
TEGRA_MUX_RESET_OUT_N,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_RSVD4,
TEGRA_MUX_RTCK,
TEGRA_MUX_SATA,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_SDMMC2,
TEGRA_MUX_SDMMC3,
TEGRA_MUX_SDMMC4,
TEGRA_MUX_SOC,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYS,
TEGRA_MUX_TMDS,
TEGRA_MUX_TRACE,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_ULPI,
TEGRA_MUX_USB,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_VI,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_VIMCLK2,
TEGRA_MUX_VIMCLK2_ALT,
};
#define FUNCTION(fname) #fname
static const char * const tegra124_functions[] = {
FUNCTION(blink),
FUNCTION(ccla),
FUNCTION(cec),
FUNCTION(cldvfs),
FUNCTION(clk),
FUNCTION(clk12),
FUNCTION(cpu),
FUNCTION(csi),
FUNCTION(dap),
FUNCTION(dap1),
FUNCTION(dap2),
FUNCTION(dev3),
FUNCTION(displaya),
FUNCTION(displaya_alt),
FUNCTION(displayb),
FUNCTION(dp),
FUNCTION(dsi_b),
FUNCTION(dtv),
FUNCTION(extperiph1),
FUNCTION(extperiph2),
FUNCTION(extperiph3),
FUNCTION(gmi),
FUNCTION(gmi_alt),
FUNCTION(hda),
FUNCTION(hsi),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2c4),
FUNCTION(i2cpwr),
FUNCTION(i2s0),
FUNCTION(i2s1),
FUNCTION(i2s2),
FUNCTION(i2s3),
FUNCTION(i2s4),
FUNCTION(irda),
FUNCTION(kbc),
FUNCTION(owr),
FUNCTION(pe),
FUNCTION(pe0),
FUNCTION(pe1),
FUNCTION(pmi),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(pwron),
FUNCTION(reset_out_n),
FUNCTION(rsvd1),
FUNCTION(rsvd2),
FUNCTION(rsvd3),
FUNCTION(rsvd4),
FUNCTION(rtck),
FUNCTION(sata),
FUNCTION(sdmmc1),
FUNCTION(sdmmc2),
FUNCTION(sdmmc3),
FUNCTION(sdmmc4),
FUNCTION(soc),
FUNCTION(spdif),
FUNCTION(spi1),
FUNCTION(spi2),
FUNCTION(spi3),
FUNCTION(spi4),
FUNCTION(spi5),
FUNCTION(spi6),
FUNCTION(sys),
FUNCTION(tmds),
FUNCTION(trace),
FUNCTION(uarta),
FUNCTION(uartb),
FUNCTION(uartc),
FUNCTION(uartd),
FUNCTION(ulpi),
FUNCTION(usb),
FUNCTION(vgp1),
FUNCTION(vgp2),
FUNCTION(vgp3),
FUNCTION(vgp4),
FUNCTION(vgp5),
FUNCTION(vgp6),
FUNCTION(vi),
FUNCTION(vi_alt1),
FUNCTION(vi_alt3),
FUNCTION(vimclk2),
FUNCTION(vimclk2_alt),
};
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
#define PINGROUP_BIT_Y(b) (b)
#define PINGROUP_BIT_N(b) (-1)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
.mux_reg = PINGROUP_REG(r), \
.mux_bank = 1, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG(r), \
.pupd_bank = 1, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG(r), \
.tri_bank = 1, \
.tri_bit = 4, \
.einput_bit = 5, \
.odrain_bit = PINGROUP_BIT_##od(6), \
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
.drv_reg = -1, \
.parked_bitmask = 0, \
}
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
slwf_b, slwf_w, drvtype) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \
.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
.parked_bitmask = 0, \
}
#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
{ \
.name = "mipi_pad_ctrl_" #pg_name, \
.pins = mipi_pad_ctrl_##pg_name##_pins, \
.npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
.funcs = { \
TEGRA_MUX_ ## f0, \
TEGRA_MUX_ ## f1, \
TEGRA_MUX_RSVD3, \
TEGRA_MUX_RSVD4, \
}, \
.mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
.mux_bank = 2, \
.mux_bit = b, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = -1, \
}
static const struct tegra_pingroup tegra124_groups[] = {
/* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N),
PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N),
PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N),
PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N),
PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N),
PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N),
PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N),
PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N),
PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N),
PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N),
PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N),
PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N),
PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N),
PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N),
PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N),
PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N),
PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N),
PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N),
PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N),
PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N),
PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N),
PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N),
PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N),
PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N),
PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N),
PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N),
PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N),
PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N),
PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N),
PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N),
PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N),
PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N),
PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N),
PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N),
PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N),
PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N),
PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N),
PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N),
PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N),
PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N),
PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N),
PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N),
PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N),
PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N),
PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N),
PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N),
PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N),
PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N),
PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N),
PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N),
PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N),
PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N),
PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N),
PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N),
PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N),
PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N),
PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N),
PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N),
PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N),
PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N),
PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N),
PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N),
PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N),
PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N),
PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N),
PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N),
PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N),
PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N),
PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N),
PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N),
PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N),
PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N),
PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N),
PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N),
PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N),
PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N),
PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N),
PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N),
PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N),
PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N),
PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N),
PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N),
PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N),
PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N),
PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N),
PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N),
PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N),
PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N),
PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N),
PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N),
PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N),
PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N),
PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N),
PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N),
PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N),
PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N),
PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N),
PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N),
PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N),
PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N),
PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N),
PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N),
PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
/* pg_name, r, b, f0, f1 */
MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
};
static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra124-gpio",
.pins = tegra124_pins,
.npins = ARRAY_SIZE(tegra124_pins),
.functions = tegra124_functions,
.nfunctions = ARRAY_SIZE(tegra124_functions),
.groups = tegra124_groups,
.ngroups = ARRAY_SIZE(tegra124_groups),
.hsm_in_mux = false,
.schmitt_in_mux = false,
.drvtype_in_mux = false,
};
static int tegra124_pinctrl_probe(struct platform_device *pdev)
{
return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
}
static const struct of_device_id tegra124_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra124-pinmux", },
{ },
};
static struct platform_driver tegra124_pinctrl_driver = {
.driver = {
.name = "tegra124-pinctrl",
.of_match_table = tegra124_pinctrl_of_match,
},
.probe = tegra124_pinctrl_probe,
};
static int __init tegra124_pinctrl_init(void)
{
return platform_driver_register(&tegra124_pinctrl_driver);
}
arch_initcall(tegra124_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra124.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for the NVIDIA Tegra30 pinmux
*
* Author: Stephen Warren <[email protected]>
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
#define TEGRA_PIN_SDMMC3_DAT5_PD0 _GPIO(24)
#define TEGRA_PIN_SDMMC3_DAT4_PD1 _GPIO(25)
#define TEGRA_PIN_LCD_DC1_PD2 _GPIO(26)
#define TEGRA_PIN_SDMMC3_DAT6_PD3 _GPIO(27)
#define TEGRA_PIN_SDMMC3_DAT7_PD4 _GPIO(28)
#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
#define TEGRA_PIN_GMI_DQS_PI2 _GPIO(66)
#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
#define TEGRA_PIN_PU0 _GPIO(160)
#define TEGRA_PIN_PU1 _GPIO(161)
#define TEGRA_PIN_PU2 _GPIO(162)
#define TEGRA_PIN_PU3 _GPIO(163)
#define TEGRA_PIN_PU4 _GPIO(164)
#define TEGRA_PIN_PU5 _GPIO(165)
#define TEGRA_PIN_PU6 _GPIO(166)
#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
#define TEGRA_PIN_PV0 _GPIO(168)
#define TEGRA_PIN_PV1 _GPIO(169)
#define TEGRA_PIN_PV2 _GPIO(170)
#define TEGRA_PIN_PV3 _GPIO(171)
#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
#define TEGRA_PIN_CRT_HSYNC_PV6 _GPIO(174)
#define TEGRA_PIN_CRT_VSYNC_PV7 _GPIO(175)
#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
#define TEGRA_PIN_PBB0 _GPIO(216)
#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
#define TEGRA_PIN_PBB3 _GPIO(219)
#define TEGRA_PIN_PBB4 _GPIO(220)
#define TEGRA_PIN_PBB5 _GPIO(221)
#define TEGRA_PIN_PBB6 _GPIO(222)
#define TEGRA_PIN_PBB7 _GPIO(223)
#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
#define TEGRA_PIN_PCC1 _GPIO(225)
#define TEGRA_PIN_PCC2 _GPIO(226)
#define TEGRA_PIN_SDMMC4_RST_N_PCC3 _GPIO(227)
#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
#define TEGRA_PIN_PEX_L2_RST_N_PCC6 _GPIO(230)
#define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7 _GPIO(231)
#define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0 _GPIO(232)
#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
#define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4 _GPIO(236)
#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
#define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7 _GPIO(239)
#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
#define TEGRA_PIN_PEE4 _GPIO(244)
#define TEGRA_PIN_PEE5 _GPIO(245)
#define TEGRA_PIN_PEE6 _GPIO(246)
#define TEGRA_PIN_PEE7 _GPIO(247)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
/* Non-GPIO pins */
#define TEGRA_PIN_CLK_32K_IN _PIN(0)
#define TEGRA_PIN_CORE_PWR_REQ _PIN(1)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(2)
#define TEGRA_PIN_JTAG_TCK _PIN(3)
#define TEGRA_PIN_JTAG_TDI _PIN(4)
#define TEGRA_PIN_JTAG_TDO _PIN(5)
#define TEGRA_PIN_JTAG_TMS _PIN(6)
#define TEGRA_PIN_JTAG_TRST_N _PIN(7)
#define TEGRA_PIN_OWR _PIN(8)
#define TEGRA_PIN_PWR_INT_N _PIN(9)
#define TEGRA_PIN_SYS_RESET_N _PIN(10)
#define TEGRA_PIN_TEST_MODE_EN _PIN(11)
static const struct pinctrl_pin_desc tegra30_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
};
static const unsigned clk_32k_out_pa0_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
};
static const unsigned uart3_cts_n_pa1_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
};
static const unsigned dap2_fs_pa2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
};
static const unsigned dap2_sclk_pa3_pins[] = {
TEGRA_PIN_DAP2_SCLK_PA3,
};
static const unsigned dap2_din_pa4_pins[] = {
TEGRA_PIN_DAP2_DIN_PA4,
};
static const unsigned dap2_dout_pa5_pins[] = {
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned sdmmc3_clk_pa6_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
};
static const unsigned sdmmc3_cmd_pa7_pins[] = {
TEGRA_PIN_SDMMC3_CMD_PA7,
};
static const unsigned gmi_a17_pb0_pins[] = {
TEGRA_PIN_GMI_A17_PB0,
};
static const unsigned gmi_a18_pb1_pins[] = {
TEGRA_PIN_GMI_A18_PB1,
};
static const unsigned lcd_pwr0_pb2_pins[] = {
TEGRA_PIN_LCD_PWR0_PB2,
};
static const unsigned lcd_pclk_pb3_pins[] = {
TEGRA_PIN_LCD_PCLK_PB3,
};
static const unsigned sdmmc3_dat3_pb4_pins[] = {
TEGRA_PIN_SDMMC3_DAT3_PB4,
};
static const unsigned sdmmc3_dat2_pb5_pins[] = {
TEGRA_PIN_SDMMC3_DAT2_PB5,
};
static const unsigned sdmmc3_dat1_pb6_pins[] = {
TEGRA_PIN_SDMMC3_DAT1_PB6,
};
static const unsigned sdmmc3_dat0_pb7_pins[] = {
TEGRA_PIN_SDMMC3_DAT0_PB7,
};
static const unsigned uart3_rts_n_pc0_pins[] = {
TEGRA_PIN_UART3_RTS_N_PC0,
};
static const unsigned lcd_pwr1_pc1_pins[] = {
TEGRA_PIN_LCD_PWR1_PC1,
};
static const unsigned uart2_txd_pc2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
};
static const unsigned uart2_rxd_pc3_pins[] = {
TEGRA_PIN_UART2_RXD_PC3,
};
static const unsigned gen1_i2c_scl_pc4_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
};
static const unsigned gen1_i2c_sda_pc5_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PC5,
};
static const unsigned lcd_pwr2_pc6_pins[] = {
TEGRA_PIN_LCD_PWR2_PC6,
};
static const unsigned gmi_wp_n_pc7_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
};
static const unsigned sdmmc3_dat5_pd0_pins[] = {
TEGRA_PIN_SDMMC3_DAT5_PD0,
};
static const unsigned sdmmc3_dat4_pd1_pins[] = {
TEGRA_PIN_SDMMC3_DAT4_PD1,
};
static const unsigned lcd_dc1_pd2_pins[] = {
TEGRA_PIN_LCD_DC1_PD2,
};
static const unsigned sdmmc3_dat6_pd3_pins[] = {
TEGRA_PIN_SDMMC3_DAT6_PD3,
};
static const unsigned sdmmc3_dat7_pd4_pins[] = {
TEGRA_PIN_SDMMC3_DAT7_PD4,
};
static const unsigned vi_d1_pd5_pins[] = {
TEGRA_PIN_VI_D1_PD5,
};
static const unsigned vi_vsync_pd6_pins[] = {
TEGRA_PIN_VI_VSYNC_PD6,
};
static const unsigned vi_hsync_pd7_pins[] = {
TEGRA_PIN_VI_HSYNC_PD7,
};
static const unsigned lcd_d0_pe0_pins[] = {
TEGRA_PIN_LCD_D0_PE0,
};
static const unsigned lcd_d1_pe1_pins[] = {
TEGRA_PIN_LCD_D1_PE1,
};
static const unsigned lcd_d2_pe2_pins[] = {
TEGRA_PIN_LCD_D2_PE2,
};
static const unsigned lcd_d3_pe3_pins[] = {
TEGRA_PIN_LCD_D3_PE3,
};
static const unsigned lcd_d4_pe4_pins[] = {
TEGRA_PIN_LCD_D4_PE4,
};
static const unsigned lcd_d5_pe5_pins[] = {
TEGRA_PIN_LCD_D5_PE5,
};
static const unsigned lcd_d6_pe6_pins[] = {
TEGRA_PIN_LCD_D6_PE6,
};
static const unsigned lcd_d7_pe7_pins[] = {
TEGRA_PIN_LCD_D7_PE7,
};
static const unsigned lcd_d8_pf0_pins[] = {
TEGRA_PIN_LCD_D8_PF0,
};
static const unsigned lcd_d9_pf1_pins[] = {
TEGRA_PIN_LCD_D9_PF1,
};
static const unsigned lcd_d10_pf2_pins[] = {
TEGRA_PIN_LCD_D10_PF2,
};
static const unsigned lcd_d11_pf3_pins[] = {
TEGRA_PIN_LCD_D11_PF3,
};
static const unsigned lcd_d12_pf4_pins[] = {
TEGRA_PIN_LCD_D12_PF4,
};
static const unsigned lcd_d13_pf5_pins[] = {
TEGRA_PIN_LCD_D13_PF5,
};
static const unsigned lcd_d14_pf6_pins[] = {
TEGRA_PIN_LCD_D14_PF6,
};
static const unsigned lcd_d15_pf7_pins[] = {
TEGRA_PIN_LCD_D15_PF7,
};
static const unsigned gmi_ad0_pg0_pins[] = {
TEGRA_PIN_GMI_AD0_PG0,
};
static const unsigned gmi_ad1_pg1_pins[] = {
TEGRA_PIN_GMI_AD1_PG1,
};
static const unsigned gmi_ad2_pg2_pins[] = {
TEGRA_PIN_GMI_AD2_PG2,
};
static const unsigned gmi_ad3_pg3_pins[] = {
TEGRA_PIN_GMI_AD3_PG3,
};
static const unsigned gmi_ad4_pg4_pins[] = {
TEGRA_PIN_GMI_AD4_PG4,
};
static const unsigned gmi_ad5_pg5_pins[] = {
TEGRA_PIN_GMI_AD5_PG5,
};
static const unsigned gmi_ad6_pg6_pins[] = {
TEGRA_PIN_GMI_AD6_PG6,
};
static const unsigned gmi_ad7_pg7_pins[] = {
TEGRA_PIN_GMI_AD7_PG7,
};
static const unsigned gmi_ad8_ph0_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
};
static const unsigned gmi_ad9_ph1_pins[] = {
TEGRA_PIN_GMI_AD9_PH1,
};
static const unsigned gmi_ad10_ph2_pins[] = {
TEGRA_PIN_GMI_AD10_PH2,
};
static const unsigned gmi_ad11_ph3_pins[] = {
TEGRA_PIN_GMI_AD11_PH3,
};
static const unsigned gmi_ad12_ph4_pins[] = {
TEGRA_PIN_GMI_AD12_PH4,
};
static const unsigned gmi_ad13_ph5_pins[] = {
TEGRA_PIN_GMI_AD13_PH5,
};
static const unsigned gmi_ad14_ph6_pins[] = {
TEGRA_PIN_GMI_AD14_PH6,
};
static const unsigned gmi_ad15_ph7_pins[] = {
TEGRA_PIN_GMI_AD15_PH7,
};
static const unsigned gmi_wr_n_pi0_pins[] = {
TEGRA_PIN_GMI_WR_N_PI0,
};
static const unsigned gmi_oe_n_pi1_pins[] = {
TEGRA_PIN_GMI_OE_N_PI1,
};
static const unsigned gmi_dqs_pi2_pins[] = {
TEGRA_PIN_GMI_DQS_PI2,
};
static const unsigned gmi_cs6_n_pi3_pins[] = {
TEGRA_PIN_GMI_CS6_N_PI3,
};
static const unsigned gmi_rst_n_pi4_pins[] = {
TEGRA_PIN_GMI_RST_N_PI4,
};
static const unsigned gmi_iordy_pi5_pins[] = {
TEGRA_PIN_GMI_IORDY_PI5,
};
static const unsigned gmi_cs7_n_pi6_pins[] = {
TEGRA_PIN_GMI_CS7_N_PI6,
};
static const unsigned gmi_wait_pi7_pins[] = {
TEGRA_PIN_GMI_WAIT_PI7,
};
static const unsigned gmi_cs0_n_pj0_pins[] = {
TEGRA_PIN_GMI_CS0_N_PJ0,
};
static const unsigned lcd_de_pj1_pins[] = {
TEGRA_PIN_LCD_DE_PJ1,
};
static const unsigned gmi_cs1_n_pj2_pins[] = {
TEGRA_PIN_GMI_CS1_N_PJ2,
};
static const unsigned lcd_hsync_pj3_pins[] = {
TEGRA_PIN_LCD_HSYNC_PJ3,
};
static const unsigned lcd_vsync_pj4_pins[] = {
TEGRA_PIN_LCD_VSYNC_PJ4,
};
static const unsigned uart2_cts_n_pj5_pins[] = {
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned uart2_rts_n_pj6_pins[] = {
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned gmi_a16_pj7_pins[] = {
TEGRA_PIN_GMI_A16_PJ7,
};
static const unsigned gmi_adv_n_pk0_pins[] = {
TEGRA_PIN_GMI_ADV_N_PK0,
};
static const unsigned gmi_clk_pk1_pins[] = {
TEGRA_PIN_GMI_CLK_PK1,
};
static const unsigned gmi_cs4_n_pk2_pins[] = {
TEGRA_PIN_GMI_CS4_N_PK2,
};
static const unsigned gmi_cs2_n_pk3_pins[] = {
TEGRA_PIN_GMI_CS2_N_PK3,
};
static const unsigned gmi_cs3_n_pk4_pins[] = {
TEGRA_PIN_GMI_CS3_N_PK4,
};
static const unsigned spdif_out_pk5_pins[] = {
TEGRA_PIN_SPDIF_OUT_PK5,
};
static const unsigned spdif_in_pk6_pins[] = {
TEGRA_PIN_SPDIF_IN_PK6,
};
static const unsigned gmi_a19_pk7_pins[] = {
TEGRA_PIN_GMI_A19_PK7,
};
static const unsigned vi_d2_pl0_pins[] = {
TEGRA_PIN_VI_D2_PL0,
};
static const unsigned vi_d3_pl1_pins[] = {
TEGRA_PIN_VI_D3_PL1,
};
static const unsigned vi_d4_pl2_pins[] = {
TEGRA_PIN_VI_D4_PL2,
};
static const unsigned vi_d5_pl3_pins[] = {
TEGRA_PIN_VI_D5_PL3,
};
static const unsigned vi_d6_pl4_pins[] = {
TEGRA_PIN_VI_D6_PL4,
};
static const unsigned vi_d7_pl5_pins[] = {
TEGRA_PIN_VI_D7_PL5,
};
static const unsigned vi_d8_pl6_pins[] = {
TEGRA_PIN_VI_D8_PL6,
};
static const unsigned vi_d9_pl7_pins[] = {
TEGRA_PIN_VI_D9_PL7,
};
static const unsigned lcd_d16_pm0_pins[] = {
TEGRA_PIN_LCD_D16_PM0,
};
static const unsigned lcd_d17_pm1_pins[] = {
TEGRA_PIN_LCD_D17_PM1,
};
static const unsigned lcd_d18_pm2_pins[] = {
TEGRA_PIN_LCD_D18_PM2,
};
static const unsigned lcd_d19_pm3_pins[] = {
TEGRA_PIN_LCD_D19_PM3,
};
static const unsigned lcd_d20_pm4_pins[] = {
TEGRA_PIN_LCD_D20_PM4,
};
static const unsigned lcd_d21_pm5_pins[] = {
TEGRA_PIN_LCD_D21_PM5,
};
static const unsigned lcd_d22_pm6_pins[] = {
TEGRA_PIN_LCD_D22_PM6,
};
static const unsigned lcd_d23_pm7_pins[] = {
TEGRA_PIN_LCD_D23_PM7,
};
static const unsigned dap1_fs_pn0_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
};
static const unsigned dap1_din_pn1_pins[] = {
TEGRA_PIN_DAP1_DIN_PN1,
};
static const unsigned dap1_dout_pn2_pins[] = {
TEGRA_PIN_DAP1_DOUT_PN2,
};
static const unsigned dap1_sclk_pn3_pins[] = {
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned lcd_cs0_n_pn4_pins[] = {
TEGRA_PIN_LCD_CS0_N_PN4,
};
static const unsigned lcd_sdout_pn5_pins[] = {
TEGRA_PIN_LCD_SDOUT_PN5,
};
static const unsigned lcd_dc0_pn6_pins[] = {
TEGRA_PIN_LCD_DC0_PN6,
};
static const unsigned hdmi_int_pn7_pins[] = {
TEGRA_PIN_HDMI_INT_PN7,
};
static const unsigned ulpi_data7_po0_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
};
static const unsigned ulpi_data0_po1_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
};
static const unsigned ulpi_data1_po2_pins[] = {
TEGRA_PIN_ULPI_DATA1_PO2,
};
static const unsigned ulpi_data2_po3_pins[] = {
TEGRA_PIN_ULPI_DATA2_PO3,
};
static const unsigned ulpi_data3_po4_pins[] = {
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned ulpi_data4_po5_pins[] = {
TEGRA_PIN_ULPI_DATA4_PO5,
};
static const unsigned ulpi_data5_po6_pins[] = {
TEGRA_PIN_ULPI_DATA5_PO6,
};
static const unsigned ulpi_data6_po7_pins[] = {
TEGRA_PIN_ULPI_DATA6_PO7,
};
static const unsigned dap3_fs_pp0_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
};
static const unsigned dap3_din_pp1_pins[] = {
TEGRA_PIN_DAP3_DIN_PP1,
};
static const unsigned dap3_dout_pp2_pins[] = {
TEGRA_PIN_DAP3_DOUT_PP2,
};
static const unsigned dap3_sclk_pp3_pins[] = {
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned dap4_fs_pp4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
};
static const unsigned dap4_din_pp5_pins[] = {
TEGRA_PIN_DAP4_DIN_PP5,
};
static const unsigned dap4_dout_pp6_pins[] = {
TEGRA_PIN_DAP4_DOUT_PP6,
};
static const unsigned dap4_sclk_pp7_pins[] = {
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned kb_col0_pq0_pins[] = {
TEGRA_PIN_KB_COL0_PQ0,
};
static const unsigned kb_col1_pq1_pins[] = {
TEGRA_PIN_KB_COL1_PQ1,
};
static const unsigned kb_col2_pq2_pins[] = {
TEGRA_PIN_KB_COL2_PQ2,
};
static const unsigned kb_col3_pq3_pins[] = {
TEGRA_PIN_KB_COL3_PQ3,
};
static const unsigned kb_col4_pq4_pins[] = {
TEGRA_PIN_KB_COL4_PQ4,
};
static const unsigned kb_col5_pq5_pins[] = {
TEGRA_PIN_KB_COL5_PQ5,
};
static const unsigned kb_col6_pq6_pins[] = {
TEGRA_PIN_KB_COL6_PQ6,
};
static const unsigned kb_col7_pq7_pins[] = {
TEGRA_PIN_KB_COL7_PQ7,
};
static const unsigned kb_row0_pr0_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
};
static const unsigned kb_row1_pr1_pins[] = {
TEGRA_PIN_KB_ROW1_PR1,
};
static const unsigned kb_row2_pr2_pins[] = {
TEGRA_PIN_KB_ROW2_PR2,
};
static const unsigned kb_row3_pr3_pins[] = {
TEGRA_PIN_KB_ROW3_PR3,
};
static const unsigned kb_row4_pr4_pins[] = {
TEGRA_PIN_KB_ROW4_PR4,
};
static const unsigned kb_row5_pr5_pins[] = {
TEGRA_PIN_KB_ROW5_PR5,
};
static const unsigned kb_row6_pr6_pins[] = {
TEGRA_PIN_KB_ROW6_PR6,
};
static const unsigned kb_row7_pr7_pins[] = {
TEGRA_PIN_KB_ROW7_PR7,
};
static const unsigned kb_row8_ps0_pins[] = {
TEGRA_PIN_KB_ROW8_PS0,
};
static const unsigned kb_row9_ps1_pins[] = {
TEGRA_PIN_KB_ROW9_PS1,
};
static const unsigned kb_row10_ps2_pins[] = {
TEGRA_PIN_KB_ROW10_PS2,
};
static const unsigned kb_row11_ps3_pins[] = {
TEGRA_PIN_KB_ROW11_PS3,
};
static const unsigned kb_row12_ps4_pins[] = {
TEGRA_PIN_KB_ROW12_PS4,
};
static const unsigned kb_row13_ps5_pins[] = {
TEGRA_PIN_KB_ROW13_PS5,
};
static const unsigned kb_row14_ps6_pins[] = {
TEGRA_PIN_KB_ROW14_PS6,
};
static const unsigned kb_row15_ps7_pins[] = {
TEGRA_PIN_KB_ROW15_PS7,
};
static const unsigned vi_pclk_pt0_pins[] = {
TEGRA_PIN_VI_PCLK_PT0,
};
static const unsigned vi_mclk_pt1_pins[] = {
TEGRA_PIN_VI_MCLK_PT1,
};
static const unsigned vi_d10_pt2_pins[] = {
TEGRA_PIN_VI_D10_PT2,
};
static const unsigned vi_d11_pt3_pins[] = {
TEGRA_PIN_VI_D11_PT3,
};
static const unsigned vi_d0_pt4_pins[] = {
TEGRA_PIN_VI_D0_PT4,
};
static const unsigned gen2_i2c_scl_pt5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
};
static const unsigned gen2_i2c_sda_pt6_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned sdmmc4_cmd_pt7_pins[] = {
TEGRA_PIN_SDMMC4_CMD_PT7,
};
static const unsigned pu0_pins[] = {
TEGRA_PIN_PU0,
};
static const unsigned pu1_pins[] = {
TEGRA_PIN_PU1,
};
static const unsigned pu2_pins[] = {
TEGRA_PIN_PU2,
};
static const unsigned pu3_pins[] = {
TEGRA_PIN_PU3,
};
static const unsigned pu4_pins[] = {
TEGRA_PIN_PU4,
};
static const unsigned pu5_pins[] = {
TEGRA_PIN_PU5,
};
static const unsigned pu6_pins[] = {
TEGRA_PIN_PU6,
};
static const unsigned jtag_rtck_pu7_pins[] = {
TEGRA_PIN_JTAG_RTCK_PU7,
};
static const unsigned pv0_pins[] = {
TEGRA_PIN_PV0,
};
static const unsigned pv1_pins[] = {
TEGRA_PIN_PV1,
};
static const unsigned pv2_pins[] = {
TEGRA_PIN_PV2,
};
static const unsigned pv3_pins[] = {
TEGRA_PIN_PV3,
};
static const unsigned ddc_scl_pv4_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
};
static const unsigned ddc_sda_pv5_pins[] = {
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned crt_hsync_pv6_pins[] = {
TEGRA_PIN_CRT_HSYNC_PV6,
};
static const unsigned crt_vsync_pv7_pins[] = {
TEGRA_PIN_CRT_VSYNC_PV7,
};
static const unsigned lcd_cs1_n_pw0_pins[] = {
TEGRA_PIN_LCD_CS1_N_PW0,
};
static const unsigned lcd_m1_pw1_pins[] = {
TEGRA_PIN_LCD_M1_PW1,
};
static const unsigned spi2_cs1_n_pw2_pins[] = {
TEGRA_PIN_SPI2_CS1_N_PW2,
};
static const unsigned spi2_cs2_n_pw3_pins[] = {
TEGRA_PIN_SPI2_CS2_N_PW3,
};
static const unsigned clk1_out_pw4_pins[] = {
TEGRA_PIN_CLK1_OUT_PW4,
};
static const unsigned clk2_out_pw5_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
};
static const unsigned uart3_txd_pw6_pins[] = {
TEGRA_PIN_UART3_TXD_PW6,
};
static const unsigned uart3_rxd_pw7_pins[] = {
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned spi2_mosi_px0_pins[] = {
TEGRA_PIN_SPI2_MOSI_PX0,
};
static const unsigned spi2_miso_px1_pins[] = {
TEGRA_PIN_SPI2_MISO_PX1,
};
static const unsigned spi2_sck_px2_pins[] = {
TEGRA_PIN_SPI2_SCK_PX2,
};
static const unsigned spi2_cs0_n_px3_pins[] = {
TEGRA_PIN_SPI2_CS0_N_PX3,
};
static const unsigned spi1_mosi_px4_pins[] = {
TEGRA_PIN_SPI1_MOSI_PX4,
};
static const unsigned spi1_sck_px5_pins[] = {
TEGRA_PIN_SPI1_SCK_PX5,
};
static const unsigned spi1_cs0_n_px6_pins[] = {
TEGRA_PIN_SPI1_CS0_N_PX6,
};
static const unsigned spi1_miso_px7_pins[] = {
TEGRA_PIN_SPI1_MISO_PX7,
};
static const unsigned ulpi_clk_py0_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
};
static const unsigned ulpi_dir_py1_pins[] = {
TEGRA_PIN_ULPI_DIR_PY1,
};
static const unsigned ulpi_nxt_py2_pins[] = {
TEGRA_PIN_ULPI_NXT_PY2,
};
static const unsigned ulpi_stp_py3_pins[] = {
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned sdmmc1_dat3_py4_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
};
static const unsigned sdmmc1_dat2_py5_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PY5,
};
static const unsigned sdmmc1_dat1_py6_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PY6,
};
static const unsigned sdmmc1_dat0_py7_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PY7,
};
static const unsigned sdmmc1_clk_pz0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PZ0,
};
static const unsigned sdmmc1_cmd_pz1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned lcd_sdin_pz2_pins[] = {
TEGRA_PIN_LCD_SDIN_PZ2,
};
static const unsigned lcd_wr_n_pz3_pins[] = {
TEGRA_PIN_LCD_WR_N_PZ3,
};
static const unsigned lcd_sck_pz4_pins[] = {
TEGRA_PIN_LCD_SCK_PZ4,
};
static const unsigned sys_clk_req_pz5_pins[] = {
TEGRA_PIN_SYS_CLK_REQ_PZ5,
};
static const unsigned pwr_i2c_scl_pz6_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PZ6,
};
static const unsigned pwr_i2c_sda_pz7_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned sdmmc4_dat0_paa0_pins[] = {
TEGRA_PIN_SDMMC4_DAT0_PAA0,
};
static const unsigned sdmmc4_dat1_paa1_pins[] = {
TEGRA_PIN_SDMMC4_DAT1_PAA1,
};
static const unsigned sdmmc4_dat2_paa2_pins[] = {
TEGRA_PIN_SDMMC4_DAT2_PAA2,
};
static const unsigned sdmmc4_dat3_paa3_pins[] = {
TEGRA_PIN_SDMMC4_DAT3_PAA3,
};
static const unsigned sdmmc4_dat4_paa4_pins[] = {
TEGRA_PIN_SDMMC4_DAT4_PAA4,
};
static const unsigned sdmmc4_dat5_paa5_pins[] = {
TEGRA_PIN_SDMMC4_DAT5_PAA5,
};
static const unsigned sdmmc4_dat6_paa6_pins[] = {
TEGRA_PIN_SDMMC4_DAT6_PAA6,
};
static const unsigned sdmmc4_dat7_paa7_pins[] = {
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned pbb0_pins[] = {
TEGRA_PIN_PBB0,
};
static const unsigned cam_i2c_scl_pbb1_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PBB1,
};
static const unsigned cam_i2c_sda_pbb2_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PBB2,
};
static const unsigned pbb3_pins[] = {
TEGRA_PIN_PBB3,
};
static const unsigned pbb4_pins[] = {
TEGRA_PIN_PBB4,
};
static const unsigned pbb5_pins[] = {
TEGRA_PIN_PBB5,
};
static const unsigned pbb6_pins[] = {
TEGRA_PIN_PBB6,
};
static const unsigned pbb7_pins[] = {
TEGRA_PIN_PBB7,
};
static const unsigned cam_mclk_pcc0_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned pcc1_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned pcc2_pins[] = {
TEGRA_PIN_PCC2,
};
static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
TEGRA_PIN_SDMMC4_RST_N_PCC3,
};
static const unsigned sdmmc4_clk_pcc4_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
};
static const unsigned clk2_req_pcc5_pins[] = {
TEGRA_PIN_CLK2_REQ_PCC5,
};
static const unsigned pex_l2_rst_n_pcc6_pins[] = {
TEGRA_PIN_PEX_L2_RST_N_PCC6,
};
static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
};
static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
};
static const unsigned pex_l0_rst_n_pdd1_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PDD1,
};
static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
};
static const unsigned pex_wake_n_pdd3_pins[] = {
TEGRA_PIN_PEX_WAKE_N_PDD3,
};
static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
};
static const unsigned pex_l1_rst_n_pdd5_pins[] = {
TEGRA_PIN_PEX_L1_RST_N_PDD5,
};
static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
};
static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
};
static const unsigned clk3_out_pee0_pins[] = {
TEGRA_PIN_CLK3_OUT_PEE0,
};
static const unsigned clk3_req_pee1_pins[] = {
TEGRA_PIN_CLK3_REQ_PEE1,
};
static const unsigned clk1_req_pee2_pins[] = {
TEGRA_PIN_CLK1_REQ_PEE2,
};
static const unsigned hdmi_cec_pee3_pins[] = {
TEGRA_PIN_HDMI_CEC_PEE3,
};
static const unsigned clk_32k_in_pins[] = {
TEGRA_PIN_CLK_32K_IN,
};
static const unsigned core_pwr_req_pins[] = {
TEGRA_PIN_CORE_PWR_REQ,
};
static const unsigned cpu_pwr_req_pins[] = {
TEGRA_PIN_CPU_PWR_REQ,
};
static const unsigned owr_pins[] = {
TEGRA_PIN_OWR,
};
static const unsigned pwr_int_n_pins[] = {
TEGRA_PIN_PWR_INT_N,
};
static const unsigned drive_ao1_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
TEGRA_PIN_KB_ROW7_PR7,
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
TEGRA_PIN_SYS_RESET_N,
};
static const unsigned drive_ao2_pins[] = {
TEGRA_PIN_CLK_32K_OUT_PA0,
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
TEGRA_PIN_KB_COL7_PQ7,
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_KB_ROW11_PS3,
TEGRA_PIN_KB_ROW12_PS4,
TEGRA_PIN_KB_ROW13_PS5,
TEGRA_PIN_KB_ROW14_PS6,
TEGRA_PIN_KB_ROW15_PS7,
TEGRA_PIN_SYS_CLK_REQ_PZ5,
TEGRA_PIN_CLK_32K_IN,
TEGRA_PIN_CORE_PWR_REQ,
TEGRA_PIN_CPU_PWR_REQ,
TEGRA_PIN_PWR_INT_N,
};
static const unsigned drive_at1_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
TEGRA_PIN_GMI_AD9_PH1,
TEGRA_PIN_GMI_AD10_PH2,
TEGRA_PIN_GMI_AD11_PH3,
TEGRA_PIN_GMI_AD12_PH4,
TEGRA_PIN_GMI_AD13_PH5,
TEGRA_PIN_GMI_AD14_PH6,
TEGRA_PIN_GMI_AD15_PH7,
TEGRA_PIN_GMI_IORDY_PI5,
TEGRA_PIN_GMI_CS7_N_PI6,
};
static const unsigned drive_at2_pins[] = {
TEGRA_PIN_GMI_AD0_PG0,
TEGRA_PIN_GMI_AD1_PG1,
TEGRA_PIN_GMI_AD2_PG2,
TEGRA_PIN_GMI_AD3_PG3,
TEGRA_PIN_GMI_AD4_PG4,
TEGRA_PIN_GMI_AD5_PG5,
TEGRA_PIN_GMI_AD6_PG6,
TEGRA_PIN_GMI_AD7_PG7,
TEGRA_PIN_GMI_WR_N_PI0,
TEGRA_PIN_GMI_OE_N_PI1,
TEGRA_PIN_GMI_DQS_PI2,
TEGRA_PIN_GMI_CS6_N_PI3,
TEGRA_PIN_GMI_RST_N_PI4,
TEGRA_PIN_GMI_WAIT_PI7,
TEGRA_PIN_GMI_ADV_N_PK0,
TEGRA_PIN_GMI_CLK_PK1,
TEGRA_PIN_GMI_CS4_N_PK2,
TEGRA_PIN_GMI_CS2_N_PK3,
TEGRA_PIN_GMI_CS3_N_PK4,
};
static const unsigned drive_at3_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
TEGRA_PIN_GMI_CS0_N_PJ0,
};
static const unsigned drive_at4_pins[] = {
TEGRA_PIN_GMI_A17_PB0,
TEGRA_PIN_GMI_A18_PB1,
TEGRA_PIN_GMI_CS1_N_PJ2,
TEGRA_PIN_GMI_A16_PJ7,
TEGRA_PIN_GMI_A19_PK7,
};
static const unsigned drive_at5_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PT5,
TEGRA_PIN_GEN2_I2C_SDA_PT6,
};
static const unsigned drive_cdev1_pins[] = {
TEGRA_PIN_CLK1_OUT_PW4,
TEGRA_PIN_CLK1_REQ_PEE2,
};
static const unsigned drive_cdev2_pins[] = {
TEGRA_PIN_CLK2_OUT_PW5,
TEGRA_PIN_CLK2_REQ_PCC5,
};
static const unsigned drive_cec_pins[] = {
TEGRA_PIN_HDMI_CEC_PEE3,
};
static const unsigned drive_crt_pins[] = {
TEGRA_PIN_CRT_HSYNC_PV6,
TEGRA_PIN_CRT_VSYNC_PV7,
};
static const unsigned drive_csus_pins[] = {
TEGRA_PIN_VI_MCLK_PT1,
};
static const unsigned drive_dap1_pins[] = {
TEGRA_PIN_SPDIF_OUT_PK5,
TEGRA_PIN_SPDIF_IN_PK6,
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned drive_dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned drive_dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned drive_dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned drive_dbg_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PC4,
TEGRA_PIN_GEN1_I2C_SDA_PC5,
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
TEGRA_PIN_JTAG_RTCK_PU7,
TEGRA_PIN_JTAG_TCK,
TEGRA_PIN_JTAG_TDI,
TEGRA_PIN_JTAG_TDO,
TEGRA_PIN_JTAG_TMS,
TEGRA_PIN_JTAG_TRST_N,
TEGRA_PIN_TEST_MODE_EN,
};
static const unsigned drive_ddc_pins[] = {
TEGRA_PIN_DDC_SCL_PV4,
TEGRA_PIN_DDC_SDA_PV5,
};
static const unsigned drive_dev3_pins[] = {
TEGRA_PIN_CLK3_OUT_PEE0,
TEGRA_PIN_CLK3_REQ_PEE1,
};
static const unsigned drive_gma_pins[] = {
TEGRA_PIN_SDMMC4_DAT0_PAA0,
TEGRA_PIN_SDMMC4_DAT1_PAA1,
TEGRA_PIN_SDMMC4_DAT2_PAA2,
TEGRA_PIN_SDMMC4_DAT3_PAA3,
TEGRA_PIN_SDMMC4_RST_N_PCC3,
};
static const unsigned drive_gmb_pins[] = {
TEGRA_PIN_SDMMC4_DAT4_PAA4,
TEGRA_PIN_SDMMC4_DAT5_PAA5,
TEGRA_PIN_SDMMC4_DAT6_PAA6,
TEGRA_PIN_SDMMC4_DAT7_PAA7,
};
static const unsigned drive_gmc_pins[] = {
TEGRA_PIN_SDMMC4_CLK_PCC4,
};
static const unsigned drive_gmd_pins[] = {
TEGRA_PIN_SDMMC4_CMD_PT7,
};
static const unsigned drive_gme_pins[] = {
TEGRA_PIN_PBB0,
TEGRA_PIN_CAM_I2C_SCL_PBB1,
TEGRA_PIN_CAM_I2C_SDA_PBB2,
TEGRA_PIN_PBB3,
TEGRA_PIN_PCC2,
};
static const unsigned drive_gmf_pins[] = {
TEGRA_PIN_PBB4,
TEGRA_PIN_PBB5,
TEGRA_PIN_PBB6,
TEGRA_PIN_PBB7,
};
static const unsigned drive_gmg_pins[] = {
TEGRA_PIN_CAM_MCLK_PCC0,
};
static const unsigned drive_gmh_pins[] = {
TEGRA_PIN_PCC1,
};
static const unsigned drive_gpv_pins[] = {
TEGRA_PIN_PEX_L2_RST_N_PCC6,
TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
TEGRA_PIN_PEX_L0_RST_N_PDD1,
TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
TEGRA_PIN_PEX_WAKE_N_PDD3,
TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
TEGRA_PIN_PEX_L1_RST_N_PDD5,
TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
};
static const unsigned drive_lcd1_pins[] = {
TEGRA_PIN_LCD_PWR1_PC1,
TEGRA_PIN_LCD_PWR2_PC6,
TEGRA_PIN_LCD_CS0_N_PN4,
TEGRA_PIN_LCD_SDOUT_PN5,
TEGRA_PIN_LCD_DC0_PN6,
TEGRA_PIN_LCD_SDIN_PZ2,
TEGRA_PIN_LCD_WR_N_PZ3,
TEGRA_PIN_LCD_SCK_PZ4,
};
static const unsigned drive_lcd2_pins[] = {
TEGRA_PIN_LCD_PWR0_PB2,
TEGRA_PIN_LCD_PCLK_PB3,
TEGRA_PIN_LCD_DC1_PD2,
TEGRA_PIN_LCD_D0_PE0,
TEGRA_PIN_LCD_D1_PE1,
TEGRA_PIN_LCD_D2_PE2,
TEGRA_PIN_LCD_D3_PE3,
TEGRA_PIN_LCD_D4_PE4,
TEGRA_PIN_LCD_D5_PE5,
TEGRA_PIN_LCD_D6_PE6,
TEGRA_PIN_LCD_D7_PE7,
TEGRA_PIN_LCD_D8_PF0,
TEGRA_PIN_LCD_D9_PF1,
TEGRA_PIN_LCD_D10_PF2,
TEGRA_PIN_LCD_D11_PF3,
TEGRA_PIN_LCD_D12_PF4,
TEGRA_PIN_LCD_D13_PF5,
TEGRA_PIN_LCD_D14_PF6,
TEGRA_PIN_LCD_D15_PF7,
TEGRA_PIN_LCD_DE_PJ1,
TEGRA_PIN_LCD_HSYNC_PJ3,
TEGRA_PIN_LCD_VSYNC_PJ4,
TEGRA_PIN_LCD_D16_PM0,
TEGRA_PIN_LCD_D17_PM1,
TEGRA_PIN_LCD_D18_PM2,
TEGRA_PIN_LCD_D19_PM3,
TEGRA_PIN_LCD_D20_PM4,
TEGRA_PIN_LCD_D21_PM5,
TEGRA_PIN_LCD_D22_PM6,
TEGRA_PIN_LCD_D23_PM7,
TEGRA_PIN_HDMI_INT_PN7,
TEGRA_PIN_LCD_CS1_N_PW0,
TEGRA_PIN_LCD_M1_PW1,
};
static const unsigned drive_owr_pins[] = {
TEGRA_PIN_OWR,
};
static const unsigned drive_sdio1_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PY4,
TEGRA_PIN_SDMMC1_DAT2_PY5,
TEGRA_PIN_SDMMC1_DAT1_PY6,
TEGRA_PIN_SDMMC1_DAT0_PY7,
TEGRA_PIN_SDMMC1_CLK_PZ0,
TEGRA_PIN_SDMMC1_CMD_PZ1,
};
static const unsigned drive_sdio2_pins[] = {
TEGRA_PIN_SDMMC3_DAT5_PD0,
TEGRA_PIN_SDMMC3_DAT4_PD1,
TEGRA_PIN_SDMMC3_DAT6_PD3,
TEGRA_PIN_SDMMC3_DAT7_PD4,
};
static const unsigned drive_sdio3_pins[] = {
TEGRA_PIN_SDMMC3_CLK_PA6,
TEGRA_PIN_SDMMC3_CMD_PA7,
TEGRA_PIN_SDMMC3_DAT3_PB4,
TEGRA_PIN_SDMMC3_DAT2_PB5,
TEGRA_PIN_SDMMC3_DAT1_PB6,
TEGRA_PIN_SDMMC3_DAT0_PB7,
};
static const unsigned drive_spi_pins[] = {
TEGRA_PIN_SPI2_CS1_N_PW2,
TEGRA_PIN_SPI2_CS2_N_PW3,
TEGRA_PIN_SPI2_MOSI_PX0,
TEGRA_PIN_SPI2_MISO_PX1,
TEGRA_PIN_SPI2_SCK_PX2,
TEGRA_PIN_SPI2_CS0_N_PX3,
TEGRA_PIN_SPI1_MOSI_PX4,
TEGRA_PIN_SPI1_SCK_PX5,
TEGRA_PIN_SPI1_CS0_N_PX6,
TEGRA_PIN_SPI1_MISO_PX7,
};
static const unsigned drive_uaa_pins[] = {
TEGRA_PIN_ULPI_DATA0_PO1,
TEGRA_PIN_ULPI_DATA1_PO2,
TEGRA_PIN_ULPI_DATA2_PO3,
TEGRA_PIN_ULPI_DATA3_PO4,
};
static const unsigned drive_uab_pins[] = {
TEGRA_PIN_ULPI_DATA7_PO0,
TEGRA_PIN_ULPI_DATA4_PO5,
TEGRA_PIN_ULPI_DATA5_PO6,
TEGRA_PIN_ULPI_DATA6_PO7,
TEGRA_PIN_PV0,
TEGRA_PIN_PV1,
TEGRA_PIN_PV2,
TEGRA_PIN_PV3,
};
static const unsigned drive_uart2_pins[] = {
TEGRA_PIN_UART2_TXD_PC2,
TEGRA_PIN_UART2_RXD_PC3,
TEGRA_PIN_UART2_CTS_N_PJ5,
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned drive_uart3_pins[] = {
TEGRA_PIN_UART3_CTS_N_PA1,
TEGRA_PIN_UART3_RTS_N_PC0,
TEGRA_PIN_UART3_TXD_PW6,
TEGRA_PIN_UART3_RXD_PW7,
};
static const unsigned drive_uda_pins[] = {
TEGRA_PIN_ULPI_CLK_PY0,
TEGRA_PIN_ULPI_DIR_PY1,
TEGRA_PIN_ULPI_NXT_PY2,
TEGRA_PIN_ULPI_STP_PY3,
};
static const unsigned drive_vi1_pins[] = {
TEGRA_PIN_VI_D1_PD5,
TEGRA_PIN_VI_VSYNC_PD6,
TEGRA_PIN_VI_HSYNC_PD7,
TEGRA_PIN_VI_D2_PL0,
TEGRA_PIN_VI_D3_PL1,
TEGRA_PIN_VI_D4_PL2,
TEGRA_PIN_VI_D5_PL3,
TEGRA_PIN_VI_D6_PL4,
TEGRA_PIN_VI_D7_PL5,
TEGRA_PIN_VI_D8_PL6,
TEGRA_PIN_VI_D9_PL7,
TEGRA_PIN_VI_PCLK_PT0,
TEGRA_PIN_VI_D10_PT2,
TEGRA_PIN_VI_D11_PT3,
TEGRA_PIN_VI_D0_PT4,
};
enum tegra_mux {
TEGRA_MUX_BLINK,
TEGRA_MUX_CEC,
TEGRA_MUX_CLK_12M_OUT,
TEGRA_MUX_CLK_32K_IN,
TEGRA_MUX_CORE_PWR_REQ,
TEGRA_MUX_CPU_PWR_REQ,
TEGRA_MUX_CRT,
TEGRA_MUX_DAP,
TEGRA_MUX_DDR,
TEGRA_MUX_DEV3,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DTV,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HDCP,
TEGRA_MUX_HDMI,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_INVALID,
TEGRA_MUX_KBC,
TEGRA_MUX_MIO,
TEGRA_MUX_NAND,
TEGRA_MUX_NAND_ALT,
TEGRA_MUX_OWR,
TEGRA_MUX_PCIE,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_PWR_INT_N,
TEGRA_MUX_RSVD1,
TEGRA_MUX_RSVD2,
TEGRA_MUX_RSVD3,
TEGRA_MUX_RSVD4,
TEGRA_MUX_RTCK,
TEGRA_MUX_SATA,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_SDMMC2,
TEGRA_MUX_SDMMC3,
TEGRA_MUX_SDMMC4,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI2_ALT,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYSCLK,
TEGRA_MUX_TEST,
TEGRA_MUX_TRACE,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_UARTE,
TEGRA_MUX_ULPI,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_VI,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT2,
TEGRA_MUX_VI_ALT3,
};
#define FUNCTION(fname) #fname
static const char * const tegra30_functions[] = {
FUNCTION(blink),
FUNCTION(cec),
FUNCTION(clk_12m_out),
FUNCTION(clk_32k_in),
FUNCTION(core_pwr_req),
FUNCTION(cpu_pwr_req),
FUNCTION(crt),
FUNCTION(dap),
FUNCTION(ddr),
FUNCTION(dev3),
FUNCTION(displaya),
FUNCTION(displayb),
FUNCTION(dtv),
FUNCTION(extperiph1),
FUNCTION(extperiph2),
FUNCTION(extperiph3),
FUNCTION(gmi),
FUNCTION(gmi_alt),
FUNCTION(hda),
FUNCTION(hdcp),
FUNCTION(hdmi),
FUNCTION(hsi),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2c4),
FUNCTION(i2cpwr),
FUNCTION(i2s0),
FUNCTION(i2s1),
FUNCTION(i2s2),
FUNCTION(i2s3),
FUNCTION(i2s4),
FUNCTION(invalid),
FUNCTION(kbc),
FUNCTION(mio),
FUNCTION(nand),
FUNCTION(nand_alt),
FUNCTION(owr),
FUNCTION(pcie),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(pwr_int_n),
FUNCTION(rsvd1),
FUNCTION(rsvd2),
FUNCTION(rsvd3),
FUNCTION(rsvd4),
FUNCTION(rtck),
FUNCTION(sata),
FUNCTION(sdmmc1),
FUNCTION(sdmmc2),
FUNCTION(sdmmc3),
FUNCTION(sdmmc4),
FUNCTION(spdif),
FUNCTION(spi1),
FUNCTION(spi2),
FUNCTION(spi2_alt),
FUNCTION(spi3),
FUNCTION(spi4),
FUNCTION(spi5),
FUNCTION(spi6),
FUNCTION(sysclk),
FUNCTION(test),
FUNCTION(trace),
FUNCTION(uarta),
FUNCTION(uartb),
FUNCTION(uartc),
FUNCTION(uartd),
FUNCTION(uarte),
FUNCTION(ulpi),
FUNCTION(vgp1),
FUNCTION(vgp2),
FUNCTION(vgp3),
FUNCTION(vgp4),
FUNCTION(vgp5),
FUNCTION(vgp6),
FUNCTION(vi),
FUNCTION(vi_alt1),
FUNCTION(vi_alt2),
FUNCTION(vi_alt3),
};
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
#define PINGROUP_BIT_Y(b) (b)
#define PINGROUP_BIT_N(b) (-1)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
.mux_reg = PINGROUP_REG(r), \
.mux_bank = 1, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG(r), \
.pupd_bank = 1, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG(r), \
.tri_bank = 1, \
.tri_bit = 4, \
.einput_bit = 5, \
.odrain_bit = PINGROUP_BIT_##od(6), \
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = -1, \
.drv_reg = -1, \
.parked_bitmask = 0, \
}
#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
slwf_b, slwf_w) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \
.npins = ARRAY_SIZE(drive_##pg_name##_pins), \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w, \
.drvtype_bit = -1, \
.parked_bitmask = 0, \
}
static const struct tegra_pingroup tegra30_groups[] = {
/* pg_name, f0, f1, f2, f3, r, od, ior */
PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N),
PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N),
PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N),
PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N),
PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N),
PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N),
PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N),
PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N),
PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N),
PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N),
PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N),
PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N),
PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N),
PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N),
PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N),
PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N),
PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N),
PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N),
PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N),
PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N),
PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N),
PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N),
PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N),
PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N),
PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N),
PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N),
PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N),
PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N),
PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N),
PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N),
PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N),
PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N),
PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N),
PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N),
PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N),
PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N),
PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N),
PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N),
PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N),
PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N),
PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N),
PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N),
PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N),
PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N),
PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N),
PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N),
PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N),
PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N),
PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N),
PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N),
PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N),
PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N),
PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N),
PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N),
PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N),
PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N),
PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N),
PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N),
PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N),
PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N),
PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N),
PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N),
PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N),
PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N),
PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N),
PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N),
PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N),
PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N),
PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N),
PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N),
PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N),
PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N),
PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N),
PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N),
PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N),
PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N),
PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N),
PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N),
PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N),
PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N),
PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N),
PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y),
PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y),
PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N),
PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N),
PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N),
PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N),
PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N),
PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N),
PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N),
PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N),
PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N),
PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N),
PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N),
PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N),
PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N),
PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N),
PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N),
PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N),
PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N),
PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N),
PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N),
PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N),
PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N),
PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N),
PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N),
PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N),
PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N),
PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N),
PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N),
PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N),
PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N),
PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N),
PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N),
PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N),
PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N),
PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N),
PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N),
PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N),
PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N),
PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N),
PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N),
PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N),
PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N),
PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N),
PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N),
PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N),
PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N),
PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N),
PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N),
PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N),
PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N),
PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N),
PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N),
PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N),
PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N),
PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N),
PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N),
PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N),
PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y),
PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y),
PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y),
PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y),
PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y),
PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N),
PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N),
PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y),
PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N),
PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N),
PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N),
PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N),
PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N),
PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N),
PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N),
PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N),
PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N),
PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N),
PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N),
PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N),
PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N),
PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N),
PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N),
PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N),
PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N),
PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N),
PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N),
PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N),
PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N),
PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N),
PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N),
PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N),
PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N),
PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N),
PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N),
PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N),
PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N),
PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N),
PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N),
PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N),
PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N),
PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N),
PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N),
PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N),
PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N),
PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N),
PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N),
PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N),
PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N),
PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N),
PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N),
PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N),
PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N),
PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N),
PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N),
PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y),
PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y),
PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y),
PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y),
PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y),
PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y),
PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y),
PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y),
PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N),
PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N),
PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N),
PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N),
PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N),
PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N),
PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N),
PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N),
PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N),
PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N),
PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N),
PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y),
PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y),
PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N),
PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N),
PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N),
PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N),
PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N),
PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N),
PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N),
PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N),
PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N),
PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N),
/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(at1, 0x870, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
DRV_PINGROUP(at2, 0x874, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
DRV_PINGROUP(at3, 0x878, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(crt, 0x8f8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(csus, 0x88c, -1, -1, -1, 12, 5, 19, 5, 24, 4, 28, 4),
DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(gma, 0x900, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
DRV_PINGROUP(gmb, 0x904, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
DRV_PINGROUP(gmc, 0x908, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
DRV_PINGROUP(gmd, 0x90c, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(lcd1, 0x8a4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(lcd2, 0x8a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
DRV_PINGROUP(sdio2, 0x8ac, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
DRV_PINGROUP(vi1, 0x8c8, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
};
static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra30-gpio",
.pins = tegra30_pins,
.npins = ARRAY_SIZE(tegra30_pins),
.functions = tegra30_functions,
.nfunctions = ARRAY_SIZE(tegra30_functions),
.groups = tegra30_groups,
.ngroups = ARRAY_SIZE(tegra30_groups),
.hsm_in_mux = false,
.schmitt_in_mux = false,
.drvtype_in_mux = false,
};
static int tegra30_pinctrl_probe(struct platform_device *pdev)
{
return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
}
static const struct of_device_id tegra30_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra30-pinmux", },
{ },
};
static struct platform_driver tegra30_pinctrl_driver = {
.driver = {
.name = "tegra30-pinctrl",
.of_match_table = tegra30_pinctrl_of_match,
},
.probe = tegra30_pinctrl_probe,
};
static int __init tegra30_pinctrl_init(void)
{
return platform_driver_register(&tegra30_pinctrl_driver);
}
arch_initcall(tegra30_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra30.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Pinctrl data for the NVIDIA Tegra234 pinmux
*
* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/* Define unique ID for each pins */
enum {
TEGRA_PIN_DAP6_SCLK_PA0,
TEGRA_PIN_DAP6_DOUT_PA1,
TEGRA_PIN_DAP6_DIN_PA2,
TEGRA_PIN_DAP6_FS_PA3,
TEGRA_PIN_DAP4_SCLK_PA4,
TEGRA_PIN_DAP4_DOUT_PA5,
TEGRA_PIN_DAP4_DIN_PA6,
TEGRA_PIN_DAP4_FS_PA7,
TEGRA_PIN_SOC_GPIO08_PB0,
TEGRA_PIN_QSPI0_SCK_PC0,
TEGRA_PIN_QSPI0_CS_N_PC1,
TEGRA_PIN_QSPI0_IO0_PC2,
TEGRA_PIN_QSPI0_IO1_PC3,
TEGRA_PIN_QSPI0_IO2_PC4,
TEGRA_PIN_QSPI0_IO3_PC5,
TEGRA_PIN_QSPI1_SCK_PC6,
TEGRA_PIN_QSPI1_CS_N_PC7,
TEGRA_PIN_QSPI1_IO0_PD0,
TEGRA_PIN_QSPI1_IO1_PD1,
TEGRA_PIN_QSPI1_IO2_PD2,
TEGRA_PIN_QSPI1_IO3_PD3,
TEGRA_PIN_EQOS_TXC_PE0,
TEGRA_PIN_EQOS_TD0_PE1,
TEGRA_PIN_EQOS_TD1_PE2,
TEGRA_PIN_EQOS_TD2_PE3,
TEGRA_PIN_EQOS_TD3_PE4,
TEGRA_PIN_EQOS_TX_CTL_PE5,
TEGRA_PIN_EQOS_RD0_PE6,
TEGRA_PIN_EQOS_RD1_PE7,
TEGRA_PIN_EQOS_RD2_PF0,
TEGRA_PIN_EQOS_RD3_PF1,
TEGRA_PIN_EQOS_RX_CTL_PF2,
TEGRA_PIN_EQOS_RXC_PF3,
TEGRA_PIN_EQOS_SMA_MDIO_PF4,
TEGRA_PIN_EQOS_SMA_MDC_PF5,
TEGRA_PIN_SOC_GPIO13_PG0,
TEGRA_PIN_SOC_GPIO14_PG1,
TEGRA_PIN_SOC_GPIO15_PG2,
TEGRA_PIN_SOC_GPIO16_PG3,
TEGRA_PIN_SOC_GPIO17_PG4,
TEGRA_PIN_SOC_GPIO18_PG5,
TEGRA_PIN_SOC_GPIO19_PG6,
TEGRA_PIN_SOC_GPIO20_PG7,
TEGRA_PIN_SOC_GPIO21_PH0,
TEGRA_PIN_SOC_GPIO22_PH1,
TEGRA_PIN_SOC_GPIO06_PH2,
TEGRA_PIN_UART4_TX_PH3,
TEGRA_PIN_UART4_RX_PH4,
TEGRA_PIN_UART4_RTS_PH5,
TEGRA_PIN_UART4_CTS_PH6,
TEGRA_PIN_SOC_GPIO41_PH7,
TEGRA_PIN_SOC_GPIO42_PI0,
TEGRA_PIN_SOC_GPIO43_PI1,
TEGRA_PIN_SOC_GPIO44_PI2,
TEGRA_PIN_GEN1_I2C_SCL_PI3,
TEGRA_PIN_GEN1_I2C_SDA_PI4,
TEGRA_PIN_CPU_PWR_REQ_PI5,
TEGRA_PIN_SOC_GPIO07_PI6,
TEGRA_PIN_SDMMC1_CLK_PJ0,
TEGRA_PIN_SDMMC1_CMD_PJ1,
TEGRA_PIN_SDMMC1_DAT0_PJ2,
TEGRA_PIN_SDMMC1_DAT1_PJ3,
TEGRA_PIN_SDMMC1_DAT2_PJ4,
TEGRA_PIN_SDMMC1_DAT3_PJ5,
TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
TEGRA_PIN_PEX_L0_RST_N_PK1,
TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
TEGRA_PIN_PEX_L1_RST_N_PK3,
TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
TEGRA_PIN_PEX_L2_RST_N_PK5,
TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
TEGRA_PIN_PEX_L3_RST_N_PK7,
TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
TEGRA_PIN_PEX_L4_RST_N_PL1,
TEGRA_PIN_PEX_WAKE_N_PL2,
TEGRA_PIN_SOC_GPIO34_PL3,
TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
TEGRA_PIN_SOC_GPIO55_PM4,
TEGRA_PIN_SOC_GPIO36_PM5,
TEGRA_PIN_SOC_GPIO53_PM6,
TEGRA_PIN_SOC_GPIO38_PM7,
TEGRA_PIN_DP_AUX_CH3_N_PN0,
TEGRA_PIN_SOC_GPIO39_PN1,
TEGRA_PIN_SOC_GPIO40_PN2,
TEGRA_PIN_DP_AUX_CH1_P_PN3,
TEGRA_PIN_DP_AUX_CH1_N_PN4,
TEGRA_PIN_DP_AUX_CH2_P_PN5,
TEGRA_PIN_DP_AUX_CH2_N_PN6,
TEGRA_PIN_DP_AUX_CH3_P_PN7,
TEGRA_PIN_EXTPERIPH1_CLK_PP0,
TEGRA_PIN_EXTPERIPH2_CLK_PP1,
TEGRA_PIN_CAM_I2C_SCL_PP2,
TEGRA_PIN_CAM_I2C_SDA_PP3,
TEGRA_PIN_SOC_GPIO23_PP4,
TEGRA_PIN_SOC_GPIO24_PP5,
TEGRA_PIN_SOC_GPIO25_PP6,
TEGRA_PIN_PWR_I2C_SCL_PP7,
TEGRA_PIN_PWR_I2C_SDA_PQ0,
TEGRA_PIN_SOC_GPIO28_PQ1,
TEGRA_PIN_SOC_GPIO29_PQ2,
TEGRA_PIN_SOC_GPIO30_PQ3,
TEGRA_PIN_SOC_GPIO31_PQ4,
TEGRA_PIN_SOC_GPIO32_PQ5,
TEGRA_PIN_SOC_GPIO33_PQ6,
TEGRA_PIN_SOC_GPIO35_PQ7,
TEGRA_PIN_SOC_GPIO37_PR0,
TEGRA_PIN_SOC_GPIO56_PR1,
TEGRA_PIN_UART1_TX_PR2,
TEGRA_PIN_UART1_RX_PR3,
TEGRA_PIN_UART1_RTS_PR4,
TEGRA_PIN_UART1_CTS_PR5,
TEGRA_PIN_GPU_PWR_REQ_PX0,
TEGRA_PIN_CV_PWR_REQ_PX1,
TEGRA_PIN_GP_PWM2_PX2,
TEGRA_PIN_GP_PWM3_PX3,
TEGRA_PIN_UART2_TX_PX4,
TEGRA_PIN_UART2_RX_PX5,
TEGRA_PIN_UART2_RTS_PX6,
TEGRA_PIN_UART2_CTS_PX7,
TEGRA_PIN_SPI3_SCK_PY0,
TEGRA_PIN_SPI3_MISO_PY1,
TEGRA_PIN_SPI3_MOSI_PY2,
TEGRA_PIN_SPI3_CS0_PY3,
TEGRA_PIN_SPI3_CS1_PY4,
TEGRA_PIN_UART5_TX_PY5,
TEGRA_PIN_UART5_RX_PY6,
TEGRA_PIN_UART5_RTS_PY7,
TEGRA_PIN_UART5_CTS_PZ0,
TEGRA_PIN_USB_VBUS_EN0_PZ1,
TEGRA_PIN_USB_VBUS_EN1_PZ2,
TEGRA_PIN_SPI1_SCK_PZ3,
TEGRA_PIN_SPI1_MISO_PZ4,
TEGRA_PIN_SPI1_MOSI_PZ5,
TEGRA_PIN_SPI1_CS0_PZ6,
TEGRA_PIN_SPI1_CS1_PZ7,
TEGRA_PIN_SPI5_SCK_PAC0,
TEGRA_PIN_SPI5_MISO_PAC1,
TEGRA_PIN_SPI5_MOSI_PAC2,
TEGRA_PIN_SPI5_CS0_PAC3,
TEGRA_PIN_SOC_GPIO57_PAC4,
TEGRA_PIN_SOC_GPIO58_PAC5,
TEGRA_PIN_SOC_GPIO59_PAC6,
TEGRA_PIN_SOC_GPIO60_PAC7,
TEGRA_PIN_SOC_GPIO45_PAD0,
TEGRA_PIN_SOC_GPIO46_PAD1,
TEGRA_PIN_SOC_GPIO47_PAD2,
TEGRA_PIN_SOC_GPIO48_PAD3,
TEGRA_PIN_UFS0_REF_CLK_PAE0,
TEGRA_PIN_UFS0_RST_N_PAE1,
TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0,
TEGRA_PIN_PEX_L5_RST_N_PAF1,
TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2,
TEGRA_PIN_PEX_L6_RST_N_PAF3,
TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0,
TEGRA_PIN_PEX_L7_RST_N_PAG1,
TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2,
TEGRA_PIN_PEX_L8_RST_N_PAG3,
TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4,
TEGRA_PIN_PEX_L9_RST_N_PAG5,
TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6,
TEGRA_PIN_PEX_L10_RST_N_PAG7,
TEGRA_PIN_EQOS_COMP,
TEGRA_PIN_QSPI_COMP,
TEGRA_PIN_SDMMC1_COMP,
};
enum {
TEGRA_PIN_CAN0_DOUT_PAA0,
TEGRA_PIN_CAN0_DIN_PAA1,
TEGRA_PIN_CAN1_DOUT_PAA2,
TEGRA_PIN_CAN1_DIN_PAA3,
TEGRA_PIN_CAN0_STB_PAA4,
TEGRA_PIN_CAN0_EN_PAA5,
TEGRA_PIN_SOC_GPIO49_PAA6,
TEGRA_PIN_CAN0_ERR_PAA7,
TEGRA_PIN_CAN1_STB_PBB0,
TEGRA_PIN_CAN1_EN_PBB1,
TEGRA_PIN_SOC_GPIO50_PBB2,
TEGRA_PIN_CAN1_ERR_PBB3,
TEGRA_PIN_SPI2_SCK_PCC0,
TEGRA_PIN_SPI2_MISO_PCC1,
TEGRA_PIN_SPI2_MOSI_PCC2,
TEGRA_PIN_SPI2_CS0_PCC3,
TEGRA_PIN_TOUCH_CLK_PCC4,
TEGRA_PIN_UART3_TX_PCC5,
TEGRA_PIN_UART3_RX_PCC6,
TEGRA_PIN_GEN2_I2C_SCL_PCC7,
TEGRA_PIN_GEN2_I2C_SDA_PDD0,
TEGRA_PIN_GEN8_I2C_SCL_PDD1,
TEGRA_PIN_GEN8_I2C_SDA_PDD2,
TEGRA_PIN_SCE_ERROR_PEE0,
TEGRA_PIN_VCOMP_ALERT_PEE1,
TEGRA_PIN_AO_RETENTION_N_PEE2,
TEGRA_PIN_BATT_OC_PEE3,
TEGRA_PIN_POWER_ON_PEE4,
TEGRA_PIN_SOC_GPIO26_PEE5,
TEGRA_PIN_SOC_GPIO27_PEE6,
TEGRA_PIN_BOOTV_CTL_N_PEE7,
TEGRA_PIN_HDMI_CEC_PGG0,
};
/* Table for pin descriptor */
static const struct pinctrl_pin_desc tegra234_pins[] = {
PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"),
PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PB0, "SOC_GPIO08_PB0"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"),
PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"),
PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"),
PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PG0, "SOC_GPIO13_PG0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PG1, "SOC_GPIO14_PG1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PG2, "SOC_GPIO15_PG2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PG3, "SOC_GPIO16_PG3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PG4, "SOC_GPIO17_PG4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PG5, "SOC_GPIO18_PG5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PG6, "SOC_GPIO19_PG6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PG7, "SOC_GPIO20_PG7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PH0, "SOC_GPIO21_PH0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PH1, "SOC_GPIO22_PH1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PH2, "SOC_GPIO06_PH2"),
PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"),
PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"),
PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"),
PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PH7, "SOC_GPIO41_PH7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PI0, "SOC_GPIO42_PI0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PI1, "SOC_GPIO43_PI1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PI2, "SOC_GPIO44_PI2"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PI5, "CPU_PWR_REQ_PI5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PI6, "SOC_GPIO07_PI6"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"),
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"),
PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"),
PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"),
PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"),
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PL3, "SOC_GPIO34_PL3"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PM4, "SOC_GPIO55_PM4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PM5, "SOC_GPIO36_PM5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PM6, "SOC_GPIO53_PM6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PM7, "SOC_GPIO38_PM7"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_N_PN0, "DP_AUX_CH3_N_PN0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO39_PN1, "SOC_GPIO39_PN1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PN2, "SOC_GPIO40_PN2"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_P_PN3, "DP_AUX_CH1_P_PN3"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_N_PN4, "DP_AUX_CH1_N_PN4"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_P_PN5, "DP_AUX_CH2_P_PN5"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_N_PN6, "DP_AUX_CH2_N_PN6"),
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_P_PN7, "DP_AUX_CH3_P_PN7"),
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"),
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PP4, "SOC_GPIO23_PP4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PP5, "SOC_GPIO24_PP5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PP6, "SOC_GPIO25_PP6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PP7, "PWR_I2C_SCL_PP7"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PQ0, "PWR_I2C_SDA_PQ0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PQ1, "SOC_GPIO28_PQ1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PQ2, "SOC_GPIO29_PQ2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PQ3, "SOC_GPIO30_PQ3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PQ4, "SOC_GPIO31_PQ4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PQ5, "SOC_GPIO32_PQ5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PQ6, "SOC_GPIO33_PQ6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PQ7, "SOC_GPIO35_PQ7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PR0, "SOC_GPIO37_PR0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PR1, "SOC_GPIO56_PR1"),
PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"),
PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"),
PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"),
PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"),
PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"),
PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"),
PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"),
PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"),
PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"),
PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"),
PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"),
PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"),
PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"),
PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"),
PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"),
PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"),
PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"),
PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"),
PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"),
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PAC0, "SPI5_SCK_PAC0"),
PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PAC1, "SPI5_MISO_PAC1"),
PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PAC2, "SPI5_MOSI_PAC2"),
PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PAC3, "SPI5_CS0_PAC3"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PAC4, "SOC_GPIO57_PAC4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PAC5, "SOC_GPIO58_PAC5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PAC6, "SOC_GPIO59_PAC6"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PAC7, "SOC_GPIO60_PAC7"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PAD0, "SOC_GPIO45_PAD0"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PAD1, "SOC_GPIO46_PAD1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PAD2, "SOC_GPIO47_PAD2"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PAD3, "SOC_GPIO48_PAD3"),
PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PAE0, "UFS0_REF_CLK_PAE0"),
PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PAE1, "UFS0_RST_N_PAE1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0, "PEX_L5_CLKREQ_N_PAF0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PAF1, "PEX_L5_RST_N_PAF1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2, "PEX_L6_CLKREQ_N_PAF2"),
PINCTRL_PIN(TEGRA_PIN_PEX_L6_RST_N_PAF3, "PEX_L6_RST_N_PAF3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0, "PEX_L7_CLKREQ_N_PAG0"),
PINCTRL_PIN(TEGRA_PIN_PEX_L7_RST_N_PAG1, "PEX_L7_RST_N_PAG1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2, "PEX_L8_CLKREQ_N_PAG2"),
PINCTRL_PIN(TEGRA_PIN_PEX_L8_RST_N_PAG3, "PEX_L8_RST_N_PAG3"),
PINCTRL_PIN(TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4, "PEX_L9_CLKREQ_N_PAG4"),
PINCTRL_PIN(TEGRA_PIN_PEX_L9_RST_N_PAG5, "PEX_L9_RST_N_PAG5"),
PINCTRL_PIN(TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6, "PEX_L10_CLKREQ_N_PAG6"),
PINCTRL_PIN(TEGRA_PIN_PEX_L10_RST_N_PAG7, "PEX_L10_RST_N_PAG7"),
PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
};
static const unsigned int dap6_sclk_pa0_pins[] = {
TEGRA_PIN_DAP6_SCLK_PA0,
};
static const unsigned int dap6_dout_pa1_pins[] = {
TEGRA_PIN_DAP6_DOUT_PA1,
};
static const unsigned int dap6_din_pa2_pins[] = {
TEGRA_PIN_DAP6_DIN_PA2,
};
static const unsigned int dap6_fs_pa3_pins[] = {
TEGRA_PIN_DAP6_FS_PA3,
};
static const unsigned int dap4_sclk_pa4_pins[] = {
TEGRA_PIN_DAP4_SCLK_PA4,
};
static const unsigned int dap4_dout_pa5_pins[] = {
TEGRA_PIN_DAP4_DOUT_PA5,
};
static const unsigned int dap4_din_pa6_pins[] = {
TEGRA_PIN_DAP4_DIN_PA6,
};
static const unsigned int dap4_fs_pa7_pins[] = {
TEGRA_PIN_DAP4_FS_PA7,
};
static const unsigned int soc_gpio08_pb0_pins[] = {
TEGRA_PIN_SOC_GPIO08_PB0,
};
static const unsigned int qspi0_sck_pc0_pins[] = {
TEGRA_PIN_QSPI0_SCK_PC0,
};
static const unsigned int qspi0_cs_n_pc1_pins[] = {
TEGRA_PIN_QSPI0_CS_N_PC1,
};
static const unsigned int qspi0_io0_pc2_pins[] = {
TEGRA_PIN_QSPI0_IO0_PC2,
};
static const unsigned int qspi0_io1_pc3_pins[] = {
TEGRA_PIN_QSPI0_IO1_PC3,
};
static const unsigned int qspi0_io2_pc4_pins[] = {
TEGRA_PIN_QSPI0_IO2_PC4,
};
static const unsigned int qspi0_io3_pc5_pins[] = {
TEGRA_PIN_QSPI0_IO3_PC5,
};
static const unsigned int qspi1_sck_pc6_pins[] = {
TEGRA_PIN_QSPI1_SCK_PC6,
};
static const unsigned int qspi1_cs_n_pc7_pins[] = {
TEGRA_PIN_QSPI1_CS_N_PC7,
};
static const unsigned int qspi1_io0_pd0_pins[] = {
TEGRA_PIN_QSPI1_IO0_PD0,
};
static const unsigned int qspi1_io1_pd1_pins[] = {
TEGRA_PIN_QSPI1_IO1_PD1,
};
static const unsigned int qspi1_io2_pd2_pins[] = {
TEGRA_PIN_QSPI1_IO2_PD2,
};
static const unsigned int qspi1_io3_pd3_pins[] = {
TEGRA_PIN_QSPI1_IO3_PD3,
};
static const unsigned int eqos_txc_pe0_pins[] = {
TEGRA_PIN_EQOS_TXC_PE0,
};
static const unsigned int eqos_td0_pe1_pins[] = {
TEGRA_PIN_EQOS_TD0_PE1,
};
static const unsigned int eqos_td1_pe2_pins[] = {
TEGRA_PIN_EQOS_TD1_PE2,
};
static const unsigned int eqos_td2_pe3_pins[] = {
TEGRA_PIN_EQOS_TD2_PE3,
};
static const unsigned int eqos_td3_pe4_pins[] = {
TEGRA_PIN_EQOS_TD3_PE4,
};
static const unsigned int eqos_tx_ctl_pe5_pins[] = {
TEGRA_PIN_EQOS_TX_CTL_PE5,
};
static const unsigned int eqos_rd0_pe6_pins[] = {
TEGRA_PIN_EQOS_RD0_PE6,
};
static const unsigned int eqos_rd1_pe7_pins[] = {
TEGRA_PIN_EQOS_RD1_PE7,
};
static const unsigned int eqos_rd2_pf0_pins[] = {
TEGRA_PIN_EQOS_RD2_PF0,
};
static const unsigned int eqos_rd3_pf1_pins[] = {
TEGRA_PIN_EQOS_RD3_PF1,
};
static const unsigned int eqos_rx_ctl_pf2_pins[] = {
TEGRA_PIN_EQOS_RX_CTL_PF2,
};
static const unsigned int eqos_rxc_pf3_pins[] = {
TEGRA_PIN_EQOS_RXC_PF3,
};
static const unsigned int eqos_sma_mdio_pf4_pins[] = {
TEGRA_PIN_EQOS_SMA_MDIO_PF4,
};
static const unsigned int eqos_sma_mdc_pf5_pins[] = {
TEGRA_PIN_EQOS_SMA_MDC_PF5,
};
static const unsigned int soc_gpio13_pg0_pins[] = {
TEGRA_PIN_SOC_GPIO13_PG0,
};
static const unsigned int soc_gpio14_pg1_pins[] = {
TEGRA_PIN_SOC_GPIO14_PG1,
};
static const unsigned int soc_gpio15_pg2_pins[] = {
TEGRA_PIN_SOC_GPIO15_PG2,
};
static const unsigned int soc_gpio16_pg3_pins[] = {
TEGRA_PIN_SOC_GPIO16_PG3,
};
static const unsigned int soc_gpio17_pg4_pins[] = {
TEGRA_PIN_SOC_GPIO17_PG4,
};
static const unsigned int soc_gpio18_pg5_pins[] = {
TEGRA_PIN_SOC_GPIO18_PG5,
};
static const unsigned int soc_gpio19_pg6_pins[] = {
TEGRA_PIN_SOC_GPIO19_PG6,
};
static const unsigned int soc_gpio20_pg7_pins[] = {
TEGRA_PIN_SOC_GPIO20_PG7,
};
static const unsigned int soc_gpio21_ph0_pins[] = {
TEGRA_PIN_SOC_GPIO21_PH0,
};
static const unsigned int soc_gpio22_ph1_pins[] = {
TEGRA_PIN_SOC_GPIO22_PH1,
};
static const unsigned int soc_gpio06_ph2_pins[] = {
TEGRA_PIN_SOC_GPIO06_PH2,
};
static const unsigned int uart4_tx_ph3_pins[] = {
TEGRA_PIN_UART4_TX_PH3,
};
static const unsigned int uart4_rx_ph4_pins[] = {
TEGRA_PIN_UART4_RX_PH4,
};
static const unsigned int uart4_rts_ph5_pins[] = {
TEGRA_PIN_UART4_RTS_PH5,
};
static const unsigned int uart4_cts_ph6_pins[] = {
TEGRA_PIN_UART4_CTS_PH6,
};
static const unsigned int soc_gpio41_ph7_pins[] = {
TEGRA_PIN_SOC_GPIO41_PH7,
};
static const unsigned int soc_gpio42_pi0_pins[] = {
TEGRA_PIN_SOC_GPIO42_PI0,
};
static const unsigned int soc_gpio43_pi1_pins[] = {
TEGRA_PIN_SOC_GPIO43_PI1,
};
static const unsigned int soc_gpio44_pi2_pins[] = {
TEGRA_PIN_SOC_GPIO44_PI2,
};
static const unsigned int gen1_i2c_scl_pi3_pins[] = {
TEGRA_PIN_GEN1_I2C_SCL_PI3,
};
static const unsigned int gen1_i2c_sda_pi4_pins[] = {
TEGRA_PIN_GEN1_I2C_SDA_PI4,
};
static const unsigned int cpu_pwr_req_pi5_pins[] = {
TEGRA_PIN_CPU_PWR_REQ_PI5,
};
static const unsigned int soc_gpio07_pi6_pins[] = {
TEGRA_PIN_SOC_GPIO07_PI6,
};
static const unsigned int sdmmc1_clk_pj0_pins[] = {
TEGRA_PIN_SDMMC1_CLK_PJ0,
};
static const unsigned int sdmmc1_cmd_pj1_pins[] = {
TEGRA_PIN_SDMMC1_CMD_PJ1,
};
static const unsigned int sdmmc1_dat0_pj2_pins[] = {
TEGRA_PIN_SDMMC1_DAT0_PJ2,
};
static const unsigned int sdmmc1_dat1_pj3_pins[] = {
TEGRA_PIN_SDMMC1_DAT1_PJ3,
};
static const unsigned int sdmmc1_dat2_pj4_pins[] = {
TEGRA_PIN_SDMMC1_DAT2_PJ4,
};
static const unsigned int sdmmc1_dat3_pj5_pins[] = {
TEGRA_PIN_SDMMC1_DAT3_PJ5,
};
static const unsigned int pex_l0_clkreq_n_pk0_pins[] = {
TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
};
static const unsigned int pex_l0_rst_n_pk1_pins[] = {
TEGRA_PIN_PEX_L0_RST_N_PK1,
};
static const unsigned int pex_l1_clkreq_n_pk2_pins[] = {
TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
};
static const unsigned int pex_l1_rst_n_pk3_pins[] = {
TEGRA_PIN_PEX_L1_RST_N_PK3,
};
static const unsigned int pex_l2_clkreq_n_pk4_pins[] = {
TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
};
static const unsigned int pex_l2_rst_n_pk5_pins[] = {
TEGRA_PIN_PEX_L2_RST_N_PK5,
};
static const unsigned int pex_l3_clkreq_n_pk6_pins[] = {
TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,
};
static const unsigned int pex_l3_rst_n_pk7_pins[] = {
TEGRA_PIN_PEX_L3_RST_N_PK7,
};
static const unsigned int pex_l4_clkreq_n_pl0_pins[] = {
TEGRA_PIN_PEX_L4_CLKREQ_N_PL0,
};
static const unsigned int pex_l4_rst_n_pl1_pins[] = {
TEGRA_PIN_PEX_L4_RST_N_PL1,
};
static const unsigned int pex_wake_n_pl2_pins[] = {
TEGRA_PIN_PEX_WAKE_N_PL2,
};
static const unsigned int soc_gpio34_pl3_pins[] = {
TEGRA_PIN_SOC_GPIO34_PL3,
};
static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = {
TEGRA_PIN_DP_AUX_CH0_HPD_PM0,
};
static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = {
TEGRA_PIN_DP_AUX_CH1_HPD_PM1,
};
static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = {
TEGRA_PIN_DP_AUX_CH2_HPD_PM2,
};
static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = {
TEGRA_PIN_DP_AUX_CH3_HPD_PM3,
};
static const unsigned int soc_gpio55_pm4_pins[] = {
TEGRA_PIN_SOC_GPIO55_PM4,
};
static const unsigned int soc_gpio36_pm5_pins[] = {
TEGRA_PIN_SOC_GPIO36_PM5,
};
static const unsigned int soc_gpio53_pm6_pins[] = {
TEGRA_PIN_SOC_GPIO53_PM6,
};
static const unsigned int soc_gpio38_pm7_pins[] = {
TEGRA_PIN_SOC_GPIO38_PM7,
};
static const unsigned int dp_aux_ch3_n_pn0_pins[] = {
TEGRA_PIN_DP_AUX_CH3_N_PN0,
};
static const unsigned int soc_gpio39_pn1_pins[] = {
TEGRA_PIN_SOC_GPIO39_PN1,
};
static const unsigned int soc_gpio40_pn2_pins[] = {
TEGRA_PIN_SOC_GPIO40_PN2,
};
static const unsigned int dp_aux_ch1_p_pn3_pins[] = {
TEGRA_PIN_DP_AUX_CH1_P_PN3,
};
static const unsigned int dp_aux_ch1_n_pn4_pins[] = {
TEGRA_PIN_DP_AUX_CH1_N_PN4,
};
static const unsigned int dp_aux_ch2_p_pn5_pins[] = {
TEGRA_PIN_DP_AUX_CH2_P_PN5,
};
static const unsigned int dp_aux_ch2_n_pn6_pins[] = {
TEGRA_PIN_DP_AUX_CH2_N_PN6,
};
static const unsigned int dp_aux_ch3_p_pn7_pins[] = {
TEGRA_PIN_DP_AUX_CH3_P_PN7,
};
static const unsigned int extperiph1_clk_pp0_pins[] = {
TEGRA_PIN_EXTPERIPH1_CLK_PP0,
};
static const unsigned int extperiph2_clk_pp1_pins[] = {
TEGRA_PIN_EXTPERIPH2_CLK_PP1,
};
static const unsigned int cam_i2c_scl_pp2_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PP2,
};
static const unsigned int cam_i2c_sda_pp3_pins[] = {
TEGRA_PIN_CAM_I2C_SDA_PP3,
};
static const unsigned int soc_gpio23_pp4_pins[] = {
TEGRA_PIN_SOC_GPIO23_PP4,
};
static const unsigned int soc_gpio24_pp5_pins[] = {
TEGRA_PIN_SOC_GPIO24_PP5,
};
static const unsigned int soc_gpio25_pp6_pins[] = {
TEGRA_PIN_SOC_GPIO25_PP6,
};
static const unsigned int pwr_i2c_scl_pp7_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PP7,
};
static const unsigned int pwr_i2c_sda_pq0_pins[] = {
TEGRA_PIN_PWR_I2C_SDA_PQ0,
};
static const unsigned int soc_gpio28_pq1_pins[] = {
TEGRA_PIN_SOC_GPIO28_PQ1,
};
static const unsigned int soc_gpio29_pq2_pins[] = {
TEGRA_PIN_SOC_GPIO29_PQ2,
};
static const unsigned int soc_gpio30_pq3_pins[] = {
TEGRA_PIN_SOC_GPIO30_PQ3,
};
static const unsigned int soc_gpio31_pq4_pins[] = {
TEGRA_PIN_SOC_GPIO31_PQ4,
};
static const unsigned int soc_gpio32_pq5_pins[] = {
TEGRA_PIN_SOC_GPIO32_PQ5,
};
static const unsigned int soc_gpio33_pq6_pins[] = {
TEGRA_PIN_SOC_GPIO33_PQ6,
};
static const unsigned int soc_gpio35_pq7_pins[] = {
TEGRA_PIN_SOC_GPIO35_PQ7,
};
static const unsigned int soc_gpio37_pr0_pins[] = {
TEGRA_PIN_SOC_GPIO37_PR0,
};
static const unsigned int soc_gpio56_pr1_pins[] = {
TEGRA_PIN_SOC_GPIO56_PR1,
};
static const unsigned int uart1_tx_pr2_pins[] = {
TEGRA_PIN_UART1_TX_PR2,
};
static const unsigned int uart1_rx_pr3_pins[] = {
TEGRA_PIN_UART1_RX_PR3,
};
static const unsigned int uart1_rts_pr4_pins[] = {
TEGRA_PIN_UART1_RTS_PR4,
};
static const unsigned int uart1_cts_pr5_pins[] = {
TEGRA_PIN_UART1_CTS_PR5,
};
static const unsigned int gpu_pwr_req_px0_pins[] = {
TEGRA_PIN_GPU_PWR_REQ_PX0,
};
static const unsigned int cv_pwr_req_px1_pins[] = {
TEGRA_PIN_CV_PWR_REQ_PX1,
};
static const unsigned int gp_pwm2_px2_pins[] = {
TEGRA_PIN_GP_PWM2_PX2,
};
static const unsigned int gp_pwm3_px3_pins[] = {
TEGRA_PIN_GP_PWM3_PX3,
};
static const unsigned int uart2_tx_px4_pins[] = {
TEGRA_PIN_UART2_TX_PX4,
};
static const unsigned int uart2_rx_px5_pins[] = {
TEGRA_PIN_UART2_RX_PX5,
};
static const unsigned int uart2_rts_px6_pins[] = {
TEGRA_PIN_UART2_RTS_PX6,
};
static const unsigned int uart2_cts_px7_pins[] = {
TEGRA_PIN_UART2_CTS_PX7,
};
static const unsigned int spi3_sck_py0_pins[] = {
TEGRA_PIN_SPI3_SCK_PY0,
};
static const unsigned int spi3_miso_py1_pins[] = {
TEGRA_PIN_SPI3_MISO_PY1,
};
static const unsigned int spi3_mosi_py2_pins[] = {
TEGRA_PIN_SPI3_MOSI_PY2,
};
static const unsigned int spi3_cs0_py3_pins[] = {
TEGRA_PIN_SPI3_CS0_PY3,
};
static const unsigned int spi3_cs1_py4_pins[] = {
TEGRA_PIN_SPI3_CS1_PY4,
};
static const unsigned int uart5_tx_py5_pins[] = {
TEGRA_PIN_UART5_TX_PY5,
};
static const unsigned int uart5_rx_py6_pins[] = {
TEGRA_PIN_UART5_RX_PY6,
};
static const unsigned int uart5_rts_py7_pins[] = {
TEGRA_PIN_UART5_RTS_PY7,
};
static const unsigned int uart5_cts_pz0_pins[] = {
TEGRA_PIN_UART5_CTS_PZ0,
};
static const unsigned int usb_vbus_en0_pz1_pins[] = {
TEGRA_PIN_USB_VBUS_EN0_PZ1,
};
static const unsigned int usb_vbus_en1_pz2_pins[] = {
TEGRA_PIN_USB_VBUS_EN1_PZ2,
};
static const unsigned int spi1_sck_pz3_pins[] = {
TEGRA_PIN_SPI1_SCK_PZ3,
};
static const unsigned int spi1_miso_pz4_pins[] = {
TEGRA_PIN_SPI1_MISO_PZ4,
};
static const unsigned int spi1_mosi_pz5_pins[] = {
TEGRA_PIN_SPI1_MOSI_PZ5,
};
static const unsigned int spi1_cs0_pz6_pins[] = {
TEGRA_PIN_SPI1_CS0_PZ6,
};
static const unsigned int spi1_cs1_pz7_pins[] = {
TEGRA_PIN_SPI1_CS1_PZ7,
};
static const unsigned int can0_dout_paa0_pins[] = {
TEGRA_PIN_CAN0_DOUT_PAA0,
};
static const unsigned int can0_din_paa1_pins[] = {
TEGRA_PIN_CAN0_DIN_PAA1,
};
static const unsigned int can1_dout_paa2_pins[] = {
TEGRA_PIN_CAN1_DOUT_PAA2,
};
static const unsigned int can1_din_paa3_pins[] = {
TEGRA_PIN_CAN1_DIN_PAA3,
};
static const unsigned int can0_stb_paa4_pins[] = {
TEGRA_PIN_CAN0_STB_PAA4,
};
static const unsigned int can0_en_paa5_pins[] = {
TEGRA_PIN_CAN0_EN_PAA5,
};
static const unsigned int soc_gpio49_paa6_pins[] = {
TEGRA_PIN_SOC_GPIO49_PAA6,
};
static const unsigned int can0_err_paa7_pins[] = {
TEGRA_PIN_CAN0_ERR_PAA7,
};
static const unsigned int spi5_sck_pac0_pins[] = {
TEGRA_PIN_SPI5_SCK_PAC0,
};
static const unsigned int spi5_miso_pac1_pins[] = {
TEGRA_PIN_SPI5_MISO_PAC1,
};
static const unsigned int spi5_mosi_pac2_pins[] = {
TEGRA_PIN_SPI5_MOSI_PAC2,
};
static const unsigned int spi5_cs0_pac3_pins[] = {
TEGRA_PIN_SPI5_CS0_PAC3,
};
static const unsigned int soc_gpio57_pac4_pins[] = {
TEGRA_PIN_SOC_GPIO57_PAC4,
};
static const unsigned int soc_gpio58_pac5_pins[] = {
TEGRA_PIN_SOC_GPIO58_PAC5,
};
static const unsigned int soc_gpio59_pac6_pins[] = {
TEGRA_PIN_SOC_GPIO59_PAC6,
};
static const unsigned int soc_gpio60_pac7_pins[] = {
TEGRA_PIN_SOC_GPIO60_PAC7,
};
static const unsigned int soc_gpio45_pad0_pins[] = {
TEGRA_PIN_SOC_GPIO45_PAD0,
};
static const unsigned int soc_gpio46_pad1_pins[] = {
TEGRA_PIN_SOC_GPIO46_PAD1,
};
static const unsigned int soc_gpio47_pad2_pins[] = {
TEGRA_PIN_SOC_GPIO47_PAD2,
};
static const unsigned int soc_gpio48_pad3_pins[] = {
TEGRA_PIN_SOC_GPIO48_PAD3,
};
static const unsigned int ufs0_ref_clk_pae0_pins[] = {
TEGRA_PIN_UFS0_REF_CLK_PAE0,
};
static const unsigned int ufs0_rst_n_pae1_pins[] = {
TEGRA_PIN_UFS0_RST_N_PAE1,
};
static const unsigned int pex_l5_clkreq_n_paf0_pins[] = {
TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0,
};
static const unsigned int pex_l5_rst_n_paf1_pins[] = {
TEGRA_PIN_PEX_L5_RST_N_PAF1,
};
static const unsigned int pex_l6_clkreq_n_paf2_pins[] = {
TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2,
};
static const unsigned int pex_l6_rst_n_paf3_pins[] = {
TEGRA_PIN_PEX_L6_RST_N_PAF3,
};
static const unsigned int pex_l7_clkreq_n_pag0_pins[] = {
TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0,
};
static const unsigned int pex_l7_rst_n_pag1_pins[] = {
TEGRA_PIN_PEX_L7_RST_N_PAG1,
};
static const unsigned int pex_l8_clkreq_n_pag2_pins[] = {
TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2,
};
static const unsigned int pex_l8_rst_n_pag3_pins[] = {
TEGRA_PIN_PEX_L8_RST_N_PAG3,
};
static const unsigned int pex_l9_clkreq_n_pag4_pins[] = {
TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4,
};
static const unsigned int pex_l9_rst_n_pag5_pins[] = {
TEGRA_PIN_PEX_L9_RST_N_PAG5,
};
static const unsigned int pex_l10_clkreq_n_pag6_pins[] = {
TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6,
};
static const unsigned int pex_l10_rst_n_pag7_pins[] = {
TEGRA_PIN_PEX_L10_RST_N_PAG7,
};
static const unsigned int can1_stb_pbb0_pins[] = {
TEGRA_PIN_CAN1_STB_PBB0,
};
static const unsigned int can1_en_pbb1_pins[] = {
TEGRA_PIN_CAN1_EN_PBB1,
};
static const unsigned int soc_gpio50_pbb2_pins[] = {
TEGRA_PIN_SOC_GPIO50_PBB2,
};
static const unsigned int can1_err_pbb3_pins[] = {
TEGRA_PIN_CAN1_ERR_PBB3,
};
static const unsigned int spi2_sck_pcc0_pins[] = {
TEGRA_PIN_SPI2_SCK_PCC0,
};
static const unsigned int spi2_miso_pcc1_pins[] = {
TEGRA_PIN_SPI2_MISO_PCC1,
};
static const unsigned int spi2_mosi_pcc2_pins[] = {
TEGRA_PIN_SPI2_MOSI_PCC2,
};
static const unsigned int spi2_cs0_pcc3_pins[] = {
TEGRA_PIN_SPI2_CS0_PCC3,
};
static const unsigned int touch_clk_pcc4_pins[] = {
TEGRA_PIN_TOUCH_CLK_PCC4,
};
static const unsigned int uart3_tx_pcc5_pins[] = {
TEGRA_PIN_UART3_TX_PCC5,
};
static const unsigned int uart3_rx_pcc6_pins[] = {
TEGRA_PIN_UART3_RX_PCC6,
};
static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
TEGRA_PIN_GEN2_I2C_SCL_PCC7,
};
static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
TEGRA_PIN_GEN2_I2C_SDA_PDD0,
};
static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
TEGRA_PIN_GEN8_I2C_SCL_PDD1,
};
static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
TEGRA_PIN_GEN8_I2C_SDA_PDD2,
};
static const unsigned int sce_error_pee0_pins[] = {
TEGRA_PIN_SCE_ERROR_PEE0,
};
static const unsigned int vcomp_alert_pee1_pins[] = {
TEGRA_PIN_VCOMP_ALERT_PEE1,
};
static const unsigned int ao_retention_n_pee2_pins[] = {
TEGRA_PIN_AO_RETENTION_N_PEE2,
};
static const unsigned int batt_oc_pee3_pins[] = {
TEGRA_PIN_BATT_OC_PEE3,
};
static const unsigned int power_on_pee4_pins[] = {
TEGRA_PIN_POWER_ON_PEE4,
};
static const unsigned int soc_gpio26_pee5_pins[] = {
TEGRA_PIN_SOC_GPIO26_PEE5,
};
static const unsigned int soc_gpio27_pee6_pins[] = {
TEGRA_PIN_SOC_GPIO27_PEE6,
};
static const unsigned int bootv_ctl_n_pee7_pins[] = {
TEGRA_PIN_BOOTV_CTL_N_PEE7,
};
static const unsigned int hdmi_cec_pgg0_pins[] = {
TEGRA_PIN_HDMI_CEC_PGG0,
};
static const unsigned int eqos_comp_pins[] = {
TEGRA_PIN_EQOS_COMP,
};
static const unsigned int qspi_comp_pins[] = {
TEGRA_PIN_QSPI_COMP,
};
static const unsigned int sdmmc1_comp_pins[] = {
TEGRA_PIN_SDMMC1_COMP,
};
/* Define unique ID for each function */
enum tegra_mux_dt {
TEGRA_MUX_GP,
TEGRA_MUX_UARTC,
TEGRA_MUX_I2C8,
TEGRA_MUX_SPI2,
TEGRA_MUX_I2C2,
TEGRA_MUX_CAN1,
TEGRA_MUX_CAN0,
TEGRA_MUX_RSVD0,
TEGRA_MUX_ETH0,
TEGRA_MUX_ETH2,
TEGRA_MUX_ETH1,
TEGRA_MUX_DP,
TEGRA_MUX_ETH3,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2C7,
TEGRA_MUX_I2C9,
TEGRA_MUX_EQOS,
TEGRA_MUX_PE2,
TEGRA_MUX_PE1,
TEGRA_MUX_PE0,
TEGRA_MUX_PE3,
TEGRA_MUX_PE4,
TEGRA_MUX_PE5,
TEGRA_MUX_PE6,
TEGRA_MUX_PE10,
TEGRA_MUX_PE7,
TEGRA_MUX_PE8,
TEGRA_MUX_PE9,
TEGRA_MUX_QSPI0,
TEGRA_MUX_QSPI1,
TEGRA_MUX_QSPI,
TEGRA_MUX_SDMMC1,
TEGRA_MUX_SCE,
TEGRA_MUX_SOC,
TEGRA_MUX_GPIO,
TEGRA_MUX_HDMI,
TEGRA_MUX_UFS0,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI1,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTE,
TEGRA_MUX_USB,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_I2C3,
TEGRA_MUX_VI0,
TEGRA_MUX_I2C5,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTD,
TEGRA_MUX_I2C1,
TEGRA_MUX_I2S4,
TEGRA_MUX_I2S6,
TEGRA_MUX_AUD,
TEGRA_MUX_SPI5,
TEGRA_MUX_TOUCH,
TEGRA_MUX_UARTJ,
TEGRA_MUX_RSVD1,
TEGRA_MUX_WDT,
TEGRA_MUX_TSC,
TEGRA_MUX_DMIC3,
TEGRA_MUX_LED,
TEGRA_MUX_VI0_ALT,
TEGRA_MUX_I2S5,
TEGRA_MUX_NV,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_EXTPERIPH4,
TEGRA_MUX_SPI4,
TEGRA_MUX_CCLA,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S8,
TEGRA_MUX_I2S3,
TEGRA_MUX_RSVD2,
TEGRA_MUX_DMIC5,
TEGRA_MUX_DCA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_VI1,
TEGRA_MUX_DCB,
TEGRA_MUX_DMIC1,
TEGRA_MUX_DMIC4,
TEGRA_MUX_I2S7,
TEGRA_MUX_DMIC2,
TEGRA_MUX_DSPK0,
TEGRA_MUX_RSVD3,
TEGRA_MUX_TSC_ALT,
TEGRA_MUX_ISTCTRL,
TEGRA_MUX_VI1_ALT,
TEGRA_MUX_DSPK1,
TEGRA_MUX_IGPU,
};
/* Make list of each function name */
#define TEGRA_PIN_FUNCTION(lid) #lid
static const char * const tegra234_functions[] = {
TEGRA_PIN_FUNCTION(gp),
TEGRA_PIN_FUNCTION(uartc),
TEGRA_PIN_FUNCTION(i2c8),
TEGRA_PIN_FUNCTION(spi2),
TEGRA_PIN_FUNCTION(i2c2),
TEGRA_PIN_FUNCTION(can1),
TEGRA_PIN_FUNCTION(can0),
TEGRA_PIN_FUNCTION(rsvd0),
TEGRA_PIN_FUNCTION(eth0),
TEGRA_PIN_FUNCTION(eth2),
TEGRA_PIN_FUNCTION(eth1),
TEGRA_PIN_FUNCTION(dp),
TEGRA_PIN_FUNCTION(eth3),
TEGRA_PIN_FUNCTION(i2c4),
TEGRA_PIN_FUNCTION(i2c7),
TEGRA_PIN_FUNCTION(i2c9),
TEGRA_PIN_FUNCTION(eqos),
TEGRA_PIN_FUNCTION(pe2),
TEGRA_PIN_FUNCTION(pe1),
TEGRA_PIN_FUNCTION(pe0),
TEGRA_PIN_FUNCTION(pe3),
TEGRA_PIN_FUNCTION(pe4),
TEGRA_PIN_FUNCTION(pe5),
TEGRA_PIN_FUNCTION(pe6),
TEGRA_PIN_FUNCTION(pe10),
TEGRA_PIN_FUNCTION(pe7),
TEGRA_PIN_FUNCTION(pe8),
TEGRA_PIN_FUNCTION(pe9),
TEGRA_PIN_FUNCTION(qspi0),
TEGRA_PIN_FUNCTION(qspi1),
TEGRA_PIN_FUNCTION(qspi),
TEGRA_PIN_FUNCTION(sdmmc1),
TEGRA_PIN_FUNCTION(sce),
TEGRA_PIN_FUNCTION(soc),
TEGRA_PIN_FUNCTION(gpio),
TEGRA_PIN_FUNCTION(hdmi),
TEGRA_PIN_FUNCTION(ufs0),
TEGRA_PIN_FUNCTION(spi3),
TEGRA_PIN_FUNCTION(spi1),
TEGRA_PIN_FUNCTION(uartb),
TEGRA_PIN_FUNCTION(uarte),
TEGRA_PIN_FUNCTION(usb),
TEGRA_PIN_FUNCTION(extperiph2),
TEGRA_PIN_FUNCTION(extperiph1),
TEGRA_PIN_FUNCTION(i2c3),
TEGRA_PIN_FUNCTION(vi0),
TEGRA_PIN_FUNCTION(i2c5),
TEGRA_PIN_FUNCTION(uarta),
TEGRA_PIN_FUNCTION(uartd),
TEGRA_PIN_FUNCTION(i2c1),
TEGRA_PIN_FUNCTION(i2s4),
TEGRA_PIN_FUNCTION(i2s6),
TEGRA_PIN_FUNCTION(aud),
TEGRA_PIN_FUNCTION(spi5),
TEGRA_PIN_FUNCTION(touch),
TEGRA_PIN_FUNCTION(uartj),
TEGRA_PIN_FUNCTION(rsvd1),
TEGRA_PIN_FUNCTION(wdt),
TEGRA_PIN_FUNCTION(tsc),
TEGRA_PIN_FUNCTION(dmic3),
TEGRA_PIN_FUNCTION(led),
TEGRA_PIN_FUNCTION(vi0_alt),
TEGRA_PIN_FUNCTION(i2s5),
TEGRA_PIN_FUNCTION(nv),
TEGRA_PIN_FUNCTION(extperiph3),
TEGRA_PIN_FUNCTION(extperiph4),
TEGRA_PIN_FUNCTION(spi4),
TEGRA_PIN_FUNCTION(ccla),
TEGRA_PIN_FUNCTION(i2s2),
TEGRA_PIN_FUNCTION(i2s1),
TEGRA_PIN_FUNCTION(i2s8),
TEGRA_PIN_FUNCTION(i2s3),
TEGRA_PIN_FUNCTION(rsvd2),
TEGRA_PIN_FUNCTION(dmic5),
TEGRA_PIN_FUNCTION(dca),
TEGRA_PIN_FUNCTION(displayb),
TEGRA_PIN_FUNCTION(displaya),
TEGRA_PIN_FUNCTION(vi1),
TEGRA_PIN_FUNCTION(dcb),
TEGRA_PIN_FUNCTION(dmic1),
TEGRA_PIN_FUNCTION(dmic4),
TEGRA_PIN_FUNCTION(i2s7),
TEGRA_PIN_FUNCTION(dmic2),
TEGRA_PIN_FUNCTION(dspk0),
TEGRA_PIN_FUNCTION(rsvd3),
TEGRA_PIN_FUNCTION(tsc_alt),
TEGRA_PIN_FUNCTION(istctrl),
TEGRA_PIN_FUNCTION(vi1_alt),
TEGRA_PIN_FUNCTION(dspk1),
TEGRA_PIN_FUNCTION(igpu),
};
#define PINGROUP_REG_Y(r) ((r))
#define PINGROUP_REG_N(r) -1
#define DRV_PINGROUP_Y(r) ((r))
#define DRV_PINGROUP_N(r) -1
#define DRV_PINGROUP_ENTRY_N(pg_name) \
.drv_reg = -1, \
.drv_bank = -1, \
.drvdn_bit = -1, \
.drvup_bit = -1, \
.slwr_bit = -1, \
.slwf_bit = -1
#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
drvup_w, slwr_b, slwr_w, slwf_b, \
slwf_w, bank) \
.drv_reg = DRV_PINGROUP_Y(r), \
.drv_bank = bank, \
.drvdn_bit = drvdn_b, \
.drvdn_width = drvdn_w, \
.drvup_bit = drvup_b, \
.drvup_width = drvup_w, \
.slwr_bit = slwr_b, \
.slwr_width = slwr_w, \
.slwf_bit = slwf_b, \
.slwf_width = slwf_w
#define PIN_PINGROUP_ENTRY_N(pg_name) \
.mux_reg = -1, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.e_io_hv_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.parked_bit = -1, \
.lpmd_bit = -1, \
.drvtype_bit = -1, \
.lpdr_bit = -1, \
.pbias_buf_bit = -1, \
.preemp_bit = -1, \
.rfu_in_bit = -1
#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
e_lpdr, e_pbias_buf, gpio_sfio_sel, \
schmitt_b) \
.mux_reg = PINGROUP_REG_Y(r), \
.lpmd_bit = -1, \
.lock_bit = -1, \
.hsm_bit = -1, \
.mux_bank = bank, \
.mux_bit = 0, \
.pupd_reg = PINGROUP_REG_##pupd(r), \
.pupd_bank = bank, \
.pupd_bit = 2, \
.tri_reg = PINGROUP_REG_Y(r), \
.tri_bank = bank, \
.tri_bit = 4, \
.einput_bit = e_input, \
.sfsel_bit = gpio_sfio_sel, \
.schmitt_bit = schmitt_b, \
.drvtype_bit = 13, \
.lpdr_bit = e_lpdr, \
/* main drive pin groups */
#define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch2_hpd_pm2 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch3_hpd_pm3 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch1_p_pn3 DRV_PINGROUP_ENTRY_Y(0x10054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch1_n_pn4 DRV_PINGROUP_ENTRY_Y(0x1005c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch2_p_pn5 DRV_PINGROUP_ENTRY_Y(0x10064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch2_n_pn6 DRV_PINGROUP_ENTRY_Y(0x1006c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch3_p_pn7 DRV_PINGROUP_ENTRY_Y(0x10074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dp_aux_ch3_n_pn0 DRV_PINGROUP_ENTRY_Y(0x1007c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l2_clkreq_n_pk4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_wake_n_pl2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l1_clkreq_n_pk2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l1_rst_n_pk3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l0_clkreq_n_pk0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l0_rst_n_pk1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l2_rst_n_pk5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l3_clkreq_n_pk6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l3_rst_n_pk7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l4_clkreq_n_pl0 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l4_rst_n_pl1 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio34_pl3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l5_clkreq_n_paf0 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l5_rst_n_paf1 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l6_clkreq_n_paf2 DRV_PINGROUP_ENTRY_Y(0x14014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l6_rst_n_paf3 DRV_PINGROUP_ENTRY_Y(0x1401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l10_clkreq_n_pag6 DRV_PINGROUP_ENTRY_Y(0x19004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l10_rst_n_pag7 DRV_PINGROUP_ENTRY_Y(0x1900c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l7_clkreq_n_pag0 DRV_PINGROUP_ENTRY_Y(0x19014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l7_rst_n_pag1 DRV_PINGROUP_ENTRY_Y(0x1901c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l8_clkreq_n_pag2 DRV_PINGROUP_ENTRY_Y(0x19024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l8_rst_n_pag3 DRV_PINGROUP_ENTRY_Y(0x1902c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l9_clkreq_n_pag4 DRV_PINGROUP_ENTRY_Y(0x19034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pex_l9_rst_n_pag5 DRV_PINGROUP_ENTRY_Y(0x1903c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_sdmmc1_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x8004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sdmmc1_cmd_pj1 DRV_PINGROUP_ENTRY_Y(0x800c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sdmmc1_dat3_pj5 DRV_PINGROUP_ENTRY_Y(0x801c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sdmmc1_dat2_pj4 DRV_PINGROUP_ENTRY_Y(0x8024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sdmmc1_dat1_pj3 DRV_PINGROUP_ENTRY_Y(0x802c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sdmmc1_dat0_pj2 DRV_PINGROUP_ENTRY_Y(0x8034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_ufs0_rst_n_pae1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 5, 24, 5, -1, -1, -1, -1, 0)
#define drive_ufs0_ref_clk_pae0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
#define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_cs0_py3 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_miso_pz4 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_cs1_py4 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_sck_pz3 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_sck_py0 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_cs1_pz7 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_mosi_pz5 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_mosi_py2 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_tx_px4 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_rx_px5 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_rts_px6 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart2_cts_px7 DRV_PINGROUP_ENTRY_Y(0xd06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_tx_py5 DRV_PINGROUP_ENTRY_Y(0xd074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_rx_py6 DRV_PINGROUP_ENTRY_Y(0xd07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_rts_py7 DRV_PINGROUP_ENTRY_Y(0xd084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart5_cts_pz0 DRV_PINGROUP_ENTRY_Y(0xd08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xd094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gp_pwm3_px3 DRV_PINGROUP_ENTRY_Y(0xd09c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gp_pwm2_px2 DRV_PINGROUP_ENTRY_Y(0xd0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cv_pwr_req_px1 DRV_PINGROUP_ENTRY_Y(0xd0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_usb_vbus_en0_pz1 DRV_PINGROUP_ENTRY_Y(0xd0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_usb_vbus_en1_pz2 DRV_PINGROUP_ENTRY_Y(0xd0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_extperiph2_clk_pp1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_extperiph1_clk_pp0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cam_i2c_sda_pp3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cam_i2c_scl_pp2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio23_pp4 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio24_pp5 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio25_pp6 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pwr_i2c_scl_pp7 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_pwr_i2c_sda_pq0 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio28_pq1 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio29_pq2 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio30_pq3 DRV_PINGROUP_ENTRY_Y(0x005c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio31_pq4 DRV_PINGROUP_ENTRY_Y(0x0064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio32_pq5 DRV_PINGROUP_ENTRY_Y(0x006c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio33_pq6 DRV_PINGROUP_ENTRY_Y(0x0074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio35_pq7 DRV_PINGROUP_ENTRY_Y(0x007c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio37_pr0 DRV_PINGROUP_ENTRY_Y(0x0084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio56_pr1 DRV_PINGROUP_ENTRY_Y(0x008c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_cts_pr5 DRV_PINGROUP_ENTRY_Y(0x0094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_rts_pr4 DRV_PINGROUP_ENTRY_Y(0x009c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_rx_pr3 DRV_PINGROUP_ENTRY_Y(0x00a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart1_tx_pr2 DRV_PINGROUP_ENTRY_Y(0x00ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_cpu_pwr_req_pi5 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_cts_ph6 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_rts_ph5 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_rx_ph4 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart4_tx_ph3 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen1_i2c_scl_pi3 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen1_i2c_sda_pi4 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio20_pg7 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio21_ph0 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio22_ph1 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio13_pg0 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio14_pg1 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio15_pg2 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio16_pg3 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio17_pg4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio18_pg5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio19_pg6 DRV_PINGROUP_ENTRY_Y(0x4084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio41_ph7 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio42_pi0 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio43_pi1 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio44_pi2 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio06_ph2 DRV_PINGROUP_ENTRY_Y(0x40ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio07_pi6 DRV_PINGROUP_ENTRY_Y(0x40b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap4_sclk_pa4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap4_dout_pa5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap4_din_pa6 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap4_fs_pa7 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap6_sclk_pa0 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap6_dout_pa1 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap6_din_pa2 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_dap6_fs_pa3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio45_pad0 DRV_PINGROUP_ENTRY_Y(0x18004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio46_pad1 DRV_PINGROUP_ENTRY_Y(0x1800c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio47_pad2 DRV_PINGROUP_ENTRY_Y(0x18014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio48_pad3 DRV_PINGROUP_ENTRY_Y(0x1801c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio57_pac4 DRV_PINGROUP_ENTRY_Y(0x18024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio58_pac5 DRV_PINGROUP_ENTRY_Y(0x1802c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio59_pac6 DRV_PINGROUP_ENTRY_Y(0x18034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio60_pac7 DRV_PINGROUP_ENTRY_Y(0x1803c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi5_cs0_pac3 DRV_PINGROUP_ENTRY_Y(0x18044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi5_miso_pac1 DRV_PINGROUP_ENTRY_Y(0x1804c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi5_mosi_pac2 DRV_PINGROUP_ENTRY_Y(0x18054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi5_sck_pac0 DRV_PINGROUP_ENTRY_Y(0x1805c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_sma_mdio_pf4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_sma_mdc_pf5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io3_pc5 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io2_pc4 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io1_pc3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_io0_pc2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_sck_pc0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi0_cs_n_pc1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io3_pd3 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io2_pd2 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io1_pd1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_io0_pd0 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_sck_pc6 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi1_cs_n_pc7 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry)
#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
gpio_sfio_sel, schmitt_b) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.funcs = { \
TEGRA_MUX_##f0, \
TEGRA_MUX_##f1, \
TEGRA_MUX_##f2, \
TEGRA_MUX_##f3, \
}, \
PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
e_input, e_lpdr, e_pbias_buf, \
gpio_sfio_sel, schmitt_b) \
drive_##pg_name, \
}
static const struct tegra_pingroup tegra234_groups[] = {
PINGROUP(soc_gpio08_pb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio36_pm5, ETH0, RSVD1, DCA, RSVD3, 0x10000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio53_pm6, ETH0, RSVD1, DCA, RSVD3, 0x10008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio55_pm4, ETH2, RSVD1, RSVD2, RSVD3, 0x10010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio38_pm7, ETH1, RSVD1, RSVD2, RSVD3, 0x10018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio39_pn1, GP, RSVD1, RSVD2, RSVD3, 0x10020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio40_pn2, ETH1, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch0_hpd_pm0, DP, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch1_hpd_pm1, ETH3, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch2_hpd_pm2, ETH3, RSVD1, DISPLAYB, RSVD3, 0x10040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch3_hpd_pm3, ETH2, RSVD1, DISPLAYA, RSVD3, 0x10048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch1_p_pn3, I2C4, RSVD1, RSVD2, RSVD3, 0x10050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch1_n_pn4, I2C4, RSVD1, RSVD2, RSVD3, 0x10058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch2_p_pn5, I2C7, RSVD1, RSVD2, RSVD3, 0x10060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch2_n_pn6, I2C7, RSVD1, RSVD2, RSVD3, 0x10068, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch3_p_pn7, I2C9, RSVD1, RSVD2, RSVD3, 0x10070, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(dp_aux_ch3_n_pn0, I2C9, RSVD1, RSVD2, RSVD3, 0x10078, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(eqos_td3_pe4, EQOS, RSVD1, RSVD2, RSVD3, 0x15000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_td2_pe3, EQOS, RSVD1, RSVD2, RSVD3, 0x15008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_td1_pe2, EQOS, RSVD1, RSVD2, RSVD3, 0x15010, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_td0_pe1, EQOS, RSVD1, RSVD2, RSVD3, 0x15018, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rd3_pf1, EQOS, RSVD1, RSVD2, RSVD3, 0x15020, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rd2_pf0, EQOS, RSVD1, RSVD2, RSVD3, 0x15028, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rd1_pe7, EQOS, RSVD1, RSVD2, RSVD3, 0x15030, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_sma_mdio_pf4, EQOS, RSVD1, RSVD2, RSVD3, 0x15038, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rd0_pe6, EQOS, RSVD1, RSVD2, RSVD3, 0x15040, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_sma_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x15048, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_comp, EQOS, RSVD1, RSVD2, RSVD3, 0x15050, 0, N, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(eqos_txc_pe0, EQOS, RSVD1, RSVD2, RSVD3, 0x15058, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rxc_pf3, EQOS, RSVD1, RSVD2, RSVD3, 0x15060, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_tx_ctl_pe5, EQOS, RSVD1, RSVD2, RSVD3, 0x15068, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(eqos_rx_ctl_pf2, EQOS, RSVD1, RSVD2, RSVD3, 0x15070, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(pex_l2_clkreq_n_pk4, PE2, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_wake_n_pl2, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l1_clkreq_n_pk2, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l1_rst_n_pk3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l0_clkreq_n_pk0, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l0_rst_n_pk1, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l2_rst_n_pk5, PE2, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l3_clkreq_n_pk6, PE3, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l3_rst_n_pk7, PE3, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l4_clkreq_n_pl0, PE4, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l4_rst_n_pl1, PE4, RSVD1, RSVD2, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio34_pl3, RSVD0, RSVD1, RSVD2, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l5_clkreq_n_paf0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l5_rst_n_paf1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l6_clkreq_n_paf2, PE6, RSVD1, RSVD2, RSVD3, 0x14010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l6_rst_n_paf3, PE6, RSVD1, RSVD2, RSVD3, 0x14018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l10_clkreq_n_pag6, PE10, RSVD1, RSVD2, RSVD3, 0x19000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l10_rst_n_pag7, PE10, RSVD1, RSVD2, RSVD3, 0x19008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l7_clkreq_n_pag0, PE7, RSVD1, RSVD2, RSVD3, 0x19010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l7_rst_n_pag1, PE7, RSVD1, RSVD2, RSVD3, 0x19018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l8_clkreq_n_pag2, PE8, RSVD1, RSVD2, RSVD3, 0x19020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l8_rst_n_pag3, PE8, RSVD1, RSVD2, RSVD3, 0x19028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l9_clkreq_n_pag4, PE9, RSVD1, RSVD2, RSVD3, 0x19030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pex_l9_rst_n_pag5, PE9, RSVD1, RSVD2, RSVD3, 0x19038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(qspi0_io3_pc5, QSPI0, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi0_io2_pc4, QSPI0, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi0_io1_pc3, QSPI0, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi0_io0_pc2, QSPI0, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi0_sck_pc0, QSPI0, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi0_cs_n_pc1, QSPI0, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_io3_pd3, QSPI1, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_io2_pd2, QSPI1, RSVD1, RSVD2, RSVD3, 0xB038, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_io1_pd1, QSPI1, RSVD1, RSVD2, RSVD3, 0xB040, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_io0_pd0, QSPI1, RSVD1, RSVD2, RSVD3, 0xB048, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_sck_pc6, QSPI1, RSVD1, RSVD2, RSVD3, 0xB050, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi1_cs_n_pc7, QSPI1, RSVD1, RSVD2, RSVD3, 0xB058, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB060, 0, N, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_clk_pj0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sdmmc1_cmd_pj1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1),
PINGROUP(sdmmc1_dat3_pj5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8018, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sdmmc1_dat2_pj4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8020, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sdmmc1_dat1_pj3, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8028, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sdmmc1_dat0_pj2, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8030, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(ufs0_rst_n_pae1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(ufs0_ref_clk_pae0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi3_cs0_py3, SPI3, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi1_miso_pz4, SPI1, RSVD1, RSVD2, RSVD3, 0xD018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi3_cs1_py4, SPI3, RSVD1, RSVD2, RSVD3, 0xD020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi1_sck_pz3, SPI1, RSVD1, RSVD2, RSVD3, 0xD028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi3_sck_py0, SPI3, RSVD1, RSVD2, RSVD3, 0xD030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi1_cs1_pz7, SPI1, RSVD1, RSVD2, RSVD3, 0xD038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi1_mosi_pz5, SPI1, RSVD1, RSVD2, RSVD3, 0xD040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi3_mosi_py2, SPI3, RSVD1, RSVD2, RSVD3, 0xD048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart2_tx_px4, UARTB, RSVD1, RSVD2, RSVD3, 0xD050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart2_rx_px5, UARTB, RSVD1, RSVD2, RSVD3, 0xD058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart2_rts_px6, UARTB, RSVD1, RSVD2, RSVD3, 0xD060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart2_cts_px7, UARTB, RSVD1, RSVD2, RSVD3, 0xD068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart5_tx_py5, UARTE, RSVD1, RSVD2, RSVD3, 0xD070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart5_rx_py6, UARTE, RSVD1, RSVD2, RSVD3, 0xD078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart5_rts_py7, UARTE, RSVD1, RSVD2, RSVD3, 0xD080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart5_cts_pz0, UARTE, RSVD1, RSVD2, RSVD3, 0xD088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(gp_pwm3_px3, GP, RSVD1, RSVD2, RSVD3, 0xD098, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gp_pwm2_px2, GP, RSVD1, RSVD2, RSVD3, 0xD0A0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(cv_pwr_req_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0xD0A8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(usb_vbus_en0_pz1, USB, RSVD1, RSVD2, RSVD3, 0xD0B0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(usb_vbus_en1_pz2, USB, RSVD1, RSVD2, RSVD3, 0xD0B8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(extperiph2_clk_pp1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(extperiph1_clk_pp0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(cam_i2c_sda_pp3, I2C3, VI0, RSVD2, VI1, 0x0010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(cam_i2c_scl_pp2, I2C3, VI0, VI0_ALT, VI1, 0x0018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio23_pp4, VI0, VI0_ALT, VI1, VI1_ALT, 0x0020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio24_pp5, VI0, SOC, VI1, VI1_ALT, 0x0028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio25_pp6, VI0, I2S5, VI1, DMIC1, 0x0030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pwr_i2c_scl_pp7, I2C5, RSVD1, RSVD2, RSVD3, 0x0038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(pwr_i2c_sda_pq0, I2C5, RSVD1, RSVD2, RSVD3, 0x0040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio28_pq1, VI0, RSVD1, VI1, RSVD3, 0x0048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio29_pq2, RSVD0, NV, RSVD2, RSVD3, 0x0050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio30_pq3, RSVD0, WDT, RSVD2, RSVD3, 0x0058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio31_pq4, RSVD0, RSVD1, RSVD2, RSVD3, 0x0060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio32_pq5, RSVD0, EXTPERIPH3, DCB, RSVD3, 0x0068, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio33_pq6, RSVD0, EXTPERIPH4, DCB, RSVD3, 0x0070, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio35_pq7, RSVD0, I2S5, DMIC1, RSVD3, 0x0078, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio37_pr0, GP, I2S5, DMIC4, DSPK1, 0x0080, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio56_pr1, RSVD0, I2S5, DMIC4, DSPK1, 0x0088, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart1_cts_pr5, UARTA, RSVD1, RSVD2, RSVD3, 0x0090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart1_rts_pr4, UARTA, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart1_rx_pr3, UARTA, RSVD1, RSVD2, RSVD3, 0x00A0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart1_tx_pr2, UARTA, RSVD1, RSVD2, RSVD3, 0x00A8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(cpu_pwr_req_pi5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart4_cts_ph6, UARTD, RSVD1, I2S7, RSVD3, 0x4008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart4_rts_ph5, UARTD, SPI4, RSVD2, RSVD3, 0x4010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart4_rx_ph4, UARTD, RSVD1, I2S7, RSVD3, 0x4018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(uart4_tx_ph3, UARTD, SPI4, RSVD2, RSVD3, 0x4020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(gen1_i2c_scl_pi3, I2C1, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gen1_i2c_sda_pi4, I2C1, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio20_pg7, RSVD0, SDMMC1, RSVD2, RSVD3, 0x4038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio21_ph0, RSVD0, GP, I2S7, RSVD3, 0x4040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio22_ph1, RSVD0, RSVD1, I2S7, RSVD3, 0x4048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio13_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio14_pg1, RSVD0, SPI4, RSVD2, RSVD3, 0x4058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio15_pg2, RSVD0, SPI4, RSVD2, RSVD3, 0x4060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio16_pg3, RSVD0, SPI4, RSVD2, RSVD3, 0x4068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio17_pg4, RSVD0, CCLA, RSVD2, RSVD3, 0x4070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio18_pg5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio19_pg6, GP, RSVD1, RSVD2, RSVD3, 0x4080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio41_ph7, RSVD0, I2S2, RSVD2, RSVD3, 0x4088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio42_pi0, RSVD0, I2S2, RSVD2, RSVD3, 0x4090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio43_pi1, RSVD0, I2S2, RSVD2, RSVD3, 0x4098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio44_pi2, RSVD0, I2S2, RSVD2, RSVD3, 0x40A0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio06_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x40A8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio07_pi6, GP, RSVD1, RSVD2, RSVD3, 0x40B0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap4_sclk_pa4, I2S4, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap4_dout_pa5, I2S4, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap4_din_pa6, I2S4, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap4_fs_pa7, I2S4, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap6_sclk_pa0, I2S6, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap6_dout_pa1, I2S6, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap6_din_pa2, I2S6, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(dap6_fs_pa3, I2S6, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio45_pad0, RSVD0, I2S1, RSVD2, RSVD3, 0x18000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio46_pad1, RSVD0, I2S1, RSVD2, RSVD3, 0x18008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio47_pad2, RSVD0, I2S1, RSVD2, RSVD3, 0x18010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio48_pad3, RSVD0, I2S1, RSVD2, RSVD3, 0x18018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio57_pac4, RSVD0, I2S8, RSVD2, SDMMC1, 0x18020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio58_pac5, RSVD0, I2S8, RSVD2, SDMMC1, 0x18028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio59_pac6, AUD, I2S8, RSVD2, RSVD3, 0x18030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio60_pac7, RSVD0, I2S8, NV, IGPU, 0x18038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(spi5_cs0_pac3, SPI5, I2S3, DMIC2, RSVD3, 0x18040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(spi5_miso_pac1, SPI5, I2S3, DSPK0, RSVD3, 0x18048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(spi5_mosi_pac2, SPI5, I2S3, DMIC2, RSVD3, 0x18050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(spi5_sck_pac0, SPI5, I2S3, DSPK0, RSVD3, 0x18058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
};
static const struct tegra_pinctrl_soc_data tegra234_pinctrl = {
.pins = tegra234_pins,
.npins = ARRAY_SIZE(tegra234_pins),
.functions = tegra234_functions,
.nfunctions = ARRAY_SIZE(tegra234_functions),
.groups = tegra234_groups,
.ngroups = ARRAY_SIZE(tegra234_groups),
.hsm_in_mux = false,
.schmitt_in_mux = true,
.drvtype_in_mux = true,
.sfsel_in_mux = true,
};
static const struct pinctrl_pin_desc tegra234_aon_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA0, "CAN0_DOUT_PAA0"),
PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA1, "CAN0_DIN_PAA1"),
PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA2, "CAN1_DOUT_PAA2"),
PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA3, "CAN1_DIN_PAA3"),
PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PAA6, "SOC_GPIO49_PAA6"),
PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PBB2, "SOC_GPIO50_PBB2"),
PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
PINCTRL_PIN(TEGRA_PIN_SCE_ERROR_PEE0, "SCE_ERROR_PEE0"),
PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE5, "SOC_GPIO26_PEE5"),
PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE6, "SOC_GPIO27_PEE6"),
PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PEE7, "BOOTV_CTL_N_PEE7"),
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PGG0, "HDMI_CEC_PGG0"),
};
/* AON drive pin groups */
#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_can1_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_din_paa3 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_din_paa1 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_soc_gpio49_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_soc_gpio50_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
#define drive_sce_error_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_bootv_ctl_n_pee7 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio26_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio27_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_hdmi_cec_pgg0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
static const struct tegra_pingroup tegra234_aon_groups[] = {
PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart3_rx_pcc6, UARTC, UARTJ, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(uart3_tx_pcc5, UARTC, UARTJ, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi2_mosi_pcc2, SPI2, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi2_cs0_pcc3, SPI2, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi2_sck_pcc0, SPI2, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(spi2_miso_pcc1, SPI2, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(can1_dout_paa2, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can1_din_paa3, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can0_dout_paa0, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can0_din_paa1, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can0_stb_paa4, RSVD0, WDT, TSC, TSC_ALT, 0x3020, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(soc_gpio49_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can0_err_paa7, RSVD0, TSC, RSVD2, TSC_ALT, 0x3038, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(soc_gpio50_pbb2, RSVD0, TSC, RSVD2, TSC_ALT, 0x3050, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(can1_err_pbb3, RSVD0, TSC, RSVD2, TSC_ALT, 0x3058, 0, Y, -1, 5, 6, -1, 9, 10, 12),
PINGROUP(sce_error_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(bootv_ctl_n_pee7, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio26_pee5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(soc_gpio27_pee6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(ao_retention_n_pee2, GPIO, LED, RSVD2, ISTCTRL, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
PINGROUP(hdmi_cec_pgg0, HDMI, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
};
static const struct tegra_pinctrl_soc_data tegra234_pinctrl_aon = {
.pins = tegra234_aon_pins,
.npins = ARRAY_SIZE(tegra234_aon_pins),
.functions = tegra234_functions,
.nfunctions = ARRAY_SIZE(tegra234_functions),
.groups = tegra234_aon_groups,
.ngroups = ARRAY_SIZE(tegra234_aon_groups),
.hsm_in_mux = false,
.schmitt_in_mux = true,
.drvtype_in_mux = true,
.sfsel_in_mux = true,
};
static int tegra234_pinctrl_probe(struct platform_device *pdev)
{
const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);
return tegra_pinctrl_probe(pdev, soc);
}
static const struct of_device_id tegra234_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra234-pinmux", .data = &tegra234_pinctrl},
{ .compatible = "nvidia,tegra234-pinmux-aon", .data = &tegra234_pinctrl_aon },
{ }
};
MODULE_DEVICE_TABLE(of, tegra234_pinctrl_of_match);
static struct platform_driver tegra234_pinctrl_driver = {
.driver = {
.name = "tegra234-pinctrl",
.of_match_table = tegra234_pinctrl_of_match,
},
.probe = tegra234_pinctrl_probe,
};
static int __init tegra234_pinctrl_init(void)
{
return platform_driver_register(&tegra234_pinctrl_driver);
}
arch_initcall(tegra234_pinctrl_init);
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra234.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the NVIDIA Tegra pinmux
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
* Copyright (C) 2009-2011 ST-Ericsson AB
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-tegra.h"
static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
{
return readl(pmx->regs[bank] + reg);
}
static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
{
writel_relaxed(val, pmx->regs[bank] + reg);
/* make sure pinmux register write completed */
pmx_readl(pmx, bank, reg);
}
static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->soc->ngroups;
}
static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->soc->groups[group].name;
}
static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
*pins = pmx->soc->groups[group].pins;
*num_pins = pmx->soc->groups[group].npins;
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
#endif
static const struct cfg_param {
const char *property;
enum tegra_pinconf_param param;
} cfg_params[] = {
{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
{"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
{"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
{"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
{"nvidia,function", TEGRA_PINCONF_PARAM_FUNCTION},
};
static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct device *dev = pctldev->dev;
int ret, i;
const char *function;
u32 val;
unsigned long config;
unsigned long *configs = NULL;
unsigned num_configs = 0;
unsigned reserve;
struct property *prop;
const char *group;
ret = of_property_read_string(np, "nvidia,function", &function);
if (ret < 0) {
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev,
"could not parse property nvidia,function\n");
function = NULL;
}
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
ret = of_property_read_u32(np, cfg_params[i].property, &val);
if (!ret) {
config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
ret = pinctrl_utils_add_config(pctldev, &configs,
&num_configs, config);
if (ret < 0)
goto exit;
/* EINVAL=missing, which is fine since it's optional */
} else if (ret != -EINVAL) {
dev_err(dev, "could not parse property %s\n",
cfg_params[i].property);
}
}
reserve = 0;
if (function != NULL)
reserve++;
if (num_configs)
reserve++;
ret = of_property_count_strings(np, "nvidia,pins");
if (ret < 0) {
dev_err(dev, "could not parse property nvidia,pins\n");
goto exit;
}
reserve *= ret;
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "nvidia,pins", prop, group) {
if (function) {
ret = pinctrl_utils_add_map_mux(pctldev, map,
reserved_maps, num_maps, group,
function);
if (ret < 0)
goto exit;
}
if (num_configs) {
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
goto exit;
}
}
ret = 0;
exit:
kfree(configs);
return ret;
}
static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
unsigned reserved_maps;
struct device_node *np;
int ret;
reserved_maps = 0;
*map = NULL;
*num_maps = 0;
for_each_child_of_node(np_config, np) {
ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map,
*num_maps);
of_node_put(np);
return ret;
}
}
return 0;
}
static const struct pinctrl_ops tegra_pinctrl_ops = {
.get_groups_count = tegra_pinctrl_get_groups_count,
.get_group_name = tegra_pinctrl_get_group_name,
.get_group_pins = tegra_pinctrl_get_group_pins,
#ifdef CONFIG_DEBUG_FS
.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
#endif
.dt_node_to_map = tegra_pinctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->soc->nfunctions;
}
static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->functions[function].name;
}
static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
*groups = pmx->functions[function].groups;
*num_groups = pmx->functions[function].ngroups;
return 0;
}
static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *g;
int i;
u32 val;
g = &pmx->soc->groups[group];
if (WARN_ON(g->mux_reg < 0))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
if (g->funcs[i] == function)
break;
}
if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
return -EINVAL;
val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
val &= ~(0x3 << g->mux_bit);
val |= i << g->mux_bit;
pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
return 0;
}
static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
unsigned int offset)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
unsigned int group, num_pins, j;
const unsigned int *pins;
int ret;
for (group = 0; group < pmx->soc->ngroups; ++group) {
ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
if (ret < 0)
continue;
for (j = 0; j < num_pins; j++) {
if (offset == pins[j])
return &pmx->soc->groups[group];
}
}
dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
return NULL;
}
static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *group;
u32 value;
if (!pmx->soc->sfsel_in_mux)
return 0;
group = tegra_pinctrl_get_group(pctldev, offset);
if (!group)
return -EINVAL;
if (group->mux_reg < 0 || group->sfsel_bit < 0)
return -EINVAL;
value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
value &= ~BIT(group->sfsel_bit);
pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
return 0;
}
static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *group;
u32 value;
if (!pmx->soc->sfsel_in_mux)
return;
group = tegra_pinctrl_get_group(pctldev, offset);
if (!group)
return;
if (group->mux_reg < 0 || group->sfsel_bit < 0)
return;
value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
value |= BIT(group->sfsel_bit);
pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
}
static const struct pinmux_ops tegra_pinmux_ops = {
.get_functions_count = tegra_pinctrl_get_funcs_count,
.get_function_name = tegra_pinctrl_get_func_name,
.get_function_groups = tegra_pinctrl_get_func_groups,
.set_mux = tegra_pinctrl_set_mux,
.gpio_request_enable = tegra_pinctrl_gpio_request_enable,
.gpio_disable_free = tegra_pinctrl_gpio_disable_free,
};
static int tegra_pinconf_reg(struct tegra_pmx *pmx,
const struct tegra_pingroup *g,
enum tegra_pinconf_param param,
bool report_err,
s8 *bank, s32 *reg, s8 *bit, s8 *width)
{
switch (param) {
case TEGRA_PINCONF_PARAM_PULL:
*bank = g->pupd_bank;
*reg = g->pupd_reg;
*bit = g->pupd_bit;
*width = 2;
break;
case TEGRA_PINCONF_PARAM_TRISTATE:
*bank = g->tri_bank;
*reg = g->tri_reg;
*bit = g->tri_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->einput_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->odrain_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_LOCK:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->lock_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_IORESET:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->ioreset_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_RCV_SEL:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->rcv_sel_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
if (pmx->soc->hsm_in_mux) {
*bank = g->mux_bank;
*reg = g->mux_reg;
} else {
*bank = g->drv_bank;
*reg = g->drv_reg;
}
*bit = g->hsm_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_SCHMITT:
if (pmx->soc->schmitt_in_mux) {
*bank = g->mux_bank;
*reg = g->mux_reg;
} else {
*bank = g->drv_bank;
*reg = g->drv_reg;
}
*bit = g->schmitt_bit;
*width = 1;
break;
case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
*bank = g->drv_bank;
*reg = g->drv_reg;
*bit = g->lpmd_bit;
*width = 2;
break;
case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
*bank = g->drv_bank;
*reg = g->drv_reg;
*bit = g->drvdn_bit;
*width = g->drvdn_width;
break;
case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
*bank = g->drv_bank;
*reg = g->drv_reg;
*bit = g->drvup_bit;
*width = g->drvup_width;
break;
case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
*bank = g->drv_bank;
*reg = g->drv_reg;
*bit = g->slwf_bit;
*width = g->slwf_width;
break;
case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
*bank = g->drv_bank;
*reg = g->drv_reg;
*bit = g->slwr_bit;
*width = g->slwr_width;
break;
case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
if (pmx->soc->drvtype_in_mux) {
*bank = g->mux_bank;
*reg = g->mux_reg;
} else {
*bank = g->drv_bank;
*reg = g->drv_reg;
}
*bit = g->drvtype_bit;
*width = 2;
break;
case TEGRA_PINCONF_PARAM_FUNCTION:
*bank = g->mux_bank;
*reg = g->mux_reg;
*bit = g->mux_bit;
*width = 2;
break;
default:
dev_err(pmx->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
if (*reg < 0 || *bit < 0) {
if (report_err) {
const char *prop = "unknown";
int i;
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
if (cfg_params[i].param == param) {
prop = cfg_params[i].property;
break;
}
}
dev_err(pmx->dev,
"Config param %04x (%s) not supported on group %s\n",
param, prop, g->name);
}
return -ENOTSUPP;
}
return 0;
}
static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
dev_err(pctldev->dev, "pin_config_get op not supported\n");
return -ENOTSUPP;
}
static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
dev_err(pctldev->dev, "pin_config_set op not supported\n");
return -ENOTSUPP;
}
static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
u16 arg;
const struct tegra_pingroup *g;
int ret;
s8 bank, bit, width;
s32 reg;
u32 val, mask;
g = &pmx->soc->groups[group];
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
&width);
if (ret < 0)
return ret;
val = pmx_readl(pmx, bank, reg);
mask = (1 << width) - 1;
arg = (val >> bit) & mask;
*config = TEGRA_PINCONF_PACK(param, arg);
return 0;
}
static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum tegra_pinconf_param param;
u16 arg;
const struct tegra_pingroup *g;
int ret, i;
s8 bank, bit, width;
s32 reg;
u32 val, mask;
g = &pmx->soc->groups[group];
for (i = 0; i < num_configs; i++) {
param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
&width);
if (ret < 0)
return ret;
val = pmx_readl(pmx, bank, reg);
/* LOCK can't be cleared */
if (param == TEGRA_PINCONF_PARAM_LOCK) {
if ((val & BIT(bit)) && !arg) {
dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
return -EINVAL;
}
}
/* Special-case Boolean values; allow any non-zero as true */
if (width == 1)
arg = !!arg;
/* Range-check user-supplied value */
mask = (1 << width) - 1;
if (arg & ~mask) {
dev_err(pctldev->dev,
"config %lx: %x too big for %d bit register\n",
configs[i], arg, width);
return -EINVAL;
}
/* Update register */
val &= ~(mask << bit);
val |= arg << bit;
pmx_writel(pmx, val, bank, reg);
} /* for each config */
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned offset)
{
}
static const char *strip_prefix(const char *s)
{
const char *comma = strchr(s, ',');
if (!comma)
return s;
return comma + 1;
}
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *g;
int i, ret;
s8 bank, bit, width;
s32 reg;
u32 val;
g = &pmx->soc->groups[group];
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
&bank, ®, &bit, &width);
if (ret < 0)
continue;
val = pmx_readl(pmx, bank, reg);
val >>= bit;
val &= (1 << width) - 1;
if (cfg_params[i].param == TEGRA_PINCONF_PARAM_FUNCTION) {
u8 idx = pmx->soc->groups[group].funcs[val];
seq_printf(s, "\n\t%s=%s",
strip_prefix(cfg_params[i].property),
pmx->functions[idx].name);
} else {
seq_printf(s, "\n\t%s=%u",
strip_prefix(cfg_params[i].property), val);
}
}
}
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned long config)
{
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
const char *pname = "unknown";
int i;
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
if (cfg_params[i].param == param) {
pname = cfg_params[i].property;
break;
}
}
seq_printf(s, "%s=%d", strip_prefix(pname), arg);
}
#endif
static const struct pinconf_ops tegra_pinconf_ops = {
.pin_config_get = tegra_pinconf_get,
.pin_config_set = tegra_pinconf_set,
.pin_config_group_get = tegra_pinconf_group_get,
.pin_config_group_set = tegra_pinconf_group_set,
#ifdef CONFIG_DEBUG_FS
.pin_config_dbg_show = tegra_pinconf_dbg_show,
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
#endif
};
static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
{
int i = 0;
const struct tegra_pingroup *g;
u32 val;
for (i = 0; i < pmx->soc->ngroups; ++i) {
g = &pmx->soc->groups[i];
if (g->parked_bitmask > 0) {
unsigned int bank, reg;
if (g->mux_reg != -1) {
bank = g->mux_bank;
reg = g->mux_reg;
} else {
bank = g->drv_bank;
reg = g->drv_reg;
}
val = pmx_readl(pmx, bank, reg);
val &= ~g->parked_bitmask;
pmx_writel(pmx, val, bank, reg);
}
}
}
static size_t tegra_pinctrl_get_bank_size(struct device *dev,
unsigned int bank_id)
{
struct platform_device *pdev = to_platform_device(dev);
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
return resource_size(res) / 4;
}
static int tegra_pinctrl_suspend(struct device *dev)
{
struct tegra_pmx *pmx = dev_get_drvdata(dev);
u32 *backup_regs = pmx->backup_regs;
u32 __iomem *regs;
size_t bank_size;
unsigned int i, k;
for (i = 0; i < pmx->nbanks; i++) {
bank_size = tegra_pinctrl_get_bank_size(dev, i);
regs = pmx->regs[i];
for (k = 0; k < bank_size; k++)
*backup_regs++ = readl_relaxed(regs++);
}
return pinctrl_force_sleep(pmx->pctl);
}
static int tegra_pinctrl_resume(struct device *dev)
{
struct tegra_pmx *pmx = dev_get_drvdata(dev);
u32 *backup_regs = pmx->backup_regs;
u32 __iomem *regs;
size_t bank_size;
unsigned int i, k;
for (i = 0; i < pmx->nbanks; i++) {
bank_size = tegra_pinctrl_get_bank_size(dev, i);
regs = pmx->regs[i];
for (k = 0; k < bank_size; k++)
writel_relaxed(*backup_regs++, regs++);
}
/* flush all the prior writes */
readl_relaxed(pmx->regs[0]);
/* wait for pinctrl register read to complete */
rmb();
return 0;
}
DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume);
static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
{
struct device_node *np;
bool has_prop = false;
np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
if (!np)
return has_prop;
has_prop = of_find_property(np, "gpio-ranges", NULL);
of_node_put(np);
return has_prop;
}
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data)
{
struct tegra_pmx *pmx;
struct resource *res;
int i;
const char **group_pins;
int fn, gn, gfn;
unsigned long backup_regs_size = 0;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
pmx->dev = &pdev->dev;
pmx->soc = soc_data;
/*
* Each mux group will appear in 4 functions' list of groups.
* This over-allocates slightly, since not all groups are mux groups.
*/
pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,
sizeof(*pmx->group_pins), GFP_KERNEL);
if (!pmx->group_pins)
return -ENOMEM;
pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,
sizeof(*pmx->functions), GFP_KERNEL);
if (!pmx->functions)
return -ENOMEM;
group_pins = pmx->group_pins;
for (fn = 0; fn < pmx->soc->nfunctions; fn++) {
struct tegra_function *func = &pmx->functions[fn];
func->name = pmx->soc->functions[fn];
func->groups = group_pins;
for (gn = 0; gn < pmx->soc->ngroups; gn++) {
const struct tegra_pingroup *g = &pmx->soc->groups[gn];
if (g->mux_reg == -1)
continue;
for (gfn = 0; gfn < 4; gfn++)
if (g->funcs[gfn] == fn)
break;
if (gfn == 4)
continue;
BUG_ON(group_pins - pmx->group_pins >=
pmx->soc->ngroups * 4);
*group_pins++ = g->name;
func->ngroups++;
}
}
pmx->gpio_range.name = "Tegra GPIOs";
pmx->gpio_range.id = 0;
pmx->gpio_range.base = 0;
pmx->gpio_range.npins = pmx->soc->ngpios;
pmx->desc.pctlops = &tegra_pinctrl_ops;
pmx->desc.pmxops = &tegra_pinmux_ops;
pmx->desc.confops = &tegra_pinconf_ops;
pmx->desc.owner = THIS_MODULE;
pmx->desc.name = dev_name(&pdev->dev);
pmx->desc.pins = pmx->soc->pins;
pmx->desc.npins = pmx->soc->npins;
for (i = 0; ; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
break;
backup_regs_size += resource_size(res);
}
pmx->nbanks = i;
pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
GFP_KERNEL);
if (!pmx->regs)
return -ENOMEM;
pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
GFP_KERNEL);
if (!pmx->backup_regs)
return -ENOMEM;
for (i = 0; i < pmx->nbanks; i++) {
pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
if (IS_ERR(pmx->regs[i]))
return PTR_ERR(pmx->regs[i]);
}
pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(pmx->pctl);
}
tegra_pinctrl_clear_parked_bits(pmx);
if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
platform_set_drvdata(pdev, pmx);
dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
return 0;
}
|
linux-master
|
drivers/pinctrl/tegra/pinctrl-tegra.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 TOSHIBA CORPORATION
* Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
* Copyright (c) 2020 Nobuhiro Iwamatsu <[email protected]>
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-common.h"
#define tmpv7700_MAGIC_NUM 0x4932f70e
/* register offset */
#define REG_KEY_CTRL 0x0000
#define REG_KEY_CMD 0x0004
#define REG_PINMUX1 0x3000
#define REG_PINMUX2 0x3004
#define REG_PINMUX3 0x3008
#define REG_PINMUX4 0x300c
#define REG_PINMUX5 0x3010
#define REG_IOSET 0x3014
#define REG_IO_VSEL 0x3018
#define REG_IO_DSEL1 0x301c
#define REG_IO_DSEL2 0x3020
#define REG_IO_DSEL3 0x3024
#define REG_IO_DSEL4 0x3028
#define REG_IO_DSEL5 0x302c
#define REG_IO_DSEL6 0x3030
#define REG_IO_DSEL7 0x3034
#define REG_IO_DSEL8 0x3038
#define REG_IO_PUDE1 0x303c
#define REG_IO_PUDE2 0x3040
#define REG_IO_PUDSEL1 0x3044
#define REG_IO_PUDSEL2 0x3048
/* PIN */
static const struct visconti_desc_pin pins_tmpv7700[] = {
VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24,
REG_IO_PUDE1, REG_IO_PUDSEL1, 30),
VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28,
REG_IO_PUDE1, REG_IO_PUDSEL1, 31),
VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0,
REG_IO_PUDE2, REG_IO_PUDSEL2, 0),
VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4,
REG_IO_PUDE2, REG_IO_PUDSEL2, 1),
VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8,
REG_IO_PUDE2, REG_IO_PUDSEL2, 2),
VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12,
REG_IO_PUDE2, REG_IO_PUDSEL2, 3),
VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16,
REG_IO_PUDE2, REG_IO_PUDSEL2, 4),
VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20,
REG_IO_PUDE2, REG_IO_PUDSEL2, 5),
VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24,
REG_IO_PUDE2, REG_IO_PUDSEL2, 6),
VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28,
REG_IO_PUDE2, REG_IO_PUDSEL2, 7),
VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0,
REG_IO_PUDE2, REG_IO_PUDSEL2, 8),
VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4,
REG_IO_PUDE2, REG_IO_PUDSEL2, 9),
VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8,
REG_IO_PUDE2, REG_IO_PUDSEL2, 10),
VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12,
REG_IO_PUDE2, REG_IO_PUDSEL2, 11),
VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16,
REG_IO_PUDE2, REG_IO_PUDSEL2, 12),
VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20,
REG_IO_PUDE2, REG_IO_PUDSEL2, 13),
VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24,
REG_IO_PUDE2, REG_IO_PUDSEL2, 14),
VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28,
REG_IO_PUDE2, REG_IO_PUDSEL2, 15),
VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0,
REG_IO_PUDE2, REG_IO_PUDSEL2, 16),
VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4,
REG_IO_PUDE2, REG_IO_PUDSEL2, 17),
VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8,
REG_IO_PUDE2, REG_IO_PUDSEL2, 18),
VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12,
REG_IO_PUDE2, REG_IO_PUDSEL2, 19),
VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16,
REG_IO_PUDE2, REG_IO_PUDSEL2, 20),
VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20,
REG_IO_PUDE2, REG_IO_PUDSEL2, 21),
VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24,
REG_IO_PUDE2, REG_IO_PUDSEL2, 22),
VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28,
REG_IO_PUDE2, REG_IO_PUDSEL2, 23),
VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0,
REG_IO_PUDE2, REG_IO_PUDSEL2, 24),
VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4,
REG_IO_PUDE2, REG_IO_PUDSEL2, 25),
VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8,
REG_IO_PUDE2, REG_IO_PUDSEL2, 26),
VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8,
REG_IO_PUDE1, REG_IO_PUDSEL1, 26),
VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4,
REG_IO_PUDE1, REG_IO_PUDSEL1, 25),
VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0,
REG_IO_PUDE1, REG_IO_PUDSEL1, 24),
VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12,
REG_IO_PUDE1, REG_IO_PUDSEL1, 27),
VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16,
REG_IO_PUDE1, REG_IO_PUDSEL1, 28),
VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20,
REG_IO_PUDE1, REG_IO_PUDSEL1, 29),
};
/* Group */
VISCONTI_PINS(i2c0, 0, 1);
VISCONTI_PINS(i2c1, 2, 3);
VISCONTI_PINS(i2c2, 12, 13);
VISCONTI_PINS(i2c3, 14, 15);
VISCONTI_PINS(i2c4, 16, 17);
VISCONTI_PINS(i2c5, 18, 19);
VISCONTI_PINS(i2c6, 33, 34);
VISCONTI_PINS(i2c7, 29, 32);
VISCONTI_PINS(i2c8, 30, 31);
VISCONTI_PINS(spi0_cs0, 29);
VISCONTI_PINS(spi0_cs1, 30);
VISCONTI_PINS(spi0_cs2, 31);
VISCONTI_PINS(spi1_cs, 3);
VISCONTI_PINS(spi2_cs, 7);
VISCONTI_PINS(spi3_cs, 11);
VISCONTI_PINS(spi4_cs, 15);
VISCONTI_PINS(spi5_cs, 19);
VISCONTI_PINS(spi6_cs, 27);
VISCONTI_PINS(spi0, 32, 33, 34);
VISCONTI_PINS(spi1, 0, 1, 2);
VISCONTI_PINS(spi2, 4, 5, 6);
VISCONTI_PINS(spi3, 8, 9, 10);
VISCONTI_PINS(spi4, 12, 13, 14);
VISCONTI_PINS(spi5, 16, 17, 18);
VISCONTI_PINS(spi6, 24, 25, 26);
VISCONTI_PINS(uart0, 4, 5, 6, 7);
VISCONTI_PINS(uart1, 8, 9, 10, 11);
VISCONTI_PINS(uart2, 12, 13, 14, 15);
VISCONTI_PINS(uart3, 16, 17, 18, 19);
VISCONTI_PINS(pwm0_gpio4, 4);
VISCONTI_PINS(pwm1_gpio5, 5);
VISCONTI_PINS(pwm2_gpio6, 6);
VISCONTI_PINS(pwm3_gpio7, 7);
VISCONTI_PINS(pwm0_gpio8, 8);
VISCONTI_PINS(pwm1_gpio9, 9);
VISCONTI_PINS(pwm2_gpio10, 10);
VISCONTI_PINS(pwm3_gpio11, 11);
VISCONTI_PINS(pwm0_gpio12, 12);
VISCONTI_PINS(pwm1_gpio13, 13);
VISCONTI_PINS(pwm2_gpio14, 14);
VISCONTI_PINS(pwm3_gpio15, 15);
VISCONTI_PINS(pwm0_gpio16, 16);
VISCONTI_PINS(pwm1_gpio17, 17);
VISCONTI_PINS(pwm2_gpio18, 18);
VISCONTI_PINS(pwm3_gpio19, 19);
VISCONTI_PINS(pcmif_out, 20, 21, 22);
VISCONTI_PINS(pcmif_in, 24, 25, 26);
static const struct visconti_pin_group groups_tmpv7700[] = {
VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022),
VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200),
VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000),
VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000),
VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077),
VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700),
VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002),
VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000),
VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000),
VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000),
VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000),
VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000),
VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000),
VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000),
VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000),
VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000),
VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000),
VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000),
VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001),
VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111),
VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000),
VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111),
VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000),
VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111),
VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111),
VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000),
VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222),
VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000),
VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222),
VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000),
VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000),
VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000),
VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000),
VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005),
VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050),
VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500),
VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000),
VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000),
VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000),
VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000),
VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000),
VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005),
VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050),
VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500),
VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000),
VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000),
VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222),
};
/* MUX */
VISCONTI_GROUPS(i2c0, "i2c0_grp");
VISCONTI_GROUPS(i2c1, "i2c1_grp");
VISCONTI_GROUPS(i2c2, "i2c2_grp");
VISCONTI_GROUPS(i2c3, "i2c3_grp");
VISCONTI_GROUPS(i2c4, "i2c4_grp");
VISCONTI_GROUPS(i2c5, "i2c5_grp");
VISCONTI_GROUPS(i2c6, "i2c6_grp");
VISCONTI_GROUPS(i2c7, "i2c7_grp");
VISCONTI_GROUPS(i2c8, "i2c8_grp");
VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp",
"spi0_cs1_grp", "spi0_cs2_grp");
VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp");
VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp");
VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp");
VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp");
VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp");
VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp");
VISCONTI_GROUPS(uart0, "uart0_grp");
VISCONTI_GROUPS(uart1, "uart1_grp");
VISCONTI_GROUPS(uart2, "uart2_grp");
VISCONTI_GROUPS(uart3, "uart3_grp");
VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp",
"pwm0_gpio12_grp", "pwm0_gpio16_grp",
"pwm1_gpio5_grp", "pwm1_gpio9_grp",
"pwm1_gpio13_grp", "pwm1_gpio17_grp",
"pwm2_gpio6_grp", "pwm2_gpio10_grp",
"pwm2_gpio14_grp", "pwm2_gpio18_grp",
"pwm3_gpio7_grp", "pwm3_gpio11_grp",
"pwm3_gpio15_grp", "pwm3_gpio19_grp");
VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp");
VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp");
static const struct visconti_pin_function functions_tmpv7700[] = {
VISCONTI_PIN_FUNCTION(i2c0),
VISCONTI_PIN_FUNCTION(i2c1),
VISCONTI_PIN_FUNCTION(i2c2),
VISCONTI_PIN_FUNCTION(i2c3),
VISCONTI_PIN_FUNCTION(i2c4),
VISCONTI_PIN_FUNCTION(i2c5),
VISCONTI_PIN_FUNCTION(i2c6),
VISCONTI_PIN_FUNCTION(i2c7),
VISCONTI_PIN_FUNCTION(i2c8),
VISCONTI_PIN_FUNCTION(spi0),
VISCONTI_PIN_FUNCTION(spi1),
VISCONTI_PIN_FUNCTION(spi2),
VISCONTI_PIN_FUNCTION(spi3),
VISCONTI_PIN_FUNCTION(spi4),
VISCONTI_PIN_FUNCTION(spi5),
VISCONTI_PIN_FUNCTION(spi6),
VISCONTI_PIN_FUNCTION(uart0),
VISCONTI_PIN_FUNCTION(uart1),
VISCONTI_PIN_FUNCTION(uart2),
VISCONTI_PIN_FUNCTION(uart3),
VISCONTI_PIN_FUNCTION(pwm),
VISCONTI_PIN_FUNCTION(pcmif_in),
VISCONTI_PIN_FUNCTION(pcmif_out),
};
/* GPIO MUX */
#define tmpv7700_GPIO_MUX(off, msk) \
{ \
.offset = off, \
.mask = msk, \
.val = 0, \
}
static const struct visconti_mux gpio_mux_tmpv7700[] = {
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)),
tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)),
tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)),
tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)),
tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)),
};
static void tmpv7700_pinctrl_unlock(void __iomem *base)
{
writel(1, base + REG_KEY_CTRL);
writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD);
}
/* chip dependent data */
static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = {
.pins = pins_tmpv7700,
.nr_pins = ARRAY_SIZE(pins_tmpv7700),
.groups = groups_tmpv7700,
.nr_groups = ARRAY_SIZE(groups_tmpv7700),
.functions = functions_tmpv7700,
.nr_functions = ARRAY_SIZE(functions_tmpv7700),
.gpio_mux = gpio_mux_tmpv7700,
.unlock = tmpv7700_pinctrl_unlock,
};
static int tmpv7700_pinctrl_probe(struct platform_device *pdev)
{
return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data);
}
static const struct of_device_id tmpv7700_pctrl_of_match[] = {
{ .compatible = "toshiba,tmpv7708-pinctrl", },
{},
};
static struct platform_driver tmpv7700_pinctrl_driver = {
.probe = tmpv7700_pinctrl_probe,
.driver = {
.name = "tmpv7700-pinctrl",
.of_match_table = tmpv7700_pctrl_of_match,
},
};
static int __init tmpv7700_pinctrl_init(void)
{
return platform_driver_register(&tmpv7700_pinctrl_driver);
}
arch_initcall(tmpv7700_pinctrl_init);
|
linux-master
|
drivers/pinctrl/visconti/pinctrl-tmpv7700.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 TOSHIBA CORPORATION
* Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
* Copyright (c) 2020 Nobuhiro Iwamatsu <[email protected]>
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-common.h"
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#define DSEL_MASK GENMASK(3, 0)
/* private data */
struct visconti_pinctrl {
void __iomem *base;
struct device *dev;
struct pinctrl_dev *pctl;
struct pinctrl_desc pctl_desc;
const struct visconti_pinctrl_devdata *devdata;
spinlock_t lock; /* protect pinctrl register */
};
/* pinconf */
static int visconti_pin_config_set(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *configs,
unsigned int num_configs)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin];
enum pin_config_param param;
unsigned int arg;
int i, ret = 0;
unsigned int val, set_val, pude_val;
unsigned long flags;
dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name);
spin_lock_irqsave(&priv->lock, flags);
for (i = 0; i < num_configs; i++) {
set_val = 0;
pude_val = 0;
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
set_val = 1;
fallthrough;
case PIN_CONFIG_BIAS_PULL_DOWN:
/* update pudsel setting */
val = readl(priv->base + pin->pudsel_offset);
val &= ~BIT(pin->pud_shift);
val |= set_val << pin->pud_shift;
writel(val, priv->base + pin->pudsel_offset);
pude_val = 1;
fallthrough;
case PIN_CONFIG_BIAS_DISABLE:
/* update pude setting */
val = readl(priv->base + pin->pude_offset);
val &= ~BIT(pin->pud_shift);
val |= pude_val << pin->pud_shift;
writel(val, priv->base + pin->pude_offset);
dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n",
param, pin->pude_offset, val);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = pinconf_to_config_argument(configs[i]);
dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg);
switch (arg) {
case 2:
case 4:
case 8:
case 16:
case 24:
case 32:
/*
* I/O drive capacity setting:
* 2mA: 0
* 4mA: 1
* 8mA: 3
* 16mA: 7
* 24mA: 11
* 32mA: 15
*/
set_val = DIV_ROUND_CLOSEST(arg, 2) - 1;
break;
default:
ret = -EINVAL;
goto err;
}
/* update drive setting */
val = readl(priv->base + pin->dsel_offset);
val &= ~(DSEL_MASK << pin->dsel_shift);
val |= set_val << pin->dsel_shift;
writel(val, priv->base + pin->dsel_offset);
break;
default:
ret = -EOPNOTSUPP;
goto err;
}
}
err:
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins;
unsigned int num_pins;
int i, ret;
pins = priv->devdata->groups[selector].pins;
num_pins = priv->devdata->groups[selector].nr_pins;
dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n",
__func__, selector, num_pins, num_configs);
for (i = 0; i < num_pins; i++) {
ret = visconti_pin_config_set(pctldev, pins[i],
configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops visconti_pinconf_ops = {
.is_generic = true,
.pin_config_set = visconti_pin_config_set,
.pin_config_group_set = visconti_pin_config_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
/* pinctrl */
static int visconti_get_groups_count(struct pinctrl_dev *pctldev)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->devdata->nr_groups;
}
static const char *visconti_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->devdata->groups[selector].name;
}
static int visconti_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
*pins = priv->devdata->groups[selector].pins;
*num_pins = priv->devdata->groups[selector].nr_pins;
return 0;
}
static const struct pinctrl_ops visconti_pinctrl_ops = {
.get_groups_count = visconti_get_groups_count,
.get_group_name = visconti_get_group_name,
.get_group_pins = visconti_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
};
/* pinmux */
static int visconti_get_functions_count(struct pinctrl_dev *pctldev)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->devdata->nr_functions;
}
static const char *visconti_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
return priv->devdata->functions[selector].name;
}
static int visconti_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
*groups = priv->devdata->functions[selector].groups;
*num_groups = priv->devdata->functions[selector].nr_groups;
return 0;
}
static int visconti_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
const struct visconti_pin_function *func = &priv->devdata->functions[function];
const struct visconti_pin_group *grp = &priv->devdata->groups[group];
const struct visconti_mux *mux = &grp->mux;
unsigned int val;
unsigned long flags;
dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__,
function, func->name, group, grp->name);
spin_lock_irqsave(&priv->lock, flags);
/* update mux */
val = readl(priv->base + mux->offset);
val &= ~mux->mask;
val |= mux->val;
writel(val, priv->base + mux->offset);
spin_unlock_irqrestore(&priv->lock, flags);
dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val);
return 0;
}
static int visconti_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
const struct visconti_mux *gpio_mux = &priv->devdata->gpio_mux[pin];
unsigned long flags;
unsigned int val;
dev_dbg(priv->dev, "%s: pin = %d\n", __func__, pin);
/* update mux */
spin_lock_irqsave(&priv->lock, flags);
val = readl(priv->base + gpio_mux->offset);
val &= ~gpio_mux->mask;
val |= gpio_mux->val;
writel(val, priv->base + gpio_mux->offset);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static const struct pinmux_ops visconti_pinmux_ops = {
.get_functions_count = visconti_get_functions_count,
.get_function_name = visconti_get_function_name,
.get_function_groups = visconti_get_function_groups,
.set_mux = visconti_set_mux,
.gpio_request_enable = visconti_gpio_request_enable,
.strict = true,
};
int visconti_pinctrl_probe(struct platform_device *pdev,
const struct visconti_pinctrl_devdata *devdata)
{
struct device *dev = &pdev->dev;
struct visconti_pinctrl *priv;
struct pinctrl_pin_desc *pins;
int i, ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->devdata = devdata;
spin_lock_init(&priv->lock);
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base)) {
dev_err(dev, "unable to map I/O space\n");
return PTR_ERR(priv->base);
}
pins = devm_kcalloc(dev, devdata->nr_pins,
sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < devdata->nr_pins; i++)
pins[i] = devdata->pins[i].pin;
priv->pctl_desc.name = dev_name(dev);
priv->pctl_desc.owner = THIS_MODULE;
priv->pctl_desc.pins = pins;
priv->pctl_desc.npins = devdata->nr_pins;
priv->pctl_desc.confops = &visconti_pinconf_ops;
priv->pctl_desc.pctlops = &visconti_pinctrl_ops;
priv->pctl_desc.pmxops = &visconti_pinmux_ops;
ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc,
priv, &priv->pctl);
if (ret) {
dev_err(dev, "couldn't register pinctrl: %d\n", ret);
return ret;
}
if (devdata->unlock)
devdata->unlock(priv->base);
return pinctrl_enable(priv->pctl);
}
|
linux-master
|
drivers/pinctrl/visconti/pinctrl-common.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pin controller and GPIO driver for Amlogic Meson SoCs
*
* Copyright (C) 2014 Beniamino Galvani <[email protected]>
*/
/*
* The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
* BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
* X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
* variable number of pins.
*
* The AO bank is special because it belongs to the Always-On power
* domain which can't be powered off; the bank also uses a set of
* registers different from the other banks.
*
* For each pin controller there are 4 different register ranges that
* control the following properties of the pins:
* 1) pin muxing
* 2) pull enable/disable
* 3) pull up/down
* 4) GPIO direction, output value, input value
*
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
* Since Meson G12A SoC, the ao register ranges for gpio, pull enable
* and pull direction are the same, so there are only 2 register ranges.
*
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
*
* In addition to this there are some registers shared between all
* banks that control the IRQ functionality. This feature is not
* supported at the moment by the driver.
*/
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-meson.h"
static const unsigned int meson_bit_strides[] = {
1, 1, 1, 1, 1, 2, 1
};
/**
* meson_get_bank() - find the bank containing a given pin
*
* @pc: the pinctrl instance
* @pin: the pin number
* @bank: the found bank
*
* Return: 0 on success, a negative value on error
*/
static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
struct meson_bank **bank)
{
int i;
for (i = 0; i < pc->data->num_banks; i++) {
if (pin >= pc->data->banks[i].first &&
pin <= pc->data->banks[i].last) {
*bank = &pc->data->banks[i];
return 0;
}
}
return -EINVAL;
}
/**
* meson_calc_reg_and_bit() - calculate register and bit for a pin
*
* @bank: the bank containing the pin
* @pin: the pin number
* @reg_type: the type of register needed (pull-enable, pull, etc...)
* @reg: the computed register offset
* @bit: the computed bit
*/
static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
enum meson_reg_type reg_type,
unsigned int *reg, unsigned int *bit)
{
struct meson_reg_desc *desc = &bank->regs[reg_type];
*bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
*reg = (desc->reg + (*bit / 32)) * 4;
*bit &= 0x1f;
}
static int meson_get_groups_count(struct pinctrl_dev *pcdev)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
return pc->data->num_groups;
}
static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
unsigned selector)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
return pc->data->groups[selector].name;
}
static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
const unsigned **pins, unsigned *num_pins)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
*pins = pc->data->groups[selector].pins;
*num_pins = pc->data->groups[selector].num_pins;
return 0;
}
static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pcdev->dev));
}
static const struct pinctrl_ops meson_pctrl_ops = {
.get_groups_count = meson_get_groups_count,
.get_group_name = meson_get_group_name,
.get_group_pins = meson_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
.pin_dbg_show = meson_pin_dbg_show,
};
int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
return pc->data->num_funcs;
}
EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count);
const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
unsigned selector)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
return pc->data->funcs[selector].name;
}
EXPORT_SYMBOL_GPL(meson_pmx_get_func_name);
int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
*groups = pc->data->funcs[selector].groups;
*num_groups = pc->data->funcs[selector].num_groups;
return 0;
}
EXPORT_SYMBOL_GPL(meson_pmx_get_groups);
static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
unsigned int pin,
unsigned int reg_type,
bool arg)
{
struct meson_bank *bank;
unsigned int reg, bit;
int ret;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit);
return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
arg ? BIT(bit) : 0);
}
static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
unsigned int pin,
unsigned int reg_type)
{
struct meson_bank *bank;
unsigned int reg, bit, val;
int ret;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit);
ret = regmap_read(pc->reg_gpio, reg, &val);
if (ret)
return ret;
return BIT(bit) & val ? 1 : 0;
}
static int meson_pinconf_set_output(struct meson_pinctrl *pc,
unsigned int pin,
bool out)
{
return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_DIR, !out);
}
static int meson_pinconf_get_output(struct meson_pinctrl *pc,
unsigned int pin)
{
int ret = meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_DIR);
if (ret < 0)
return ret;
return !ret;
}
static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
unsigned int pin,
bool high)
{
return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high);
}
static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
unsigned int pin)
{
return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT);
}
static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
unsigned int pin,
bool high)
{
int ret;
ret = meson_pinconf_set_output(pc, pin, true);
if (ret)
return ret;
return meson_pinconf_set_drive(pc, pin, high);
}
static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
unsigned int pin)
{
struct meson_bank *bank;
unsigned int reg, bit = 0;
int ret;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit);
ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
if (ret)
return ret;
return 0;
}
static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
bool pull_up)
{
struct meson_bank *bank;
unsigned int reg, bit, val = 0;
int ret;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit);
if (pull_up)
val = BIT(bit);
ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit);
ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
if (ret)
return ret;
return 0;
}
static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
unsigned int pin,
u16 drive_strength_ua)
{
struct meson_bank *bank;
unsigned int reg, bit, ds_val;
int ret;
if (!pc->reg_ds) {
dev_err(pc->dev, "drive-strength not supported\n");
return -ENOTSUPP;
}
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit);
if (drive_strength_ua <= 500) {
ds_val = MESON_PINCONF_DRV_500UA;
} else if (drive_strength_ua <= 2500) {
ds_val = MESON_PINCONF_DRV_2500UA;
} else if (drive_strength_ua <= 3000) {
ds_val = MESON_PINCONF_DRV_3000UA;
} else if (drive_strength_ua <= 4000) {
ds_val = MESON_PINCONF_DRV_4000UA;
} else {
dev_warn_once(pc->dev,
"pin %u: invalid drive-strength : %d , default to 4mA\n",
pin, drive_strength_ua);
ds_val = MESON_PINCONF_DRV_4000UA;
}
ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
if (ret)
return ret;
return 0;
}
static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
unsigned long *configs, unsigned num_configs)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
enum pin_config_param param;
unsigned int arg = 0;
int i, ret;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH_UA:
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_OUTPUT:
arg = pinconf_to_config_argument(configs[i]);
break;
default:
break;
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = meson_pinconf_disable_bias(pc, pin);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = meson_pinconf_enable_bias(pc, pin, true);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = meson_pinconf_enable_bias(pc, pin, false);
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
ret = meson_pinconf_set_drive_strength(pc, pin, arg);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
ret = meson_pinconf_set_output(pc, pin, arg);
break;
case PIN_CONFIG_OUTPUT:
ret = meson_pinconf_set_output_drive(pc, pin, arg);
break;
default:
ret = -ENOTSUPP;
}
if (ret)
return ret;
}
return 0;
}
static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
{
struct meson_bank *bank;
unsigned int reg, bit, val;
int ret, conf;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, ®, &bit);
ret = regmap_read(pc->reg_pullen, reg, &val);
if (ret)
return ret;
if (!(val & BIT(bit))) {
conf = PIN_CONFIG_BIAS_DISABLE;
} else {
meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, ®, &bit);
ret = regmap_read(pc->reg_pull, reg, &val);
if (ret)
return ret;
if (val & BIT(bit))
conf = PIN_CONFIG_BIAS_PULL_UP;
else
conf = PIN_CONFIG_BIAS_PULL_DOWN;
}
return conf;
}
static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
unsigned int pin,
u16 *drive_strength_ua)
{
struct meson_bank *bank;
unsigned int reg, bit;
unsigned int val;
int ret;
if (!pc->reg_ds)
return -ENOTSUPP;
ret = meson_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, ®, &bit);
ret = regmap_read(pc->reg_ds, reg, &val);
if (ret)
return ret;
switch ((val >> bit) & 0x3) {
case MESON_PINCONF_DRV_500UA:
*drive_strength_ua = 500;
break;
case MESON_PINCONF_DRV_2500UA:
*drive_strength_ua = 2500;
break;
case MESON_PINCONF_DRV_3000UA:
*drive_strength_ua = 3000;
break;
case MESON_PINCONF_DRV_4000UA:
*drive_strength_ua = 4000;
break;
default:
return -EINVAL;
}
return 0;
}
static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
unsigned long *config)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
enum pin_config_param param = pinconf_to_config_param(*config);
u16 arg;
int ret;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
if (meson_pinconf_get_pull(pc, pin) == param)
arg = 1;
else
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
if (ret)
return ret;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
ret = meson_pinconf_get_output(pc, pin);
if (ret <= 0)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_OUTPUT:
ret = meson_pinconf_get_output(pc, pin);
if (ret <= 0)
return -EINVAL;
ret = meson_pinconf_get_drive(pc, pin);
if (ret < 0)
return -EINVAL;
arg = ret;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
return 0;
}
static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
unsigned int num_group,
unsigned long *configs, unsigned num_configs)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_group *group = &pc->data->groups[num_group];
int i;
dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
for (i = 0; i < group->num_pins; i++) {
meson_pinconf_set(pcdev, group->pins[i], configs,
num_configs);
}
return 0;
}
static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
unsigned int group, unsigned long *config)
{
return -ENOTSUPP;
}
static const struct pinconf_ops meson_pinconf_ops = {
.pin_config_get = meson_pinconf_get,
.pin_config_set = meson_pinconf_set,
.pin_config_group_get = meson_pinconf_group_get,
.pin_config_group_set = meson_pinconf_group_set,
.is_generic = true,
};
static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
{
struct meson_pinctrl *pc = gpiochip_get_data(chip);
int ret;
ret = meson_pinconf_get_output(pc, gpio);
if (ret < 0)
return ret;
return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
}
static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
}
static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
int value)
{
return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
gpio, value);
}
static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
{
meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
}
static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
struct meson_pinctrl *pc = gpiochip_get_data(chip);
unsigned int reg, bit, val;
struct meson_bank *bank;
int ret;
ret = meson_get_bank(pc, gpio, &bank);
if (ret)
return ret;
meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, ®, &bit);
regmap_read(pc->reg_gpio, reg, &val);
return !!(val & BIT(bit));
}
static int meson_gpiolib_register(struct meson_pinctrl *pc)
{
int ret;
pc->chip.label = pc->data->name;
pc->chip.parent = pc->dev;
pc->chip.fwnode = pc->fwnode;
pc->chip.request = gpiochip_generic_request;
pc->chip.free = gpiochip_generic_free;
pc->chip.set_config = gpiochip_generic_config;
pc->chip.get_direction = meson_gpio_get_direction;
pc->chip.direction_input = meson_gpio_direction_input;
pc->chip.direction_output = meson_gpio_direction_output;
pc->chip.get = meson_gpio_get;
pc->chip.set = meson_gpio_set;
pc->chip.base = -1;
pc->chip.ngpio = pc->data->num_pins;
pc->chip.can_sleep = false;
ret = gpiochip_add_data(&pc->chip, pc);
if (ret) {
dev_err(pc->dev, "can't add gpio chip %s\n",
pc->data->name);
return ret;
}
return 0;
}
static struct regmap_config meson_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
struct device_node *node, char *name)
{
struct resource res;
void __iomem *base;
int i;
i = of_property_match_string(node, "reg-names", name);
if (of_address_to_resource(node, i, &res))
return NULL;
base = devm_ioremap_resource(pc->dev, &res);
if (IS_ERR(base))
return ERR_CAST(base);
meson_regmap_config.max_register = resource_size(&res) - 4;
meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
"%pOFn-%s", node,
name);
if (!meson_regmap_config.name)
return ERR_PTR(-ENOMEM);
return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
}
static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
{
struct device_node *gpio_np;
unsigned int chips;
chips = gpiochip_node_count(pc->dev);
if (!chips) {
dev_err(pc->dev, "no gpio node found\n");
return -EINVAL;
}
if (chips > 1) {
dev_err(pc->dev, "multiple gpio nodes\n");
return -EINVAL;
}
pc->fwnode = gpiochip_node_get_first(pc->dev);
gpio_np = to_of_node(pc->fwnode);
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
if (IS_ERR_OR_NULL(pc->reg_mux)) {
dev_err(pc->dev, "mux registers not found\n");
return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT;
}
pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
if (IS_ERR_OR_NULL(pc->reg_gpio)) {
dev_err(pc->dev, "gpio registers not found\n");
return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT;
}
pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
if (IS_ERR(pc->reg_pull))
pc->reg_pull = NULL;
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = NULL;
pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
if (IS_ERR(pc->reg_ds)) {
dev_dbg(pc->dev, "ds registers not found - skipping\n");
pc->reg_ds = NULL;
}
if (pc->data->parse_dt)
return pc->data->parse_dt(pc);
return 0;
}
int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
{
if (!pc->reg_pull)
return -EINVAL;
pc->reg_pullen = pc->reg_pull;
return 0;
}
EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra);
int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
{
pc->reg_pull = pc->reg_gpio;
pc->reg_pullen = pc->reg_gpio;
pc->reg_ds = pc->reg_gpio;
return 0;
}
EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra);
int meson_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct meson_pinctrl *pc;
int ret;
pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
if (!pc)
return -ENOMEM;
pc->dev = dev;
pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
ret = meson_pinctrl_parse_dt(pc);
if (ret)
return ret;
pc->desc.name = "pinctrl-meson";
pc->desc.owner = THIS_MODULE;
pc->desc.pctlops = &meson_pctrl_ops;
pc->desc.pmxops = pc->data->pmx_ops;
pc->desc.confops = &meson_pinconf_ops;
pc->desc.pins = pc->data->pins;
pc->desc.npins = pc->data->num_pins;
pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
if (IS_ERR(pc->pcdev)) {
dev_err(pc->dev, "can't register pinctrl device");
return PTR_ERR(pc->pcdev);
}
return meson_gpiolib_register(pc);
}
EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson.c
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Pin controller and GPIO driver for Amlogic Meson AXG SoC.
*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <[email protected]>
*/
#include <dt-bindings/gpio/meson-axg-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static const struct pinctrl_pin_desc meson_axg_periphs_pins[] = {
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(GPIOA_0),
MESON_PIN(GPIOA_1),
MESON_PIN(GPIOA_2),
MESON_PIN(GPIOA_3),
MESON_PIN(GPIOA_4),
MESON_PIN(GPIOA_5),
MESON_PIN(GPIOA_6),
MESON_PIN(GPIOA_7),
MESON_PIN(GPIOA_8),
MESON_PIN(GPIOA_9),
MESON_PIN(GPIOA_10),
MESON_PIN(GPIOA_11),
MESON_PIN(GPIOA_12),
MESON_PIN(GPIOA_13),
MESON_PIN(GPIOA_14),
MESON_PIN(GPIOA_15),
MESON_PIN(GPIOA_16),
MESON_PIN(GPIOA_17),
MESON_PIN(GPIOA_18),
MESON_PIN(GPIOA_19),
MESON_PIN(GPIOA_20),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
MESON_PIN(GPIOX_20),
MESON_PIN(GPIOX_21),
MESON_PIN(GPIOX_22),
MESON_PIN(GPIOY_0),
MESON_PIN(GPIOY_1),
MESON_PIN(GPIOY_2),
MESON_PIN(GPIOY_3),
MESON_PIN(GPIOY_4),
MESON_PIN(GPIOY_5),
MESON_PIN(GPIOY_6),
MESON_PIN(GPIOY_7),
MESON_PIN(GPIOY_8),
MESON_PIN(GPIOY_9),
MESON_PIN(GPIOY_10),
MESON_PIN(GPIOY_11),
MESON_PIN(GPIOY_12),
MESON_PIN(GPIOY_13),
MESON_PIN(GPIOY_14),
MESON_PIN(GPIOY_15),
};
static const struct pinctrl_pin_desc meson_axg_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIOAO_10),
MESON_PIN(GPIOAO_11),
MESON_PIN(GPIOAO_12),
MESON_PIN(GPIOAO_13),
MESON_PIN(GPIO_TEST_N),
};
/* emmc */
static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
static const unsigned int emmc_clk_pins[] = {BOOT_8};
static const unsigned int emmc_cmd_pins[] = {BOOT_10};
static const unsigned int emmc_ds_pins[] = {BOOT_13};
/* nand */
static const unsigned int nand_ce0_pins[] = {BOOT_8};
static const unsigned int nand_ale_pins[] = {BOOT_9};
static const unsigned int nand_cle_pins[] = {BOOT_10};
static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
static const unsigned int nand_rb0_pins[] = {BOOT_13};
/* nor */
static const unsigned int nor_hold_pins[] = {BOOT_3};
static const unsigned int nor_d_pins[] = {BOOT_4};
static const unsigned int nor_q_pins[] = {BOOT_5};
static const unsigned int nor_c_pins[] = {BOOT_6};
static const unsigned int nor_wp_pins[] = {BOOT_9};
static const unsigned int nor_cs_pins[] = {BOOT_14};
/* sdio */
static const unsigned int sdio_d0_pins[] = {GPIOX_0};
static const unsigned int sdio_d1_pins[] = {GPIOX_1};
static const unsigned int sdio_d2_pins[] = {GPIOX_2};
static const unsigned int sdio_d3_pins[] = {GPIOX_3};
static const unsigned int sdio_clk_pins[] = {GPIOX_4};
static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
/* spi0 */
static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
/* spi1 */
static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
/* i2c0 */
static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
/* i2c1 */
static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
/* i2c2 */
static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
/* i2c3 */
static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
/* uart_a */
static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
/* uart_b */
static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
/* uart_ao_b */
static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
/* pwm_a */
static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
/* pwm_b */
static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
/* pwm_c */
static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
/* pwm_d */
static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
/* pwm_vs */
static const unsigned int pwm_vs_pins[] = {GPIOA_0};
/* spdif_in */
static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
/* spdif_out */
static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
/* jtag_ee */
static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
/* eth */
static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
/* pdm */
static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
static const unsigned int pdm_din0_pins[] = {GPIOA_15};
static const unsigned int pdm_din1_pins[] = {GPIOA_16};
static const unsigned int pdm_din2_pins[] = {GPIOA_17};
static const unsigned int pdm_din3_pins[] = {GPIOA_18};
/* mclk */
static const unsigned int mclk_c_pins[] = {GPIOA_0};
static const unsigned int mclk_b_pins[] = {GPIOA_1};
/* tdm */
static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
static const unsigned int tdma_fs_pins[] = {GPIOX_13};
static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
static const unsigned int tdma_din0_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
static const unsigned int tdma_din1_pins[] = {GPIOX_15};
static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
static struct meson_pmx_group meson_axg_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(GPIOA_0),
GPIO_GROUP(GPIOA_1),
GPIO_GROUP(GPIOA_2),
GPIO_GROUP(GPIOA_3),
GPIO_GROUP(GPIOA_4),
GPIO_GROUP(GPIOA_5),
GPIO_GROUP(GPIOA_6),
GPIO_GROUP(GPIOA_7),
GPIO_GROUP(GPIOA_8),
GPIO_GROUP(GPIOA_9),
GPIO_GROUP(GPIOA_10),
GPIO_GROUP(GPIOA_11),
GPIO_GROUP(GPIOA_12),
GPIO_GROUP(GPIOA_13),
GPIO_GROUP(GPIOA_14),
GPIO_GROUP(GPIOA_15),
GPIO_GROUP(GPIOA_16),
GPIO_GROUP(GPIOA_17),
GPIO_GROUP(GPIOA_18),
GPIO_GROUP(GPIOA_19),
GPIO_GROUP(GPIOA_20),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
GPIO_GROUP(GPIOX_20),
GPIO_GROUP(GPIOX_21),
GPIO_GROUP(GPIOX_22),
GPIO_GROUP(GPIOY_0),
GPIO_GROUP(GPIOY_1),
GPIO_GROUP(GPIOY_2),
GPIO_GROUP(GPIOY_3),
GPIO_GROUP(GPIOY_4),
GPIO_GROUP(GPIOY_5),
GPIO_GROUP(GPIOY_6),
GPIO_GROUP(GPIOY_7),
GPIO_GROUP(GPIOY_8),
GPIO_GROUP(GPIOY_9),
GPIO_GROUP(GPIOY_10),
GPIO_GROUP(GPIOY_11),
GPIO_GROUP(GPIOY_12),
GPIO_GROUP(GPIOY_13),
GPIO_GROUP(GPIOY_14),
GPIO_GROUP(GPIOY_15),
/* bank BOOT */
GROUP(emmc_nand_d0, 1),
GROUP(emmc_nand_d1, 1),
GROUP(emmc_nand_d2, 1),
GROUP(emmc_nand_d3, 1),
GROUP(emmc_nand_d4, 1),
GROUP(emmc_nand_d5, 1),
GROUP(emmc_nand_d6, 1),
GROUP(emmc_nand_d7, 1),
GROUP(emmc_clk, 1),
GROUP(emmc_cmd, 1),
GROUP(emmc_ds, 1),
GROUP(nand_ce0, 2),
GROUP(nand_ale, 2),
GROUP(nand_cle, 2),
GROUP(nand_wen_clk, 2),
GROUP(nand_ren_wr, 2),
GROUP(nand_rb0, 2),
GROUP(nor_hold, 3),
GROUP(nor_d, 3),
GROUP(nor_q, 3),
GROUP(nor_c, 3),
GROUP(nor_wp, 3),
GROUP(nor_cs, 3),
/* bank GPIOZ */
GROUP(spi0_clk, 1),
GROUP(spi0_mosi, 1),
GROUP(spi0_miso, 1),
GROUP(spi0_ss0, 1),
GROUP(spi0_ss1, 1),
GROUP(spi0_ss2, 1),
GROUP(i2c0_sck, 1),
GROUP(i2c0_sda, 1),
GROUP(i2c1_sck_z, 1),
GROUP(i2c1_sda_z, 1),
GROUP(uart_rts_b_z, 2),
GROUP(uart_cts_b_z, 2),
GROUP(uart_tx_b_z, 2),
GROUP(uart_rx_b_z, 2),
GROUP(pwm_a_z, 2),
GROUP(pwm_b_z, 2),
GROUP(spdif_in_z, 3),
GROUP(spdif_out_z, 3),
GROUP(uart_ao_tx_b_z, 2),
GROUP(uart_ao_rx_b_z, 2),
GROUP(uart_ao_cts_b_z, 2),
GROUP(uart_ao_rts_b_z, 2),
/* bank GPIOX */
GROUP(sdio_d0, 1),
GROUP(sdio_d1, 1),
GROUP(sdio_d2, 1),
GROUP(sdio_d3, 1),
GROUP(sdio_clk, 1),
GROUP(sdio_cmd, 1),
GROUP(i2c1_sck_x, 1),
GROUP(i2c1_sda_x, 1),
GROUP(i2c2_sck_x, 1),
GROUP(i2c2_sda_x, 1),
GROUP(uart_rts_a, 1),
GROUP(uart_cts_a, 1),
GROUP(uart_tx_a, 1),
GROUP(uart_rx_a, 1),
GROUP(uart_rts_b_x, 2),
GROUP(uart_cts_b_x, 2),
GROUP(uart_tx_b_x, 2),
GROUP(uart_rx_b_x, 2),
GROUP(jtag_tdo_x, 2),
GROUP(jtag_tdi_x, 2),
GROUP(jtag_clk_x, 2),
GROUP(jtag_tms_x, 2),
GROUP(spi1_clk_x, 4),
GROUP(spi1_mosi_x, 4),
GROUP(spi1_miso_x, 4),
GROUP(spi1_ss0_x, 4),
GROUP(pwm_a_x18, 3),
GROUP(pwm_a_x20, 1),
GROUP(pwm_b_x, 3),
GROUP(pwm_c_x10, 3),
GROUP(pwm_c_x17, 3),
GROUP(pwm_d_x11, 3),
GROUP(pwm_d_x16, 3),
GROUP(eth_txd0_x, 4),
GROUP(eth_txd1_x, 4),
GROUP(eth_txen_x, 4),
GROUP(eth_rgmii_rx_clk_x, 4),
GROUP(eth_rxd0_x, 4),
GROUP(eth_rxd1_x, 4),
GROUP(eth_rx_dv_x, 4),
GROUP(eth_mdio_x, 4),
GROUP(eth_mdc_x, 4),
GROUP(tdma_sclk, 1),
GROUP(tdma_sclk_slv, 2),
GROUP(tdma_fs, 1),
GROUP(tdma_fs_slv, 2),
GROUP(tdma_din0, 1),
GROUP(tdma_dout0_x14, 2),
GROUP(tdma_dout0_x15, 1),
GROUP(tdma_dout1, 2),
GROUP(tdma_din1, 3),
/* bank GPIOY */
GROUP(eth_txd0_y, 1),
GROUP(eth_txd1_y, 1),
GROUP(eth_txen_y, 1),
GROUP(eth_rgmii_rx_clk_y, 1),
GROUP(eth_rxd0_y, 1),
GROUP(eth_rxd1_y, 1),
GROUP(eth_rx_dv_y, 1),
GROUP(eth_mdio_y, 1),
GROUP(eth_mdc_y, 1),
GROUP(eth_rxd2_rgmii, 1),
GROUP(eth_rxd3_rgmii, 1),
GROUP(eth_rgmii_tx_clk, 1),
GROUP(eth_txd2_rgmii, 1),
GROUP(eth_txd3_rgmii, 1),
/* bank GPIOA */
GROUP(spdif_out_a1, 4),
GROUP(spdif_out_a11, 3),
GROUP(spdif_out_a19, 2),
GROUP(spdif_out_a20, 1),
GROUP(spdif_in_a1, 3),
GROUP(spdif_in_a7, 3),
GROUP(spdif_in_a19, 1),
GROUP(spdif_in_a20, 2),
GROUP(spi1_clk_a, 3),
GROUP(spi1_mosi_a, 3),
GROUP(spi1_miso_a, 3),
GROUP(spi1_ss0_a, 3),
GROUP(spi1_ss1, 3),
GROUP(pwm_a_a, 3),
GROUP(pwm_b_a, 3),
GROUP(pwm_c_a, 3),
GROUP(pwm_vs, 2),
GROUP(i2c2_sda_a, 3),
GROUP(i2c2_sck_a, 3),
GROUP(i2c3_sda_a6, 4),
GROUP(i2c3_sck_a7, 4),
GROUP(i2c3_sda_a12, 4),
GROUP(i2c3_sck_a13, 4),
GROUP(i2c3_sda_a19, 4),
GROUP(i2c3_sck_a20, 4),
GROUP(pdm_dclk_a14, 1),
GROUP(pdm_dclk_a19, 3),
GROUP(pdm_din0, 1),
GROUP(pdm_din1, 1),
GROUP(pdm_din2, 1),
GROUP(pdm_din3, 1),
GROUP(mclk_c, 1),
GROUP(mclk_b, 1),
GROUP(tdmc_sclk, 1),
GROUP(tdmc_sclk_slv, 2),
GROUP(tdmc_fs, 1),
GROUP(tdmc_fs_slv, 2),
GROUP(tdmc_din0, 2),
GROUP(tdmc_dout0, 1),
GROUP(tdmc_din1, 2),
GROUP(tdmc_dout1, 1),
GROUP(tdmc_din2, 2),
GROUP(tdmc_dout2, 1),
GROUP(tdmc_din3, 2),
GROUP(tdmc_dout3, 1),
GROUP(tdmb_sclk, 1),
GROUP(tdmb_sclk_slv, 2),
GROUP(tdmb_fs, 1),
GROUP(tdmb_fs_slv, 2),
GROUP(tdmb_din0, 2),
GROUP(tdmb_dout0, 1),
GROUP(tdmb_din1, 2),
GROUP(tdmb_dout1, 1),
GROUP(tdmb_din2, 2),
GROUP(tdmb_dout2, 1),
GROUP(tdmb_din3, 2),
GROUP(tdmb_dout3, 1),
};
/* uart_ao_a */
static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
/* uart_ao_b */
static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
/* i2c_ao */
static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
/* i2c_ao_slave */
static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
/* ir_in */
static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
/* ir_out */
static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
/* pwm_ao_a */
static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
/* pwm_ao_b */
static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
/* pwm_ao_c */
static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
/* pwm_ao_d */
static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
/* jtag_ao */
static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
/* gen_clk */
static const unsigned int gen_clk_ee_pins[] = {GPIOAO_13};
static struct meson_pmx_group meson_axg_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
GPIO_GROUP(GPIOAO_10),
GPIO_GROUP(GPIOAO_11),
GPIO_GROUP(GPIOAO_12),
GPIO_GROUP(GPIOAO_13),
GPIO_GROUP(GPIO_TEST_N),
/* bank AO */
GROUP(uart_ao_tx_a, 1),
GROUP(uart_ao_rx_a, 1),
GROUP(uart_ao_cts_a, 2),
GROUP(uart_ao_rts_a, 2),
GROUP(uart_ao_tx_b, 1),
GROUP(uart_ao_rx_b, 1),
GROUP(uart_ao_cts_b, 1),
GROUP(uart_ao_rts_b, 1),
GROUP(i2c_ao_sck_4, 2),
GROUP(i2c_ao_sda_5, 2),
GROUP(i2c_ao_sck_8, 2),
GROUP(i2c_ao_sda_9, 2),
GROUP(i2c_ao_sck_10, 2),
GROUP(i2c_ao_sda_11, 2),
GROUP(i2c_ao_slave_sck, 1),
GROUP(i2c_ao_slave_sda, 1),
GROUP(remote_input_ao, 1),
GROUP(remote_out_ao, 1),
GROUP(pwm_ao_a, 3),
GROUP(pwm_ao_b_ao2, 3),
GROUP(pwm_ao_b_ao12, 3),
GROUP(pwm_ao_c_ao8, 3),
GROUP(pwm_ao_c_ao13, 3),
GROUP(pwm_ao_d, 3),
GROUP(jtag_ao_tdi, 4),
GROUP(jtag_ao_tdo, 4),
GROUP(jtag_ao_clk, 4),
GROUP(jtag_ao_tms, 4),
GROUP(gen_clk_ee, 4),
};
static const char * const gpio_periphs_groups[] = {
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
"GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
"GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
"GPIOA_20",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
"GPIOX_20", "GPIOX_21", "GPIOX_22",
"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
"GPIOY_15",
};
static const char * const emmc_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_cmd", "emmc_ds",
};
static const char * const nand_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"nand_ce0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_wr", "nand_rb0",
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs",
"nor_hold", "nor_wp",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_cmd", "sdio_clk",
};
static const char * const spi0_groups[] = {
"spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
"spi0_ss1", "spi0_ss2"
};
static const char * const spi1_groups[] = {
"spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
"spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
"spi1_ss1"
};
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
static const char * const uart_b_groups[] = {
"uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
};
static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
};
static const char * const i2c0_groups[] = {
"i2c0_sck", "i2c0_sda",
};
static const char * const i2c1_groups[] = {
"i2c1_sck_z", "i2c1_sda_z",
"i2c1_sck_x", "i2c1_sda_x",
};
static const char * const i2c2_groups[] = {
"i2c2_sck_x", "i2c2_sda_x",
"i2c2_sda_a", "i2c2_sck_a",
};
static const char * const i2c3_groups[] = {
"i2c3_sda_a6", "i2c3_sck_a7",
"i2c3_sda_a12", "i2c3_sck_a13",
"i2c3_sda_a19", "i2c3_sck_a20",
};
static const char * const eth_groups[] = {
"eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
"eth_txd2_rgmii", "eth_txd3_rgmii",
"eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
"eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
"eth_mdc_x",
"eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
"eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
"eth_mdc_y",
};
static const char * const pwm_a_groups[] = {
"pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b_z", "pwm_b_x", "pwm_b_a",
};
static const char * const pwm_c_groups[] = {
"pwm_c_x10", "pwm_c_x17", "pwm_c_a",
};
static const char * const pwm_d_groups[] = {
"pwm_d_x11", "pwm_d_x16",
};
static const char * const pwm_vs_groups[] = {
"pwm_vs",
};
static const char * const spdif_out_groups[] = {
"spdif_out_z", "spdif_out_a1", "spdif_out_a11",
"spdif_out_a19", "spdif_out_a20",
};
static const char * const spdif_in_groups[] = {
"spdif_in_z", "spdif_in_a1", "spdif_in_a7",
"spdif_in_a19", "spdif_in_a20",
};
static const char * const jtag_ee_groups[] = {
"jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
"jtag_tms_x",
};
static const char * const pdm_groups[] = {
"pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
"pdm_dclk_a14", "pdm_dclk_a19",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
"GPIO_TEST_N",
};
static const char * const uart_ao_a_groups[] = {
"uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
};
static const char * const uart_ao_b_groups[] = {
"uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
};
static const char * const i2c_ao_groups[] = {
"i2c_ao_sck_4", "i2c_ao_sda_5",
"i2c_ao_sck_8", "i2c_ao_sda_9",
"i2c_ao_sck_10", "i2c_ao_sda_11",
};
static const char * const i2c_ao_slave_groups[] = {
"i2c_ao_slave_sck", "i2c_ao_slave_sda",
};
static const char * const remote_input_ao_groups[] = {
"remote_input_ao",
};
static const char * const remote_out_ao_groups[] = {
"remote_out_ao",
};
static const char * const pwm_ao_a_groups[] = {
"pwm_ao_a",
};
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b_ao2", "pwm_ao_b_ao12",
};
static const char * const pwm_ao_c_groups[] = {
"pwm_ao_c_ao8", "pwm_ao_c_ao13",
};
static const char * const pwm_ao_d_groups[] = {
"pwm_ao_d",
};
static const char * const jtag_ao_groups[] = {
"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
};
static const char * const mclk_c_groups[] = {
"mclk_c",
};
static const char * const mclk_b_groups[] = {
"mclk_b",
};
static const char * const tdma_groups[] = {
"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
"tdma_din1",
};
static const char * const tdmc_groups[] = {
"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
"tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1",
"tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3",
};
static const char * const tdmb_groups[] = {
"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
"tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1",
"tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3",
};
static const char * const gen_clk_ee_groups[] = {
"gen_clk_ee",
};
static struct meson_pmx_func meson_axg_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(spi0),
FUNCTION(spi1),
FUNCTION(sdio),
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_ao_b_z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(eth),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_vs),
FUNCTION(spdif_out),
FUNCTION(spdif_in),
FUNCTION(jtag_ee),
FUNCTION(pdm),
FUNCTION(mclk_b),
FUNCTION(mclk_c),
FUNCTION(tdma),
FUNCTION(tdmb),
FUNCTION(tdmc),
};
static struct meson_pmx_func meson_axg_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao_a),
FUNCTION(uart_ao_b),
FUNCTION(i2c_ao),
FUNCTION(i2c_ao_slave),
FUNCTION(remote_input_ao),
FUNCTION(remote_out_ao),
FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
FUNCTION(pwm_ao_c),
FUNCTION(pwm_ao_d),
FUNCTION(jtag_ao),
FUNCTION(gen_clk_ee),
};
static struct meson_bank meson_axg_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("A", GPIOA_0, GPIOA_20, 40, 60, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
BANK("X", GPIOX_0, GPIOX_22, 61, 83, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
};
static struct meson_bank meson_axg_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0),
BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0),
BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
};
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
.pmx_banks = meson_axg_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
};
static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
};
static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
.pmx_banks = meson_axg_aobus_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
};
static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_axg_periphs_pins,
.groups = meson_axg_periphs_groups,
.funcs = meson_axg_periphs_functions,
.banks = meson_axg_periphs_banks,
.num_pins = ARRAY_SIZE(meson_axg_periphs_pins),
.num_groups = ARRAY_SIZE(meson_axg_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_axg_periphs_functions),
.num_banks = ARRAY_SIZE(meson_axg_periphs_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_axg_periphs_pmx_banks_data,
};
static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_axg_aobus_pins,
.groups = meson_axg_aobus_groups,
.funcs = meson_axg_aobus_functions,
.banks = meson_axg_aobus_banks,
.num_pins = ARRAY_SIZE(meson_axg_aobus_pins),
.num_groups = ARRAY_SIZE(meson_axg_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_axg_aobus_functions),
.num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_axg_aobus_pmx_banks_data,
.parse_dt = meson8_aobus_parse_dt_extra,
};
static const struct of_device_id meson_axg_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-axg-periphs-pinctrl",
.data = &meson_axg_periphs_pinctrl_data,
},
{
.compatible = "amlogic,meson-axg-aobus-pinctrl",
.data = &meson_axg_aobus_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_axg_pinctrl_dt_match);
static struct platform_driver meson_axg_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-axg-pinctrl",
.of_match_table = meson_axg_pinctrl_dt_match,
},
};
module_platform_driver(meson_axg_pinctrl_driver);
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-axg.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pin controller and GPIO driver for Amlogic Meson8b.
*
* Copyright (C) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <[email protected]>
*/
#include <dt-bindings/gpio/meson8b-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson8-pmx.h"
static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
MESON_PIN(GPIOX_20),
MESON_PIN(GPIOX_21),
MESON_PIN(GPIOY_0),
MESON_PIN(GPIOY_1),
MESON_PIN(GPIOY_3),
MESON_PIN(GPIOY_6),
MESON_PIN(GPIOY_7),
MESON_PIN(GPIOY_8),
MESON_PIN(GPIOY_9),
MESON_PIN(GPIOY_10),
MESON_PIN(GPIOY_11),
MESON_PIN(GPIOY_12),
MESON_PIN(GPIOY_13),
MESON_PIN(GPIOY_14),
MESON_PIN(GPIODV_9),
MESON_PIN(GPIODV_24),
MESON_PIN(GPIODV_25),
MESON_PIN(GPIODV_26),
MESON_PIN(GPIODV_27),
MESON_PIN(GPIODV_28),
MESON_PIN(GPIODV_29),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(GPIOH_4),
MESON_PIN(GPIOH_5),
MESON_PIN(GPIOH_6),
MESON_PIN(GPIOH_7),
MESON_PIN(GPIOH_8),
MESON_PIN(GPIOH_9),
MESON_PIN(CARD_0),
MESON_PIN(CARD_1),
MESON_PIN(CARD_2),
MESON_PIN(CARD_3),
MESON_PIN(CARD_4),
MESON_PIN(CARD_5),
MESON_PIN(CARD_6),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(BOOT_15),
MESON_PIN(BOOT_16),
MESON_PIN(BOOT_17),
MESON_PIN(BOOT_18),
MESON_PIN(DIF_0_P),
MESON_PIN(DIF_0_N),
MESON_PIN(DIF_1_P),
MESON_PIN(DIF_1_N),
MESON_PIN(DIF_2_P),
MESON_PIN(DIF_2_N),
MESON_PIN(DIF_3_P),
MESON_PIN(DIF_3_N),
MESON_PIN(DIF_4_P),
MESON_PIN(DIF_4_N),
};
static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIOAO_10),
MESON_PIN(GPIOAO_11),
MESON_PIN(GPIOAO_12),
MESON_PIN(GPIOAO_13),
/*
* The following 2 pins are not mentionned in the public datasheet
* According to this datasheet, they can't be used with the gpio
* interrupt controller
*/
MESON_PIN(GPIO_BSD_EN),
MESON_PIN(GPIO_TEST_N),
};
/* bank X */
static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 };
static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5,
GPIOX_6, GPIOX_7 };
static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6,
GPIOX_7 };
static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 };
static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2,
GPIOX_3 };
static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 };
static const unsigned int pwm_e_pins[] = { GPIOX_10 };
static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 };
static const unsigned int uart_tx_a_pins[] = { GPIOX_4 };
static const unsigned int uart_rx_a_pins[] = { GPIOX_5 };
static const unsigned int uart_cts_a_pins[] = { GPIOX_6 };
static const unsigned int uart_rts_a_pins[] = { GPIOX_7 };
static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 };
static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 };
static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 };
static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 };
static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 };
static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 };
static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 };
static const unsigned int spi_miso_0_pins[] = { GPIOX_9 };
static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 };
static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 };
static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 };
static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 };
static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 };
static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 };
static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 };
static const unsigned int pwm_b_pins[] = { GPIOX_11 };
static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 };
/* bank Y */
static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 };
static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 };
static const unsigned int tsin_d17_a_pins[] = {
GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14,
};
static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 };
static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 };
static const unsigned int spdif_out_0_pins[] = { GPIOY_3 };
static const unsigned int xtal_24m_pins[] = { GPIOY_3 };
static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 };
static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 };
/* bank DV */
static const unsigned int pwm_d_pins[] = { GPIODV_28 };
static const unsigned int pwm_c0_pins[] = { GPIODV_29 };
static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 };
static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 };
static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 };
static const unsigned int xtal24_out_pins[] = { GPIODV_29 };
static const unsigned int uart_tx_c_pins[] = { GPIODV_24 };
static const unsigned int uart_rx_c_pins[] = { GPIODV_25 };
static const unsigned int uart_cts_c_pins[] = { GPIODV_26 };
static const unsigned int uart_rts_c_pins[] = { GPIODV_27 };
static const unsigned int pwm_c1_pins[] = { GPIODV_9 };
static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 };
static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 };
static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 };
static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 };
/* bank H */
static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };
static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };
static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };
static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 };
static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 };
static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };
static const unsigned int spi_ss1_pins[] = { GPIOH_0 };
static const unsigned int spi_ss2_pins[] = { GPIOH_1 };
static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 };
static const unsigned int spi_miso_1_pins[] = { GPIOH_4 };
static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 };
static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 };
static const unsigned int eth_txd3_pins[] = { GPIOH_7 };
static const unsigned int eth_txd2_pins[] = { GPIOH_8 };
static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 };
static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 };
static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 };
static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 };
static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 };
static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
/* bank BOOT */
static const unsigned int nand_io_pins[] = {
BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
};
static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
static const unsigned int nand_ale_pins[] = { BOOT_11 };
static const unsigned int nand_cle_pins[] = { BOOT_12 };
static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
static const unsigned int nand_dqs_15_pins[] = { BOOT_15 };
static const unsigned int nand_dqs_18_pins[] = { BOOT_18 };
static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2,
BOOT_3 };
static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5,
BOOT_6, BOOT_7 };
static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 };
static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 };
static const unsigned int nor_d_pins[] = { BOOT_11 };
static const unsigned int nor_q_pins[] = { BOOT_12 };
static const unsigned int nor_c_pins[] = { BOOT_13 };
static const unsigned int nor_cs_pins[] = { BOOT_18 };
static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
static const unsigned int sd_cmd_c_pins[] = { BOOT_8 };
static const unsigned int sd_clk_c_pins[] = { BOOT_10 };
/* bank CARD */
static const unsigned int sd_d1_b_pins[] = { CARD_0 };
static const unsigned int sd_d0_b_pins[] = { CARD_1 };
static const unsigned int sd_clk_b_pins[] = { CARD_2 };
static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
static const unsigned int sd_d3_b_pins[] = { CARD_4 };
static const unsigned int sd_d2_b_pins[] = { CARD_5 };
static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4,
CARD_5 };
static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
/* bank AO */
static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 };
static const unsigned int remote_input_pins[] = { GPIOAO_7 };
static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 };
static const unsigned int ir_blaster_pins[] = { GPIOAO_13 };
static const unsigned int pwm_c2_pins[] = { GPIOAO_3 };
static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 };
static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 };
static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 };
static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 };
static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 };
static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 };
static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 };
static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 };
static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 };
static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 };
static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 };
/* bank DIF */
static const unsigned int eth_rxd1_pins[] = { DIF_0_P };
static const unsigned int eth_rxd0_pins[] = { DIF_0_N };
static const unsigned int eth_rx_dv_pins[] = { DIF_1_P };
static const unsigned int eth_rx_clk_pins[] = { DIF_1_N };
static const unsigned int eth_txd0_1_pins[] = { DIF_2_P };
static const unsigned int eth_txd1_1_pins[] = { DIF_2_N };
static const unsigned int eth_rxd3_pins[] = { DIF_2_P };
static const unsigned int eth_rxd2_pins[] = { DIF_2_N };
static const unsigned int eth_tx_en_pins[] = { DIF_3_P };
static const unsigned int eth_ref_clk_pins[] = { DIF_3_N };
static const unsigned int eth_mdc_pins[] = { DIF_4_P };
static const unsigned int eth_mdio_en_pins[] = { DIF_4_N };
static struct meson_pmx_group meson8b_cbus_groups[] = {
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
GPIO_GROUP(GPIOX_20),
GPIO_GROUP(GPIOX_21),
GPIO_GROUP(GPIOY_0),
GPIO_GROUP(GPIOY_1),
GPIO_GROUP(GPIOY_3),
GPIO_GROUP(GPIOY_6),
GPIO_GROUP(GPIOY_7),
GPIO_GROUP(GPIOY_8),
GPIO_GROUP(GPIOY_9),
GPIO_GROUP(GPIOY_10),
GPIO_GROUP(GPIOY_11),
GPIO_GROUP(GPIOY_12),
GPIO_GROUP(GPIOY_13),
GPIO_GROUP(GPIOY_14),
GPIO_GROUP(GPIODV_9),
GPIO_GROUP(GPIODV_24),
GPIO_GROUP(GPIODV_25),
GPIO_GROUP(GPIODV_26),
GPIO_GROUP(GPIODV_27),
GPIO_GROUP(GPIODV_28),
GPIO_GROUP(GPIODV_29),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(GPIOH_4),
GPIO_GROUP(GPIOH_5),
GPIO_GROUP(GPIOH_6),
GPIO_GROUP(GPIOH_7),
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(GPIOH_9),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(BOOT_18),
GPIO_GROUP(DIF_0_P),
GPIO_GROUP(DIF_0_N),
GPIO_GROUP(DIF_1_P),
GPIO_GROUP(DIF_1_N),
GPIO_GROUP(DIF_2_P),
GPIO_GROUP(DIF_2_N),
GPIO_GROUP(DIF_3_P),
GPIO_GROUP(DIF_3_N),
GPIO_GROUP(DIF_4_P),
GPIO_GROUP(DIF_4_N),
/* bank X */
GROUP(sd_d0_a, 8, 5),
GROUP(sd_d1_a, 8, 4),
GROUP(sd_d2_a, 8, 3),
GROUP(sd_d3_a, 8, 2),
GROUP(sdxc_d0_0_a, 5, 29),
GROUP(sdxc_d47_a, 5, 12),
GROUP(sdxc_d13_0_a, 5, 28),
GROUP(sd_clk_a, 8, 1),
GROUP(sd_cmd_a, 8, 0),
GROUP(xtal_32k_out, 3, 22),
GROUP(xtal_24m_out, 3, 20),
GROUP(uart_tx_b0, 4, 9),
GROUP(uart_rx_b0, 4, 8),
GROUP(uart_cts_b0, 4, 7),
GROUP(uart_rts_b0, 4, 6),
GROUP(sdxc_d0_1_a, 5, 14),
GROUP(sdxc_d13_1_a, 5, 13),
GROUP(pcm_out_a, 3, 30),
GROUP(pcm_in_a, 3, 29),
GROUP(pcm_fs_a, 3, 28),
GROUP(pcm_clk_a, 3, 27),
GROUP(sdxc_clk_a, 5, 11),
GROUP(sdxc_cmd_a, 5, 10),
GROUP(pwm_vs_0, 7, 31),
GROUP(pwm_e, 9, 19),
GROUP(pwm_vs_1, 7, 30),
GROUP(uart_tx_a, 4, 17),
GROUP(uart_rx_a, 4, 16),
GROUP(uart_cts_a, 4, 15),
GROUP(uart_rts_a, 4, 14),
GROUP(uart_tx_b1, 6, 19),
GROUP(uart_rx_b1, 6, 18),
GROUP(uart_cts_b1, 6, 17),
GROUP(uart_rts_b1, 6, 16),
GROUP(iso7816_0_clk, 5, 9),
GROUP(iso7816_0_data, 5, 8),
GROUP(spi_sclk_0, 4, 22),
GROUP(spi_miso_0, 4, 24),
GROUP(spi_mosi_0, 4, 23),
GROUP(iso7816_det, 4, 21),
GROUP(iso7816_reset, 4, 20),
GROUP(iso7816_1_clk, 4, 19),
GROUP(iso7816_1_data, 4, 18),
GROUP(spi_ss0_0, 4, 25),
GROUP(tsin_clk_b, 3, 6),
GROUP(tsin_sop_b, 3, 7),
GROUP(tsin_d0_b, 3, 8),
GROUP(pwm_b, 2, 3),
GROUP(i2c_sda_d0, 4, 5),
GROUP(i2c_sck_d0, 4, 4),
GROUP(tsin_d_valid_b, 3, 9),
/* bank Y */
GROUP(tsin_d_valid_a, 3, 2),
GROUP(tsin_sop_a, 3, 1),
GROUP(tsin_d17_a, 3, 5),
GROUP(tsin_clk_a, 3, 0),
GROUP(tsin_d0_a, 3, 4),
GROUP(spdif_out_0, 1, 7),
GROUP(xtal_24m, 3, 18),
GROUP(iso7816_2_clk, 5, 7),
GROUP(iso7816_2_data, 5, 6),
/* bank DV */
GROUP(pwm_d, 3, 26),
GROUP(pwm_c0, 3, 25),
GROUP(pwm_vs_2, 7, 28),
GROUP(pwm_vs_3, 7, 27),
GROUP(pwm_vs_4, 7, 26),
GROUP(xtal24_out, 7, 25),
GROUP(uart_tx_c, 6, 23),
GROUP(uart_rx_c, 6, 22),
GROUP(uart_cts_c, 6, 21),
GROUP(uart_rts_c, 6, 20),
GROUP(pwm_c1, 3, 24),
GROUP(i2c_sda_a, 9, 31),
GROUP(i2c_sck_a, 9, 30),
GROUP(i2c_sda_b0, 9, 29),
GROUP(i2c_sck_b0, 9, 28),
GROUP(i2c_sda_c0, 9, 27),
GROUP(i2c_sck_c0, 9, 26),
/* bank H */
GROUP(hdmi_hpd, 1, 26),
GROUP(hdmi_sda, 1, 25),
GROUP(hdmi_scl, 1, 24),
GROUP(hdmi_cec_0, 1, 23),
GROUP(eth_txd1_0, 7, 21),
GROUP(eth_txd0_0, 7, 20),
GROUP(clk_24m_out, 4, 1),
GROUP(spi_ss1, 8, 11),
GROUP(spi_ss2, 8, 12),
GROUP(spi_ss0_1, 9, 13),
GROUP(spi_miso_1, 9, 12),
GROUP(spi_mosi_1, 9, 11),
GROUP(spi_sclk_1, 9, 10),
GROUP(eth_rxd3_h, 6, 15),
GROUP(eth_rxd2_h, 6, 14),
GROUP(eth_txd3, 6, 13),
GROUP(eth_txd2, 6, 12),
GROUP(eth_tx_clk, 6, 11),
GROUP(i2c_sda_b1, 5, 27),
GROUP(i2c_sck_b1, 5, 26),
GROUP(i2c_sda_c1, 5, 25),
GROUP(i2c_sck_c1, 5, 24),
GROUP(i2c_sda_d1, 4, 3),
GROUP(i2c_sck_d1, 4, 2),
/* bank BOOT */
GROUP(nand_io, 2, 26),
GROUP(nand_io_ce0, 2, 25),
GROUP(nand_io_ce1, 2, 24),
GROUP(nand_io_rb0, 2, 17),
GROUP(nand_ale, 2, 21),
GROUP(nand_cle, 2, 20),
GROUP(nand_wen_clk, 2, 19),
GROUP(nand_ren_clk, 2, 18),
GROUP(nand_dqs_15, 2, 27),
GROUP(nand_dqs_18, 2, 28),
GROUP(sdxc_d0_c, 4, 30),
GROUP(sdxc_d13_c, 4, 29),
GROUP(sdxc_d47_c, 4, 28),
GROUP(sdxc_clk_c, 7, 19),
GROUP(sdxc_cmd_c, 7, 18),
GROUP(nor_d, 5, 1),
GROUP(nor_q, 5, 3),
GROUP(nor_c, 5, 2),
GROUP(nor_cs, 5, 0),
GROUP(sd_d0_c, 6, 29),
GROUP(sd_d1_c, 6, 28),
GROUP(sd_d2_c, 6, 27),
GROUP(sd_d3_c, 6, 26),
GROUP(sd_cmd_c, 6, 30),
GROUP(sd_clk_c, 6, 31),
/* bank CARD */
GROUP(sd_d1_b, 2, 14),
GROUP(sd_d0_b, 2, 15),
GROUP(sd_clk_b, 2, 11),
GROUP(sd_cmd_b, 2, 10),
GROUP(sd_d3_b, 2, 12),
GROUP(sd_d2_b, 2, 13),
GROUP(sdxc_d13_b, 2, 6),
GROUP(sdxc_d0_b, 2, 7),
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
/* bank DIF */
GROUP(eth_rxd1, 6, 0),
GROUP(eth_rxd0, 6, 1),
GROUP(eth_rx_dv, 6, 2),
GROUP(eth_rx_clk, 6, 3),
GROUP(eth_txd0_1, 6, 4),
GROUP(eth_txd1_1, 6, 5),
GROUP(eth_tx_en, 6, 6),
GROUP(eth_ref_clk, 6, 8),
GROUP(eth_mdc, 6, 9),
GROUP(eth_mdio_en, 6, 10),
GROUP(eth_rxd3, 7, 22),
GROUP(eth_rxd2, 7, 23),
};
static struct meson_pmx_group meson8b_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
GPIO_GROUP(GPIOAO_10),
GPIO_GROUP(GPIOAO_11),
GPIO_GROUP(GPIOAO_12),
GPIO_GROUP(GPIOAO_13),
GPIO_GROUP(GPIO_BSD_EN),
GPIO_GROUP(GPIO_TEST_N),
/* bank AO */
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
GROUP(i2c_mst_sck_ao, 0, 6),
GROUP(i2c_mst_sda_ao, 0, 5),
GROUP(clk_32k_in_out, 0, 18),
GROUP(remote_input, 0, 0),
GROUP(hdmi_cec_1, 0, 17),
GROUP(ir_blaster, 0, 31),
GROUP(pwm_c2, 0, 22),
GROUP(i2c_sck_ao, 0, 2),
GROUP(i2c_sda_ao, 0, 1),
GROUP(ir_remote_out, 0, 21),
GROUP(i2s_am_clk_out, 0, 30),
GROUP(i2s_ao_clk_out, 0, 29),
GROUP(i2s_lr_clk_out, 0, 28),
GROUP(i2s_out_01, 0, 27),
GROUP(uart_tx_ao_b0, 0, 26),
GROUP(uart_rx_ao_b0, 0, 25),
GROUP(uart_cts_ao_b, 0, 8),
GROUP(uart_rts_ao_b, 0, 7),
GROUP(uart_tx_ao_b1, 0, 24),
GROUP(uart_rx_ao_b1, 0, 23),
GROUP(spdif_out_1, 0, 16),
GROUP(i2s_in_ch01, 0, 13),
GROUP(i2s_ao_clk_in, 0, 15),
GROUP(i2s_lr_clk_in, 0, 14),
};
static const char * const gpio_periphs_groups[] = {
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
"GPIOX_19", "GPIOX_20", "GPIOX_21",
"GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7",
"GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12",
"GPIOY_13", "GPIOY_14",
"GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26",
"GPIODV_27", "GPIODV_28", "GPIODV_29",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
"GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
"CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
"CARD_5", "CARD_6",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
"DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
"DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
"DIF_4_P", "DIF_4_N"
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
"GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
};
static const char * const sd_a_groups[] = {
"sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
"sd_cmd_a"
};
static const char * const sdxc_a_groups[] = {
"sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a",
"sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d13_1_a"
};
static const char * const pcm_a_groups[] = {
"pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
};
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"
};
static const char * const uart_b_groups[] = {
"uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
"uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
};
static const char * const iso7816_groups[] = {
"iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data",
"iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data"
};
static const char * const i2c_d_groups[] = {
"i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
};
static const char * const xtal_groups[] = {
"xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out"
};
static const char * const uart_c_groups[] = {
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
};
static const char * const i2c_c_groups[] = {
"i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
};
static const char * const hdmi_groups[] = {
"hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
};
static const char * const hdmi_cec_groups[] = {
"hdmi_cec_1"
};
static const char * const spi_groups[] = {
"spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
"spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1",
"spi_miso_1", "spi_ss2"
};
static const char * const ethernet_groups[] = {
"eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
"eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
"eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
"eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2",
"eth_rxd3_h", "eth_rxd2_h"
};
static const char * const i2c_a_groups[] = {
"i2c_sda_a", "i2c_sck_a",
};
static const char * const i2c_b_groups[] = {
"i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1"
};
static const char * const sd_c_groups[] = {
"sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
"sd_cmd_c", "sd_clk_c"
};
static const char * const sdxc_c_groups[] = {
"sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
"sdxc_clk_c"
};
static const char * const nand_groups[] = {
"nand_io", "nand_io_ce0", "nand_io_ce1",
"nand_io_rb0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_clk", "nand_dqs_15",
"nand_dqs_18"
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs"
};
static const char * const sd_b_groups[] = {
"sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
"sd_d3_b", "sd_d2_b"
};
static const char * const sdxc_b_groups[] = {
"sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
};
static const char * const uart_ao_groups[] = {
"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
};
static const char * const remote_groups[] = {
"remote_input", "ir_blaster", "ir_remote_out"
};
static const char * const i2c_slave_ao_groups[] = {
"i2c_sck_ao", "i2c_sda_ao"
};
static const char * const uart_ao_b_groups[] = {
"uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1",
"uart_cts_ao_b", "uart_rts_ao_b"
};
static const char * const i2c_mst_ao_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
static const char * const clk_24m_groups[] = {
"clk_24m_out"
};
static const char * const clk_32k_groups[] = {
"clk_32k_in_out"
};
static const char * const spdif_0_groups[] = {
"spdif_out_0"
};
static const char * const spdif_1_groups[] = {
"spdif_out_1"
};
static const char * const i2s_groups[] = {
"i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out",
"i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in",
"i2s_lr_clk_in"
};
static const char * const pwm_b_groups[] = {
"pwm_b"
};
static const char * const pwm_c_groups[] = {
"pwm_c0", "pwm_c1"
};
static const char * const pwm_c_ao_groups[] = {
"pwm_c2"
};
static const char * const pwm_d_groups[] = {
"pwm_d"
};
static const char * const pwm_e_groups[] = {
"pwm_e"
};
static const char * const pwm_vs_groups[] = {
"pwm_vs_0", "pwm_vs_1", "pwm_vs_2",
"pwm_vs_3", "pwm_vs_4"
};
static const char * const tsin_a_groups[] = {
"tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a",
"tsin_d_valid_a"
};
static const char * const tsin_b_groups[] = {
"tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
};
static struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(pcm_a),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(iso7816),
FUNCTION(i2c_d),
FUNCTION(xtal),
FUNCTION(uart_c),
FUNCTION(i2c_c),
FUNCTION(hdmi),
FUNCTION(spi),
FUNCTION(ethernet),
FUNCTION(i2c_a),
FUNCTION(i2c_b),
FUNCTION(sd_c),
FUNCTION(sdxc_c),
FUNCTION(nand),
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
FUNCTION(spdif_0),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_vs),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
FUNCTION(clk_24m),
};
static struct meson_pmx_func meson8b_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_slave_ao),
FUNCTION(i2c_mst_ao),
FUNCTION(i2s),
FUNCTION(remote),
FUNCTION(clk_32k),
FUNCTION(pwm_c_ao),
FUNCTION(spdif_1),
FUNCTION(hdmi_cec),
};
static struct meson_bank meson8b_cbus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3),
BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6),
BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9),
BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24),
BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
/*
* The following bank is not mentionned in the public datasheet
* There is no information whether it can be used with the gpio
* interrupt controller
*/
BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
static struct meson_bank meson8b_aobus_banks[] = {
/* name first lastc irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
.name = "cbus-banks",
.pins = meson8b_cbus_pins,
.groups = meson8b_cbus_groups,
.funcs = meson8b_cbus_functions,
.banks = meson8b_cbus_banks,
.num_pins = ARRAY_SIZE(meson8b_cbus_pins),
.num_groups = ARRAY_SIZE(meson8b_cbus_groups),
.num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
.num_banks = ARRAY_SIZE(meson8b_cbus_banks),
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson8b_aobus_pins,
.groups = meson8b_aobus_groups,
.funcs = meson8b_aobus_functions,
.banks = meson8b_aobus_banks,
.num_pins = ARRAY_SIZE(meson8b_aobus_pins),
.num_groups = ARRAY_SIZE(meson8b_aobus_groups),
.num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
.num_banks = ARRAY_SIZE(meson8b_aobus_banks),
.pmx_ops = &meson8_pmx_ops,
.parse_dt = &meson8_aobus_parse_dt_extra,
};
static const struct of_device_id meson8b_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson8b-cbus-pinctrl",
.data = &meson8b_cbus_pinctrl_data,
},
{
.compatible = "amlogic,meson8b-aobus-pinctrl",
.data = &meson8b_aobus_pinctrl_data,
},
{ },
};
static struct platform_driver meson8b_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson8b-pinctrl",
.of_match_table = meson8b_pinctrl_dt_match,
},
};
builtin_platform_driver(meson8b_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson8b.c
|
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Pin controller and GPIO driver for Amlogic C3 SoC.
*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Huqiang Qin <[email protected]>
*/
#include <dt-bindings/gpio/amlogic-c3-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static const struct pinctrl_pin_desc c3_periphs_pins[] = {
MESON_PIN(GPIOE_0),
MESON_PIN(GPIOE_1),
MESON_PIN(GPIOE_2),
MESON_PIN(GPIOE_3),
MESON_PIN(GPIOE_4),
MESON_PIN(GPIOB_0),
MESON_PIN(GPIOB_1),
MESON_PIN(GPIOB_2),
MESON_PIN(GPIOB_3),
MESON_PIN(GPIOB_4),
MESON_PIN(GPIOB_5),
MESON_PIN(GPIOB_6),
MESON_PIN(GPIOB_7),
MESON_PIN(GPIOB_8),
MESON_PIN(GPIOB_9),
MESON_PIN(GPIOB_10),
MESON_PIN(GPIOB_11),
MESON_PIN(GPIOB_12),
MESON_PIN(GPIOB_13),
MESON_PIN(GPIOB_14),
MESON_PIN(GPIOC_0),
MESON_PIN(GPIOC_1),
MESON_PIN(GPIOC_2),
MESON_PIN(GPIOC_3),
MESON_PIN(GPIOC_4),
MESON_PIN(GPIOC_5),
MESON_PIN(GPIOC_6),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOD_0),
MESON_PIN(GPIOD_1),
MESON_PIN(GPIOD_2),
MESON_PIN(GPIOD_3),
MESON_PIN(GPIOD_4),
MESON_PIN(GPIOD_5),
MESON_PIN(GPIOD_6),
MESON_PIN(GPIOA_0),
MESON_PIN(GPIOA_1),
MESON_PIN(GPIOA_2),
MESON_PIN(GPIOA_3),
MESON_PIN(GPIOA_4),
MESON_PIN(GPIOA_5),
MESON_PIN(GPIO_TEST_N),
};
/* Bank E func1 */
static const unsigned int pwm_a_pins[] = { GPIOE_0 };
static const unsigned int pwm_b_pins[] = { GPIOE_1 };
static const unsigned int i2c2_sda_pins[] = { GPIOE_2 };
static const unsigned int i2c2_scl_pins[] = { GPIOE_3 };
static const unsigned int gen_clk_e_pins[] = { GPIOE_4 };
/* Bank E func2 */
static const unsigned int i2c0_sda_e_pins[] = { GPIOE_0 };
static const unsigned int i2c0_scl_e_pins[] = { GPIOE_1 };
static const unsigned int clk_32k_in_pins[] = { GPIOE_4 };
/* Bank E func3 */
static const unsigned int i2c_slave_scl_pins[] = { GPIOE_0 };
static const unsigned int i2c_slave_sda_pins[] = { GPIOE_1 };
static const unsigned int clk12_24_e_pins[] = { GPIOE_4 };
/* Bank B func1 */
static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
static const unsigned int emmc_rst_pins[] = { GPIOB_9 };
static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
/* Bank B func2 */
static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
static const unsigned int nand_ale_pins[] = { GPIOB_9 };
static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
static const unsigned int nand_cle_pins[] = { GPIOB_11 };
static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
/* Bank B func3 */
static const unsigned int pwm_g_b_pins[] = { GPIOB_0 };
static const unsigned int pwm_h_b_pins[] = { GPIOB_1 };
static const unsigned int pwm_i_b_pins[] = { GPIOB_2 };
static const unsigned int spif_hold_pins[] = { GPIOB_3 };
static const unsigned int spif_mo_pins[] = { GPIOB_4 };
static const unsigned int spif_mi_pins[] = { GPIOB_5 };
static const unsigned int spif_clk_pins[] = { GPIOB_6 };
static const unsigned int spif_wp_pins[] = { GPIOB_7 };
static const unsigned int pwm_j_b_pins[] = { GPIOB_8 };
static const unsigned int pwm_k_b_pins[] = { GPIOB_9 };
static const unsigned int pwm_l_b_pins[] = { GPIOB_10 };
static const unsigned int pwm_m_b_pins[] = { GPIOB_11 };
static const unsigned int pwm_n_b_pins[] = { GPIOB_12 };
static const unsigned int spif_cs_pins[] = { GPIOB_13 };
static const unsigned int spif_clk_loop_pins[] = { GPIOB_14 };
/* Bank B func4 */
static const unsigned int lcd_d0_pins[] = { GPIOB_0 };
static const unsigned int lcd_d1_pins[] = { GPIOB_1 };
static const unsigned int lcd_d2_pins[] = { GPIOB_2 };
static const unsigned int lcd_d3_pins[] = { GPIOB_8 };
static const unsigned int lcd_d4_pins[] = { GPIOB_9 };
static const unsigned int lcd_d5_pins[] = { GPIOB_10 };
static const unsigned int lcd_d6_pins[] = { GPIOB_11 };
static const unsigned int lcd_d7_pins[] = { GPIOB_12 };
/* Bank B func5 */
static const unsigned int spi_a_mosi_b_pins[] = { GPIOB_0 };
static const unsigned int spi_a_miso_b_pins[] = { GPIOB_1 };
static const unsigned int spi_a_clk_b_pins[] = { GPIOB_2 };
static const unsigned int spi_a_ss0_b_pins[] = { GPIOB_8 };
static const unsigned int spi_a_ss1_b_pins[] = { GPIOB_9 };
static const unsigned int spi_a_ss2_b_pins[] = { GPIOB_10 };
static const unsigned int i2c1_sda_b_pins[] = { GPIOB_11 };
static const unsigned int i2c1_scl_b_pins[] = { GPIOB_12 };
/* Bank B func6 */
static const unsigned int uart_a_tx_b_pins[] = { GPIOB_0 };
static const unsigned int uart_a_rx_b_pins[] = { GPIOB_1 };
static const unsigned int uart_a_cts_b_pins[] = { GPIOB_2 };
static const unsigned int uart_a_rts_b_pins[] = { GPIOB_8 };
static const unsigned int uart_d_tx_b_pins[] = { GPIOB_9 };
static const unsigned int uart_d_rx_b_pins[] = { GPIOB_10 };
static const unsigned int pdm_dclk_b_pins[] = { GPIOB_11 };
static const unsigned int pdm_din0_b_pins[] = { GPIOB_12 };
/* Bank C func1 */
static const unsigned int sdcard_d0_pins[] = { GPIOC_0 };
static const unsigned int sdcard_d1_pins[] = { GPIOC_1 };
static const unsigned int sdcard_d2_pins[] = { GPIOC_2 };
static const unsigned int sdcard_d3_pins[] = { GPIOC_3 };
static const unsigned int sdcard_clk_pins[] = { GPIOC_4 };
static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 };
static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
/* Bank C func2 */
static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
static const unsigned int gen_clk_c_pins[] = { GPIOC_6 };
/* Bank C func3 */
static const unsigned int tdm_d3_pins[] = { GPIOC_0 };
static const unsigned int tdm_d2_pins[] = { GPIOC_1 };
static const unsigned int mclk_1_pins[] = { GPIOC_2 };
static const unsigned int tdm_sclk1_pins[] = { GPIOC_3 };
static const unsigned int tdm_fs1_pins[] = { GPIOC_4 };
static const unsigned int pdm_dclk_c_pins[] = { GPIOC_5 };
static const unsigned int pdm_din0_c_pins[] = { GPIOC_6 };
/* Bank C func4 */
static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 };
static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 };
static const unsigned int spi_a_clk_c_pins[] = { GPIOC_2 };
static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_3 };
static const unsigned int spi_a_ss1_c_pins[] = { GPIOC_4 };
/* Bank C func5 */
static const unsigned int pwm_g_c_pins[] = { GPIOC_0 };
static const unsigned int pwm_h_c_pins[] = { GPIOC_1 };
static const unsigned int pwm_i_c_pins[] = { GPIOC_2 };
static const unsigned int pwm_j_c_pins[] = { GPIOC_3 };
static const unsigned int pwm_k_c_pins[] = { GPIOC_4 };
static const unsigned int pwm_l_c_pins[] = { GPIOC_5 };
static const unsigned int pwm_m_c_pins[] = { GPIOC_6 };
/* Bank C func6 */
static const unsigned int uart_a_rx_c_pins[] = { GPIOC_0 };
static const unsigned int uart_a_tx_c_pins[] = { GPIOC_1 };
static const unsigned int uart_c_rx_c_pins[] = { GPIOC_2 };
static const unsigned int uart_c_tx_c_pins[] = { GPIOC_3 };
static const unsigned int i2c3_sda_c_pins[] = { GPIOC_4 };
static const unsigned int i2c3_scl_c_pins[] = { GPIOC_5 };
static const unsigned int clk12_24_c_pins[] = { GPIOC_6 };
/* Bank X func1 */
static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
static const unsigned int clk12_24_x_pins[] = { GPIOX_6 };
static const unsigned int uart_e_tx_x_pins[] = { GPIOX_7 };
static const unsigned int uart_e_rx_x_pins[] = { GPIOX_8 };
static const unsigned int uart_e_cts_pins[] = { GPIOX_9 };
static const unsigned int uart_e_rts_pins[] = { GPIOX_10 };
static const unsigned int pwm_e_pins[] = { GPIOX_11 };
static const unsigned int pwm_j_x12_pins[] = { GPIOX_12 };
static const unsigned int pwm_k_x13_pins[] = { GPIOX_13 };
/* Bank X func2 */
static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_0 };
static const unsigned int spi_a_miso_x_pins[] = { GPIOX_1 };
static const unsigned int spi_a_clk_x_pins[] = { GPIOX_2 };
static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_3 };
static const unsigned int spi_a_ss1_x_pins[] = { GPIOX_4 };
static const unsigned int spi_a_ss2_x_pins[] = { GPIOX_5 };
static const unsigned int spi_b_ss2_x6_pins[] = { GPIOX_6 };
static const unsigned int spi_b_miso_x_pins[] = { GPIOX_7 };
static const unsigned int spi_b_clk_x_pins[] = { GPIOX_8 };
static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_9 };
static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 };
static const unsigned int spi_b_ss1_x_pins[] = { GPIOX_11 };
static const unsigned int spi_b_ss2_x12_pins[] = { GPIOX_12 };
static const unsigned int gen_clk_x_pins[] = { GPIOX_13 };
/* Bank X func3 */
static const unsigned int tdm_d1_x_pins[] = { GPIOX_0 };
static const unsigned int tdm_d0_x_pins[] = { GPIOX_1 };
static const unsigned int mclk_0_x_pins[] = { GPIOX_2 };
static const unsigned int tdm_sclk0_x_pins[] = { GPIOX_3 };
static const unsigned int tdm_fs0_x_pins[] = { GPIOX_4 };
static const unsigned int pdm_dclk_x5_pins[] = { GPIOX_5 };
static const unsigned int pdm_din0_x6_pins[] = { GPIOX_6 };
static const unsigned int pdm_din0_x9_pins[] = { GPIOX_9 };
static const unsigned int pdm_dclk_x10_pins[] = { GPIOX_10 };
static const unsigned int clk12_24_x13_pins[] = { GPIOX_13 };
/* Bank X func4 */
static const unsigned int lcd_d8_pins[] = { GPIOX_0 };
static const unsigned int lcd_d9_pins[] = { GPIOX_1 };
static const unsigned int lcd_d10_pins[] = { GPIOX_2 };
static const unsigned int lcd_d11_pins[] = { GPIOX_3 };
static const unsigned int lcd_d12_pins[] = { GPIOX_4 };
static const unsigned int lcd_d13_pins[] = { GPIOX_5 };
static const unsigned int lcd_d14_pins[] = { GPIOX_6 };
static const unsigned int lcd_d15_pins[] = { GPIOX_7 };
static const unsigned int lcd_vs_pins[] = { GPIOX_8 };
static const unsigned int lcd_hs_pins[] = { GPIOX_9 };
static const unsigned int lcd_den_pins[] = { GPIOX_10 };
static const unsigned int lcd_d16_pins[] = { GPIOX_11 };
static const unsigned int lcd_clk_x_pins[] = { GPIOX_12 };
static const unsigned int lcd_d17_pins[] = { GPIOX_13 };
/* Bank X func5 */
static const unsigned int pwm_g_x0_pins[] = { GPIOX_0 };
static const unsigned int pwm_h_x1_pins[] = { GPIOX_1 };
static const unsigned int pwm_i_x2_pins[] = { GPIOX_2 };
static const unsigned int pwm_j_x3_pins[] = { GPIOX_3 };
static const unsigned int pwm_k_x4_pins[] = { GPIOX_4 };
static const unsigned int pwm_l_x_pins[] = { GPIOX_5 };
static const unsigned int pwm_m_x_pins[] = { GPIOX_6 };
static const unsigned int pwm_n_x_pins[] = { GPIOX_7 };
static const unsigned int pwm_g_x8_pins[] = { GPIOX_8 };
static const unsigned int pwm_h_x9_pins[] = { GPIOX_9 };
static const unsigned int pwm_i_x10_pins[] = { GPIOX_10 };
static const unsigned int clk12_24_x11_pins[] = { GPIOX_11 };
/* Bank X func6 */
static const unsigned int uart_a_rx_x_pins[] = { GPIOX_0 };
static const unsigned int uart_a_tx_x_pins[] = { GPIOX_1 };
static const unsigned int uart_c_rx_x_pins[] = { GPIOX_2 };
static const unsigned int uart_c_tx_x_pins[] = { GPIOX_3 };
static const unsigned int i2c3_sda_x_pins[] = { GPIOX_4 };
static const unsigned int i2c3_scl_x_pins[] = { GPIOX_5 };
static const unsigned int i2c1_sda_x_pins[] = { GPIOX_7 };
static const unsigned int i2c1_scl_x_pins[] = { GPIOX_8 };
static const unsigned int uart_d_tx_x_pins[] = { GPIOX_9 };
static const unsigned int uart_d_rx_x_pins[] = { GPIOX_10 };
/* Bank D func1 */
static const unsigned int pwm_g_d_pins[] = { GPIOD_0 };
static const unsigned int pwm_h_d_pins[] = { GPIOD_1 };
static const unsigned int eth_led_act_pins[] = { GPIOD_2 };
static const unsigned int eth_led_link_pins[] = { GPIOD_3 };
static const unsigned int pwm_d_pins[] = { GPIOD_4 };
static const unsigned int pwm_f_pins[] = { GPIOD_5 };
static const unsigned int pwm_k_d_pins[] = { GPIOD_6 };
/* Bank D func2 */
static const unsigned int uart_a_tx_d_pins[] = { GPIOD_0 };
static const unsigned int uart_a_rx_d_pins[] = { GPIOD_1 };
static const unsigned int spi_b_miso_d_pins[] = { GPIOD_2 };
static const unsigned int spi_b_clk_d_pins[] = { GPIOD_3 };
static const unsigned int spi_b_mosi_d_pins[] = { GPIOD_4 };
static const unsigned int spi_b_ss0_d_pins[] = { GPIOD_5 };
static const unsigned int spi_b_ss1_d_pins[] = { GPIOD_6 };
/* Bank D func3 */
static const unsigned int i2c0_sda_d_pins[] = { GPIOD_0 };
static const unsigned int i2c0_scl_d_pins[] = { GPIOD_1 };
static const unsigned int i2c1_sda_d_pins[] = { GPIOD_2 };
static const unsigned int i2c1_scl_d_pins[] = { GPIOD_3 };
static const unsigned int pdm_dclk_d_pins[] = { GPIOD_4 };
static const unsigned int pdm_din0_d_pins[] = { GPIOD_5 };
static const unsigned int ir_in_d6_pins[] = { GPIOD_6 };
/* Bank D func4 */
static const unsigned int ir_in_d0_pins[] = { GPIOD_0 };
static const unsigned int ir_out_pins[] = { GPIOD_1 };
static const unsigned int pwm_i_d_pins[] = { GPIOD_2 };
static const unsigned int pwm_j_d_pins[] = { GPIOD_3 };
static const unsigned int i2c3_sda_d_pins[] = { GPIOD_4 };
static const unsigned int i2c3_scl_d_pins[] = { GPIOD_5 };
/* Bank D func5 */
static const unsigned int tdm_fs0_d_pins[] = { GPIOD_2 };
static const unsigned int tdm_sclk0_d_pins[] = { GPIOD_3 };
static const unsigned int mclk_0_d_pins[] = { GPIOD_4 };
static const unsigned int tdm_d1_d_pins[] = { GPIOD_5 };
static const unsigned int tdm_d0_d_pins[] = { GPIOD_6 };
/* Bank D func6 */
static const unsigned int uart_d_tx_d_pins[] = { GPIOD_0 };
static const unsigned int uart_d_rx_d_pins[] = { GPIOD_1 };
static const unsigned int uart_c_tx_d_pins[] = { GPIOD_2 };
static const unsigned int uart_c_rx_d_pins[] = { GPIOD_3 };
/* Bank A func1 */
static const unsigned int uart_b_tx_a_pins[] = { GPIOA_0 };
static const unsigned int uart_b_rx_a_pins[] = { GPIOA_1 };
static const unsigned int pwm_c_pins[] = { GPIOA_2 };
static const unsigned int pwm_l_a_pins[] = { GPIOA_3 };
static const unsigned int i2c1_sda_a_pins[] = { GPIOA_4 };
static const unsigned int i2c1_scl_a_pins[] = { GPIOA_5 };
/* Bank A func2 */
static const unsigned int pwm_c_hiz_pins[] = { GPIOA_2 };
static const unsigned int gen_clk_a_pins[] = { GPIOA_3 };
static const unsigned int pdm_dclk_z_pins[] = { GPIOA_4 };
static const unsigned int pdm_din0_a_pins[] = { GPIOA_5 };
/* Bank A func3 */
static const unsigned int jtag_a_clk_pins[] = { GPIOA_2 };
static const unsigned int jtag_a_tms_pins[] = { GPIOA_3 };
static const unsigned int jtag_a_tdi_pins[] = { GPIOA_4 };
static const unsigned int jtag_a_tdo_pins[] = { GPIOA_5 };
/* Bank A func4 */
static const unsigned int lcd_clk_a_pins[] = { GPIOA_3 };
static const unsigned int uart_f_tx_a_pins[] = { GPIOA_4 };
static const unsigned int uart_f_rx_a_pins[] = { GPIOA_5 };
/* Bank A func5 */
static const unsigned int uart_e_tx_a_pins[] = { GPIOA_2 };
static const unsigned int uart_e_rx_a_pins[] = { GPIOA_3 };
static const unsigned int pwm_m_a_pins[] = { GPIOA_4 };
static const unsigned int pwm_n_a_pins[] = { GPIOA_5 };
/* Bank A func6 */
static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_3 };
static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 };
static const unsigned int clk12_24_a_pins[] = { GPIOA_5 };
static struct meson_pmx_group c3_periphs_groups[] = {
GPIO_GROUP(GPIOE_0),
GPIO_GROUP(GPIOE_1),
GPIO_GROUP(GPIOE_2),
GPIO_GROUP(GPIOE_3),
GPIO_GROUP(GPIOE_4),
GPIO_GROUP(GPIOB_0),
GPIO_GROUP(GPIOB_1),
GPIO_GROUP(GPIOB_2),
GPIO_GROUP(GPIOB_3),
GPIO_GROUP(GPIOB_4),
GPIO_GROUP(GPIOB_5),
GPIO_GROUP(GPIOB_6),
GPIO_GROUP(GPIOB_7),
GPIO_GROUP(GPIOB_8),
GPIO_GROUP(GPIOB_9),
GPIO_GROUP(GPIOB_10),
GPIO_GROUP(GPIOB_11),
GPIO_GROUP(GPIOB_12),
GPIO_GROUP(GPIOB_13),
GPIO_GROUP(GPIOB_14),
GPIO_GROUP(GPIOC_0),
GPIO_GROUP(GPIOC_1),
GPIO_GROUP(GPIOC_2),
GPIO_GROUP(GPIOC_3),
GPIO_GROUP(GPIOC_4),
GPIO_GROUP(GPIOC_5),
GPIO_GROUP(GPIOC_6),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOD_0),
GPIO_GROUP(GPIOD_1),
GPIO_GROUP(GPIOD_2),
GPIO_GROUP(GPIOD_3),
GPIO_GROUP(GPIOD_4),
GPIO_GROUP(GPIOD_5),
GPIO_GROUP(GPIOD_6),
GPIO_GROUP(GPIOA_0),
GPIO_GROUP(GPIOA_1),
GPIO_GROUP(GPIOA_2),
GPIO_GROUP(GPIOA_3),
GPIO_GROUP(GPIOA_4),
GPIO_GROUP(GPIOA_5),
GPIO_GROUP(GPIO_TEST_N),
/* Bank E func1 */
GROUP(pwm_a, 1),
GROUP(pwm_b, 1),
GROUP(i2c2_sda, 1),
GROUP(i2c2_scl, 1),
GROUP(gen_clk_e, 1),
/* Bank E func2 */
GROUP(i2c0_sda_e, 2),
GROUP(i2c0_scl_e, 2),
GROUP(clk_32k_in, 2),
/* Bank E func3 */
GROUP(i2c_slave_scl, 3),
GROUP(i2c_slave_sda, 3),
GROUP(clk12_24_e, 3),
/* Bank B func1 */
GROUP(emmc_nand_d0, 1),
GROUP(emmc_nand_d1, 1),
GROUP(emmc_nand_d2, 1),
GROUP(emmc_nand_d3, 1),
GROUP(emmc_nand_d4, 1),
GROUP(emmc_nand_d5, 1),
GROUP(emmc_nand_d6, 1),
GROUP(emmc_nand_d7, 1),
GROUP(emmc_clk, 1),
GROUP(emmc_rst, 1),
GROUP(emmc_cmd, 1),
GROUP(emmc_nand_ds, 1),
/* Bank B func2 */
GROUP(nand_wen_clk, 2),
GROUP(nand_ale, 2),
GROUP(nand_ren_wr, 2),
GROUP(nand_cle, 2),
GROUP(nand_ce0, 2),
/* Bank B func3 */
GROUP(pwm_g_b, 3),
GROUP(pwm_h_b, 3),
GROUP(pwm_i_b, 3),
GROUP(spif_hold, 3),
GROUP(spif_mo, 3),
GROUP(spif_mi, 3),
GROUP(spif_clk, 3),
GROUP(spif_wp, 3),
GROUP(pwm_j_b, 3),
GROUP(pwm_k_b, 3),
GROUP(pwm_l_b, 3),
GROUP(pwm_m_b, 3),
GROUP(pwm_n_b, 3),
GROUP(spif_cs, 3),
GROUP(spif_clk_loop, 3),
/* Bank B func4 */
GROUP(lcd_d0, 4),
GROUP(lcd_d1, 4),
GROUP(lcd_d2, 4),
GROUP(lcd_d3, 4),
GROUP(lcd_d4, 4),
GROUP(lcd_d5, 4),
GROUP(lcd_d6, 4),
GROUP(lcd_d7, 4),
/* Bank B func5 */
GROUP(spi_a_mosi_b, 5),
GROUP(spi_a_miso_b, 5),
GROUP(spi_a_clk_b, 5),
GROUP(spi_a_ss0_b, 5),
GROUP(spi_a_ss1_b, 5),
GROUP(spi_a_ss2_b, 5),
GROUP(i2c1_sda_b, 5),
GROUP(i2c1_scl_b, 5),
/* Bank B func6 */
GROUP(uart_a_tx_b, 6),
GROUP(uart_a_rx_b, 6),
GROUP(uart_a_cts_b, 6),
GROUP(uart_a_rts_b, 6),
GROUP(uart_d_tx_b, 6),
GROUP(uart_d_rx_b, 6),
GROUP(pdm_dclk_b, 6),
GROUP(pdm_din0_b, 6),
/* Bank C func1 */
GROUP(sdcard_d0, 1),
GROUP(sdcard_d1, 1),
GROUP(sdcard_d2, 1),
GROUP(sdcard_d3, 1),
GROUP(sdcard_clk, 1),
GROUP(sdcard_cmd, 1),
GROUP(sdcard_cd, 1),
/* Bank C func2 */
GROUP(jtag_b_tdo, 2),
GROUP(jtag_b_tdi, 2),
GROUP(uart_b_rx_c, 2),
GROUP(uart_b_tx_c, 2),
GROUP(jtag_b_clk, 2),
GROUP(jtag_b_tms, 2),
GROUP(gen_clk_c, 2),
/* Bank C func3 */
GROUP(tdm_d3, 3),
GROUP(tdm_d2, 3),
GROUP(mclk_1, 3),
GROUP(tdm_sclk1, 3),
GROUP(tdm_fs1, 3),
GROUP(pdm_dclk_c, 3),
GROUP(pdm_din0_c, 3),
/* Bank C func4 */
GROUP(spi_a_mosi_c, 4),
GROUP(spi_a_miso_c, 4),
GROUP(spi_a_clk_c, 4),
GROUP(spi_a_ss0_c, 4),
GROUP(spi_a_ss1_c, 4),
/* Bank C func5 */
GROUP(pwm_g_c, 5),
GROUP(pwm_h_c, 5),
GROUP(pwm_i_c, 5),
GROUP(pwm_j_c, 5),
GROUP(pwm_k_c, 5),
GROUP(pwm_l_c, 5),
GROUP(pwm_m_c, 5),
/* Bank C func6 */
GROUP(uart_a_rx_c, 6),
GROUP(uart_a_tx_c, 6),
GROUP(uart_c_rx_c, 6),
GROUP(uart_c_tx_c, 6),
GROUP(i2c3_sda_c, 6),
GROUP(i2c3_scl_c, 6),
GROUP(clk12_24_c, 6),
/* Bank X func1 */
GROUP(sdio_d0, 1),
GROUP(sdio_d1, 1),
GROUP(sdio_d2, 1),
GROUP(sdio_d3, 1),
GROUP(sdio_clk, 1),
GROUP(sdio_cmd, 1),
GROUP(clk12_24_x, 1),
GROUP(uart_e_tx_x, 1),
GROUP(uart_e_rx_x, 1),
GROUP(uart_e_cts, 1),
GROUP(uart_e_rts, 1),
GROUP(pwm_e, 1),
GROUP(pwm_j_x12, 1),
GROUP(pwm_k_x13, 1),
/* Bank X func2 */
GROUP(spi_a_mosi_x, 2),
GROUP(spi_a_miso_x, 2),
GROUP(spi_a_clk_x, 2),
GROUP(spi_a_ss0_x, 2),
GROUP(spi_a_ss1_x, 2),
GROUP(spi_a_ss2_x, 2),
GROUP(spi_b_ss2_x6, 2),
GROUP(spi_b_miso_x, 2),
GROUP(spi_b_clk_x, 2),
GROUP(spi_b_mosi_x, 2),
GROUP(spi_b_ss0_x, 2),
GROUP(spi_b_ss1_x, 2),
GROUP(spi_b_ss2_x12, 2),
GROUP(gen_clk_x, 2),
/* Bank X func3 */
GROUP(tdm_d1_x, 3),
GROUP(tdm_d0_x, 3),
GROUP(mclk_0_x, 3),
GROUP(tdm_sclk0_x, 3),
GROUP(tdm_fs0_x, 3),
GROUP(pdm_dclk_x5, 3),
GROUP(pdm_din0_x6, 3),
GROUP(pdm_din0_x9, 3),
GROUP(pdm_dclk_x10, 3),
GROUP(clk12_24_x13, 3),
/* Bank X func4 */
GROUP(lcd_d8, 4),
GROUP(lcd_d9, 4),
GROUP(lcd_d10, 4),
GROUP(lcd_d11, 4),
GROUP(lcd_d12, 4),
GROUP(lcd_d13, 4),
GROUP(lcd_d14, 4),
GROUP(lcd_d15, 4),
GROUP(lcd_vs, 4),
GROUP(lcd_hs, 4),
GROUP(lcd_den, 4),
GROUP(lcd_d16, 4),
GROUP(lcd_clk_x, 4),
GROUP(lcd_d17, 4),
/* Bank X func5 */
GROUP(pwm_g_x0, 5),
GROUP(pwm_h_x1, 5),
GROUP(pwm_i_x2, 5),
GROUP(pwm_j_x3, 5),
GROUP(pwm_k_x4, 5),
GROUP(pwm_l_x, 5),
GROUP(pwm_m_x, 5),
GROUP(pwm_n_x, 5),
GROUP(pwm_g_x8, 5),
GROUP(pwm_h_x9, 5),
GROUP(pwm_i_x10, 5),
GROUP(clk12_24_x11, 5),
/* Bank X func6 */
GROUP(uart_a_rx_x, 6),
GROUP(uart_a_tx_x, 6),
GROUP(uart_c_rx_x, 6),
GROUP(uart_c_tx_x, 6),
GROUP(i2c3_sda_x, 6),
GROUP(i2c3_scl_x, 6),
GROUP(i2c1_sda_x, 6),
GROUP(i2c1_scl_x, 6),
GROUP(uart_d_tx_x, 6),
GROUP(uart_d_rx_x, 6),
/* Bank D func1 */
GROUP(pwm_g_d, 1),
GROUP(pwm_h_d, 1),
GROUP(eth_led_act, 1),
GROUP(eth_led_link, 1),
GROUP(pwm_d, 1),
GROUP(pwm_f, 1),
GROUP(pwm_k_d, 1),
/* Bank D func2 */
GROUP(uart_a_tx_d, 2),
GROUP(uart_a_rx_d, 2),
GROUP(spi_b_miso_d, 2),
GROUP(spi_b_clk_d, 2),
GROUP(spi_b_mosi_d, 2),
GROUP(spi_b_ss0_d, 2),
GROUP(spi_b_ss1_d, 2),
/* Bank D func3 */
GROUP(i2c0_sda_d, 3),
GROUP(i2c0_scl_d, 3),
GROUP(i2c1_sda_d, 3),
GROUP(i2c1_scl_d, 3),
GROUP(pdm_dclk_d, 3),
GROUP(pdm_din0_d, 3),
GROUP(ir_in_d6, 3),
/* Bank D func4 */
GROUP(ir_in_d0, 4),
GROUP(ir_out, 4),
GROUP(pwm_i_d, 4),
GROUP(pwm_j_d, 4),
GROUP(i2c3_sda_d, 4),
GROUP(i2c3_scl_d, 4),
/* Bank D func5 */
GROUP(tdm_fs0_d, 5),
GROUP(tdm_sclk0_d, 5),
GROUP(mclk_0_d, 5),
GROUP(tdm_d1_d, 5),
GROUP(tdm_d0_d, 5),
/* Bank D func6 */
GROUP(uart_d_tx_d, 6),
GROUP(uart_d_rx_d, 6),
GROUP(uart_c_tx_d, 6),
GROUP(uart_c_rx_d, 6),
/* Bank A func1 */
GROUP(uart_b_tx_a, 1),
GROUP(uart_b_rx_a, 1),
GROUP(pwm_c, 1),
GROUP(pwm_l_a, 1),
GROUP(i2c1_sda_a, 1),
GROUP(i2c1_scl_a, 1),
/* Bank A func2 */
GROUP(pwm_c_hiz, 2),
GROUP(gen_clk_a, 2),
GROUP(pdm_dclk_z, 2),
GROUP(pdm_din0_a, 2),
/* Bank A func3 */
GROUP(jtag_a_clk, 3),
GROUP(jtag_a_tms, 3),
GROUP(jtag_a_tdi, 3),
GROUP(jtag_a_tdo, 3),
/* Bank A func4 */
GROUP(lcd_clk_a, 4),
GROUP(uart_f_tx_a, 4),
GROUP(uart_f_rx_a, 4),
/* Bank A func5 */
GROUP(uart_e_tx_a, 5),
GROUP(uart_e_rx_a, 5),
GROUP(pwm_m_a, 5),
GROUP(pwm_n_a, 5),
/* Bank A func6 */
GROUP(spi_a_mosi_a, 6),
GROUP(gen_clk_a4, 6),
GROUP(clk12_24_a, 6),
};
static const char * const gpio_periphs_groups[] = {
"GPIO_TEST_N",
"GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4",
"GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
"GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9",
"GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13",
"GPIOB_14",
"GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
"GPIOC_5", "GPIOC_6",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13",
"GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4",
"GPIOD_5", "GPIOD_6",
"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
"GPIOA_5",
};
static const char * const uart_a_groups[] = {
"uart_a_tx_b", "uart_a_rx_b", "uart_a_cts_b", "uart_a_rts_b",
"uart_a_rx_c", "uart_a_tx_c", "uart_a_rx_x", "uart_a_tx_x",
"uart_a_tx_d", "uart_a_rx_d",
};
static const char * const uart_b_groups[] = {
"uart_b_rx_c", "uart_b_tx_c", "uart_b_tx_a", "uart_b_rx_a",
};
static const char * const uart_c_groups[] = {
"uart_c_rx_c", "uart_c_tx_c",
"uart_c_rx_x", "uart_c_tx_x",
"uart_c_tx_d", "uart_c_rx_d",
};
static const char * const uart_d_groups[] = {
"uart_d_tx_b", "uart_d_rx_b", "uart_d_tx_d", "uart_d_rx_d",
"uart_d_rx_x", "uart_d_tx_x",
};
static const char * const uart_e_groups[] = {
"uart_e_cts", "uart_e_tx_x", "uart_e_rx_x", "uart_e_rts",
"uart_e_tx_a", "uart_e_rx_a",
};
static const char * const i2c0_groups[] = {
"i2c0_sda_e", "i2c0_scl_e",
"i2c0_sda_d", "i2c0_scl_d",
};
static const char * const i2c1_groups[] = {
"i2c1_sda_x", "i2c1_scl_x",
"i2c1_sda_d", "i2c1_scl_d",
"i2c1_sda_a", "i2c1_scl_a",
"i2c1_sda_b", "i2c1_scl_b",
};
static const char * const i2c2_groups[] = {
"i2c2_sda", "i2c2_scl",
};
static const char * const i2c3_groups[] = {
"i2c3_sda_c", "i2c3_scl_c",
"i2c3_sda_x", "i2c3_scl_x",
"i2c3_sda_d", "i2c3_scl_d",
};
static const char * const i2c_slave_groups[] = {
"i2c_slave_scl", "i2c_slave_sda",
};
static const char * const pwm_a_groups[] = {
"pwm_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b",
};
static const char * const pwm_c_groups[] = {
"pwm_c",
};
static const char * const pwm_d_groups[] = {
"pwm_d",
};
static const char * const pwm_e_groups[] = {
"pwm_e",
};
static const char * const pwm_f_groups[] = {
"pwm_f",
};
static const char * const pwm_g_groups[] = {
"pwm_g_b", "pwm_g_c", "pwm_g_d", "pwm_g_x0", "pwm_g_x8",
};
static const char * const pwm_h_groups[] = {
"pwm_h_b", "pwm_h_c", "pwm_h_d", "pwm_h_x1", "pwm_h_x9",
};
static const char * const pwm_i_groups[] = {
"pwm_i_b", "pwm_i_c", "pwm_i_d", "pwm_i_x2", "pwm_i_x10",
};
static const char * const pwm_j_groups[] = {
"pwm_j_c", "pwm_j_d", "pwm_j_b", "pwm_j_x3", "pwm_j_x12",
};
static const char * const pwm_k_groups[] = {
"pwm_k_c", "pwm_k_d", "pwm_k_b", "pwm_k_x4", "pwm_k_x13",
};
static const char * const pwm_l_groups[] = {
"pwm_l_c", "pwm_l_x", "pwm_l_b", "pwm_l_a",
};
static const char * const pwm_m_groups[] = {
"pwm_m_c", "pwm_m_x", "pwm_m_a", "pwm_m_b",
};
static const char * const pwm_n_groups[] = {
"pwm_n_x", "pwm_n_a", "pwm_n_b",
};
static const char * const pwm_c_hiz_groups[] = {
"pwm_c_hiz",
};
static const char * const ir_out_groups[] = {
"ir_out",
};
static const char * const ir_in_groups[] = {
"ir_in_d0", "ir_in_d6",
};
static const char * const jtag_a_groups[] = {
"jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
};
static const char * const jtag_b_groups[] = {
"jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms",
};
static const char * const gen_clk_groups[] = {
"gen_clk_e", "gen_clk_c", "gen_clk_a", "gen_clk_x",
"gen_clk_a4",
};
static const char * const clk12_24_groups[] = {
"clk12_24_e", "clk12_24_c", "clk12_24_x", "clk12_24_a",
"clk12_24_x13", "clk12_24_x11",
};
static const char * const clk_32k_in_groups[] = {
"clk_32k_in",
};
static const char * const emmc_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds",
};
static const char * const nand_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds",
"nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle",
"nand_ce0",
};
static const char * const spif_groups[] = {
"spif_mo", "spif_mi", "spif_wp", "spif_cs",
"spif_clk", "spif_hold", "spif_clk_loop",
};
static const char * const spi_a_groups[] = {
"spi_a_clk_b", "spi_a_ss0_b", "spi_a_ss1_b", "spi_a_ss2_b",
"spi_a_mosi_b", "spi_a_miso_b",
"spi_a_clk_c", "spi_a_ss0_c", "spi_a_ss1_c",
"spi_a_mosi_c", "spi_a_miso_c",
"spi_a_clk_x", "spi_a_ss0_x", "spi_a_ss1_x", "spi_a_ss2_x",
"spi_a_mosi_x", "spi_a_miso_x",
"spi_a_mosi_a",
};
static const char * const spi_b_groups[] = {
"spi_b_clk_x", "spi_b_ss0_x", "spi_b_ss1_x", "spi_b_ss2_x6",
"spi_b_miso_x", "spi_b_mosi_x", "spi_b_ss2_x12",
"spi_b_clk_d", "spi_b_ss0_d", "spi_b_ss1_d", "spi_b_miso_d",
"spi_b_mosi_d",
};
static const char * const sdcard_groups[] = {
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
"sdcard_cd", "sdcard_clk", "sdcard_cmd",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_clk", "sdio_cmd",
};
static const char * const pdm_groups[] = {
"pdm_dclk_c", "pdm_din0_c", "pdm_dclk_d", "pdm_din0_d",
"pdm_dclk_z", "pdm_din0_a", "pdm_dclk_b", "pdm_din0_b",
"pdm_dclk_x5", "pdm_din0_x6", "pdm_din0_x9", "pdm_dclk_x10",
};
static const char * const eth_groups[] = {
"eth_led_act", "eth_led_link",
};
static const char * const mclk_0_groups[] = {
"mclk_0_x", "mclk_0_d",
};
static const char * const mclk_1_groups[] = {
"mclk_1",
};
static const char * const tdm_groups[] = {
"tdm_d3", "tdm_d2", "tdm_fs1", "tdm_d1_x", "tdm_d0_x",
"tdm_d1_d", "tdm_d0_d", "tdm_sclk1", "tdm_fs0_x", "tdm_fs0_d",
"tdm_sclk0_x", "tdm_sclk0_d",
};
static const char * const lcd_groups[] = {
"lcd_d0", "lcd_d1", "lcd_d2", "lcd_d3", "lcd_d4",
"lcd_d5", "lcd_d6", "lcd_d7", "lcd_d8", "lcd_d9",
"lcd_d10", "lcd_d11", "lcd_d12", "lcd_d13", "lcd_d14",
"lcd_d15", "lcd_d16", "lcd_d17", "lcd_den",
"lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs",
};
static struct meson_pmx_func c3_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(uart_d),
FUNCTION(uart_e),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2c_slave),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f),
FUNCTION(pwm_g),
FUNCTION(pwm_h),
FUNCTION(pwm_i),
FUNCTION(pwm_j),
FUNCTION(pwm_k),
FUNCTION(pwm_l),
FUNCTION(pwm_m),
FUNCTION(pwm_n),
FUNCTION(pwm_c_hiz),
FUNCTION(ir_out),
FUNCTION(ir_in),
FUNCTION(jtag_a),
FUNCTION(jtag_b),
FUNCTION(gen_clk),
FUNCTION(clk12_24),
FUNCTION(clk_32k_in),
FUNCTION(emmc),
FUNCTION(nand),
FUNCTION(spif),
FUNCTION(spi_a),
FUNCTION(spi_b),
FUNCTION(sdcard),
FUNCTION(sdio),
FUNCTION(pdm),
FUNCTION(eth),
FUNCTION(mclk_0),
FUNCTION(mclk_1),
FUNCTION(tdm),
FUNCTION(lcd),
};
static struct meson_bank c3_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53,
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
BANK_DS("D", GPIOD_0, GPIOD_6, 33, 39,
0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0),
BANK_DS("E", GPIOE_0, GPIOE_4, 22, 26,
0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0),
BANK_DS("C", GPIOC_0, GPIOC_6, 15, 21,
0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0),
BANK_DS("B", GPIOB_0, GPIOB_14, 0, 14,
0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0),
BANK_DS("A", GPIOA_0, GPIOA_5, 27, 32,
0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 54, 54,
0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0),
};
static struct meson_pmx_bank c3_periphs_pmx_banks[] = {
/* name first last reg offset */
BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0),
BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0),
BANK_PMX("C", GPIOC_0, GPIOC_6, 0x09, 0),
BANK_PMX("A", GPIOA_0, GPIOA_5, 0x0b, 0),
BANK_PMX("D", GPIOD_0, GPIOD_6, 0x10, 0),
BANK_PMX("E", GPIOE_0, GPIOE_4, 0x12, 0),
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0),
};
static struct meson_axg_pmx_data c3_periphs_pmx_banks_data = {
.pmx_banks = c3_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks),
};
static struct meson_pinctrl_data c3_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = c3_periphs_pins,
.groups = c3_periphs_groups,
.funcs = c3_periphs_functions,
.banks = c3_periphs_banks,
.num_pins = ARRAY_SIZE(c3_periphs_pins),
.num_groups = ARRAY_SIZE(c3_periphs_groups),
.num_funcs = ARRAY_SIZE(c3_periphs_functions),
.num_banks = ARRAY_SIZE(c3_periphs_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &c3_periphs_pmx_banks_data,
.parse_dt = &meson_a1_parse_dt_extra,
};
static const struct of_device_id c3_pinctrl_dt_match[] = {
{
.compatible = "amlogic,c3-periphs-pinctrl",
.data = &c3_periphs_pinctrl_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, c3_pinctrl_dt_match);
static struct platform_driver c3_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "amlogic-c3-pinctrl",
.of_match_table = c3_pinctrl_dt_match,
},
};
module_platform_driver(c3_pinctrl_driver);
MODULE_AUTHOR("Huqiang Qin <[email protected]>");
MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic C3 SoC");
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-amlogic-c3.c
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Pin controller and GPIO driver for Amlogic Meson A1 SoC.
*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Qianggui Song <[email protected]>
*/
#include <dt-bindings/gpio/meson-a1-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static const struct pinctrl_pin_desc meson_a1_periphs_pins[] = {
MESON_PIN(GPIOP_0),
MESON_PIN(GPIOP_1),
MESON_PIN(GPIOP_2),
MESON_PIN(GPIOP_3),
MESON_PIN(GPIOP_4),
MESON_PIN(GPIOP_5),
MESON_PIN(GPIOP_6),
MESON_PIN(GPIOP_7),
MESON_PIN(GPIOP_8),
MESON_PIN(GPIOP_9),
MESON_PIN(GPIOP_10),
MESON_PIN(GPIOP_11),
MESON_PIN(GPIOP_12),
MESON_PIN(GPIOB_0),
MESON_PIN(GPIOB_1),
MESON_PIN(GPIOB_2),
MESON_PIN(GPIOB_3),
MESON_PIN(GPIOB_4),
MESON_PIN(GPIOB_5),
MESON_PIN(GPIOB_6),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOF_0),
MESON_PIN(GPIOF_1),
MESON_PIN(GPIOF_2),
MESON_PIN(GPIOF_3),
MESON_PIN(GPIOF_4),
MESON_PIN(GPIOF_5),
MESON_PIN(GPIOF_6),
MESON_PIN(GPIOF_7),
MESON_PIN(GPIOF_8),
MESON_PIN(GPIOF_9),
MESON_PIN(GPIOF_10),
MESON_PIN(GPIOF_11),
MESON_PIN(GPIOF_12),
MESON_PIN(GPIOA_0),
MESON_PIN(GPIOA_1),
MESON_PIN(GPIOA_2),
MESON_PIN(GPIOA_3),
MESON_PIN(GPIOA_4),
MESON_PIN(GPIOA_5),
MESON_PIN(GPIOA_6),
MESON_PIN(GPIOA_7),
MESON_PIN(GPIOA_8),
MESON_PIN(GPIOA_9),
MESON_PIN(GPIOA_10),
MESON_PIN(GPIOA_11),
};
/* psram */
static const unsigned int psram_clkn_pins[] = { GPIOP_0 };
static const unsigned int psram_clkp_pins[] = { GPIOP_1 };
static const unsigned int psram_ce_n_pins[] = { GPIOP_2 };
static const unsigned int psram_rst_n_pins[] = { GPIOP_3 };
static const unsigned int psram_adq0_pins[] = { GPIOP_4 };
static const unsigned int psram_adq1_pins[] = { GPIOP_5 };
static const unsigned int psram_adq2_pins[] = { GPIOP_6 };
static const unsigned int psram_adq3_pins[] = { GPIOP_7 };
static const unsigned int psram_adq4_pins[] = { GPIOP_8 };
static const unsigned int psram_adq5_pins[] = { GPIOP_9 };
static const unsigned int psram_adq6_pins[] = { GPIOP_10 };
static const unsigned int psram_adq7_pins[] = { GPIOP_11 };
static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 };
/* sdcard */
static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 };
static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 };
static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 };
static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 };
static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 };
static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 };
static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 };
/* spif */
static const unsigned int spif_mo_pins[] = { GPIOB_0 };
static const unsigned int spif_mi_pins[] = { GPIOB_1 };
static const unsigned int spif_wp_n_pins[] = { GPIOB_2 };
static const unsigned int spif_hold_n_pins[] = { GPIOB_3 };
static const unsigned int spif_clk_pins[] = { GPIOB_4 };
static const unsigned int spif_cs_pins[] = { GPIOB_5 };
/* i2c0 */
static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 };
static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 };
static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 };
static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 };
/* i2c1 */
static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 };
static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 };
static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 };
static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 };
/* i2c2 */
static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 };
static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 };
static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 };
static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 };
static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 };
static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 };
static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 };
static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 };
/* i2c3 */
static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 };
static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 };
static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 };
static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 };
/* i2c slave */
static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 };
static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 };
static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 };
static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 };
/* uart_a */
static const unsigned int uart_a_tx_pins[] = { GPIOX_11 };
static const unsigned int uart_a_rx_pins[] = { GPIOX_12 };
static const unsigned int uart_a_cts_pins[] = { GPIOX_13 };
static const unsigned int uart_a_rts_pins[] = { GPIOX_14 };
/* uart_b */
static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 };
static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 };
static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 };
static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 };
/* uart_c */
static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 };
static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 };
static const unsigned int uart_c_cts_pins[] = { GPIOX_2 };
static const unsigned int uart_c_rts_pins[] = { GPIOX_3 };
static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 };
static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 };
/* pmw_a */
static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 };
static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 };
static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 };
static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 };
static const unsigned int pwm_a_a_pins[] = { GPIOA_5 };
/* pmw_b */
static const unsigned int pwm_b_x_pins[] = { GPIOX_8 };
static const unsigned int pwm_b_f_pins[] = { GPIOF_7 };
static const unsigned int pwm_b_a_pins[] = { GPIOA_11 };
/* pmw_c */
static const unsigned int pwm_c_x_pins[] = { GPIOX_9 };
static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 };
static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 };
static const unsigned int pwm_c_a_pins[] = { GPIOA_10 };
/* pwm_d */
static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 };
static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 };
static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 };
static const unsigned int pwm_d_f_pins[] = { GPIOF_11 };
/* pwm_e */
static const unsigned int pwm_e_p_pins[] = { GPIOP_3 };
static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 };
static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 };
static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 };
static const unsigned int pwm_e_f_pins[] = { GPIOF_3 };
static const unsigned int pwm_e_a_pins[] = { GPIOA_0 };
/* pwm_f */
static const unsigned int pwm_f_b_pins[] = { GPIOB_6 };
static const unsigned int pwm_f_x_pins[] = { GPIOX_3 };
static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 };
static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 };
/* pwm_a_hiz */
static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 };
static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 };
static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 };
/* pwm_b_hiz */
static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 };
/* pmw_c_hiz */
static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 };
/* tdm_a */
static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 };
static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 };
static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 };
static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 };
static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 };
static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 };
static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 };
static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 };
/* spi_a */
static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 };
static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 };
static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 };
static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 };
static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 };
static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 };
static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 };
static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 };
static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 };
static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 };
static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 };
/* pdm */
static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 };
static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 };
static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 };
static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 };
static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 };
static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
static const unsigned int pdm_dclk_pins[] = { GPIOA_9 };
/* gen_clk */
static const unsigned int gen_clk_x_pins[] = { GPIOX_7 };
static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 };
static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 };
static const unsigned int gen_clk_a_pins[] = { GPIOA_11 };
/* jtag_a */
static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 };
static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 };
static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 };
static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 };
/* clk_32_in */
static const unsigned int clk_32k_in_pins[] = { GPIOF_2 };
/* ir in */
static const unsigned int remote_input_f_pins[] = { GPIOF_3 };
static const unsigned int remote_input_a_pins[] = { GPIOA_11 };
/* ir out */
static const unsigned int remote_out_pins[] = { GPIOF_5 };
/* spdif */
static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 };
static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 };
/* sw */
static const unsigned int swclk_pins[] = { GPIOF_4 };
static const unsigned int swdio_pins[] = { GPIOF_5 };
/* clk_25 */
static const unsigned int clk25_pins[] = { GPIOF_10 };
/* cec_a */
static const unsigned int cec_a_pins[] = { GPIOF_2 };
/* cec_b */
static const unsigned int cec_b_pins[] = { GPIOF_2 };
/* clk12_24 */
static const unsigned int clk12_24_pins[] = { GPIOF_10 };
/* mclk_0 */
static const unsigned int mclk_0_pins[] = { GPIOA_0 };
/* tdm_b */
static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 };
static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 };
static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 };
static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 };
static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 };
static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 };
static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 };
/* mclk_vad */
static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
/* tdm_vad */
static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
/* tst_out */
static const unsigned int tst_out0_pins[] = { GPIOA_0 };
static const unsigned int tst_out1_pins[] = { GPIOA_1 };
static const unsigned int tst_out2_pins[] = { GPIOA_2 };
static const unsigned int tst_out3_pins[] = { GPIOA_3 };
static const unsigned int tst_out4_pins[] = { GPIOA_4 };
static const unsigned int tst_out5_pins[] = { GPIOA_5 };
static const unsigned int tst_out6_pins[] = { GPIOA_6 };
static const unsigned int tst_out7_pins[] = { GPIOA_7 };
static const unsigned int tst_out8_pins[] = { GPIOA_8 };
static const unsigned int tst_out9_pins[] = { GPIOA_9 };
static const unsigned int tst_out10_pins[] = { GPIOA_10 };
static const unsigned int tst_out11_pins[] = { GPIOA_11 };
/* mute */
static const unsigned int mute_key_pins[] = { GPIOA_4 };
static const unsigned int mute_en_pins[] = { GPIOA_5 };
static struct meson_pmx_group meson_a1_periphs_groups[] = {
GPIO_GROUP(GPIOP_0),
GPIO_GROUP(GPIOP_1),
GPIO_GROUP(GPIOP_2),
GPIO_GROUP(GPIOP_3),
GPIO_GROUP(GPIOP_4),
GPIO_GROUP(GPIOP_5),
GPIO_GROUP(GPIOP_6),
GPIO_GROUP(GPIOP_7),
GPIO_GROUP(GPIOP_8),
GPIO_GROUP(GPIOP_9),
GPIO_GROUP(GPIOP_10),
GPIO_GROUP(GPIOP_11),
GPIO_GROUP(GPIOP_12),
GPIO_GROUP(GPIOB_0),
GPIO_GROUP(GPIOB_1),
GPIO_GROUP(GPIOB_2),
GPIO_GROUP(GPIOB_3),
GPIO_GROUP(GPIOB_4),
GPIO_GROUP(GPIOB_5),
GPIO_GROUP(GPIOB_6),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOF_0),
GPIO_GROUP(GPIOF_1),
GPIO_GROUP(GPIOF_2),
GPIO_GROUP(GPIOF_3),
GPIO_GROUP(GPIOF_4),
GPIO_GROUP(GPIOF_5),
GPIO_GROUP(GPIOF_6),
GPIO_GROUP(GPIOF_7),
GPIO_GROUP(GPIOF_8),
GPIO_GROUP(GPIOF_9),
GPIO_GROUP(GPIOF_10),
GPIO_GROUP(GPIOF_11),
GPIO_GROUP(GPIOF_12),
GPIO_GROUP(GPIOA_0),
GPIO_GROUP(GPIOA_1),
GPIO_GROUP(GPIOA_2),
GPIO_GROUP(GPIOA_3),
GPIO_GROUP(GPIOA_4),
GPIO_GROUP(GPIOA_5),
GPIO_GROUP(GPIOA_6),
GPIO_GROUP(GPIOA_7),
GPIO_GROUP(GPIOA_8),
GPIO_GROUP(GPIOA_9),
GPIO_GROUP(GPIOA_10),
GPIO_GROUP(GPIOA_11),
/* bank P func1 */
GROUP(psram_clkn, 1),
GROUP(psram_clkp, 1),
GROUP(psram_ce_n, 1),
GROUP(psram_rst_n, 1),
GROUP(psram_adq0, 1),
GROUP(psram_adq1, 1),
GROUP(psram_adq2, 1),
GROUP(psram_adq3, 1),
GROUP(psram_adq4, 1),
GROUP(psram_adq5, 1),
GROUP(psram_adq6, 1),
GROUP(psram_adq7, 1),
GROUP(psram_dqs_dm, 1),
/*bank P func2 */
GROUP(pwm_e_p, 2),
/*bank B func1 */
GROUP(spif_mo, 1),
GROUP(spif_mi, 1),
GROUP(spif_wp_n, 1),
GROUP(spif_hold_n, 1),
GROUP(spif_clk, 1),
GROUP(spif_cs, 1),
GROUP(pwm_f_b, 1),
/*bank B func2 */
GROUP(sdcard_d0_b, 2),
GROUP(sdcard_d1_b, 2),
GROUP(sdcard_d2_b, 2),
GROUP(sdcard_d3_b, 2),
GROUP(sdcard_clk_b, 2),
GROUP(sdcard_cmd_b, 2),
/*bank X func1 */
GROUP(sdcard_d0_x, 1),
GROUP(sdcard_d1_x, 1),
GROUP(sdcard_d2_x, 1),
GROUP(sdcard_d3_x, 1),
GROUP(sdcard_clk_x, 1),
GROUP(sdcard_cmd_x, 1),
GROUP(pwm_a_x6, 1),
GROUP(tdm_a_dout1, 1),
GROUP(tdm_a_dout0, 1),
GROUP(tdm_a_fs, 1),
GROUP(tdm_a_sclk, 1),
GROUP(uart_a_tx, 1),
GROUP(uart_a_rx, 1),
GROUP(uart_a_cts, 1),
GROUP(uart_a_rts, 1),
GROUP(pwm_d_x15, 1),
GROUP(pwm_e_x16, 1),
/*bank X func2 */
GROUP(i2c2_sck_x0, 2),
GROUP(i2c2_sda_x1, 2),
GROUP(spi_a_mosi_x2, 2),
GROUP(spi_a_ss0_x3, 2),
GROUP(spi_a_sclk_x4, 2),
GROUP(spi_a_miso_x5, 2),
GROUP(tdm_a_din1, 2),
GROUP(tdm_a_din0, 2),
GROUP(tdm_a_slv_fs, 2),
GROUP(tdm_a_slv_sclk, 2),
GROUP(i2c3_sck_x, 2),
GROUP(i2c3_sda_x, 2),
GROUP(pwm_d_x13, 2),
GROUP(pwm_e_x14, 2),
GROUP(i2c2_sck_x15, 2),
GROUP(i2c2_sda_x16, 2),
/*bank X func3 */
GROUP(uart_c_tx_x0, 3),
GROUP(uart_c_rx_x1, 3),
GROUP(uart_c_cts, 3),
GROUP(uart_c_rts, 3),
GROUP(pdm_din0_x, 3),
GROUP(pdm_din1_x, 3),
GROUP(pdm_din2_x, 3),
GROUP(pdm_dclk_x, 3),
GROUP(uart_c_tx_x15, 3),
GROUP(uart_c_rx_x16, 3),
/*bank X func4 */
GROUP(pwm_e_x2, 4),
GROUP(pwm_f_x, 4),
GROUP(spi_a_mosi_x7, 4),
GROUP(spi_a_miso_x8, 4),
GROUP(spi_a_ss0_x9, 4),
GROUP(spi_a_sclk_x10, 4),
/*bank X func5 */
GROUP(uart_b_tx_x, 5),
GROUP(uart_b_rx_x, 5),
GROUP(i2c1_sda_x, 5),
GROUP(i2c1_sck_x, 5),
/*bank X func6 */
GROUP(pwm_a_x7, 6),
GROUP(pwm_b_x, 6),
GROUP(pwm_c_x, 6),
GROUP(pwm_d_x10, 6),
/*bank X func7 */
GROUP(gen_clk_x, 7),
/*bank F func1 */
GROUP(uart_b_tx_f, 1),
GROUP(uart_b_rx_f, 1),
GROUP(remote_input_f, 1),
GROUP(jtag_a_clk, 1),
GROUP(jtag_a_tms, 1),
GROUP(jtag_a_tdi, 1),
GROUP(jtag_a_tdo, 1),
GROUP(gen_clk_f8, 1),
GROUP(pwm_a_f10, 1),
GROUP(i2c0_sck_f11, 1),
GROUP(i2c0_sda_f12, 1),
/*bank F func2 */
GROUP(clk_32k_in, 2),
GROUP(pwm_e_f, 2),
GROUP(pwm_f_f4, 2),
GROUP(remote_out, 2),
GROUP(spdif_in_f6, 2),
GROUP(spdif_in_f7, 2),
GROUP(pwm_a_hiz_f8, 2),
GROUP(pwm_a_hiz_f10, 2),
GROUP(pwm_d_f, 2),
GROUP(pwm_f_f12, 2),
/*bank F func3 */
GROUP(pwm_c_f3, 3),
GROUP(swclk, 3),
GROUP(swdio, 3),
GROUP(pwm_a_f6, 3),
GROUP(pwm_b_f, 3),
GROUP(pwm_c_f8, 3),
GROUP(clk25, 3),
GROUP(i2c_slave_sck_f, 3),
GROUP(i2c_slave_sda_f, 3),
/*bank F func4 */
GROUP(cec_a, 4),
GROUP(i2c3_sck_f, 4),
GROUP(i2c3_sda_f, 4),
GROUP(pmw_a_hiz_f6, 4),
GROUP(pwm_b_hiz, 4),
GROUP(pwm_c_hiz, 4),
GROUP(i2c0_sck_f9, 4),
GROUP(i2c0_sda_f10, 4),
/*bank F func5 */
GROUP(cec_b, 5),
GROUP(clk12_24, 5),
/*bank F func7 */
GROUP(gen_clk_f10, 7),
/*bank A func1 */
GROUP(mclk_0, 1),
GROUP(tdm_b_sclk, 1),
GROUP(tdm_b_fs, 1),
GROUP(tdm_b_dout0, 1),
GROUP(tdm_b_dout1, 1),
GROUP(tdm_b_dout2, 1),
GROUP(tdm_b_dout3, 1),
GROUP(tdm_b_dout4, 1),
GROUP(tdm_b_dout5, 1),
GROUP(remote_input_a, 1),
/*bank A func2 */
GROUP(pwm_e_a, 2),
GROUP(tdm_b_slv_sclk, 2),
GROUP(tdm_b_slv_fs, 2),
GROUP(tdm_b_din0, 2),
GROUP(tdm_b_din1, 2),
GROUP(tdm_b_din2, 2),
GROUP(i2c1_sda_a, 2),
GROUP(i2c1_sck_a, 2),
/*bank A func3 */
GROUP(i2c2_sck_a4, 3),
GROUP(i2c2_sda_a5, 3),
GROUP(pdm_din2_a, 3),
GROUP(pdm_din1_a, 3),
GROUP(pdm_din0_a, 3),
GROUP(pdm_dclk, 3),
GROUP(pwm_c_a, 3),
GROUP(pwm_b_a, 3),
/*bank A func4 */
GROUP(pwm_a_a, 4),
GROUP(spi_a_mosi_a, 4),
GROUP(spi_a_miso_a, 4),
GROUP(spi_a_ss0_a, 4),
GROUP(spi_a_sclk_a, 4),
GROUP(i2c_slave_sck_a, 4),
GROUP(i2c_slave_sda_a, 4),
/*bank A func5 */
GROUP(mclk_vad, 5),
GROUP(tdm_vad_sclk_a1, 5),
GROUP(tdm_vad_fs_a2, 5),
GROUP(tdm_vad_sclk_a5, 5),
GROUP(tdm_vad_fs_a6, 5),
GROUP(i2c2_sck_a8, 5),
GROUP(i2c2_sda_a9, 5),
/*bank A func6 */
GROUP(tst_out0, 6),
GROUP(tst_out1, 6),
GROUP(tst_out2, 6),
GROUP(tst_out3, 6),
GROUP(tst_out4, 6),
GROUP(tst_out5, 6),
GROUP(tst_out6, 6),
GROUP(tst_out7, 6),
GROUP(tst_out8, 6),
GROUP(tst_out9, 6),
GROUP(tst_out10, 6),
GROUP(tst_out11, 6),
/*bank A func7 */
GROUP(mute_key, 7),
GROUP(mute_en, 7),
GROUP(gen_clk_a, 7),
};
static const char * const gpio_periphs_groups[] = {
"GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
"GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
"GPIOP_10", "GPIOP_11", "GPIOP_12",
"GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
"GPIOB_5", "GPIOB_6",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16",
"GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
"GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
"GPIOF_10", "GPIOF_11", "GPIOF_12",
"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
"GPIOA_10", "GPIOA_11",
};
static const char * const psram_groups[] = {
"psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
"psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
"psram_adq6", "psram_adq7", "psram_dqs_dm",
};
static const char * const pwm_a_groups[] = {
"pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b_x", "pwm_b_f", "pwm_b_a",
};
static const char * const pwm_c_groups[] = {
"pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
};
static const char * const pwm_d_groups[] = {
"pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
};
static const char * const pwm_e_groups[] = {
"pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
"pwm_e_a",
};
static const char * const pwm_f_groups[] = {
"pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
};
static const char * const pwm_a_hiz_groups[] = {
"pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6",
};
static const char * const pwm_b_hiz_groups[] = {
"pwm_b_hiz",
};
static const char * const pwm_c_hiz_groups[] = {
"pwm_c_hiz",
};
static const char * const spif_groups[] = {
"spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
"spif_cs",
};
static const char * const sdcard_groups[] = {
"sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
"sdcard_clk_b", "sdcard_cmd_b",
"sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
"sdcard_clk_x", "sdcard_cmd_x",
};
static const char * const tdm_a_groups[] = {
"tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk",
"tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1",
};
static const char * const uart_a_groups[] = {
"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
};
static const char * const uart_b_groups[] = {
"uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
};
static const char * const uart_c_groups[] = {
"uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
"uart_c_tx_x15", "uart_c_rx_x16",
};
static const char * const i2c0_groups[] = {
"i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10",
};
static const char * const i2c1_groups[] = {
"i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a",
};
static const char * const i2c2_groups[] = {
"i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16",
"i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9",
};
static const char * const i2c3_groups[] = {
"i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
};
static const char * const spi_a_groups[] = {
"spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
"spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
"spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
};
static const char * const pdm_groups[] = {
"pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
"pdm_din1_a", "pdm_din0_a", "pdm_dclk",
};
static const char * const gen_clk_groups[] = {
"gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
};
static const char * const remote_input_groups[] = {
"remote_input_f",
"remote_input_a",
};
static const char * const jtag_a_groups[] = {
"jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
};
static const char * const clk_32k_in_groups[] = {
"clk_32k_in",
};
static const char * const remote_out_groups[] = {
"remote_out",
};
static const char * const spdif_in_groups[] = {
"spdif_in_f6", "spdif_in_f7",
};
static const char * const sw_groups[] = {
"swclk", "swdio",
};
static const char * const clk25_groups[] = {
"clk_25",
};
static const char * const cec_a_groups[] = {
"cec_a",
};
static const char * const cec_b_groups[] = {
"cec_b",
};
static const char * const clk12_24_groups[] = {
"clk12_24",
};
static const char * const mclk_0_groups[] = {
"mclk_0",
};
static const char * const tdm_b_groups[] = {
"tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
"tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
"tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
"tdm_b_slv_sclk", "tdm_b_slv_fs",
};
static const char * const mclk_vad_groups[] = {
"mclk_vad",
};
static const char * const tdm_vad_groups[] = {
"tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
};
static const char * const tst_out_groups[] = {
"tst_out0", "tst_out1", "tst_out2", "tst_out3",
"tst_out4", "tst_out5", "tst_out6", "tst_out7",
"tst_out8", "tst_out9", "tst_out10", "tst_out11",
};
static const char * const mute_groups[] = {
"mute_key", "mute_en",
};
static struct meson_pmx_func meson_a1_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(psram),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f),
FUNCTION(pwm_a_hiz),
FUNCTION(pwm_b_hiz),
FUNCTION(pwm_c_hiz),
FUNCTION(spif),
FUNCTION(sdcard),
FUNCTION(tdm_a),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(spi_a),
FUNCTION(pdm),
FUNCTION(gen_clk),
FUNCTION(remote_input),
FUNCTION(jtag_a),
FUNCTION(clk_32k_in),
FUNCTION(remote_out),
FUNCTION(spdif_in),
FUNCTION(sw),
FUNCTION(clk25),
FUNCTION(cec_a),
FUNCTION(cec_b),
FUNCTION(clk12_24),
FUNCTION(mclk_0),
FUNCTION(tdm_b),
FUNCTION(mclk_vad),
FUNCTION(tdm_vad),
FUNCTION(tst_out),
FUNCTION(mute),
};
static struct meson_bank meson_a1_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds*/
BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
BANK_DS("B", GPIOB_0, GPIOB_6, 13, 19, 0x13, 0, 0x14, 0,
0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0),
BANK_DS("X", GPIOX_0, GPIOX_16, 20, 36, 0x23, 0, 0x24, 0,
0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0),
BANK_DS("F", GPIOF_0, GPIOF_12, 37, 49, 0x33, 0, 0x34, 0,
0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0),
BANK_DS("A", GPIOA_0, GPIOA_11, 50, 61, 0x43, 0, 0x44, 0,
0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
};
static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
/* name first lask reg offset */
BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0),
BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0),
BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
};
static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
.pmx_banks = meson_a1_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
};
static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_a1_periphs_pins,
.groups = meson_a1_periphs_groups,
.funcs = meson_a1_periphs_functions,
.banks = meson_a1_periphs_banks,
.num_pins = ARRAY_SIZE(meson_a1_periphs_pins),
.num_groups = ARRAY_SIZE(meson_a1_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_a1_periphs_functions),
.num_banks = ARRAY_SIZE(meson_a1_periphs_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_a1_periphs_pmx_banks_data,
.parse_dt = &meson_a1_parse_dt_extra,
};
static const struct of_device_id meson_a1_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-a1-periphs-pinctrl",
.data = &meson_a1_periphs_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_a1_pinctrl_dt_match);
static struct platform_driver meson_a1_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-a1-pinctrl",
.of_match_table = meson_a1_pinctrl_dt_match,
},
};
module_platform_driver(meson_a1_pinctrl_driver);
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-a1.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pin controller and GPIO driver for Amlogic Meson GXBB.
*
* Copyright (C) 2016 Endless Mobile, Inc.
* Author: Carlo Caione <[email protected]>
*/
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson8-pmx.h"
static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(GPIOZ_11),
MESON_PIN(GPIOZ_12),
MESON_PIN(GPIOZ_13),
MESON_PIN(GPIOZ_14),
MESON_PIN(GPIOZ_15),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(BOOT_15),
MESON_PIN(BOOT_16),
MESON_PIN(BOOT_17),
MESON_PIN(CARD_0),
MESON_PIN(CARD_1),
MESON_PIN(CARD_2),
MESON_PIN(CARD_3),
MESON_PIN(CARD_4),
MESON_PIN(CARD_5),
MESON_PIN(CARD_6),
MESON_PIN(GPIODV_0),
MESON_PIN(GPIODV_1),
MESON_PIN(GPIODV_2),
MESON_PIN(GPIODV_3),
MESON_PIN(GPIODV_4),
MESON_PIN(GPIODV_5),
MESON_PIN(GPIODV_6),
MESON_PIN(GPIODV_7),
MESON_PIN(GPIODV_8),
MESON_PIN(GPIODV_9),
MESON_PIN(GPIODV_10),
MESON_PIN(GPIODV_11),
MESON_PIN(GPIODV_12),
MESON_PIN(GPIODV_13),
MESON_PIN(GPIODV_14),
MESON_PIN(GPIODV_15),
MESON_PIN(GPIODV_16),
MESON_PIN(GPIODV_17),
MESON_PIN(GPIODV_18),
MESON_PIN(GPIODV_19),
MESON_PIN(GPIODV_20),
MESON_PIN(GPIODV_21),
MESON_PIN(GPIODV_22),
MESON_PIN(GPIODV_23),
MESON_PIN(GPIODV_24),
MESON_PIN(GPIODV_25),
MESON_PIN(GPIODV_26),
MESON_PIN(GPIODV_27),
MESON_PIN(GPIODV_28),
MESON_PIN(GPIODV_29),
MESON_PIN(GPIOY_0),
MESON_PIN(GPIOY_1),
MESON_PIN(GPIOY_2),
MESON_PIN(GPIOY_3),
MESON_PIN(GPIOY_4),
MESON_PIN(GPIOY_5),
MESON_PIN(GPIOY_6),
MESON_PIN(GPIOY_7),
MESON_PIN(GPIOY_8),
MESON_PIN(GPIOY_9),
MESON_PIN(GPIOY_10),
MESON_PIN(GPIOY_11),
MESON_PIN(GPIOY_12),
MESON_PIN(GPIOY_13),
MESON_PIN(GPIOY_14),
MESON_PIN(GPIOY_15),
MESON_PIN(GPIOY_16),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
MESON_PIN(GPIOX_20),
MESON_PIN(GPIOX_21),
MESON_PIN(GPIOX_22),
MESON_PIN(GPIOCLK_0),
MESON_PIN(GPIOCLK_1),
MESON_PIN(GPIOCLK_2),
MESON_PIN(GPIOCLK_3),
};
static const unsigned int emmc_nand_d07_pins[] = {
BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7,
};
static const unsigned int emmc_clk_pins[] = { BOOT_8 };
static const unsigned int emmc_cmd_pins[] = { BOOT_10 };
static const unsigned int emmc_ds_pins[] = { BOOT_15 };
static const unsigned int nor_d_pins[] = { BOOT_11 };
static const unsigned int nor_q_pins[] = { BOOT_12 };
static const unsigned int nor_c_pins[] = { BOOT_13 };
static const unsigned int nor_cs_pins[] = { BOOT_15 };
static const unsigned int spi_sclk_pins[] = { GPIOZ_6 };
static const unsigned int spi_ss0_pins[] = { GPIOZ_7 };
static const unsigned int spi_miso_pins[] = { GPIOZ_12 };
static const unsigned int spi_mosi_pins[] = { GPIOZ_13 };
static const unsigned int sdcard_d0_pins[] = { CARD_1 };
static const unsigned int sdcard_d1_pins[] = { CARD_0 };
static const unsigned int sdcard_d2_pins[] = { CARD_5 };
static const unsigned int sdcard_d3_pins[] = { CARD_4 };
static const unsigned int sdcard_cmd_pins[] = { CARD_3 };
static const unsigned int sdcard_clk_pins[] = { CARD_2 };
static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
static const unsigned int sdio_cmd_pins[] = { GPIOX_4 };
static const unsigned int sdio_clk_pins[] = { GPIOX_5 };
static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
static const unsigned int nand_ce0_pins[] = { BOOT_8 };
static const unsigned int nand_ce1_pins[] = { BOOT_9 };
static const unsigned int nand_rb0_pins[] = { BOOT_10 };
static const unsigned int nand_ale_pins[] = { BOOT_11 };
static const unsigned int nand_cle_pins[] = { BOOT_12 };
static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
static const unsigned int nand_ren_wr_pins[] = { BOOT_14 };
static const unsigned int nand_dqs_pins[] = { BOOT_15 };
static const unsigned int uart_tx_a_pins[] = { GPIOX_12 };
static const unsigned int uart_rx_a_pins[] = { GPIOX_13 };
static const unsigned int uart_cts_a_pins[] = { GPIOX_14 };
static const unsigned int uart_rts_a_pins[] = { GPIOX_15 };
static const unsigned int uart_tx_b_pins[] = { GPIODV_24 };
static const unsigned int uart_rx_b_pins[] = { GPIODV_25 };
static const unsigned int uart_cts_b_pins[] = { GPIODV_26 };
static const unsigned int uart_rts_b_pins[] = { GPIODV_27 };
static const unsigned int uart_tx_c_pins[] = { GPIOY_13 };
static const unsigned int uart_rx_c_pins[] = { GPIOY_14 };
static const unsigned int uart_cts_c_pins[] = { GPIOY_11 };
static const unsigned int uart_rts_c_pins[] = { GPIOY_12 };
static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 };
static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 };
static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 };
static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 };
static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };
static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 };
static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 };
static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 };
static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
static const unsigned int eth_txd2_pins[] = { GPIOZ_12 };
static const unsigned int eth_txd3_pins[] = { GPIOZ_13 };
static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
static const unsigned int pwm_b_pins[] = { GPIODV_29 };
static const unsigned int pwm_d_pins[] = { GPIODV_28 };
static const unsigned int pwm_e_pins[] = { GPIOX_19 };
static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
static const unsigned int pwm_f_y_pins[] = { GPIOY_15 };
static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
static const unsigned int tsin_a_d_valid_pins[] = { GPIOY_0 };
static const unsigned int tsin_a_sop_pins[] = { GPIOY_1 };
static const unsigned int tsin_a_clk_pins[] = { GPIOY_2 };
static const unsigned int tsin_a_d0_pins[] = { GPIOY_3 };
static const unsigned int tsin_a_dp_pins[] = {
GPIOY_4, GPIOY_5, GPIOY_6, GPIOY_7, GPIOY_8, GPIOY_9, GPIOY_10
};
static const unsigned int tsin_a_fail_pins[] = { GPIOY_11 };
static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 };
static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 };
static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 };
static const unsigned int tsin_b_d_valid_pins[] = { GPIOX_6 };
static const unsigned int tsin_b_sop_pins[] = { GPIOX_7 };
static const unsigned int tsin_b_clk_pins[] = { GPIOX_8 };
static const unsigned int tsin_b_d0_pins[] = { GPIOX_9 };
static const unsigned int spdif_out_y_pins[] = { GPIOY_12 };
static const unsigned int gen_clk_out_pins[] = { GPIOY_15 };
static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIOAO_10),
MESON_PIN(GPIOAO_11),
MESON_PIN(GPIOAO_12),
MESON_PIN(GPIOAO_13),
MESON_PIN(GPIO_TEST_N),
};
static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 };
static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 };
static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 };
static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 };
static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 };
static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 };
static const unsigned int remote_input_ao_pins[] = { GPIOAO_7 };
static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 };
static const unsigned int pwm_ao_a_6_pins[] = { GPIOAO_6 };
static const unsigned int pwm_ao_a_12_pins[] = { GPIOAO_12 };
static const unsigned int pwm_ao_b_pins[] = { GPIOAO_13 };
static const unsigned int i2s_am_clk_pins[] = { GPIOAO_8 };
static const unsigned int i2s_out_ao_clk_pins[] = { GPIOAO_9 };
static const unsigned int i2s_out_lr_clk_pins[] = { GPIOAO_10 };
static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_12 };
static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_13 };
static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N };
static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 };
static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 };
static const unsigned int ao_cec_pins[] = { GPIOAO_12 };
static const unsigned int ee_cec_pins[] = { GPIOAO_12 };
static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(GPIOZ_11),
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(GPIOZ_15),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(GPIODV_0),
GPIO_GROUP(GPIODV_1),
GPIO_GROUP(GPIODV_2),
GPIO_GROUP(GPIODV_3),
GPIO_GROUP(GPIODV_4),
GPIO_GROUP(GPIODV_5),
GPIO_GROUP(GPIODV_6),
GPIO_GROUP(GPIODV_7),
GPIO_GROUP(GPIODV_8),
GPIO_GROUP(GPIODV_9),
GPIO_GROUP(GPIODV_10),
GPIO_GROUP(GPIODV_11),
GPIO_GROUP(GPIODV_12),
GPIO_GROUP(GPIODV_13),
GPIO_GROUP(GPIODV_14),
GPIO_GROUP(GPIODV_15),
GPIO_GROUP(GPIODV_16),
GPIO_GROUP(GPIODV_17),
GPIO_GROUP(GPIODV_19),
GPIO_GROUP(GPIODV_20),
GPIO_GROUP(GPIODV_21),
GPIO_GROUP(GPIODV_22),
GPIO_GROUP(GPIODV_23),
GPIO_GROUP(GPIODV_24),
GPIO_GROUP(GPIODV_25),
GPIO_GROUP(GPIODV_26),
GPIO_GROUP(GPIODV_27),
GPIO_GROUP(GPIODV_28),
GPIO_GROUP(GPIODV_29),
GPIO_GROUP(GPIOY_0),
GPIO_GROUP(GPIOY_1),
GPIO_GROUP(GPIOY_2),
GPIO_GROUP(GPIOY_3),
GPIO_GROUP(GPIOY_4),
GPIO_GROUP(GPIOY_5),
GPIO_GROUP(GPIOY_6),
GPIO_GROUP(GPIOY_7),
GPIO_GROUP(GPIOY_8),
GPIO_GROUP(GPIOY_9),
GPIO_GROUP(GPIOY_10),
GPIO_GROUP(GPIOY_11),
GPIO_GROUP(GPIOY_12),
GPIO_GROUP(GPIOY_13),
GPIO_GROUP(GPIOY_14),
GPIO_GROUP(GPIOY_15),
GPIO_GROUP(GPIOY_16),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
GPIO_GROUP(GPIOX_20),
GPIO_GROUP(GPIOX_21),
GPIO_GROUP(GPIOX_22),
GPIO_GROUP(GPIOCLK_0),
GPIO_GROUP(GPIOCLK_1),
GPIO_GROUP(GPIOCLK_2),
GPIO_GROUP(GPIOCLK_3),
GPIO_GROUP(GPIO_TEST_N),
/* Bank X */
GROUP(sdio_d0, 8, 5),
GROUP(sdio_d1, 8, 4),
GROUP(sdio_d2, 8, 3),
GROUP(sdio_d3, 8, 2),
GROUP(sdio_cmd, 8, 1),
GROUP(sdio_clk, 8, 0),
GROUP(sdio_irq, 8, 11),
GROUP(uart_tx_a, 4, 13),
GROUP(uart_rx_a, 4, 12),
GROUP(uart_cts_a, 4, 11),
GROUP(uart_rts_a, 4, 10),
GROUP(pwm_a_x, 3, 17),
GROUP(pwm_e, 2, 30),
GROUP(pwm_f_x, 3, 18),
GROUP(tsin_b_d_valid, 3, 9),
GROUP(tsin_b_sop, 3, 8),
GROUP(tsin_b_clk, 3, 10),
GROUP(tsin_b_d0, 3, 7),
/* Bank Y */
GROUP(uart_cts_c, 1, 17),
GROUP(uart_rts_c, 1, 16),
GROUP(uart_tx_c, 1, 19),
GROUP(uart_rx_c, 1, 18),
GROUP(tsin_a_fail, 3, 3),
GROUP(tsin_a_d_valid, 3, 2),
GROUP(tsin_a_sop, 3, 1),
GROUP(tsin_a_clk, 3, 0),
GROUP(tsin_a_d0, 3, 4),
GROUP(tsin_a_dp, 3, 5),
GROUP(pwm_a_y, 1, 21),
GROUP(pwm_f_y, 1, 20),
GROUP(i2s_out_ch23_y, 1, 5),
GROUP(i2s_out_ch45_y, 1, 6),
GROUP(i2s_out_ch67_y, 1, 7),
GROUP(spdif_out_y, 1, 9),
GROUP(gen_clk_out, 6, 15),
/* Bank Z */
GROUP(eth_mdio, 6, 1),
GROUP(eth_mdc, 6, 0),
GROUP(eth_clk_rx_clk, 6, 13),
GROUP(eth_rx_dv, 6, 12),
GROUP(eth_rxd0, 6, 11),
GROUP(eth_rxd1, 6, 10),
GROUP(eth_rxd2, 6, 9),
GROUP(eth_rxd3, 6, 8),
GROUP(eth_rgmii_tx_clk, 6, 7),
GROUP(eth_tx_en, 6, 6),
GROUP(eth_txd0, 6, 5),
GROUP(eth_txd1, 6, 4),
GROUP(eth_txd2, 6, 3),
GROUP(eth_txd3, 6, 2),
GROUP(spi_ss0, 5, 26),
GROUP(spi_sclk, 5, 27),
GROUP(spi_miso, 5, 28),
GROUP(spi_mosi, 5, 29),
/* Bank H */
GROUP(hdmi_hpd, 1, 26),
GROUP(hdmi_sda, 1, 25),
GROUP(hdmi_scl, 1, 24),
/* Bank DV */
GROUP(uart_tx_b, 2, 29),
GROUP(uart_rx_b, 2, 28),
GROUP(uart_cts_b, 2, 27),
GROUP(uart_rts_b, 2, 26),
GROUP(pwm_b, 3, 21),
GROUP(pwm_d, 3, 20),
GROUP(i2c_sck_a, 7, 27),
GROUP(i2c_sda_a, 7, 26),
GROUP(i2c_sck_b, 7, 25),
GROUP(i2c_sda_b, 7, 24),
GROUP(i2c_sck_c, 7, 23),
GROUP(i2c_sda_c, 7, 22),
/* Bank BOOT */
GROUP(emmc_nand_d07, 4, 30),
GROUP(emmc_clk, 4, 18),
GROUP(emmc_cmd, 4, 19),
GROUP(emmc_ds, 4, 31),
GROUP(nor_d, 5, 1),
GROUP(nor_q, 5, 3),
GROUP(nor_c, 5, 2),
GROUP(nor_cs, 5, 0),
GROUP(nand_ce0, 4, 26),
GROUP(nand_ce1, 4, 27),
GROUP(nand_rb0, 4, 25),
GROUP(nand_ale, 4, 24),
GROUP(nand_cle, 4, 23),
GROUP(nand_wen_clk, 4, 22),
GROUP(nand_ren_wr, 4, 21),
GROUP(nand_dqs, 4, 20),
/* Bank CARD */
GROUP(sdcard_d1, 2, 14),
GROUP(sdcard_d0, 2, 15),
GROUP(sdcard_d3, 2, 12),
GROUP(sdcard_d2, 2, 13),
GROUP(sdcard_cmd, 2, 10),
GROUP(sdcard_clk, 2, 11),
};
static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
GPIO_GROUP(GPIOAO_10),
GPIO_GROUP(GPIOAO_11),
GPIO_GROUP(GPIOAO_12),
GPIO_GROUP(GPIOAO_13),
/* bank AO */
GROUP(uart_tx_ao_b, 0, 24),
GROUP(uart_rx_ao_b, 0, 25),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
GROUP(uart_cts_ao_b, 0, 8),
GROUP(uart_rts_ao_b, 0, 7),
GROUP(i2c_sck_ao, 0, 6),
GROUP(i2c_sda_ao, 0, 5),
GROUP(i2c_slave_sck_ao, 0, 2),
GROUP(i2c_slave_sda_ao, 0, 1),
GROUP(remote_input_ao, 0, 0),
GROUP(pwm_ao_a_3, 0, 22),
GROUP(pwm_ao_a_6, 0, 18),
GROUP(pwm_ao_a_12, 0, 17),
GROUP(pwm_ao_b, 0, 3),
GROUP(i2s_am_clk, 0, 30),
GROUP(i2s_out_ao_clk, 0, 29),
GROUP(i2s_out_lr_clk, 0, 28),
GROUP(i2s_out_ch01_ao, 0, 27),
GROUP(i2s_out_ch23_ao, 1, 0),
GROUP(i2s_out_ch45_ao, 1, 1),
GROUP(spdif_out_ao_6, 0, 16),
GROUP(spdif_out_ao_13, 0, 4),
GROUP(ao_cec, 0, 15),
GROUP(ee_cec, 0, 14),
/* test n pin */
GROUP(i2s_out_ch67_ao, 1, 2),
};
static const char * const gpio_periphs_groups[] = {
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
"GPIOZ_15",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17",
"CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
"CARD_5", "CARD_6",
"GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
"GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
"GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
"GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
"GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
"GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
"GPIOY_15", "GPIOY_16",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
"GPIOX_20", "GPIOX_21", "GPIOX_22",
};
static const char * const tsin_a_groups[] = {
"tsin_a_clk", "tsin_a_sop", "tsin_a_d_valid", "tsin_a_d0",
"tsin_a_dp", "tsin_a_fail",
};
static const char * const tsin_b_groups[] = {
"tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0",
};
static const char * const emmc_groups[] = {
"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs",
};
static const char * const spi_groups[] = {
"spi_mosi", "spi_miso", "spi_ss0", "spi_sclk",
};
static const char * const sdcard_groups[] = {
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
"sdcard_cmd", "sdcard_clk",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_cmd", "sdio_clk", "sdio_irq",
};
static const char * const nand_groups[] = {
"emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
"nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
};
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
static const char * const uart_b_groups[] = {
"uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
};
static const char * const uart_c_groups[] = {
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
};
static const char * const i2c_a_groups[] = {
"i2c_sck_a", "i2c_sda_a",
};
static const char * const i2c_b_groups[] = {
"i2c_sck_b", "i2c_sda_b",
};
static const char * const i2c_c_groups[] = {
"i2c_sck_c", "i2c_sda_c",
};
static const char * const eth_groups[] = {
"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
"eth_rgmii_tx_clk", "eth_tx_en",
"eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
};
static const char * const pwm_a_x_groups[] = {
"pwm_a_x",
};
static const char * const pwm_a_y_groups[] = {
"pwm_a_y",
};
static const char * const pwm_b_groups[] = {
"pwm_b",
};
static const char * const pwm_d_groups[] = {
"pwm_d",
};
static const char * const pwm_e_groups[] = {
"pwm_e",
};
static const char * const pwm_f_x_groups[] = {
"pwm_f_x",
};
static const char * const pwm_f_y_groups[] = {
"pwm_f_y",
};
static const char * const hdmi_hpd_groups[] = {
"hdmi_hpd",
};
static const char * const hdmi_i2c_groups[] = {
"hdmi_sda", "hdmi_scl",
};
static const char * const i2s_out_groups[] = {
"i2s_out_ch23_y", "i2s_out_ch45_y", "i2s_out_ch67_y",
};
static const char * const spdif_out_groups[] = {
"spdif_out_y",
};
static const char * const gen_clk_out_groups[] = {
"gen_clk_out",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
"GPIO_TEST_N",
};
static const char * const uart_ao_groups[] = {
"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
};
static const char * const uart_ao_b_groups[] = {
"uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
};
static const char * const i2c_ao_groups[] = {
"i2c_sck_ao", "i2c_sda_ao",
};
static const char * const i2c_slave_ao_groups[] = {
"i2c_slave_sck_ao", "i2c_slave_sda_ao",
};
static const char * const remote_input_ao_groups[] = {
"remote_input_ao",
};
static const char * const pwm_ao_a_3_groups[] = {
"pwm_ao_a_3",
};
static const char * const pwm_ao_a_6_groups[] = {
"pwm_ao_a_6",
};
static const char * const pwm_ao_a_12_groups[] = {
"pwm_ao_a_12",
};
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b",
};
static const char * const i2s_out_ao_groups[] = {
"i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk",
"i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao",
"i2s_out_ch67_ao",
};
static const char * const spdif_out_ao_groups[] = {
"spdif_out_ao_6", "spdif_out_ao_13",
};
static const char * const cec_ao_groups[] = {
"ao_cec", "ee_cec",
};
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(spi),
FUNCTION(sdcard),
FUNCTION(sdio),
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(i2c_a),
FUNCTION(i2c_b),
FUNCTION(i2c_c),
FUNCTION(eth),
FUNCTION(pwm_a_x),
FUNCTION(pwm_a_y),
FUNCTION(pwm_b),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f_x),
FUNCTION(pwm_f_y),
FUNCTION(hdmi_hpd),
FUNCTION(hdmi_i2c),
FUNCTION(i2s_out),
FUNCTION(spdif_out),
FUNCTION(gen_clk_out),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
};
static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_ao),
FUNCTION(i2c_slave_ao),
FUNCTION(remote_input_ao),
FUNCTION(pwm_ao_a_3),
FUNCTION(pwm_ao_a_6),
FUNCTION(pwm_ao_a_12),
FUNCTION(pwm_ao_b),
FUNCTION(i2s_out_ao),
FUNCTION(spdif_out_ao),
FUNCTION(cec_ao),
};
static struct meson_bank meson_gxbb_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
BANK("DV", GPIODV_0, GPIODV_29, 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
BANK("H", GPIOH_0, GPIOH_3, 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
BANK("Z", GPIOZ_0, GPIOZ_15, 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
BANK("BOOT", BOOT_0, BOOT_17, 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
};
static struct meson_bank meson_gxbb_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_gxbb_periphs_pins,
.groups = meson_gxbb_periphs_groups,
.funcs = meson_gxbb_periphs_functions,
.banks = meson_gxbb_periphs_banks,
.num_pins = ARRAY_SIZE(meson_gxbb_periphs_pins),
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_gxbb_aobus_pins,
.groups = meson_gxbb_aobus_groups,
.funcs = meson_gxbb_aobus_functions,
.banks = meson_gxbb_aobus_banks,
.num_pins = ARRAY_SIZE(meson_gxbb_aobus_pins),
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
.pmx_ops = &meson8_pmx_ops,
.parse_dt = meson8_aobus_parse_dt_extra,
};
static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-gxbb-periphs-pinctrl",
.data = &meson_gxbb_periphs_pinctrl_data,
},
{
.compatible = "amlogic,meson-gxbb-aobus-pinctrl",
.data = &meson_gxbb_aobus_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match);
static struct platform_driver meson_gxbb_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-gxbb-pinctrl",
.of_match_table = meson_gxbb_pinctrl_dt_match,
},
};
module_platform_driver(meson_gxbb_pinctrl_driver);
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
*
* Copyright (C) 2014 Beniamino Galvani <[email protected]>
*/
#include <dt-bindings/gpio/meson8-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson8-pmx.h"
static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
MESON_PIN(GPIOX_20),
MESON_PIN(GPIOX_21),
MESON_PIN(GPIOY_0),
MESON_PIN(GPIOY_1),
MESON_PIN(GPIOY_2),
MESON_PIN(GPIOY_3),
MESON_PIN(GPIOY_4),
MESON_PIN(GPIOY_5),
MESON_PIN(GPIOY_6),
MESON_PIN(GPIOY_7),
MESON_PIN(GPIOY_8),
MESON_PIN(GPIOY_9),
MESON_PIN(GPIOY_10),
MESON_PIN(GPIOY_11),
MESON_PIN(GPIOY_12),
MESON_PIN(GPIOY_13),
MESON_PIN(GPIOY_14),
MESON_PIN(GPIOY_15),
MESON_PIN(GPIOY_16),
MESON_PIN(GPIODV_0),
MESON_PIN(GPIODV_1),
MESON_PIN(GPIODV_2),
MESON_PIN(GPIODV_3),
MESON_PIN(GPIODV_4),
MESON_PIN(GPIODV_5),
MESON_PIN(GPIODV_6),
MESON_PIN(GPIODV_7),
MESON_PIN(GPIODV_8),
MESON_PIN(GPIODV_9),
MESON_PIN(GPIODV_10),
MESON_PIN(GPIODV_11),
MESON_PIN(GPIODV_12),
MESON_PIN(GPIODV_13),
MESON_PIN(GPIODV_14),
MESON_PIN(GPIODV_15),
MESON_PIN(GPIODV_16),
MESON_PIN(GPIODV_17),
MESON_PIN(GPIODV_18),
MESON_PIN(GPIODV_19),
MESON_PIN(GPIODV_20),
MESON_PIN(GPIODV_21),
MESON_PIN(GPIODV_22),
MESON_PIN(GPIODV_23),
MESON_PIN(GPIODV_24),
MESON_PIN(GPIODV_25),
MESON_PIN(GPIODV_26),
MESON_PIN(GPIODV_27),
MESON_PIN(GPIODV_28),
MESON_PIN(GPIODV_29),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(GPIOH_4),
MESON_PIN(GPIOH_5),
MESON_PIN(GPIOH_6),
MESON_PIN(GPIOH_7),
MESON_PIN(GPIOH_8),
MESON_PIN(GPIOH_9),
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(GPIOZ_11),
MESON_PIN(GPIOZ_12),
MESON_PIN(GPIOZ_13),
MESON_PIN(GPIOZ_14),
MESON_PIN(CARD_0),
MESON_PIN(CARD_1),
MESON_PIN(CARD_2),
MESON_PIN(CARD_3),
MESON_PIN(CARD_4),
MESON_PIN(CARD_5),
MESON_PIN(CARD_6),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(BOOT_15),
MESON_PIN(BOOT_16),
MESON_PIN(BOOT_17),
MESON_PIN(BOOT_18),
};
static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIOAO_10),
MESON_PIN(GPIOAO_11),
MESON_PIN(GPIOAO_12),
MESON_PIN(GPIOAO_13),
MESON_PIN(GPIO_BSD_EN),
MESON_PIN(GPIO_TEST_N),
};
/* bank X */
static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 };
static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 };
static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6,
GPIOX_7 };
static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 };
static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 };
static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 };
static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 };
static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 };
static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 };
static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 };
static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 };
static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
static const unsigned int iso7816_clk_pins[] = { GPIOX_18 };
static const unsigned int iso7816_data_pins[] = { GPIOX_19 };
static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
static const unsigned int pwm_e_pins[] = { GPIOX_10 };
static const unsigned int pwm_b_x_pins[] = { GPIOX_11 };
/* bank Y */
static const unsigned int uart_tx_c_pins[] = { GPIOY_0 };
static const unsigned int uart_rx_c_pins[] = { GPIOY_1 };
static const unsigned int uart_cts_c_pins[] = { GPIOY_2 };
static const unsigned int uart_rts_c_pins[] = { GPIOY_3 };
static const unsigned int pcm_out_b_pins[] = { GPIOY_4 };
static const unsigned int pcm_in_b_pins[] = { GPIOY_5 };
static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 };
static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 };
static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 };
static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 };
static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 };
static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 };
static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 };
static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 };
static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 };
static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 };
static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 };
static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 };
static const unsigned int spdif_in_pins[] = { GPIOY_2 };
static const unsigned int spdif_out_pins[] = { GPIOY_3 };
/* bank DV */
static const unsigned int dvin_rgb_pins[] = {
GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5,
GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11,
GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17,
GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23
};
static const unsigned int dvin_vs_pins[] = { GPIODV_24 };
static const unsigned int dvin_hs_pins[] = { GPIODV_25 };
static const unsigned int dvin_clk_pins[] = { GPIODV_26 };
static const unsigned int dvin_de_pins[] = { GPIODV_27 };
static const unsigned int enc_0_pins[] = { GPIODV_0 };
static const unsigned int enc_1_pins[] = { GPIODV_1 };
static const unsigned int enc_2_pins[] = { GPIODV_2 };
static const unsigned int enc_3_pins[] = { GPIODV_3 };
static const unsigned int enc_4_pins[] = { GPIODV_4 };
static const unsigned int enc_5_pins[] = { GPIODV_5 };
static const unsigned int enc_6_pins[] = { GPIODV_6 };
static const unsigned int enc_7_pins[] = { GPIODV_7 };
static const unsigned int enc_8_pins[] = { GPIODV_8 };
static const unsigned int enc_9_pins[] = { GPIODV_9 };
static const unsigned int enc_10_pins[] = { GPIODV_10 };
static const unsigned int enc_11_pins[] = { GPIODV_11 };
static const unsigned int enc_12_pins[] = { GPIODV_12 };
static const unsigned int enc_13_pins[] = { GPIODV_13 };
static const unsigned int enc_14_pins[] = { GPIODV_14 };
static const unsigned int enc_15_pins[] = { GPIODV_15 };
static const unsigned int enc_16_pins[] = { GPIODV_16 };
static const unsigned int enc_17_pins[] = { GPIODV_17 };
static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 };
static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 };
static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 };
static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 };
static const unsigned int vga_vs_pins[] = { GPIODV_24 };
static const unsigned int vga_hs_pins[] = { GPIODV_25 };
static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 };
static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 };
static const unsigned int pwm_d_pins[] = { GPIODV_28 };
/* bank H */
static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
static const unsigned int hdmi_cec_pins[] = { GPIOH_3 };
static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 };
static const unsigned int spi_miso_0_pins[] = { GPIOH_4 };
static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 };
static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 };
static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
/* bank Z */
static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 };
static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 };
static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 };
static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
static const unsigned int eth_txd3_pins[] = { GPIOZ_0 };
static const unsigned int eth_txd2_pins[] = { GPIOZ_1 };
static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 };
static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 };
static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
static const unsigned int eth_txd0_pins[] = { GPIOZ_7 };
static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 };
static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 };
static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 };
static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 };
static const unsigned int eth_mdio_pins[] = { GPIOZ_12 };
static const unsigned int eth_mdc_pins[] = { GPIOZ_13 };
static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 };
static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 };
static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 };
static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 };
static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 };
static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 };
static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 };
static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 };
static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 };
static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 };
static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 };
static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 };
static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 };
static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 };
/* bank BOOT */
static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
static const unsigned int sd_cmd_c_pins[] = { BOOT_16 };
static const unsigned int sd_clk_c_pins[] = { BOOT_17 };
static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 };
static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6,
BOOT_7 };
static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 };
static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 };
static const unsigned int nand_io_pins[] = {
BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
};
static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
static const unsigned int nand_ale_pins[] = { BOOT_11 };
static const unsigned int nand_cle_pins[] = { BOOT_12 };
static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
static const unsigned int nand_dqs_pins[] = { BOOT_15 };
static const unsigned int nand_ce2_pins[] = { BOOT_16 };
static const unsigned int nand_ce3_pins[] = { BOOT_17 };
static const unsigned int nor_d_pins[] = { BOOT_11 };
static const unsigned int nor_q_pins[] = { BOOT_12 };
static const unsigned int nor_c_pins[] = { BOOT_13 };
static const unsigned int nor_cs_pins[] = { BOOT_18 };
/* bank CARD */
static const unsigned int sd_d1_b_pins[] = { CARD_0 };
static const unsigned int sd_d0_b_pins[] = { CARD_1 };
static const unsigned int sd_clk_b_pins[] = { CARD_2 };
static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
static const unsigned int sd_d3_b_pins[] = { CARD_4 };
static const unsigned int sd_d2_b_pins[] = { CARD_5 };
static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 };
static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
/* bank AO */
static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
static const unsigned int remote_input_pins[] = { GPIOAO_7 };
static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 };
static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 };
static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 };
static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N };
static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 };
static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 };
static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 };
static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
GPIO_GROUP(GPIOX_20),
GPIO_GROUP(GPIOX_21),
GPIO_GROUP(GPIOY_0),
GPIO_GROUP(GPIOY_1),
GPIO_GROUP(GPIOY_2),
GPIO_GROUP(GPIOY_3),
GPIO_GROUP(GPIOY_4),
GPIO_GROUP(GPIOY_5),
GPIO_GROUP(GPIOY_6),
GPIO_GROUP(GPIOY_7),
GPIO_GROUP(GPIOY_8),
GPIO_GROUP(GPIOY_9),
GPIO_GROUP(GPIOY_10),
GPIO_GROUP(GPIOY_11),
GPIO_GROUP(GPIOY_12),
GPIO_GROUP(GPIOY_13),
GPIO_GROUP(GPIOY_14),
GPIO_GROUP(GPIOY_15),
GPIO_GROUP(GPIOY_16),
GPIO_GROUP(GPIODV_0),
GPIO_GROUP(GPIODV_1),
GPIO_GROUP(GPIODV_2),
GPIO_GROUP(GPIODV_3),
GPIO_GROUP(GPIODV_4),
GPIO_GROUP(GPIODV_5),
GPIO_GROUP(GPIODV_6),
GPIO_GROUP(GPIODV_7),
GPIO_GROUP(GPIODV_8),
GPIO_GROUP(GPIODV_9),
GPIO_GROUP(GPIODV_10),
GPIO_GROUP(GPIODV_11),
GPIO_GROUP(GPIODV_12),
GPIO_GROUP(GPIODV_13),
GPIO_GROUP(GPIODV_14),
GPIO_GROUP(GPIODV_15),
GPIO_GROUP(GPIODV_16),
GPIO_GROUP(GPIODV_17),
GPIO_GROUP(GPIODV_18),
GPIO_GROUP(GPIODV_19),
GPIO_GROUP(GPIODV_20),
GPIO_GROUP(GPIODV_21),
GPIO_GROUP(GPIODV_22),
GPIO_GROUP(GPIODV_23),
GPIO_GROUP(GPIODV_24),
GPIO_GROUP(GPIODV_25),
GPIO_GROUP(GPIODV_26),
GPIO_GROUP(GPIODV_27),
GPIO_GROUP(GPIODV_28),
GPIO_GROUP(GPIODV_29),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(GPIOH_4),
GPIO_GROUP(GPIOH_5),
GPIO_GROUP(GPIOH_6),
GPIO_GROUP(GPIOH_7),
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(GPIOH_9),
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(GPIOZ_11),
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(BOOT_18),
/* bank X */
GROUP(sd_d0_a, 8, 5),
GROUP(sd_d1_a, 8, 4),
GROUP(sd_d2_a, 8, 3),
GROUP(sd_d3_a, 8, 2),
GROUP(sd_clk_a, 8, 1),
GROUP(sd_cmd_a, 8, 0),
GROUP(sdxc_d0_a, 5, 14),
GROUP(sdxc_d13_a, 5, 13),
GROUP(sdxc_d47_a, 5, 12),
GROUP(sdxc_clk_a, 5, 11),
GROUP(sdxc_cmd_a, 5, 10),
GROUP(pcm_out_a, 3, 30),
GROUP(pcm_in_a, 3, 29),
GROUP(pcm_fs_a, 3, 28),
GROUP(pcm_clk_a, 3, 27),
GROUP(uart_tx_a0, 4, 17),
GROUP(uart_rx_a0, 4, 16),
GROUP(uart_cts_a0, 4, 15),
GROUP(uart_rts_a0, 4, 14),
GROUP(uart_tx_a1, 4, 13),
GROUP(uart_rx_a1, 4, 12),
GROUP(uart_cts_a1, 4, 11),
GROUP(uart_rts_a1, 4, 10),
GROUP(uart_tx_b0, 4, 9),
GROUP(uart_rx_b0, 4, 8),
GROUP(uart_cts_b0, 4, 7),
GROUP(uart_rts_b0, 4, 6),
GROUP(iso7816_det, 4, 21),
GROUP(iso7816_reset, 4, 20),
GROUP(iso7816_clk, 4, 19),
GROUP(iso7816_data, 4, 18),
GROUP(i2c_sda_d0, 4, 5),
GROUP(i2c_sck_d0, 4, 4),
GROUP(xtal_32k_out, 3, 22),
GROUP(xtal_24m_out, 3, 23),
GROUP(pwm_e, 9, 19),
GROUP(pwm_b_x, 2, 3),
/* bank Y */
GROUP(uart_tx_c, 1, 19),
GROUP(uart_rx_c, 1, 18),
GROUP(uart_cts_c, 1, 17),
GROUP(uart_rts_c, 1, 16),
GROUP(pcm_out_b, 4, 25),
GROUP(pcm_in_b, 4, 24),
GROUP(pcm_fs_b, 4, 23),
GROUP(pcm_clk_b, 4, 22),
GROUP(i2c_sda_c0, 1, 15),
GROUP(i2c_sck_c0, 1, 14),
GROUP(pwm_a_y, 9, 14),
GROUP(i2s_out_ch45, 1, 10),
GROUP(i2s_out_ch23, 1, 19),
GROUP(i2s_out_ch01, 1, 6),
GROUP(i2s_in_ch01, 1, 5),
GROUP(i2s_lr_clk_in, 1, 4),
GROUP(i2s_ao_clk_in, 1, 2),
GROUP(i2s_am_clk, 1, 0),
GROUP(i2s_out_ch78, 1, 11),
GROUP(spdif_in, 1, 8),
GROUP(spdif_out, 1, 7),
/* bank DV */
GROUP(dvin_rgb, 0, 6),
GROUP(dvin_vs, 0, 9),
GROUP(dvin_hs, 0, 8),
GROUP(dvin_clk, 0, 7),
GROUP(dvin_de, 0, 10),
GROUP(enc_0, 7, 0),
GROUP(enc_1, 7, 1),
GROUP(enc_2, 7, 2),
GROUP(enc_3, 7, 3),
GROUP(enc_4, 7, 4),
GROUP(enc_5, 7, 5),
GROUP(enc_6, 7, 6),
GROUP(enc_7, 7, 7),
GROUP(enc_8, 7, 8),
GROUP(enc_9, 7, 9),
GROUP(enc_10, 7, 10),
GROUP(enc_11, 7, 11),
GROUP(enc_12, 7, 12),
GROUP(enc_13, 7, 13),
GROUP(enc_14, 7, 14),
GROUP(enc_15, 7, 15),
GROUP(enc_16, 7, 16),
GROUP(enc_17, 7, 17),
GROUP(uart_tx_b1, 6, 23),
GROUP(uart_rx_b1, 6, 22),
GROUP(uart_cts_b1, 6, 21),
GROUP(uart_rts_b1, 6, 20),
GROUP(vga_vs, 0, 21),
GROUP(vga_hs, 0, 20),
GROUP(pwm_c_dv9, 3, 24),
GROUP(pwm_c_dv29, 3, 25),
GROUP(pwm_d, 3, 26),
/* bank H */
GROUP(hdmi_hpd, 1, 26),
GROUP(hdmi_sda, 1, 25),
GROUP(hdmi_scl, 1, 24),
GROUP(hdmi_cec, 1, 23),
GROUP(spi_ss0_0, 9, 13),
GROUP(spi_miso_0, 9, 12),
GROUP(spi_mosi_0, 9, 11),
GROUP(spi_sclk_0, 9, 10),
GROUP(i2c_sda_d1, 4, 3),
GROUP(i2c_sck_d1, 4, 2),
/* bank Z */
GROUP(spi_ss0_1, 8, 16),
GROUP(spi_ss1_1, 8, 12),
GROUP(spi_sclk_1, 8, 15),
GROUP(spi_mosi_1, 8, 14),
GROUP(spi_miso_1, 8, 13),
GROUP(spi_ss2_1, 8, 17),
GROUP(eth_tx_clk_50m, 6, 15),
GROUP(eth_tx_en, 6, 14),
GROUP(eth_txd1, 6, 13),
GROUP(eth_txd0, 6, 12),
GROUP(eth_rx_clk_in, 6, 10),
GROUP(eth_rx_dv, 6, 11),
GROUP(eth_rxd1, 6, 8),
GROUP(eth_rxd0, 6, 7),
GROUP(eth_mdio, 6, 6),
GROUP(eth_mdc, 6, 5),
/* NOTE: the following four groups are only available on Meson8m2: */
GROUP(eth_rxd2, 6, 3),
GROUP(eth_rxd3, 6, 2),
GROUP(eth_txd2, 6, 1),
GROUP(eth_txd3, 6, 0),
GROUP(i2c_sda_a0, 5, 31),
GROUP(i2c_sck_a0, 5, 30),
GROUP(i2c_sda_b, 5, 27),
GROUP(i2c_sck_b, 5, 26),
GROUP(i2c_sda_c1, 5, 25),
GROUP(i2c_sck_c1, 5, 24),
GROUP(i2c_sda_a1, 5, 9),
GROUP(i2c_sck_a1, 5, 8),
GROUP(i2c_sda_a2, 5, 7),
GROUP(i2c_sck_a2, 5, 6),
GROUP(pwm_a_z0, 9, 16),
GROUP(pwm_a_z7, 2, 0),
GROUP(pwm_b_z, 9, 15),
GROUP(pwm_c_z, 2, 1),
/* bank BOOT */
GROUP(sd_d0_c, 6, 29),
GROUP(sd_d1_c, 6, 28),
GROUP(sd_d2_c, 6, 27),
GROUP(sd_d3_c, 6, 26),
GROUP(sd_cmd_c, 6, 25),
GROUP(sd_clk_c, 6, 24),
GROUP(sdxc_d0_c, 4, 30),
GROUP(sdxc_d13_c, 4, 29),
GROUP(sdxc_d47_c, 4, 28),
GROUP(sdxc_cmd_c, 4, 27),
GROUP(sdxc_clk_c, 4, 26),
GROUP(nand_io, 2, 26),
GROUP(nand_io_ce0, 2, 25),
GROUP(nand_io_ce1, 2, 24),
GROUP(nand_io_rb0, 2, 17),
GROUP(nand_ale, 2, 21),
GROUP(nand_cle, 2, 20),
GROUP(nand_wen_clk, 2, 19),
GROUP(nand_ren_clk, 2, 18),
GROUP(nand_dqs, 2, 27),
GROUP(nand_ce2, 2, 23),
GROUP(nand_ce3, 2, 22),
GROUP(nor_d, 5, 1),
GROUP(nor_q, 5, 3),
GROUP(nor_c, 5, 2),
GROUP(nor_cs, 5, 0),
/* bank CARD */
GROUP(sd_d1_b, 2, 14),
GROUP(sd_d0_b, 2, 15),
GROUP(sd_clk_b, 2, 11),
GROUP(sd_cmd_b, 2, 10),
GROUP(sd_d3_b, 2, 12),
GROUP(sd_d2_b, 2, 13),
GROUP(sdxc_d13_b, 2, 6),
GROUP(sdxc_d0_b, 2, 7),
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
};
static struct meson_pmx_group meson8_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
GPIO_GROUP(GPIOAO_10),
GPIO_GROUP(GPIOAO_11),
GPIO_GROUP(GPIOAO_12),
GPIO_GROUP(GPIOAO_13),
GPIO_GROUP(GPIO_BSD_EN),
GPIO_GROUP(GPIO_TEST_N),
/* bank AO */
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
GROUP(remote_input, 0, 0),
GROUP(remote_output_ao, 0, 31),
GROUP(i2c_slave_sck_ao, 0, 2),
GROUP(i2c_slave_sda_ao, 0, 1),
GROUP(uart_tx_ao_b0, 0, 26),
GROUP(uart_rx_ao_b0, 0, 25),
GROUP(uart_tx_ao_b1, 0, 24),
GROUP(uart_rx_ao_b1, 0, 23),
GROUP(i2c_mst_sck_ao, 0, 6),
GROUP(i2c_mst_sda_ao, 0, 5),
GROUP(pwm_f_ao, 0, 19),
GROUP(i2s_am_clk_out_ao, 0, 30),
GROUP(i2s_ao_clk_out_ao, 0, 29),
GROUP(i2s_lr_clk_out_ao, 0, 28),
GROUP(i2s_out_ch01_ao, 0, 27),
GROUP(hdmi_cec_ao, 0, 17),
};
static const char * const gpio_periphs_groups[] = {
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
"GPIOX_20", "GPIOX_21",
"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
"GPIOY_15", "GPIOY_16",
"GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
"GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
"GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
"GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
"GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
"GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
"GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
"CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
"CARD_5", "CARD_6",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
"GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
};
static const char * const sd_a_groups[] = {
"sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
};
static const char * const sdxc_a_groups[] = {
"sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
};
static const char * const pcm_a_groups[] = {
"pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
};
static const char * const uart_a_groups[] = {
"uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
"uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
};
static const char * const uart_b_groups[] = {
"uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
"uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
};
static const char * const iso7816_groups[] = {
"iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
};
static const char * const i2c_d_groups[] = {
"i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
};
static const char * const xtal_groups[] = {
"xtal_32k_out", "xtal_24m_out"
};
static const char * const uart_c_groups[] = {
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
};
static const char * const pcm_b_groups[] = {
"pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
};
static const char * const i2c_c_groups[] = {
"i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
};
static const char * const dvin_groups[] = {
"dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
};
static const char * const enc_groups[] = {
"enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
"enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
"enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
};
static const char * const vga_groups[] = {
"vga_vs", "vga_hs"
};
static const char * const hdmi_groups[] = {
"hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
};
static const char * const spi_groups[] = {
"spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
"spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
"spi_miso_1", "spi_ss2_1"
};
static const char * const ethernet_groups[] = {
"eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
"eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
"eth_rxd3", "eth_txd2", "eth_txd3"
};
static const char * const i2c_a_groups[] = {
"i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
"i2c_sda_a2", "i2c_sck_a2"
};
static const char * const i2c_b_groups[] = {
"i2c_sda_b", "i2c_sck_b"
};
static const char * const i2s_groups[] = {
"i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
"i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
"i2s_am_clk_pins", "i2s_out_ch78_pins"
};
static const char * const sd_c_groups[] = {
"sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
"sd_cmd_c", "sd_clk_c"
};
static const char * const sdxc_c_groups[] = {
"sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
"sdxc_clk_c"
};
static const char * const nand_groups[] = {
"nand_io", "nand_io_ce0", "nand_io_ce1",
"nand_io_rb0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_clk", "nand_dqs",
"nand_ce2", "nand_ce3"
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs"
};
static const char * const pwm_a_groups[] = {
"pwm_a_y", "pwm_a_z0", "pwm_a_z7"
};
static const char * const pwm_b_groups[] = {
"pwm_b_x", "pwm_b_z"
};
static const char * const pwm_c_groups[] = {
"pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
};
static const char * const pwm_d_groups[] = {
"pwm_d"
};
static const char * const pwm_e_groups[] = {
"pwm_e"
};
static const char * const sd_b_groups[] = {
"sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
"sd_d3_b", "sd_d2_b"
};
static const char * const sdxc_b_groups[] = {
"sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
};
static const char * const spdif_groups[] = {
"spdif_in", "spdif_out"
};
static const char * const uart_ao_groups[] = {
"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
};
static const char * const remote_groups[] = {
"remote_input", "remote_output_ao"
};
static const char * const i2c_slave_ao_groups[] = {
"i2c_slave_sck_ao", "i2c_slave_sda_ao"
};
static const char * const uart_ao_b_groups[] = {
"uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
};
static const char * const i2c_mst_ao_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
static const char * const pwm_f_ao_groups[] = {
"pwm_f_ao"
};
static const char * const i2s_ao_groups[] = {
"i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
"i2s_out_ch01_ao"
};
static const char * const hdmi_cec_ao_groups[] = {
"hdmi_cec_ao"
};
static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(pcm_a),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(iso7816),
FUNCTION(i2c_d),
FUNCTION(xtal),
FUNCTION(uart_c),
FUNCTION(pcm_b),
FUNCTION(i2c_c),
FUNCTION(dvin),
FUNCTION(enc),
FUNCTION(vga),
FUNCTION(hdmi),
FUNCTION(spi),
FUNCTION(ethernet),
FUNCTION(i2c_a),
FUNCTION(i2c_b),
FUNCTION(sd_c),
FUNCTION(sdxc_c),
FUNCTION(nand),
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(i2s),
FUNCTION(spdif),
};
static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_mst_ao),
FUNCTION(pwm_f_ao),
FUNCTION(i2s_ao),
FUNCTION(hdmi_cec_ao),
};
static struct meson_bank meson8_cbus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
};
static struct meson_bank meson8_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
.name = "cbus-banks",
.pins = meson8_cbus_pins,
.groups = meson8_cbus_groups,
.funcs = meson8_cbus_functions,
.banks = meson8_cbus_banks,
.num_pins = ARRAY_SIZE(meson8_cbus_pins),
.num_groups = ARRAY_SIZE(meson8_cbus_groups),
.num_funcs = ARRAY_SIZE(meson8_cbus_functions),
.num_banks = ARRAY_SIZE(meson8_cbus_banks),
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
.name = "ao-bank",
.pins = meson8_aobus_pins,
.groups = meson8_aobus_groups,
.funcs = meson8_aobus_functions,
.banks = meson8_aobus_banks,
.num_pins = ARRAY_SIZE(meson8_aobus_pins),
.num_groups = ARRAY_SIZE(meson8_aobus_groups),
.num_funcs = ARRAY_SIZE(meson8_aobus_functions),
.num_banks = ARRAY_SIZE(meson8_aobus_banks),
.pmx_ops = &meson8_pmx_ops,
.parse_dt = &meson8_aobus_parse_dt_extra,
};
static const struct of_device_id meson8_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson8-cbus-pinctrl",
.data = &meson8_cbus_pinctrl_data,
},
{
.compatible = "amlogic,meson8-aobus-pinctrl",
.data = &meson8_aobus_pinctrl_data,
},
{
.compatible = "amlogic,meson8m2-cbus-pinctrl",
.data = &meson8_cbus_pinctrl_data,
},
{
.compatible = "amlogic,meson8m2-aobus-pinctrl",
.data = &meson8_aobus_pinctrl_data,
},
{ },
};
static struct platform_driver meson8_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson8-pinctrl",
.of_match_table = meson8_pinctrl_dt_match,
},
};
builtin_platform_driver(meson8_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson8.c
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Pin controller and GPIO driver for Amlogic Meson S4 SoC.
*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
* Author: Qianggui Song <[email protected]>
*/
#include <dt-bindings/gpio/meson-s4-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = {
MESON_PIN(GPIOE_0),
MESON_PIN(GPIOE_1),
MESON_PIN(GPIOB_0),
MESON_PIN(GPIOB_1),
MESON_PIN(GPIOB_2),
MESON_PIN(GPIOB_3),
MESON_PIN(GPIOB_4),
MESON_PIN(GPIOB_5),
MESON_PIN(GPIOB_6),
MESON_PIN(GPIOB_7),
MESON_PIN(GPIOB_8),
MESON_PIN(GPIOB_9),
MESON_PIN(GPIOB_10),
MESON_PIN(GPIOB_11),
MESON_PIN(GPIOB_12),
MESON_PIN(GPIOB_13),
MESON_PIN(GPIOC_0),
MESON_PIN(GPIOC_1),
MESON_PIN(GPIOC_2),
MESON_PIN(GPIOC_3),
MESON_PIN(GPIOC_4),
MESON_PIN(GPIOC_5),
MESON_PIN(GPIOC_6),
MESON_PIN(GPIOC_7),
MESON_PIN(GPIOD_0),
MESON_PIN(GPIOD_1),
MESON_PIN(GPIOD_2),
MESON_PIN(GPIOD_3),
MESON_PIN(GPIOD_4),
MESON_PIN(GPIOD_5),
MESON_PIN(GPIOD_6),
MESON_PIN(GPIOD_7),
MESON_PIN(GPIOD_8),
MESON_PIN(GPIOD_9),
MESON_PIN(GPIOD_10),
MESON_PIN(GPIOD_11),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(GPIOH_4),
MESON_PIN(GPIOH_5),
MESON_PIN(GPIOH_6),
MESON_PIN(GPIOH_7),
MESON_PIN(GPIOH_8),
MESON_PIN(GPIOH_9),
MESON_PIN(GPIOH_10),
MESON_PIN(GPIOH_11),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(GPIOZ_11),
MESON_PIN(GPIOZ_12),
MESON_PIN(GPIO_TEST_N),
};
/* BANK E func1 */
static const unsigned int i2c0_sda_pins[] = { GPIOE_0 };
static const unsigned int i2c0_scl_pins[] = { GPIOE_1 };
/* BANK E func2 */
static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 };
static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 };
/* BANK E func3 */
static const unsigned int pwm_h_pins[] = { GPIOE_0 };
static const unsigned int pwm_j_pins[] = { GPIOE_1 };
/* BANK B func1 */
static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
static const unsigned int emmc_rst_pins[] = { GPIOB_9 };
static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
/* Bank B func2 */
static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
static const unsigned int nand_ale_pins[] = { GPIOB_9 };
static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
static const unsigned int nand_cle_pins[] = { GPIOB_11 };
static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
/* Bank B func3 */
static const unsigned int spif_hold_pins[] = { GPIOB_3 };
static const unsigned int spif_mo_pins[] = { GPIOB_4 };
static const unsigned int spif_mi_pins[] = { GPIOB_5 };
static const unsigned int spif_clk_pins[] = { GPIOB_6 };
static const unsigned int spif_wp_pins[] = { GPIOB_7 };
static const unsigned int spif_cs_pins[] = { GPIOB_13 };
/* Bank C func1 */
static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
/* Bank C func2 */
static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 };
static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 };
static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 };
static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 };
static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 };
static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 };
/* Bank C func3 */
static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 };
static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 };
static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 };
static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 };
static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
/* Bank C func4 */
static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 };
static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 };
static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 };
static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 };
static const unsigned int mclk_1_c_pins[] = { GPIOC_4 };
static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 };
static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 };
/* Bank D func1 */
static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 };
static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 };
static const unsigned int remote_out_pins[] = { GPIOD_4 };
static const unsigned int remote_in_pins[] = { GPIOD_5 };
static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 };
static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 };
static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 };
static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 };
static const unsigned int clk12_24_pins[] = { GPIOD_10 };
static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 };
/* Bank D func2 */
static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 };
static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 };
static const unsigned int mclk_1_d_pins[] = { GPIOD_4 };
static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 };
static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 };
static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 };
static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 };
static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 };
static const unsigned int pwm_g_d_pins[] = { GPIOD_11 };
/* Bank D func3 */
static const unsigned int uart_c_tx_pins[] = { GPIOD_2 };
static const unsigned int uart_c_rx_pins[] = { GPIOD_3 };
static const unsigned int pwm_b_d_pins[] = { GPIOD_4 };
static const unsigned int pwm_a_d_pins[] = { GPIOD_6 };
static const unsigned int pwm_c_d_pins[] = { GPIOD_7 };
static const unsigned int pwm_d_d_pins[] = { GPIOD_8 };
static const unsigned int pwm_i_d_pins[] = { GPIOD_9 };
/* Bank D func4 */
static const unsigned int clk_32k_in_pins[] = { GPIOD_2 };
static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 };
static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 };
static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 };
static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 };
static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 };
static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 };
/* Bank D func5 */
static const unsigned int mic_mute_en_pins[] = { GPIOD_2 };
static const unsigned int mic_mute_key_pins[] = { GPIOD_3 };
static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 };
static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 };
static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 };
static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 };
/* Bank D func6 */
static const unsigned int gen_clk_d_pins[] = { GPIOD_10 };
static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 };
static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 };
static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 };
static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 };
/* Bank H func1 */
static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 };
static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
static const unsigned int ao_cec_a_pins[] = { GPIOH_3 };
static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
static const unsigned int spdif_in_pins[] = { GPIOH_5 };
static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 };
static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 };
static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 };
static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 };
static const unsigned int eth_link_led_pins[] = { GPIOH_10 };
static const unsigned int eth_act_led_pins[] = { GPIOH_11 };
/* Bank H func2 */
static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 };
static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 };
static const unsigned int ao_cec_b_pins[] = { GPIOH_3 };
static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 };
static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 };
static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 };
static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 };
static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 };
static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 };
static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 };
static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 };
/* Bank H func3 */
static const unsigned int pwm_d_h_pins[] = { GPIOH_6 };
static const unsigned int pwm_i_h_pins[] = { GPIOH_7 };
static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 };
static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 };
static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 };
/* Bank H func4 */
static const unsigned int mclk_1_h_pins[] = { GPIOH_4 };
static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 };
static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 };
static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 };
static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 };
static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 };
/* Bank H func5 */
static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 };
static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 };
static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 };
static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 };
/* Bank H func6 */
static const unsigned int gen_clk_h_pins[] = { GPIOH_11 };
static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 };
static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 };
static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 };
static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 };
/* Bank X func1 */
static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
static const unsigned int tdm_d1_pins[] = { GPIOX_8 };
static const unsigned int tdm_d0_pins[] = { GPIOX_9 };
static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
static const unsigned int uart_a_tx_pins[] = { GPIOX_12 };
static const unsigned int uart_a_rx_pins[] = { GPIOX_13 };
static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
static const unsigned int pwm_e_x_pins[] = { GPIOX_16 };
static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 };
static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 };
static const unsigned int pwm_b_x_pins[] = { GPIOX_19 };
/* Bank X func2 */
static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 };
static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 };
static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 };
/* Bank X func3 */
static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 };
static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 };
static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 };
static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 };
/* Bank X func4 */
static const unsigned int pwm_c_x_pins[] = { GPIOX_8 };
static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 };
static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 };
/* Bank X func5 */
static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 };
static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 };
/* Bank Z func1 */
static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 };
static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 };
static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 };
static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 };
static const unsigned int tdm_d6_pins[] = { GPIOZ_4 };
static const unsigned int tdm_d7_pins[] = { GPIOZ_5 };
static const unsigned int mclk_2_pins[] = { GPIOZ_6 };
static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 };
static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 };
static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 };
static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 };
/* Bank Z func2 */
static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 };
static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 };
static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 };
static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 };
static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 };
static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 };
static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 };
static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 };
static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 };
static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 };
/* Bank Z func3 */
static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 };
static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 };
static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 };
static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 };
static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 };
static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 };
static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 };
static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 };
static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 };
static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 };
static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 };
/* Bank Z func4 */
static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 };
static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 };
static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 };
static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 };
static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 };
static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 };
static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 };
static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 };
/* Bank Z func5 */
static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 };
static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 };
static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 };
static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 };
static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 };
static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 };
static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 };
static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 };
static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 };
static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 };
static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 };
/* Bank Z func6 */
static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 };
static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 };
static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 };
static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 };
static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 };
static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 };
static const unsigned int diseqc_out_pins[] = { GPIOZ_7 };
static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 };
static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 };
/* Bank Z func7 */
static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
static struct meson_pmx_group meson_s4_periphs_groups[] = {
GPIO_GROUP(GPIOE_0),
GPIO_GROUP(GPIOE_1),
GPIO_GROUP(GPIOB_0),
GPIO_GROUP(GPIOB_1),
GPIO_GROUP(GPIOB_2),
GPIO_GROUP(GPIOB_3),
GPIO_GROUP(GPIOB_4),
GPIO_GROUP(GPIOB_5),
GPIO_GROUP(GPIOB_6),
GPIO_GROUP(GPIOB_7),
GPIO_GROUP(GPIOB_8),
GPIO_GROUP(GPIOB_9),
GPIO_GROUP(GPIOB_10),
GPIO_GROUP(GPIOB_11),
GPIO_GROUP(GPIOB_12),
GPIO_GROUP(GPIOB_13),
GPIO_GROUP(GPIOC_0),
GPIO_GROUP(GPIOC_1),
GPIO_GROUP(GPIOC_2),
GPIO_GROUP(GPIOC_3),
GPIO_GROUP(GPIOC_4),
GPIO_GROUP(GPIOC_5),
GPIO_GROUP(GPIOC_6),
GPIO_GROUP(GPIOC_7),
GPIO_GROUP(GPIOD_0),
GPIO_GROUP(GPIOD_1),
GPIO_GROUP(GPIOD_2),
GPIO_GROUP(GPIOD_3),
GPIO_GROUP(GPIOD_4),
GPIO_GROUP(GPIOD_5),
GPIO_GROUP(GPIOD_6),
GPIO_GROUP(GPIOD_7),
GPIO_GROUP(GPIOD_8),
GPIO_GROUP(GPIOD_9),
GPIO_GROUP(GPIOD_10),
GPIO_GROUP(GPIOD_11),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(GPIOH_4),
GPIO_GROUP(GPIOH_5),
GPIO_GROUP(GPIOH_6),
GPIO_GROUP(GPIOH_7),
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(GPIOH_9),
GPIO_GROUP(GPIOH_10),
GPIO_GROUP(GPIOH_11),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(GPIOZ_11),
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIO_TEST_N),
/* BANK E func1 */
GROUP(i2c0_sda, 1),
GROUP(i2c0_scl, 1),
/* BANK E func2 */
GROUP(uart_b_tx_e, 2),
GROUP(uart_b_rx_e, 2),
/* BANK E func3 */
GROUP(pwm_h, 3),
GROUP(pwm_j, 3),
/* BANK B func1 */
GROUP(emmc_nand_d0, 1),
GROUP(emmc_nand_d1, 1),
GROUP(emmc_nand_d2, 1),
GROUP(emmc_nand_d3, 1),
GROUP(emmc_nand_d4, 1),
GROUP(emmc_nand_d5, 1),
GROUP(emmc_nand_d6, 1),
GROUP(emmc_nand_d7, 1),
GROUP(emmc_clk, 1),
GROUP(emmc_rst, 1),
GROUP(emmc_cmd, 1),
GROUP(emmc_nand_ds, 1),
/* Bank B func2 */
GROUP(nand_wen_clk, 2),
GROUP(nand_ale, 2),
GROUP(nand_ren_wr, 2),
GROUP(nand_cle, 2),
GROUP(nand_ce0, 2),
/* Bank B func3 */
GROUP(spif_hold, 3),
GROUP(spif_mo, 3),
GROUP(spif_mi, 3),
GROUP(spif_clk, 3),
GROUP(spif_wp, 3),
GROUP(spif_cs, 3),
/* Bank C func1 */
GROUP(sdcard_d0_c, 1),
GROUP(sdcard_d1_c, 1),
GROUP(sdcard_d2_c, 1),
GROUP(sdcard_d3_c, 1),
GROUP(sdcard_clk_c, 1),
GROUP(sdcard_cmd_c, 1),
GROUP(sdcard_cd, 1),
/* Bank C func2 */
GROUP(jtag_2_tdo, 2),
GROUP(jtag_2_tdi, 2),
GROUP(uart_b_rx_c, 2),
GROUP(uart_b_tx_c, 2),
GROUP(jtag_2_clk, 2),
GROUP(jtag_2_tms, 2),
GROUP(i2c1_sda_c, 2),
GROUP(i2c1_scl_c, 2),
/* Bank C func3 */
GROUP(pdm_din1_c, 3),
GROUP(pdm_din0_c, 3),
GROUP(i2c4_sda_c, 3),
GROUP(i2c4_scl_c, 3),
GROUP(pdm_dclk_c, 3),
GROUP(iso7816_clk_c, 3),
GROUP(iso7816_data_c, 3),
/* Bank C func4 */
GROUP(tdm_d2_c, 4),
GROUP(tdm_d3_c, 4),
GROUP(tdm_fs1_c, 4),
GROUP(tdm_sclk1_c, 4),
GROUP(mclk_1_c, 4),
GROUP(tdm_d4_c, 4),
GROUP(tdm_d5_c, 4),
/* Bank D func1 */
GROUP(uart_b_tx_d, 1),
GROUP(uart_b_rx_d, 1),
GROUP(uart_b_cts_d, 1),
GROUP(uart_b_rts_d, 1),
GROUP(remote_out, 1),
GROUP(remote_in, 1),
GROUP(jtag_1_clk, 1),
GROUP(jtag_1_tms, 1),
GROUP(jtag_1_tdi, 1),
GROUP(jtag_1_tdo, 1),
GROUP(clk12_24, 1),
GROUP(pwm_g_hiz, 1),
/* Bank D func2 */
GROUP(i2c4_sda_d, 2),
GROUP(i2c4_scl_d, 2),
GROUP(mclk_1_d, 2),
GROUP(tdm_sclk1_d, 2),
GROUP(tdm_fs1_d, 2),
GROUP(tdm_d4_d, 2),
GROUP(tdm_d3_d, 2),
GROUP(tdm_d2_d, 2),
GROUP(pwm_g_d, 2),
/* Bank D func3 */
GROUP(uart_c_tx, 3),
GROUP(uart_c_rx, 3),
GROUP(pwm_b_d, 3),
GROUP(pwm_a_d, 3),
GROUP(pwm_c_d, 3),
GROUP(pwm_d_d, 3),
GROUP(pwm_i_d, 3),
/* Bank D func4 */
GROUP(clk_32k_in, 4),
GROUP(pwm_b_hiz, 4),
GROUP(pwm_a_hiz, 4),
GROUP(pwm_c_hiz, 4),
GROUP(pdm_dclk_d, 4),
GROUP(pdm_din0_d, 4),
GROUP(pdm_din1_d, 4),
/* Bank D func5 */
GROUP(mic_mute_en, 5),
GROUP(mic_mute_key, 5),
GROUP(i2c1_sda_d, 5),
GROUP(i2c1_scl_d, 5),
GROUP(i2c2_sda_d, 5),
GROUP(i2c2_scl_d, 5),
/* Bank D func6 */
GROUP(gen_clk_d, 6),
GROUP(tsin_b_clk_c, 6),
GROUP(tsin_b_sop_c, 6),
GROUP(tsin_b_valid_c, 6),
GROUP(tsin_b_d0_c, 6),
/* Bank H func1 */
GROUP(hdmitx_sda, 1),
GROUP(hdmitx_sck, 1),
GROUP(hdmitx_hpd_in, 1),
GROUP(ao_cec_a, 1),
GROUP(spdif_out_h, 1),
GROUP(spdif_in, 1),
GROUP(i2c1_sda_h, 1),
GROUP(i2c1_scl_h, 1),
GROUP(i2c2_sda_h8, 1),
GROUP(i2c2_scl_h9, 1),
GROUP(eth_link_led, 1),
GROUP(eth_act_led, 1),
/* Bank H func2 */
GROUP(i2c2_sda_h0, 2),
GROUP(i2c2_scl_h1, 2),
GROUP(ao_cec_b, 2),
GROUP(uart_d_tx_h, 2),
GROUP(uart_d_rx_h, 2),
GROUP(uart_d_cts_h, 2),
GROUP(uart_d_rts_h, 2),
GROUP(iso7816_clk_h, 2),
GROUP(iso7816_data_h, 2),
GROUP(uart_e_tx_h, 2),
GROUP(uart_e_rx_h, 2),
/* Bank H func3 */
GROUP(pwm_d_h, 3),
GROUP(pwm_i_h, 3),
GROUP(pdm_dclk_h, 3),
GROUP(pdm_din0_h, 3),
GROUP(pdm_din1_h, 3),
/* Bank H func4 */
GROUP(mclk_1_h, 4),
GROUP(tdm_sclk1_h, 4),
GROUP(tdm_fs1_h, 4),
GROUP(tdm_d2_h, 4),
GROUP(tdm_d3_h, 4),
GROUP(tdm_d4_h, 4),
/* Bank H func5 */
GROUP(spi_a_miso_h, 5),
GROUP(spi_a_mosi_h, 5),
GROUP(spi_a_clk_h, 5),
GROUP(spi_a_ss0_h, 5),
/* Bank H func6 */
GROUP(gen_clk_h, 6),
GROUP(tsin_b1_clk, 6),
GROUP(tsin_b1_sop, 6),
GROUP(tsin_b1_valid, 6),
GROUP(tsin_b1_d0, 6),
/* Bank X func1 */
GROUP(sdio_d0, 1),
GROUP(sdio_d1, 1),
GROUP(sdio_d2, 1),
GROUP(sdio_d3, 1),
GROUP(sdio_clk, 1),
GROUP(sdio_cmd, 1),
GROUP(pwm_a_x, 1),
GROUP(pwm_f_x, 1),
GROUP(tdm_d1, 1),
GROUP(tdm_d0, 1),
GROUP(tdm_fs0, 1),
GROUP(tdm_sclk0, 1),
GROUP(uart_a_tx, 1),
GROUP(uart_a_rx, 1),
GROUP(uart_a_cts, 1),
GROUP(uart_a_rts, 1),
GROUP(pwm_e_x, 1),
GROUP(i2c1_sda_x, 1),
GROUP(i2c1_scl_x, 1),
GROUP(pwm_b_x, 1),
/* Bank X func2 */
GROUP(pdm_din0_x, 2),
GROUP(pdm_din1_x, 2),
GROUP(pdm_dclk_x, 2),
/* Bank X func3 */
GROUP(spi_a_mosi_x, 3),
GROUP(spi_a_miso_x, 3),
GROUP(spi_a_ss0_x, 3),
GROUP(spi_a_clk_x, 3),
/* Bank X func4 */
GROUP(pwm_c_x, 4),
GROUP(i2c_slave_scl, 4),
GROUP(i2c_slave_sda, 4),
/* Bank X func5 */
GROUP(i2c3_sda_x, 5),
GROUP(i2c3_scl_x, 5),
/* Bank Z func1 */
GROUP(tdm_fs2, 1),
GROUP(tdm_sclk2, 1),
GROUP(tdm_d4_z, 1),
GROUP(tdm_d5_z, 1),
GROUP(tdm_d6, 1),
GROUP(tdm_d7, 1),
GROUP(mclk_2, 1),
GROUP(spdif_out_z, 1),
GROUP(dtv_a_if_agc_z10, 1),
GROUP(uart_e_tx_z11, 1),
GROUP(uart_e_rx_z12, 1),
/* Bank Z func2 */
GROUP(tsin_a_clk, 2),
GROUP(tsin_a_sop, 2),
GROUP(tsin_a_valid, 2),
GROUP(tsin_a_din0, 2),
GROUP(dtv_a_if_agc_z6, 2),
GROUP(dtv_b_if_agc, 2),
GROUP(i2c3_sda_z, 2),
GROUP(i2c3_scl_z, 2),
GROUP(dtv_a_rf_agc, 2),
GROUP(dtv_b_rf_agc, 2),
/* Bank Z func3 */
GROUP(sdcard_d0_z, 3),
GROUP(sdcard_d1_z, 3),
GROUP(sdcard_d2_z, 3),
GROUP(sdcard_d3_z, 3),
GROUP(sdcard_clk_z, 3),
GROUP(sdcard_cmd_z, 3),
GROUP(uart_e_tx_z8, 3),
GROUP(uart_e_rx_z9, 3),
GROUP(pdm_din1_z, 3),
GROUP(pdm_din0_z, 3),
GROUP(pdm_dclk_z, 3),
/* Bank Z func4 */
GROUP(spi_a_miso_z, 4),
GROUP(spi_a_mosi_z, 4),
GROUP(spi_a_clk_z, 4),
GROUP(spi_a_ss0_z, 4),
GROUP(spi_a_ss1_z, 4),
GROUP(spi_a_ss2_z, 4),
GROUP(i2c4_scl_z, 4),
GROUP(i2c4_sda_z, 4),
/* Bank Z func5 */
GROUP(uart_d_tx_z, 5),
GROUP(uart_d_rx_z, 5),
GROUP(uart_d_cts_z, 5),
GROUP(uart_d_rts_z, 5),
GROUP(pwm_g_z, 5),
GROUP(pwm_f_z, 5),
GROUP(pwm_e_z, 5),
GROUP(tsin_b_clk_z, 5),
GROUP(tsin_b_sop_z, 5),
GROUP(tsin_b_valid_z, 5),
GROUP(tsin_b_d0_z, 5),
/* Bank Z func6 */
GROUP(s2_demod_gpio7, 6),
GROUP(s2_demod_gpio6, 6),
GROUP(s2_demod_gpio5, 6),
GROUP(s2_demod_gpio4, 6),
GROUP(s2_demod_gpio3, 6),
GROUP(s2_demod_gpio2, 6),
GROUP(diseqc_out, 6),
GROUP(s2_demod_gpio1, 6),
GROUP(s2_demod_gpio0, 6),
/* Bank Z func7 */
GROUP(gen_clk_z9, 7),
GROUP(gen_clk_z12, 7),
};
static const char * const gpio_periphs_groups[] = {
"GPIOE_0", "GPIOE_1",
"GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
"GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11",
"GPIOB_12", "GPIOB_13",
"GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
"GPIOC_6", "GPIOC_7",
"GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
"GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
"GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
"GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
"GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
"GPIOX_18", "GPIOX_19",
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
"GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10",
"GPIOZ_11", "GPIOZ_12",
"GPIO_TEST_N",
};
static const char * const i2c0_groups[] = {
"i2c0_sda", "i2c0_scl",
};
static const char * const i2c1_groups[] = {
"i2c1_sda_c", "i2c1_scl_c",
"i2c1_sda_d", "i2c1_scl_d",
"i2c1_sda_h", "i2c1_scl_h",
"i2c1_sda_x", "i2c1_scl_x",
};
static const char * const i2c2_groups[] = {
"i2c2_sda_d", "i2c2_scl_d",
"i2c2_sda_h8", "i2c2_scl_h9",
"i2c2_sda_h0", "i2c2_scl_h1l,"
};
static const char * const i2c3_groups[] = {
"i2c3_sda_x", "i2c3_scl_x",
"i2c3_sda_z", "i2c3_scl_z",
};
static const char * const i2c4_groups[] = {
"i2c4_sda_c", "i2c4_scl_c",
"i2c4_sda_d", "i2c4_scl_d",
"i2c4_scl_z", "i2c4_sda_z",
};
static const char * const uart_a_groups[] = {
"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
};
static const char * const uart_b_groups[] = {
"uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c",
"uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d",
};
static const char * const uart_c_groups[] = {
"uart_c_tx", "uart_c_rx",
};
static const char * const uart_d_groups[] = {
"uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h",
"uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z",
};
static const char * const uart_e_groups[] = {
"uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12",
"uart_e_tx_z8", "uart_e_rx_z9",
};
static const char * const emmc_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds",
};
static const char * const nand_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
"emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
"nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0",
};
static const char * const spif_groups[] = {
"spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp",
"spif_cs",
};
static const char * const sdcard_groups[] = {
"sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
"sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd",
"sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
"sdcard_clk_z", "sdcard_cmd_z",
};
static const char * const jtag_1_groups[] = {
"jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo",
};
static const char * const jtag_2_groups[] = {
"jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms",
};
static const char * const pdm_groups[] = {
"pdm_din1_c", "pdm_din0_c", "pdm_dclk_c",
"pdm_dclk_d", "pdm_din0_d", "pdm_din1_d",
"pdm_dclk_h", "pdm_din0_h", "pdm_din1_h",
"pdm_din0_x", "pdm_din1_x", "pdm_dclk_x",
"pdm_din1_z", "pdm_din0_z", "pdm_dclk_z",
};
static const char * const iso7816_groups[] = {
"iso7816_clk_c", "iso7816_data_c",
"iso7816_clk_h", "iso7816_data_h",
};
static const char * const tdm_groups[] = {
"tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", "tdm_sclk1_c",
"tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d",
"tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h",
"tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2",
"tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7",
};
static const char * const mclk_1_groups[] = {
"mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2",
};
static const char * const mclk_2_groups[] = {
"mclk_2",
};
static const char * const remote_out_groups[] = {
"remote_out",
};
static const char * const remote_in_groups[] = {
"remote_in",
};
static const char * const clk12_24_groups[] = {
"clk12_24",
};
static const char * const clk_32k_in_groups[] = {
"clk_32k_in",
};
static const char * const pwm_a_hiz_groups[] = {
"pwm_a_hiz",
};
static const char * const pwm_b_hiz_groups[] = {
"pwm_b_hiz",
};
static const char * const pwm_c_hiz_groups[] = {
"pwm_c_hiz",
};
static const char * const pwm_g_hiz_groups[] = {
"pwm_g_hiz",
};
static const char * const pwm_a_groups[] = {
"pwm_a_d",
};
static const char * const pwm_b_groups[] = {
"pwm_b_d", "pwm_b_x",
};
static const char * const pwm_c_groups[] = {
"pwm_c_d", "pwm_c_x",
};
static const char * const pwm_d_groups[] = {
"pwm_d_d", "pwm_d_h",
};
static const char * const pwm_e_groups[] = {
"pwm_e_x", "pwm_e_z",
};
static const char * const pwm_f_groups[] = {
"pwm_f_x", "pwm_f_z",
};
static const char * const pwm_g_groups[] = {
"pwm_g_d", "pwm_g_z",
};
static const char * const pwm_h_groups[] = {
"pwm_h",
};
static const char * const pwm_i_groups[] = {
"pwm_i_d", "pwm_i_h"
};
static const char * const pwm_j_groups[] = {
"pwm_j",
};
static const char * const mic_mute_groups[] = {
"mic_mute_en", "mic_mute_key",
};
static const char * const hdmitx_groups[] = {
"hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in",
};
static const char * const ao_cec_a_groups[] = {
"ao_cec_a",
};
static const char * const ao_cec_b_groups[] = {
"ao_cec_b",
};
static const char * const spdif_out_groups[] = {
"spdif_out_h", "spdif_out_z",
};
static const char * const spdif_in_groups[] = {
"spdif_in",
};
static const char * const eth_groups[] = {
"eth_link_led", "eth_act_led",
};
static const char * const spi_a_groups[] = {
"spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h",
"spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x",
"spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z",
"spi_a_ss1_z", "spi_a_ss2_z",
};
static const char * const gen_clk_groups[] = {
"gen_clk_h", "gen_clk_z9", "gen_clk_z12",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd",
};
static const char * const i2c_slave_groups[] = {
"i2c_slave_scl", "i2c_slave_sda",
};
static const char * const dtv_groups[] = {
"dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc",
"dtv_a_rf_agc", "dtv_b_rf_agc",
};
static const char * const tsin_a_groups[] = {
"tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0",
};
static const char * const tsin_b_groups[] = {
"tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c",
"tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z",
};
static const char * const tsin_b1_groups[] = {
"tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0",
};
static const char * const diseqc_out_groups[] = {
"diseqc_out",
};
static const char * const s2_demod_groups[] = {
"s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4",
"s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0",
};
static struct meson_pmx_func meson_s4_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(i2c4),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(uart_d),
FUNCTION(uart_e),
FUNCTION(emmc),
FUNCTION(nand),
FUNCTION(spif),
FUNCTION(sdcard),
FUNCTION(jtag_1),
FUNCTION(jtag_2),
FUNCTION(pdm),
FUNCTION(iso7816),
FUNCTION(tdm),
FUNCTION(mclk_1),
FUNCTION(mclk_2),
FUNCTION(remote_out),
FUNCTION(remote_in),
FUNCTION(clk12_24),
FUNCTION(clk_32k_in),
FUNCTION(pwm_a_hiz),
FUNCTION(pwm_b_hiz),
FUNCTION(pwm_c_hiz),
FUNCTION(pwm_g_hiz),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f),
FUNCTION(pwm_g),
FUNCTION(pwm_h),
FUNCTION(pwm_i),
FUNCTION(pwm_j),
FUNCTION(mic_mute),
FUNCTION(hdmitx),
FUNCTION(ao_cec_a),
FUNCTION(ao_cec_b),
FUNCTION(spdif_out),
FUNCTION(spdif_in),
FUNCTION(eth),
FUNCTION(spi_a),
FUNCTION(gen_clk),
FUNCTION(sdio),
FUNCTION(i2c_slave),
FUNCTION(dtv),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
FUNCTION(tsin_b1),
FUNCTION(diseqc_out),
FUNCTION(s2_demod),
};
static struct meson_bank meson_s4_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13,
0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21,
0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0),
BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23,
0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0),
BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35,
0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0),
BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47,
0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0),
BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67,
0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0),
BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80,
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1,
0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
};
static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
/*name first lask reg offset*/
BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0),
BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0),
BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0),
BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0),
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
};
static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
.pmx_banks = meson_s4_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
};
static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_s4_periphs_pins,
.groups = meson_s4_periphs_groups,
.funcs = meson_s4_periphs_functions,
.banks = meson_s4_periphs_banks,
.num_pins = ARRAY_SIZE(meson_s4_periphs_pins),
.num_groups = ARRAY_SIZE(meson_s4_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_s4_periphs_functions),
.num_banks = ARRAY_SIZE(meson_s4_periphs_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_s4_periphs_pmx_banks_data,
.parse_dt = &meson_a1_parse_dt_extra,
};
static const struct of_device_id meson_s4_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-s4-periphs-pinctrl",
.data = &meson_s4_periphs_pinctrl_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match);
static struct platform_driver meson_s4_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-s4-pinctrl",
.of_match_table = meson_s4_pinctrl_dt_match,
},
};
module_platform_driver(meson_s4_pinctrl_driver);
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-s4.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* First generation of pinmux driver for Amlogic Meson SoCs
*
* Copyright (C) 2014 Beniamino Galvani <[email protected]>
* Copyright (C) 2017 Jerome Brunet <[email protected]>
*/
/* For this first generation of pinctrl driver every pinmux group can be
* enabled by a specific bit in the first register range. When all groups for
* a given pin are disabled the pin acts as a GPIO.
*/
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson8-pmx.h"
/**
* meson8_pmx_disable_other_groups() - disable other groups using a given pin
*
* @pc: meson pin controller device
* @pin: number of the pin
* @sel_group: index of the selected group, or -1 if none
*
* The function disables all pinmux groups using a pin except the
* selected one. If @sel_group is -1 all groups are disabled, leaving
* the pin in GPIO mode.
*/
static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc,
unsigned int pin, int sel_group)
{
struct meson_pmx_group *group;
struct meson8_pmx_data *pmx_data;
int i, j;
for (i = 0; i < pc->data->num_groups; i++) {
group = &pc->data->groups[i];
pmx_data = (struct meson8_pmx_data *)group->data;
if (pmx_data->is_gpio || i == sel_group)
continue;
for (j = 0; j < group->num_pins; j++) {
if (group->pins[j] == pin) {
/* We have found a group using the pin */
regmap_update_bits(pc->reg_mux,
pmx_data->reg * 4,
BIT(pmx_data->bit), 0);
}
}
}
}
static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
unsigned group_num)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
struct meson8_pmx_data *pmx_data =
(struct meson8_pmx_data *)group->data;
int i, ret = 0;
dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
group->name);
/*
* Disable groups using the same pin.
* The selected group is not disabled to avoid glitches.
*/
for (i = 0; i < group->num_pins; i++)
meson8_pmx_disable_other_groups(pc, group->pins[i], group_num);
/* Function 0 (GPIO) doesn't need any additional setting */
if (func_num)
ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4,
BIT(pmx_data->bit),
BIT(pmx_data->bit));
return ret;
}
static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
meson8_pmx_disable_other_groups(pc, offset, -1);
return 0;
}
const struct pinmux_ops meson8_pmx_ops = {
.set_mux = meson8_pmx_set_mux,
.get_functions_count = meson_pmx_get_funcs_count,
.get_function_name = meson_pmx_get_func_name,
.get_function_groups = meson_pmx_get_groups,
.gpio_request_enable = meson8_pmx_request_gpio,
};
EXPORT_SYMBOL_GPL(meson8_pmx_ops);
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Pin controller and GPIO driver for Amlogic Meson G12A SoC.
*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <[email protected]>
* Author: Yixun Lan <[email protected]>
*/
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static const struct pinctrl_pin_desc meson_g12a_periphs_pins[] = {
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(GPIOZ_11),
MESON_PIN(GPIOZ_12),
MESON_PIN(GPIOZ_13),
MESON_PIN(GPIOZ_14),
MESON_PIN(GPIOZ_15),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(GPIOH_4),
MESON_PIN(GPIOH_5),
MESON_PIN(GPIOH_6),
MESON_PIN(GPIOH_7),
MESON_PIN(GPIOH_8),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(BOOT_15),
MESON_PIN(GPIOC_0),
MESON_PIN(GPIOC_1),
MESON_PIN(GPIOC_2),
MESON_PIN(GPIOC_3),
MESON_PIN(GPIOC_4),
MESON_PIN(GPIOC_5),
MESON_PIN(GPIOC_6),
MESON_PIN(GPIOC_7),
MESON_PIN(GPIOA_0),
MESON_PIN(GPIOA_1),
MESON_PIN(GPIOA_2),
MESON_PIN(GPIOA_3),
MESON_PIN(GPIOA_4),
MESON_PIN(GPIOA_5),
MESON_PIN(GPIOA_6),
MESON_PIN(GPIOA_7),
MESON_PIN(GPIOA_8),
MESON_PIN(GPIOA_9),
MESON_PIN(GPIOA_10),
MESON_PIN(GPIOA_11),
MESON_PIN(GPIOA_12),
MESON_PIN(GPIOA_13),
MESON_PIN(GPIOA_14),
MESON_PIN(GPIOA_15),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOX_19),
};
static const struct pinctrl_pin_desc meson_g12a_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIOAO_10),
MESON_PIN(GPIOAO_11),
MESON_PIN(GPIOE_0),
MESON_PIN(GPIOE_1),
MESON_PIN(GPIOE_2),
};
/* emmc */
static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 };
static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 };
static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 };
static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 };
static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 };
static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 };
static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 };
static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 };
static const unsigned int emmc_clk_pins[] = { BOOT_8 };
static const unsigned int emmc_cmd_pins[] = { BOOT_10 };
static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 };
/* nand */
static const unsigned int nand_wen_clk_pins[] = { BOOT_8 };
static const unsigned int nand_ale_pins[] = { BOOT_9 };
static const unsigned int nand_cle_pins[] = { BOOT_10 };
static const unsigned int nand_ce0_pins[] = { BOOT_11 };
static const unsigned int nand_ren_wr_pins[] = { BOOT_12 };
static const unsigned int nand_rb0_pins[] = { BOOT_14 };
static const unsigned int nand_ce1_pins[] = { BOOT_15 };
/* nor */
static const unsigned int nor_hold_pins[] = { BOOT_3 };
static const unsigned int nor_d_pins[] = { BOOT_4 };
static const unsigned int nor_q_pins[] = { BOOT_5 };
static const unsigned int nor_c_pins[] = { BOOT_6 };
static const unsigned int nor_wp_pins[] = { BOOT_7 };
static const unsigned int nor_cs_pins[] = { BOOT_14 };
/* sdio */
static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
/* sdcard */
static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 };
static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 };
static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 };
static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 };
static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 };
static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 };
/* spi0 */
static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 };
static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 };
static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 };
static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 };
static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 };
static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 };
static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 };
static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 };
/* spi1 */
static const unsigned int spi1_mosi_pins[] = { GPIOH_4 };
static const unsigned int spi1_miso_pins[] = { GPIOH_5 };
static const unsigned int spi1_ss0_pins[] = { GPIOH_6 };
static const unsigned int spi1_clk_pins[] = { GPIOH_7 };
/* i2c0 */
static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 };
static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 };
static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 };
static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 };
static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 };
static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 };
/* i2c1 */
static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 };
static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 };
static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 };
static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 };
static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 };
static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 };
/* i2c2 */
static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 };
static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 };
static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 };
static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 };
/* i2c3 */
static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 };
static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 };
static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 };
static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 };
/* uart_a */
static const unsigned int uart_a_tx_pins[] = { GPIOX_12 };
static const unsigned int uart_a_rx_pins[] = { GPIOX_13 };
static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
/* uart_b */
static const unsigned int uart_b_tx_pins[] = { GPIOX_6 };
static const unsigned int uart_b_rx_pins[] = { GPIOX_7 };
/* uart_c */
static const unsigned int uart_c_rts_pins[] = { GPIOH_4 };
static const unsigned int uart_c_cts_pins[] = { GPIOH_5 };
static const unsigned int uart_c_rx_pins[] = { GPIOH_6 };
static const unsigned int uart_c_tx_pins[] = { GPIOH_7 };
/* uart_ao_a_c */
static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 };
static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 };
/* iso7816 */
static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 };
static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 };
static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 };
static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 };
static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 };
static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
/* eth */
static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 };
static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 };
static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 };
static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
static const unsigned int eth_txen_pins[] = { GPIOZ_9 };
static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 };
static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 };
static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
/* pwm_a */
static const unsigned int pwm_a_pins[] = { GPIOX_6 };
/* pwm_b */
static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 };
static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 };
/* pwm_c */
static const unsigned int pwm_c_c_pins[] = { GPIOC_4 };
static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 };
static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 };
/* pwm_d */
static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 };
static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 };
/* pwm_e */
static const unsigned int pwm_e_pins[] = { GPIOX_16 };
/* pwm_f */
static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 };
static const unsigned int pwm_f_a_pins[] = { GPIOA_11 };
static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
static const unsigned int pwm_f_h_pins[] = { GPIOH_5 };
/* cec_ao */
static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 };
static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 };
/* jtag_b */
static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
/* bt565_a */
static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 };
static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 };
static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 };
static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 };
static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 };
static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 };
static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 };
static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 };
static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 };
static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 };
static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 };
/* tsin_a */
static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 };
static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 };
static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 };
static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 };
/* tsin_b */
static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 };
static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 };
static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 };
static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 };
static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 };
static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 };
static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 };
static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 };
static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 };
static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 };
static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 };
static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 };
static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 };
static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 };
static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 };
static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 };
/* hdmitx */
static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 };
static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
/* pdm */
static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 };
static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 };
static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 };
static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 };
static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 };
static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 };
static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 };
static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 };
static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 };
static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 };
static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 };
static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 };
static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 };
static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 };
static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 };
static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 };
static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 };
/* spdif_in */
static const unsigned int spdif_in_h_pins[] = { GPIOH_5 };
static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 };
static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 };
/* spdif_out */
static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 };
static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 };
/* mclk0 */
static const unsigned int mclk0_a_pins[] = { GPIOA_0 };
/* mclk1 */
static const unsigned int mclk1_x_pins[] = { GPIOX_5 };
static const unsigned int mclk1_z_pins[] = { GPIOZ_8 };
static const unsigned int mclk1_a_pins[] = { GPIOA_11 };
/* tdm */
static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 };
static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 };
static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 };
static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 };
static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 };
static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 };
static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 };
static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 };
static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 };
static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 };
static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 };
static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 };
static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 };
static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 };
static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 };
static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 };
static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 };
static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 };
static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 };
static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 };
static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 };
static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 };
static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 };
static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 };
static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 };
static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 };
static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 };
static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 };
static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 };
static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 };
static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 };
static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 };
static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 };
static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 };
static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 };
static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 };
static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 };
static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 };
static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 };
static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 };
static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 };
static struct meson_pmx_group meson_g12a_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(GPIOZ_11),
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(GPIOZ_15),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(GPIOH_4),
GPIO_GROUP(GPIOH_5),
GPIO_GROUP(GPIOH_6),
GPIO_GROUP(GPIOH_7),
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(GPIOC_0),
GPIO_GROUP(GPIOC_1),
GPIO_GROUP(GPIOC_2),
GPIO_GROUP(GPIOC_3),
GPIO_GROUP(GPIOC_4),
GPIO_GROUP(GPIOC_5),
GPIO_GROUP(GPIOC_6),
GPIO_GROUP(GPIOC_7),
GPIO_GROUP(GPIOA_0),
GPIO_GROUP(GPIOA_1),
GPIO_GROUP(GPIOA_2),
GPIO_GROUP(GPIOA_3),
GPIO_GROUP(GPIOA_4),
GPIO_GROUP(GPIOA_5),
GPIO_GROUP(GPIOA_6),
GPIO_GROUP(GPIOA_7),
GPIO_GROUP(GPIOA_8),
GPIO_GROUP(GPIOA_9),
GPIO_GROUP(GPIOA_10),
GPIO_GROUP(GPIOA_11),
GPIO_GROUP(GPIOA_12),
GPIO_GROUP(GPIOA_13),
GPIO_GROUP(GPIOA_14),
GPIO_GROUP(GPIOA_15),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOX_19),
/* bank BOOT */
GROUP(emmc_nand_d0, 1),
GROUP(emmc_nand_d1, 1),
GROUP(emmc_nand_d2, 1),
GROUP(emmc_nand_d3, 1),
GROUP(emmc_nand_d4, 1),
GROUP(emmc_nand_d5, 1),
GROUP(emmc_nand_d6, 1),
GROUP(emmc_nand_d7, 1),
GROUP(emmc_clk, 1),
GROUP(emmc_cmd, 1),
GROUP(emmc_nand_ds, 1),
GROUP(nand_ce0, 2),
GROUP(nand_ale, 2),
GROUP(nand_cle, 2),
GROUP(nand_wen_clk, 2),
GROUP(nand_ren_wr, 2),
GROUP(nand_rb0, 2),
GROUP(nand_ce1, 2),
GROUP(nor_hold, 3),
GROUP(nor_d, 3),
GROUP(nor_q, 3),
GROUP(nor_c, 3),
GROUP(nor_wp, 3),
GROUP(nor_cs, 3),
/* bank GPIOZ */
GROUP(sdcard_d0_z, 5),
GROUP(sdcard_d1_z, 5),
GROUP(sdcard_d2_z, 5),
GROUP(sdcard_d3_z, 5),
GROUP(sdcard_clk_z, 5),
GROUP(sdcard_cmd_z, 5),
GROUP(i2c0_sda_z0, 4),
GROUP(i2c0_sck_z1, 4),
GROUP(i2c0_sda_z7, 7),
GROUP(i2c0_sck_z8, 7),
GROUP(i2c2_sda_z, 3),
GROUP(i2c2_sck_z, 3),
GROUP(iso7816_clk_z, 3),
GROUP(iso7816_data_z, 3),
GROUP(eth_mdio, 1),
GROUP(eth_mdc, 1),
GROUP(eth_rgmii_rx_clk, 1),
GROUP(eth_rx_dv, 1),
GROUP(eth_rxd0, 1),
GROUP(eth_rxd1, 1),
GROUP(eth_rxd2_rgmii, 1),
GROUP(eth_rxd3_rgmii, 1),
GROUP(eth_rgmii_tx_clk, 1),
GROUP(eth_txen, 1),
GROUP(eth_txd0, 1),
GROUP(eth_txd1, 1),
GROUP(eth_txd2_rgmii, 1),
GROUP(eth_txd3_rgmii, 1),
GROUP(eth_link_led, 1),
GROUP(eth_act_led, 1),
GROUP(bt565_a_vs, 2),
GROUP(bt565_a_hs, 2),
GROUP(bt565_a_clk, 2),
GROUP(bt565_a_din0, 2),
GROUP(bt565_a_din1, 2),
GROUP(bt565_a_din2, 2),
GROUP(bt565_a_din3, 2),
GROUP(bt565_a_din4, 2),
GROUP(bt565_a_din5, 2),
GROUP(bt565_a_din6, 2),
GROUP(bt565_a_din7, 2),
GROUP(tsin_b_valid_z, 3),
GROUP(tsin_b_sop_z, 3),
GROUP(tsin_b_din0_z, 3),
GROUP(tsin_b_clk_z, 3),
GROUP(tsin_b_fail, 3),
GROUP(tsin_b_din1, 3),
GROUP(tsin_b_din2, 3),
GROUP(tsin_b_din3, 3),
GROUP(tsin_b_din4, 3),
GROUP(tsin_b_din5, 3),
GROUP(tsin_b_din6, 3),
GROUP(tsin_b_din7, 3),
GROUP(pdm_din0_z, 7),
GROUP(pdm_din1_z, 7),
GROUP(pdm_din2_z, 7),
GROUP(pdm_din3_z, 7),
GROUP(pdm_dclk_z, 7),
GROUP(tdm_c_slv_sclk_z, 6),
GROUP(tdm_c_slv_fs_z, 6),
GROUP(tdm_c_din0_z, 6),
GROUP(tdm_c_din1_z, 6),
GROUP(tdm_c_din2_z, 6),
GROUP(tdm_c_din3_z, 6),
GROUP(tdm_c_sclk_z, 4),
GROUP(tdm_c_fs_z, 4),
GROUP(tdm_c_dout0_z, 4),
GROUP(tdm_c_dout1_z, 4),
GROUP(tdm_c_dout2_z, 4),
GROUP(tdm_c_dout3_z, 4),
GROUP(mclk1_z, 4),
GROUP(pwm_f_z, 5),
/* bank GPIOX */
GROUP(sdio_d0, 1),
GROUP(sdio_d1, 1),
GROUP(sdio_d2, 1),
GROUP(sdio_d3, 1),
GROUP(sdio_clk, 1),
GROUP(sdio_cmd, 1),
GROUP(spi0_mosi_x, 4),
GROUP(spi0_miso_x, 4),
GROUP(spi0_ss0_x, 4),
GROUP(spi0_clk_x, 4),
GROUP(i2c1_sda_x, 5),
GROUP(i2c1_sck_x, 5),
GROUP(i2c2_sda_x, 1),
GROUP(i2c2_sck_x, 1),
GROUP(uart_a_tx, 1),
GROUP(uart_a_rx, 1),
GROUP(uart_a_cts, 1),
GROUP(uart_a_rts, 1),
GROUP(uart_b_tx, 2),
GROUP(uart_b_rx, 2),
GROUP(iso7816_clk_x, 6),
GROUP(iso7816_data_x, 6),
GROUP(pwm_a, 1),
GROUP(pwm_b_x7, 4),
GROUP(pwm_b_x19, 1),
GROUP(pwm_c_x5, 4),
GROUP(pwm_c_x8, 5),
GROUP(pwm_d_x3, 4),
GROUP(pwm_d_x6, 4),
GROUP(pwm_e, 1),
GROUP(pwm_f_x, 1),
GROUP(tsin_a_valid, 3),
GROUP(tsin_a_sop, 3),
GROUP(tsin_a_din0, 3),
GROUP(tsin_a_clk, 3),
GROUP(tsin_b_valid_x, 3),
GROUP(tsin_b_sop_x, 3),
GROUP(tsin_b_din0_x, 3),
GROUP(tsin_b_clk_x, 3),
GROUP(pdm_din0_x, 2),
GROUP(pdm_din1_x, 2),
GROUP(pdm_din2_x, 2),
GROUP(pdm_din3_x, 2),
GROUP(pdm_dclk_x, 2),
GROUP(tdm_a_slv_sclk, 2),
GROUP(tdm_a_slv_fs, 2),
GROUP(tdm_a_din0, 2),
GROUP(tdm_a_din1, 2),
GROUP(tdm_a_sclk, 1),
GROUP(tdm_a_fs, 1),
GROUP(tdm_a_dout0, 1),
GROUP(tdm_a_dout1, 1),
GROUP(mclk1_x, 2),
/* bank GPIOC */
GROUP(sdcard_d0_c, 1),
GROUP(sdcard_d1_c, 1),
GROUP(sdcard_d2_c, 1),
GROUP(sdcard_d3_c, 1),
GROUP(sdcard_clk_c, 1),
GROUP(sdcard_cmd_c, 1),
GROUP(spi0_mosi_c, 5),
GROUP(spi0_miso_c, 5),
GROUP(spi0_ss0_c, 5),
GROUP(spi0_clk_c, 5),
GROUP(i2c0_sda_c, 3),
GROUP(i2c0_sck_c, 3),
GROUP(uart_ao_a_rx_c, 2),
GROUP(uart_ao_a_tx_c, 2),
GROUP(iso7816_clk_c, 5),
GROUP(iso7816_data_c, 5),
GROUP(pwm_c_c, 5),
GROUP(jtag_b_tdo, 2),
GROUP(jtag_b_tdi, 2),
GROUP(jtag_b_clk, 2),
GROUP(jtag_b_tms, 2),
GROUP(pdm_din0_c, 4),
GROUP(pdm_din1_c, 4),
GROUP(pdm_din2_c, 4),
GROUP(pdm_din3_c, 4),
GROUP(pdm_dclk_c, 4),
/* bank GPIOH */
GROUP(spi1_mosi, 3),
GROUP(spi1_miso, 3),
GROUP(spi1_ss0, 3),
GROUP(spi1_clk, 3),
GROUP(i2c1_sda_h2, 2),
GROUP(i2c1_sck_h3, 2),
GROUP(i2c1_sda_h6, 4),
GROUP(i2c1_sck_h7, 4),
GROUP(i2c3_sda_h, 2),
GROUP(i2c3_sck_h, 2),
GROUP(uart_c_tx, 2),
GROUP(uart_c_rx, 2),
GROUP(uart_c_cts, 2),
GROUP(uart_c_rts, 2),
GROUP(iso7816_clk_h, 1),
GROUP(iso7816_data_h, 1),
GROUP(pwm_f_h, 4),
GROUP(cec_ao_a_h, 4),
GROUP(cec_ao_b_h, 5),
GROUP(hdmitx_sda, 1),
GROUP(hdmitx_sck, 1),
GROUP(hdmitx_hpd_in, 1),
GROUP(spdif_out_h, 1),
GROUP(spdif_in_h, 1),
GROUP(tdm_b_din3_h, 6),
GROUP(tdm_b_dout3_h, 5),
/* bank GPIOA */
GROUP(i2c3_sda_a, 2),
GROUP(i2c3_sck_a, 2),
GROUP(pdm_din0_a, 1),
GROUP(pdm_din1_a, 1),
GROUP(pdm_din2_a, 1),
GROUP(pdm_din3_a, 1),
GROUP(pdm_dclk_a, 1),
GROUP(spdif_in_a10, 1),
GROUP(spdif_in_a12, 1),
GROUP(spdif_out_a11, 1),
GROUP(spdif_out_a13, 1),
GROUP(tdm_b_slv_sclk, 2),
GROUP(tdm_b_slv_fs, 2),
GROUP(tdm_b_din0, 2),
GROUP(tdm_b_din1, 2),
GROUP(tdm_b_din2, 2),
GROUP(tdm_b_din3_a, 2),
GROUP(tdm_b_sclk, 1),
GROUP(tdm_b_fs, 1),
GROUP(tdm_b_dout0, 1),
GROUP(tdm_b_dout1, 1),
GROUP(tdm_b_dout2, 3),
GROUP(tdm_b_dout3_a, 3),
GROUP(tdm_c_slv_sclk_a, 3),
GROUP(tdm_c_slv_fs_a, 3),
GROUP(tdm_c_din0_a, 3),
GROUP(tdm_c_din1_a, 3),
GROUP(tdm_c_din2_a, 3),
GROUP(tdm_c_din3_a, 3),
GROUP(tdm_c_sclk_a, 2),
GROUP(tdm_c_fs_a, 2),
GROUP(tdm_c_dout0_a, 2),
GROUP(tdm_c_dout1_a, 2),
GROUP(tdm_c_dout2_a, 2),
GROUP(tdm_c_dout3_a, 2),
GROUP(mclk0_a, 1),
GROUP(mclk1_a, 2),
GROUP(pwm_f_a, 3),
};
/* uart_ao_a */
static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 };
static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 };
static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 };
static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 };
/* uart_ao_b */
static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 };
static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 };
static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 };
static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 };
static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 };
static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 };
/* i2c_ao */
static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 };
static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 };
static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 };
static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 };
/* i2c_ao_slave */
static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 };
static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 };
/* ir_in */
static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 };
/* ir_out */
static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 };
/* pwm_a_e */
static const unsigned int pwm_a_e_pins[] = { GPIOE_2 };
/* pwm_ao_a */
static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 };
static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 };
/* pwm_ao_b */
static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 };
/* pwm_ao_c */
static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 };
static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 };
static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 };
/* pwm_ao_d */
static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 };
static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 };
static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 };
/* jtag_a */
static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 };
static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 };
static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 };
static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 };
/* cec_ao */
static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 };
static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 };
/* tsin_ao_a */
static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 };
static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 };
static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 };
static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 };
/* spdif_ao_out */
static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 };
/* tdm_ao_b */
static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 };
static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 };
static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 };
static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 };
static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 };
static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 };
static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 };
static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 };
static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 };
static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 };
/* mclk0_ao */
static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 };
static struct meson_pmx_group meson_g12a_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
GPIO_GROUP(GPIOAO_10),
GPIO_GROUP(GPIOAO_11),
GPIO_GROUP(GPIOE_0),
GPIO_GROUP(GPIOE_1),
GPIO_GROUP(GPIOE_2),
/* bank AO */
GROUP(uart_ao_a_tx, 1),
GROUP(uart_ao_a_rx, 1),
GROUP(uart_ao_a_cts, 1),
GROUP(uart_ao_a_rts, 1),
GROUP(uart_ao_b_tx_2, 2),
GROUP(uart_ao_b_rx_3, 2),
GROUP(uart_ao_b_tx_8, 3),
GROUP(uart_ao_b_rx_9, 3),
GROUP(uart_ao_b_cts, 2),
GROUP(uart_ao_b_rts, 2),
GROUP(i2c_ao_sck, 1),
GROUP(i2c_ao_sda, 1),
GROUP(i2c_ao_sck_e, 4),
GROUP(i2c_ao_sda_e, 4),
GROUP(i2c_ao_slave_sck, 3),
GROUP(i2c_ao_slave_sda, 3),
GROUP(remote_ao_input, 1),
GROUP(remote_ao_out, 1),
GROUP(pwm_a_e, 3),
GROUP(pwm_ao_a, 3),
GROUP(pwm_ao_a_hiz, 2),
GROUP(pwm_ao_b, 3),
GROUP(pwm_ao_c_4, 3),
GROUP(pwm_ao_c_hiz, 4),
GROUP(pwm_ao_c_6, 3),
GROUP(pwm_ao_d_5, 3),
GROUP(pwm_ao_d_10, 3),
GROUP(pwm_ao_d_e, 3),
GROUP(jtag_a_tdi, 1),
GROUP(jtag_a_tdo, 1),
GROUP(jtag_a_clk, 1),
GROUP(jtag_a_tms, 1),
GROUP(cec_ao_a, 1),
GROUP(cec_ao_b, 2),
GROUP(tsin_ao_asop, 4),
GROUP(tsin_ao_adin0, 4),
GROUP(tsin_ao_aclk, 4),
GROUP(tsin_ao_a_valid, 4),
GROUP(spdif_ao_out, 4),
GROUP(tdm_ao_b_dout0, 5),
GROUP(tdm_ao_b_dout1, 5),
GROUP(tdm_ao_b_dout2, 5),
GROUP(tdm_ao_b_fs, 5),
GROUP(tdm_ao_b_sclk, 5),
GROUP(tdm_ao_b_din0, 6),
GROUP(tdm_ao_b_din1, 6),
GROUP(tdm_ao_b_din2, 6),
GROUP(tdm_ao_b_slv_fs, 6),
GROUP(tdm_ao_b_slv_sclk, 6),
GROUP(mclk0_ao, 5),
};
static const char * const gpio_periphs_groups[] = {
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
"GPIOZ_15",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
"GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15",
"GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
"GPIOC_5", "GPIOC_6", "GPIOC_7",
"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
"GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
"GPIOA_15",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
};
static const char * const emmc_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"emmc_clk", "emmc_cmd", "emmc_nand_ds",
};
static const char * const nand_groups[] = {
"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
"emmc_nand_d6", "emmc_nand_d7",
"nand_ce0", "nand_ale", "nand_cle",
"nand_wen_clk", "nand_ren_wr", "nand_rb0",
"emmc_nand_ds", "nand_ce1",
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs",
"nor_hold", "nor_wp",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_cmd", "sdio_clk", "sdio_dummy",
};
static const char * const sdcard_groups[] = {
"sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
"sdcard_clk_c", "sdcard_cmd_c",
"sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
"sdcard_clk_z", "sdcard_cmd_z",
};
static const char * const spi0_groups[] = {
"spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c",
"spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x",
};
static const char * const spi1_groups[] = {
"spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk",
};
static const char * const i2c0_groups[] = {
"i2c0_sda_c", "i2c0_sck_c",
"i2c0_sda_z0", "i2c0_sck_z1",
"i2c0_sda_z7", "i2c0_sck_z8",
};
static const char * const i2c1_groups[] = {
"i2c1_sda_x", "i2c1_sck_x",
"i2c1_sda_h2", "i2c1_sck_h3",
"i2c1_sda_h6", "i2c1_sck_h7",
};
static const char * const i2c2_groups[] = {
"i2c2_sda_x", "i2c2_sck_x",
"i2c2_sda_z", "i2c2_sck_z",
};
static const char * const i2c3_groups[] = {
"i2c3_sda_h", "i2c3_sck_h",
"i2c3_sda_a", "i2c3_sck_a",
};
static const char * const uart_a_groups[] = {
"uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
};
static const char * const uart_b_groups[] = {
"uart_b_tx", "uart_b_rx",
};
static const char * const uart_c_groups[] = {
"uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts",
};
static const char * const uart_ao_a_c_groups[] = {
"uart_ao_a_rx_c", "uart_ao_a_tx_c",
};
static const char * const iso7816_groups[] = {
"iso7816_clk_c", "iso7816_data_c",
"iso7816_clk_x", "iso7816_data_x",
"iso7816_clk_h", "iso7816_data_h",
"iso7816_clk_z", "iso7816_data_z",
};
static const char * const eth_groups[] = {
"eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
"eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk",
"eth_txd0", "eth_txd1", "eth_txen", "eth_mdc",
"eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio",
"eth_link_led", "eth_act_led",
};
static const char * const pwm_a_groups[] = {
"pwm_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b_x7", "pwm_b_x19",
};
static const char * const pwm_c_groups[] = {
"pwm_c_c", "pwm_c_x5", "pwm_c_x8",
};
static const char * const pwm_d_groups[] = {
"pwm_d_x3", "pwm_d_x6",
};
static const char * const pwm_e_groups[] = {
"pwm_e",
};
static const char * const pwm_f_groups[] = {
"pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h",
};
static const char * const cec_ao_a_h_groups[] = {
"cec_ao_a_h",
};
static const char * const cec_ao_b_h_groups[] = {
"cec_ao_b_h",
};
static const char * const jtag_b_groups[] = {
"jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms",
};
static const char * const bt565_a_groups[] = {
"bt565_a_vs", "bt565_a_hs", "bt565_a_clk",
"bt565_a_din0", "bt565_a_din1", "bt565_a_din2",
"bt565_a_din3", "bt565_a_din4", "bt565_a_din5",
"bt565_a_din6", "bt565_a_din7",
};
static const char * const tsin_a_groups[] = {
"tsin_a_valid", "tsin_a_sop", "tsin_a_din0",
"tsin_a_clk",
};
static const char * const tsin_b_groups[] = {
"tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x",
"tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z",
"tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3",
"tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7",
};
static const char * const hdmitx_groups[] = {
"hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in",
};
static const char * const pdm_groups[] = {
"pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c",
"pdm_dclk_c",
"pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x",
"pdm_dclk_x",
"pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z",
"pdm_dclk_z",
"pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a",
"pdm_dclk_a",
};
static const char * const spdif_in_groups[] = {
"spdif_in_h", "spdif_in_a10", "spdif_in_a12",
};
static const char * const spdif_out_groups[] = {
"spdif_out_h", "spdif_out_a11", "spdif_out_a13",
};
static const char * const mclk0_groups[] = {
"mclk0_a",
};
static const char * const mclk1_groups[] = {
"mclk1_x", "mclk1_z", "mclk1_a",
};
static const char * const tdm_a_groups[] = {
"tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs",
"tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1",
};
static const char * const tdm_b_groups[] = {
"tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs",
"tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
"tdm_b_din3_a", "tdm_b_din3_h",
"tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2",
"tdm_b_dout3_a", "tdm_b_dout3_h",
};
static const char * const tdm_c_groups[] = {
"tdm_c_slv_sclk_a", "tdm_c_slv_fs_a",
"tdm_c_slv_sclk_z", "tdm_c_slv_fs_z",
"tdm_c_sclk_a", "tdm_c_fs_a",
"tdm_c_sclk_z", "tdm_c_fs_z",
"tdm_c_din0_a", "tdm_c_din1_a",
"tdm_c_din2_a", "tdm_c_din3_a",
"tdm_c_din0_z", "tdm_c_din1_z",
"tdm_c_din2_z", "tdm_c_din3_z",
"tdm_c_dout0_a", "tdm_c_dout1_a",
"tdm_c_dout2_a", "tdm_c_dout3_a",
"tdm_c_dout0_z", "tdm_c_dout1_z",
"tdm_c_dout2_z", "tdm_c_dout3_z",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
"GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2",
};
static const char * const uart_ao_a_groups[] = {
"uart_ao_a_tx", "uart_ao_a_rx",
"uart_ao_a_cts", "uart_ao_a_rts",
};
static const char * const uart_ao_b_groups[] = {
"uart_ao_b_tx_2", "uart_ao_b_rx_3",
"uart_ao_b_tx_8", "uart_ao_b_rx_9",
"uart_ao_b_cts", "uart_ao_b_rts",
};
static const char * const i2c_ao_groups[] = {
"i2c_ao_sck", "i2c_ao_sda",
"i2c_ao_sck_e", "i2c_ao_sda_e",
};
static const char * const i2c_ao_slave_groups[] = {
"i2c_ao_slave_sck", "i2c_ao_slave_sda",
};
static const char * const remote_ao_input_groups[] = {
"remote_ao_input",
};
static const char * const remote_ao_out_groups[] = {
"remote_ao_out",
};
static const char * const pwm_a_e_groups[] = {
"pwm_a_e",
};
static const char * const pwm_ao_a_groups[] = {
"pwm_ao_a", "pwm_ao_a_hiz",
};
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b",
};
static const char * const pwm_ao_c_groups[] = {
"pwm_ao_c_4", "pwm_ao_c_hiz",
"pwm_ao_c_6",
};
static const char * const pwm_ao_d_groups[] = {
"pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e",
};
static const char * const jtag_a_groups[] = {
"jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms",
};
static const char * const cec_ao_a_groups[] = {
"cec_ao_a",
};
static const char * const cec_ao_b_groups[] = {
"cec_ao_b",
};
static const char * const tsin_ao_a_groups[] = {
"tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid",
};
static const char * const spdif_ao_out_groups[] = {
"spdif_ao_out",
};
static const char * const tdm_ao_b_groups[] = {
"tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2",
"tdm_ao_b_fs", "tdm_ao_b_sclk",
"tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2",
"tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk",
};
static const char * const mclk0_ao_groups[] = {
"mclk0_ao",
};
static struct meson_pmx_func meson_g12a_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(spi0),
FUNCTION(spi1),
FUNCTION(sdio),
FUNCTION(nand),
FUNCTION(sdcard),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(uart_ao_a_c),
FUNCTION(iso7816),
FUNCTION(eth),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f),
FUNCTION(cec_ao_a_h),
FUNCTION(cec_ao_b_h),
FUNCTION(jtag_b),
FUNCTION(bt565_a),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
FUNCTION(hdmitx),
FUNCTION(pdm),
FUNCTION(spdif_out),
FUNCTION(spdif_in),
FUNCTION(mclk0),
FUNCTION(mclk1),
FUNCTION(tdm_a),
FUNCTION(tdm_b),
FUNCTION(tdm_c),
};
static struct meson_pmx_func meson_g12a_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao_a),
FUNCTION(uart_ao_b),
FUNCTION(i2c_ao),
FUNCTION(i2c_ao_slave),
FUNCTION(remote_ao_input),
FUNCTION(remote_ao_out),
FUNCTION(pwm_a_e),
FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
FUNCTION(pwm_ao_c),
FUNCTION(pwm_ao_d),
FUNCTION(jtag_a),
FUNCTION(cec_ao_a),
FUNCTION(cec_ao_b),
FUNCTION(tsin_ao_a),
FUNCTION(spdif_ao_out),
FUNCTION(tdm_ao_b),
FUNCTION(mclk0_ao),
};
static struct meson_bank meson_g12a_periphs_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15,
4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0),
BANK_DS("H", GPIOH_0, GPIOH_8, IRQID_GPIOH_0, IRQID_GPIOH_8,
3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0),
BANK_DS("BOOT", BOOT_0, BOOT_15, IRQID_BOOT_0, IRQID_BOOT_15,
0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0),
BANK_DS("C", GPIOC_0, GPIOC_7, IRQID_GPIOC_0, IRQID_GPIOC_7,
1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0),
BANK_DS("A", GPIOA_0, GPIOA_15, IRQID_GPIOA_0, IRQID_GPIOA_15,
5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0),
BANK_DS("X", GPIOX_0, GPIOX_19, IRQID_GPIOX_0, IRQID_GPIOX_19,
2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0),
};
static struct meson_bank meson_g12a_aobus_banks[] = {
/* name first last irq pullen pull dir out in ds */
BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11,
3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0),
/* GPIOE actually located in the AO bank */
BANK_DS("E", GPIOE_0, GPIOE_2, IRQID_GPIOE_0, IRQID_GPIOE_2,
3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0),
};
static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
/* name first last reg offset */
BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0),
BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0),
BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0),
BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0),
BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
};
static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
.pmx_banks = meson_g12a_periphs_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks),
};
static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0),
BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16),
};
static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
.pmx_banks = meson_g12a_aobus_pmx_banks,
.num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks),
};
static int meson_g12a_aobus_parse_dt_extra(struct meson_pinctrl *pc)
{
pc->reg_pull = pc->reg_gpio;
pc->reg_pullen = pc->reg_gpio;
return 0;
}
static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_g12a_periphs_pins,
.groups = meson_g12a_periphs_groups,
.funcs = meson_g12a_periphs_functions,
.banks = meson_g12a_periphs_banks,
.num_pins = ARRAY_SIZE(meson_g12a_periphs_pins),
.num_groups = ARRAY_SIZE(meson_g12a_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions),
.num_banks = ARRAY_SIZE(meson_g12a_periphs_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_g12a_periphs_pmx_banks_data,
};
static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_g12a_aobus_pins,
.groups = meson_g12a_aobus_groups,
.funcs = meson_g12a_aobus_functions,
.banks = meson_g12a_aobus_banks,
.num_pins = ARRAY_SIZE(meson_g12a_aobus_pins),
.num_groups = ARRAY_SIZE(meson_g12a_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions),
.num_banks = ARRAY_SIZE(meson_g12a_aobus_banks),
.pmx_ops = &meson_axg_pmx_ops,
.pmx_data = &meson_g12a_aobus_pmx_banks_data,
.parse_dt = meson_g12a_aobus_parse_dt_extra,
};
static const struct of_device_id meson_g12a_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-g12a-periphs-pinctrl",
.data = &meson_g12a_periphs_pinctrl_data,
},
{
.compatible = "amlogic,meson-g12a-aobus-pinctrl",
.data = &meson_g12a_aobus_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_g12a_pinctrl_dt_match);
static struct platform_driver meson_g12a_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-g12a-pinctrl",
.of_match_table = meson_g12a_pinctrl_dt_match,
},
};
module_platform_driver(meson_g12a_pinctrl_driver);
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-g12a.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pin controller and GPIO driver for Amlogic Meson GXL.
*
* Copyright (C) 2016 Endless Mobile, Inc.
* Author: Carlo Caione <[email protected]>
*/
#include <dt-bindings/gpio/meson-gxl-gpio.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson8-pmx.h"
static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {
MESON_PIN(GPIOZ_0),
MESON_PIN(GPIOZ_1),
MESON_PIN(GPIOZ_2),
MESON_PIN(GPIOZ_3),
MESON_PIN(GPIOZ_4),
MESON_PIN(GPIOZ_5),
MESON_PIN(GPIOZ_6),
MESON_PIN(GPIOZ_7),
MESON_PIN(GPIOZ_8),
MESON_PIN(GPIOZ_9),
MESON_PIN(GPIOZ_10),
MESON_PIN(GPIOZ_11),
MESON_PIN(GPIOZ_12),
MESON_PIN(GPIOZ_13),
MESON_PIN(GPIOZ_14),
MESON_PIN(GPIOZ_15),
MESON_PIN(GPIOH_0),
MESON_PIN(GPIOH_1),
MESON_PIN(GPIOH_2),
MESON_PIN(GPIOH_3),
MESON_PIN(GPIOH_4),
MESON_PIN(GPIOH_5),
MESON_PIN(GPIOH_6),
MESON_PIN(GPIOH_7),
MESON_PIN(GPIOH_8),
MESON_PIN(GPIOH_9),
MESON_PIN(BOOT_0),
MESON_PIN(BOOT_1),
MESON_PIN(BOOT_2),
MESON_PIN(BOOT_3),
MESON_PIN(BOOT_4),
MESON_PIN(BOOT_5),
MESON_PIN(BOOT_6),
MESON_PIN(BOOT_7),
MESON_PIN(BOOT_8),
MESON_PIN(BOOT_9),
MESON_PIN(BOOT_10),
MESON_PIN(BOOT_11),
MESON_PIN(BOOT_12),
MESON_PIN(BOOT_13),
MESON_PIN(BOOT_14),
MESON_PIN(BOOT_15),
MESON_PIN(CARD_0),
MESON_PIN(CARD_1),
MESON_PIN(CARD_2),
MESON_PIN(CARD_3),
MESON_PIN(CARD_4),
MESON_PIN(CARD_5),
MESON_PIN(CARD_6),
MESON_PIN(GPIODV_0),
MESON_PIN(GPIODV_1),
MESON_PIN(GPIODV_2),
MESON_PIN(GPIODV_3),
MESON_PIN(GPIODV_4),
MESON_PIN(GPIODV_5),
MESON_PIN(GPIODV_6),
MESON_PIN(GPIODV_7),
MESON_PIN(GPIODV_8),
MESON_PIN(GPIODV_9),
MESON_PIN(GPIODV_10),
MESON_PIN(GPIODV_11),
MESON_PIN(GPIODV_12),
MESON_PIN(GPIODV_13),
MESON_PIN(GPIODV_14),
MESON_PIN(GPIODV_15),
MESON_PIN(GPIODV_16),
MESON_PIN(GPIODV_17),
MESON_PIN(GPIODV_18),
MESON_PIN(GPIODV_19),
MESON_PIN(GPIODV_20),
MESON_PIN(GPIODV_21),
MESON_PIN(GPIODV_22),
MESON_PIN(GPIODV_23),
MESON_PIN(GPIODV_24),
MESON_PIN(GPIODV_25),
MESON_PIN(GPIODV_26),
MESON_PIN(GPIODV_27),
MESON_PIN(GPIODV_28),
MESON_PIN(GPIODV_29),
MESON_PIN(GPIOX_0),
MESON_PIN(GPIOX_1),
MESON_PIN(GPIOX_2),
MESON_PIN(GPIOX_3),
MESON_PIN(GPIOX_4),
MESON_PIN(GPIOX_5),
MESON_PIN(GPIOX_6),
MESON_PIN(GPIOX_7),
MESON_PIN(GPIOX_8),
MESON_PIN(GPIOX_9),
MESON_PIN(GPIOX_10),
MESON_PIN(GPIOX_11),
MESON_PIN(GPIOX_12),
MESON_PIN(GPIOX_13),
MESON_PIN(GPIOX_14),
MESON_PIN(GPIOX_15),
MESON_PIN(GPIOX_16),
MESON_PIN(GPIOX_17),
MESON_PIN(GPIOX_18),
MESON_PIN(GPIOCLK_0),
MESON_PIN(GPIOCLK_1),
};
static const unsigned int emmc_nand_d07_pins[] = {
BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7,
};
static const unsigned int emmc_clk_pins[] = { BOOT_8 };
static const unsigned int emmc_cmd_pins[] = { BOOT_10 };
static const unsigned int emmc_ds_pins[] = { BOOT_15 };
static const unsigned int nor_d_pins[] = { BOOT_11 };
static const unsigned int nor_q_pins[] = { BOOT_12 };
static const unsigned int nor_c_pins[] = { BOOT_13 };
static const unsigned int nor_cs_pins[] = { BOOT_15 };
static const unsigned int spi_mosi_pins[] = { GPIOX_8 };
static const unsigned int spi_miso_pins[] = { GPIOX_9 };
static const unsigned int spi_ss0_pins[] = { GPIOX_10 };
static const unsigned int spi_sclk_pins[] = { GPIOX_11 };
static const unsigned int sdcard_d0_pins[] = { CARD_1 };
static const unsigned int sdcard_d1_pins[] = { CARD_0 };
static const unsigned int sdcard_d2_pins[] = { CARD_5 };
static const unsigned int sdcard_d3_pins[] = { CARD_4 };
static const unsigned int sdcard_cmd_pins[] = { CARD_3 };
static const unsigned int sdcard_clk_pins[] = { CARD_2 };
static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
static const unsigned int nand_ce0_pins[] = { BOOT_8 };
static const unsigned int nand_ce1_pins[] = { BOOT_9 };
static const unsigned int nand_rb0_pins[] = { BOOT_10 };
static const unsigned int nand_ale_pins[] = { BOOT_11 };
static const unsigned int nand_cle_pins[] = { BOOT_12 };
static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
static const unsigned int nand_ren_wr_pins[] = { BOOT_14 };
static const unsigned int nand_dqs_pins[] = { BOOT_15 };
static const unsigned int uart_tx_a_pins[] = { GPIOX_12 };
static const unsigned int uart_rx_a_pins[] = { GPIOX_13 };
static const unsigned int uart_cts_a_pins[] = { GPIOX_14 };
static const unsigned int uart_rts_a_pins[] = { GPIOX_15 };
static const unsigned int uart_tx_b_pins[] = { GPIODV_24 };
static const unsigned int uart_rx_b_pins[] = { GPIODV_25 };
static const unsigned int uart_cts_b_pins[] = { GPIODV_26 };
static const unsigned int uart_rts_b_pins[] = { GPIODV_27 };
static const unsigned int uart_tx_c_pins[] = { GPIOX_8 };
static const unsigned int uart_rx_c_pins[] = { GPIOX_9 };
static const unsigned int uart_cts_c_pins[] = { GPIOX_10 };
static const unsigned int uart_rts_c_pins[] = { GPIOX_11 };
static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 };
static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 };
static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 };
static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 };
static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 };
static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 };
static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };
static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 };
static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 };
static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 };
static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
static const unsigned int eth_txd2_pins[] = { GPIOZ_12 };
static const unsigned int eth_txd3_pins[] = { GPIOZ_13 };
static const unsigned int pwm_a_pins[] = { GPIOX_6 };
static const unsigned int pwm_b_pins[] = { GPIODV_29 };
static const unsigned int pwm_c_pins[] = { GPIOZ_15 };
static const unsigned int pwm_d_pins[] = { GPIODV_28 };
static const unsigned int pwm_e_pins[] = { GPIOX_16 };
static const unsigned int pwm_f_clk_pins[] = { GPIOCLK_1 };
static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
static const unsigned int i2s_am_clk_pins[] = { GPIOH_6 };
static const unsigned int i2s_out_ao_clk_pins[] = { GPIOH_7 };
static const unsigned int i2s_out_lr_clk_pins[] = { GPIOH_8 };
static const unsigned int i2s_out_ch01_pins[] = { GPIOH_9 };
static const unsigned int i2s_out_ch23_z_pins[] = { GPIOZ_5 };
static const unsigned int i2s_out_ch45_z_pins[] = { GPIOZ_6 };
static const unsigned int i2s_out_ch67_z_pins[] = { GPIOZ_7 };
static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 };
static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 };
static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 };
static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };
static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 };
static const unsigned int tsin_a_dp_pins[] = {
GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,
};
static const unsigned int tsin_b_clk_pins[] = { GPIOH_6 };
static const unsigned int tsin_b_d0_pins[] = { GPIOH_7 };
static const unsigned int tsin_b_sop_pins[] = { GPIOH_8 };
static const unsigned int tsin_b_d_valid_pins[] = { GPIOH_9 };
static const unsigned int tsin_b_fail_z4_pins[] = { GPIOZ_4 };
static const unsigned int tsin_b_clk_z3_pins[] = { GPIOZ_3 };
static const unsigned int tsin_b_d0_z2_pins[] = { GPIOZ_2 };
static const unsigned int tsin_b_sop_z1_pins[] = { GPIOZ_1 };
static const unsigned int tsin_b_d_valid_z0_pins[] = { GPIOZ_0 };
static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
MESON_PIN(GPIOAO_2),
MESON_PIN(GPIOAO_3),
MESON_PIN(GPIOAO_4),
MESON_PIN(GPIOAO_5),
MESON_PIN(GPIOAO_6),
MESON_PIN(GPIOAO_7),
MESON_PIN(GPIOAO_8),
MESON_PIN(GPIOAO_9),
MESON_PIN(GPIO_TEST_N),
};
static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
static const unsigned int uart_tx_ao_b_0_pins[] = { GPIOAO_0 };
static const unsigned int uart_rx_ao_b_1_pins[] = { GPIOAO_1 };
static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 };
static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 };
static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
static const unsigned int i2c_sck_ao_pins[] = {GPIOAO_4 };
static const unsigned int i2c_sda_ao_pins[] = {GPIOAO_5 };
static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 };
static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 };
static const unsigned int remote_input_ao_pins[] = {GPIOAO_7 };
static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 };
static const unsigned int pwm_ao_a_8_pins[] = { GPIOAO_8 };
static const unsigned int pwm_ao_b_pins[] = { GPIOAO_9 };
static const unsigned int pwm_ao_b_6_pins[] = { GPIOAO_6 };
static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_8 };
static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_9 };
static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N };
static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 };
static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 };
static const unsigned int ao_cec_pins[] = { GPIOAO_8 };
static const unsigned int ee_cec_pins[] = { GPIOAO_8 };
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0),
GPIO_GROUP(GPIOZ_1),
GPIO_GROUP(GPIOZ_2),
GPIO_GROUP(GPIOZ_3),
GPIO_GROUP(GPIOZ_4),
GPIO_GROUP(GPIOZ_5),
GPIO_GROUP(GPIOZ_6),
GPIO_GROUP(GPIOZ_7),
GPIO_GROUP(GPIOZ_8),
GPIO_GROUP(GPIOZ_9),
GPIO_GROUP(GPIOZ_10),
GPIO_GROUP(GPIOZ_11),
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(GPIOZ_15),
GPIO_GROUP(GPIOH_0),
GPIO_GROUP(GPIOH_1),
GPIO_GROUP(GPIOH_2),
GPIO_GROUP(GPIOH_3),
GPIO_GROUP(GPIOH_4),
GPIO_GROUP(GPIOH_5),
GPIO_GROUP(GPIOH_6),
GPIO_GROUP(GPIOH_7),
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(GPIOH_9),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(GPIODV_0),
GPIO_GROUP(GPIODV_1),
GPIO_GROUP(GPIODV_2),
GPIO_GROUP(GPIODV_3),
GPIO_GROUP(GPIODV_4),
GPIO_GROUP(GPIODV_5),
GPIO_GROUP(GPIODV_6),
GPIO_GROUP(GPIODV_7),
GPIO_GROUP(GPIODV_8),
GPIO_GROUP(GPIODV_9),
GPIO_GROUP(GPIODV_10),
GPIO_GROUP(GPIODV_11),
GPIO_GROUP(GPIODV_12),
GPIO_GROUP(GPIODV_13),
GPIO_GROUP(GPIODV_14),
GPIO_GROUP(GPIODV_15),
GPIO_GROUP(GPIODV_16),
GPIO_GROUP(GPIODV_17),
GPIO_GROUP(GPIODV_19),
GPIO_GROUP(GPIODV_20),
GPIO_GROUP(GPIODV_21),
GPIO_GROUP(GPIODV_22),
GPIO_GROUP(GPIODV_23),
GPIO_GROUP(GPIODV_24),
GPIO_GROUP(GPIODV_25),
GPIO_GROUP(GPIODV_26),
GPIO_GROUP(GPIODV_27),
GPIO_GROUP(GPIODV_28),
GPIO_GROUP(GPIODV_29),
GPIO_GROUP(GPIOX_0),
GPIO_GROUP(GPIOX_1),
GPIO_GROUP(GPIOX_2),
GPIO_GROUP(GPIOX_3),
GPIO_GROUP(GPIOX_4),
GPIO_GROUP(GPIOX_5),
GPIO_GROUP(GPIOX_6),
GPIO_GROUP(GPIOX_7),
GPIO_GROUP(GPIOX_8),
GPIO_GROUP(GPIOX_9),
GPIO_GROUP(GPIOX_10),
GPIO_GROUP(GPIOX_11),
GPIO_GROUP(GPIOX_12),
GPIO_GROUP(GPIOX_13),
GPIO_GROUP(GPIOX_14),
GPIO_GROUP(GPIOX_15),
GPIO_GROUP(GPIOX_16),
GPIO_GROUP(GPIOX_17),
GPIO_GROUP(GPIOX_18),
GPIO_GROUP(GPIOCLK_0),
GPIO_GROUP(GPIOCLK_1),
GPIO_GROUP(GPIO_TEST_N),
/* Bank X */
GROUP(sdio_d0, 5, 31),
GROUP(sdio_d1, 5, 30),
GROUP(sdio_d2, 5, 29),
GROUP(sdio_d3, 5, 28),
GROUP(sdio_clk, 5, 27),
GROUP(sdio_cmd, 5, 26),
GROUP(sdio_irq, 5, 24),
GROUP(uart_tx_a, 5, 19),
GROUP(uart_rx_a, 5, 18),
GROUP(uart_cts_a, 5, 17),
GROUP(uart_rts_a, 5, 16),
GROUP(uart_tx_c, 5, 13),
GROUP(uart_rx_c, 5, 12),
GROUP(uart_cts_c, 5, 11),
GROUP(uart_rts_c, 5, 10),
GROUP(pwm_a, 5, 25),
GROUP(pwm_e, 5, 15),
GROUP(pwm_f_x, 5, 14),
GROUP(spi_mosi, 5, 3),
GROUP(spi_miso, 5, 2),
GROUP(spi_ss0, 5, 1),
GROUP(spi_sclk, 5, 0),
/* Bank Z */
GROUP(eth_mdio, 4, 23),
GROUP(eth_mdc, 4, 22),
GROUP(eth_clk_rx_clk, 4, 21),
GROUP(eth_rx_dv, 4, 20),
GROUP(eth_rxd0, 4, 19),
GROUP(eth_rxd1, 4, 18),
GROUP(eth_rxd2, 4, 17),
GROUP(eth_rxd3, 4, 16),
GROUP(eth_rgmii_tx_clk, 4, 15),
GROUP(eth_tx_en, 4, 14),
GROUP(eth_txd0, 4, 13),
GROUP(eth_txd1, 4, 12),
GROUP(eth_txd2, 4, 11),
GROUP(eth_txd3, 4, 10),
GROUP(tsin_b_fail_z4, 3, 15),
GROUP(tsin_b_clk_z3, 3, 16),
GROUP(tsin_b_d0_z2, 3, 17),
GROUP(tsin_b_sop_z1, 3, 18),
GROUP(tsin_b_d_valid_z0, 3, 19),
GROUP(pwm_c, 3, 20),
GROUP(i2s_out_ch23_z, 3, 26),
GROUP(i2s_out_ch45_z, 3, 25),
GROUP(i2s_out_ch67_z, 3, 24),
GROUP(eth_link_led, 4, 25),
GROUP(eth_act_led, 4, 24),
/* Bank H */
GROUP(hdmi_hpd, 6, 31),
GROUP(hdmi_sda, 6, 30),
GROUP(hdmi_scl, 6, 29),
GROUP(i2s_am_clk, 6, 26),
GROUP(i2s_out_ao_clk, 6, 25),
GROUP(i2s_out_lr_clk, 6, 24),
GROUP(i2s_out_ch01, 6, 23),
GROUP(spdif_out_h, 6, 28),
GROUP(tsin_b_d0, 6, 17),
GROUP(tsin_b_sop, 6, 18),
GROUP(tsin_b_d_valid, 6, 19),
GROUP(tsin_b_clk, 6, 20),
/* Bank DV */
GROUP(uart_tx_b, 2, 16),
GROUP(uart_rx_b, 2, 15),
GROUP(uart_cts_b, 2, 14),
GROUP(uart_rts_b, 2, 13),
GROUP(i2c_sda_c_dv18, 1, 17),
GROUP(i2c_sck_c_dv19, 1, 16),
GROUP(i2c_sda_a, 1, 15),
GROUP(i2c_sck_a, 1, 14),
GROUP(i2c_sda_b, 1, 13),
GROUP(i2c_sck_b, 1, 12),
GROUP(i2c_sda_c, 1, 11),
GROUP(i2c_sck_c, 1, 10),
GROUP(pwm_b, 2, 11),
GROUP(pwm_d, 2, 12),
GROUP(tsin_a_d0, 2, 4),
GROUP(tsin_a_dp, 2, 3),
GROUP(tsin_a_clk, 2, 2),
GROUP(tsin_a_sop, 2, 1),
GROUP(tsin_a_d_valid, 2, 0),
GROUP(tsin_a_fail, 1, 31),
/* Bank BOOT */
GROUP(emmc_nand_d07, 7, 31),
GROUP(emmc_clk, 7, 30),
GROUP(emmc_cmd, 7, 29),
GROUP(emmc_ds, 7, 28),
GROUP(nor_d, 7, 13),
GROUP(nor_q, 7, 12),
GROUP(nor_c, 7, 11),
GROUP(nor_cs, 7, 10),
GROUP(nand_ce0, 7, 7),
GROUP(nand_ce1, 7, 6),
GROUP(nand_rb0, 7, 5),
GROUP(nand_ale, 7, 4),
GROUP(nand_cle, 7, 3),
GROUP(nand_wen_clk, 7, 2),
GROUP(nand_ren_wr, 7, 1),
GROUP(nand_dqs, 7, 0),
/* Bank CARD */
GROUP(sdcard_d1, 6, 5),
GROUP(sdcard_d0, 6, 4),
GROUP(sdcard_d3, 6, 1),
GROUP(sdcard_d2, 6, 0),
GROUP(sdcard_cmd, 6, 2),
GROUP(sdcard_clk, 6, 3),
/* Bank CLK */
GROUP(pwm_f_clk, 8, 30),
};
static struct meson_pmx_group meson_gxl_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
GPIO_GROUP(GPIOAO_2),
GPIO_GROUP(GPIOAO_3),
GPIO_GROUP(GPIOAO_4),
GPIO_GROUP(GPIOAO_5),
GPIO_GROUP(GPIOAO_6),
GPIO_GROUP(GPIOAO_7),
GPIO_GROUP(GPIOAO_8),
GPIO_GROUP(GPIOAO_9),
/* bank AO */
GROUP(uart_tx_ao_b_0, 0, 26),
GROUP(uart_rx_ao_b_1, 0, 25),
GROUP(uart_tx_ao_b, 0, 24),
GROUP(uart_rx_ao_b, 0, 23),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
GROUP(uart_cts_ao_b, 0, 8),
GROUP(uart_rts_ao_b, 0, 7),
GROUP(i2c_sck_ao, 0, 6),
GROUP(i2c_sda_ao, 0, 5),
GROUP(i2c_slave_sck_ao, 0, 2),
GROUP(i2c_slave_sda_ao, 0, 1),
GROUP(remote_input_ao, 0, 0),
GROUP(pwm_ao_a_3, 0, 22),
GROUP(pwm_ao_b_6, 0, 18),
GROUP(pwm_ao_a_8, 0, 17),
GROUP(pwm_ao_b, 0, 3),
GROUP(i2s_out_ch23_ao, 1, 0),
GROUP(i2s_out_ch45_ao, 1, 1),
GROUP(spdif_out_ao_6, 0, 16),
GROUP(spdif_out_ao_9, 0, 4),
GROUP(ao_cec, 0, 15),
GROUP(ee_cec, 0, 14),
/* test n pin */
GROUP(i2s_out_ch67_ao, 1, 2),
};
static const char * const gpio_periphs_groups[] = {
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
"GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
"GPIOZ_15",
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
"GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15",
"CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
"CARD_5", "CARD_6",
"GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
"GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
"GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
"GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
"GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
"GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18",
};
static const char * const emmc_groups[] = {
"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
};
static const char * const nor_groups[] = {
"nor_d", "nor_q", "nor_c", "nor_cs",
};
static const char * const spi_groups[] = {
"spi_mosi", "spi_miso", "spi_ss0", "spi_sclk",
};
static const char * const sdcard_groups[] = {
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
"sdcard_cmd", "sdcard_clk",
};
static const char * const sdio_groups[] = {
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
"sdio_cmd", "sdio_clk", "sdio_irq",
};
static const char * const nand_groups[] = {
"emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
"nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
};
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
static const char * const uart_b_groups[] = {
"uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
};
static const char * const uart_c_groups[] = {
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
};
static const char * const i2c_a_groups[] = {
"i2c_sck_a", "i2c_sda_a",
};
static const char * const i2c_b_groups[] = {
"i2c_sck_b", "i2c_sda_b",
};
static const char * const i2c_c_groups[] = {
"i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19",
};
static const char * const eth_groups[] = {
"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
"eth_rgmii_tx_clk", "eth_tx_en",
"eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
};
static const char * const pwm_a_groups[] = {
"pwm_a",
};
static const char * const pwm_b_groups[] = {
"pwm_b",
};
static const char * const pwm_c_groups[] = {
"pwm_c",
};
static const char * const pwm_d_groups[] = {
"pwm_d",
};
static const char * const pwm_e_groups[] = {
"pwm_e",
};
static const char * const pwm_f_groups[] = {
"pwm_f_clk", "pwm_f_x",
};
static const char * const hdmi_hpd_groups[] = {
"hdmi_hpd",
};
static const char * const hdmi_i2c_groups[] = {
"hdmi_sda", "hdmi_scl",
};
static const char * const i2s_out_groups[] = {
"i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk",
"i2s_out_ch01", "i2s_out_ch23_z", "i2s_out_ch45_z", "i2s_out_ch67_z",
};
static const char * const spdif_out_groups[] = {
"spdif_out_h",
};
static const char * const eth_led_groups[] = {
"eth_link_led", "eth_act_led",
};
static const char * const tsin_a_groups[] = {
"tsin_a_clk", "tsin_a_sop",
"tsin_a_d_valid", "tsin_a_d0",
"tsin_a_dp", "tsin_a_fail",
};
static const char * const tsin_b_groups[] = {
"tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0",
"tsin_b_clk_z3", "tsin_b_sop_z1", "tsin_b_d_valid_z0", "tsin_b_d0_z2",
"tsin_b_fail_z4",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
"GPIO_TEST_N",
};
static const char * const uart_ao_groups[] = {
"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
};
static const char * const uart_ao_b_groups[] = {
"uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
"uart_tx_ao_b_0", "uart_rx_ao_b_1",
};
static const char * const i2c_ao_groups[] = {
"i2c_sck_ao", "i2c_sda_ao",
};
static const char * const i2c_slave_ao_groups[] = {
"i2c_slave_sck_ao", "i2c_slave_sda_ao",
};
static const char * const remote_input_ao_groups[] = {
"remote_input_ao",
};
static const char * const pwm_ao_a_groups[] = {
"pwm_ao_a_3", "pwm_ao_a_8",
};
static const char * const pwm_ao_b_groups[] = {
"pwm_ao_b", "pwm_ao_b_6",
};
static const char * const i2s_out_ao_groups[] = {
"i2s_out_ch23_ao", "i2s_out_ch45_ao", "i2s_out_ch67_ao",
};
static const char * const spdif_out_ao_groups[] = {
"spdif_out_ao_6", "spdif_out_ao_9",
};
static const char * const cec_ao_groups[] = {
"ao_cec", "ee_cec",
};
static struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(spi),
FUNCTION(sdcard),
FUNCTION(sdio),
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
FUNCTION(i2c_a),
FUNCTION(i2c_b),
FUNCTION(i2c_c),
FUNCTION(eth),
FUNCTION(pwm_a),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
FUNCTION(pwm_e),
FUNCTION(pwm_f),
FUNCTION(hdmi_hpd),
FUNCTION(hdmi_i2c),
FUNCTION(i2s_out),
FUNCTION(spdif_out),
FUNCTION(eth_led),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
};
static struct meson_pmx_func meson_gxl_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_ao),
FUNCTION(i2c_slave_ao),
FUNCTION(remote_input_ao),
FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
FUNCTION(i2s_out_ao),
FUNCTION(spdif_out_ao),
FUNCTION(cec_ao),
};
static struct meson_bank meson_gxl_periphs_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
BANK("H", GPIOH_0, GPIOH_9, 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
BANK("Z", GPIOZ_0, GPIOZ_15, 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
BANK("BOOT", BOOT_0, BOOT_15, 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
};
static struct meson_bank meson_gxl_aobus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
};
static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
.name = "periphs-banks",
.pins = meson_gxl_periphs_pins,
.groups = meson_gxl_periphs_groups,
.funcs = meson_gxl_periphs_functions,
.banks = meson_gxl_periphs_banks,
.num_pins = ARRAY_SIZE(meson_gxl_periphs_pins),
.num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
.num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
.pmx_ops = &meson8_pmx_ops,
};
static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
.name = "aobus-banks",
.pins = meson_gxl_aobus_pins,
.groups = meson_gxl_aobus_groups,
.funcs = meson_gxl_aobus_functions,
.banks = meson_gxl_aobus_banks,
.num_pins = ARRAY_SIZE(meson_gxl_aobus_pins),
.num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
.num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
.pmx_ops = &meson8_pmx_ops,
.parse_dt = meson8_aobus_parse_dt_extra,
};
static const struct of_device_id meson_gxl_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson-gxl-periphs-pinctrl",
.data = &meson_gxl_periphs_pinctrl_data,
},
{
.compatible = "amlogic,meson-gxl-aobus-pinctrl",
.data = &meson_gxl_aobus_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_gxl_pinctrl_dt_match);
static struct platform_driver meson_gxl_pinctrl_driver = {
.probe = meson_pinctrl_probe,
.driver = {
.name = "meson-gxl-pinctrl",
.of_match_table = meson_gxl_pinctrl_dt_match,
},
};
module_platform_driver(meson_gxl_pinctrl_driver);
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-gxl.c
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Second generation of pinmux driver for Amlogic Meson-AXG SoC.
*
* Copyright (c) 2017 Baylibre SAS.
* Author: Jerome Brunet <[email protected]>
*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
* Author: Xingyu Chen <[email protected]>
*/
/*
* This new generation of pinctrl IP is mainly adopted by the
* Meson-AXG SoC and later series, which use 4-width continuous
* register bit to select the function for each pin.
*
* The value 0 is always selecting the GPIO mode, while other
* values (start from 1) for selecting the function mode.
*/
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
unsigned int pin,
struct meson_pmx_bank **bank)
{
int i;
struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
for (i = 0; i < pmx->num_pmx_banks; i++)
if (pin >= pmx->pmx_banks[i].first &&
pin <= pmx->pmx_banks[i].last) {
*bank = &pmx->pmx_banks[i];
return 0;
}
return -EINVAL;
}
static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
unsigned int pin, unsigned int *reg,
unsigned int *offset)
{
int shift;
shift = pin - bank->first;
*reg = bank->reg + (bank->offset + (shift << 2)) / 32;
*offset = (bank->offset + (shift << 2)) % 32;
return 0;
}
static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
unsigned int pin, unsigned int func)
{
int ret;
int reg;
int offset;
struct meson_pmx_bank *bank;
ret = meson_axg_pmx_get_bank(pc, pin, &bank);
if (ret)
return ret;
meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset);
ret = regmap_update_bits(pc->reg_mux, reg << 2,
0xf << offset, (func & 0xf) << offset);
return ret;
}
static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev,
unsigned int func_num, unsigned int group_num)
{
int i;
int ret;
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
struct meson_pmx_axg_data *pmx_data =
(struct meson_pmx_axg_data *)group->data;
dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
group->name);
for (i = 0; i < group->num_pins; i++) {
ret = meson_axg_pmx_update_function(pc, group->pins[i],
pmx_data->func);
if (ret)
return ret;
}
return 0;
}
static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev,
struct pinctrl_gpio_range *range, unsigned int offset)
{
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
return meson_axg_pmx_update_function(pc, offset, 0);
}
const struct pinmux_ops meson_axg_pmx_ops = {
.set_mux = meson_axg_pmx_set_mux,
.get_functions_count = meson_pmx_get_funcs_count,
.get_function_name = meson_pmx_get_func_name,
.get_function_groups = meson_pmx_get_groups,
.gpio_request_enable = meson_axg_pmx_request_gpio,
};
EXPORT_SYMBOL_GPL(meson_axg_pmx_ops);
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32mp257_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(0, "PA0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "LPTIM1_CH2"),
STM32_FUNCTION(3, "SPI5_RDY"),
STM32_FUNCTION(4, "UART8_CTS"),
STM32_FUNCTION(5, "SAI2_MCLK_B"),
STM32_FUNCTION(6, "UART5_TX"),
STM32_FUNCTION(7, "USART3_TX"),
STM32_FUNCTION(8, "TIM3_ETR"),
STM32_FUNCTION(9, "TIM5_CH2"),
STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(1, "PA1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(3, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_SD_A"),
STM32_FUNCTION(6, "USART1_RTS"),
STM32_FUNCTION(7, "USART6_CK"),
STM32_FUNCTION(8, "TIM4_CH2"),
STM32_FUNCTION(9, "I2C4_SDA"),
STM32_FUNCTION(10, "I2C6_SDA"),
STM32_FUNCTION(12, "LCD_R3"),
STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
STM32_FUNCTION(15, "ETH3_PHY_INTN"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(2, "PA2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "LPTIM2_IN1"),
STM32_FUNCTION(3, "SPI7_MISO"),
STM32_FUNCTION(6, "MDF1_SDI7"),
STM32_FUNCTION(7, "USART1_RX"),
STM32_FUNCTION(9, "I3C1_SDA"),
STM32_FUNCTION(11, "I2C1_SDA"),
STM32_FUNCTION(12, "LCD_B0"),
STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
STM32_FUNCTION(15, "ETH3_RGMII_RX_CTL ETH3_RMII_CRS_DV"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(3, "PA3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "LPTIM2_ETR"),
STM32_FUNCTION(3, "SPI7_MOSI"),
STM32_FUNCTION(6, "MDF1_CKI7"),
STM32_FUNCTION(7, "USART1_TX"),
STM32_FUNCTION(9, "I3C1_SCL"),
STM32_FUNCTION(10, "I2C7_SMBA"),
STM32_FUNCTION(11, "I2C1_SCL"),
STM32_FUNCTION(12, "LCD_B1"),
STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
STM32_FUNCTION(15, "ETH3_RGMII_TX_CTL ETH3_RMII_TX_EN"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(4, "PA4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(7, "USART2_TX"),
STM32_FUNCTION(8, "FDCAN2_TX"),
STM32_FUNCTION(9, "TIM2_CH1"),
STM32_FUNCTION(11, "LCD_R1"),
STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
STM32_FUNCTION(15, "ETH3_PPS_OUT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(5, "PA5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(4, "SPI4_MOSI"),
STM32_FUNCTION(5, "SAI2_MCLK_B"),
STM32_FUNCTION(6, "SAI2_SD_B"),
STM32_FUNCTION(7, "USART2_RTS"),
STM32_FUNCTION(8, "FDCAN2_RX"),
STM32_FUNCTION(9, "TIM2_CH4"),
STM32_FUNCTION(11, "LCD_G0"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
STM32_FUNCTION(15, "ETH3_RGMII_RX_CLK ETH3_RMII_REF_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(6, "PA6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(4, "SPI4_SCK"),
STM32_FUNCTION(5, "SAI2_FS_B"),
STM32_FUNCTION(6, "MDF1_SDI6"),
STM32_FUNCTION(7, "USART2_CK"),
STM32_FUNCTION(8, "TIM13_CH1"),
STM32_FUNCTION(9, "TIM2_ETR"),
STM32_FUNCTION(11, "LCD_G4"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
STM32_FUNCTION(15, "ETH3_RGMII_TXD0 ETH3_RMII_TXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(7, "PA7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(3, "AUDIOCLK"),
STM32_FUNCTION(4, "SPI6_RDY"),
STM32_FUNCTION(5, "PCIE_CLKREQN"),
STM32_FUNCTION(6, "MDF1_CCK0"),
STM32_FUNCTION(7, "USART1_CTS"),
STM32_FUNCTION(8, "TIM4_ETR"),
STM32_FUNCTION(9, "I2C2_SMBA"),
STM32_FUNCTION(10, "I2C6_SMBA"),
STM32_FUNCTION(11, "LCD_B5"),
STM32_FUNCTION(12, "I2C3_SMBA"),
STM32_FUNCTION(13, "I2C4_SMBA"),
STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
STM32_FUNCTION(15, "ETH3_RGMII_TXD1 ETH3_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(8, "PA8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(2, "LPTIM2_CH2"),
STM32_FUNCTION(3, "SPI7_NSS"),
STM32_FUNCTION(5, "SAI1_FS_B"),
STM32_FUNCTION(7, "USART1_CK"),
STM32_FUNCTION(9, "USART2_RX"),
STM32_FUNCTION(10, "I2C5_SCL"),
STM32_FUNCTION(13, "LCD_B2"),
STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(9, "PA9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(4, "SPI4_NSS"),
STM32_FUNCTION(5, "SAI2_SCK_B"),
STM32_FUNCTION(7, "USART2_CTS"),
STM32_FUNCTION(8, "LPTIM5_ETR"),
STM32_FUNCTION(9, "TIM2_CH3"),
STM32_FUNCTION(11, "ETH1_MDC"),
STM32_FUNCTION(13, "LCD_G7"),
STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
STM32_FUNCTION(15, "ETH3_RGMII_RXD0 ETH3_RMII_RXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(10, "PA10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(4, "SPI4_MISO"),
STM32_FUNCTION(5, "SAI2_SD_B"),
STM32_FUNCTION(7, "USART2_RX"),
STM32_FUNCTION(8, "LPTIM5_IN1"),
STM32_FUNCTION(9, "TIM2_CH2"),
STM32_FUNCTION(11, "ETH1_MDIO"),
STM32_FUNCTION(13, "LCD_R6"),
STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
STM32_FUNCTION(15, "ETH3_RGMII_RXD1 ETH3_RMII_RXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(11, "PA11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "SPI8_SCK"),
STM32_FUNCTION(3, "LPTIM2_CH1"),
STM32_FUNCTION(5, "SAI4_SD_B"),
STM32_FUNCTION(6, "MDF1_SDI4"),
STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(12, "PA12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(3, "SPI6_MOSI"),
STM32_FUNCTION(5, "SAI3_FS_A"),
STM32_FUNCTION(8, "TIM4_CH1"),
STM32_FUNCTION(9, "I2C4_SCL"),
STM32_FUNCTION(10, "I2C6_SCL"),
STM32_FUNCTION(11, "ETH1_PHY_INTN"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(13, "PA13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(2, "SPI8_RDY"),
STM32_FUNCTION(3, "I2S3_MCK"),
STM32_FUNCTION(4, "LPTIM2_ETR"),
STM32_FUNCTION(6, "MDF1_CKI3"),
STM32_FUNCTION(7, "USART2_CTS"),
STM32_FUNCTION(10, "I2C7_SMBA"),
STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(14, "PA14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(2, "SPI8_NSS"),
STM32_FUNCTION(3, "LPTIM2_CH2"),
STM32_FUNCTION(5, "SAI4_FS_B"),
STM32_FUNCTION(6, "MDF1_CCK1"),
STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(15, "PA15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "USART2_RX"),
STM32_FUNCTION(10, "I2C7_SDA"),
STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(16, "PB0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "USART1_CK"),
STM32_FUNCTION(8, "TIM16_CH1"),
STM32_FUNCTION(9, "TIM20_CH4N"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(17, "PB1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "TIM16_CH1N"),
STM32_FUNCTION(9, "TIM20_CH3N"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"),
STM32_FUNCTION(13, "FMC_NCE4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(18, "PB2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(6, "MDF1_CKI3"),
STM32_FUNCTION(7, "TIM17_BKIN"),
STM32_FUNCTION(8, "TIM16_BKIN"),
STM32_FUNCTION(9, "TIM20_CH2N"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(19, "PB3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_SDI3"),
STM32_FUNCTION(9, "TIM20_CH3"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"),
STM32_FUNCTION(13, "FMC_NCE3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(20, "PB4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(3, "SPI2_RDY"),
STM32_FUNCTION(4, "UART4_CTS"),
STM32_FUNCTION(5, "SAI4_FS_B"),
STM32_FUNCTION(6, "MDF1_SDI4"),
STM32_FUNCTION(7, "TIM14_CH1"),
STM32_FUNCTION(9, "TIM20_CH2"),
STM32_FUNCTION(10, "I2C2_SDA"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"),
STM32_FUNCTION(14, "I3C2_SDA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(21, "PB5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(3, "I2S2_MCK"),
STM32_FUNCTION(4, "UART4_RTS"),
STM32_FUNCTION(5, "SAI4_SD_B"),
STM32_FUNCTION(6, "MDF1_CKI4"),
STM32_FUNCTION(9, "TIM20_CH1"),
STM32_FUNCTION(10, "I2C2_SCL"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"),
STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
STM32_FUNCTION(14, "I3C2_SCL"),
STM32_FUNCTION(15, "SDMMC3_D123DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(22, "PB6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(4, "UART4_RX"),
STM32_FUNCTION(5, "SAI4_SCK_B"),
STM32_FUNCTION(9, "TIM20_CH1N"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"),
STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
STM32_FUNCTION(15, "SDMMC3_D0DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(23, "PB7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(4, "UART4_TX"),
STM32_FUNCTION(5, "SAI4_MCLK_B"),
STM32_FUNCTION(9, "TIM20_ETR"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"),
STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
STM32_FUNCTION(15, "SDMMC3_CDIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(24, "PB8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(5, "PCIE_CLKREQN"),
STM32_FUNCTION(7, "USART1_TX"),
STM32_FUNCTION(8, "TIM17_CH1"),
STM32_FUNCTION(9, "TIM20_CH4"),
STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"),
STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(25, "PB9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(2, "SPI3_RDY"),
STM32_FUNCTION(7, "USART1_RTS"),
STM32_FUNCTION(8, "FDCAN1_TX"),
STM32_FUNCTION(9, "TIM20_BKIN"),
STM32_FUNCTION(10, "TIM10_CH1"),
STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"),
STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(26, "PB10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "USART1_RX"),
STM32_FUNCTION(8, "TIM17_CH1N"),
STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"),
STM32_FUNCTION(13, "FMC_AD15 FMC_D15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(27, "PB11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "I2S3_MCK"),
STM32_FUNCTION(7, "USART1_CTS"),
STM32_FUNCTION(8, "FDCAN1_RX"),
STM32_FUNCTION(9, "TIM20_BKIN2"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"),
STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"),
STM32_FUNCTION(13, "FMC_AD14 FMC_D14"),
STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(28, "PB12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(6, "UART8_CTS"),
STM32_FUNCTION(8, "TIM13_CH1"),
STM32_FUNCTION(10, "DSI_TE"),
STM32_FUNCTION(11, "SDMMC3_D2"),
STM32_FUNCTION(12, "FMC_NWAIT"),
STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(29, "PB13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(5, "SAI1_SD_B"),
STM32_FUNCTION(6, "UART8_RX"),
STM32_FUNCTION(11, "SDMMC3_CK"),
STM32_FUNCTION(12, "FMC_AD5 FMC_D5"),
STM32_FUNCTION(13, "FMC_AD0 FMC_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(30, "PB14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(6, "MDF1_CKI7"),
STM32_FUNCTION(7, "UART9_RX"),
STM32_FUNCTION(10, "TIM4_CH2"),
STM32_FUNCTION(11, "SDMMC3_D0"),
STM32_FUNCTION(12, "FMC_AD7 FMC_D7"),
STM32_FUNCTION(13, "FMC_AD2 FMC_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(31, "PB15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(3, "SPI5_SCK"),
STM32_FUNCTION(4, "UART8_RTS"),
STM32_FUNCTION(5, "SAI2_SD_B"),
STM32_FUNCTION(6, "UART5_RX"),
STM32_FUNCTION(8, "TIM3_CH2"),
STM32_FUNCTION(9, "TIM5_CH1"),
STM32_FUNCTION(11, "ETH1_PPS_OUT"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(14, "LCD_R4"),
STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(32, "PC0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(2, "LPTIM1_CH1"),
STM32_FUNCTION(4, "SPI6_SCK"),
STM32_FUNCTION(5, "SAI3_MCLK_B"),
STM32_FUNCTION(6, "USART6_TX"),
STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"),
STM32_FUNCTION(14, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(33, "PC1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(7, "USART2_TX"),
STM32_FUNCTION(10, "I2C7_SCL"),
STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(34, "PC2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(2, "SPI8_MOSI"),
STM32_FUNCTION(3, "LPTIM2_IN1"),
STM32_FUNCTION(5, "SAI4_MCLK_B"),
STM32_FUNCTION(6, "MDF1_SDI3"),
STM32_FUNCTION(7, "USART2_RTS"),
STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(35, "PC3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(4, "SPI6_RDY"),
STM32_FUNCTION(7, "USART6_RTS"),
STM32_FUNCTION(8, "FDCAN2_TX"),
STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
STM32_FUNCTION(14, "LCD_G6"),
STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(36, "PC4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(4, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_FS_B"),
STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"),
STM32_FUNCTION(13, "ETH1_RGMII_CLK125"),
STM32_FUNCTION(14, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(37, "PC5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(3, "SPDIFRX1_IN1"),
STM32_FUNCTION(6, "MDF1_SDI1"),
STM32_FUNCTION(9, "TIM8_CH1N"),
STM32_FUNCTION(10, "I2C4_SDA"),
STM32_FUNCTION(11, "ETH2_MDIO"),
STM32_FUNCTION(12, "ETH1_MII_COL"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(14, "ETH1_PPS_OUT"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(38, "PC6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(3, "SPDIFRX1_IN0"),
STM32_FUNCTION(6, "MDF1_CKI1"),
STM32_FUNCTION(9, "TIM8_CH1"),
STM32_FUNCTION(10, "I2C4_SCL"),
STM32_FUNCTION(11, "ETH2_MDC"),
STM32_FUNCTION(12, "ETH1_MII_CRS"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(14, "ETH1_PHY_INTN"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(39, "PC7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(4, "SPI6_MOSI"),
STM32_FUNCTION(5, "SAI3_SD_B"),
STM32_FUNCTION(9, "TIM8_CH2N"),
STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"),
STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
STM32_FUNCTION(14, "LCD_B4"),
STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(40, "PC8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(4, "SPI6_NSS"),
STM32_FUNCTION(5, "SAI3_SCK_B"),
STM32_FUNCTION(7, "USART6_CTS"),
STM32_FUNCTION(9, "TIM8_CH2"),
STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
STM32_FUNCTION(12, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
STM32_FUNCTION(14, "LCD_B3"),
STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(41, "PC9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(5, "SAI2_SCK_A"),
STM32_FUNCTION(8, "TIM13_CH1"),
STM32_FUNCTION(9, "TIM8_CH4N"),
STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
STM32_FUNCTION(12, "USB3DR_OVRCUR"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "LCD_G2"),
STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(42, "PC10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "LPTIM4_ETR"),
STM32_FUNCTION(9, "TIM8_CH4"),
STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
STM32_FUNCTION(12, "USB3DR_VBUSEN"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(14, "LCD_G3"),
STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(43, "PC11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(2, "LPTIM1_CH1"),
STM32_FUNCTION(3, "SPI5_NSS"),
STM32_FUNCTION(5, "SAI2_MCLK_A"),
STM32_FUNCTION(6, "UART5_RTS"),
STM32_FUNCTION(7, "USART3_RTS"),
STM32_FUNCTION(8, "TIM3_CH1"),
STM32_FUNCTION(9, "TIM5_ETR"),
STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "LCD_R2"),
STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(44, "PC12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(2, "LPTIM1_CH2"),
STM32_FUNCTION(4, "I3C3_SCL"),
STM32_FUNCTION(6, "MDF1_CKI2"),
STM32_FUNCTION(9, "TIM8_CH3"),
STM32_FUNCTION(10, "I2C3_SCL"),
STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
STM32_FUNCTION(14, "LCD_G1"),
STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(45, "PC13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(48, "PD0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(2, "HDP0"),
STM32_FUNCTION(3, "SPI7_RDY"),
STM32_FUNCTION(4, "SAI1_D2"),
STM32_FUNCTION(6, "SAI4_FS_A"),
STM32_FUNCTION(7, "UART7_RX"),
STM32_FUNCTION(8, "TIM15_CH2"),
STM32_FUNCTION(10, "SDVSEL1"),
STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"),
STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(49, "PD1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(2, "HDP1"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(4, "SAI1_CK2"),
STM32_FUNCTION(6, "SAI4_SD_A"),
STM32_FUNCTION(7, "UART7_RTS"),
STM32_FUNCTION(8, "TIM15_CH1"),
STM32_FUNCTION(9, "TIM1_BKIN"),
STM32_FUNCTION(10, "FDCAN3_RX"),
STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"),
STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"),
STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(50, "PD2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(2, "HDP2"),
STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(4, "SAI1_CK1"),
STM32_FUNCTION(6, "SAI4_SCK_A"),
STM32_FUNCTION(7, "UART7_CTS"),
STM32_FUNCTION(8, "TIM15_BKIN"),
STM32_FUNCTION(9, "TIM1_ETR"),
STM32_FUNCTION(10, "FDCAN3_TX"),
STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"),
STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"),
STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(51, "PD3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(2, "SAI1_MCLK_A"),
STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(4, "SAI1_D1"),
STM32_FUNCTION(6, "SAI4_MCLK_A"),
STM32_FUNCTION(7, "UART7_TX"),
STM32_FUNCTION(8, "TIM15_CH1N"),
STM32_FUNCTION(9, "TIM1_BKIN2"),
STM32_FUNCTION(10, "SDVSEL2"),
STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"),
STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(52, "PD4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "SPI4_MISO"),
STM32_FUNCTION(3, "HDP3"),
STM32_FUNCTION(4, "SAI1_D3"),
STM32_FUNCTION(5, "SAI1_SD_B"),
STM32_FUNCTION(9, "TIM1_CH4N"),
STM32_FUNCTION(10, "TIM4_CH1"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"),
STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(53, "PD5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "SPI4_NSS"),
STM32_FUNCTION(3, "HDP4"),
STM32_FUNCTION(4, "SAI1_D4"),
STM32_FUNCTION(5, "SAI1_FS_B"),
STM32_FUNCTION(9, "TIM1_CH3N"),
STM32_FUNCTION(10, "TIM4_CH2"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"),
STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(54, "PD6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "SPI4_MOSI"),
STM32_FUNCTION(3, "HDP5"),
STM32_FUNCTION(5, "SAI1_SCK_B"),
STM32_FUNCTION(6, "MDF1_SDI2"),
STM32_FUNCTION(9, "TIM1_CH2N"),
STM32_FUNCTION(10, "TIM4_CH3"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"),
STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(55, "PD7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "SPI4_SCK"),
STM32_FUNCTION(3, "SPI1_RDY"),
STM32_FUNCTION(5, "SAI1_MCLK_B"),
STM32_FUNCTION(6, "MDF1_CKI2"),
STM32_FUNCTION(9, "TIM1_CH1N"),
STM32_FUNCTION(10, "TIM4_CH4"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"),
STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(56, "PD8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "SPI4_RDY"),
STM32_FUNCTION(3, "I2S1_MCK"),
STM32_FUNCTION(4, "SAI1_FS_A"),
STM32_FUNCTION(5, "UART4_CTS"),
STM32_FUNCTION(6, "MDF1_SDI1"),
STM32_FUNCTION(9, "TIM1_CH4"),
STM32_FUNCTION(10, "TIM4_ETR"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"),
STM32_FUNCTION(12, "SDMMC1_D7"),
STM32_FUNCTION(13, "SDMMC1_D123DIR"),
STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(57, "PD9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "HDP6"),
STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(4, "SAI1_SD_A"),
STM32_FUNCTION(5, "UART4_RTS"),
STM32_FUNCTION(6, "MDF1_CKI1"),
STM32_FUNCTION(9, "TIM1_CH3"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"),
STM32_FUNCTION(12, "SDMMC1_D6"),
STM32_FUNCTION(13, "SDMMC1_D0DIR"),
STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(58, "PD10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(2, "HDP7"),
STM32_FUNCTION(4, "SAI1_SCK_A"),
STM32_FUNCTION(5, "UART4_RX"),
STM32_FUNCTION(6, "MDF1_SDI0"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(9, "TIM1_CH2"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"),
STM32_FUNCTION(12, "SDMMC1_D5"),
STM32_FUNCTION(13, "SDMMC1_CDIR"),
STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(59, "PD11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(4, "SAI1_MCLK_A"),
STM32_FUNCTION(5, "UART4_TX"),
STM32_FUNCTION(6, "MDF1_CKI0"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(9, "TIM1_CH1"),
STM32_FUNCTION(10, "SDVSEL1"),
STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"),
STM32_FUNCTION(12, "SDMMC1_D4"),
STM32_FUNCTION(13, "SDMMC1_CKIN"),
STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(60, "PD12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(2, "SPI7_MISO"),
STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(4, "SPDIFRX1_IN2"),
STM32_FUNCTION(6, "UART8_RTS"),
STM32_FUNCTION(10, "TIM4_ETR"),
STM32_FUNCTION(11, "SDMMC3_CMD"),
STM32_FUNCTION(12, "FMC_AD6 FMC_D6"),
STM32_FUNCTION(13, "FMC_AD1 FMC_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(61, "PD13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_SDI7"),
STM32_FUNCTION(7, "UART9_TX"),
STM32_FUNCTION(10, "TIM4_CH4"),
STM32_FUNCTION(11, "SDMMC3_D1"),
STM32_FUNCTION(12, "FMC_AD11 FMC_D11"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(62, "PD14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "I2S1_MCK"),
STM32_FUNCTION(8, "FDCAN1_RX"),
STM32_FUNCTION(9, "TIM11_CH1"),
STM32_FUNCTION(11, "I2C7_SDA"),
STM32_FUNCTION(12, "FMC_AD4 FMC_D4"),
STM32_FUNCTION(13, "SDMMC3_D3"),
STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(63, "PD15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(2, "SPI1_RDY"),
STM32_FUNCTION(6, "DSI_TE"),
STM32_FUNCTION(7, "I2C5_SDA"),
STM32_FUNCTION(8, "FDCAN1_TX"),
STM32_FUNCTION(9, "TIM1_BKIN2"),
STM32_FUNCTION(10, "TIM5_ETR"),
STM32_FUNCTION(11, "I2C7_SCL"),
STM32_FUNCTION(12, "FMC_AD3 FMC_D3"),
STM32_FUNCTION(13, "SDMMC3_CKIN"),
STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(64, "PE0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "LPTIM2_CH1"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(4, "SPI3_RDY"),
STM32_FUNCTION(7, "USART3_CK"),
STM32_FUNCTION(11, "SDMMC1_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(65, "PE1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "LPTIM2_CH2"),
STM32_FUNCTION(3, "I2S1_MCK"),
STM32_FUNCTION(4, "I2S3_MCK"),
STM32_FUNCTION(7, "USART3_RX"),
STM32_FUNCTION(11, "SDMMC1_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(66, "PE2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(2, "LPTIM2_ETR"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(5, "SAI1_SCK_B"),
STM32_FUNCTION(9, "TIM10_CH1"),
STM32_FUNCTION(11, "SDMMC1_CMD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(67, "PE3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SPI1_RDY"),
STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(5, "SAI1_MCLK_B"),
STM32_FUNCTION(7, "USART3_TX"),
STM32_FUNCTION(9, "TIM11_CH1"),
STM32_FUNCTION(11, "SDMMC1_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(68, "PE4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "LPTIM2_IN1"),
STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(5, "SAI1_SD_B"),
STM32_FUNCTION(7, "USART3_CTS"),
STM32_FUNCTION(8, "FDCAN1_TX"),
STM32_FUNCTION(11, "SDMMC1_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(69, "PE5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "LPTIM2_IN2"),
STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(5, "SAI1_FS_B"),
STM32_FUNCTION(7, "USART3_RTS"),
STM32_FUNCTION(8, "FDCAN1_RX"),
STM32_FUNCTION(11, "SDMMC1_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(70, "PE6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(2, "SPI4_RDY"),
STM32_FUNCTION(5, "SPDIFRX1_IN2"),
STM32_FUNCTION(7, "USART1_TX"),
STM32_FUNCTION(9, "TIM1_ETR"),
STM32_FUNCTION(12, "FMC_AD1 FMC_D1"),
STM32_FUNCTION(13, "SDMMC2_D6"),
STM32_FUNCTION(14, "SDMMC2_D0DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(71, "PE7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(4, "SAI4_D4"),
STM32_FUNCTION(5, "SPDIFRX1_IN3"),
STM32_FUNCTION(7, "USART1_RX"),
STM32_FUNCTION(9, "TIM1_CH4N"),
STM32_FUNCTION(11, "TIM14_CH1"),
STM32_FUNCTION(12, "FMC_AD2 FMC_D2"),
STM32_FUNCTION(13, "SDMMC2_D7"),
STM32_FUNCTION(14, "SDMMC2_D123DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(72, "PE8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "SPI4_MOSI"),
STM32_FUNCTION(4, "SAI4_CK1"),
STM32_FUNCTION(5, "SAI4_MCLK_A"),
STM32_FUNCTION(6, "MDF1_CKI0"),
STM32_FUNCTION(9, "TIM1_CH1"),
STM32_FUNCTION(12, "FMC_A17 FMC_ALE"),
STM32_FUNCTION(13, "SDMMC2_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(73, "PE9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "SPI4_MISO"),
STM32_FUNCTION(4, "SAI4_D2"),
STM32_FUNCTION(5, "SAI4_FS_A"),
STM32_FUNCTION(7, "USART1_CK"),
STM32_FUNCTION(9, "TIM1_CH4"),
STM32_FUNCTION(12, "FMC_AD0 FMC_D0"),
STM32_FUNCTION(13, "SDMMC2_D5"),
STM32_FUNCTION(14, "SDMMC2_CDIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(74, "PE10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "SPI4_SCK"),
STM32_FUNCTION(4, "SAI4_D1"),
STM32_FUNCTION(5, "SAI4_SD_A"),
STM32_FUNCTION(7, "USART1_CTS"),
STM32_FUNCTION(9, "TIM1_CH3"),
STM32_FUNCTION(11, "FMC_NE3"),
STM32_FUNCTION(12, "FMC_NCE2"),
STM32_FUNCTION(13, "SDMMC2_D4"),
STM32_FUNCTION(14, "SDMMC2_CKIN"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(75, "PE11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(4, "SAI4_D3"),
STM32_FUNCTION(5, "SAI1_FS_A"),
STM32_FUNCTION(8, "TIM15_CH2"),
STM32_FUNCTION(9, "TIM1_CH3N"),
STM32_FUNCTION(12, "FMC_A16 FMC_CLE"),
STM32_FUNCTION(13, "SDMMC2_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(76, "PE12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "SPI4_NSS"),
STM32_FUNCTION(4, "SAI4_CK2"),
STM32_FUNCTION(5, "SAI4_SCK_A"),
STM32_FUNCTION(6, "MDF1_SDI0"),
STM32_FUNCTION(7, "USART1_RTS"),
STM32_FUNCTION(9, "TIM1_CH2"),
STM32_FUNCTION(11, "FMC_NE2"),
STM32_FUNCTION(12, "FMC_NCE1"),
STM32_FUNCTION(13, "SDMMC2_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(77, "PE13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(3, "SPI7_MISO"),
STM32_FUNCTION(5, "SAI1_SD_A"),
STM32_FUNCTION(8, "TIM15_CH1"),
STM32_FUNCTION(9, "TIM1_CH2N"),
STM32_FUNCTION(12, "FMC_RNB"),
STM32_FUNCTION(13, "SDMMC2_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(78, "PE14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(3, "SPI7_NSS"),
STM32_FUNCTION(5, "SAI1_MCLK_A"),
STM32_FUNCTION(6, "MDF1_CKI6"),
STM32_FUNCTION(8, "TIM15_BKIN"),
STM32_FUNCTION(9, "TIM1_BKIN"),
STM32_FUNCTION(12, "FMC_NWE"),
STM32_FUNCTION(13, "SDMMC2_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(79, "PE15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(3, "SPI7_MOSI"),
STM32_FUNCTION(5, "SAI1_SCK_A"),
STM32_FUNCTION(6, "MDF1_SDI6"),
STM32_FUNCTION(8, "TIM15_CH1N"),
STM32_FUNCTION(9, "TIM1_CH1N"),
STM32_FUNCTION(12, "FMC_NOE"),
STM32_FUNCTION(13, "SDMMC2_CMD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(80, "PF0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "FDCAN2_RX"),
STM32_FUNCTION(9, "TIM12_CH2"),
STM32_FUNCTION(10, "I2C2_SDA"),
STM32_FUNCTION(11, "ETH1_MDC"),
STM32_FUNCTION(12, "ETH2_MII_CRS"),
STM32_FUNCTION(14, "I3C2_SDA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(81, "PF1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(2, "SPI8_MISO"),
STM32_FUNCTION(3, "LPTIM2_IN2"),
STM32_FUNCTION(5, "SAI4_SCK_B"),
STM32_FUNCTION(6, "MDF1_CKI4"),
STM32_FUNCTION(7, "USART2_CK"),
STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(82, "PF2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(3, "SPI3_RDY"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(9, "TIM12_CH1"),
STM32_FUNCTION(10, "I2C2_SCL"),
STM32_FUNCTION(11, "ETH1_MDIO"),
STM32_FUNCTION(12, "ETH2_MII_COL"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(14, "I3C2_SCL"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(83, "PF3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(4, "UART8_RX"),
STM32_FUNCTION(5, "SAI2_SCK_B"),
STM32_FUNCTION(6, "MDF1_CCK0"),
STM32_FUNCTION(8, "TIM3_CH4"),
STM32_FUNCTION(9, "TIM8_BKIN2"),
STM32_FUNCTION(10, "ETH1_CLK"),
STM32_FUNCTION(11, "ETH2_PPS_OUT"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "LCD_R6"),
STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(84, "PF4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(3, "SPI6_NSS"),
STM32_FUNCTION(5, "SAI3_SCK_A"),
STM32_FUNCTION(7, "USART6_RX"),
STM32_FUNCTION(8, "TIM4_CH4"),
STM32_FUNCTION(9, "ETH1_MDC"),
STM32_FUNCTION(10, "ETH2_CLK"),
STM32_FUNCTION(11, "ETH2_PPS_OUT"),
STM32_FUNCTION(12, "ETH1_PPS_OUT"),
STM32_FUNCTION(14, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(85, "PF5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(3, "SPI6_SCK"),
STM32_FUNCTION(5, "SAI3_MCLK_A"),
STM32_FUNCTION(7, "USART6_TX"),
STM32_FUNCTION(8, "TIM4_CH3"),
STM32_FUNCTION(9, "ETH1_MDIO"),
STM32_FUNCTION(10, "ETH1_CLK"),
STM32_FUNCTION(11, "ETH2_PHY_INTN"),
STM32_FUNCTION(12, "ETH1_PHY_INTN"),
STM32_FUNCTION(14, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(86, "PF6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(4, "SAI3_MCLK_B"),
STM32_FUNCTION(7, "USART6_CK"),
STM32_FUNCTION(8, "TIM12_CH1"),
STM32_FUNCTION(10, "I2C3_SMBA"),
STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
STM32_FUNCTION(14, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(87, "PF7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(3, "SPDIFRX1_IN1"),
STM32_FUNCTION(4, "SPI6_SCK"),
STM32_FUNCTION(5, "SAI3_SD_A"),
STM32_FUNCTION(8, "TIM2_ETR"),
STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
STM32_FUNCTION(12, "ETH2_MII_TX_CLK"),
STM32_FUNCTION(14, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(88, "PF8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(4, "SAI3_SCK_B"),
STM32_FUNCTION(7, "USART3_RX"),
STM32_FUNCTION(8, "TIM12_CH2"),
STM32_FUNCTION(10, "ETH1_CLK"),
STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
STM32_FUNCTION(12, "ETH2_MII_RX_ER"),
STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
STM32_FUNCTION(14, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(89, "PF9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(4, "SAI3_SD_B"),
STM32_FUNCTION(5, "SAI2_SD_A"),
STM32_FUNCTION(6, "MDF1_SDI5"),
STM32_FUNCTION(7, "UART8_RTS"),
STM32_FUNCTION(8, "TIM2_CH2"),
STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
STM32_FUNCTION(12, "ETH2_MDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(90, "PF10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(3, "SPI3_RDY"),
STM32_FUNCTION(5, "SAI2_MCLK_A"),
STM32_FUNCTION(6, "MDF1_CKI6"),
STM32_FUNCTION(7, "UART8_TX"),
STM32_FUNCTION(8, "TIM2_CH3"),
STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(91, "PF11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "SPDIFRX1_IN0"),
STM32_FUNCTION(4, "SPI6_RDY"),
STM32_FUNCTION(5, "SAI2_SCK_A"),
STM32_FUNCTION(6, "MDF1_SDI6"),
STM32_FUNCTION(7, "UART8_RX"),
STM32_FUNCTION(8, "TIM2_CH4"),
STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(92, "PF12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SPI5_MISO"),
STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(7, "UART9_RTS"),
STM32_FUNCTION(9, "TIM5_CH1"),
STM32_FUNCTION(14, "LCD_CLK"),
STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(93, "PF13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "HDP0"),
STM32_FUNCTION(3, "AUDIOCLK"),
STM32_FUNCTION(4, "USART6_TX"),
STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_CKI7"),
STM32_FUNCTION(7, "USART3_CTS"),
STM32_FUNCTION(8, "FDCAN3_TX"),
STM32_FUNCTION(9, "TIM3_CH3"),
STM32_FUNCTION(14, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(94, "PF14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "HDP1"),
STM32_FUNCTION(4, "USART6_RX"),
STM32_FUNCTION(6, "MDF1_SDI7"),
STM32_FUNCTION(7, "USART3_RTS"),
STM32_FUNCTION(8, "FDCAN3_RX"),
STM32_FUNCTION(9, "TIM3_CH4"),
STM32_FUNCTION(14, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(95, "PF15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "HDP2"),
STM32_FUNCTION(3, "SPI2_RDY"),
STM32_FUNCTION(4, "USART6_CTS"),
STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "USART3_CK"),
STM32_FUNCTION(8, "TIM2_CH2"),
STM32_FUNCTION(9, "TIM3_ETR"),
STM32_FUNCTION(10, "I2C6_SMBA"),
STM32_FUNCTION(14, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(96, "PG0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(4, "I3C3_SDA"),
STM32_FUNCTION(6, "MDF1_SDI2"),
STM32_FUNCTION(9, "TIM8_CH3N"),
STM32_FUNCTION(10, "I2C3_SDA"),
STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"),
STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
STM32_FUNCTION(14, "LCD_G5"),
STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(97, "PG1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "I2S3_MCK"),
STM32_FUNCTION(4, "I3C3_SCL"),
STM32_FUNCTION(5, "SAI2_SD_A"),
STM32_FUNCTION(6, "UART5_CTS"),
STM32_FUNCTION(7, "USART3_CTS"),
STM32_FUNCTION(9, "TIM5_CH4"),
STM32_FUNCTION(10, "I2C3_SCL"),
STM32_FUNCTION(11, "ETH2_MII_RX_ER"),
STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "LCD_VSYNC"),
STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(98, "PG2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(2, "RTC_REFIN"),
STM32_FUNCTION(3, "I2S3_MCK"),
STM32_FUNCTION(4, "I3C3_SDA"),
STM32_FUNCTION(5, "SAI2_FS_A"),
STM32_FUNCTION(7, "USART3_CK"),
STM32_FUNCTION(9, "TIM5_CH3"),
STM32_FUNCTION(10, "I2C3_SDA"),
STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
STM32_FUNCTION(12, "ETH2_RGMII_CLK125"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(99, "PG3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(3, "SPI5_MOSI"),
STM32_FUNCTION(4, "UART8_TX"),
STM32_FUNCTION(5, "SAI2_FS_B"),
STM32_FUNCTION(8, "TIM3_CH3"),
STM32_FUNCTION(9, "TIM8_ETR"),
STM32_FUNCTION(10, "ETH2_CLK"),
STM32_FUNCTION(11, "ETH2_PHY_INTN"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(14, "LCD_R5"),
STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(100, "PG4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(3, "SPI5_MISO"),
STM32_FUNCTION(4, "SAI3_FS_B"),
STM32_FUNCTION(8, "LPTIM4_IN1"),
STM32_FUNCTION(9, "TIM8_BKIN"),
STM32_FUNCTION(11, "ETH2_PPS_OUT"),
STM32_FUNCTION(12, "ETH2_MDC"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "LCD_R7"),
STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(101, "PG5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "HDP3"),
STM32_FUNCTION(4, "USART6_RTS"),
STM32_FUNCTION(8, "TIM2_CH3"),
STM32_FUNCTION(10, "I2C6_SDA"),
STM32_FUNCTION(14, "LCD_R5"),
STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(102, "PG6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "HDP4"),
STM32_FUNCTION(3, "SPI5_SCK"),
STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(8, "TIM2_CH4"),
STM32_FUNCTION(10, "I2C6_SCL"),
STM32_FUNCTION(14, "LCD_R6"),
STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(103, "PG7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "HDP5"),
STM32_FUNCTION(3, "SPI5_NSS"),
STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "UART9_CTS"),
STM32_FUNCTION(9, "TIM5_ETR"),
STM32_FUNCTION(14, "LCD_R7"),
STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(104, "PG8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(2, "HDP6"),
STM32_FUNCTION(3, "SPI5_RDY"),
STM32_FUNCTION(4, "SPI1_RDY"),
STM32_FUNCTION(5, "USART6_CK"),
STM32_FUNCTION(6, "UART5_RTS"),
STM32_FUNCTION(7, "UART9_TX"),
STM32_FUNCTION(9, "TIM5_CH3"),
STM32_FUNCTION(14, "LCD_G2"),
STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(105, "PG9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(6, "UART5_TX"),
STM32_FUNCTION(9, "TIM5_CH4"),
STM32_FUNCTION(14, "LCD_G3"),
STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(106, "PG10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(1, "TRACED8"),
STM32_FUNCTION(2, "HDP0"),
STM32_FUNCTION(6, "UART5_RX"),
STM32_FUNCTION(9, "TIM8_CH4N"),
STM32_FUNCTION(14, "LCD_G4"),
STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(107, "PG11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(1, "TRACED9"),
STM32_FUNCTION(2, "HDP1"),
STM32_FUNCTION(3, "SPI7_MOSI"),
STM32_FUNCTION(8, "FDCAN1_TX"),
STM32_FUNCTION(9, "TIM8_CH4"),
STM32_FUNCTION(14, "LCD_G5"),
STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(108, "PG12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(1, "TRACED10"),
STM32_FUNCTION(2, "HDP2"),
STM32_FUNCTION(3, "SPI7_MISO"),
STM32_FUNCTION(8, "FDCAN1_RX"),
STM32_FUNCTION(9, "TIM8_CH1N"),
STM32_FUNCTION(14, "LCD_G6"),
STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(109, "PG13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED11"),
STM32_FUNCTION(2, "HDP3"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(6, "MDF1_CKI6"),
STM32_FUNCTION(9, "TIM8_CH2N"),
STM32_FUNCTION(10, "I2C1_SCL"),
STM32_FUNCTION(11, "I3C1_SCL"),
STM32_FUNCTION(14, "LCD_G7"),
STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(110, "PG14"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED12"),
STM32_FUNCTION(2, "HDP4"),
STM32_FUNCTION(3, "SPI7_RDY"),
STM32_FUNCTION(6, "MDF1_CKI5"),
STM32_FUNCTION(7, "USART1_TX"),
STM32_FUNCTION(9, "TIM8_BKIN2"),
STM32_FUNCTION(14, "LCD_B1"),
STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(111, "PG15"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(1, "TRACED13"),
STM32_FUNCTION(2, "HDP5"),
STM32_FUNCTION(4, "LPTIM1_CH2"),
STM32_FUNCTION(6, "MDF1_SDI5"),
STM32_FUNCTION(7, "USART1_RX"),
STM32_FUNCTION(9, "TIM8_ETR"),
STM32_FUNCTION(14, "LCD_B2"),
STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(114, "PH2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(2, "LPTIM2_CH1"),
STM32_FUNCTION(3, "SPI7_RDY"),
STM32_FUNCTION(4, "SPDIFRX1_IN3"),
STM32_FUNCTION(5, "SAI1_SCK_B"),
STM32_FUNCTION(6, "I3C3_SDA"),
STM32_FUNCTION(8, "TIM16_CH1"),
STM32_FUNCTION(9, "I2C5_SDA"),
STM32_FUNCTION(10, "I2C3_SDA"),
STM32_FUNCTION(15, "ETH3_RGMII_GTX_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(115, "PH3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "UART7_RX"),
STM32_FUNCTION(8, "TIM17_CH1N"),
STM32_FUNCTION(10, "TIM5_CH3"),
STM32_FUNCTION(11, "I2C7_SCL"),
STM32_FUNCTION(15, "ETH3_RGMII_TXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(116, "PH4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(7, "UART7_TX"),
STM32_FUNCTION(8, "TIM17_BKIN"),
STM32_FUNCTION(10, "TIM5_CH2"),
STM32_FUNCTION(11, "LCD_R0"),
STM32_FUNCTION(12, "USB3DR_OVRCUR"),
STM32_FUNCTION(13, "USBH_HS_OVRCUR"),
STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"),
STM32_FUNCTION(15, "ETH3_PPS_OUT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(117, "PH5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "SAI2_FS_A"),
STM32_FUNCTION(7, "UART8_CTS"),
STM32_FUNCTION(8, "TIM2_CH1"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(11, "LCD_G1"),
STM32_FUNCTION(12, "USB3DR_VBUSEN"),
STM32_FUNCTION(13, "USBH_HS_VBUSEN"),
STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(118, "PH6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(2, "LPTIM2_IN2"),
STM32_FUNCTION(5, "SAI1_MCLK_B"),
STM32_FUNCTION(6, "I3C3_SCL"),
STM32_FUNCTION(8, "TIM16_CH1N"),
STM32_FUNCTION(9, "I2C5_SCL"),
STM32_FUNCTION(10, "I2C3_SCL"),
STM32_FUNCTION(11, "I2C1_SMBA"),
STM32_FUNCTION(15, "ETH3_RGMII_TXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(119, "PH7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(5, "UART4_TX"),
STM32_FUNCTION(7, "UART7_RTS"),
STM32_FUNCTION(8, "TIM17_CH1"),
STM32_FUNCTION(10, "TIM5_CH4"),
STM32_FUNCTION(11, "I2C7_SDA"),
STM32_FUNCTION(15, "ETH3_RGMII_RXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(120, "PH8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(4, "SPDIFRX1_IN3"),
STM32_FUNCTION(5, "UART4_RX"),
STM32_FUNCTION(7, "UART7_CTS"),
STM32_FUNCTION(10, "TIM5_CH1"),
STM32_FUNCTION(11, "I2C3_SMBA"),
STM32_FUNCTION(12, "I2C5_SMBA"),
STM32_FUNCTION(15, "ETH3_RGMII_RXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(121, "PH9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(4, "SPI6_NSS"),
STM32_FUNCTION(5, "SAI3_MCLK_A"),
STM32_FUNCTION(7, "USART6_RX"),
STM32_FUNCTION(8, "TIM15_CH1N"),
STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(122, "PH10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(4, "SPI6_MOSI"),
STM32_FUNCTION(5, "SAI3_SCK_A"),
STM32_FUNCTION(8, "TIM15_CH1"),
STM32_FUNCTION(10, "ETH2_MDC"),
STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(123, "PH11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(4, "SPI6_MISO"),
STM32_FUNCTION(5, "SAI3_FS_A"),
STM32_FUNCTION(8, "TIM15_CH2"),
STM32_FUNCTION(10, "ETH2_MDIO"),
STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(124, "PH12"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(4, "SPI6_MISO"),
STM32_FUNCTION(9, "TIM10_CH1"),
STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(125, "PH13"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(4, "SPI6_MOSI"),
STM32_FUNCTION(8, "TIM15_BKIN"),
STM32_FUNCTION(9, "TIM11_CH1"),
STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(128, "PI0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(1, "TRACED14"),
STM32_FUNCTION(2, "HDP6"),
STM32_FUNCTION(4, "LPTIM1_IN1"),
STM32_FUNCTION(5, "SAI4_MCLK_B"),
STM32_FUNCTION(7, "USART1_CK"),
STM32_FUNCTION(9, "TIM8_BKIN"),
STM32_FUNCTION(14, "LCD_B3"),
STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(129, "PI1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(1, "TRACED15"),
STM32_FUNCTION(2, "HDP7"),
STM32_FUNCTION(3, "SPI7_NSS"),
STM32_FUNCTION(6, "MDF1_SDI6"),
STM32_FUNCTION(9, "TIM8_CH3N"),
STM32_FUNCTION(10, "I2C1_SDA"),
STM32_FUNCTION(11, "I3C1_SDA"),
STM32_FUNCTION(14, "LCD_B4"),
STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(130, "PI2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(5, "SAI4_SCK_B"),
STM32_FUNCTION(7, "USART1_RTS"),
STM32_FUNCTION(9, "TIM8_CH1"),
STM32_FUNCTION(14, "LCD_B5"),
STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(131, "PI3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(5, "SAI4_SD_B"),
STM32_FUNCTION(7, "USART1_CTS"),
STM32_FUNCTION(9, "TIM8_CH2"),
STM32_FUNCTION(14, "LCD_B6"),
STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(132, "PI4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "LPTIM1_CH1"),
STM32_FUNCTION(5, "SAI4_FS_B"),
STM32_FUNCTION(9, "TIM8_CH3"),
STM32_FUNCTION(14, "LCD_B7"),
STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(133, "PI5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(3, "SPI5_MOSI"),
STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(6, "UART5_CTS"),
STM32_FUNCTION(7, "UART9_RX"),
STM32_FUNCTION(9, "TIM5_CH2"),
STM32_FUNCTION(14, "LCD_DE"),
STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(134, "PI6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(7, "USART3_TX"),
STM32_FUNCTION(8, "TIM2_ETR"),
STM32_FUNCTION(9, "TIM3_CH1"),
STM32_FUNCTION(14, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(135, "PI7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(7, "USART3_RX"),
STM32_FUNCTION(8, "TIM2_CH1"),
STM32_FUNCTION(9, "TIM3_CH2"),
STM32_FUNCTION(14, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(136, "PI8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(137, "PI9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(2, "SPI7_MOSI"),
STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(5, "FDCAN2_TX"),
STM32_FUNCTION(7, "UART9_CTS"),
STM32_FUNCTION(9, "TIM16_BKIN"),
STM32_FUNCTION(10, "SDVSEL2"),
STM32_FUNCTION(11, "FMC_NWAIT"),
STM32_FUNCTION(13, "DSI_TE"),
STM32_FUNCTION(14, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(138, "PI10"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(2, "SAI1_SCK_A"),
STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(4, "SPDIFRX1_IN0"),
STM32_FUNCTION(5, "FDCAN2_RX"),
STM32_FUNCTION(6, "MDF1_CCK0"),
STM32_FUNCTION(9, "TIM4_CH1"),
STM32_FUNCTION(10, "SDVSEL1"),
STM32_FUNCTION(13, "FMC_AD12 FMC_D12"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(139, "PI11"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(3, "I2S2_MCK"),
STM32_FUNCTION(6, "UART8_TX"),
STM32_FUNCTION(7, "UART9_RTS"),
STM32_FUNCTION(10, "TIM4_CH3"),
STM32_FUNCTION(11, "SDMMC3_D3"),
STM32_FUNCTION(12, "FMC_AD15 FMC_D15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(140, "PI12"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(3, "SPI4_NSS"),
STM32_FUNCTION(8, "FDCAN3_RX"),
STM32_FUNCTION(9, "TIM11_CH1"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(14, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(141, "PI13"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(3, "SPI4_MOSI"),
STM32_FUNCTION(5, "FDCAN2_RX"),
STM32_FUNCTION(9, "TIM10_CH1"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(14, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(142, "PI14"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(6, "MDF1_SDI1"),
STM32_FUNCTION(8, "TIM20_CH3"),
STM32_FUNCTION(9, "TIM1_CH3N"),
STM32_FUNCTION(11, "FMC_NWAIT"),
STM32_FUNCTION(13, "FMC_AD10 FMC_D10"),
STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(143, "PI15"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(3, "I2S2_MCK"),
STM32_FUNCTION(4, "UART4_RX"),
STM32_FUNCTION(6, "MDF1_CKI2"),
STM32_FUNCTION(8, "TIM20_BKIN2"),
STM32_FUNCTION(9, "TIM1_BKIN2"),
STM32_FUNCTION(10, "SDVSEL1"),
STM32_FUNCTION(11, "SDMMC3_CDIR"),
STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(144, "PJ0"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(3, "SPI5_MOSI"),
STM32_FUNCTION(5, "PCIE_CLKREQN"),
STM32_FUNCTION(6, "SAI4_D2"),
STM32_FUNCTION(7, "USART6_CTS"),
STM32_FUNCTION(10, "USBH_HS_VBUSEN"),
STM32_FUNCTION(12, "ETH2_PTP_AUX_TS"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(14, "ETH3_PPS_OUT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(145, "PJ1"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(7, "USART6_RX"),
STM32_FUNCTION(9, "TIM8_CH1N"),
STM32_FUNCTION(10, "I2C1_SCL"),
STM32_FUNCTION(11, "I3C1_SCL"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(146, "PJ2"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(5, "SAI2_SD_B"),
STM32_FUNCTION(7, "UART9_RTS"),
STM32_FUNCTION(9, "TIM8_CH4N"),
STM32_FUNCTION(10, "USBH_HS_OVRCUR"),
STM32_FUNCTION(13, "FMC_A14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(147, "PJ3"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(3, "SPI5_NSS"),
STM32_FUNCTION(4, "SAI2_FS_A"),
STM32_FUNCTION(6, "SAI4_D1"),
STM32_FUNCTION(7, "USART6_RTS"),
STM32_FUNCTION(9, "TIM8_CH3"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(148, "PJ4"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(4, "SAI2_FS_B"),
STM32_FUNCTION(6, "MDF1_CCK1"),
STM32_FUNCTION(7, "USART6_CK"),
STM32_FUNCTION(9, "TIM8_CH4"),
STM32_FUNCTION(10, "I2C2_SMBA"),
STM32_FUNCTION(11, "I2C5_SMBA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(149, "PJ5"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(3, "SPI5_MISO"),
STM32_FUNCTION(4, "SAI2_SCK_B"),
STM32_FUNCTION(6, "SAI4_CK1"),
STM32_FUNCTION(7, "USART6_TX"),
STM32_FUNCTION(9, "TIM8_CH1"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(150, "PJ6"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(3, "SPI7_MOSI"),
STM32_FUNCTION(5, "SAI4_SD_A"),
STM32_FUNCTION(7, "USART2_CK"),
STM32_FUNCTION(8, "TIM20_CH1N"),
STM32_FUNCTION(9, "TIM1_CH1"),
STM32_FUNCTION(10, "I2C6_SMBA"),
STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(151, "PJ7"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(3, "SPI5_MISO"),
STM32_FUNCTION(5, "SAI2_MCLK_B"),
STM32_FUNCTION(6, "SAI4_D3"),
STM32_FUNCTION(7, "USART6_CK"),
STM32_FUNCTION(9, "TIM8_CH2N"),
STM32_FUNCTION(10, "I2C1_SMBA"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(152, "PJ8"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(3, "SPI5_SCK"),
STM32_FUNCTION(6, "SAI4_CK2"),
STM32_FUNCTION(7, "USART6_RX"),
STM32_FUNCTION(9, "TIM8_CH2"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(153, "PJ9"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(3, "SPI4_RDY"),
STM32_FUNCTION(8, "TIM12_CH1"),
STM32_FUNCTION(9, "TIM8_BKIN"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(154, "PJ10"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(8, "TIM12_CH2"),
STM32_FUNCTION(9, "TIM8_ETR"),
STM32_FUNCTION(10, "I2C1_SDA"),
STM32_FUNCTION(11, "I3C1_SDA"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(155, "PJ11"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(3, "SPI5_RDY"),
STM32_FUNCTION(4, "SAI2_SCK_A"),
STM32_FUNCTION(6, "SAI4_D4"),
STM32_FUNCTION(7, "UART9_CTS"),
STM32_FUNCTION(9, "TIM8_CH3N"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(156, "PJ12"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(4, "SAI2_SD_A"),
STM32_FUNCTION(7, "UART9_RX"),
STM32_FUNCTION(8, "FDCAN1_TX"),
STM32_FUNCTION(9, "TIM8_BKIN2"),
STM32_FUNCTION(10, "I2C2_SCL"),
STM32_FUNCTION(11, "I3C2_SCL"),
STM32_FUNCTION(13, "FMC_A15"),
STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(157, "PJ13"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(4, "SAI2_MCLK_A"),
STM32_FUNCTION(7, "UART9_TX"),
STM32_FUNCTION(8, "FDCAN1_RX"),
STM32_FUNCTION(9, "TIM10_CH1"),
STM32_FUNCTION(10, "I2C2_SDA"),
STM32_FUNCTION(11, "I3C2_SDA"),
STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(158, "PJ14"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(3, "SPI4_SCK"),
STM32_FUNCTION(8, "FDCAN3_TX"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(14, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(159, "PJ15"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(2, "HDP7"),
STM32_FUNCTION(3, "SPI4_MISO"),
STM32_FUNCTION(5, "FDCAN2_TX"),
STM32_FUNCTION(9, "TIM11_CH1"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(14, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(160, "PK0"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(4, "SPDIFRX1_IN2"),
STM32_FUNCTION(6, "MDF1_CCK0"),
STM32_FUNCTION(8, "TIM20_ETR"),
STM32_FUNCTION(9, "TIM1_ETR"),
STM32_FUNCTION(11, "SDMMC3_D123DIR"),
STM32_FUNCTION(13, "FMC_AD11 FMC_D11"),
STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(161, "PK1"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(6, "MDF1_SDI2"),
STM32_FUNCTION(8, "TIM20_BKIN"),
STM32_FUNCTION(9, "TIM1_BKIN"),
STM32_FUNCTION(10, "SDVSEL2"),
STM32_FUNCTION(11, "SDMMC3_D0DIR"),
STM32_FUNCTION(13, "FMC_AD13 FMC_D13"),
STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(162, "PK2"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(3, "SPI7_NSS"),
STM32_FUNCTION(5, "SAI4_SCK_A"),
STM32_FUNCTION(7, "USART1_RTS"),
STM32_FUNCTION(8, "TIM20_CH2"),
STM32_FUNCTION(9, "TIM1_CH2N"),
STM32_FUNCTION(10, "I2C6_SDA"),
STM32_FUNCTION(13, "FMC_NCE3"),
STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(163, "PK3"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(3, "SPI7_RDY"),
STM32_FUNCTION(6, "MDF1_CKI1"),
STM32_FUNCTION(8, "TIM20_CH3N"),
STM32_FUNCTION(9, "TIM1_CH3"),
STM32_FUNCTION(13, "FMC_AD8 FMC_D8"),
STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"),
STM32_FUNCTION(15, "FMC_NCE4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(164, "PK4"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(3, "SPI7_MISO"),
STM32_FUNCTION(4, "UART4_TX"),
STM32_FUNCTION(5, "SAI4_FS_A"),
STM32_FUNCTION(8, "TIM20_CH1"),
STM32_FUNCTION(9, "TIM1_CH1N"),
STM32_FUNCTION(11, "SDMMC3_CKIN"),
STM32_FUNCTION(13, "FMC_AD9 FMC_D9"),
STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(165, "PK5"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(3, "SPI2_RDY"),
STM32_FUNCTION(6, "MDF1_CKI0"),
STM32_FUNCTION(7, "USART1_TX"),
STM32_FUNCTION(8, "TIM20_CH4N"),
STM32_FUNCTION(9, "TIM1_CH4"),
STM32_FUNCTION(11, "I2C5_SCL"),
STM32_FUNCTION(13, "FMC_AD5 FMC_D5"),
STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(166, "PK6"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(3, "SPI7_SCK"),
STM32_FUNCTION(5, "SAI4_MCLK_A"),
STM32_FUNCTION(7, "USART1_CTS"),
STM32_FUNCTION(8, "TIM20_CH2N"),
STM32_FUNCTION(9, "TIM1_CH2"),
STM32_FUNCTION(10, "I2C6_SCL"),
STM32_FUNCTION(12, "FMC_AD14 FMC_D14"),
STM32_FUNCTION(13, "FMC_AD7 FMC_D7"),
STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(167, "PK7"),
STM32MP_PKG_AI,
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(6, "MDF1_SDI0"),
STM32_FUNCTION(7, "USART1_RX"),
STM32_FUNCTION(8, "TIM20_CH4"),
STM32_FUNCTION(9, "TIM1_CH4N"),
STM32_FUNCTION(11, "I2C5_SDA"),
STM32_FUNCTION(12, "FMC_NCE4"),
STM32_FUNCTION(13, "FMC_AD6 FMC_D6"),
STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static const struct stm32_desc_pin stm32mp257_z_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(400, "PZ0"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ0"),
STM32_FUNCTION(3, "LPTIM3_IN1"),
STM32_FUNCTION(4, "SPI8_MOSI"),
STM32_FUNCTION(5, "TIM8_CH1"),
STM32_FUNCTION(7, "LPUART1_TX"),
STM32_FUNCTION(8, "LPTIM5_OUT"),
STM32_FUNCTION(9, "I2C8_SDA"),
STM32_FUNCTION(11, "LPTIM3_CH2"),
STM32_FUNCTION(12, "I3C4_SDA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(401, "PZ1"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ1"),
STM32_FUNCTION(3, "LPTIM3_CH1"),
STM32_FUNCTION(4, "SPI8_MISO"),
STM32_FUNCTION(5, "TIM8_CH2"),
STM32_FUNCTION(7, "LPUART1_RX"),
STM32_FUNCTION(8, "LPTIM5_ETR"),
STM32_FUNCTION(9, "I2C8_SCL"),
STM32_FUNCTION(10, "I2C8_SMBA"),
STM32_FUNCTION(12, "I3C4_SCL"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(402, "PZ2"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ2"),
STM32_FUNCTION(3, "LPTIM3_CH1"),
STM32_FUNCTION(4, "SPI8_SCK"),
STM32_FUNCTION(6, "ADF1_CCK0"),
STM32_FUNCTION(7, "LPUART1_RTS"),
STM32_FUNCTION(8, "LPTIM4_ETR"),
STM32_FUNCTION(9, "I2C8_SCL"),
STM32_FUNCTION(12, "I3C4_SCL"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(403, "PZ3"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ3"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
STM32_FUNCTION(3, "LPTIM3_ETR"),
STM32_FUNCTION(4, "SPI8_NSS"),
STM32_FUNCTION(5, "MDF1_SDI5"),
STM32_FUNCTION(6, "ADF1_SDI0"),
STM32_FUNCTION(7, "LPUART1_CTS"),
STM32_FUNCTION(8, "LPTIM4_IN1"),
STM32_FUNCTION(9, "I2C8_SDA"),
STM32_FUNCTION(11, "LPTIM4_CH2"),
STM32_FUNCTION(12, "I3C4_SDA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(404, "PZ4"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ4"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
STM32_FUNCTION(3, "MCO2"),
STM32_FUNCTION(4, "SPI8_RDY"),
STM32_FUNCTION(5, "MDF1_CCK1"),
STM32_FUNCTION(6, "ADF1_CCK1"),
STM32_FUNCTION(7, "LPUART1_RX"),
STM32_FUNCTION(8, "LPTIM4_CH1"),
STM32_FUNCTION(9, "I2C8_SCL"),
STM32_FUNCTION(12, "I3C4_SCL"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(405, "PZ5"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ5"),
STM32_FUNCTION(2, "MCO1"),
STM32_FUNCTION(3, "LPTIM3_ETR"),
STM32_FUNCTION(4, "SPI8_SCK"),
STM32_FUNCTION(6, "ADF1_CCK0"),
STM32_FUNCTION(7, "LPUART1_RTS"),
STM32_FUNCTION(8, "LPTIM5_IN1"),
STM32_FUNCTION(11, "LPTIM4_CH2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(406, "PZ6"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ6"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "DBTRGO"),
STM32_FUNCTION(4, "SPI8_NSS"),
STM32_FUNCTION(5, "TIM8_CH3"),
STM32_FUNCTION(6, "ADF1_SDI0"),
STM32_FUNCTION(7, "LPUART1_CTS"),
STM32_FUNCTION(8, "LPTIM5_OUT"),
STM32_FUNCTION(11, "LPTIM4_CH2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(407, "PZ7"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ7"),
STM32_FUNCTION(4, "SPI8_MOSI"),
STM32_FUNCTION(5, "MDF1_CCK1"),
STM32_FUNCTION(6, "ADF1_CCK1"),
STM32_FUNCTION(7, "LPUART1_TX"),
STM32_FUNCTION(8, "LPTIM5_IN1"),
STM32_FUNCTION(11, "LPTIM3_CH2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(408, "PZ8"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ8"),
STM32_FUNCTION(3, "LPTIM3_IN1"),
STM32_FUNCTION(4, "SPI8_MISO"),
STM32_FUNCTION(5, "MDF1_SDI5"),
STM32_FUNCTION(6, "ADF1_SDI0"),
STM32_FUNCTION(7, "LPUART1_RX"),
STM32_FUNCTION(8, "LPTIM4_CH1"),
STM32_FUNCTION(9, "I2C8_SMBA"),
STM32_FUNCTION(10, "LPTIM5_ETR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(409, "PZ9"),
STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL,
STM32_FUNCTION(0, "GPIOZ9"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(4, "SPI8_RDY"),
STM32_FUNCTION(5, "MDF1_CKI5"),
STM32_FUNCTION(7, "LPUART1_TX"),
STM32_FUNCTION(8, "LPTIM4_ETR"),
STM32_FUNCTION(9, "I2C8_SDA"),
STM32_FUNCTION(11, "LPTIM3_CH2"),
STM32_FUNCTION(12, "I3C4_SDA"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32mp257_match_data = {
.pins = stm32mp257_pins,
.npins = ARRAY_SIZE(stm32mp257_pins),
};
static struct stm32_pinctrl_match_data stm32mp257_z_match_data = {
.pins = stm32mp257_z_pins,
.npins = ARRAY_SIZE(stm32mp257_z_pins),
};
static const struct of_device_id stm32mp257_pctrl_match[] = {
{
.compatible = "st,stm32mp257-pinctrl",
.data = &stm32mp257_match_data,
},
{
.compatible = "st,stm32mp257-z-pinctrl",
.data = &stm32mp257_z_match_data,
},
{ }
};
static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume)
};
static struct platform_driver stm32mp257_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32mp257-pinctrl",
.of_match_table = stm32mp257_pctrl_match,
.pm = &stm32_pinctrl_dev_pm_ops,
},
};
static int __init stm32mp257_pinctrl_init(void)
{
return platform_driver_register(&stm32mp257_pinctrl_driver);
}
arch_initcall(stm32mp257_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32mp257.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32mp157_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(0, "PA0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "SDMMC2_CMD"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(1, "PA1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(1, "ETH_CLK"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(4, "LPTIM3_OUT"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(8, "USART2_RTS USART2_DE"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH1_GMII_RX_CLK ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(2, "PA2"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "LPTIM4_OUT"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(9, "SAI2_SCK_B"),
STM32_FUNCTION(11, "SDMMC2_D0DIR"),
STM32_FUNCTION(12, "ETH1_MDIO"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(3, "PA3"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "LPTIM5_OUT"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(10, "LCD_B2"),
STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(4, "PA4"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(1, "HDP0"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(5, "SAI4_D2"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(9, "SPI6_NSS"),
STM32_FUNCTION(13, "SAI4_FS_A"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(5, "PA5"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(5, "SAI4_CK1"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(13, "SAI4_MCLK_A"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(6, "PA6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(5, "SAI4_CK2"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(12, "MDIOS_MDC"),
STM32_FUNCTION(13, "SAI4_SCK_A"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(7, "PA7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(5, "SAI4_D1"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_CLK"),
STM32_FUNCTION(12, "ETH1_GMII_RX_DV ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
STM32_FUNCTION(13, "SAI4_SD_A"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(8, "PA8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(9, "SDMMC2_CKIN"),
STM32_FUNCTION(10, "SDMMC2_D4"),
STM32_FUNCTION(11, "OTG_FS_SOF OTG_HS_SOF"),
STM32_FUNCTION(13, "SAI4_SD_B"),
STM32_FUNCTION(14, "UART7_RX"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(9, "PA9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(9, "SDMMC2_CDIR"),
STM32_FUNCTION(11, "SDMMC2_D5"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(10, "PA10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(12, "MDIOS_MDIO"),
STM32_FUNCTION(13, "SAI4_FS_B"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(11, "PA11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "UART4_RX"),
STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(12, "PA12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(7, "UART4_TX"),
STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(13, "PA13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(2, "DBTRGI"),
STM32_FUNCTION(3, "MCO1"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(14, "PA14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(2, "DBTRGI"),
STM32_FUNCTION(3, "MCO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(15, "PA15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "SAI4_D2"),
STM32_FUNCTION(4, "SDMMC1_CDIR"),
STM32_FUNCTION(5, "CEC"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "SPI6_NSS"),
STM32_FUNCTION(9, "UART4_RTS UART4_DE"),
STM32_FUNCTION(10, "SDMMC2_D5"),
STM32_FUNCTION(11, "SDMMC2_CDIR"),
STM32_FUNCTION(12, "SDMMC1_D5"),
STM32_FUNCTION(13, "SAI4_FS_A"),
STM32_FUNCTION(14, "UART7_TX"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(16, "PB0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(7, "DFSDM1_CKOUT"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(12, "ETH1_GMII_RXD2 ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(17, "PB1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(7, "DFSDM1_DATIN1"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(12, "ETH1_GMII_RXD3 ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(18, "PB2"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(4, "DFSDM1_CKIN1"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(19, "PB3"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "TRACED9"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(5, "SAI4_CK1"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(10, "SDMMC2_D2"),
STM32_FUNCTION(13, "SAI4_MCLK_A"),
STM32_FUNCTION(14, "UART7_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(20, "PB4"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "TRACED8"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(5, "SAI4_CK2"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(10, "SDMMC2_D3"),
STM32_FUNCTION(13, "SAI4_SCK_A"),
STM32_FUNCTION(14, "UART7_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(21, "PB5"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(1, "ETH_CLK"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "SAI4_D1"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "FDCAN2_RX"),
STM32_FUNCTION(11, "SAI4_SD_A"),
STM32_FUNCTION(12, "ETH1_PPS_OUT"),
STM32_FUNCTION(13, "UART5_RX"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(22, "PB6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(6, "CEC"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "FDCAN2_TX"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "DFSDM1_DATIN5"),
STM32_FUNCTION(13, "UART5_TX"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(23, "PB7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(11, "SDMMC2_D1"),
STM32_FUNCTION(12, "DFSDM1_CKIN5"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(24, "PB8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(1, "HDP6"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "DFSDM1_CKIN7"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(6, "SDMMC1_CKIN"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(8, "SDMMC2_CKIN"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(11, "SDMMC2_D4"),
STM32_FUNCTION(12, "ETH1_GMII_TXD3 ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
STM32_FUNCTION(13, "SDMMC1_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(25, "PB9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(1, "HDP7"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "DFSDM1_DATIN7"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "SDMMC2_CDIR"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(11, "SDMMC2_D5"),
STM32_FUNCTION(12, "SDMMC1_CDIR"),
STM32_FUNCTION(13, "SDMMC1_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(26, "PB10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(4, "LPTIM2_IN1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM1_DATIN7"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "ETH1_GMII_RX_ER ETH1_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(27, "PB11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(4, "LPTIM2_ETR"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(7, "DFSDM1_CKIN7"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(12, "ETH1_GMII_TX_EN ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(28, "PB12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "I2C6_SMBA"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "DFSDM1_DATIN1"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "USART3_RX"),
STM32_FUNCTION(10, "FDCAN2_RX"),
STM32_FUNCTION(12, "ETH1_GMII_TXD0 ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
STM32_FUNCTION(15, "UART5_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(29, "PB13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(5, "LPTIM2_OUT"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM1_CKIN1"),
STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
STM32_FUNCTION(10, "FDCAN2_TX"),
STM32_FUNCTION(12, "ETH1_GMII_TXD1 ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
STM32_FUNCTION(15, "UART5_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(30, "PB14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM12_CH1"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "DFSDM1_DATIN2"),
STM32_FUNCTION(8, "USART3_RTS USART3_DE"),
STM32_FUNCTION(10, "SDMMC2_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(31, "PB15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM12_CH2"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(7, "DFSDM1_CKIN2"),
STM32_FUNCTION(10, "SDMMC2_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(32, "PC0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(4, "DFSDM1_CKIN0"),
STM32_FUNCTION(5, "LPTIM2_IN2"),
STM32_FUNCTION(7, "DFSDM1_DATIN4"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(11, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(33, "PC1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(4, "DFSDM1_DATIN0"),
STM32_FUNCTION(5, "DFSDM1_CKIN4"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(10, "SDMMC2_CK"),
STM32_FUNCTION(12, "ETH1_MDC"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(34, "PC2"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(4, "DFSDM1_CKIN1"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "DFSDM1_CKOUT"),
STM32_FUNCTION(12, "ETH1_GMII_TXD2 ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(35, "PC3"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(4, "DFSDM1_DATIN1"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(12, "ETH1_GMII_TX_CLK ETH1_MII_TX_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(36, "PC4"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(4, "DFSDM1_CKIN2"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(10, "SPDIFRX_IN2"),
STM32_FUNCTION(12, "ETH1_GMII_RXD0 ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(37, "PC5"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(3, "SAI1_D3"),
STM32_FUNCTION(4, "DFSDM1_DATIN2"),
STM32_FUNCTION(5, "SAI4_D4"),
STM32_FUNCTION(7, "SAI1_D4"),
STM32_FUNCTION(10, "SPDIFRX_IN3"),
STM32_FUNCTION(12, "ETH1_GMII_RXD1 ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
STM32_FUNCTION(13, "SAI4_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(38, "PC6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(1, "HDP1"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(5, "DFSDM1_CKIN3"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(9, "SDMMC1_D0DIR"),
STM32_FUNCTION(10, "SDMMC2_D0DIR"),
STM32_FUNCTION(11, "SDMMC2_D6"),
STM32_FUNCTION(12, "DSI_TE"),
STM32_FUNCTION(13, "SDMMC1_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(39, "PC7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(1, "HDP4"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(5, "DFSDM1_DATIN3"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "SDMMC1_D123DIR"),
STM32_FUNCTION(10, "SDMMC2_D123DIR"),
STM32_FUNCTION(11, "SDMMC2_D7"),
STM32_FUNCTION(13, "SDMMC1_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(40, "PC8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(7, "UART4_TX"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(9, "UART5_RTS UART5_DE"),
STM32_FUNCTION(13, "SDMMC1_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(41, "PC9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(9, "UART5_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(13, "SDMMC1_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(42, "PC10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(4, "DFSDM1_CKIN5"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "SAI4_MCLK_B"),
STM32_FUNCTION(13, "SDMMC1_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(43, "PC11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(4, "DFSDM1_DATIN5"),
STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(11, "SAI4_SCK_B"),
STM32_FUNCTION(13, "SDMMC1_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(44, "PC12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(3, "SAI4_D3"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(11, "SAI4_SD_B"),
STM32_FUNCTION(13, "SDMMC1_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(45, "PC13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(46, "PC14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(47, "PC15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(48, "PD0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(4, "DFSDM1_CKIN6"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(7, "SAI3_SCK_A"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(11, "SDMMC3_CMD"),
STM32_FUNCTION(12, "DFSDM1_DATIN7"),
STM32_FUNCTION(13, "FMC_D2 FMC_DA2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(49, "PD1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(4, "DFSDM1_DATIN6"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(7, "SAI3_SD_A"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(11, "SDMMC3_D0"),
STM32_FUNCTION(12, "DFSDM1_CKIN7"),
STM32_FUNCTION(13, "FMC_D3 FMC_DA3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(50, "PD2"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(7, "UART4_RX"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDMMC1_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(51, "PD3"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(1, "HDP5"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM1_DATIN0"),
STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(9, "SDMMC1_D123DIR"),
STM32_FUNCTION(10, "SDMMC2_D7"),
STM32_FUNCTION(11, "SDMMC2_D123DIR"),
STM32_FUNCTION(12, "SDMMC1_D7"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(52, "PD4"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(7, "SAI3_FS_A"),
STM32_FUNCTION(8, "USART2_RTS USART2_DE"),
STM32_FUNCTION(11, "SDMMC3_D1"),
STM32_FUNCTION(12, "DFSDM1_CKIN0"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(53, "PD5"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(11, "SDMMC3_D2"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(54, "PD6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(4, "DFSDM1_CKIN4"),
STM32_FUNCTION(5, "DFSDM1_DATIN1"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(55, "PD7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(4, "DFSDM1_DATIN4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(7, "DFSDM1_CKIN1"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(10, "SPDIFRX_IN0"),
STM32_FUNCTION(11, "SDMMC3_D3"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(56, "PD8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(4, "DFSDM1_CKIN3"),
STM32_FUNCTION(7, "SAI3_SCK_B"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "SPDIFRX_IN1"),
STM32_FUNCTION(13, "FMC_D13 FMC_DA13"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(57, "PD9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(4, "DFSDM1_DATIN3"),
STM32_FUNCTION(7, "SAI3_SD_B"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "FMC_D14 FMC_DA14"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(58, "PD10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "SAI3_FS_B"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(13, "FMC_D15 FMC_DA15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(59, "PD11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(4, "LPTIM2_IN2"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(6, "I2C1_SMBA"),
STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_CLE FMC_A16"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(60, "PD12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "LPTIM2_IN1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(6, "I2C1_SCL"),
STM32_FUNCTION(8, "USART3_RTS USART3_DE"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_ALE FMC_A17"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(61, "PD13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(2, "LPTIM1_OUT"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(6, "I2C1_SDA"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(62, "PD14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(7, "SAI3_MCLK_B"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D0 FMC_DA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(63, "PD15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(7, "SAI3_MCLK_A"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D1 FMC_DA1"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(64, "PE0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(5, "LPTIM2_ETR"),
STM32_FUNCTION(6, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(7, "SAI4_MCLK_B"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(65, "PE1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(7, "SAI3_SD_B"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(66, "PE2"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SAI1_CK1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(12, "ETH1_GMII_TXD3 ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(67, "PE3"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(10, "SDMMC2_CK"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(68, "PE4"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "SAI1_D2"),
STM32_FUNCTION(4, "DFSDM1_DATIN3"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(8, "SDMMC2_CKIN"),
STM32_FUNCTION(9, "SDMMC1_CKIN"),
STM32_FUNCTION(10, "SDMMC2_D4"),
STM32_FUNCTION(12, "SDMMC1_D4"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(69, "PE5"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(3, "SAI1_CK2"),
STM32_FUNCTION(4, "DFSDM1_CKIN3"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(8, "SDMMC2_D0DIR"),
STM32_FUNCTION(9, "SDMMC1_D0DIR"),
STM32_FUNCTION(10, "SDMMC2_D6"),
STM32_FUNCTION(12, "SDMMC1_D6"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(70, "PE6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "SDMMC2_D0"),
STM32_FUNCTION(9, "SDMMC1_D2"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(71, "PE7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(4, "DFSDM1_DATIN2"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(13, "FMC_D4 FMC_DA4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(72, "PE8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "DFSDM1_CKIN2"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_D5 FMC_DA5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(73, "PE9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D6 FMC_DA6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(74, "PE10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "DFSDM1_DATIN4"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_D7 FMC_DA7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(75, "PE11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(4, "DFSDM1_CKIN4"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_D8 FMC_DA8"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(76, "PE12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "DFSDM1_DATIN5"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(9, "SDMMC1_D0DIR"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(13, "FMC_D9 FMC_DA9"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(77, "PE13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(1, "HDP2"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(4, "DFSDM1_CKIN5"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_D10 FMC_DA10"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(78, "PE14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "SDMMC1_D123DIR"),
STM32_FUNCTION(13, "FMC_D11 FMC_DA11"),
STM32_FUNCTION(14, "LCD_G0"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(79, "PE15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(1, "HDP3"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(11, "FMC_NCE2"),
STM32_FUNCTION(13, "FMC_D12 FMC_DA12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(80, "PF0"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(10, "SDMMC3_D0"),
STM32_FUNCTION(11, "SDMMC3_CKIN"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(81, "PF1"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(10, "SDMMC3_CMD"),
STM32_FUNCTION(11, "SDMMC3_CDIR"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(82, "PF2"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(10, "SDMMC2_D0DIR"),
STM32_FUNCTION(11, "SDMMC3_D0DIR"),
STM32_FUNCTION(12, "SDMMC1_D0DIR"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(83, "PF3"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(12, "ETH1_GMII_TX_ER ETH1_MII_TX_ER"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(84, "PF4"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(10, "SDMMC3_D1"),
STM32_FUNCTION(11, "SDMMC3_D123DIR"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(85, "PF5"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(10, "SDMMC3_D2"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(86, "PF6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(13, "SAI4_SCK_B"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(87, "PF7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(88, "PF8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(1, "TRACED12"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(89, "PF9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(1, "TRACED13"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(90, "PF10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "SAI1_D3"),
STM32_FUNCTION(4, "SAI4_D4"),
STM32_FUNCTION(7, "SAI1_D4"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(13, "SAI4_D3"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(91, "PF11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(92, "PF12"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(12, "ETH1_GMII_RXD4"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(93, "PF13"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(4, "DFSDM1_DATIN6"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(6, "I2C1_SMBA"),
STM32_FUNCTION(7, "DFSDM1_DATIN3"),
STM32_FUNCTION(12, "ETH1_GMII_RXD5"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(94, "PF14"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(4, "DFSDM1_CKIN6"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(6, "I2C1_SCL"),
STM32_FUNCTION(12, "ETH1_GMII_RXD6"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(95, "PF15"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(6, "I2C1_SDA"),
STM32_FUNCTION(12, "ETH1_GMII_RXD7"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(96, "PG0"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(4, "DFSDM1_DATIN0"),
STM32_FUNCTION(12, "ETH1_GMII_TXD4"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(97, "PG1"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(12, "ETH1_GMII_TXD5"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(98, "PG2"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(12, "ETH1_GMII_TXD6"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(99, "PG3"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "DFSDM1_CKIN1"),
STM32_FUNCTION(12, "ETH1_GMII_TXD7"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(100, "PG4"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(12, "ETH1_GMII_GTX_CLK ETH1_RGMII_GTX_CLK"),
STM32_FUNCTION(13, "FMC_A14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(101, "PG5"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(12, "ETH1_GMII_CLK125 ETH1_RGMII_CLK125"),
STM32_FUNCTION(13, "FMC_A15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(102, "PG6"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(1, "TRACED14"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(11, "SDMMC2_CMD"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(103, "PG7"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(12, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_INT"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(104, "PG8"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(1, "TRACED15"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "ETH_CLK"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(7, "SAI4_D2"),
STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
STM32_FUNCTION(9, "USART3_RTS USART3_DE"),
STM32_FUNCTION(10, "SPDIFRX_IN2"),
STM32_FUNCTION(11, "SAI4_FS_A"),
STM32_FUNCTION(12, "ETH1_PPS_OUT"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(105, "PG9"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "SPDIFRX_IN3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_NCE FMC_NE2"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(106, "PG10"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(1, "TRACED10"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(107, "PG11"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(1, "TRACED11"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(7, "UART4_TX"),
STM32_FUNCTION(9, "SPDIFRX_IN0"),
STM32_FUNCTION(12, "ETH1_GMII_TX_EN ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(108, "PG12"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(7, "SAI4_CK2"),
STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
STM32_FUNCTION(9, "SPDIFRX_IN1"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(11, "SAI4_SCK_A"),
STM32_FUNCTION(12, "ETH1_PHY_INTN"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(109, "PG13"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "LPTIM1_OUT"),
STM32_FUNCTION(3, "SAI1_CK2"),
STM32_FUNCTION(5, "SAI4_CK1"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
STM32_FUNCTION(11, "SAI4_MCLK_A"),
STM32_FUNCTION(12, "ETH1_GMII_TXD0 ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(110, "PG14"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(7, "SAI4_D1"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(11, "SAI4_SD_A"),
STM32_FUNCTION(12, "ETH1_GMII_TXD1 ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(111, "PG15"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(3, "SAI1_D2"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
STM32_FUNCTION(11, "SDMMC3_CK"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(112, "PH0"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(113, "PH1"),
STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(114, "PH2"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(115, "PH3"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(4, "DFSDM1_CKIN4"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(116, "PH4"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(10, "LCD_G5"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(117, "PH5"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "SAI4_SD_B"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(118, "PH6"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(3, "TIM12_CH1"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(12, "ETH1_GMII_RXD2 ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(119, "PH7"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH1_GMII_RXD3 ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(120, "PH8"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(121, "PH9"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(3, "TIM12_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(122, "PH10"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(6, "I2C1_SMBA"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(123, "PH11"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(6, "I2C1_SCL"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(124, "PH12"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(1, "HDP2"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(6, "I2C1_SDA"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(125, "PH13"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(126, "PH14"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(127, "PH15"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(128, "PI0"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(129, "PI1"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(130, "PI2"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(131, "PI3"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(132, "PI4"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(133, "PI5"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(134, "PI6"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(135, "PI7"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(136, "PI8"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(137, "PI9"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(1, "HDP1"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(138, "PI10"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(1, "HDP0"),
STM32_FUNCTION(9, "USART3_CTS USART3_NSS"),
STM32_FUNCTION(12, "ETH1_GMII_RX_ER ETH1_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(139, "PI11"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(10, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(140, "PI12"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "HDP0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(141, "PI13"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "HDP1"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(142, "PI14"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(143, "PI15"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(10, "LCD_G2"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(144, "PJ0"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(1, "TRACED8"),
STM32_FUNCTION(10, "LCD_R7"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(145, "PJ1"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(1, "TRACED9"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(146, "PJ2"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(1, "TRACED10"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(147, "PJ3"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(1, "TRACED11"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(148, "PJ4"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(1, "TRACED12"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(149, "PJ5"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "HDP2"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(150, "PJ6"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(3, "HDP3"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(151, "PJ7"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(1, "TRACED13"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(152, "PJ8"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(1, "TRACED14"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(153, "PJ9"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(1, "TRACED15"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(154, "PJ10"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(155, "PJ11"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(156, "PJ12"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(157, "PJ13"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(10, "LCD_G4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(158, "PJ14"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(159, "PJ15"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(160, "PK0"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(161, "PK1"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(3, "HDP4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(162, "PK2"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "HDP5"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(163, "PK3"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(164, "PK4"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(165, "PK5"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(3, "HDP6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(166, "PK6"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(3, "HDP7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(167, "PK7"),
STM32MP_PKG_AA,
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static const struct stm32_desc_pin stm32mp157_z_pins[] = {
STM32_PIN_PKG(
PINCTRL_PIN(400, "PZ0"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ0"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(4, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(401, "PZ1"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ1"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(4, "I2C2_SDA"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(402, "PZ2"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ2"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(4, "I2C2_SCL"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(403, "PZ3"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ3"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(4, "I2C2_SDA"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
STM32_FUNCTION(9, "SPI6_NSS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(404, "PZ4"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ4"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(4, "I2C2_SCL"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(405, "PZ5"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ5"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(4, "I2C2_SDA"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(406, "PZ6"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ6"),
STM32_FUNCTION(3, "I2C6_SCL"),
STM32_FUNCTION(4, "I2C2_SCL"),
STM32_FUNCTION(5, "USART1_CK"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN_PKG(
PINCTRL_PIN(407, "PZ7"),
STM32MP_PKG_AA | STM32MP_PKG_AC,
STM32_FUNCTION(0, "GPIOZ7"),
STM32_FUNCTION(3, "I2C6_SDA"),
STM32_FUNCTION(4, "I2C2_SDA"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32mp157_match_data = {
.pins = stm32mp157_pins,
.npins = ARRAY_SIZE(stm32mp157_pins),
};
static struct stm32_pinctrl_match_data stm32mp157_z_match_data = {
.pins = stm32mp157_z_pins,
.npins = ARRAY_SIZE(stm32mp157_z_pins),
};
static const struct of_device_id stm32mp157_pctrl_match[] = {
{
.compatible = "st,stm32mp157-pinctrl",
.data = &stm32mp157_match_data,
},
{
.compatible = "st,stm32mp157-z-pinctrl",
.data = &stm32mp157_z_match_data,
},
{ }
};
static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
};
static struct platform_driver stm32mp157_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32mp157-pinctrl",
.of_match_table = stm32mp157_pctrl_match,
.pm = &stm32_pinctrl_dev_pm_ops,
},
};
static int __init stm32mp157_pinctrl_init(void)
{
return platform_driver_register(&stm32mp157_pinctrl_driver);
}
arch_initcall(stm32mp157_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32mp157.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32mp135_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(12, "ETH1_MII_CRS"),
STM32_FUNCTION(13, "ETH2_MII_CRS"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(4, "LPTIM3_OUT"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(7, "DFSDM1_CKIN0"),
STM32_FUNCTION(8, "USART2_RTS USART2_DE"),
STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "LPTIM4_OUT"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(12, "ETH1_MDIO"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "LPTIM5_OUT"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(12, "ETH1_MII_COL"),
STM32_FUNCTION(13, "ETH2_MII_COL"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(4, "USART2_CK"),
STM32_FUNCTION(5, "SAI1_SCK_B"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "DFSDM1_CKIN1"),
STM32_FUNCTION(11, "ETH1_PPS_OUT"),
STM32_FUNCTION(12, "ETH2_PPS_OUT"),
STM32_FUNCTION(13, "SAI1_SCK_A"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "USART2_CK"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(5, "SAI1_D1"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(11, "ETH1_PPS_OUT"),
STM32_FUNCTION(12, "ETH2_PPS_OUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(5, "SAI2_CK2"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(9, "UART4_RTS UART4_DE"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(13, "SAI2_SCK_A"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(5, "SAI2_D1"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(12, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
STM32_FUNCTION(13, "SAI2_SD_A"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(3, "SAI2_MCLK_A"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI2_CK1"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(9, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(11, "OTG_HS_SOF"),
STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(7, "DFSDM1_DATIN0"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(11, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMIPP_D0"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
STM32_FUNCTION(12, "ETH1_CLK"),
STM32_FUNCTION(14, "ETH2_CLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(3, "SAI2_MCLK_A"),
STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
STM32_FUNCTION(11, "TSC_G1_IO2"),
STM32_FUNCTION(12, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(14, "DCMIPP_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(2, "DBTRGI"),
STM32_FUNCTION(3, "MCO1"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(2, "DBTRGI"),
STM32_FUNCTION(3, "MCO2"),
STM32_FUNCTION(11, "OTG_HS_SOF"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "TRACED5"),
STM32_FUNCTION(2, "TIM2_CH1"),
STM32_FUNCTION(6, "I2S4_MCK"),
STM32_FUNCTION(8, "UART4_RTS UART4_DE"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "LCD_R0"),
STM32_FUNCTION(11, "TSC_G3_IO1"),
STM32_FUNCTION(12, "LCD_G7"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(14, "DCMIPP_D14"),
STM32_FUNCTION(15, "DCMIPP_D5"),
STM32_FUNCTION(16, "HDP5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(1, "DBTRGI"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(7, "SAI2_FS_A"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(11, "SAI2_D2"),
STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(7, "DFSDM1_DATIN1"),
STM32_FUNCTION(8, "UART4_RX"),
STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(2, "RTC_OUT2"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "ETH2_MDIO"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(5, "SAI2_CK1"),
STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"),
STM32_FUNCTION(9, "SDMMC1_D123DIR"),
STM32_FUNCTION(11, "SDMMC2_D2"),
STM32_FUNCTION(12, "LCD_R6"),
STM32_FUNCTION(13, "SAI2_MCLK_A"),
STM32_FUNCTION(14, "UART7_RX"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "TRACED14"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(5, "SAI2_CK2"),
STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(11, "SDMMC2_D3"),
STM32_FUNCTION(12, "LCD_G1"),
STM32_FUNCTION(13, "SAI2_SCK_A"),
STM32_FUNCTION(14, "LCD_B6"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(9, "SDMMC1_CKIN"),
STM32_FUNCTION(10, "FDCAN2_RX"),
STM32_FUNCTION(12, "UART5_RX"),
STM32_FUNCTION(14, "LCD_B6"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(1, "TRACED6"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(7, "SAI1_CK2"),
STM32_FUNCTION(8, "LCD_B6"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(11, "TSC_G1_IO4"),
STM32_FUNCTION(12, "ETH2_MDIO"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMIPP_D5"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "HDP6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(4, "TSC_SYNC"),
STM32_FUNCTION(6, "I2S4_CK"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(11, "FMC_NCE2"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMIPP_D13"),
STM32_FUNCTION(15, "DCMIPP_PIXCLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(6, "I2C3_SCL"),
STM32_FUNCTION(7, "DFSDM1_DATIN1"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(11, "SAI1_D1"),
STM32_FUNCTION(13, "FMC_D13 FMC_AD13"),
STM32_FUNCTION(14, "DCMIPP_D6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(11, "SDMMC2_D5"),
STM32_FUNCTION(12, "UART5_TX"),
STM32_FUNCTION(13, "SDMMC1_CDIR"),
STM32_FUNCTION(14, "LCD_DE"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(4, "LPTIM2_IN1"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"),
STM32_FUNCTION(7, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(4, "LPTIM1_OUT"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(12, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(1, "TRACED10"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(7, "DFSDM1_DATIN1"),
STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
STM32_FUNCTION(9, "USART3_RX"),
STM32_FUNCTION(12, "UART5_RX"),
STM32_FUNCTION(13, "SDMMC1_D5"),
STM32_FUNCTION(14, "LCD_R3"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(5, "LPTIM2_OUT"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(9, "SDMMC1_D123DIR"),
STM32_FUNCTION(10, "FDCAN2_TX"),
STM32_FUNCTION(12, "UART5_TX"),
STM32_FUNCTION(14, "LCD_CLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM12_CH1"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(11, "SDMMC2_D0"),
STM32_FUNCTION(12, "SDMMC1_D4"),
STM32_FUNCTION(14, "LCD_R0"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM12_CH2"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(5, "SAI2_D2"),
STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"),
STM32_FUNCTION(7, "DFSDM1_CKIN2"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(9, "SDMMC1_CKIN"),
STM32_FUNCTION(11, "SDMMC2_D1"),
STM32_FUNCTION(13, "SAI2_FS_A"),
STM32_FUNCTION(14, "LCD_CLK"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(3, "SAI1_SCK_A"),
STM32_FUNCTION(5, "SAI1_CK2"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(7, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(4, "DFSDM1_DATIN0"),
STM32_FUNCTION(7, "SAI1_D3"),
STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RMII_CRS_DV"),
STM32_FUNCTION(12, "ETH1_RGMII_GTX_CLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(2, "SPI5_NSS"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SAI2_MCLK_A"),
STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
STM32_FUNCTION(11, "SAI2_CK1"),
STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(3, "SAI1_CK1"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(7, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(9, "UART5_CTS"),
STM32_FUNCTION(11, "SAI1_MCLK_A"),
STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
STM32_FUNCTION(13, "ETH2_MII_TX_CLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(4, "DFSDM1_CKIN2"),
STM32_FUNCTION(5, "SAI1_D3"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(9, "UART5_RTS UART5_DE"),
STM32_FUNCTION(10, "SPDIFRX_IN2"),
STM32_FUNCTION(12, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
STM32_FUNCTION(13, "SAI2_D3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(4, "DFSDM1_DATIN2"),
STM32_FUNCTION(5, "SAI2_D4"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(7, "SAI1_D4"),
STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(10, "SPDIFRX_IN3"),
STM32_FUNCTION(12, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(5, "DFSDM1_DATIN0"),
STM32_FUNCTION(6, "I2S3_MCK"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(9, "SDMMC1_D6"),
STM32_FUNCTION(10, "SDMMC2_D0DIR"),
STM32_FUNCTION(11, "SDMMC2_D6"),
STM32_FUNCTION(12, "LCD_B1"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(14, "LCD_R6"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "HDP2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(7, "I2S2_MCK"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "USART3_CTS"),
STM32_FUNCTION(10, "SDMMC2_CDIR"),
STM32_FUNCTION(11, "SDMMC2_D7"),
STM32_FUNCTION(12, "LCD_R1"),
STM32_FUNCTION(13, "SDMMC1_D7"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "HDP4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(9, "USART3_CTS"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(12, "UART5_RTS UART5_DE"),
STM32_FUNCTION(13, "SDMMC1_D0"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(9, "UART5_CTS"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(13, "SDMMC1_D1"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(6, "I2C1_SCL"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "SDMMC1_D2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(13, "SDMMC1_D3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "SDMMC1_CK"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(3, "SAI1_MCLK_A"),
STM32_FUNCTION(7, "SAI1_CK1"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(13, "FMC_D2 FMC_AD2"),
STM32_FUNCTION(14, "DCMIPP_D1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "LCD_B6"),
STM32_FUNCTION(13, "FMC_D3 FMC_AD3"),
STM32_FUNCTION(14, "DCMIPP_D13"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(1, "TRACED4"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(7, "SAI2_D1"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "SDMMC1_CMD"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(3, "TIM2_CH1"),
STM32_FUNCTION(4, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(5, "DFSDM1_CKOUT"),
STM32_FUNCTION(6, "I2C1_SDA"),
STM32_FUNCTION(7, "SAI1_D3"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMIPP_D5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(4, "USART2_RTS USART2_DE"),
STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(7, "DFSDM1_CKIN0"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(12, "LCD_R1"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(14, "LCD_R4"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(14, "LCD_B0"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "TSC_G2_IO1"),
STM32_FUNCTION(14, "DCMIPP_D4"),
STM32_FUNCTION(15, "DCMIPP_D0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(4, "USART2_CK"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "I2C3_SDA"),
STM32_FUNCTION(10, "SPDIFRX_IN0"),
STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
STM32_FUNCTION(12, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(4, "USART2_TX"),
STM32_FUNCTION(6, "I2S4_WS"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(11, "TSC_G1_IO3"),
STM32_FUNCTION(14, "DCMIPP_D9"),
STM32_FUNCTION(15, "DCMIPP_D3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(4, "DFSDM1_DATIN3"),
STM32_FUNCTION(11, "SDMMC2_CDIR"),
STM32_FUNCTION(12, "LCD_B5"),
STM32_FUNCTION(13, "FMC_D14 FMC_AD14"),
STM32_FUNCTION(14, "LCD_CLK"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(5, "I2C5_SMBA"),
STM32_FUNCTION(6, "SPI4_NSS I2S4_WS"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "LCD_G5"),
STM32_FUNCTION(11, "TSC_G2_IO2"),
STM32_FUNCTION(12, "LCD_B7"),
STM32_FUNCTION(13, "FMC_D15 FMC_AD15"),
STM32_FUNCTION(14, "DCMIPP_VSYNC"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(4, "LPTIM2_IN2"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
STM32_FUNCTION(9, "SPDIFRX_IN0"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(11, "ETH2_RGMII_CLK125"),
STM32_FUNCTION(12, "LCD_R7"),
STM32_FUNCTION(13, "FMC_CLE FMC_A16"),
STM32_FUNCTION(14, "UART7_RX"),
STM32_FUNCTION(15, "DCMIPP_D4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(6, "I2C1_SCL"),
STM32_FUNCTION(8, "USART3_RTS USART3_DE"),
STM32_FUNCTION(13, "FMC_ALE FMC_A17"),
STM32_FUNCTION(14, "DCMIPP_D6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(2, "LPTIM2_ETR"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(5, "SAI1_CK1"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "TSC_G2_IO4"),
STM32_FUNCTION(12, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D0 FMC_AD0"),
STM32_FUNCTION(14, "DCMIPP_D8"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(2, "USART2_RX"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "DFSDM1_DATIN2"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(13, "FMC_D1 FMC_AD1"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(7, "DCMIPP_D12"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(10, "FDCAN2_RX"),
STM32_FUNCTION(11, "TSC_G4_IO1"),
STM32_FUNCTION(12, "LCD_B1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(14, "DCMIPP_D1"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(4, "TSC_G2_IO3"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(10, "LCD_HSYNC"),
STM32_FUNCTION(12, "LCD_R4"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMIPP_D3"),
STM32_FUNCTION(15, "DCMIPP_D12"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(2, "TIM2_ETR"),
STM32_FUNCTION(4, "TSC_G5_IO1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
STM32_FUNCTION(10, "SPDIFRX_IN1"),
STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED11"),
STM32_FUNCTION(3, "SAI2_D4"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"),
STM32_FUNCTION(9, "USART3_RTS USART3_DE"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(11, "SDMMC2_CK"),
STM32_FUNCTION(14, "LCD_R4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(2, "SPI5_MISO"),
STM32_FUNCTION(3, "SAI1_D2"),
STM32_FUNCTION(4, "DFSDM1_DATIN3"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(11, "FMC_NCE2"),
STM32_FUNCTION(12, "TSC_G1_IO1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(14, "DCMIPP_D3"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(3, "SAI2_SCK_B"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(3, "SAI2_SCK_B"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(6, "I2C3_SMBA"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(9, "UART4_RTS UART4_DE"),
STM32_FUNCTION(12, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMIPP_D7"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(5, "LPTIM2_IN1"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "FMC_D4 FMC_AD4"),
STM32_FUNCTION(14, "LCD_B3"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "DFSDM1_CKIN2"),
STM32_FUNCTION(6, "I2C1_SDA"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(13, "FMC_D5 FMC_AD5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(12, "LCD_HSYNC"),
STM32_FUNCTION(13, "FMC_D6 FMC_AD6"),
STM32_FUNCTION(14, "DCMIPP_D7"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "HDP3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(13, "FMC_D7 FMC_AD7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(3, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(5, "SAI1_D2"),
STM32_FUNCTION(6, "SPI4_MOSI I2S4_SDO"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(10, "LCD_R0"),
STM32_FUNCTION(11, "ETH2_MII_TX_ER"),
STM32_FUNCTION(12, "ETH1_MII_TX_ER"),
STM32_FUNCTION(13, "FMC_D8 FMC_AD8"),
STM32_FUNCTION(14, "DCMIPP_D10"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"),
STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
STM32_FUNCTION(10, "LCD_VSYNC"),
STM32_FUNCTION(11, "TSC_G3_IO2"),
STM32_FUNCTION(12, "LCD_G4"),
STM32_FUNCTION(13, "FMC_D9 FMC_AD9"),
STM32_FUNCTION(14, "DCMIPP_D11"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "HDP4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"),
STM32_FUNCTION(12, "LCD_B1"),
STM32_FUNCTION(13, "FMC_D10 FMC_AD10"),
STM32_FUNCTION(14, "DCMIPP_D4"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "SAI1_D4"),
STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D11 FMC_AD11"),
STM32_FUNCTION(14, "DCMIPP_D7"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM2_ETR"),
STM32_FUNCTION(3, "TIM1_BKIN"),
STM32_FUNCTION(4, "USART2_CTS USART2_NSS"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_D12 FMC_AD12"),
STM32_FUNCTION(14, "DCMIPP_D10"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "HDP7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(1, "TRACED13"),
STM32_FUNCTION(4, "DFSDM1_CKOUT"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(11, "SDMMC2_D4"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(14, "LCD_R6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(1, "TRACED7"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(14, "LCD_B7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "HDP7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(7, "DFSDM1_CKIN1"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(10, "SDMMC2_D0DIR"),
STM32_FUNCTION(12, "SDMMC1_D0DIR"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(14, "LCD_G4"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(4, "LPTIM2_IN2"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(6, "SPI4_MISO I2S4_SDI"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(4, "USART2_RX"),
STM32_FUNCTION(11, "TSC_G3_IO3"),
STM32_FUNCTION(12, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(14, "DCMIPP_D4"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(1, "TRACED12"),
STM32_FUNCTION(5, "DFSDM1_CKIN0"),
STM32_FUNCTION(6, "I2C1_SMBA"),
STM32_FUNCTION(10, "LCD_G0"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(14, "DCMIPP_D11"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(12, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"),
STM32_FUNCTION(14, "LCD_R7"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(11, "ETH1_RGMII_CLK125"),
STM32_FUNCTION(12, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(14, "DCMIPP_D15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(3, "TIM1_CH1"),
STM32_FUNCTION(4, "DFSDM1_CKIN3"),
STM32_FUNCTION(7, "SAI1_D4"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(12, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "SAI1_D3"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
STM32_FUNCTION(9, "UART7_RTS UART7_DE"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(14, "DCMIPP_HSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(2, "USART2_TX"),
STM32_FUNCTION(3, "SAI1_D2"),
STM32_FUNCTION(4, "DFSDM1_CKIN3"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(13, "ETH2_MII_RX_ER"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(11, "ETH1_MII_TX_ER"),
STM32_FUNCTION(12, "ETH1_RGMII_CLK125"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(2, "TIM2_ETR"),
STM32_FUNCTION(3, "SAI1_MCLK_B"),
STM32_FUNCTION(7, "DFSDM1_DATIN3"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(10, "FDCAN2_TX"),
STM32_FUNCTION(11, "TSC_G4_IO2"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(14, "DCMIPP_PIXCLK"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(4, "SAI2_FS_A"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "SAI2_D2"),
STM32_FUNCTION(10, "FDCAN2_TX"),
STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(2, "MCO2"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH1_MDC"),
STM32_FUNCTION(14, "DCMIPP_D1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(7, "SAI2_SD_B"),
STM32_FUNCTION(10, "FDCAN2_RX"),
STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"),
STM32_FUNCTION(12, "ETH1_MDIO"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(14, "DCMIPP_D15"),
STM32_FUNCTION(15, "DCMIPP_D12"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(5, "DFSDM1_CKIN3"),
STM32_FUNCTION(9, "USART3_RX"),
STM32_FUNCTION(11, "SDMMC2_D123DIR"),
STM32_FUNCTION(12, "LCD_VSYNC"),
STM32_FUNCTION(13, "FMC_A14"),
STM32_FUNCTION(14, "DCMIPP_D8"),
STM32_FUNCTION(15, "DCMIPP_D13"),
STM32_FUNCTION(16, "HDP1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(11, "ETH2_MDC"),
STM32_FUNCTION(12, "LCD_G4"),
STM32_FUNCTION(13, "FMC_A15"),
STM32_FUNCTION(14, "DCMIPP_VSYNC"),
STM32_FUNCTION(15, "DCMIPP_D3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "SAI2_D1"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(7, "SAI2_SD_A"),
STM32_FUNCTION(11, "SDMMC2_CMD"),
STM32_FUNCTION(12, "LCD_G0"),
STM32_FUNCTION(14, "LCD_DE"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "HDP3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(1, "TRACED8"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(11, "SDMMC2_CKIN"),
STM32_FUNCTION(12, "LCD_R1"),
STM32_FUNCTION(14, "LCD_R5"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(2, "TIM2_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(8, "LCD_B1"),
STM32_FUNCTION(9, "USART3_RTS USART3_DE"),
STM32_FUNCTION(10, "SPDIFRX_IN2"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(12, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(13, "FMC_NE2"),
STM32_FUNCTION(14, "ETH2_CLK"),
STM32_FUNCTION(15, "DCMIPP_D6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(1, "DBTRGO"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "SPDIFRX_IN3"),
STM32_FUNCTION(10, "FDCAN1_RX"),
STM32_FUNCTION(11, "FMC_NE2"),
STM32_FUNCTION(13, "FMC_NCE"),
STM32_FUNCTION(14, "DCMIPP_VSYNC"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(10, "FDCAN1_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMIPP_D2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(5, "SAI2_D3"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(14, "DCMIPP_D14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(4, "TSC_G5_IO2"),
STM32_FUNCTION(5, "SAI2_SCK_A"),
STM32_FUNCTION(7, "SAI2_CK2"),
STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
STM32_FUNCTION(9, "USART3_CTS"),
STM32_FUNCTION(11, "ETH2_PHY_INTN"),
STM32_FUNCTION(12, "ETH1_PHY_INTN"),
STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(2, "LPTIM1_OUT"),
STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
STM32_FUNCTION(12, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(7, "SAI2_D1"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(12, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "ETH2_PHY_INTN"),
STM32_FUNCTION(12, "LCD_B4"),
STM32_FUNCTION(14, "DCMIPP_D10"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(4, "TSC_G4_IO3"),
STM32_FUNCTION(7, "DCMIPP_D9"),
STM32_FUNCTION(8, "LCD_G1"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(11, "ETH2_MII_CRS"),
STM32_FUNCTION(12, "ETH1_MII_CRS"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(14, "ETH2_RGMII_CLK125"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(11, "ETH1_MII_COL"),
STM32_FUNCTION(12, "LCD_R5"),
STM32_FUNCTION(13, "ETH2_MII_COL"),
STM32_FUNCTION(14, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(1, "JTDO"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(3, "TIM12_CH1"),
STM32_FUNCTION(4, "USART2_CK"),
STM32_FUNCTION(5, "I2C5_SDA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(11, "ETH1_PHY_INTN"),
STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
STM32_FUNCTION(13, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
STM32_FUNCTION(14, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(3, "SAI2_FS_B"),
STM32_FUNCTION(6, "I2C3_SDA"),
STM32_FUNCTION(7, "SPI5_SCK"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(11, "ETH2_MII_TX_CLK"),
STM32_FUNCTION(12, "ETH1_MII_TX_CLK"),
STM32_FUNCTION(14, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(1, "TRACED9"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(4, "USART2_RX"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(12, "LCD_R6"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(14, "DCMIPP_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "HDP2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(3, "TIM12_CH2"),
STM32_FUNCTION(4, "TSC_SYNC"),
STM32_FUNCTION(6, "SPI4_SCK I2S4_CK"),
STM32_FUNCTION(7, "DCMIPP_D13"),
STM32_FUNCTION(10, "LCD_B5"),
STM32_FUNCTION(12, "LCD_DE"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMIPP_D9"),
STM32_FUNCTION(15, "DCMIPP_D8"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "SAI2_D3"),
STM32_FUNCTION(5, "DFSDM1_DATIN2"),
STM32_FUNCTION(6, "I2S3_MCK"),
STM32_FUNCTION(7, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
STM32_FUNCTION(9, "SDMMC1_D4"),
STM32_FUNCTION(14, "LCD_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "HDP0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(2, "SPI5_NSS"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(4, "SAI2_SD_A"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(12, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(2, "USART2_TX"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "DFSDM1_CKIN1"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(11, "SAI1_CK2"),
STM32_FUNCTION(12, "ETH1_MII_CRS"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(14, "DCMIPP_D3"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(1, "TRACED15"),
STM32_FUNCTION(3, "USART2_CK"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(5, "I2C5_SCL"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(14, "LCD_G3"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "DFSDM1_DATIN2"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(7, "DCMIPP_D8"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(12, "LCD_B4"),
STM32_FUNCTION(14, "DCMIPP_D2"),
STM32_FUNCTION(15, "DCMIPP_PIXCLK"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(9, "SPDIFRX_IN0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(9, "SPDIFRX_IN1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(9, "SPDIFRX_IN2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(9, "SPDIFRX_IN3"),
STM32_FUNCTION(12, "ETH1_MII_RX_ER"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(1, "BOOT0"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(1, "BOOT1"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(1, "BOOT2"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32mp135_match_data = {
.pins = stm32mp135_pins,
.npins = ARRAY_SIZE(stm32mp135_pins),
.secure_control = true,
};
static const struct of_device_id stm32mp135_pctrl_match[] = {
{
.compatible = "st,stm32mp135-pinctrl",
.data = &stm32mp135_match_data,
},
{ }
};
static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(stm32_pinctrl_suspend, stm32_pinctrl_resume)
};
static struct platform_driver stm32mp135_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32mp135-pinctrl",
.of_match_table = stm32mp135_pctrl_match,
.pm = &stm32_pinctrl_dev_pm_ops,
},
};
static int __init stm32mp135_pinctrl_init(void)
{
return platform_driver_register(&stm32mp135_pinctrl_driver);
}
arch_initcall(stm32mp135_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32mp135.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2017
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32f469_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(12, "ETH_MDIO"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(10, "LCD_B2"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(6, "SPI1_NSS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(13, "OTG_HS_SOF"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_SCK"),
STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_MOSI"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_CLK"),
STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(11, "OTG_FS_SOF"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(11, "OTG_FS_ID"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(8, "USART1_CTS"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "OTG_FS_DM"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(8, "USART1_RTS"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "OTG_FS_DP"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(6, "SPI1_NSS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "JTDO TRACESWO"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(6, "SPI1_SCK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "NJTRST"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "I2S3EXT_SD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "SDIO_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "SDIO_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DSIHOST_TE"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "OTG_HS_ID"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(13, "OTG_HS_DM"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "OTG_HS_DP"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(12, "ETH_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(12, "ETH_MII_TXD2"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(13, "SDIO_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(13, "SDIO_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "SDIO_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(13, "SDIO_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(13, "SDIO_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(6, "I2S3EXT_SD"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(13, "SDIO_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "SDIO_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDIO_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(13, "FMC_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "FMC_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(13, "FMC_D15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(13, "FMC_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(13, "FMC_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(13, "FMC_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(13, "FMC_D8"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(13, "FMC_D9"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(13, "FMC_D10"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(13, "FMC_D11"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(13, "FMC_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(13, "FMC_SDNRAS"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "FMC_INT"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCLK"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(13, "FMC_SDNCAS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(10, "LCD_G5"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(13, "FMC_D16"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "FMC_D17"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(13, "FMC_D18"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(13, "FMC_D19"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(13, "FMC_D20"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D21"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(13, "FMC_D22"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(127, "PH15"),
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(13, "FMC_D23"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(13, "FMC_D24"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(13, "FMC_D25"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(13, "FMC_D26"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(13, "FMC_D27"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(13, "FMC_NBL2"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(13, "FMC_NBL3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(13, "FMC_D28"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(13, "FMC_D29"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(136, "PI8"),
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(137, "PI9"),
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D30"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(138, "PI10"),
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(13, "FMC_D31"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(139, "PI11"),
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(10, "LCD_G6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(140, "PI12"),
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(141, "PI13"),
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(142, "PI14"),
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(143, "PI15"),
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(10, "LCD_G2"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(144, "PJ0"),
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(10, "LCD_R7"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(145, "PJ1"),
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(146, "PJ2"),
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(14, "DSIHOST_TE"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(147, "PJ3"),
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(148, "PJ4"),
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(149, "PJ5"),
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(156, "PJ12"),
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(157, "PJ13"),
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(10, "LCD_G4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(158, "PJ14"),
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(159, "PJ15"),
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(163, "PK3"),
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(164, "PK4"),
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(165, "PK5"),
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(166, "PK6"),
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(167, "PK7"),
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32f469_match_data = {
.pins = stm32f469_pins,
.npins = ARRAY_SIZE(stm32f469_pins),
};
static const struct of_device_id stm32f469_pctrl_match[] = {
{
.compatible = "st,stm32f469-pinctrl",
.data = &stm32f469_match_data,
},
{ }
};
static struct platform_driver stm32f469_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32f469-pinctrl",
.of_match_table = stm32f469_pctrl_match,
},
};
static int __init stm32f469_pinctrl_init(void)
{
return platform_driver_register(&stm32f469_pinctrl_driver);
}
arch_initcall(stm32f469_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32f469.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
* Copyright (C) STMicroelectronics 2017
* Author: Maxime Coquelin <[email protected]>
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32f429_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(12, "ETH_MDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(6, "SPI1_NSS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(13, "OTG_HS_SOF"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_SCK"),
STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_MOSI"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(11, "OTG_FS_SOF"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(11, "OTG_FS_ID"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(8, "USART1_CTS"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "OTG_FS_DM"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(8, "USART1_RTS"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "OTG_FS_DP"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(6, "SPI1_NSS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "JTDO TRACESWO"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(6, "SPI1_SCK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "NJTRST"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "I2S3EXT_SD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "SDIO_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "SDIO_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "OTG_HS_ID"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(13, "OTG_HS_DM"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "OTG_HS_DP"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(12, "ETH_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(12, "ETH_MII_TXD2"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(13, "SDIO_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(13, "SDIO_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "SDIO_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(13, "SDIO_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(13, "SDIO_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(6, "I2S3EXT_SD"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(13, "SDIO_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "SDIO_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDIO_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(13, "FMC_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "FMC_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(13, "FMC_D15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(13, "FMC_A16"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(13, "FMC_A17"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(13, "FMC_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(13, "FMC_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(13, "FMC_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(13, "FMC_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(13, "FMC_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(13, "FMC_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(13, "FMC_D8"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(13, "FMC_D9"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(13, "FMC_D10"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(13, "FMC_D11"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(13, "FMC_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(13, "FMC_NIORD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(13, "FMC_NREG"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(13, "FMC_NIOWR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(13, "FMC_CD"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(13, "FMC_INTR"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(13, "FMC_SDNRAS"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(13, "FMC_INT2"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "FMC_INT3"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(13, "FMC_NCE4_2"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(13, "FMC_SDNCAS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(13, "FMC_D16"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "FMC_D17"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(13, "FMC_D18"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(13, "FMC_D19"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(13, "FMC_D20"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D21"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(13, "FMC_D22"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(127, "PH15"),
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(13, "FMC_D23"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(13, "FMC_D24"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(13, "FMC_D25"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "I2S2EXT_SD"),
STM32_FUNCTION(13, "FMC_D26"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(13, "FMC_D27"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(13, "FMC_NBL2"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(13, "FMC_NBL3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(13, "FMC_D28"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(13, "FMC_D29"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(136, "PI8"),
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(137, "PI9"),
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D30"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(138, "PI10"),
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(13, "FMC_D31"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(139, "PI11"),
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(140, "PI12"),
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(141, "PI13"),
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(142, "PI14"),
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(143, "PI15"),
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(144, "PJ0"),
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(145, "PJ1"),
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(146, "PJ2"),
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(147, "PJ3"),
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(148, "PJ4"),
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(149, "PJ5"),
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(150, "PJ6"),
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(151, "PJ7"),
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(152, "PJ8"),
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(153, "PJ9"),
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(154, "PJ10"),
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(155, "PJ11"),
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(156, "PJ12"),
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(157, "PJ13"),
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(158, "PJ14"),
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(159, "PJ15"),
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(160, "PK0"),
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(161, "PK1"),
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(162, "PK2"),
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(163, "PK3"),
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(164, "PK4"),
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(165, "PK5"),
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(166, "PK6"),
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(167, "PK7"),
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32f429_match_data = {
.pins = stm32f429_pins,
.npins = ARRAY_SIZE(stm32f429_pins),
};
static const struct of_device_id stm32f429_pctrl_match[] = {
{
.compatible = "st,stm32f429-pinctrl",
.data = &stm32f429_match_data,
},
{ }
};
static struct platform_driver stm32f429_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32f429-pinctrl",
.of_match_table = stm32f429_pctrl_match,
},
};
static int __init stm32f429_pinctrl_init(void)
{
return platform_driver_register(&stm32f429_pinctrl_driver);
}
arch_initcall(stm32f429_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32f429.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2017
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32f769_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(9, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MDIO"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(10, "LCD_B2"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(9, "SPI6_NSS"),
STM32_FUNCTION(13, "OTG_HS_SOF"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(11, "OTG_FS_SOF"),
STM32_FUNCTION(12, "CAN3_RX"),
STM32_FUNCTION(13, "UART7_RX"),
STM32_FUNCTION(14, "LCD_B3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(11, "OTG_FS_ID"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "UART4_RX"),
STM32_FUNCTION(8, "USART1_CTS"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "OTG_FS_DM"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "UART4_TX"),
STM32_FUNCTION(8, "USART1_RTS"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "OTG_FS_DP"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(5, "HDMI_CEC"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "SPI6_NSS"),
STM32_FUNCTION(9, "UART4_RTS"),
STM32_FUNCTION(12, "CAN3_TX"),
STM32_FUNCTION(13, "UART7_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(7, "DFSDM_CKOUT"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(7, "DFSDM_DATIN1"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(11, "DFSDM_CKIN1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "JTDO TRACESWO"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(11, "SDMMC2_D2"),
STM32_FUNCTION(12, "CAN3_RX"),
STM32_FUNCTION(13, "UART7_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "NJTRST"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(11, "SDMMC2_D3"),
STM32_FUNCTION(12, "CAN3_TX"),
STM32_FUNCTION(13, "UART7_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(2, "UART5_RX"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(2, "UART5_TX"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "HDMI_CEC"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(7, "DFSDM_DATIN5"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(7, "DFSDM_CKIN5"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(12, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(2, "I2C4_SCL"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(7, "DFSDM_CKIN7"),
STM32_FUNCTION(8, "UART5_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "SDMMC2_D4"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "SDMMC1_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(2, "I2C4_SDA"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "DFSDM_DATIN7"),
STM32_FUNCTION(8, "UART5_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "SDMMC2_D5"),
STM32_FUNCTION(12, "I2C4_SMBA"),
STM32_FUNCTION(13, "SDMMC1_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM_DATIN7"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(7, "DFSDM_CKIN7"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "DFSDM_DATIN1"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "OTG_HS_ID"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM_CKIN1"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "DFSDM_DATIN2"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(9, "UART4_RTS"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(11, "SDMMC2_D0"),
STM32_FUNCTION(13, "OTG_HS_DM"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(7, "DFSDM_CKIN2"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(11, "SDMMC2_D1"),
STM32_FUNCTION(13, "OTG_HS_DP"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(4, "DFSDM_CKIN0"),
STM32_FUNCTION(7, "DFSDM_DATIN4"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(4, "DFSDM_DATIN0"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(11, "DFSDM_CKIN4"),
STM32_FUNCTION(12, "ETH_MDC"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(4, "DFSDM_CKIN1"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(7, "DFSDM_CKOUT"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(12, "ETH_MII_TXD2"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(4, "DFSDM_DATIN1"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(4, "DFSDM_CKIN2"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(9, "SPDIF_RX2"),
STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(4, "DFSDM_DATIN2"),
STM32_FUNCTION(9, "SPDIF_RX3"),
STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(8, "DFSDM_CKIN3"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(10, "FMC_NWAIT"),
STM32_FUNCTION(11, "SDMMC2_D6"),
STM32_FUNCTION(13, "SDMMC1_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(8, "DFSDM_DATIN3"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(10, "FMC_NE1"),
STM32_FUNCTION(11, "SDMMC2_D7"),
STM32_FUNCTION(13, "SDMMC1_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(8, "UART5_RTS"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(10, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(13, "SDMMC1_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(8, "UART5_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "LCD_G3"),
STM32_FUNCTION(13, "SDMMC1_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(4, "DFSDM_CKIN5"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(13, "SDMMC1_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(4, "DFSDM_DATIN5"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(13, "SDMMC1_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "SDMMC1_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(4, "DFSDM_CKIN6"),
STM32_FUNCTION(7, "DFSDM_DATIN7"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(4, "DFSDM_DATIN6"),
STM32_FUNCTION(7, "DFSDM_CKIN7"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDMMC1_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(4, "DFSDM_CKOUT"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM_DATIN0"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(7, "DFSDM_CKIN0"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(4, "DFSDM_CKIN4"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(11, "DFSDM_DATIN1"),
STM32_FUNCTION(12, "SDMMC2_CK"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(4, "DFSDM_DATIN4"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
STM32_FUNCTION(7, "DFSDM_CKIN1"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(9, "SPDIF_RX0"),
STM32_FUNCTION(12, "SDMMC2_CMD"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(4, "DFSDM_CKIN3"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "SPDIF_RX1"),
STM32_FUNCTION(13, "FMC_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(4, "DFSDM_DATIN3"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "FMC_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(4, "DFSDM_CKOUT"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(13, "FMC_D15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "LPTIM1_IN1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(4, "LPTIM1_OUT"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(9, "UART8_RTS"),
STM32_FUNCTION(13, "FMC_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(11, "DFSDM_DATIN3"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(11, "DFSDM_CKIN3"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(7, "DFSDM_DATIN2"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(13, "FMC_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(7, "DFSDM_CKIN2"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(7, "DFSDM_CKOUT"),
STM32_FUNCTION(9, "UART7_RTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(7, "DFSDM_DATIN4"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "DFSDM_CKIN4"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_D8"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "DFSDM_DATIN5"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(13, "FMC_D9"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "DFSDM_CKIN5"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_D10"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "FMC_D11"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(13, "FMC_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(9, "UART7_RTS"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_SDNRAS"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(7, "DFSDM_DATIN6"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(7, "DFSDM_CKIN6"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "FMC_INT"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(8, "SPDIF_RX2"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCLK"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(8, "SPDIF_RX3"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(12, "SDMMC2_D0"),
STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "SDMMC2_D1"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(8, "SPDIF_RX0"),
STM32_FUNCTION(11, "SDMMC2_D2"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(4, "LPTIM1_IN1"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(8, "SPDIF_RX1"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(12, "SDMMC2_D3"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(4, "LPTIM1_OUT"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(13, "FMC_SDNCAS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(10, "LCD_G5"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(13, "FMC_D16"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "FMC_D17"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(13, "FMC_D18"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_D19"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_D20"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D21"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D22"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(127, "PH15"),
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(13, "FMC_D23"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(13, "FMC_D24"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(13, "FMC_D25"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(13, "FMC_D26"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(13, "FMC_D27"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(13, "FMC_NBL2"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_NBL3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_D28"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_D29"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(136, "PI8"),
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(137, "PI9"),
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D30"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(138, "PI10"),
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(13, "FMC_D31"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(139, "PI11"),
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(10, "LCD_G6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(140, "PI12"),
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(141, "PI13"),
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(142, "PI14"),
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(143, "PI15"),
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(10, "LCD_G2"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(144, "PJ0"),
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(10, "LCD_R7"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(145, "PJ1"),
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(146, "PJ2"),
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(147, "PJ3"),
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(148, "PJ4"),
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(149, "PJ5"),
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(150, "PJ6"),
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(151, "PJ7"),
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(152, "PJ8"),
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(153, "PJ9"),
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(154, "PJ10"),
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(155, "PJ11"),
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(156, "PJ12"),
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(157, "PJ13"),
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(10, "LCD_G4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(158, "PJ14"),
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(159, "PJ15"),
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(160, "PK0"),
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(161, "PK1"),
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(162, "PK2"),
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(163, "PK3"),
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(164, "PK4"),
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(165, "PK5"),
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(166, "PK6"),
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(167, "PK7"),
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32f769_match_data = {
.pins = stm32f769_pins,
.npins = ARRAY_SIZE(stm32f769_pins),
};
static const struct of_device_id stm32f769_pctrl_match[] = {
{
.compatible = "st,stm32f769-pinctrl",
.data = &stm32f769_match_data,
},
{ }
};
static struct platform_driver stm32f769_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32f769-pinctrl",
.of_match_table = stm32f769_pctrl_match,
},
};
static int __init stm32f769_pinctrl_init(void)
{
return platform_driver_register(&stm32f769_pinctrl_driver);
}
arch_initcall(stm32f769_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32f769.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
* Copyright (C) STMicroelectronics 2017
* Author: Maxime Coquelin <[email protected]>
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32f746_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(9, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MDIO"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(13, "OTG_HS_SOF"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(11, "OTG_FS_SOF"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(11, "OTG_FS_ID"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(8, "USART1_CTS"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "OTG_FS_DM"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(8, "USART1_RTS"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "OTG_FS_DP"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(5, "HDMI_CEC"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(9, "UART4_RTS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "JTDO TRACESWO"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "NJTRST"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(6, "SPI1_MISO"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "HDMI_CEC"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "SDMMC1_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "SDMMC1_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "OTG_HS_ID"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(13, "OTG_HS_DM"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "OTG_HS_DP"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(12, "ETH_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(12, "ETH_MII_TXD2"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(9, "SPDIFRX_IN2"),
STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(9, "SPDIFRX_IN3"),
STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(13, "SDMMC1_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(13, "SDMMC1_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(8, "UART5_RTS"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "SDMMC1_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(8, "UART5_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(13, "SDMMC1_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(13, "SDMMC1_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(7, "SPI3_MISO"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(13, "SDMMC1_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "SDMMC1_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDMMC1_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(9, "SPDIFRX_IN0"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "SPDIFRX_IN1"),
STM32_FUNCTION(13, "FMC_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(13, "FMC_D14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(13, "FMC_D15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART3_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "LPTIM1_IN1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(4, "LPTIM1_OUT"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(9, "UART8_RTS"),
STM32_FUNCTION(13, "FMC_D1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(4, "TIM9_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(4, "TIM9_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(13, "FMC_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_D5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(9, "UART7_RTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_D7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_D8"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(13, "FMC_D9"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_D10"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(13, "FMC_D11"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(13, "FMC_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(4, "TIM10_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "UART7_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(4, "TIM11_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(9, "UART7_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(9, "UART7_RTS"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(9, "UART7_CTS"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_SDNRAS"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(9, "USART6_CK"),
STM32_FUNCTION(13, "FMC_INT"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(8, "SPDIFRX_IN2"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(8, "SPDIFRX_IN3"),
STM32_FUNCTION(9, "USART6_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(8, "SPDIFRX_IN0"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(4, "LPTIM1_IN1"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(8, "SPDIFRX_IN1"),
STM32_FUNCTION(9, "USART6_RTS"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(4, "LPTIM1_OUT"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(4, "LPTIM1_ETR"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(9, "USART6_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(9, "USART6_CTS"),
STM32_FUNCTION(13, "FMC_SDNCAS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(4, "LPTIM1_IN2"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(11, "SAI2_MCLK_B"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(10, "TIM12_CH1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(13, "FMC_D16"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(10, "TIM12_CH2"),
STM32_FUNCTION(13, "FMC_D17"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(13, "FMC_D18"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_D19"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_D20"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D21"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(13, "FMC_D22"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(127, "PH15"),
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(13, "FMC_D23"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(13, "FMC_D24"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(13, "FMC_D25"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO"),
STM32_FUNCTION(13, "FMC_D26"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
STM32_FUNCTION(13, "FMC_D27"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "SAI2_MCLK_A"),
STM32_FUNCTION(13, "FMC_NBL2"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_NBL3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_D28"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_D29"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(136, "PI8"),
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(137, "PI9"),
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D30"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(138, "PI10"),
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(13, "FMC_D31"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(139, "PI11"),
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(140, "PI12"),
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(141, "PI13"),
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(142, "PI14"),
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(143, "PI15"),
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(144, "PJ0"),
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(145, "PJ1"),
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(146, "PJ2"),
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(147, "PJ3"),
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(148, "PJ4"),
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(149, "PJ5"),
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(150, "PJ6"),
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(151, "PJ7"),
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(152, "PJ8"),
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(153, "PJ9"),
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(154, "PJ10"),
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(155, "PJ11"),
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(156, "PJ12"),
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(157, "PJ13"),
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(158, "PJ14"),
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(159, "PJ15"),
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(160, "PK0"),
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(161, "PK1"),
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(162, "PK2"),
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(163, "PK3"),
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(164, "PK4"),
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(165, "PK5"),
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(166, "PK6"),
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(167, "PK7"),
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32f746_match_data = {
.pins = stm32f746_pins,
.npins = ARRAY_SIZE(stm32f746_pins),
};
static const struct of_device_id stm32f746_pctrl_match[] = {
{
.compatible = "st,stm32f746-pinctrl",
.data = &stm32f746_match_data,
},
{ }
};
static struct platform_driver stm32f746_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32f746-pinctrl",
.of_match_table = stm32f746_pctrl_match,
},
};
static int __init stm32f746_pinctrl_init(void)
{
return platform_driver_register(&stm32f746_pinctrl_driver);
}
arch_initcall(stm32f746_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32f746.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2017
* Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-stm32.h"
static const struct stm32_desc_pin stm32h743_pins[] = {
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(8, "USART2_CTS_NSS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "SDMMC2_CMD"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(1, "PA1"),
STM32_FUNCTION(0, "GPIOA1"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(4, "LPTIM3_OUT"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_MCK_B"),
STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(2, "PA2"),
STM32_FUNCTION(0, "GPIOA2"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(4, "LPTIM4_OUT"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(9, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MDIO"),
STM32_FUNCTION(13, "MDIOS_MDIO"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(3, "PA3"),
STM32_FUNCTION(0, "GPIOA3"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(4, "LPTIM5_OUT"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(10, "LCD_B2"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(4, "PA4"),
STM32_FUNCTION(0, "GPIOA4"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(9, "SPI6_NSS"),
STM32_FUNCTION(13, "OTG_HS_SOF"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(5, "PA5"),
STM32_FUNCTION(0, "GPIOA5"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(6, "PA6"),
STM32_FUNCTION(0, "GPIOA6"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "TIM8_BKIN_COMP12"),
STM32_FUNCTION(12, "MDIOS_MDC"),
STM32_FUNCTION(13, "TIM1_BKIN_COMP12"),
STM32_FUNCTION(14, "DCMI_PIXCLK"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(7, "PA7"),
STM32_FUNCTION(0, "GPIOA7"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(8, "PA8"),
STM32_FUNCTION(0, "GPIOA8"),
STM32_FUNCTION(1, "MCO1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(3, "HRTIM_CHB2"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(8, "USART1_CK"),
STM32_FUNCTION(11, "OTG_FS_SOF"),
STM32_FUNCTION(12, "UART7_RX"),
STM32_FUNCTION(13, "TIM8_BKIN2_COMP12"),
STM32_FUNCTION(14, "LCD_B3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(9, "PA9"),
STM32_FUNCTION(0, "GPIOA9"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(3, "HRTIM_CHC1"),
STM32_FUNCTION(4, "LPUART1_TX"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(10, "CAN1_RXFD"),
STM32_FUNCTION(12, "ETH_TX_ER"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(10, "PA10"),
STM32_FUNCTION(0, "GPIOA10"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(3, "HRTIM_CHC2"),
STM32_FUNCTION(4, "LPUART1_RX"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(10, "CAN1_TXFD"),
STM32_FUNCTION(11, "OTG_FS_ID"),
STM32_FUNCTION(12, "MDIOS_MDIO"),
STM32_FUNCTION(13, "LCD_B4"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(11, "PA11"),
STM32_FUNCTION(0, "GPIOA11"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(3, "HRTIM_CHD1"),
STM32_FUNCTION(4, "LPUART1_CTS"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "UART4_RX"),
STM32_FUNCTION(8, "USART1_CTS_NSS"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "OTG_FS_DM"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(12, "PA12"),
STM32_FUNCTION(0, "GPIOA12"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(3, "HRTIM_CHD2"),
STM32_FUNCTION(4, "LPUART1_RTS"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "UART4_TX"),
STM32_FUNCTION(8, "USART1_RTS"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "OTG_FS_DP"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(13, "PA13"),
STM32_FUNCTION(0, "GPIOA13"),
STM32_FUNCTION(1, "JTMS SWDIO"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(14, "PA14"),
STM32_FUNCTION(0, "GPIOA14"),
STM32_FUNCTION(1, "JTCK SWCLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(15, "PA15"),
STM32_FUNCTION(0, "GPIOA15"),
STM32_FUNCTION(1, "JTDI"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "HRTIM_FLT1"),
STM32_FUNCTION(5, "HDMI_CEC"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
STM32_FUNCTION(8, "SPI6_NSS"),
STM32_FUNCTION(9, "UART4_RTS"),
STM32_FUNCTION(12, "UART7_TX"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(16, "PB0"),
STM32_FUNCTION(0, "GPIOB0"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(7, "DFSDM_CKOUT"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "LCD_R3"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(17, "PB1"),
STM32_FUNCTION(0, "GPIOB1"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(7, "DFSDM_DATIN1"),
STM32_FUNCTION(10, "LCD_R6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(18, "PB2"),
STM32_FUNCTION(0, "GPIOB2"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(5, "DFSDM_CKIN1"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(9, "SAI4_SD_A"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(11, "SAI4_D1"),
STM32_FUNCTION(12, "ETH_TX_ER"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(19, "PB3"),
STM32_FUNCTION(0, "GPIOB3"),
STM32_FUNCTION(1, "JTDO TRACESWO"),
STM32_FUNCTION(2, "TIM2_CH2"),
STM32_FUNCTION(3, "HRTIM_FLT4"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(9, "SPI6_SCK"),
STM32_FUNCTION(10, "SDMMC2_D2"),
STM32_FUNCTION(12, "UART7_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(20, "PB4"),
STM32_FUNCTION(0, "GPIOB4"),
STM32_FUNCTION(1, "NJTRST"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "HRTIM_EEV6"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(9, "SPI6_MISO"),
STM32_FUNCTION(10, "SDMMC2_D3"),
STM32_FUNCTION(12, "UART7_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(21, "PB5"),
STM32_FUNCTION(0, "GPIOB5"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "HRTIM_EEV7"),
STM32_FUNCTION(5, "I2C1_SMBA"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(7, "I2C4_SMBA"),
STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(9, "SPI6_MOSI"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "UART5_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(22, "PB6"),
STM32_FUNCTION(0, "GPIOB6"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "HRTIM_EEV8"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(6, "HDMI_CEC"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(8, "USART1_TX"),
STM32_FUNCTION(9, "LPUART1_TX"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(12, "DFSDM_DATIN5"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "UART5_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(23, "PB7"),
STM32_FUNCTION(0, "GPIOB7"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(4, "HRTIM_EEV9"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "USART1_RX"),
STM32_FUNCTION(9, "LPUART1_RX"),
STM32_FUNCTION(10, "CAN2_TXFD"),
STM32_FUNCTION(12, "DFSDM_CKIN5"),
STM32_FUNCTION(13, "FMC_NL"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(24, "PB8"),
STM32_FUNCTION(0, "GPIOB8"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(4, "DFSDM_CKIN7"),
STM32_FUNCTION(5, "I2C1_SCL"),
STM32_FUNCTION(7, "I2C4_SCL"),
STM32_FUNCTION(8, "SDMMC1_CKIN"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(11, "SDMMC2_D4"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "SDMMC1_D4"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(25, "PB9"),
STM32_FUNCTION(0, "GPIOB9"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(4, "DFSDM_DATIN7"),
STM32_FUNCTION(5, "I2C1_SDA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "I2C4_SDA"),
STM32_FUNCTION(8, "SDMMC1_CDIR"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(11, "SDMMC2_D5"),
STM32_FUNCTION(12, "I2C4_SMBA"),
STM32_FUNCTION(13, "SDMMC1_D5"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(26, "PB10"),
STM32_FUNCTION(0, "GPIOB10"),
STM32_FUNCTION(2, "TIM2_CH3"),
STM32_FUNCTION(3, "HRTIM_SCOUT"),
STM32_FUNCTION(4, "LPTIM2_IN1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM_DATIN7"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(27, "PB11"),
STM32_FUNCTION(0, "GPIOB11"),
STM32_FUNCTION(2, "TIM2_CH4"),
STM32_FUNCTION(3, "HRTIM_SCIN"),
STM32_FUNCTION(4, "LPTIM2_ETR"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(7, "DFSDM_CKIN7"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(28, "PB12"),
STM32_FUNCTION(0, "GPIOB12"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(7, "DFSDM_DATIN1"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "CAN2_RX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "OTG_HS_ID"),
STM32_FUNCTION(14, "TIM1_BKIN_COMP12"),
STM32_FUNCTION(15, "UART5_RX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(29, "PB13"),
STM32_FUNCTION(0, "GPIOB13"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "LPTIM2_OUT"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(7, "DFSDM_CKIN1"),
STM32_FUNCTION(8, "USART3_CTS_NSS"),
STM32_FUNCTION(10, "CAN2_TX"),
STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(15, "UART5_TX"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(30, "PB14"),
STM32_FUNCTION(0, "GPIOB14"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(5, "USART1_TX"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "DFSDM_DATIN2"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(9, "UART4_RTS"),
STM32_FUNCTION(10, "SDMMC2_D0"),
STM32_FUNCTION(13, "OTG_HS_DM"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(31, "PB15"),
STM32_FUNCTION(0, "GPIOB15"),
STM32_FUNCTION(1, "RTC_REFIN"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(5, "USART1_RX"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(7, "DFSDM_CKIN2"),
STM32_FUNCTION(9, "UART4_CTS"),
STM32_FUNCTION(10, "SDMMC2_D1"),
STM32_FUNCTION(13, "OTG_HS_DP"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(32, "PC0"),
STM32_FUNCTION(0, "GPIOC0"),
STM32_FUNCTION(4, "DFSDM_CKIN0"),
STM32_FUNCTION(7, "DFSDM_DATIN4"),
STM32_FUNCTION(9, "SAI2_FS_B"),
STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(33, "PC1"),
STM32_FUNCTION(0, "GPIOC1"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(4, "DFSDM_DATIN0"),
STM32_FUNCTION(5, "DFSDM_CKIN4"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(9, "SAI4_SD_A"),
STM32_FUNCTION(10, "SDMMC2_CK"),
STM32_FUNCTION(11, "SAI4_D1"),
STM32_FUNCTION(12, "ETH_MDC"),
STM32_FUNCTION(13, "MDIOS_MDC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(34, "PC2"),
STM32_FUNCTION(0, "GPIOC2"),
STM32_FUNCTION(4, "DFSDM_CKIN1"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(7, "DFSDM_CKOUT"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(12, "ETH_MII_TXD2"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(35, "PC3"),
STM32_FUNCTION(0, "GPIOC3"),
STM32_FUNCTION(4, "DFSDM_DATIN1"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(36, "PC4"),
STM32_FUNCTION(0, "GPIOC4"),
STM32_FUNCTION(4, "DFSDM_CKIN2"),
STM32_FUNCTION(6, "I2S1_MCK"),
STM32_FUNCTION(10, "SPDIFRX_IN2"),
STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(37, "PC5"),
STM32_FUNCTION(0, "GPIOC5"),
STM32_FUNCTION(3, "SAI1_D3"),
STM32_FUNCTION(4, "DFSDM_DATIN2"),
STM32_FUNCTION(10, "SPDIFRX_IN3"),
STM32_FUNCTION(11, "SAI4_D3"),
STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(14, "COMP_1_OUT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(38, "PC6"),
STM32_FUNCTION(0, "GPIOC6"),
STM32_FUNCTION(2, "HRTIM_CHA1"),
STM32_FUNCTION(3, "TIM3_CH1"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(5, "DFSDM_CKIN3"),
STM32_FUNCTION(6, "I2S2_MCK"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(9, "SDMMC1_D0DIR"),
STM32_FUNCTION(10, "FMC_NWAIT"),
STM32_FUNCTION(11, "SDMMC2_D6"),
STM32_FUNCTION(13, "SDMMC1_D6"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(39, "PC7"),
STM32_FUNCTION(0, "GPIOC7"),
STM32_FUNCTION(1, "TRGIO"),
STM32_FUNCTION(2, "HRTIM_CHA2"),
STM32_FUNCTION(3, "TIM3_CH2"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(5, "DFSDM_DATIN3"),
STM32_FUNCTION(7, "I2S3_MCK"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "SDMMC1_D123DIR"),
STM32_FUNCTION(10, "FMC_NE1"),
STM32_FUNCTION(11, "SDMMC2_D7"),
STM32_FUNCTION(12, "SWPMI_TX"),
STM32_FUNCTION(13, "SDMMC1_D7"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(40, "PC8"),
STM32_FUNCTION(0, "GPIOC8"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "HRTIM_CHB1"),
STM32_FUNCTION(3, "TIM3_CH3"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(9, "UART5_RTS"),
STM32_FUNCTION(10, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(12, "SWPMI_RX"),
STM32_FUNCTION(13, "SDMMC1_D0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(41, "PC9"),
STM32_FUNCTION(0, "GPIOC9"),
STM32_FUNCTION(1, "MCO2"),
STM32_FUNCTION(3, "TIM3_CH4"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(6, "I2S_CKIN"),
STM32_FUNCTION(9, "UART5_CTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "LCD_G3"),
STM32_FUNCTION(12, "SWPMI_SUSPEND"),
STM32_FUNCTION(13, "SDMMC1_D1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(42, "PC10"),
STM32_FUNCTION(0, "GPIOC10"),
STM32_FUNCTION(3, "HRTIM_EEV1"),
STM32_FUNCTION(4, "DFSDM_CKIN5"),
STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(13, "SDMMC1_D2"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(43, "PC11"),
STM32_FUNCTION(0, "GPIOC11"),
STM32_FUNCTION(3, "HRTIM_FLT2"),
STM32_FUNCTION(4, "DFSDM_DATIN5"),
STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
STM32_FUNCTION(13, "SDMMC1_D3"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(44, "PC12"),
STM32_FUNCTION(0, "GPIOC12"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(3, "HRTIM_EEV2"),
STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(9, "UART5_TX"),
STM32_FUNCTION(13, "SDMMC1_CK"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(45, "PC13"),
STM32_FUNCTION(0, "GPIOC13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(46, "PC14"),
STM32_FUNCTION(0, "GPIOC14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(47, "PC15"),
STM32_FUNCTION(0, "GPIOC15"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(48, "PD0"),
STM32_FUNCTION(0, "GPIOD0"),
STM32_FUNCTION(4, "DFSDM_CKIN6"),
STM32_FUNCTION(7, "SAI3_SCK_A"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D2 FMC_DA2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(49, "PD1"),
STM32_FUNCTION(0, "GPIOD1"),
STM32_FUNCTION(4, "DFSDM_DATIN6"),
STM32_FUNCTION(7, "SAI3_SD_A"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D3 FMC_DA3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(50, "PD2"),
STM32_FUNCTION(0, "GPIOD2"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "TIM3_ETR"),
STM32_FUNCTION(9, "UART5_RX"),
STM32_FUNCTION(13, "SDMMC1_CMD"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(51, "PD3"),
STM32_FUNCTION(0, "GPIOD3"),
STM32_FUNCTION(4, "DFSDM_CKOUT"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(8, "USART2_CTS_NSS"),
STM32_FUNCTION(13, "FMC_CLK"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(52, "PD4"),
STM32_FUNCTION(0, "GPIOD4"),
STM32_FUNCTION(3, "HRTIM_FLT3"),
STM32_FUNCTION(7, "SAI3_FS_A"),
STM32_FUNCTION(8, "USART2_RTS"),
STM32_FUNCTION(10, "CAN1_RXFD"),
STM32_FUNCTION(13, "FMC_NOE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(53, "PD5"),
STM32_FUNCTION(0, "GPIOD5"),
STM32_FUNCTION(3, "HRTIM_EEV3"),
STM32_FUNCTION(8, "USART2_TX"),
STM32_FUNCTION(10, "CAN1_TXFD"),
STM32_FUNCTION(13, "FMC_NWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(54, "PD6"),
STM32_FUNCTION(0, "GPIOD6"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(4, "DFSDM_CKIN4"),
STM32_FUNCTION(5, "DFSDM_DATIN1"),
STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(8, "USART2_RX"),
STM32_FUNCTION(9, "SAI4_SD_A"),
STM32_FUNCTION(10, "CAN2_RXFD"),
STM32_FUNCTION(11, "SAI4_D1"),
STM32_FUNCTION(12, "SDMMC2_CK"),
STM32_FUNCTION(13, "FMC_NWAIT"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(55, "PD7"),
STM32_FUNCTION(0, "GPIOD7"),
STM32_FUNCTION(4, "DFSDM_DATIN4"),
STM32_FUNCTION(6, "SPI1_MOSI I2S1_SDO"),
STM32_FUNCTION(7, "DFSDM_CKIN1"),
STM32_FUNCTION(8, "USART2_CK"),
STM32_FUNCTION(10, "SPDIFRX_IN0"),
STM32_FUNCTION(12, "SDMMC2_CMD"),
STM32_FUNCTION(13, "FMC_NE1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(56, "PD8"),
STM32_FUNCTION(0, "GPIOD8"),
STM32_FUNCTION(4, "DFSDM_CKIN3"),
STM32_FUNCTION(7, "SAI3_SCK_B"),
STM32_FUNCTION(8, "USART3_TX"),
STM32_FUNCTION(10, "SPDIFRX_IN1"),
STM32_FUNCTION(13, "FMC_D13 FMC_DA13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(57, "PD9"),
STM32_FUNCTION(0, "GPIOD9"),
STM32_FUNCTION(4, "DFSDM_DATIN3"),
STM32_FUNCTION(7, "SAI3_SD_B"),
STM32_FUNCTION(8, "USART3_RX"),
STM32_FUNCTION(10, "CAN2_RXFD"),
STM32_FUNCTION(13, "FMC_D14 FMC_DA14"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(58, "PD10"),
STM32_FUNCTION(0, "GPIOD10"),
STM32_FUNCTION(4, "DFSDM_CKOUT"),
STM32_FUNCTION(7, "SAI3_FS_B"),
STM32_FUNCTION(8, "USART3_CK"),
STM32_FUNCTION(10, "CAN2_TXFD"),
STM32_FUNCTION(13, "FMC_D15 FMC_DA15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(59, "PD11"),
STM32_FUNCTION(0, "GPIOD11"),
STM32_FUNCTION(4, "LPTIM2_IN2"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(8, "USART3_CTS_NSS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_A16"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(60, "PD12"),
STM32_FUNCTION(0, "GPIOD12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "TIM4_CH1"),
STM32_FUNCTION(4, "LPTIM2_IN1"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(8, "USART3_RTS"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_A17"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(61, "PD13"),
STM32_FUNCTION(0, "GPIOD13"),
STM32_FUNCTION(2, "LPTIM1_OUT"),
STM32_FUNCTION(3, "TIM4_CH2"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_A18"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(62, "PD14"),
STM32_FUNCTION(0, "GPIOD14"),
STM32_FUNCTION(3, "TIM4_CH3"),
STM32_FUNCTION(7, "SAI3_MCLK_B"),
STM32_FUNCTION(9, "UART8_CTS"),
STM32_FUNCTION(13, "FMC_D0 FMC_DA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(63, "PD15"),
STM32_FUNCTION(0, "GPIOD15"),
STM32_FUNCTION(3, "TIM4_CH4"),
STM32_FUNCTION(7, "SAI3_MCLK_A"),
STM32_FUNCTION(9, "UART8_RTS"),
STM32_FUNCTION(13, "FMC_D1 FMC_DA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(64, "PE0"),
STM32_FUNCTION(0, "GPIOE0"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(3, "TIM4_ETR"),
STM32_FUNCTION(4, "HRTIM_SCIN"),
STM32_FUNCTION(5, "LPTIM2_ETR"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(10, "CAN1_RXFD"),
STM32_FUNCTION(11, "SAI2_MCK_A"),
STM32_FUNCTION(13, "FMC_NBL0"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(65, "PE1"),
STM32_FUNCTION(0, "GPIOE1"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(4, "HRTIM_SCOUT"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(10, "CAN1_TXFD"),
STM32_FUNCTION(13, "FMC_NBL1"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(66, "PE2"),
STM32_FUNCTION(0, "GPIOE2"),
STM32_FUNCTION(1, "TRACECLK"),
STM32_FUNCTION(3, "SAI1_CK1"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(9, "SAI4_MCLK_A"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(11, "SAI4_CK1"),
STM32_FUNCTION(12, "ETH_MII_TXD3"),
STM32_FUNCTION(13, "FMC_A23"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(67, "PE3"),
STM32_FUNCTION(0, "GPIOE3"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(5, "TIM15_BKIN"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(9, "SAI4_SD_B"),
STM32_FUNCTION(13, "FMC_A19"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(68, "PE4"),
STM32_FUNCTION(0, "GPIOE4"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(3, "SAI1_D2"),
STM32_FUNCTION(4, "DFSDM_DATIN3"),
STM32_FUNCTION(5, "TIM15_CH1N"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(7, "SAI1_FS_A"),
STM32_FUNCTION(9, "SAI4_FS_A"),
STM32_FUNCTION(11, "SAI4_D2"),
STM32_FUNCTION(13, "FMC_A20"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(69, "PE5"),
STM32_FUNCTION(0, "GPIOE5"),
STM32_FUNCTION(1, "TRACED2"),
STM32_FUNCTION(3, "SAI1_CK2"),
STM32_FUNCTION(4, "DFSDM_CKIN3"),
STM32_FUNCTION(5, "TIM15_CH1"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_A"),
STM32_FUNCTION(9, "SAI4_SCK_A"),
STM32_FUNCTION(11, "SAI4_CK2"),
STM32_FUNCTION(13, "FMC_A21"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(70, "PE6"),
STM32_FUNCTION(0, "GPIOE6"),
STM32_FUNCTION(1, "TRACED3"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(3, "SAI1_D1"),
STM32_FUNCTION(5, "TIM15_CH2"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(7, "SAI1_SD_A"),
STM32_FUNCTION(9, "SAI4_SD_A"),
STM32_FUNCTION(10, "SAI4_D1"),
STM32_FUNCTION(11, "SAI2_MCK_B"),
STM32_FUNCTION(12, "TIM1_BKIN2_COMP12"),
STM32_FUNCTION(13, "FMC_A22"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(71, "PE7"),
STM32_FUNCTION(0, "GPIOE7"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(4, "DFSDM_DATIN2"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(13, "FMC_D4 FMC_DA4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(72, "PE8"),
STM32_FUNCTION(0, "GPIOE8"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "DFSDM_CKIN2"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(13, "FMC_D5 FMC_DA5"),
STM32_FUNCTION(14, "COMP_2_OUT"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(73, "PE9"),
STM32_FUNCTION(0, "GPIOE9"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "DFSDM_CKOUT"),
STM32_FUNCTION(8, "UART7_RTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(13, "FMC_D6 FMC_DA6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(74, "PE10"),
STM32_FUNCTION(0, "GPIOE10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "DFSDM_DATIN4"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(13, "FMC_D7 FMC_DA7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(75, "PE11"),
STM32_FUNCTION(0, "GPIOE11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(4, "DFSDM_CKIN4"),
STM32_FUNCTION(6, "SPI4_NSS"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_D8 FMC_DA8"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(76, "PE12"),
STM32_FUNCTION(0, "GPIOE12"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "DFSDM_DATIN5"),
STM32_FUNCTION(6, "SPI4_SCK"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(13, "FMC_D9 FMC_DA9"),
STM32_FUNCTION(14, "COMP_1_OUT"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(77, "PE13"),
STM32_FUNCTION(0, "GPIOE13"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(4, "DFSDM_CKIN5"),
STM32_FUNCTION(6, "SPI4_MISO"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_D10 FMC_DA10"),
STM32_FUNCTION(14, "COMP_2_OUT"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(78, "PE14"),
STM32_FUNCTION(0, "GPIOE14"),
STM32_FUNCTION(2, "TIM1_CH4"),
STM32_FUNCTION(6, "SPI4_MOSI"),
STM32_FUNCTION(11, "SAI2_MCK_B"),
STM32_FUNCTION(13, "FMC_D11 FMC_DA11"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(79, "PE15"),
STM32_FUNCTION(0, "GPIOE15"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(6, "HDMI__TIM1_BKIN"),
STM32_FUNCTION(13, "FMC_D12 FMC_DA12"),
STM32_FUNCTION(14, "TIM1_BKIN_COMP12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(80, "PF0"),
STM32_FUNCTION(0, "GPIOF0"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(13, "FMC_A0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(81, "PF1"),
STM32_FUNCTION(0, "GPIOF1"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(13, "FMC_A1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(82, "PF2"),
STM32_FUNCTION(0, "GPIOF2"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(13, "FMC_A2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(83, "PF3"),
STM32_FUNCTION(0, "GPIOF3"),
STM32_FUNCTION(13, "FMC_A3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(84, "PF4"),
STM32_FUNCTION(0, "GPIOF4"),
STM32_FUNCTION(13, "FMC_A4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(85, "PF5"),
STM32_FUNCTION(0, "GPIOF5"),
STM32_FUNCTION(13, "FMC_A5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(86, "PF6"),
STM32_FUNCTION(0, "GPIOF6"),
STM32_FUNCTION(2, "TIM16_CH1"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(7, "SAI1_SD_B"),
STM32_FUNCTION(8, "UART7_RX"),
STM32_FUNCTION(9, "SAI4_SD_B"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(87, "PF7"),
STM32_FUNCTION(0, "GPIOF7"),
STM32_FUNCTION(2, "TIM17_CH1"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(7, "SAI1_MCLK_B"),
STM32_FUNCTION(8, "UART7_TX"),
STM32_FUNCTION(9, "SAI4_MCLK_B"),
STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(88, "PF8"),
STM32_FUNCTION(0, "GPIOF8"),
STM32_FUNCTION(2, "TIM16_CH1N"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(7, "SAI1_SCK_B"),
STM32_FUNCTION(8, "UART7_RTS"),
STM32_FUNCTION(9, "SAI4_SCK_B"),
STM32_FUNCTION(10, "TIM13_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(89, "PF9"),
STM32_FUNCTION(0, "GPIOF9"),
STM32_FUNCTION(2, "TIM17_CH1N"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(7, "SAI1_FS_B"),
STM32_FUNCTION(8, "UART7_CTS"),
STM32_FUNCTION(9, "SAI4_FS_B"),
STM32_FUNCTION(10, "TIM14_CH1"),
STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(90, "PF10"),
STM32_FUNCTION(0, "GPIOF10"),
STM32_FUNCTION(2, "TIM16_BKIN"),
STM32_FUNCTION(3, "SAI1_D3"),
STM32_FUNCTION(10, "QUADSPI_CLK"),
STM32_FUNCTION(11, "SAI4_D3"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(91, "PF11"),
STM32_FUNCTION(0, "GPIOF11"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_SDNRAS"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(92, "PF12"),
STM32_FUNCTION(0, "GPIOF12"),
STM32_FUNCTION(13, "FMC_A6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(93, "PF13"),
STM32_FUNCTION(0, "GPIOF13"),
STM32_FUNCTION(4, "DFSDM_DATIN6"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(13, "FMC_A7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(94, "PF14"),
STM32_FUNCTION(0, "GPIOF14"),
STM32_FUNCTION(4, "DFSDM_CKIN6"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_A8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(95, "PF15"),
STM32_FUNCTION(0, "GPIOF15"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_A9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(96, "PG0"),
STM32_FUNCTION(0, "GPIOG0"),
STM32_FUNCTION(13, "FMC_A10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(97, "PG1"),
STM32_FUNCTION(0, "GPIOG1"),
STM32_FUNCTION(13, "FMC_A11"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(98, "PG2"),
STM32_FUNCTION(0, "GPIOG2"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(12, "TIM8_BKIN_COMP12"),
STM32_FUNCTION(13, "FMC_A12"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(99, "PG3"),
STM32_FUNCTION(0, "GPIOG3"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(12, "TIM8_BKIN2_COMP12"),
STM32_FUNCTION(13, "FMC_A13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(100, "PG4"),
STM32_FUNCTION(0, "GPIOG4"),
STM32_FUNCTION(2, "TIM1_BKIN2"),
STM32_FUNCTION(12, "TIM1_BKIN2_COMP12"),
STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(101, "PG5"),
STM32_FUNCTION(0, "GPIOG5"),
STM32_FUNCTION(2, "TIM1_ETR"),
STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(102, "PG6"),
STM32_FUNCTION(0, "GPIOG6"),
STM32_FUNCTION(2, "TIM17_BKIN"),
STM32_FUNCTION(3, "HRTIM_CHE1"),
STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D12"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(103, "PG7"),
STM32_FUNCTION(0, "GPIOG7"),
STM32_FUNCTION(3, "HRTIM_CHE2"),
STM32_FUNCTION(7, "SAI1_MCLK_A"),
STM32_FUNCTION(8, "USART6_CK"),
STM32_FUNCTION(13, "FMC_INT"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(104, "PG8"),
STM32_FUNCTION(0, "GPIOG8"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI6_NSS"),
STM32_FUNCTION(8, "USART6_RTS"),
STM32_FUNCTION(9, "SPDIFRX_IN2"),
STM32_FUNCTION(12, "ETH_PPS_OUT"),
STM32_FUNCTION(13, "FMC_SDCLK"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(105, "PG9"),
STM32_FUNCTION(0, "GPIOG9"),
STM32_FUNCTION(6, "SPI1_MISO I2S1_SDI"),
STM32_FUNCTION(8, "USART6_RX"),
STM32_FUNCTION(9, "SPDIFRX_IN3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
STM32_FUNCTION(11, "SAI2_FS_B"),
STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(106, "PG10"),
STM32_FUNCTION(0, "GPIOG10"),
STM32_FUNCTION(3, "HRTIM_FLT5"),
STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(11, "SAI2_SD_B"),
STM32_FUNCTION(13, "FMC_NE3"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(107, "PG11"),
STM32_FUNCTION(0, "GPIOG11"),
STM32_FUNCTION(3, "HRTIM_EEV4"),
STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
STM32_FUNCTION(9, "SPDIFRX_IN0"),
STM32_FUNCTION(11, "SDMMC2_D2"),
STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(108, "PG12"),
STM32_FUNCTION(0, "GPIOG12"),
STM32_FUNCTION(2, "LPTIM1_IN1"),
STM32_FUNCTION(3, "HRTIM_EEV5"),
STM32_FUNCTION(6, "SPI6_MISO"),
STM32_FUNCTION(8, "USART6_RTS"),
STM32_FUNCTION(9, "SPDIFRX_IN1"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_NE4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(109, "PG13"),
STM32_FUNCTION(0, "GPIOG13"),
STM32_FUNCTION(1, "TRACED0"),
STM32_FUNCTION(2, "LPTIM1_OUT"),
STM32_FUNCTION(3, "HRTIM_EEV10"),
STM32_FUNCTION(6, "SPI6_SCK"),
STM32_FUNCTION(8, "USART6_CTS_NSS"),
STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
STM32_FUNCTION(13, "FMC_A24"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(110, "PG14"),
STM32_FUNCTION(0, "GPIOG14"),
STM32_FUNCTION(1, "TRACED1"),
STM32_FUNCTION(2, "LPTIM1_ETR"),
STM32_FUNCTION(6, "SPI6_MOSI"),
STM32_FUNCTION(8, "USART6_TX"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
STM32_FUNCTION(13, "FMC_A25"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(111, "PG15"),
STM32_FUNCTION(0, "GPIOG15"),
STM32_FUNCTION(8, "USART6_CTS_NSS"),
STM32_FUNCTION(13, "FMC_SDNCAS"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(112, "PH0"),
STM32_FUNCTION(0, "GPIOH0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(113, "PH1"),
STM32_FUNCTION(0, "GPIOH1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(114, "PH2"),
STM32_FUNCTION(0, "GPIOH2"),
STM32_FUNCTION(2, "LPTIM1_IN2"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
STM32_FUNCTION(11, "SAI2_SCK_B"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(13, "FMC_SDCKE0"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(115, "PH3"),
STM32_FUNCTION(0, "GPIOH3"),
STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
STM32_FUNCTION(11, "SAI2_MCK_B"),
STM32_FUNCTION(12, "ETH_MII_COL"),
STM32_FUNCTION(13, "FMC_SDNE0"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(116, "PH4"),
STM32_FUNCTION(0, "GPIOH4"),
STM32_FUNCTION(5, "I2C2_SCL"),
STM32_FUNCTION(10, "LCD_G5"),
STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(117, "PH5"),
STM32_FUNCTION(0, "GPIOH5"),
STM32_FUNCTION(5, "I2C2_SDA"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(13, "FMC_SDNWE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(118, "PH6"),
STM32_FUNCTION(0, "GPIOH6"),
STM32_FUNCTION(5, "I2C2_SMBA"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(12, "ETH_MII_RXD2"),
STM32_FUNCTION(13, "FMC_SDNE1"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(119, "PH7"),
STM32_FUNCTION(0, "GPIOH7"),
STM32_FUNCTION(5, "I2C3_SCL"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(12, "ETH_MII_RXD3"),
STM32_FUNCTION(13, "FMC_SDCKE1"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(120, "PH8"),
STM32_FUNCTION(0, "GPIOH8"),
STM32_FUNCTION(3, "TIM5_ETR"),
STM32_FUNCTION(5, "I2C3_SDA"),
STM32_FUNCTION(13, "FMC_D16"),
STM32_FUNCTION(14, "DCMI_HSYNC"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(121, "PH9"),
STM32_FUNCTION(0, "GPIOH9"),
STM32_FUNCTION(5, "I2C3_SMBA"),
STM32_FUNCTION(13, "FMC_D17"),
STM32_FUNCTION(14, "DCMI_D0"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(122, "PH10"),
STM32_FUNCTION(0, "GPIOH10"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(5, "I2C4_SMBA"),
STM32_FUNCTION(13, "FMC_D18"),
STM32_FUNCTION(14, "DCMI_D1"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(123, "PH11"),
STM32_FUNCTION(0, "GPIOH11"),
STM32_FUNCTION(3, "TIM5_CH2"),
STM32_FUNCTION(5, "I2C4_SCL"),
STM32_FUNCTION(13, "FMC_D19"),
STM32_FUNCTION(14, "DCMI_D2"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(124, "PH12"),
STM32_FUNCTION(0, "GPIOH12"),
STM32_FUNCTION(3, "TIM5_CH3"),
STM32_FUNCTION(5, "I2C4_SDA"),
STM32_FUNCTION(13, "FMC_D20"),
STM32_FUNCTION(14, "DCMI_D3"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(125, "PH13"),
STM32_FUNCTION(0, "GPIOH13"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(10, "CAN1_TX"),
STM32_FUNCTION(13, "FMC_D21"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(126, "PH14"),
STM32_FUNCTION(0, "GPIOH14"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D22"),
STM32_FUNCTION(14, "DCMI_D4"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(127, "PH15"),
STM32_FUNCTION(0, "GPIOH15"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(10, "CAN1_TXFD"),
STM32_FUNCTION(13, "FMC_D23"),
STM32_FUNCTION(14, "DCMI_D11"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(128, "PI0"),
STM32_FUNCTION(0, "GPIOI0"),
STM32_FUNCTION(3, "TIM5_CH4"),
STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
STM32_FUNCTION(10, "CAN1_RXFD"),
STM32_FUNCTION(13, "FMC_D24"),
STM32_FUNCTION(14, "DCMI_D13"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(129, "PI1"),
STM32_FUNCTION(0, "GPIOI1"),
STM32_FUNCTION(4, "TIM8_BKIN2"),
STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
STM32_FUNCTION(12, "TIM8_BKIN2_COMP12"),
STM32_FUNCTION(13, "FMC_D25"),
STM32_FUNCTION(14, "DCMI_D8"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(130, "PI2"),
STM32_FUNCTION(0, "GPIOI2"),
STM32_FUNCTION(4, "TIM8_CH4"),
STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
STM32_FUNCTION(13, "FMC_D26"),
STM32_FUNCTION(14, "DCMI_D9"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(131, "PI3"),
STM32_FUNCTION(0, "GPIOI3"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
STM32_FUNCTION(13, "FMC_D27"),
STM32_FUNCTION(14, "DCMI_D10"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(132, "PI4"),
STM32_FUNCTION(0, "GPIOI4"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "SAI2_MCK_A"),
STM32_FUNCTION(12, "TIM8_BKIN_COMP12"),
STM32_FUNCTION(13, "FMC_NBL2"),
STM32_FUNCTION(14, "DCMI_D5"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(133, "PI5"),
STM32_FUNCTION(0, "GPIOI5"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(11, "SAI2_SCK_A"),
STM32_FUNCTION(13, "FMC_NBL3"),
STM32_FUNCTION(14, "DCMI_VSYNC"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(134, "PI6"),
STM32_FUNCTION(0, "GPIOI6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(11, "SAI2_SD_A"),
STM32_FUNCTION(13, "FMC_D28"),
STM32_FUNCTION(14, "DCMI_D6"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(135, "PI7"),
STM32_FUNCTION(0, "GPIOI7"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(11, "SAI2_FS_A"),
STM32_FUNCTION(13, "FMC_D29"),
STM32_FUNCTION(14, "DCMI_D7"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(136, "PI8"),
STM32_FUNCTION(0, "GPIOI8"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(137, "PI9"),
STM32_FUNCTION(0, "GPIOI9"),
STM32_FUNCTION(9, "UART4_RX"),
STM32_FUNCTION(10, "CAN1_RX"),
STM32_FUNCTION(13, "FMC_D30"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(138, "PI10"),
STM32_FUNCTION(0, "GPIOI10"),
STM32_FUNCTION(10, "CAN1_RXFD"),
STM32_FUNCTION(12, "ETH_MII_RX_ER"),
STM32_FUNCTION(13, "FMC_D31"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(139, "PI11"),
STM32_FUNCTION(0, "GPIOI11"),
STM32_FUNCTION(10, "LCD_G6"),
STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(140, "PI12"),
STM32_FUNCTION(0, "GPIOI12"),
STM32_FUNCTION(12, "ETH_TX_ER"),
STM32_FUNCTION(15, "LCD_HSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(141, "PI13"),
STM32_FUNCTION(0, "GPIOI13"),
STM32_FUNCTION(15, "LCD_VSYNC"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(142, "PI14"),
STM32_FUNCTION(0, "GPIOI14"),
STM32_FUNCTION(15, "LCD_CLK"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(143, "PI15"),
STM32_FUNCTION(0, "GPIOI15"),
STM32_FUNCTION(10, "LCD_G2"),
STM32_FUNCTION(15, "LCD_R0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(144, "PJ0"),
STM32_FUNCTION(0, "GPIOJ0"),
STM32_FUNCTION(10, "LCD_R7"),
STM32_FUNCTION(15, "LCD_R1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(145, "PJ1"),
STM32_FUNCTION(0, "GPIOJ1"),
STM32_FUNCTION(15, "LCD_R2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(146, "PJ2"),
STM32_FUNCTION(0, "GPIOJ2"),
STM32_FUNCTION(14, "DSI_TE"),
STM32_FUNCTION(15, "LCD_R3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(147, "PJ3"),
STM32_FUNCTION(0, "GPIOJ3"),
STM32_FUNCTION(15, "LCD_R4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(148, "PJ4"),
STM32_FUNCTION(0, "GPIOJ4"),
STM32_FUNCTION(15, "LCD_R5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(149, "PJ5"),
STM32_FUNCTION(0, "GPIOJ5"),
STM32_FUNCTION(15, "LCD_R6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(150, "PJ6"),
STM32_FUNCTION(0, "GPIOJ6"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(15, "LCD_R7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(151, "PJ7"),
STM32_FUNCTION(0, "GPIOJ7"),
STM32_FUNCTION(1, "TRGIN"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(15, "LCD_G0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(152, "PJ8"),
STM32_FUNCTION(0, "GPIOJ8"),
STM32_FUNCTION(2, "TIM1_CH3N"),
STM32_FUNCTION(4, "TIM8_CH1"),
STM32_FUNCTION(9, "UART8_TX"),
STM32_FUNCTION(15, "LCD_G1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(153, "PJ9"),
STM32_FUNCTION(0, "GPIOJ9"),
STM32_FUNCTION(2, "TIM1_CH3"),
STM32_FUNCTION(4, "TIM8_CH1N"),
STM32_FUNCTION(9, "UART8_RX"),
STM32_FUNCTION(15, "LCD_G2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(154, "PJ10"),
STM32_FUNCTION(0, "GPIOJ10"),
STM32_FUNCTION(2, "TIM1_CH2N"),
STM32_FUNCTION(4, "TIM8_CH2"),
STM32_FUNCTION(6, "SPI5_MOSI"),
STM32_FUNCTION(15, "LCD_G3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(155, "PJ11"),
STM32_FUNCTION(0, "GPIOJ11"),
STM32_FUNCTION(2, "TIM1_CH2"),
STM32_FUNCTION(4, "TIM8_CH2N"),
STM32_FUNCTION(6, "SPI5_MISO"),
STM32_FUNCTION(15, "LCD_G4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(156, "PJ12"),
STM32_FUNCTION(0, "GPIOJ12"),
STM32_FUNCTION(1, "TRGOUT"),
STM32_FUNCTION(10, "LCD_G3"),
STM32_FUNCTION(15, "LCD_B0"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(157, "PJ13"),
STM32_FUNCTION(0, "GPIOJ13"),
STM32_FUNCTION(10, "LCD_B4"),
STM32_FUNCTION(15, "LCD_B1"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(158, "PJ14"),
STM32_FUNCTION(0, "GPIOJ14"),
STM32_FUNCTION(15, "LCD_B2"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(159, "PJ15"),
STM32_FUNCTION(0, "GPIOJ15"),
STM32_FUNCTION(15, "LCD_B3"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(160, "PK0"),
STM32_FUNCTION(0, "GPIOK0"),
STM32_FUNCTION(2, "TIM1_CH1N"),
STM32_FUNCTION(4, "TIM8_CH3"),
STM32_FUNCTION(6, "SPI5_SCK"),
STM32_FUNCTION(15, "LCD_G5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(161, "PK1"),
STM32_FUNCTION(0, "GPIOK1"),
STM32_FUNCTION(2, "TIM1_CH1"),
STM32_FUNCTION(4, "TIM8_CH3N"),
STM32_FUNCTION(6, "SPI5_NSS"),
STM32_FUNCTION(15, "LCD_G6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(162, "PK2"),
STM32_FUNCTION(0, "GPIOK2"),
STM32_FUNCTION(2, "TIM1_BKIN"),
STM32_FUNCTION(4, "TIM8_BKIN"),
STM32_FUNCTION(11, "TIM8_BKIN_COMP12"),
STM32_FUNCTION(12, "TIM1_BKIN_COMP12"),
STM32_FUNCTION(15, "LCD_G7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(163, "PK3"),
STM32_FUNCTION(0, "GPIOK3"),
STM32_FUNCTION(15, "LCD_B4"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(164, "PK4"),
STM32_FUNCTION(0, "GPIOK4"),
STM32_FUNCTION(15, "LCD_B5"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(165, "PK5"),
STM32_FUNCTION(0, "GPIOK5"),
STM32_FUNCTION(15, "LCD_B6"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(166, "PK6"),
STM32_FUNCTION(0, "GPIOK6"),
STM32_FUNCTION(15, "LCD_B7"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
STM32_PIN(
PINCTRL_PIN(167, "PK7"),
STM32_FUNCTION(0, "GPIOK7"),
STM32_FUNCTION(15, "LCD_DE"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
};
static struct stm32_pinctrl_match_data stm32h743_match_data = {
.pins = stm32h743_pins,
.npins = ARRAY_SIZE(stm32h743_pins),
};
static const struct of_device_id stm32h743_pctrl_match[] = {
{
.compatible = "st,stm32h743-pinctrl",
.data = &stm32h743_match_data,
},
{ }
};
static struct platform_driver stm32h743_pinctrl_driver = {
.probe = stm32_pctl_probe,
.driver = {
.name = "stm32h743-pinctrl",
.of_match_table = stm32h743_pctrl_match,
},
};
static int __init stm32h743_pinctrl_init(void)
{
return platform_driver_register(&stm32h743_pinctrl_driver);
}
arch_initcall(stm32h743_pinctrl_init);
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32h743.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
* Copyright (C) STMicroelectronics 2017
* Author: Maxime Coquelin <[email protected]>
*
* Heavily based on Mediatek's pinctrl driver
*/
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/hwspinlock.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "pinctrl-stm32.h"
#define STM32_GPIO_MODER 0x00
#define STM32_GPIO_TYPER 0x04
#define STM32_GPIO_SPEEDR 0x08
#define STM32_GPIO_PUPDR 0x0c
#define STM32_GPIO_IDR 0x10
#define STM32_GPIO_ODR 0x14
#define STM32_GPIO_BSRR 0x18
#define STM32_GPIO_LCKR 0x1c
#define STM32_GPIO_AFRL 0x20
#define STM32_GPIO_AFRH 0x24
#define STM32_GPIO_SECCFGR 0x30
/* custom bitfield to backup pin status */
#define STM32_GPIO_BKP_MODE_SHIFT 0
#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
#define STM32_GPIO_BKP_ALT_SHIFT 2
#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
#define STM32_GPIO_BKP_SPEED_SHIFT 6
#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
#define STM32_GPIO_BKP_PUPD_SHIFT 8
#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
#define STM32_GPIO_BKP_TYPE 10
#define STM32_GPIO_BKP_VAL 11
#define STM32_GPIO_PINS_PER_BANK 16
#define STM32_GPIO_IRQ_LINE 16
#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
#define HWSPNLCK_TIMEOUT 1000 /* usec */
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
"af5", "af6", "af7",
"af8", "af9", "af10",
"af11", "af12", "af13",
"af14", "af15", "analog",
};
struct stm32_pinctrl_group {
const char *name;
unsigned long config;
unsigned pin;
};
struct stm32_gpio_bank {
void __iomem *base;
struct clk *clk;
struct reset_control *rstc;
spinlock_t lock;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
struct fwnode_handle *fwnode;
struct irq_domain *domain;
u32 bank_nr;
u32 bank_ioport_nr;
u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
bool secure_control;
};
struct stm32_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
struct stm32_pinctrl_group *groups;
unsigned ngroups;
const char **grp_names;
struct stm32_gpio_bank *banks;
unsigned nbanks;
const struct stm32_pinctrl_match_data *match_data;
struct irq_domain *domain;
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
struct hwspinlock *hwlock;
struct stm32_desc_pin *pins;
u32 npins;
u32 pkg;
u16 irqmux_map;
spinlock_t irqmux_lock;
};
static inline int stm32_gpio_pin(int gpio)
{
return gpio % STM32_GPIO_PINS_PER_BANK;
}
static inline u32 stm32_gpio_get_mode(u32 function)
{
switch (function) {
case STM32_PIN_GPIO:
return 0;
case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
return 2;
case STM32_PIN_ANALOG:
return 3;
}
return 0;
}
static inline u32 stm32_gpio_get_alt(u32 function)
{
switch (function) {
case STM32_PIN_GPIO:
return 0;
case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
return function - 1;
case STM32_PIN_ANALOG:
return 0;
}
return 0;
}
static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
u32 offset, u32 value)
{
bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
}
static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
u32 mode, u32 alt)
{
bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
STM32_GPIO_BKP_ALT_MASK);
bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
}
static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
u32 drive)
{
bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
}
static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
u32 speed)
{
bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
}
static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
u32 bias)
{
bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
}
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
unsigned offset, int value)
{
stm32_gpio_backup_value(bank, offset, value);
if (!value)
offset += STM32_GPIO_PINS_PER_BANK;
writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
}
static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
struct pinctrl_gpio_range *range;
int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
if (!range) {
dev_err(pctl->dev, "pin %d not in range.\n", pin);
return -EINVAL;
}
return pinctrl_gpio_request(chip->base + offset);
}
static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
{
pinctrl_gpio_free(chip->base + offset);
}
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
}
static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
}
static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int stm32_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
pinctrl_gpio_direction_output(chip->base + offset);
return 0;
}
static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
struct irq_fwspec fwspec;
fwspec.fwnode = bank->fwnode;
fwspec.param_count = 2;
fwspec.param[0] = offset;
fwspec.param[1] = IRQ_TYPE_NONE;
return irq_create_fwspec_mapping(&fwspec);
}
static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
int pin = stm32_gpio_pin(offset);
int ret;
u32 mode, alt;
stm32_pmx_get_mode(bank, pin, &mode, &alt);
if ((alt == 0) && (mode == 0))
ret = GPIO_LINE_DIRECTION_IN;
else if ((alt == 0) && (mode == 1))
ret = GPIO_LINE_DIRECTION_OUT;
else
ret = -EINVAL;
return ret;
}
static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned int i;
u32 sec;
/* All gpio are valid per default */
bitmap_fill(valid_mask, ngpios);
if (bank->secure_control) {
/* Tag secured pins as invalid */
sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
for (i = 0; i < ngpios; i++) {
if (sec & BIT(i)) {
clear_bit(i, valid_mask);
dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
}
}
}
return 0;
}
static const struct gpio_chip stm32_gpio_template = {
.request = stm32_gpio_request,
.free = stm32_gpio_free,
.get = stm32_gpio_get,
.set = stm32_gpio_set,
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
.get_direction = stm32_gpio_get_direction,
.set_config = gpiochip_generic_config,
.init_valid_mask = stm32_gpio_init_valid_mask,
};
static void stm32_gpio_irq_trigger(struct irq_data *d)
{
struct stm32_gpio_bank *bank = d->domain->host_data;
int level;
/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
return;
/* If level interrupt type then retrig */
level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
(level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
irq_chip_retrigger_hierarchy(d);
}
static void stm32_gpio_irq_eoi(struct irq_data *d)
{
irq_chip_eoi_parent(d);
stm32_gpio_irq_trigger(d);
};
static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
{
struct stm32_gpio_bank *bank = d->domain->host_data;
u32 parent_type;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
parent_type = type;
break;
case IRQ_TYPE_LEVEL_HIGH:
parent_type = IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_LEVEL_LOW:
parent_type = IRQ_TYPE_EDGE_FALLING;
break;
default:
return -EINVAL;
}
bank->irq_type[d->hwirq] = type;
return irq_chip_set_type_parent(d, parent_type);
};
static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
{
struct stm32_gpio_bank *bank = irq_data->domain->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
int ret;
ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
if (ret)
return ret;
ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
if (ret) {
dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
irq_data->hwirq);
return ret;
}
return 0;
}
static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
{
struct stm32_gpio_bank *bank = irq_data->domain->host_data;
gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
}
static void stm32_gpio_irq_unmask(struct irq_data *d)
{
irq_chip_unmask_parent(d);
stm32_gpio_irq_trigger(d);
}
static struct irq_chip stm32_gpio_irq_chip = {
.name = "stm32gpio",
.irq_eoi = stm32_gpio_irq_eoi,
.irq_ack = irq_chip_ack_parent,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = stm32_gpio_irq_unmask,
.irq_set_type = stm32_gpio_set_type,
.irq_set_wake = irq_chip_set_wake_parent,
.irq_request_resources = stm32_gpio_irq_request_resources,
.irq_release_resources = stm32_gpio_irq_release_resources,
};
static int stm32_gpio_domain_translate(struct irq_domain *d,
struct irq_fwspec *fwspec,
unsigned long *hwirq,
unsigned int *type)
{
if ((fwspec->param_count != 2) ||
(fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
return -EINVAL;
*hwirq = fwspec->param[0];
*type = fwspec->param[1];
return 0;
}
static int stm32_gpio_domain_activate(struct irq_domain *d,
struct irq_data *irq_data, bool reserve)
{
struct stm32_gpio_bank *bank = d->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
int ret = 0;
if (pctl->hwlock) {
ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
HWSPNLCK_TIMEOUT);
if (ret) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
return ret;
}
}
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
if (pctl->hwlock)
hwspin_unlock_in_atomic(pctl->hwlock);
return ret;
}
static int stm32_gpio_domain_alloc(struct irq_domain *d,
unsigned int virq,
unsigned int nr_irqs, void *data)
{
struct stm32_gpio_bank *bank = d->host_data;
struct irq_fwspec *fwspec = data;
struct irq_fwspec parent_fwspec;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
irq_hw_number_t hwirq = fwspec->param[0];
unsigned long flags;
int ret = 0;
/*
* Check first that the IRQ MUX of that line is free.
* gpio irq mux is shared between several banks, protect with a lock
*/
spin_lock_irqsave(&pctl->irqmux_lock, flags);
if (pctl->irqmux_map & BIT(hwirq)) {
dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
ret = -EBUSY;
} else {
pctl->irqmux_map |= BIT(hwirq);
}
spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
if (ret)
return ret;
parent_fwspec.fwnode = d->parent->fwnode;
parent_fwspec.param_count = 2;
parent_fwspec.param[0] = fwspec->param[0];
parent_fwspec.param[1] = fwspec->param[1];
irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
bank);
return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
}
static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
unsigned int nr_irqs)
{
struct stm32_gpio_bank *bank = d->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
unsigned long flags, hwirq = irq_data->hwirq;
irq_domain_free_irqs_common(d, virq, nr_irqs);
spin_lock_irqsave(&pctl->irqmux_lock, flags);
pctl->irqmux_map &= ~BIT(hwirq);
spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
}
static const struct irq_domain_ops stm32_gpio_domain_ops = {
.translate = stm32_gpio_domain_translate,
.alloc = stm32_gpio_domain_alloc,
.free = stm32_gpio_domain_free,
.activate = stm32_gpio_domain_activate,
};
/* Pinctrl functions */
static struct stm32_pinctrl_group *
stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
{
int i;
for (i = 0; i < pctl->ngroups; i++) {
struct stm32_pinctrl_group *grp = pctl->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
u32 pin_num, u32 fnum)
{
int i, k;
for (i = 0; i < pctl->npins; i++) {
const struct stm32_desc_pin *pin = pctl->pins + i;
const struct stm32_desc_function *func = pin->functions;
if (pin->pin.number != pin_num)
continue;
for (k = 0; k < STM32_CONFIG_NUM; k++) {
if (func->num == fnum)
return true;
func++;
}
break;
}
dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
return false;
}
static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps)
{
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
return -EINVAL;
(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct stm32_pinctrl *pctl;
struct stm32_pinctrl_group *grp;
struct property *pins;
u32 pinfunc, pin, func;
unsigned long *configs;
unsigned int num_configs;
bool has_config = 0;
unsigned reserve = 0;
int num_pins, num_funcs, maps_per_pin, i, err = 0;
pctl = pinctrl_dev_get_drvdata(pctldev);
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = 1;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin) {
err = -EINVAL;
goto exit;
}
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps, num_maps, reserve);
if (err)
goto exit;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux",
i, &pinfunc);
if (err)
goto exit;
pin = STM32_GET_PIN_NO(pinfunc);
func = STM32_GET_PIN_FUNC(pinfunc);
if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
err = -EINVAL;
goto exit;
}
grp = stm32_pctrl_find_group_by_pin(pctl, pin);
if (!grp) {
dev_err(pctl->dev, "unable to match pin %d to group\n",
pin);
err = -EINVAL;
goto exit;
}
err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
reserved_maps, num_maps);
if (err)
goto exit;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, grp->name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err)
goto exit;
}
}
exit:
kfree(configs);
return err;
}
static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
struct device_node *np;
unsigned reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node(np_config, np) {
ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
return 0;
}
static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops stm32_pctrl_ops = {
.dt_node_to_map = stm32_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
.get_groups_count = stm32_pctrl_get_groups_count,
.get_group_name = stm32_pctrl_get_group_name,
.get_group_pins = stm32_pctrl_get_group_pins,
};
/* Pinmux functions */
static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(stm32_gpio_functions);
}
static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return stm32_gpio_functions[selector];
}
static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->grp_names;
*num_groups = pctl->ngroups;
return 0;
}
static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
int err = 0;
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
HWSPNLCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
}
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
writel_relaxed(val, bank->base + alt_offset);
val = readl_relaxed(bank->base + STM32_GPIO_MODER);
val &= ~GENMASK(pin * 2 + 1, pin * 2);
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
if (pctl->hwlock)
hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_mode(bank, pin, mode, alt);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
return err;
}
void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
u32 *alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + alt_offset);
val &= GENMASK(alt_shift + 3, alt_shift);
*alt = val >> alt_shift;
val = readl_relaxed(bank->base + STM32_GPIO_MODER);
val &= GENMASK(pin * 2 + 1, pin * 2);
*mode = val >> (pin * 2);
spin_unlock_irqrestore(&bank->lock, flags);
}
static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
bool ret;
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct stm32_pinctrl_group *g = pctl->groups + group;
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
u32 mode, alt;
int pin;
ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
if (!ret)
return -EINVAL;
range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
}
bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
mode = stm32_gpio_get_mode(function);
alt = stm32_gpio_get_alt(function);
return stm32_pmx_set_mode(bank, pin, mode, alt);
}
static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned gpio,
bool input)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
int pin = stm32_gpio_pin(gpio);
return stm32_pmx_set_mode(bank, pin, !input, 0);
}
static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_gpio_range *range;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
}
if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
return -EACCES;
}
return 0;
}
static const struct pinmux_ops stm32_pmx_ops = {
.get_functions_count = stm32_pmx_get_funcs_cnt,
.get_function_name = stm32_pmx_get_func_name,
.get_function_groups = stm32_pmx_get_func_groups,
.set_mux = stm32_pmx_set_mux,
.gpio_set_direction = stm32_pmx_gpio_set_direction,
.request = stm32_pmx_request,
.strict = true,
};
/* Pinconf functions */
static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
HWSPNLCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
}
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
if (pctl->hwlock)
hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_driving(bank, offset, drive);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
return err;
}
static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
unsigned int offset)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= BIT(offset);
spin_unlock_irqrestore(&bank->lock, flags);
return (val >> offset);
}
static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
HWSPNLCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
}
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
if (pctl->hwlock)
hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_speed(bank, offset, speed);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
return err;
}
static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
unsigned int offset)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
spin_unlock_irqrestore(&bank->lock, flags);
return (val >> (offset * 2));
}
static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
HWSPNLCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
}
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= bias << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
if (pctl->hwlock)
hwspin_unlock_in_atomic(pctl->hwlock);
stm32_gpio_backup_bias(bank, offset, bias);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
return err;
}
static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
unsigned int offset)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
spin_unlock_irqrestore(&bank->lock, flags);
return (val >> (offset * 2));
}
static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
unsigned int offset, bool dir)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&bank->lock, flags);
if (dir)
val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
BIT(offset));
else
val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
BIT(offset));
spin_unlock_irqrestore(&bank->lock, flags);
return val;
}
static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset, ret = 0;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
}
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
if (!gpiochip_line_is_valid(range->gc, offset)) {
dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
return -EACCES;
}
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
ret = stm32_pconf_set_driving(bank, offset, 0);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
ret = stm32_pconf_set_driving(bank, offset, 1);
break;
case PIN_CONFIG_SLEW_RATE:
ret = stm32_pconf_set_speed(bank, offset, arg);
break;
case PIN_CONFIG_BIAS_DISABLE:
ret = stm32_pconf_set_bias(bank, offset, 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = stm32_pconf_set_bias(bank, offset, 1);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = stm32_pconf_set_bias(bank, offset, 2);
break;
case PIN_CONFIG_OUTPUT:
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
default:
ret = -ENOTSUPP;
}
return ret;
}
static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *config)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*config = pctl->groups[group].config;
return 0;
}
static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct stm32_pinctrl_group *g = &pctl->groups[group];
int i, ret;
for (i = 0; i < num_configs; i++) {
mutex_lock(&pctldev->mutex);
ret = stm32_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
mutex_unlock(&pctldev->mutex);
if (ret < 0)
return ret;
g->config = configs[i];
}
return 0;
}
static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = stm32_pconf_parse_conf(pctldev, pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
}
return 0;
}
static struct stm32_desc_pin *
stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
unsigned int pin_number)
{
struct stm32_desc_pin *pins = pctl->pins;
int i;
for (i = 0; i < pctl->npins; i++) {
if (pins->pin.number == pin_number)
return pins;
pins++;
}
return NULL;
}
static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct stm32_desc_pin *pin_desc;
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset;
u32 mode, alt, drive, speed, bias;
static const char * const modes[] = {
"input", "output", "alternate", "analog" };
static const char * const speeds[] = {
"low", "medium", "high", "very high" };
static const char * const biasing[] = {
"floating", "pull up", "pull down", "" };
bool val;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range)
return;
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
if (!gpiochip_line_is_valid(range->gc, offset)) {
seq_puts(s, "NO ACCESS");
return;
}
stm32_pmx_get_mode(bank, offset, &mode, &alt);
bias = stm32_pconf_get_bias(bank, offset);
seq_printf(s, "%s ", modes[mode]);
switch (mode) {
/* input */
case 0:
val = stm32_pconf_get(bank, offset, true);
seq_printf(s, "- %s - %s",
val ? "high" : "low",
biasing[bias]);
break;
/* output */
case 1:
drive = stm32_pconf_get_driving(bank, offset);
speed = stm32_pconf_get_speed(bank, offset);
val = stm32_pconf_get(bank, offset, false);
seq_printf(s, "- %s - %s - %s - %s %s",
val ? "high" : "low",
drive ? "open drain" : "push pull",
biasing[bias],
speeds[speed], "speed");
break;
/* alternate */
case 2:
drive = stm32_pconf_get_driving(bank, offset);
speed = stm32_pconf_get_speed(bank, offset);
pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
if (!pin_desc)
return;
seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
pin_desc->functions[alt + 1].name,
drive ? "open drain" : "push pull",
biasing[bias],
speeds[speed], "speed");
break;
/* analog */
case 3:
break;
}
}
static const struct pinconf_ops stm32_pconf_ops = {
.pin_config_group_get = stm32_pconf_group_get,
.pin_config_group_set = stm32_pconf_group_set,
.pin_config_set = stm32_pconf_set,
.pin_config_dbg_show = stm32_pconf_dbg_show,
};
static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
struct stm32_gpio_bank *bank,
unsigned int offset)
{
unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
struct stm32_desc_pin *pin_desc;
int i;
/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
pin_desc = pctl->pins + stm32_pin_nb;
if (pin_desc->pin.number == stm32_pin_nb)
return pin_desc;
/* Otherwise, loop all array to find the pin with the right number */
for (i = 0; i < pctl->npins; i++) {
pin_desc = pctl->pins + i;
if (pin_desc->pin.number == stm32_pin_nb)
return pin_desc;
}
return NULL;
}
static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
{
struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
int bank_ioport_nr;
struct pinctrl_gpio_range *range = &bank->range;
struct fwnode_reference_args args;
struct device *dev = pctl->dev;
struct resource res;
int npins = STM32_GPIO_PINS_PER_BANK;
int bank_nr, err, i = 0;
struct stm32_desc_pin *stm32_pin;
char **names;
if (!IS_ERR(bank->rstc))
reset_control_deassert(bank->rstc);
if (of_address_to_resource(to_of_node(fwnode), 0, &res))
return -ENODEV;
bank->base = devm_ioremap_resource(dev, &res);
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
err = clk_prepare_enable(bank->clk);
if (err) {
dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
return err;
}
bank->gpio_chip = stm32_gpio_template;
fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip.base = args.args[1];
/* get the last defined gpio line (offset + nb of pins) */
npins = args.args[0] + args.args[2];
while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
npins = max(npins, (int)(args.args[0] + args.args[2]));
} else {
bank_nr = pctl->nbanks;
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
range->name = bank->gpio_chip.label;
range->id = bank_nr;
range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
range->base = range->id * STM32_GPIO_PINS_PER_BANK;
range->npins = npins;
range->gc = &bank->gpio_chip;
pinctrl_add_gpio_range(pctl->pctl_dev,
&pctl->banks[bank_nr].range);
}
if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
bank_ioport_nr = bank_nr;
bank->gpio_chip.base = -1;
bank->gpio_chip.ngpio = npins;
bank->gpio_chip.fwnode = fwnode;
bank->gpio_chip.parent = dev;
bank->bank_nr = bank_nr;
bank->bank_ioport_nr = bank_ioport_nr;
bank->secure_control = pctl->match_data->secure_control;
spin_lock_init(&bank->lock);
if (pctl->domain) {
/* create irq hierarchical domain */
bank->fwnode = fwnode;
bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
bank->fwnode, &stm32_gpio_domain_ops,
bank);
if (!bank->domain) {
err = -ENODEV;
goto err_clk;
}
}
names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
for (i = 0; i < npins; i++) {
stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
if (stm32_pin && stm32_pin->pin.name)
names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
else
names[i] = NULL;
}
bank->gpio_chip.names = (const char * const *)names;
err = gpiochip_add_data(&bank->gpio_chip, bank);
if (err) {
dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
goto err_clk;
}
dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
return 0;
err_clk:
clk_disable_unprepare(bank->clk);
return err;
}
static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *parent;
struct irq_domain *domain;
if (!of_property_present(np, "interrupt-parent"))
return NULL;
parent = of_irq_find_parent(np);
if (!parent)
return ERR_PTR(-ENXIO);
domain = irq_find_host(parent);
of_node_put(parent);
if (!domain)
/* domain not registered yet */
return ERR_PTR(-EPROBE_DEFER);
return domain;
}
static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
struct stm32_pinctrl *pctl)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct regmap *rm;
int offset, ret, i;
int mask, mask_width;
pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(pctl->regmap))
return PTR_ERR(pctl->regmap);
rm = pctl->regmap;
ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
if (ret)
return ret;
ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
if (ret)
mask = SYSCFG_IRQMUX_MASK;
mask_width = fls(mask);
for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
struct reg_field mux;
mux.reg = offset + (i / 4) * 4;
mux.lsb = (i % 4) * mask_width;
mux.msb = mux.lsb + mask_width - 1;
dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
i, mux.reg, mux.lsb, mux.msb);
pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
if (IS_ERR(pctl->irqmux[i]))
return PTR_ERR(pctl->irqmux[i]);
}
return 0;
}
static int stm32_pctrl_build_state(struct platform_device *pdev)
{
struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
int i;
pctl->ngroups = pctl->npins;
/* Allocate groups */
pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->groups), GFP_KERNEL);
if (!pctl->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->grp_names), GFP_KERNEL);
if (!pctl->grp_names)
return -ENOMEM;
for (i = 0; i < pctl->npins; i++) {
const struct stm32_desc_pin *pin = pctl->pins + i;
struct stm32_pinctrl_group *group = pctl->groups + i;
group->name = pin->pin.name;
group->pin = pin->pin.number;
pctl->grp_names[i] = pin->pin.name;
}
return 0;
}
static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
struct stm32_desc_pin *pins)
{
const struct stm32_desc_pin *p;
int i, nb_pins_available = 0;
for (i = 0; i < pctl->match_data->npins; i++) {
p = pctl->match_data->pins + i;
if (pctl->pkg && !(pctl->pkg & p->pkg))
continue;
pins->pin = p->pin;
memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
pins++;
nb_pins_available++;
}
pctl->npins = nb_pins_available;
return 0;
}
int stm32_pctl_probe(struct platform_device *pdev)
{
const struct stm32_pinctrl_match_data *match_data;
struct fwnode_handle *child;
struct device *dev = &pdev->dev;
struct stm32_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
int i, ret, hwlock_id;
unsigned int banks;
match_data = device_get_match_data(dev);
if (!match_data)
return -EINVAL;
pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
/* check for IRQ controller (may require deferred probe) */
pctl->domain = stm32_pctrl_get_irq_domain(pdev);
if (IS_ERR(pctl->domain))
return PTR_ERR(pctl->domain);
if (!pctl->domain)
dev_warn(dev, "pinctrl without interrupt support\n");
/* hwspinlock is optional */
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
if (hwlock_id < 0) {
if (hwlock_id == -EPROBE_DEFER)
return hwlock_id;
} else {
pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
}
spin_lock_init(&pctl->irqmux_lock);
pctl->dev = dev;
pctl->match_data = match_data;
/* get optional package information */
if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
sizeof(*pctl->pins), GFP_KERNEL);
if (!pctl->pins)
return -ENOMEM;
ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
if (ret)
return ret;
ret = stm32_pctrl_build_state(pdev);
if (ret) {
dev_err(dev, "build state failed: %d\n", ret);
return -EINVAL;
}
if (pctl->domain) {
ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
if (ret)
return ret;
}
pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < pctl->npins; i++)
pins[i] = pctl->pins[i].pin;
pctl->pctl_desc.name = dev_name(&pdev->dev);
pctl->pctl_desc.owner = THIS_MODULE;
pctl->pctl_desc.pins = pins;
pctl->pctl_desc.npins = pctl->npins;
pctl->pctl_desc.link_consumers = true;
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
pctl->dev = &pdev->dev;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
pctl);
if (IS_ERR(pctl->pctl_dev)) {
dev_err(&pdev->dev, "Failed pinctrl registration\n");
return PTR_ERR(pctl->pctl_dev);
}
banks = gpiochip_node_count(dev);
if (!banks) {
dev_err(dev, "at least one GPIO bank is required\n");
return -EINVAL;
}
pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
GFP_KERNEL);
if (!pctl->banks)
return -ENOMEM;
i = 0;
for_each_gpiochip_node(dev, child) {
struct stm32_gpio_bank *bank = &pctl->banks[i];
struct device_node *np = to_of_node(child);
bank->rstc = of_reset_control_get_exclusive(np, NULL);
if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
fwnode_handle_put(child);
return -EPROBE_DEFER;
}
bank->clk = of_clk_get_by_name(np, NULL);
if (IS_ERR(bank->clk)) {
fwnode_handle_put(child);
return dev_err_probe(dev, PTR_ERR(bank->clk),
"failed to get clk\n");
}
i++;
}
for_each_gpiochip_node(dev, child) {
ret = stm32_gpiolib_register_bank(pctl, child);
if (ret) {
fwnode_handle_put(child);
for (i = 0; i < pctl->nbanks; i++)
clk_disable_unprepare(pctl->banks[i].clk);
return ret;
}
pctl->nbanks++;
}
dev_info(dev, "Pinctrl STM32 initialized\n");
return 0;
}
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
struct stm32_pinctrl *pctl, u32 pin)
{
const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
u32 val, alt, mode, offset = stm32_gpio_pin(pin);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
bool pin_is_irq;
int ret;
range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
if (!range)
return 0;
if (!gpiochip_line_is_valid(range->gc, offset))
return 0;
pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
if (!desc || (!pin_is_irq && !desc->gpio_owner))
return 0;
bank = gpiochip_get_data(range->gc);
alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
alt >>= STM32_GPIO_BKP_ALT_SHIFT;
mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
mode >>= STM32_GPIO_BKP_MODE_SHIFT;
ret = stm32_pmx_set_mode(bank, offset, mode, alt);
if (ret)
return ret;
if (mode == 1) {
val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
val = val >> STM32_GPIO_BKP_VAL;
__stm32_gpio_set(bank, offset, val);
}
val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
val >>= STM32_GPIO_BKP_TYPE;
ret = stm32_pconf_set_driving(bank, offset, val);
if (ret)
return ret;
val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
val >>= STM32_GPIO_BKP_SPEED_SHIFT;
ret = stm32_pconf_set_speed(bank, offset, val);
if (ret)
return ret;
val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
val >>= STM32_GPIO_BKP_PUPD_SHIFT;
ret = stm32_pconf_set_bias(bank, offset, val);
if (ret)
return ret;
if (pin_is_irq)
regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
return 0;
}
int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
int i;
for (i = 0; i < pctl->nbanks; i++)
clk_disable(pctl->banks[i].clk);
return 0;
}
int __maybe_unused stm32_pinctrl_resume(struct device *dev)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
struct stm32_pinctrl_group *g = pctl->groups;
int i;
for (i = 0; i < pctl->nbanks; i++)
clk_enable(pctl->banks[i].clk);
for (i = 0; i < pctl->ngroups; i++, g++)
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
return 0;
}
|
linux-master
|
drivers/pinctrl/stm32/pinctrl-stm32.c
|
/*
* Allwinner a83t SoCs pinctrl driver.
*
* Copyright (C) 2015 Vishnu Patekar <[email protected]>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "tdm"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm")), /* PWM */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x4, "ccir")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x4, "ccir")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x4, "ccir")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x4, "ccir")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x4, "ccir")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x4, "ccir")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "ccir")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "ccir")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
SUNXI_FUNCTION(0x4, "ccir")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
SUNXI_FUNCTION(0x4, "ccir")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif")), /* DOUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION(0x3, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */
};
static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
.pins = sun8i_a83t_pins,
.npins = ARRAY_SIZE(sun8i_a83t_pins),
.irq_banks = 3,
};
static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_a83t_pinctrl_data);
}
static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-a83t-pinctrl", },
{}
};
static struct platform_driver sun8i_a83t_pinctrl_driver = {
.probe = sun8i_a83t_pinctrl_probe,
.driver = {
.name = "sun8i-a83t-pinctrl",
.of_match_table = sun8i_a83t_pinctrl_match,
},
};
builtin_platform_driver(sun8i_a83t_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner H6 SoC pinctrl driver.
*
* Copyright (C) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin h6_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x2, "ccir"), /* DE */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
SUNXI_FUNCTION(0x2, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION(0x4, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION(0x4, "spi0")), /* WP */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
SUNXI_FUNCTION(0x4, "csi"), /* PCLK */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
SUNXI_FUNCTION(0x4, "csi"), /* MCLK */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */
SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
SUNXI_FUNCTION(0x4, "csi"), /* D0 */
SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
SUNXI_FUNCTION(0x4, "csi"), /* D1 */
SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
SUNXI_FUNCTION(0x4, "csi"), /* D2 */
SUNXI_FUNCTION(0x5, "emac")), /* ENULL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
SUNXI_FUNCTION(0x4, "csi"), /* D3 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
SUNXI_FUNCTION(0x4, "csi"), /* D4 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
SUNXI_FUNCTION(0x4, "csi"), /* D5 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
SUNXI_FUNCTION(0x4, "csi"), /* D6 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
SUNXI_FUNCTION(0x4, "csi"), /* D7 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "ts1"), /* CLK */
SUNXI_FUNCTION(0x4, "csi"), /* SCK */
SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "ts1"), /* ERR */
SUNXI_FUNCTION(0x4, "csi"), /* SDA */
SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */
SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION(0x5, "csi")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x5, "csi")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "ts1"), /* D0 */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "ts2"), /* CLK */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "ts2"), /* ERR */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION(0x5, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts2"), /* D0 */
SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
SUNXI_FUNCTION(0x3, "ts3"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x3, "ts3"), /* ERR */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION(0x5, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "ts3"), /* D0 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION(0x5, "jtag")), /* DI */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */
SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */
SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */
SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */
SUNXI_FUNCTION(0x4, "sim0"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */
SUNXI_FUNCTION(0x4, "sim0"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */
SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */
SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir_tx"),
SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */
SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */
SUNXI_FUNCTION(0x5, "sim1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */
SUNXI_FUNCTION(0x5, "sim1"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "sim1"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "spdif"), /* IN */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "sim1"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
};
static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.pins = h6_pins,
.npins = ARRAY_SIZE(h6_pins),
.irq_banks = 4,
.irq_bank_map = h6_irq_bank_map,
.irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
static int h6_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&h6_pinctrl_data);
}
static const struct of_device_id h6_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h6-pinctrl", },
{}
};
static struct platform_driver h6_pinctrl_driver = {
.probe = h6_pinctrl_probe,
.driver = {
.name = "sun50i-h6-pinctrl",
.of_match_table = h6_pinctrl_match,
},
};
builtin_platform_driver(h6_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner D1 SoC pinctrl driver.
*
* Copyright (c) 2020 [email protected]
* Copyright (c) 2021-2022 Samuel Holland <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin d1_pins[] = {
/* PB */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm3"),
SUNXI_FUNCTION(0x3, "ir"), /* TX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* WP */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x7, "uart2"), /* TX */
SUNXI_FUNCTION(0x8, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm4"),
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT3 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN3 */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x7, "uart2"), /* RX */
SUNXI_FUNCTION(0x8, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT2 */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x7, "uart4"), /* TX */
SUNXI_FUNCTION(0x8, "can0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x7, "uart4"), /* RX */
SUNXI_FUNCTION(0x8, "can0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x7, "uart5"), /* TX */
SUNXI_FUNCTION(0x8, "can1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "pwm0"),
SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x7, "uart5"), /* RX */
SUNXI_FUNCTION(0x8, "can1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION(0x6, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x7, "uart3"), /* TX */
SUNXI_FUNCTION(0x8, "bist0"), /* BIST_RESULT0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION(0x6, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x7, "uart3"), /* RX */
SUNXI_FUNCTION(0x8, "bist1"), /* BIST_RESULT1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x3, "pwm5"),
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* HOLD */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x7, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x3, "pwm6"),
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "spi1"), /* MISO */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x7, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x3, "pwm7"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x7, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x3, "pwm2"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "spi1"), /* CLK */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x7, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* CLK */
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION(0x4, "spdif"), /* IN */
SUNXI_FUNCTION(0x5, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x6, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x7, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 12)),
/* PC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "ledc"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
SUNXI_FUNCTION(0x4, "boot"), /* SEL0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION(0x4, "boot"), /* SEL1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* WP */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x6, "pll"), /* DBG-CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* HOLD */
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 1, 7)),
/* PD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V0P */
SUNXI_FUNCTION(0x4, "dsi"), /* D0P */
SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V0N */
SUNXI_FUNCTION(0x4, "dsi"), /* D0N */
SUNXI_FUNCTION(0x5, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V1P */
SUNXI_FUNCTION(0x4, "dsi"), /* D1P */
SUNXI_FUNCTION(0x5, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V1N */
SUNXI_FUNCTION(0x4, "dsi"), /* D1N */
SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V2P */
SUNXI_FUNCTION(0x4, "dsi"), /* CKP */
SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V2N */
SUNXI_FUNCTION(0x4, "dsi"), /* CKN */
SUNXI_FUNCTION(0x5, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */
SUNXI_FUNCTION(0x4, "dsi"), /* D2P */
SUNXI_FUNCTION(0x5, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */
SUNXI_FUNCTION(0x4, "dsi"), /* D2N */
SUNXI_FUNCTION(0x5, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V3P */
SUNXI_FUNCTION(0x4, "dsi"), /* D3P */
SUNXI_FUNCTION(0x5, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "lvds0"), /* V3N */
SUNXI_FUNCTION(0x4, "dsi"), /* D3N */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V0P */
SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V0N */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V1P */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V1N */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION(0x5, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V2P */
SUNXI_FUNCTION(0x4, "spi1"), /* HOLD */
SUNXI_FUNCTION(0x5, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds1"), /* V2N */
SUNXI_FUNCTION(0x4, "spi1"), /* WP */
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x5, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds1"), /* V3P */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x5, "pwm2"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds1"), /* V3N */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x5, "pwm3"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION(0x5, "pwm4"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION(0x5, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 21)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION(0x3, "ir"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION(0x5, "pwm7"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 2, 22)),
/* PE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x8, "emac"), /* RXCTL/CRS_DV */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x8, "emac"), /* RXD0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* PCLK */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "uart0"), /* TX */
SUNXI_FUNCTION(0x8, "emac"), /* RXD1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* MCLK */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "uart0"), /* RX */
SUNXI_FUNCTION(0x8, "emac"), /* TXCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D0 */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "d_jtag"), /* MS */
SUNXI_FUNCTION(0x7, "r_jtag"), /* MS */
SUNXI_FUNCTION(0x8, "emac"), /* TXD0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D1 */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "ledc"),
SUNXI_FUNCTION(0x6, "d_jtag"), /* DI */
SUNXI_FUNCTION(0x7, "r_jtag"), /* DI */
SUNXI_FUNCTION(0x8, "emac"), /* TXD1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D2 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x5, "spdif"), /* IN */
SUNXI_FUNCTION(0x6, "d_jtag"), /* DO */
SUNXI_FUNCTION(0x7, "r_jtag"), /* DO */
SUNXI_FUNCTION(0x8, "emac"), /* TXCTL/TXEN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
SUNXI_FUNCTION(0x6, "d_jtag"), /* CK */
SUNXI_FUNCTION(0x7, "r_jtag"), /* CK */
SUNXI_FUNCTION(0x8, "emac"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D4 */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION(0x4, "pwm2"),
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION(0x6, "jtag"), /* MS */
SUNXI_FUNCTION(0x8, "emac"), /* MDC */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D5 */
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION(0x4, "pwm3"),
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION(0x6, "jtag"), /* DI */
SUNXI_FUNCTION(0x8, "emac"), /* MDIO */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D6 */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION(0x4, "pwm4"),
SUNXI_FUNCTION(0x5, "ir"), /* RX */
SUNXI_FUNCTION(0x6, "jtag"), /* DO */
SUNXI_FUNCTION(0x8, "emac"), /* EPHY-25M */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ncsi0"), /* D7 */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT3 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN3 */
SUNXI_FUNCTION(0x6, "jtag"), /* CK */
SUNXI_FUNCTION(0x8, "emac"), /* TXD2 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x3, "ncsi0"), /* FIELD */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT2 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN2 */
SUNXI_FUNCTION(0x8, "emac"), /* TXD3 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x3, "pwm5"),
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x8, "emac"), /* RXD2 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "d_jtag"), /* MS */
SUNXI_FUNCTION(0x4, "i2s0_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x5, "i2s0_din"), /* DIN0 */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x8, "emac"), /* RXD3 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "d_jtag"), /* DI */
SUNXI_FUNCTION(0x4, "pwm6"),
SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x8, "emac"), /* RXCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x3, "d_jtag"), /* DO */
SUNXI_FUNCTION(0x4, "pwm7"),
SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x6, "dmic"), /* DATA0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x3, "d_jtag"), /* CK */
SUNXI_FUNCTION(0x4, "ir"), /* TX */
SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x6, "dmic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 3, 17)),
/* PF */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION(0x4, "r_jtag"), /* MS */
SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION(0x4, "r_jtag"), /* DI */
SUNXI_FUNCTION(0x5, "i2s2_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x6, "i2s2_din"), /* DIN1 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "ledc"),
SUNXI_FUNCTION(0x6, "spdif"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION(0x4, "r_jtag"), /* DO */
SUNXI_FUNCTION(0x5, "i2s2"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION(0x6, "ir"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "r_jtag"), /* CK */
SUNXI_FUNCTION(0x5, "i2s2"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION(0x4, "ir"), /* RX */
SUNXI_FUNCTION(0x5, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x6, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 4, 6)),
/* PG */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "emac"), /* RXCTRL/CRS_DV */
SUNXI_FUNCTION(0x5, "pwm7"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "emac"), /* RXD0 */
SUNXI_FUNCTION(0x5, "pwm6"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION(0x4, "emac"), /* RXD1 */
SUNXI_FUNCTION(0x5, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION(0x4, "emac"), /* TXCK */
SUNXI_FUNCTION(0x5, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION(0x4, "emac"), /* TXD0 */
SUNXI_FUNCTION(0x5, "pwm5"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION(0x4, "emac"), /* TXD1 */
SUNXI_FUNCTION(0x5, "pwm4"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* TXD2 */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* TXD3 */
SUNXI_FUNCTION(0x5, "spdif"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* RXD2 */
SUNXI_FUNCTION(0x5, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* RXD3 */
SUNXI_FUNCTION(0x5, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm3"),
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* RXCK */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* MCLK */
SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* EPHY-25M */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "tcon"), /* TRIG0 */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* TXCTL/TXEN */
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "pwm0"),
SUNXI_FUNCTION(0x7, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* CLKIN/RXER */
SUNXI_FUNCTION(0x5, "pwm2"),
SUNXI_FUNCTION(0x6, "ledc"),
SUNXI_FUNCTION(0x7, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1_din"), /* DIN0 */
SUNXI_FUNCTION(0x3, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x4, "emac"), /* MDC */
SUNXI_FUNCTION(0x5, "i2s1_dout"), /* DOUT1 */
SUNXI_FUNCTION(0x6, "spi0"), /* WP */
SUNXI_FUNCTION(0x7, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1_dout"), /* DOUT0 */
SUNXI_FUNCTION(0x3, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x4, "emac"), /* MDIO */
SUNXI_FUNCTION(0x5, "i2s1_din"), /* DIN1 */
SUNXI_FUNCTION(0x6, "spi0"), /* HOLD */
SUNXI_FUNCTION(0x7, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir"), /* RX */
SUNXI_FUNCTION(0x3, "tcon"), /* TRIG0 */
SUNXI_FUNCTION(0x4, "pwm5"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT2 */
SUNXI_FUNCTION(0x6, "spdif"), /* IN */
SUNXI_FUNCTION(0x7, "ledc"),
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "pwm7"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT0 */
SUNXI_FUNCTION(0x6, "ir"), /* TX */
SUNXI_FUNCTION(0x7, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "i2c3"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm6"),
SUNXI_FUNCTION(0x5, "clk"), /* FANOUT1 */
SUNXI_FUNCTION(0x6, "spdif"), /* OUT */
SUNXI_FUNCTION(0x7, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0xe, 5, 18)),
};
static const unsigned int d1_irq_bank_map[] = { 1, 2, 3, 4, 5, 6 };
static const struct sunxi_pinctrl_desc d1_pinctrl_data = {
.pins = d1_pins,
.npins = ARRAY_SIZE(d1_pins),
.irq_banks = ARRAY_SIZE(d1_irq_bank_map),
.irq_bank_map = d1_irq_bank_map,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int d1_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &d1_pinctrl_data, variant);
}
static const struct of_device_id d1_pinctrl_match[] = {
{
.compatible = "allwinner,sun20i-d1-pinctrl",
.data = (void *)PINCTRL_SUN20I_D1
},
{}
};
static struct platform_driver d1_pinctrl_driver = {
.probe = d1_pinctrl_probe,
.driver = {
.name = "sun20i-d1-pinctrl",
.of_match_table = d1_pinctrl_match,
},
};
builtin_platform_driver(d1_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Yangtao Li <[email protected]>
*
* Based on:
* huangshuosheng <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin a100_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_cir"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
};
static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = {
.pins = a100_r_pins,
.npins = ARRAY_SIZE(a100_r_pins),
.pin_base = PL_BASE,
.irq_banks = 1,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int a100_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &a100_r_pinctrl_data);
}
static const struct of_device_id a100_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-a100-r-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match);
static struct platform_driver a100_r_pinctrl_driver = {
.probe = a100_r_pinctrl_probe,
.driver = {
.name = "sun50i-a100-r-pinctrl",
.of_match_table = a100_r_pinctrl_match,
},
};
module_platform_driver(a100_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
|
/*
* Allwinner A1X SoCs pinctrl driver.
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include "../core.h"
#include "pinctrl-sunxi.h"
/*
* These lock classes tell lockdep that GPIO IRQs are in a different
* category than their parents, so it won't report false recursion.
*/
static struct lock_class_key sunxi_pinctrl_irq_lock_class;
static struct lock_class_key sunxi_pinctrl_irq_request_class;
static struct irq_chip sunxi_pinctrl_edge_irq_chip;
static struct irq_chip sunxi_pinctrl_level_irq_chip;
/*
* The sunXi PIO registers are organized as a series of banks, with registers
* for each bank in the following order:
* - Mux config
* - Data value
* - Drive level
* - Pull direction
*
* Multiple consecutive registers are used for fields wider than one bit.
*
* The following functions calculate the register and the bit offset to access.
* They take a pin number which is relative to the start of the current device.
*/
static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
}
static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
}
static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
*reg = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(pctl->dlevel_field_width) - 1) << *shift;
}
static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
u32 pin, u32 *reg, u32 *shift, u32 *mask)
{
u32 bank = pin / PINS_PER_BANK;
u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH;
*reg = bank * pctl->bank_mem_size + pctl->pull_regs_offset +
offset / BITS_PER_TYPE(u32) * sizeof(u32);
*shift = offset % BITS_PER_TYPE(u32);
*mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
}
static struct sunxi_pinctrl_group *
sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
{
int i;
for (i = 0; i < pctl->ngroups; i++) {
struct sunxi_pinctrl_group *grp = pctl->groups + i;
if (!strcmp(grp->name, group))
return grp;
}
return NULL;
}
static struct sunxi_pinctrl_function *
sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
const char *name)
{
struct sunxi_pinctrl_function *func = pctl->functions;
int i;
for (i = 0; i < pctl->nfunctions; i++) {
if (!func[i].name)
break;
if (!strcmp(func[i].name, name))
return func + i;
}
return NULL;
}
static struct sunxi_desc_function *
sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
const char *pin_name,
const char *func_name)
{
int i;
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
if (!strcmp(pin->pin.name, pin_name)) {
struct sunxi_desc_function *func = pin->functions;
while (func->name) {
if (!strcmp(func->name, func_name) &&
(!func->variant ||
func->variant & pctl->variant))
return func;
func++;
}
}
}
return NULL;
}
static struct sunxi_desc_function *
sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
const u16 pin_num,
const char *func_name)
{
int i;
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
if (pin->pin.number == pin_num) {
struct sunxi_desc_function *func = pin->functions;
while (func->name) {
if (!strcmp(func->name, func_name))
return func;
func++;
}
}
}
return NULL;
}
static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
{
return of_property_present(node, "bias-pull-up") ||
of_property_present(node, "bias-pull-down") ||
of_property_present(node, "bias-disable") ||
of_property_present(node, "allwinner,pull");
}
static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
{
return of_property_present(node, "drive-strength") ||
of_property_present(node, "allwinner,drive");
}
static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
{
u32 val;
/* Try the new style binding */
if (of_property_present(node, "bias-pull-up"))
return PIN_CONFIG_BIAS_PULL_UP;
if (of_property_present(node, "bias-pull-down"))
return PIN_CONFIG_BIAS_PULL_DOWN;
if (of_property_present(node, "bias-disable"))
return PIN_CONFIG_BIAS_DISABLE;
/* And fall back to the old binding */
if (of_property_read_u32(node, "allwinner,pull", &val))
return -EINVAL;
switch (val) {
case SUN4I_PINCTRL_NO_PULL:
return PIN_CONFIG_BIAS_DISABLE;
case SUN4I_PINCTRL_PULL_UP:
return PIN_CONFIG_BIAS_PULL_UP;
case SUN4I_PINCTRL_PULL_DOWN:
return PIN_CONFIG_BIAS_PULL_DOWN;
}
return -EINVAL;
}
static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
{
u32 val;
/* Try the new style binding */
if (!of_property_read_u32(node, "drive-strength", &val)) {
/* We can't go below 10mA ... */
if (val < 10)
return -EINVAL;
/* ... and only up to 40 mA ... */
if (val > 40)
val = 40;
/* by steps of 10 mA */
return rounddown(val, 10);
}
/* And then fall back to the old binding */
if (of_property_read_u32(node, "allwinner,drive", &val))
return -EINVAL;
return (val + 1) * 10;
}
static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
{
const char *function;
int ret;
/* Try the generic binding */
ret = of_property_read_string(node, "function", &function);
if (!ret)
return function;
/* And fall back to our legacy one */
ret = of_property_read_string(node, "allwinner,function", &function);
if (!ret)
return function;
return NULL;
}
static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
int *npins)
{
int count;
/* Try the generic binding */
count = of_property_count_strings(node, "pins");
if (count > 0) {
*npins = count;
return "pins";
}
/* And fall back to our legacy one */
count = of_property_count_strings(node, "allwinner,pins");
if (count > 0) {
*npins = count;
return "allwinner,pins";
}
return NULL;
}
static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
unsigned int *len)
{
unsigned long *pinconfig;
unsigned int configlen = 0, idx = 0;
int ret;
if (sunxi_pctrl_has_drive_prop(node))
configlen++;
if (sunxi_pctrl_has_bias_prop(node))
configlen++;
/*
* If we don't have any configuration, bail out
*/
if (!configlen)
return NULL;
pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
if (!pinconfig)
return ERR_PTR(-ENOMEM);
if (sunxi_pctrl_has_drive_prop(node)) {
int drive = sunxi_pctrl_parse_drive_prop(node);
if (drive < 0) {
ret = drive;
goto err_free;
}
pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
drive);
}
if (sunxi_pctrl_has_bias_prop(node)) {
int pull = sunxi_pctrl_parse_bias_prop(node);
int arg = 0;
if (pull < 0) {
ret = pull;
goto err_free;
}
if (pull != PIN_CONFIG_BIAS_DISABLE)
arg = 1; /* hardware uses weak pull resistors */
pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
}
*len = configlen;
return pinconfig;
err_free:
kfree(pinconfig);
return ERR_PTR(ret);
}
static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned long *pinconfig;
struct property *prop;
const char *function, *pin_prop;
const char *group;
int ret, npins, nmaps, configlen = 0, i = 0;
*map = NULL;
*num_maps = 0;
function = sunxi_pctrl_parse_function_prop(node);
if (!function) {
dev_err(pctl->dev, "missing function property in node %pOFn\n",
node);
return -EINVAL;
}
pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
if (!pin_prop) {
dev_err(pctl->dev, "missing pins property in node %pOFn\n",
node);
return -EINVAL;
}
/*
* We have two maps for each pin: one for the function, one
* for the configuration (bias, strength, etc).
*
* We might be slightly overshooting, since we might not have
* any configuration.
*/
nmaps = npins * 2;
*map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
if (IS_ERR(pinconfig)) {
ret = PTR_ERR(pinconfig);
goto err_free_map;
}
of_property_for_each_string(node, pin_prop, prop, group) {
struct sunxi_pinctrl_group *grp =
sunxi_pinctrl_find_group_by_name(pctl, group);
if (!grp) {
dev_err(pctl->dev, "unknown pin %s", group);
continue;
}
if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
grp->name,
function)) {
dev_err(pctl->dev, "unsupported function %s on pin %s",
function, group);
continue;
}
(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[i].data.mux.group = group;
(*map)[i].data.mux.function = function;
i++;
if (pinconfig) {
(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
(*map)[i].data.configs.group_or_pin = group;
(*map)[i].data.configs.configs = pinconfig;
(*map)[i].data.configs.num_configs = configlen;
i++;
}
}
*num_maps = i;
/*
* We know have the number of maps we need, we can resize our
* map array
*/
*map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
return 0;
err_free_map:
kfree(*map);
*map = NULL;
return ret;
}
static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned num_maps)
{
int i;
/* pin config is never in the first map */
for (i = 1; i < num_maps; i++) {
if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
continue;
/*
* All the maps share the same pin config,
* free only the first one we find.
*/
kfree(map[i].data.configs.configs);
break;
}
kfree(map);
}
static const struct pinctrl_ops sunxi_pctrl_ops = {
.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
.dt_free_map = sunxi_pctrl_dt_free_map,
.get_groups_count = sunxi_pctrl_get_groups_count,
.get_group_name = sunxi_pctrl_get_group_name,
.get_group_pins = sunxi_pctrl_get_group_pins,
};
static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
u32 pin, enum pin_config_param param,
u32 *reg, u32 *shift, u32 *mask)
{
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
sunxi_pull_reg(pctl, pin, reg, shift, mask);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 reg, shift, mask, val;
u16 arg;
int ret;
pin -= pctl->desc->pin_base;
ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
if (ret < 0)
return ret;
val = (readl(pctl->membase + reg) & mask) >> shift;
switch (pinconf_to_config_param(*config)) {
case PIN_CONFIG_DRIVE_STRENGTH:
arg = (val + 1) * 10;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (val != SUN4I_PINCTRL_PULL_UP)
return -EINVAL;
arg = 1; /* hardware is weak pull-up */
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (val != SUN4I_PINCTRL_PULL_DOWN)
return -EINVAL;
arg = 1; /* hardware is weak pull-down */
break;
case PIN_CONFIG_BIAS_DISABLE:
if (val != SUN4I_PINCTRL_NO_PULL)
return -EINVAL;
arg = 0;
break;
default:
/* sunxi_pconf_reg should catch anything unsupported */
WARN_ON(1);
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *config)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
/* We only support 1 pin per group. Chain it to the pin callback */
return sunxi_pconf_get(pctldev, g->pin, config);
}
static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
int i;
pin -= pctl->desc->pin_base;
for (i = 0; i < num_configs; i++) {
u32 arg, reg, shift, mask, val;
enum pin_config_param param;
unsigned long flags;
int ret;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask);
if (ret < 0)
return ret;
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
if (arg < 10 || arg > 40)
return -EINVAL;
/*
* We convert from mA to what the register expects:
* 0: 10mA
* 1: 20mA
* 2: 30mA
* 3: 40mA
*/
val = arg / 10 - 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
val = 0;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (arg == 0)
return -EINVAL;
val = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (arg == 0)
return -EINVAL;
val = 2;
break;
default:
/* sunxi_pconf_reg should catch anything unsupported */
WARN_ON(1);
return -ENOTSUPP;
}
raw_spin_lock_irqsave(&pctl->lock, flags);
writel((readl(pctl->membase + reg) & ~mask) | val << shift,
pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
} /* for each config */
return 0;
}
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
/* We only support 1 pin per group. Chain it to the pin callback */
return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
}
static const struct pinconf_ops sunxi_pconf_ops = {
.is_generic = true,
.pin_config_get = sunxi_pconf_get,
.pin_config_set = sunxi_pconf_set,
.pin_config_group_get = sunxi_pconf_group_get,
.pin_config_group_set = sunxi_pconf_group_set,
};
static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin,
struct regulator *supply)
{
unsigned short bank;
unsigned long flags;
u32 val, reg;
int uV;
if (!pctl->desc->io_bias_cfg_variant)
return 0;
uV = regulator_get_voltage(supply);
if (uV < 0)
return uV;
/* Might be dummy regulator with no voltage set */
if (uV == 0)
return 0;
pin -= pctl->desc->pin_base;
bank = pin / PINS_PER_BANK;
switch (pctl->desc->io_bias_cfg_variant) {
case BIAS_VOLTAGE_GRP_CONFIG:
/*
* Configured value must be equal or greater to actual
* voltage.
*/
if (uV <= 1800000)
val = 0x0; /* 1.8V */
else if (uV <= 2500000)
val = 0x6; /* 2.5V */
else if (uV <= 2800000)
val = 0x9; /* 2.8V */
else if (uV <= 3000000)
val = 0xA; /* 3.0V */
else
val = 0xD; /* 3.3V */
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
return 0;
case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
reg &= ~BIT(bank);
writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
fallthrough;
case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
val = uV <= 1800000 ? 1 : 0;
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
reg &= ~(1 << bank);
writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
default:
return -EINVAL;
}
}
static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->nfunctions;
}
static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->functions[function].name;
}
static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->functions[function].groups;
*num_groups = pctl->functions[function].ngroups;
return 0;
}
static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
unsigned pin,
u8 config)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
u32 reg, shift, mask;
unsigned long flags;
pin -= pctl->desc->pin_base;
sunxi_mux_reg(pctl, pin, ®, &shift, &mask);
raw_spin_lock_irqsave(&pctl->lock, flags);
writel((readl(pctl->membase + reg) & ~mask) | config << shift,
pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = pctl->groups + group;
struct sunxi_pinctrl_function *func = pctl->functions + function;
struct sunxi_desc_function *desc =
sunxi_pinctrl_desc_find_function_by_name(pctl,
g->name,
func->name);
if (!desc)
return -EINVAL;
sunxi_pmx_set(pctldev, g->pin, desc->muxval);
return 0;
}
static int
sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset,
bool input)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_desc_function *desc;
const char *func;
if (input)
func = "gpio_in";
else
func = "gpio_out";
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
if (!desc)
return -EINVAL;
sunxi_pmx_set(pctldev, offset, desc->muxval);
return 0;
}
static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned short bank = offset / PINS_PER_BANK;
unsigned short bank_offset = bank - pctl->desc->pin_base /
PINS_PER_BANK;
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
struct regulator *reg = s_reg->regulator;
char supply[16];
int ret;
if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators)))
return -EINVAL;
if (reg) {
refcount_inc(&s_reg->refcount);
return 0;
}
snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
reg = regulator_get(pctl->dev, supply);
if (IS_ERR(reg))
return dev_err_probe(pctl->dev, PTR_ERR(reg),
"Couldn't get bank P%c regulator\n",
'A' + bank);
ret = regulator_enable(reg);
if (ret) {
dev_err(pctl->dev,
"Couldn't enable bank P%c regulator\n", 'A' + bank);
goto out;
}
sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
s_reg->regulator = reg;
refcount_set(&s_reg->refcount, 1);
return 0;
out:
regulator_put(s_reg->regulator);
return ret;
}
static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned short bank = offset / PINS_PER_BANK;
unsigned short bank_offset = bank - pctl->desc->pin_base /
PINS_PER_BANK;
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
if (!refcount_dec_and_test(&s_reg->refcount))
return 0;
regulator_disable(s_reg->regulator);
regulator_put(s_reg->regulator);
s_reg->regulator = NULL;
return 0;
}
static const struct pinmux_ops sunxi_pmx_ops = {
.get_functions_count = sunxi_pmx_get_funcs_cnt,
.get_function_name = sunxi_pmx_get_func_name,
.get_function_groups = sunxi_pmx_get_func_groups,
.set_mux = sunxi_pmx_set_mux,
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
.request = sunxi_pmx_request,
.free = sunxi_pmx_free,
.strict = true,
};
static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
chip->base + offset, true);
}
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
bool set_mux = pctl->desc->irq_read_needs_mux &&
gpiochip_line_is_irq(chip, offset);
u32 pin = offset + chip->base;
u32 reg, shift, mask, val;
sunxi_data_reg(pctl, offset, ®, &shift, &mask);
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
val = (readl(pctl->membase + reg) & mask) >> shift;
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
return val;
}
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
u32 reg, shift, mask, val;
unsigned long flags;
sunxi_data_reg(pctl, offset, ®, &shift, &mask);
raw_spin_lock_irqsave(&pctl->lock, flags);
val = readl(pctl->membase + reg);
if (value)
val |= mask;
else
val &= ~mask;
writel(val, pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
sunxi_pinctrl_gpio_set(chip, offset, value);
return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
chip->base + offset, false);
}
static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
const struct of_phandle_args *gpiospec,
u32 *flags)
{
int pin, base;
base = PINS_PER_BANK * gpiospec->args[0];
pin = base + gpiospec->args[1];
if (pin > gc->ngpio)
return -EINVAL;
if (flags)
*flags = gpiospec->args[2];
return pin;
}
static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
struct sunxi_desc_function *desc;
unsigned pinnum = pctl->desc->pin_base + offset;
unsigned irqnum;
if (offset >= chip->ngpio)
return -ENXIO;
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
if (!desc)
return -EINVAL;
irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
chip->label, offset + chip->base, irqnum);
return irq_find_mapping(pctl->domain, irqnum);
}
static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
struct sunxi_desc_function *func;
int ret;
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
pctl->irq_array[d->hwirq], "irq");
if (!func)
return -EINVAL;
ret = gpiochip_lock_as_irq(pctl->chip,
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
if (ret) {
dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
irqd_to_hwirq(d));
return ret;
}
/* Change muxing to INT mode */
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
return 0;
}
static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
gpiochip_unlock_as_irq(pctl->chip,
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
}
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
u8 index = sunxi_irq_cfg_offset(d->hwirq);
unsigned long flags;
u32 regval;
u8 mode;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
mode = IRQ_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
mode = IRQ_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
mode = IRQ_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
mode = IRQ_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
mode = IRQ_LEVEL_LOW;
break;
default:
return -EINVAL;
}
raw_spin_lock_irqsave(&pctl->lock, flags);
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
handle_fasteoi_irq, NULL);
else
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
handle_edge_irq, NULL);
regval = readl(pctl->membase + reg);
regval &= ~(IRQ_CFG_IRQ_MASK << index);
writel(regval | (mode << index), pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
static void sunxi_pinctrl_irq_ack(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
/* Clear the IRQ */
writel(1 << status_idx, pctl->membase + status_reg);
}
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&pctl->lock, flags);
/* Mask the IRQ */
val = readl(pctl->membase + reg);
writel(val & ~(1 << idx), pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&pctl->lock, flags);
/* Unmask the IRQ */
val = readl(pctl->membase + reg);
writel(val | (1 << idx), pctl->membase + reg);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
{
sunxi_pinctrl_irq_ack(d);
sunxi_pinctrl_irq_unmask(d);
}
static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u8 bank = d->hwirq / IRQ_PER_BANK;
return irq_set_irq_wake(pctl->irq[bank], on);
}
static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
.name = "sunxi_pio_edge",
.irq_ack = sunxi_pinctrl_irq_ack,
.irq_mask = sunxi_pinctrl_irq_mask,
.irq_unmask = sunxi_pinctrl_irq_unmask,
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
.irq_set_type = sunxi_pinctrl_irq_set_type,
.irq_set_wake = sunxi_pinctrl_irq_set_wake,
.flags = IRQCHIP_MASK_ON_SUSPEND,
};
static struct irq_chip sunxi_pinctrl_level_irq_chip = {
.name = "sunxi_pio_level",
.irq_eoi = sunxi_pinctrl_irq_ack,
.irq_mask = sunxi_pinctrl_irq_mask,
.irq_unmask = sunxi_pinctrl_irq_unmask,
/* Define irq_enable / disable to avoid spurious irqs for drivers
* using these to suppress irqs while they clear the irq source */
.irq_enable = sunxi_pinctrl_irq_ack_unmask,
.irq_disable = sunxi_pinctrl_irq_mask,
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
.irq_set_type = sunxi_pinctrl_irq_set_type,
.irq_set_wake = sunxi_pinctrl_irq_set_wake,
.flags = IRQCHIP_EOI_THREADED |
IRQCHIP_MASK_ON_SUSPEND |
IRQCHIP_EOI_IF_HANDLED,
};
static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
struct device_node *node,
const u32 *intspec,
unsigned int intsize,
unsigned long *out_hwirq,
unsigned int *out_type)
{
struct sunxi_pinctrl *pctl = d->host_data;
struct sunxi_desc_function *desc;
int pin, base;
if (intsize < 3)
return -EINVAL;
base = PINS_PER_BANK * intspec[0];
pin = pctl->desc->pin_base + base + intspec[1];
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
if (!desc)
return -EINVAL;
*out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
*out_type = intspec[2];
return 0;
}
static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
.xlate = sunxi_pinctrl_irq_of_xlate,
};
static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
unsigned long bank, reg, val;
for (bank = 0; bank < pctl->desc->irq_banks; bank++)
if (irq == pctl->irq[bank])
break;
WARN_ON(bank == pctl->desc->irq_banks);
chained_irq_enter(chip, desc);
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
int irqoffset;
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
generic_handle_domain_irq(pctl->domain,
bank * IRQ_PER_BANK + irqoffset);
}
chained_irq_exit(chip, desc);
}
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
const char *name)
{
struct sunxi_pinctrl_function *func = pctl->functions;
while (func->name) {
/* function already there */
if (strcmp(func->name, name) == 0) {
func->ngroups++;
return -EEXIST;
}
func++;
}
func->name = name;
func->ngroups = 1;
pctl->nfunctions++;
return 0;
}
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
{
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
void *ptr;
int i;
/*
* Allocate groups
*
* We assume that the number of groups is the number of pins
* given in the data array.
* This will not always be true, since some pins might not be
* available in the current variant, but fortunately for us,
* this means that the number of pins is the maximum group
* number we will ever see.
*/
pctl->groups = devm_kcalloc(&pdev->dev,
pctl->desc->npins, sizeof(*pctl->groups),
GFP_KERNEL);
if (!pctl->groups)
return -ENOMEM;
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
if (pin->variant && !(pctl->variant & pin->variant))
continue;
group->name = pin->pin.name;
group->pin = pin->pin.number;
/* And now we count the actual number of pins / groups */
pctl->ngroups++;
}
/*
* Find an upper bound for the maximum number of functions: in
* the worst case we have gpio_in, gpio_out, irq and up to seven
* special functions per pin, plus one entry for the sentinel.
* We'll reallocate that later anyway.
*/
pctl->functions = kcalloc(7 * pctl->ngroups + 4,
sizeof(*pctl->functions),
GFP_KERNEL);
if (!pctl->functions)
return -ENOMEM;
/* Count functions and their associated groups */
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
struct sunxi_desc_function *func;
if (pin->variant && !(pctl->variant & pin->variant))
continue;
for (func = pin->functions; func->name; func++) {
if (func->variant && !(pctl->variant & func->variant))
continue;
/* Create interrupt mapping while we're at it */
if (!strcmp(func->name, "irq")) {
int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
pctl->irq_array[irqnum] = pin->pin.number;
}
sunxi_pinctrl_add_function(pctl, func->name);
}
}
/* And now allocated and fill the array for real */
ptr = krealloc(pctl->functions,
pctl->nfunctions * sizeof(*pctl->functions),
GFP_KERNEL);
if (!ptr) {
kfree(pctl->functions);
pctl->functions = NULL;
return -ENOMEM;
}
pctl->functions = ptr;
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
struct sunxi_desc_function *func;
if (pin->variant && !(pctl->variant & pin->variant))
continue;
for (func = pin->functions; func->name; func++) {
struct sunxi_pinctrl_function *func_item;
const char **func_grp;
if (func->variant && !(pctl->variant & func->variant))
continue;
func_item = sunxi_pinctrl_find_function_by_name(pctl,
func->name);
if (!func_item) {
kfree(pctl->functions);
return -EINVAL;
}
if (!func_item->groups) {
func_item->groups =
devm_kcalloc(&pdev->dev,
func_item->ngroups,
sizeof(*func_item->groups),
GFP_KERNEL);
if (!func_item->groups) {
kfree(pctl->functions);
return -ENOMEM;
}
}
func_grp = func_item->groups;
while (*func_grp)
func_grp++;
*func_grp = pin->pin.name;
}
}
return 0;
}
static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
{
unsigned long clock = clk_get_rate(clk);
unsigned int best_diff, best_div;
int i;
best_diff = abs(freq - clock);
best_div = 0;
for (i = 1; i < 8; i++) {
int cur_diff = abs(freq - (clock >> i));
if (cur_diff < best_diff) {
best_diff = cur_diff;
best_div = i;
}
}
*diff = best_diff;
return best_div;
}
static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
struct device_node *node)
{
unsigned int hosc_diff, losc_diff;
unsigned int hosc_div, losc_div;
struct clk *hosc, *losc;
u8 div, src;
int i, ret;
/* Deal with old DTs that didn't have the oscillators */
if (of_clk_get_parent_count(node) != 3)
return 0;
/* If we don't have any setup, bail out */
if (!of_property_present(node, "input-debounce"))
return 0;
losc = devm_clk_get(pctl->dev, "losc");
if (IS_ERR(losc))
return PTR_ERR(losc);
hosc = devm_clk_get(pctl->dev, "hosc");
if (IS_ERR(hosc))
return PTR_ERR(hosc);
for (i = 0; i < pctl->desc->irq_banks; i++) {
unsigned long debounce_freq;
u32 debounce;
ret = of_property_read_u32_index(node, "input-debounce",
i, &debounce);
if (ret)
return ret;
if (!debounce)
continue;
debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
losc_div = sunxi_pinctrl_get_debounce_div(losc,
debounce_freq,
&losc_diff);
hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
debounce_freq,
&hosc_diff);
if (hosc_diff < losc_diff) {
div = hosc_div;
src = 1;
} else {
div = losc_div;
src = 0;
}
writel(src | div << 4,
pctl->membase +
sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
}
return 0;
}
int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
const struct sunxi_pinctrl_desc *desc,
unsigned long variant)
{
struct device_node *node = pdev->dev.of_node;
struct pinctrl_desc *pctrl_desc;
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
struct pinmux_ops *pmxops;
int i, ret, last_pin, pin_idx;
struct clk *clk;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
raw_spin_lock_init(&pctl->lock);
pctl->membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctl->membase))
return PTR_ERR(pctl->membase);
pctl->dev = &pdev->dev;
pctl->desc = desc;
pctl->variant = variant;
if (pctl->variant >= PINCTRL_SUN20I_D1) {
pctl->bank_mem_size = D1_BANK_MEM_SIZE;
pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
} else {
pctl->bank_mem_size = BANK_MEM_SIZE;
pctl->pull_regs_offset = PULL_REGS_OFFSET;
pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
}
pctl->irq_array = devm_kcalloc(&pdev->dev,
IRQ_PER_BANK * pctl->desc->irq_banks,
sizeof(*pctl->irq_array),
GFP_KERNEL);
if (!pctl->irq_array)
return -ENOMEM;
ret = sunxi_pinctrl_build_state(pdev);
if (ret) {
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
return ret;
}
pins = devm_kcalloc(&pdev->dev,
pctl->desc->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
if (pin->variant && !(pctl->variant & pin->variant))
continue;
pins[pin_idx++] = pin->pin;
}
pctrl_desc = devm_kzalloc(&pdev->dev,
sizeof(*pctrl_desc),
GFP_KERNEL);
if (!pctrl_desc)
return -ENOMEM;
pctrl_desc->name = dev_name(&pdev->dev);
pctrl_desc->owner = THIS_MODULE;
pctrl_desc->pins = pins;
pctrl_desc->npins = pctl->ngroups;
pctrl_desc->confops = &sunxi_pconf_ops;
pctrl_desc->pctlops = &sunxi_pctrl_ops;
pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
GFP_KERNEL);
if (!pmxops)
return -ENOMEM;
if (desc->disable_strict_mode)
pmxops->strict = false;
pctrl_desc->pmxops = pmxops;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
if (IS_ERR(pctl->pctl_dev)) {
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
return PTR_ERR(pctl->pctl_dev);
}
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
if (!pctl->chip)
return -ENOMEM;
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
pctl->chip->owner = THIS_MODULE;
pctl->chip->request = gpiochip_generic_request;
pctl->chip->free = gpiochip_generic_free;
pctl->chip->set_config = gpiochip_generic_config;
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
pctl->chip->get = sunxi_pinctrl_gpio_get;
pctl->chip->set = sunxi_pinctrl_gpio_set;
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
pctl->chip->of_gpio_n_cells = 3;
pctl->chip->can_sleep = false;
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
pctl->desc->pin_base;
pctl->chip->label = dev_name(&pdev->dev);
pctl->chip->parent = &pdev->dev;
pctl->chip->base = pctl->desc->pin_base;
ret = gpiochip_add_data(pctl->chip, pctl);
if (ret)
return ret;
for (i = 0; i < pctl->desc->npins; i++) {
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
pin->pin.number - pctl->desc->pin_base,
pin->pin.number, 1);
if (ret)
goto gpiochip_error;
}
ret = of_clk_get_parent_count(node);
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto gpiochip_error;
}
ret = clk_prepare_enable(clk);
if (ret)
goto gpiochip_error;
pctl->irq = devm_kcalloc(&pdev->dev,
pctl->desc->irq_banks,
sizeof(*pctl->irq),
GFP_KERNEL);
if (!pctl->irq) {
ret = -ENOMEM;
goto clk_error;
}
for (i = 0; i < pctl->desc->irq_banks; i++) {
pctl->irq[i] = platform_get_irq(pdev, i);
if (pctl->irq[i] < 0) {
ret = pctl->irq[i];
goto clk_error;
}
}
pctl->domain = irq_domain_add_linear(node,
pctl->desc->irq_banks * IRQ_PER_BANK,
&sunxi_pinctrl_irq_domain_ops,
pctl);
if (!pctl->domain) {
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
ret = -ENOMEM;
goto clk_error;
}
for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
int irqno = irq_create_mapping(pctl->domain, i);
irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
&sunxi_pinctrl_irq_request_class);
irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
handle_edge_irq);
irq_set_chip_data(irqno, pctl);
}
for (i = 0; i < pctl->desc->irq_banks; i++) {
/* Mask and clear all IRQs before registering a handler */
writel(0, pctl->membase +
sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
writel(0xffffffff,
pctl->membase +
sunxi_irq_status_reg_from_bank(pctl->desc, i));
irq_set_chained_handler_and_data(pctl->irq[i],
sunxi_pinctrl_irq_handler,
pctl);
}
sunxi_pinctrl_setup_debounce(pctl, node);
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
return 0;
clk_error:
clk_disable_unprepare(clk);
gpiochip_error:
gpiochip_remove(pctl->chip);
return ret;
}
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sunxi.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner H6 R_PIO pin controller driver
*
* Copyright (C) 2017 Icenowy Zheng <[email protected]>
*
* Based on pinctrl-sun6i-a31-r.c, which is:
* Copyright (C) 2014 Boris Brezillon
* Boris Brezillon <[email protected]>
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_w1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2), /* PM_EINT2 */
SUNXI_FUNCTION(0x3, "1wire")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
};
static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
.pins = sun50i_h6_r_pins,
.npins = ARRAY_SIZE(sun50i_h6_r_pins),
.pin_base = PL_BASE,
.irq_banks = 2,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun50i_h6_r_pinctrl_data);
}
static const struct of_device_id sun50i_h6_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h6-r-pinctrl", },
{}
};
static struct platform_driver sun50i_h6_r_pinctrl_driver = {
.probe = sun50i_h6_r_pinctrl_probe,
.driver = {
.name = "sun50i-h6-r-pinctrl",
.of_match_table = sun50i_h6_r_pinctrl_match,
},
};
builtin_platform_driver(sun50i_h6_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
|
/*
* Allwinner H3 SoCs pinctrl driver.
*
* Copyright (C) 2016 Krzysztof Adamski <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
};
static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
.pins = sun8i_h3_r_pins,
.npins = ARRAY_SIZE(sun8i_h3_r_pins),
.irq_banks = 1,
.pin_base = PL_BASE,
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_h3_r_pinctrl_data);
}
static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
{}
};
static struct platform_driver sun8i_h3_r_pinctrl_driver = {
.probe = sun8i_h3_r_pinctrl_probe,
.driver = {
.name = "sun8i-h3-r-pinctrl",
.of_match_table = sun8i_h3_r_pinctrl_match,
},
};
builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
|
/*
* Allwinner H5 SoC pinctrl driver.
*
* Copyright (C) 2016 Icenowy Zheng <[email protected]>
*
* Based on pinctrl-sun8i-h3.c, which is:
* Copyright (C) 2015 Jens Kuske <[email protected]>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun50i_h5_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "di"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "di"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
SUNXI_FUNCTION(0x4, "mmc2")), /* DS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */
SUNXI_FUNCTION(0x3, "di"), /* TX */
SUNXI_FUNCTION(0x4, "ts2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */
SUNXI_FUNCTION(0x3, "di"), /* RX */
SUNXI_FUNCTION(0x4, "ts2")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */
SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */
SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXCK */
SUNXI_FUNCTION(0x4, "ts2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */
SUNXI_FUNCTION(0x4, "ts2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* RXERR */
SUNXI_FUNCTION(0x4, "ts2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */
SUNXI_FUNCTION(0x4, "ts2"), /* D3 */
SUNXI_FUNCTION(0x5, "ts3")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */
SUNXI_FUNCTION(0x4, "ts2"), /* D4 */
SUNXI_FUNCTION(0x5, "ts3")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */
SUNXI_FUNCTION(0x4, "ts2"), /* D5 */
SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */
SUNXI_FUNCTION(0x4, "ts2"), /* D6 */
SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* CRS */
SUNXI_FUNCTION(0x4, "ts2"), /* D7 */
SUNXI_FUNCTION(0x5, "ts3")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXCK */
SUNXI_FUNCTION(0x4, "sim")), /* PWREN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */
SUNXI_FUNCTION(0x4, "sim")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* TXERR */
SUNXI_FUNCTION(0x4, "sim")), /* DATA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */
SUNXI_FUNCTION(0x4, "sim")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* MDC */
SUNXI_FUNCTION(0x4, "sim")), /* DET */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "ts0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "ts0")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "ts0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "ts0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "ts0")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
SUNXI_FUNCTION(0x4, "ts1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
SUNXI_FUNCTION(0x4, "ts1")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "ts"), /* D7 */
SUNXI_FUNCTION(0x4, "ts1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
};
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 2,
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 3,
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = platform_irq_count(pdev);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
"Couldn't determine irq count\n");
switch (ret) {
case 2:
dev_warn(&pdev->dev,
"Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
dev_warn(&pdev->dev,
"Please update the device tree, otherwise PG bank IRQ won't work.\n");
return sunxi_pinctrl_init(pdev,
&sun50i_h5_pinctrl_data_broken);
case 3:
return sunxi_pinctrl_init(pdev,
&sun50i_h5_pinctrl_data);
default:
return -EINVAL;
}
}
static const struct of_device_id sun50i_h5_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h5-pinctrl", },
{}
};
static struct platform_driver sun50i_h5_pinctrl_driver = {
.probe = sun50i_h5_pinctrl_probe,
.driver = {
.name = "sun50i-h5-pinctrl",
.of_match_table = sun50i_h5_pinctrl_match,
},
};
builtin_platform_driver(sun50i_h5_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
|
/*
* Allwinner a33 SoCs pinctrl driver.
*
* Copyright (C) 2015 Vishnu Patekar <[email protected]>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_a33_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "uart1")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm1")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS */
SUNXI_FUNCTION(0x3, "uart3")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
};
static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
.pins = sun8i_a33_pins,
.npins = ARRAY_SIZE(sun8i_a33_pins),
.irq_banks = 2,
.irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
.disable_strict_mode = true,
};
static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_a33_pinctrl_data);
}
static const struct of_device_id sun8i_a33_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-a33-pinctrl", },
{}
};
static struct platform_driver sun8i_a33_pinctrl_driver = {
.probe = sun8i_a33_pinctrl_probe,
.driver = {
.name = "sun8i-a33-pinctrl",
.of_match_table = sun8i_a33_pinctrl_match,
},
};
builtin_platform_driver(sun8i_a33_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
|
/*
* Allwinner A31 SoCs special pins pinctrl driver.
*
* Copyright (C) 2014 Boris Brezillon
* Boris Brezillon <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
SUNXI_FUNCTION(0x3, "1wire")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
};
static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
.pins = sun6i_a31_r_pins,
.npins = ARRAY_SIZE(sun6i_a31_r_pins),
.pin_base = PL_BASE,
.irq_banks = 2,
.disable_strict_mode = true,
};
static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &sun6i_a31_r_pinctrl_data);
}
static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun6i-a31-r-pinctrl", },
{}
};
static struct platform_driver sun6i_a31_r_pinctrl_driver = {
.probe = sun6i_a31_r_pinctrl_probe,
.driver = {
.name = "sun6i-a31-r-pinctrl",
.of_match_table = sun6i_a31_r_pinctrl_match,
},
};
builtin_platform_driver(sun6i_a31_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
|
/*
* Allwinner A83T SoCs special pins pinctrl driver.
*
* Copyright (C) 2017 Chen-Yu Tsai
* Chen-Yu Tsai <[email protected]>
*
* Based on pinctrl-sun50i-a64-r.c
*
* Copyright (C) 2016 Icenowy Zheng
* Icenowy Zheng <[email protected]>
*
* Copyright (C) 2014 Chen-Yu Tsai
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Boris Brezillon
* Boris Brezillon <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
};
static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = {
.pins = sun8i_a83t_r_pins,
.npins = ARRAY_SIZE(sun8i_a83t_r_pins),
.pin_base = PL_BASE,
.irq_banks = 1,
};
static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_a83t_r_pinctrl_data);
}
static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
{}
};
static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
.probe = sun8i_a83t_r_pinctrl_probe,
.driver = {
.name = "sun8i-a83t-r-pinctrl",
.of_match_table = sun8i_a83t_r_pinctrl_match,
},
};
builtin_platform_driver(sun8i_a83t_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
|
/*
* Allwinner A23 SoCs pinctrl driver.
*
* Copyright (C) 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_a23_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "jtag"), /* CKO */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "jtag"), /* DOO */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "jtag"), /* DIO */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "uart3")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "uart3")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "uart1")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm1")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS */
SUNXI_FUNCTION(0x3, "uart3")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
};
static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
.pins = sun8i_a23_pins,
.npins = ARRAY_SIZE(sun8i_a23_pins),
.irq_banks = 3,
.disable_strict_mode = true,
};
static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_a23_pinctrl_data);
}
static const struct of_device_id sun8i_a23_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-a23-pinctrl", },
{}
};
static struct platform_driver sun8i_a23_pinctrl_driver = {
.probe = sun8i_a23_pinctrl_probe,
.driver = {
.name = "sun8i-a23-pinctrl",
.of_match_table = sun8i_a23_pinctrl_match,
},
};
builtin_platform_driver(sun8i_a23_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
|
/*
* Allwinner A64 SoCs pinctrl driver.
*
* Copyright (C) 2016 - ARM Ltd.
* Author: Andre Przywara <[email protected]>
*
* Based on pinctrl-sun7i-a20.c, which is:
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin a64_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x5, "sim"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x5, "sim"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x5, "sim"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x5, "sim"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
SUNXI_FUNCTION(0x4, "spi0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
SUNXI_FUNCTION(0x4, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION(0x5, "ccir")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
SUNXI_FUNCTION(0x5, "ccir")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
SUNXI_FUNCTION(0x5, "ccir")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x5, "ccir")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x5, "ccir")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x5, "ccir")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x5, "ccir")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
SUNXI_FUNCTION(0x4, "emac")), /* ENULL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x5, "ccir")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x5, "ccir")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
SUNXI_FUNCTION(0x4, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCK */
SUNXI_FUNCTION(0x4, "ts")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* CK */
SUNXI_FUNCTION(0x4, "ts")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x4, "ts")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x4, "ts")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x4, "ts")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x4, "ts")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x4, "ts")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x4, "ts")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x4, "ts")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x4, "ts")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x4, "ts")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x4, "ts")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mic"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
};
static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
.pins = a64_pins,
.npins = ARRAY_SIZE(a64_pins),
.irq_banks = 3,
};
static int a64_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&a64_pinctrl_data);
}
static const struct of_device_id a64_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-a64-pinctrl", },
{}
};
static struct platform_driver a64_pinctrl_driver = {
.probe = a64_pinctrl_probe,
.driver = {
.name = "sun50i-a64-pinctrl",
.of_match_table = a64_pinctrl_match,
},
};
builtin_platform_driver(a64_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Yangtao Li <[email protected]>
*
* Based on:
* huangshuosheng <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "spi2"), /* CS */
SUNXI_FUNCTION(0x4, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
SUNXI_FUNCTION(0x4, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x4, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
SUNXI_FUNCTION(0x4, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* DIN */
SUNXI_FUNCTION(0x3, "i2s0_dout0"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2s0_din1"), /* DIN1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* DOUT */
SUNXI_FUNCTION(0x3, "i2s0_din0"), /* DIN0 */
SUNXI_FUNCTION(0x4, "i2s0_dout1"), /* DOUT1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
SUNXI_FUNCTION(0x4, "spi0"), /* WP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D0P */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D0N */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D1P */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D1N */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D2P */
SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0"), /* D2N */
SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "pwm2"),
SUNXI_FUNCTION(0x4, "uart4"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "pwm3"),
SUNXI_FUNCTION(0x4, "uart4"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm1"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0"),
SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "pll"), /* LOCK_DBG */
SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x5, "ledc"), /* LEDC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "bist0"), /* RESULT0 */
SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SM_VS */
SUNXI_FUNCTION(0x3, "bist0"), /* RESULT1 */
SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
SUNXI_FUNCTION(0x5, "tcon0"), /* TRIG */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "bist0"), /* RESULT2 */
SUNXI_FUNCTION(0x4, "i2s2"), /* DOUT0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "bist0"), /* RESULT3 */
SUNXI_FUNCTION(0x4, "i2s2"), /* DIN0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s1_dout0"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2s1_din1"), /* DIN1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s1_din0"), /* DIN0 */
SUNXI_FUNCTION(0x4, "i2s1_dout1"), /* DOUT1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
/* HOLE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* TX */
SUNXI_FUNCTION(0x3, "spi1"), /* CS */
SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RX */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "ledc"),
SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* CLK */
SUNXI_FUNCTION(0x3, "spi2"), /* CS */
SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x5, "i2s2_din2"), /* DIN2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
SUNXI_FUNCTION(0x4, "i2s2_dout0"), /* DOUT0 */
SUNXI_FUNCTION(0x5, "i2s2_din1"), /* DIN1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s2_din0"), /* DIN0 */
SUNXI_FUNCTION(0x5, "i2s2_dout1"), /* DOUT1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "cir0"), /* IN */
SUNXI_FUNCTION(0x3, "i2s3_dout3"), /* DOUT3 */
SUNXI_FUNCTION(0x4, "i2s3_din3"), /* DIN3 */
SUNXI_FUNCTION(0x5, "ledc"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
};
static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.pins = a100_pins,
.npins = ARRAY_SIZE(a100_pins),
.irq_banks = 7,
.irq_bank_map = a100_irq_bank_map,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int a100_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &a100_pinctrl_data);
}
static const struct of_device_id a100_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-a100-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, a100_pinctrl_match);
static struct platform_driver a100_pinctrl_driver = {
.probe = a100_pinctrl_probe,
.driver = {
.name = "sun50i-a100-pinctrl",
.of_match_table = a100_pinctrl_match,
},
};
module_platform_driver(a100_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner H616 SoC pinctrl driver.
*
* Copyright (C) 2020 Arm Ltd.
* based on the H6 pinctrl driver
* Copyright (C) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin h616_pins[] = {
/* Internal connection to the AC200 part */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x2, "pwm5")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PC_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PC_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PC_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PC_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PC_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PC_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PC_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PC_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PC_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PC_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PC_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PC_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PC_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
SUNXI_FUNCTION(0x4, "spi0"), /* WP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PC_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), /* PF_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), /* PF_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), /* PF_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), /* PF_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), /* PF_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), /* PF_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), /* PF_EINT6 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION(0x4, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION(0x4, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x3, "clock"), /* PLL_LOCK_DEBUG */
SUNXI_FUNCTION(0x4, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x3, "clock"), /* X32KFOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), /* PG_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)), /* PG_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)), /* PG_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)), /* PG_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)), /* PG_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)), /* PG_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)), /* PG_EINT19 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x4, "pwm3"),
SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), /* PH_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x4, "pwm4"),
SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), /* PH_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart5"), /* TX */
SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
SUNXI_FUNCTION(0x4, "pwm2"),
SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), /* PH_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart5"), /* RX */
SUNXI_FUNCTION(0x4, "pwm1"),
SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), /* PH_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), /* PH_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "i2s3"), /* MCLK */
SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), /* PH_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "i2s3"), /* BCLK */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), /* PH_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "i2s3"), /* SYNC */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), /* PH_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DO0 */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION(0x5, "i2s3_din1"), /* DI1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), /* PH_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s3_din0"), /* DI0 */
SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x5, "i2s3_dout1"), /* DO1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), /* PH_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "ir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), /* PH_EINT10 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "dmic"), /* CLK */
SUNXI_FUNCTION(0x4, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x5, "hdmi"), /* HSCL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)), /* PI_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x4, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x5, "hdmi"), /* HSDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)), /* PI_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */
SUNXI_FUNCTION(0x4, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x5, "hdmi"), /* HCEC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)), /* PI_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */
SUNXI_FUNCTION(0x4, "i2s0_dout0"), /* DO0 */
SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DI1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)), /* PI_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXCK */
SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */
SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DI0 */
SUNXI_FUNCTION(0x5, "i2s0_dout1"), /* DO1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)), /* PI_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ERXCTL */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)), /* PI_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ENULL */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)), /* PI_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)), /* PI_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)), /* PI_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)), /* PI_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXD0 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)), /* PI_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXCK */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
SUNXI_FUNCTION(0x5, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)), /* PI_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ETXCTL */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
SUNXI_FUNCTION(0x5, "pwm2"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)), /* PI_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* ECLKIN */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
SUNXI_FUNCTION(0x5, "pwm3"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)), /* PI_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* MDC */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
SUNXI_FUNCTION(0x5, "pwm4"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)), /* PI_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* MDIO */
SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)), /* PI_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac0"), /* EPHY_CLK */
SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)), /* PI_EINT16 */
};
static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
.pins = h616_pins,
.npins = ARRAY_SIZE(h616_pins),
.irq_banks = ARRAY_SIZE(h616_irq_bank_map),
.irq_bank_map = h616_irq_bank_map,
.irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
static int h616_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &h616_pinctrl_data);
}
static const struct of_device_id h616_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h616-pinctrl", },
{}
};
static struct platform_driver h616_pinctrl_driver = {
.probe = h616_pinctrl_probe,
.driver = {
.name = "sun50i-h616-pinctrl",
.of_match_table = h616_pinctrl_match,
},
};
builtin_platform_driver(h616_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner H616 R_PIO pin controller driver
*
* Copyright (C) 2020 Arm Ltd.
* Based on former work, which is:
* Copyright (C) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun50i_h616_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c")), /* SDA */
};
static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = {
.pins = sun50i_h616_r_pins,
.npins = ARRAY_SIZE(sun50i_h616_r_pins),
.pin_base = PL_BASE,
};
static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun50i_h616_r_pinctrl_data);
}
static const struct of_device_id sun50i_h616_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h616-r-pinctrl", },
{}
};
static struct platform_driver sun50i_h616_r_pinctrl_driver = {
.probe = sun50i_h616_r_pinctrl_probe,
.driver = {
.name = "sun50i-h616-r-pinctrl",
.of_match_table = sun50i_h616_r_pinctrl_match,
},
};
builtin_platform_driver(sun50i_h616_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
|
/*
* Allwinner A23 SoCs special pins pinctrl driver.
*
* Copyright (C) 2014 Chen-Yu Tsai
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Boris Brezillon
* Boris Brezillon <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 10)), /* PL_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 11)), /* PL_EINT11 */
};
static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
.pins = sun8i_a23_r_pins,
.npins = ARRAY_SIZE(sun8i_a23_r_pins),
.pin_base = PL_BASE,
.irq_banks = 1,
.disable_strict_mode = true,
};
static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &sun8i_a23_r_pinctrl_data);
}
static const struct of_device_id sun8i_a23_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-a23-r-pinctrl", },
{}
};
static struct platform_driver sun8i_a23_r_pinctrl_driver = {
.probe = sun8i_a23_r_pinctrl_probe,
.driver = {
.name = "sun8i-a23-r-pinctrl",
.of_match_table = sun8i_a23_r_pinctrl_match,
},
};
builtin_platform_driver(sun8i_a23_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
|
/*
* Allwinner V3/V3s SoCs pinctrl driver.
*
* Copyright (C) 2016 Icenowy Zheng <[email protected]>
*
* Based on pinctrl-sun8i-h3.c, which is:
* Copyright (C) 2015 Jens Kuske <[email protected]>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* RST */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */
/* Hole */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D4 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
SUNXI_FUNCTION(0x4, "emac")), /* RXCK */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
SUNXI_FUNCTION(0x4, "emac")), /* RXERR */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
SUNXI_FUNCTION(0x4, "emac")), /* CRS */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */
SUNXI_FUNCTION(0x4, "emac")), /* TXCK */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */
SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */
SUNXI_FUNCTION(0x4, "emac")), /* TXERR */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */
SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */
SUNXI_FUNCTION(0x4, "emac")), /* MDC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */
SUNXI_FUNCTION(0x4, "emac")), /* MDIO */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds")), /* VPC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
SUNXI_FUNCTION(0x3, "lvds")), /* VNC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "lcd")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "lcd")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "lcd")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "lcd")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "lcd")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "lcd")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "lcd")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "lcd")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "lcd")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "lcd")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
SUNXI_FUNCTION(0x3, "lcd")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
SUNXI_FUNCTION(0x3, "lcd")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D10 */
SUNXI_FUNCTION(0x3, "lcd")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D11 */
SUNXI_FUNCTION(0x3, "lcd")), /* D15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D12 */
SUNXI_FUNCTION(0x3, "lcd")), /* D18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D13 */
SUNXI_FUNCTION(0x3, "lcd")), /* D19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D14 */
SUNXI_FUNCTION(0x3, "lcd")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D15 */
SUNXI_FUNCTION(0x3, "lcd")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* FIELD */
SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "lcd"), /* D22 */
SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "lcd"), /* D23 */
SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
};
static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map,
.irq_read_needs_mux = true
};
static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data,
variant);
}
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
{
.compatible = "allwinner,sun8i-v3-pinctrl",
.data = (void *)PINCTRL_SUN8I_V3
},
{
.compatible = "allwinner,sun8i-v3s-pinctrl",
.data = (void *)PINCTRL_SUN8I_V3S
},
{ },
};
static struct platform_driver sun8i_v3s_pinctrl_driver = {
.probe = sun8i_v3s_pinctrl_probe,
.driver = {
.name = "sun8i-v3s-pinctrl",
.of_match_table = sun8i_v3s_pinctrl_match,
},
};
builtin_platform_driver(sun8i_v3s_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
|
/*
* Allwinner A10 SoCs pinctrl driver.
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
SUNXI_FUNCTION(0x3, "can"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
SUNXI_FUNCTION(0x3, "can"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_VARIANT(0x3, "pll_lock_dbg",
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM1 */
PINCTRL_SUN8I_R40),
/*
* The SPDIF block is not referenced at all in the A10 user
* manual. However it is described in the code leaked and the
* pin descriptions are declared in the A20 user manual which
* is pin compatible with this device.
*/
SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
/*
* On A10 there's only one I2S controller and the pin group
* is simply named "i2s". On A20 there's two and thus it's
* renamed to "i2s0". Deal with these name here, in order
* to satisfy existing device trees.
*/
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM6 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM7 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97"), /* DI */
/* Undocumented mux function on A10 - See SPDIF MCLK above */
SUNXI_FUNCTION_VARIANT(0x4, "spdif", /* SPDIF IN */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
/* Undocumented mux function on A10 - See SPDIF MCLK above */
SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF OUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM4 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM5 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_VARIANT(0x3, "ir1", /* TX */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "ir1")), /* RX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* DS */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D4 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D5 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D6 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D7 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* RST */
PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "sim")), /* DET */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "sim")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "sim")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "sim")), /* SDA */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
SUNXI_FUNCTION(0x3, "csi0")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
SUNXI_FUNCTION(0x3, "csi1"), /* CK */
SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION(0x5, "csi0"), /* D13 */
SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT0 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION(0x5, "csi0"), /* D14 */
SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT1 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIRQ */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* BS */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* CLK */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D1 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D2 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D3 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD8 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD9 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x5, "sim"), /* RST */
SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
SUNXI_FUNCTION(0x5, "sim"), /* DET */
SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
SUNXI_FUNCTION(0x5, "sim"), /* SCK */
SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
SUNXI_FUNCTION(0x5, "sim"), /* SDA */
SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SDA */
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a",
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b",
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSCL */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM2 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSDA */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM3 */
PINCTRL_SUN8I_R40)),
};
static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
.pins = sun4i_a10_pins,
.npins = ARRAY_SIZE(sun4i_a10_pins),
.irq_banks = 1,
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data,
variant);
}
static const struct of_device_id sun4i_a10_pinctrl_match[] = {
{
.compatible = "allwinner,sun4i-a10-pinctrl",
.data = (void *)PINCTRL_SUN4I_A10
},
{
.compatible = "allwinner,sun7i-a20-pinctrl",
.data = (void *)PINCTRL_SUN7I_A20
},
{
.compatible = "allwinner,sun8i-r40-pinctrl",
.data = (void *)PINCTRL_SUN8I_R40
},
{}
};
static struct platform_driver sun4i_a10_pinctrl_driver = {
.probe = sun4i_a10_pinctrl_probe,
.driver = {
.name = "sun4i-pinctrl",
.of_match_table = sun4i_a10_pinctrl_match,
},
};
builtin_platform_driver(sun4i_a10_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
|
/*
* Allwinner A64 SoCs special pins pinctrl driver.
*
* Based on pinctrl-sun8i-a23-r.c
*
* Copyright (C) 2016 Icenowy Zheng
* Icenowy Zheng <[email protected]>
*
* Copyright (C) 2014 Chen-Yu Tsai
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Boris Brezillon
* Boris Brezillon <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
};
static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
.pins = sun50i_a64_r_pins,
.npins = ARRAY_SIZE(sun50i_a64_r_pins),
.pin_base = PL_BASE,
.irq_banks = 1,
};
static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun50i_a64_r_pinctrl_data);
}
static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-a64-r-pinctrl", },
{}
};
static struct platform_driver sun50i_a64_r_pinctrl_driver = {
.probe = sun50i_a64_r_pinctrl_probe,
.driver = {
.name = "sun50i-a64-r-pinctrl",
.of_match_table = sun50i_a64_r_pinctrl_match,
},
};
builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
|
/*
* Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
*
* Copyright (C) 2018 Icenowy Zheng
*
* Icenowy Zheng <[email protected]>
*
* Copyright (C) 2014 Jackie Hwang
*
* Jackie Hwang <[email protected]>
*
* Copyright (C) 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <[email protected]>
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* CKE */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS */
SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
SUNXI_FUNCTION(0x3, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
SUNXI_FUNCTION(0x3, "spi0"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
SUNXI_FUNCTION(0x4, "clk"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION(0x4, "ir0"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
};
static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
.pins = suniv_f1c100s_pins,
.npins = ARRAY_SIZE(suniv_f1c100s_pins),
.irq_banks = 3,
};
static int suniv_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&suniv_f1c100s_pinctrl_data);
}
static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
{ .compatible = "allwinner,suniv-f1c100s-pinctrl", },
{}
};
static struct platform_driver suniv_f1c100s_pinctrl_driver = {
.probe = suniv_pinctrl_probe,
.driver = {
.name = "suniv-f1c100s-pinctrl",
.of_match_table = suniv_f1c100s_pinctrl_match,
},
};
builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
|
/*
* Allwinner A80 SoCs special pins pinctrl driver.
*
* Copyright (C) 2014 Maxime Ripard
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "1wire"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */
};
static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
.pins = sun9i_a80_r_pins,
.npins = ARRAY_SIZE(sun9i_a80_r_pins),
.pin_base = PL_BASE,
.irq_banks = 2,
.disable_strict_mode = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
};
static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun9i_a80_r_pinctrl_data);
}
static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{}
};
static struct platform_driver sun9i_a80_r_pinctrl_driver = {
.probe = sun9i_a80_r_pinctrl_probe,
.driver = {
.name = "sun9i-a80-r-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sun9i_a80_r_pinctrl_match,
},
};
builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
|
/*
* Allwinner H3 SoCs pinctrl driver.
*
* Copyright (C) 2015 Jens Kuske <[email protected]>
*
* Based on pinctrl-sun8i-a23.c, which is:
* Copyright (C) 2014 Chen-Yu Tsai <[email protected]>
* Copyright (C) 2014 Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_h3_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sim"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "di"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "di"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXCTL/RXDV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* RXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* CRS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXCTL/TXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* TXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* CLKIN/COL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* MDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "ts")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "ts")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "ts")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "ts")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "ts")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "ts")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "ts")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "ts")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "ts")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "ts")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
};
static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
.pins = sun8i_h3_pins,
.npins = ARRAY_SIZE(sun8i_h3_pins),
.irq_banks = 2,
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_h3_pinctrl_data);
}
static const struct of_device_id sun8i_h3_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-h3-pinctrl", },
{}
};
static struct platform_driver sun8i_h3_pinctrl_driver = {
.probe = sun8i_h3_pinctrl_probe,
.driver = {
.name = "sun8i-h3-pinctrl",
.of_match_table = sun8i_h3_pinctrl_match,
},
};
builtin_platform_driver(sun8i_h3_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
|
/*
* Allwinner A31 SoCs pinctrl driver.
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D0 */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D1 */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D2 */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D3 */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D4 */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D5 */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D6 */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D7 */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D8 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D9 */
SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D10 */
SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D11 */
SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D12 */
SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D13 */
SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D14 */
SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D15 */
SUNXI_FUNCTION(0x4, "clk_out_a"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D16 */
SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D17 */
SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D18 */
SUNXI_FUNCTION(0x4, "clk_out_b"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D19 */
SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D20 */
SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D21 */
SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D22 */
SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* COL */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* D23 */
SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* CLK */
SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* DE */
SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* HSYNC */
SUNXI_FUNCTION(0x4, "clk_out_c"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
PINCTRL_SUN6I_A31), /* VSYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x4, "csi",
PINCTRL_SUN6I_A31), /* MCLK1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
/* Hole in pin numbering for A31s */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 19), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 20), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 21), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 22), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 23), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION_VARIANT(0x3, "lvds1",
PINCTRL_SUN6I_A31)), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "ts"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "ts"), /* ERR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "ts"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "ts"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "ts"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "ts"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
SUNXI_FUNCTION(0x3, "ts"), /* D4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
SUNXI_FUNCTION(0x3, "ts"), /* D5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D10 */
SUNXI_FUNCTION(0x3, "ts"), /* D6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D11 */
SUNXI_FUNCTION(0x3, "ts"), /* D7 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 16), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION_VARIANT(0x3, "usb",
PINCTRL_SUN6I_A31), /* DP3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION_VARIANT(0x3, "usb",
PINCTRL_SUN6I_A31), /* DM3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
/* Hole; H starts at pin 9 for A31s */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 0), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* WE */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 1), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 2), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 3), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 4), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 5), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* RE */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 6), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 7), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 8), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
/*
* The SPDIF block is not referenced at all in the A31 user
* manual. However it is described in the code leaked and the
* configuration files supplied by vendors.
*/
SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF IN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
/* Undocumented mux function - see above */
SUNXI_FUNCTION(0x3, "spdif")), /* SPDIF OUT */
/* 2 extra pins for A31 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 29), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 30), PINCTRL_SUN6I_A31,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
};
static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
.pins = sun6i_a31_pins,
.npins = ARRAY_SIZE(sun6i_a31_pins),
.irq_banks = 4,
.disable_strict_mode = true,
};
static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant =
(unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev,
&sun6i_a31_pinctrl_data,
variant);
}
static const struct of_device_id sun6i_a31_pinctrl_match[] = {
{
.compatible = "allwinner,sun6i-a31-pinctrl",
.data = (void *)PINCTRL_SUN6I_A31
},
{
.compatible = "allwinner,sun6i-a31s-pinctrl",
.data = (void *)PINCTRL_SUN6I_A31S
},
{}
};
static struct platform_driver sun6i_a31_pinctrl_driver = {
.probe = sun6i_a31_pinctrl_probe,
.driver = {
.name = "sun6i-a31-pinctrl",
.of_match_table = sun6i_a31_pinctrl_match,
},
};
builtin_platform_driver(sun6i_a31_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
|
/*
* Allwinner A80 SoCs pinctrl driver.
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun9i_a80_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
SUNXI_FUNCTION(0x4, "eclk"), /* IN0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
SUNXI_FUNCTION(0x4, "eclk"), /* IN1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
SUNXI_FUNCTION(0x4, "clk_out_a"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MII-CRS */
SUNXI_FUNCTION(0x4, "clk_out_b"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* TXCK */
SUNXI_FUNCTION(0x4, "pwm3"), /* PWM_P */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-TXCK / GMII-TXEN */
SUNXI_FUNCTION(0x4, "pwm3"), /* PWM_N */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* MII-TXERR */
SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-CLKIN / MII-COL */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* EMDC */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "gmac"), /* EMDIO */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* SCK */
SUNXI_FUNCTION(0x4, "i2c4"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* SDA */
SUNXI_FUNCTION(0x4, "i2c4"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE2 */
SUNXI_FUNCTION(0x3, "nand0_b")), /* RE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE3 */
SUNXI_FUNCTION(0x3, "nand0_b")), /* DQS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "ts"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
SUNXI_FUNCTION(0x3, "ts"), /* ERR */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart5"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
SUNXI_FUNCTION(0x4, "uart5"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "ts"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "ts"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "ts"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "ts"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D8 */
SUNXI_FUNCTION(0x3, "ts"), /* D4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D9 */
SUNXI_FUNCTION(0x3, "ts"), /* D5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D10 */
SUNXI_FUNCTION(0x3, "ts"), /* D6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D11 */
SUNXI_FUNCTION(0x3, "ts"), /* D7 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
SUNXI_FUNCTION(0x3, "i2c4"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
SUNXI_FUNCTION(0x3, "i2c4"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PE_EINT17 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "pwm1"), /* Positive */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)), /* PH_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "pwm1"), /* Negative */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)), /* PH_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "pwm2"), /* Positive */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 10)), /* PH_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "pwm2"), /* Negative */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 11)), /* PH_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x3, "spi3"), /* CS2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 12)), /* PH_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "spi3"), /* CS2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 13)), /* PH_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi3"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 14)), /* PH_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi3"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 15)), /* PH_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi3"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /* PH_EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi3"), /* CS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 17)), /* PH_EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi3"), /* CS1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 18)), /* PH_EINT18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi")), /* SCL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi")), /* CEC */
};
static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
.pins = sun9i_a80_pins,
.npins = ARRAY_SIZE(sun9i_a80_pins),
.irq_banks = 5,
.disable_strict_mode = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
};
static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun9i_a80_pinctrl_data);
}
static const struct of_device_id sun9i_a80_pinctrl_match[] = {
{ .compatible = "allwinner,sun9i-a80-pinctrl", },
{}
};
static struct platform_driver sun9i_a80_pinctrl_driver = {
.probe = sun9i_a80_pinctrl_probe,
.driver = {
.name = "sun9i-a80-pinctrl",
.of_match_table = sun9i_a80_pinctrl_match,
},
};
builtin_platform_driver(sun9i_a80_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
|
/*
* Allwinner sun5i SoCs pinctrl driver.
*
* Copyright (C) 2014-2016 Maxime Ripard <[email protected]>
* Copyright (C) 2016 Mylene Josserand <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun5i_pins[] = {
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 0),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 1),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 2),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 3),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 4),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 5),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 6),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 7),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 8),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 9),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 10),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 11),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 12),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 13),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 14),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 15),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 16),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
SUNXI_FUNCTION(0x3, "uart2")), /* TX */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 17),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
SUNXI_FUNCTION_VARIANT(0x3,
"spdif", /* DO */
PINCTRL_SUN5I_GR8),
SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir0"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir0"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 5),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 6),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 7),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 8),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DO */
SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 9),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DI */
SUNXI_FUNCTION_VARIANT(0x3,
"spdif", /* DI */
PINCTRL_SUN5I_GR8),
SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x3,
"spdif", /* DO */
PINCTRL_SUN5I_GR8),
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 14),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 19),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 20),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
SUNXI_FUNCTION(0x4, "uart3")), /* TX */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
SUNXI_FUNCTION(0x4, "uart3")), /* RX */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
/* Hole */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "uart2")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart2")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
PINCTRL_SUN5I_A10S,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
SUNXI_FUNCTION(0x3, "csi0"), /* CK */
SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "gps"), /* CLK */
SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x2, "gps"), /* MAG */
SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 5),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x5, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x5, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13),
PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */
SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
};
static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = {
.pins = sun5i_pins,
.npins = ARRAY_SIZE(sun5i_pins),
.irq_banks = 1,
.disable_strict_mode = true,
};
static int sun5i_pinctrl_probe(struct platform_device *pdev)
{
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &sun5i_pinctrl_data,
variant);
}
static const struct of_device_id sun5i_pinctrl_match[] = {
{
.compatible = "allwinner,sun5i-a10s-pinctrl",
.data = (void *)PINCTRL_SUN5I_A10S
},
{
.compatible = "allwinner,sun5i-a13-pinctrl",
.data = (void *)PINCTRL_SUN5I_A13
},
{
.compatible = "nextthing,gr8-pinctrl",
.data = (void *)PINCTRL_SUN5I_GR8
},
{ },
};
static struct platform_driver sun5i_pinctrl_driver = {
.probe = sun5i_pinctrl_probe,
.driver = {
.name = "sun5i-pinctrl",
.of_match_table = sun5i_pinctrl_match,
},
};
builtin_platform_driver(sun5i_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/sunxi/pinctrl-sun5i.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Orion pinctrl driver based on mvebu pinctrl core
*
* Author: Thomas Petazzoni <[email protected]>
*
* The first 16 MPP pins on Orion are easy to handle: they are
* configured through 2 consecutive registers, located at the base
* address of the MPP device.
*
* However the last 4 MPP pins are handled by a register at offset
* 0x50 from the base address, so it is not consecutive with the first
* two registers.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static void __iomem *mpp_base;
static void __iomem *high_mpp_base;
static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
unsigned pid, unsigned long *config)
{
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
if (pid < 16) {
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
}
else {
*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
}
return 0;
}
static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
unsigned pid, unsigned long config)
{
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
if (pid < 16) {
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
writel(reg | (config << shift), mpp_base + off);
}
else {
u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
writel(reg | (config << shift), high_mpp_base);
}
return 0;
}
#define V(f5181, f5182, f5281) \
((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
enum orion_variant {
V_5181 = V(1, 0, 0),
V_5182 = V(0, 1, 0),
V_5281 = V(0, 0, 1),
V_ALL = V(1, 1, 1),
};
static struct mvebu_mpp_mode orion_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281),
MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
};
static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 16),
};
static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 19),
};
static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 16),
};
static struct mvebu_pinctrl_soc_info mv88f5181_info = {
.variant = V_5181,
.controls = orion_mpp_controls,
.ncontrols = ARRAY_SIZE(orion_mpp_controls),
.modes = orion_mpp_modes,
.nmodes = ARRAY_SIZE(orion_mpp_modes),
.gpioranges = mv88f5181_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f5182_info = {
.variant = V_5182,
.controls = orion_mpp_controls,
.ncontrols = ARRAY_SIZE(orion_mpp_controls),
.modes = orion_mpp_modes,
.nmodes = ARRAY_SIZE(orion_mpp_modes),
.gpioranges = mv88f5182_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
};
static struct mvebu_pinctrl_soc_info mv88f5281_info = {
.variant = V_5281,
.controls = orion_mpp_controls,
.ncontrols = ARRAY_SIZE(orion_mpp_controls),
.modes = orion_mpp_modes,
.nmodes = ARRAY_SIZE(orion_mpp_modes),
.gpioranges = mv88f5281_gpio_ranges,
.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
};
/*
* There are multiple variants of the Orion SoCs, but in terms of pin
* muxing, they are identical.
*/
static const struct of_device_id orion_pinctrl_of_match[] = {
{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
{ }
};
static int orion_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(orion_pinctrl_of_match, &pdev->dev);
pdev->dev.platform_data = (void*)match->data;
mpp_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mpp_base))
return PTR_ERR(mpp_base);
high_mpp_base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(high_mpp_base))
return PTR_ERR(high_mpp_base);
return mvebu_pinctrl_probe(pdev);
}
static struct platform_driver orion_pinctrl_driver = {
.driver = {
.name = "orion-pinctrl",
.of_match_table = of_match_ptr(orion_pinctrl_of_match),
},
.probe = orion_pinctrl_probe,
};
builtin_platform_driver(orion_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-orion.c
|
/*
* Marvell 37xx SoC pinctrl driver
*
* Copyright (C) 2017 Marvell
*
* Gregory CLEMENT <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2 or later. This program is licensed "as is"
* without any warranty of any kind, whether express or implied.
*/
#include <linux/gpio/driver.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
#include "../pinctrl-utils.h"
#define OUTPUT_EN 0x0
#define INPUT_VAL 0x10
#define OUTPUT_VAL 0x18
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
#define IRQ_EN 0x0
#define IRQ_POL 0x08
#define IRQ_STATUS 0x10
#define IRQ_WKUP 0x18
#define NB_FUNCS 3
#define GPIO_PER_REG 32
/**
* struct armada_37xx_pin_group: represents group of pins of a pinmux function.
* The pins of a pinmux groups are composed of one or two groups of contiguous
* pins.
* @name: Name of the pin group, used to lookup the group.
* @start_pin: Index of the first pin of the main range of pins belonging to
* the group
* @npins: Number of pins included in the first range
* @reg_mask: Bit mask matching the group in the selection register
* @val: Value to write to the registers for a given function
* @extra_pin: Index of the first pin of the optional second range of pins
* belonging to the group
* @extra_npins:Number of pins included in the second optional range
* @funcs: A list of pinmux functions that can be selected for this group.
* @pins: List of the pins included in the group
*/
struct armada_37xx_pin_group {
const char *name;
unsigned int start_pin;
unsigned int npins;
u32 reg_mask;
u32 val[NB_FUNCS];
unsigned int extra_pin;
unsigned int extra_npins;
const char *funcs[NB_FUNCS];
unsigned int *pins;
};
struct armada_37xx_pin_data {
u8 nr_pins;
char *name;
struct armada_37xx_pin_group *groups;
int ngroups;
};
struct armada_37xx_pmx_func {
const char *name;
const char **groups;
unsigned int ngroups;
};
struct armada_37xx_pm_state {
u32 out_en_l;
u32 out_en_h;
u32 out_val_l;
u32 out_val_h;
u32 irq_en_l;
u32 irq_en_h;
u32 irq_pol_l;
u32 irq_pol_h;
u32 selection;
};
struct armada_37xx_pinctrl {
struct regmap *regmap;
void __iomem *base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chip gpio_chip;
raw_spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group *groups;
unsigned int ngroups;
struct armada_37xx_pmx_func *funcs;
unsigned int nfuncs;
struct armada_37xx_pm_state pm;
};
#define PIN_GRP_GPIO_0(_name, _start, _nr) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = 0, \
.val = {0}, \
.funcs = {"gpio"} \
}
#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {0, _mask}, \
.funcs = {_func1, "gpio"} \
}
#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {_val1, _val2}, \
.funcs = {_func1, "gpio"} \
}
#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {_v1, _v2, _v3}, \
.funcs = {_f1, _f2, "gpio"} \
}
#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
_f1, _f2) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {_v1, _v2}, \
.extra_pin = _start2, \
.extra_npins = _nr2, \
.funcs = {_f1, _f2} \
}
static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
"pwm", "led"),
PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO_0("gpio1_5", 5, 1),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
18, 2, "gpio", "uart"),
};
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
PIN_GRP_GPIO_0("gpio2_2", 2, 1),
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
"ptp", "mii"),
PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
"ptp", "mii"),
PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
"mii", "mii_err"),
};
static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
.nr_pins = 36,
.name = "GPIO1",
.groups = armada_37xx_nb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
};
static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.nr_pins = 30,
.name = "GPIO2",
.groups = armada_37xx_sb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
};
static inline void armada_37xx_update_reg(unsigned int *reg,
unsigned int *offset)
{
/* We never have more than 2 registers */
if (*offset >= GPIO_PER_REG) {
*offset -= GPIO_PER_REG;
*reg += sizeof(u32);
}
}
static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
struct armada_37xx_pinctrl *info, int pin, int *grp)
{
while (*grp < info->ngroups) {
struct armada_37xx_pin_group *group = &info->groups[*grp];
int j;
*grp = *grp + 1;
for (j = 0; j < (group->npins + group->extra_npins); j++)
if (group->pins[j] == pin)
return group;
}
return NULL;
}
static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned long *config)
{
return -ENOTSUPP;
}
static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned long *configs,
unsigned int num_configs)
{
return -ENOTSUPP;
}
static const struct pinconf_ops armada_37xx_pinconf_ops = {
.is_generic = true,
.pin_config_group_get = armada_37xx_pin_config_group_get,
.pin_config_group_set = armada_37xx_pin_config_group_set,
};
static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->ngroups;
}
static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->groups[group].name;
}
static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*npins = info->groups[selector].npins +
info->groups[selector].extra_npins;
return 0;
}
static const struct pinctrl_ops armada_37xx_pctrl_ops = {
.get_groups_count = armada_37xx_get_groups_count,
.get_group_name = armada_37xx_get_group_name,
.get_group_pins = armada_37xx_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
};
/*
* Pinmux_ops handling
*/
static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->nfuncs;
}
static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->funcs[selector].name;
}
static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*groups = info->funcs[selector].groups;
*num_groups = info->funcs[selector].ngroups;
return 0;
}
static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
const char *name,
struct armada_37xx_pin_group *grp)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = info->dev;
unsigned int reg = SELECTION;
unsigned int mask = grp->reg_mask;
int func, val;
dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
func = match_string(grp->funcs, NB_FUNCS, name);
if (func < 0)
return -ENOTSUPP;
val = grp->val[func];
regmap_update_bits(info->regmap, reg, mask, val);
return 0;
}
static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned int group)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct armada_37xx_pin_group *grp = &info->groups[group];
const char *name = info->funcs[selector].name;
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
static inline void armada_37xx_irq_update_reg(unsigned int *reg,
struct irq_data *d)
{
int offset = irqd_to_hwirq(d);
armada_37xx_update_reg(reg, &offset);
}
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, 0);
}
static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int val, mask;
armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
regmap_read(info->regmap, reg, &val);
if (val & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask, val, ret;
armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
ret = regmap_update_bits(info->regmap, reg, mask, mask);
if (ret)
return ret;
reg = OUTPUT_VAL;
val = value ? mask : 0;
regmap_update_bits(info->regmap, reg, mask, val);
return 0;
}
static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = INPUT_VAL;
unsigned int val, mask;
armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
regmap_read(info->regmap, reg, &val);
return (val & mask) != 0;
}
static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_VAL;
unsigned int mask, val;
armada_37xx_update_reg(®, &offset);
mask = BIT(offset);
val = value ? mask : 0;
regmap_update_bits(info->regmap, reg, mask, val);
}
static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = range->gc;
dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
offset, range->name, offset, input ? "input" : "output");
if (input)
armada_37xx_gpio_direction_input(chip, offset);
else
armada_37xx_gpio_direction_output(chip, offset, 0);
return 0;
}
static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct armada_37xx_pin_group *group;
int grp = 0;
int ret;
dev_dbg(info->dev, "requesting gpio %d\n", offset);
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) {
ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
if (ret)
return ret;
}
return 0;
}
static const struct pinmux_ops armada_37xx_pmx_ops = {
.get_functions_count = armada_37xx_pmx_get_funcs_count,
.get_function_name = armada_37xx_pmx_get_func_name,
.get_function_groups = armada_37xx_pmx_get_groups,
.set_mux = armada_37xx_pmx_set,
.gpio_request_enable = armada_37xx_gpio_request_enable,
.gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
};
static const struct gpio_chip armada_37xx_gpiolib_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.set = armada_37xx_gpio_set,
.get = armada_37xx_gpio_get,
.get_direction = armada_37xx_gpio_get_direction,
.direction_input = armada_37xx_gpio_direction_input,
.direction_output = armada_37xx_gpio_direction_output,
.owner = THIS_MODULE,
};
static void armada_37xx_irq_ack(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
u32 reg = IRQ_STATUS;
unsigned long flags;
armada_37xx_irq_update_reg(®, d);
raw_spin_lock_irqsave(&info->irq_lock, flags);
writel(d->mask, info->base + reg);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
}
static void armada_37xx_irq_mask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
u32 val, reg = IRQ_EN;
unsigned long flags;
armada_37xx_irq_update_reg(®, d);
raw_spin_lock_irqsave(&info->irq_lock, flags);
val = readl(info->base + reg);
writel(val & ~d->mask, info->base + reg);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
gpiochip_disable_irq(chip, irqd_to_hwirq(d));
}
static void armada_37xx_irq_unmask(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
u32 val, reg = IRQ_EN;
unsigned long flags;
gpiochip_enable_irq(chip, irqd_to_hwirq(d));
armada_37xx_irq_update_reg(®, d);
raw_spin_lock_irqsave(&info->irq_lock, flags);
val = readl(info->base + reg);
writel(val | d->mask, info->base + reg);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
}
static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
u32 val, reg = IRQ_WKUP;
unsigned long flags;
armada_37xx_irq_update_reg(®, d);
raw_spin_lock_irqsave(&info->irq_lock, flags);
val = readl(info->base + reg);
if (on)
val |= (BIT(d->hwirq % GPIO_PER_REG));
else
val &= ~(BIT(d->hwirq % GPIO_PER_REG));
writel(val, info->base + reg);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
return 0;
}
static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
u32 val, reg = IRQ_POL;
unsigned long flags;
raw_spin_lock_irqsave(&info->irq_lock, flags);
armada_37xx_irq_update_reg(®, d);
val = readl(info->base + reg);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
val &= ~(BIT(d->hwirq % GPIO_PER_REG));
break;
case IRQ_TYPE_EDGE_FALLING:
val |= (BIT(d->hwirq % GPIO_PER_REG));
break;
case IRQ_TYPE_EDGE_BOTH: {
u32 in_val, in_reg = INPUT_VAL;
armada_37xx_irq_update_reg(&in_reg, d);
regmap_read(info->regmap, in_reg, &in_val);
/* Set initial polarity based on current input level. */
if (in_val & BIT(d->hwirq % GPIO_PER_REG))
val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
else
val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
break;
}
default:
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
return -EINVAL;
}
writel(val, info->base + reg);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
return 0;
}
static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
u32 pin_idx)
{
u32 reg_idx = pin_idx / GPIO_PER_REG;
u32 bit_num = pin_idx % GPIO_PER_REG;
u32 p, l, ret;
unsigned long flags;
regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
raw_spin_lock_irqsave(&info->irq_lock, flags);
p = readl(info->base + IRQ_POL + 4 * reg_idx);
if ((p ^ l) & (1 << bit_num)) {
/*
* For the gpios which are used for both-edge irqs, when their
* interrupts happen, their input levels are changed,
* yet their interrupt polarities are kept in old values, we
* should synchronize their interrupt polarities; for example,
* at first a gpio's input level is low and its interrupt
* polarity control is "Detect rising edge", then the gpio has
* a interrupt , its level turns to high, we should change its
* polarity control to "Detect falling edge" correspondingly.
*/
p ^= 1 << bit_num;
writel(p, info->base + IRQ_POL + 4 * reg_idx);
ret = 0;
} else {
/* Spurious irq */
ret = -1;
}
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
return ret;
}
static void armada_37xx_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
struct irq_domain *d = gc->irq.domain;
int i;
chained_irq_enter(chip, desc);
for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
u32 status;
unsigned long flags;
raw_spin_lock_irqsave(&info->irq_lock, flags);
status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
/* Manage only the interrupt that was enabled */
status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
while (status) {
u32 hwirq = ffs(status) - 1;
u32 virq = irq_find_mapping(d, hwirq +
i * GPIO_PER_REG);
u32 t = irq_get_trigger_type(virq);
if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
/* Swap polarity (race with GPIO line) */
if (armada_37xx_edge_both_irq_swap_pol(info,
hwirq + i * GPIO_PER_REG)) {
/*
* For spurious irq, which gpio level
* is not as expected after incoming
* edge, just ack the gpio irq.
*/
writel(1 << hwirq,
info->base +
IRQ_STATUS + 4 * i);
goto update_status;
}
}
generic_handle_irq(virq);
update_status:
/* Update status in case a new IRQ appears */
raw_spin_lock_irqsave(&info->irq_lock, flags);
status = readl_relaxed(info->base +
IRQ_STATUS + 4 * i);
/* Manage only the interrupt that was enabled */
status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
raw_spin_unlock_irqrestore(&info->irq_lock, flags);
}
}
chained_irq_exit(chip, desc);
}
static unsigned int armada_37xx_irq_startup(struct irq_data *d)
{
/*
* The mask field is a "precomputed bitmask for accessing the
* chip registers" which was introduced for the generic
* irqchip framework. As we don't use this framework, we can
* reuse this field for our own usage.
*/
d->mask = BIT(d->hwirq % GPIO_PER_REG);
armada_37xx_irq_unmask(d);
return 0;
}
static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
seq_printf(p, info->data->name);
}
static const struct irq_chip armada_37xx_irqchip = {
.irq_ack = armada_37xx_irq_ack,
.irq_mask = armada_37xx_irq_mask,
.irq_unmask = armada_37xx_irq_unmask,
.irq_set_wake = armada_37xx_irq_set_wake,
.irq_set_type = armada_37xx_irq_set_type,
.irq_startup = armada_37xx_irq_startup,
.irq_print_chip = armada_37xx_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int armada_37xx_irqchip_register(struct platform_device *pdev,
struct armada_37xx_pinctrl *info)
{
struct gpio_chip *gc = &info->gpio_chip;
struct gpio_irq_chip *girq = &gc->irq;
struct device_node *np = to_of_node(gc->fwnode);
struct device *dev = &pdev->dev;
unsigned int i, nr_irq_parent;
raw_spin_lock_init(&info->irq_lock);
nr_irq_parent = of_irq_count(np);
if (!nr_irq_parent) {
dev_err(dev, "invalid or no IRQ\n");
return 0;
}
info->base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(info->base))
return PTR_ERR(info->base);
gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip);
girq->parent_handler = armada_37xx_irq_handler;
/*
* Many interrupts are connected to the parent interrupt
* controller. But we do not take advantage of this and use
* the chained irq with all of them.
*/
girq->num_parents = nr_irq_parent;
girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
for (i = 0; i < nr_irq_parent; i++) {
int irq = irq_of_parse_and_map(np, i);
if (!irq)
continue;
girq->parents[i] = irq;
}
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_edge_irq;
return 0;
}
static int armada_37xx_gpiochip_register(struct platform_device *pdev,
struct armada_37xx_pinctrl *info)
{
struct device *dev = &pdev->dev;
struct fwnode_handle *fwnode;
struct gpio_chip *gc;
int ret;
fwnode = gpiochip_node_get_first(dev);
if (!fwnode)
return -ENODEV;
info->gpio_chip = armada_37xx_gpiolib_chip;
gc = &info->gpio_chip;
gc->ngpio = info->data->nr_pins;
gc->parent = dev;
gc->base = -1;
gc->fwnode = fwnode;
gc->label = info->data->name;
ret = armada_37xx_irqchip_register(pdev, info);
if (ret)
return ret;
return devm_gpiochip_add_data(dev, gc, info);
}
/**
* armada_37xx_add_function() - Add a new function to the list
* @funcs: array of function to add the new one
* @funcsize: size of the remaining space for the function
* @name: name of the function to add
*
* If it is a new function then create it by adding its name else
* increment the number of group associated to this function.
*/
static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
int *funcsize, const char *name)
{
int i = 0;
if (*funcsize <= 0)
return -EOVERFLOW;
while (funcs->ngroups) {
/* function already there */
if (strcmp(funcs->name, name) == 0) {
funcs->ngroups++;
return -EEXIST;
}
funcs++;
i++;
}
/* append new unique function */
funcs->name = name;
funcs->ngroups = 1;
(*funcsize)--;
return 0;
}
/**
* armada_37xx_fill_group() - complete the group array
* @info: info driver instance
*
* Based on the data available from the armada_37xx_pin_group array
* completes the last member of the struct for each function: the list
* of the groups associated to this function.
*
*/
static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
{
int n, num = 0, funcsize = info->data->nr_pins;
struct device *dev = info->dev;
for (n = 0; n < info->ngroups; n++) {
struct armada_37xx_pin_group *grp = &info->groups[n];
int i, j, f;
grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
sizeof(*grp->pins),
GFP_KERNEL);
if (!grp->pins)
return -ENOMEM;
for (i = 0; i < grp->npins; i++)
grp->pins[i] = grp->start_pin + i;
for (j = 0; j < grp->extra_npins; j++)
grp->pins[i+j] = grp->extra_pin + j;
for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
int ret;
/* check for unique functions and count groups */
ret = armada_37xx_add_function(info->funcs, &funcsize,
grp->funcs[f]);
if (ret == -EOVERFLOW)
dev_err(dev, "More functions than pins(%d)\n",
info->data->nr_pins);
if (ret < 0)
continue;
num++;
}
}
info->nfuncs = num;
return 0;
}
/**
* armada_37xx_fill_func() - complete the funcs array
* @info: info driver instance
*
* Based on the data available from the armada_37xx_pin_group array
* completes the last two member of the struct for each group:
* - the list of the pins included in the group
* - the list of pinmux functions that can be selected for this group
*
*/
static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
{
struct armada_37xx_pmx_func *funcs = info->funcs;
struct device *dev = info->dev;
int n;
for (n = 0; n < info->nfuncs; n++) {
const char *name = funcs[n].name;
const char **groups;
int g;
funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
sizeof(*(funcs[n].groups)),
GFP_KERNEL);
if (!funcs[n].groups)
return -ENOMEM;
groups = funcs[n].groups;
for (g = 0; g < info->ngroups; g++) {
struct armada_37xx_pin_group *gp = &info->groups[g];
int f;
f = match_string(gp->funcs, NB_FUNCS, name);
if (f < 0)
continue;
*groups = gp->name;
groups++;
}
}
return 0;
}
static int armada_37xx_pinctrl_register(struct platform_device *pdev,
struct armada_37xx_pinctrl *info)
{
const struct armada_37xx_pin_data *pin_data = info->data;
struct pinctrl_desc *ctrldesc = &info->pctl;
struct pinctrl_pin_desc *pindesc, *pdesc;
struct device *dev = &pdev->dev;
char **pin_names;
int pin, ret;
info->groups = pin_data->groups;
info->ngroups = pin_data->ngroups;
ctrldesc->name = "armada_37xx-pinctrl";
ctrldesc->owner = THIS_MODULE;
ctrldesc->pctlops = &armada_37xx_pctrl_ops;
ctrldesc->pmxops = &armada_37xx_pmx_ops;
ctrldesc->confops = &armada_37xx_pinconf_ops;
pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
if (!pindesc)
return -ENOMEM;
ctrldesc->pins = pindesc;
ctrldesc->npins = pin_data->nr_pins;
pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins);
if (IS_ERR(pin_names))
return PTR_ERR(pin_names);
pdesc = pindesc;
for (pin = 0; pin < pin_data->nr_pins; pin++) {
pdesc->number = pin;
pdesc->name = pin_names[pin];
pdesc++;
}
/*
* we allocate functions for number of pins and hope there are
* fewer unique functions than pins available
*/
info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
if (!info->funcs)
return -ENOMEM;
ret = armada_37xx_fill_group(info);
if (ret)
return ret;
ret = armada_37xx_fill_func(info);
if (ret)
return ret;
info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
if (IS_ERR(info->pctl_dev))
return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
return 0;
}
static int armada_3700_pinctrl_suspend(struct device *dev)
{
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
/* Save GPIO state */
regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
&info->pm.out_val_h);
info->pm.irq_en_l = readl(info->base + IRQ_EN);
info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
info->pm.irq_pol_l = readl(info->base + IRQ_POL);
info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
/* Save pinctrl state */
regmap_read(info->regmap, SELECTION, &info->pm.selection);
return 0;
}
static int armada_3700_pinctrl_resume(struct device *dev)
{
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
struct gpio_chip *gc;
struct irq_domain *d;
int i;
/* Restore GPIO state */
regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
info->pm.out_en_h);
regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
info->pm.out_val_h);
/*
* Input levels may change during suspend, which is not monitored at
* that time. GPIOs used for both-edge IRQs may not be synchronized
* anymore with their polarities (rising/falling edge) and must be
* re-configured manually.
*/
gc = &info->gpio_chip;
d = gc->irq.domain;
for (i = 0; i < gc->ngpio; i++) {
u32 irq_bit = BIT(i % GPIO_PER_REG);
u32 mask, *irq_pol, input_reg, virq, type, level;
if (i < GPIO_PER_REG) {
mask = info->pm.irq_en_l;
irq_pol = &info->pm.irq_pol_l;
input_reg = INPUT_VAL;
} else {
mask = info->pm.irq_en_h;
irq_pol = &info->pm.irq_pol_h;
input_reg = INPUT_VAL + sizeof(u32);
}
if (!(mask & irq_bit))
continue;
virq = irq_find_mapping(d, i);
type = irq_get_trigger_type(virq);
/*
* Synchronize level and polarity for both-edge irqs:
* - a high input level expects a falling edge,
* - a low input level exepects a rising edge.
*/
if ((type & IRQ_TYPE_SENSE_MASK) ==
IRQ_TYPE_EDGE_BOTH) {
regmap_read(info->regmap, input_reg, &level);
if ((*irq_pol ^ level) & irq_bit)
*irq_pol ^= irq_bit;
}
}
writel(info->pm.irq_en_l, info->base + IRQ_EN);
writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
writel(info->pm.irq_pol_l, info->base + IRQ_POL);
writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
/* Restore pinctrl state */
regmap_write(info->regmap, SELECTION, info->pm.selection);
return 0;
}
/*
* Since pinctrl is an infrastructure module, its resume should be issued prior
* to other IO drivers.
*/
static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops,
armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume);
static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
{
.compatible = "marvell,armada3710-sb-pinctrl",
.data = &armada_37xx_pin_sb,
},
{
.compatible = "marvell,armada3710-nb-pinctrl",
.data = &armada_37xx_pin_nb,
},
{ },
};
static const struct regmap_config armada_37xx_pinctrl_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.use_raw_spinlock = true,
};
static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
{
struct armada_37xx_pinctrl *info;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int ret;
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(base)) {
dev_err(dev, "failed to ioremap base address: %pe\n", base);
return PTR_ERR(base);
}
regmap = devm_regmap_init_mmio(dev, base,
&armada_37xx_pinctrl_regmap_config);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to create regmap: %pe\n", regmap);
return PTR_ERR(regmap);
}
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->dev = dev;
info->regmap = regmap;
info->data = of_device_get_match_data(dev);
ret = armada_37xx_pinctrl_register(pdev, info);
if (ret)
return ret;
ret = armada_37xx_gpiochip_register(pdev, info);
if (ret)
return ret;
platform_set_drvdata(pdev, info);
return 0;
}
static struct platform_driver armada_37xx_pinctrl_driver = {
.driver = {
.name = "armada-37xx-pinctrl",
.of_match_table = armada_37xx_pinctrl_of_match,
.pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops),
},
};
builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
armada_37xx_pinctrl_probe);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada 375 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad2"),
MPP_FUNCTION(0x2, "spi0", "cs1"),
MPP_FUNCTION(0x3, "spi1", "cs1"),
MPP_FUNCTION(0x5, "nand", "io2")),
MPP_MODE(1,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad3"),
MPP_FUNCTION(0x2, "spi0", "mosi"),
MPP_FUNCTION(0x3, "spi1", "mosi"),
MPP_FUNCTION(0x5, "nand", "io3")),
MPP_MODE(2,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad4"),
MPP_FUNCTION(0x2, "ptp", "evreq"),
MPP_FUNCTION(0x3, "led", "c0"),
MPP_FUNCTION(0x4, "audio", "sdi"),
MPP_FUNCTION(0x5, "nand", "io4"),
MPP_FUNCTION(0x6, "spi1", "mosi")),
MPP_MODE(3,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad5"),
MPP_FUNCTION(0x2, "ptp", "trig"),
MPP_FUNCTION(0x3, "led", "p3"),
MPP_FUNCTION(0x4, "audio", "mclk"),
MPP_FUNCTION(0x5, "nand", "io5"),
MPP_FUNCTION(0x6, "spi1", "miso")),
MPP_MODE(4,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad6"),
MPP_FUNCTION(0x2, "spi0", "miso"),
MPP_FUNCTION(0x3, "spi1", "miso"),
MPP_FUNCTION(0x5, "nand", "io6")),
MPP_MODE(5,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad7"),
MPP_FUNCTION(0x2, "spi0", "cs2"),
MPP_FUNCTION(0x3, "spi1", "cs2"),
MPP_FUNCTION(0x5, "nand", "io7"),
MPP_FUNCTION(0x6, "spi1", "miso")),
MPP_MODE(6,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad0"),
MPP_FUNCTION(0x3, "led", "p1"),
MPP_FUNCTION(0x4, "audio", "lrclk"),
MPP_FUNCTION(0x5, "nand", "io0")),
MPP_MODE(7,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad1"),
MPP_FUNCTION(0x2, "ptp", "clk"),
MPP_FUNCTION(0x3, "led", "p2"),
MPP_FUNCTION(0x4, "audio", "extclk"),
MPP_FUNCTION(0x5, "nand", "io1")),
MPP_MODE(8,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "bootcs"),
MPP_FUNCTION(0x2, "spi0", "cs0"),
MPP_FUNCTION(0x3, "spi1", "cs0"),
MPP_FUNCTION(0x5, "nand", "ce")),
MPP_MODE(9,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "spi0", "sck"),
MPP_FUNCTION(0x3, "spi1", "sck"),
MPP_FUNCTION(0x5, "nand", "we")),
MPP_MODE(10,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "dram", "vttctrl"),
MPP_FUNCTION(0x3, "led", "c1"),
MPP_FUNCTION(0x5, "nand", "re"),
MPP_FUNCTION(0x6, "spi1", "sck")),
MPP_MODE(11,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "a0"),
MPP_FUNCTION(0x3, "led", "c2"),
MPP_FUNCTION(0x4, "audio", "sdo"),
MPP_FUNCTION(0x5, "nand", "cle")),
MPP_MODE(12,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "a1"),
MPP_FUNCTION(0x4, "audio", "bclk"),
MPP_FUNCTION(0x5, "nand", "ale")),
MPP_MODE(13,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ready"),
MPP_FUNCTION(0x2, "pcie0", "rstout"),
MPP_FUNCTION(0x3, "pcie1", "rstout"),
MPP_FUNCTION(0x5, "nand", "rb"),
MPP_FUNCTION(0x6, "spi1", "mosi")),
MPP_MODE(14,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "i2c0", "sda"),
MPP_FUNCTION(0x3, "uart1", "txd")),
MPP_MODE(15,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "i2c0", "sck"),
MPP_FUNCTION(0x3, "uart1", "rxd")),
MPP_MODE(16,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "uart0", "txd")),
MPP_MODE(17,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "uart0", "rxd")),
MPP_MODE(18,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "int")),
MPP_MODE(19,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "rst")),
MPP_MODE(20,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "pclk")),
MPP_MODE(21,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "fsync")),
MPP_MODE(22,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "drx")),
MPP_MODE(23,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "tdm", "dtx")),
MPP_MODE(24,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p0"),
MPP_FUNCTION(0x2, "ge1", "rxd0"),
MPP_FUNCTION(0x3, "sd", "cmd"),
MPP_FUNCTION(0x4, "uart0", "rts"),
MPP_FUNCTION(0x5, "spi0", "cs0"),
MPP_FUNCTION(0x6, "dev", "cs1")),
MPP_MODE(25,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p2"),
MPP_FUNCTION(0x2, "ge1", "rxd1"),
MPP_FUNCTION(0x3, "sd", "d0"),
MPP_FUNCTION(0x4, "uart0", "cts"),
MPP_FUNCTION(0x5, "spi0", "mosi"),
MPP_FUNCTION(0x6, "dev", "cs2")),
MPP_MODE(26,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "clkreq"),
MPP_FUNCTION(0x2, "ge1", "rxd2"),
MPP_FUNCTION(0x3, "sd", "d2"),
MPP_FUNCTION(0x4, "uart1", "rts"),
MPP_FUNCTION(0x5, "spi0", "cs1"),
MPP_FUNCTION(0x6, "led", "c1")),
MPP_MODE(27,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie1", "clkreq"),
MPP_FUNCTION(0x2, "ge1", "rxd3"),
MPP_FUNCTION(0x3, "sd", "d1"),
MPP_FUNCTION(0x4, "uart1", "cts"),
MPP_FUNCTION(0x5, "spi0", "miso"),
MPP_FUNCTION(0x6, "led", "c2")),
MPP_MODE(28,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p3"),
MPP_FUNCTION(0x2, "ge1", "txctl"),
MPP_FUNCTION(0x3, "sd", "clk"),
MPP_FUNCTION(0x5, "dram", "vttctrl")),
MPP_MODE(29,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie1", "clkreq"),
MPP_FUNCTION(0x2, "ge1", "rxclk"),
MPP_FUNCTION(0x3, "sd", "d3"),
MPP_FUNCTION(0x5, "spi0", "sck"),
MPP_FUNCTION(0x6, "pcie0", "rstout")),
MPP_MODE(30,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd0"),
MPP_FUNCTION(0x3, "spi1", "cs0"),
MPP_FUNCTION(0x5, "led", "p3"),
MPP_FUNCTION(0x6, "ptp", "evreq")),
MPP_MODE(31,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd1"),
MPP_FUNCTION(0x3, "spi1", "mosi"),
MPP_FUNCTION(0x5, "led", "p0")),
MPP_MODE(32,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd2"),
MPP_FUNCTION(0x3, "spi1", "sck"),
MPP_FUNCTION(0x4, "ptp", "trig"),
MPP_FUNCTION(0x5, "led", "c0")),
MPP_MODE(33,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txd3"),
MPP_FUNCTION(0x3, "spi1", "miso"),
MPP_FUNCTION(0x5, "led", "p2")),
MPP_MODE(34,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "txclkout"),
MPP_FUNCTION(0x3, "spi1", "sck"),
MPP_FUNCTION(0x5, "led", "c1")),
MPP_MODE(35,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge1", "rxctl"),
MPP_FUNCTION(0x3, "spi1", "cs1"),
MPP_FUNCTION(0x4, "spi0", "cs2"),
MPP_FUNCTION(0x5, "led", "p1")),
MPP_MODE(36,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "clkreq"),
MPP_FUNCTION(0x5, "led", "c2")),
MPP_MODE(37,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "clkreq"),
MPP_FUNCTION(0x2, "tdm", "int"),
MPP_FUNCTION(0x4, "ge", "mdc")),
MPP_MODE(38,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie1", "clkreq"),
MPP_FUNCTION(0x4, "ge", "mdio")),
MPP_MODE(39,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "ref", "clkout"),
MPP_FUNCTION(0x5, "led", "p3")),
MPP_MODE(40,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "uart1", "txd"),
MPP_FUNCTION(0x5, "led", "p0")),
MPP_MODE(41,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "uart1", "rxd"),
MPP_FUNCTION(0x5, "led", "p1")),
MPP_MODE(42,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x3, "spi1", "cs2"),
MPP_FUNCTION(0x4, "led", "c0"),
MPP_FUNCTION(0x6, "ptp", "clk")),
MPP_MODE(43,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "dram", "vttctrl"),
MPP_FUNCTION(0x5, "led", "c1")),
MPP_MODE(44,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "sata0", "prsnt")),
MPP_MODE(45,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "spi0", "cs2"),
MPP_FUNCTION(0x4, "pcie0", "rstout"),
MPP_FUNCTION(0x5, "led", "c2"),
MPP_FUNCTION(0x6, "spi1", "cs2")),
MPP_MODE(46,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p0"),
MPP_FUNCTION(0x2, "ge0", "txd0"),
MPP_FUNCTION(0x3, "ge1", "txd0"),
MPP_FUNCTION(0x6, "dev", "we1")),
MPP_MODE(47,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p1"),
MPP_FUNCTION(0x2, "ge0", "txd1"),
MPP_FUNCTION(0x3, "ge1", "txd1"),
MPP_FUNCTION(0x5, "ptp", "trig"),
MPP_FUNCTION(0x6, "dev", "ale0")),
MPP_MODE(48,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p2"),
MPP_FUNCTION(0x2, "ge0", "txd2"),
MPP_FUNCTION(0x3, "ge1", "txd2"),
MPP_FUNCTION(0x6, "dev", "ale1")),
MPP_MODE(49,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "p3"),
MPP_FUNCTION(0x2, "ge0", "txd3"),
MPP_FUNCTION(0x3, "ge1", "txd3"),
MPP_FUNCTION(0x6, "dev", "a2")),
MPP_MODE(50,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "c0"),
MPP_FUNCTION(0x2, "ge0", "rxd0"),
MPP_FUNCTION(0x3, "ge1", "rxd0"),
MPP_FUNCTION(0x5, "ptp", "evreq"),
MPP_FUNCTION(0x6, "dev", "ad12")),
MPP_MODE(51,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "c1"),
MPP_FUNCTION(0x2, "ge0", "rxd1"),
MPP_FUNCTION(0x3, "ge1", "rxd1"),
MPP_FUNCTION(0x6, "dev", "ad8")),
MPP_MODE(52,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "led", "c2"),
MPP_FUNCTION(0x2, "ge0", "rxd2"),
MPP_FUNCTION(0x3, "ge1", "rxd2"),
MPP_FUNCTION(0x5, "i2c0", "sda"),
MPP_FUNCTION(0x6, "dev", "ad9")),
MPP_MODE(53,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie1", "rstout"),
MPP_FUNCTION(0x2, "ge0", "rxd3"),
MPP_FUNCTION(0x3, "ge1", "rxd3"),
MPP_FUNCTION(0x5, "i2c0", "sck"),
MPP_FUNCTION(0x6, "dev", "ad10")),
MPP_MODE(54,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "pcie0", "rstout"),
MPP_FUNCTION(0x2, "ge0", "rxctl"),
MPP_FUNCTION(0x3, "ge1", "rxctl"),
MPP_FUNCTION(0x6, "dev", "ad11")),
MPP_MODE(55,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge0", "rxclk"),
MPP_FUNCTION(0x3, "ge1", "rxclk"),
MPP_FUNCTION(0x6, "dev", "cs0")),
MPP_MODE(56,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge0", "txclkout"),
MPP_FUNCTION(0x3, "ge1", "txclkout"),
MPP_FUNCTION(0x6, "dev", "oe")),
MPP_MODE(57,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ge0", "txctl"),
MPP_FUNCTION(0x3, "ge1", "txctl"),
MPP_FUNCTION(0x6, "dev", "we0")),
MPP_MODE(58,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "led", "c0")),
MPP_MODE(59,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x4, "led", "c1")),
MPP_MODE(60,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x4, "led", "c2"),
MPP_FUNCTION(0x6, "dev", "ad13")),
MPP_MODE(61,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c1", "sda"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "spi1", "cs2"),
MPP_FUNCTION(0x4, "led", "p0"),
MPP_FUNCTION(0x6, "dev", "ad14")),
MPP_MODE(62,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c1", "sck"),
MPP_FUNCTION(0x4, "led", "p1"),
MPP_FUNCTION(0x6, "dev", "ad15")),
MPP_MODE(63,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ptp", "trig"),
MPP_FUNCTION(0x4, "led", "p2"),
MPP_FUNCTION(0x6, "dev", "burst/last")),
MPP_MODE(64,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "dram", "vttctrl"),
MPP_FUNCTION(0x4, "led", "p3")),
MPP_MODE(65,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "sata1", "prsnt")),
MPP_MODE(66,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x2, "ptp", "evreq"),
MPP_FUNCTION(0x4, "spi1", "cs3"),
MPP_FUNCTION(0x5, "pcie0", "rstout"),
MPP_FUNCTION(0x6, "dev", "cs3")),
};
static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info;
static const struct of_device_id armada_375_pinctrl_of_match[] = {
{ .compatible = "marvell,mv88f6720-pinctrl" },
{ },
};
static const struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = {
MPP_FUNC_CTRL(0, 69, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 3),
};
static int armada_375_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info;
soc->variant = 0; /* no variants for Armada 375 */
soc->controls = mv88f6720_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv88f6720_mpp_controls);
soc->modes = mv88f6720_mpp_modes;
soc->nmodes = ARRAY_SIZE(mv88f6720_mpp_modes);
soc->gpioranges = mv88f6720_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv88f6720_mpp_gpio_ranges);
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver armada_375_pinctrl_driver = {
.driver = {
.name = "armada-375-pinctrl",
.of_match_table = of_match_ptr(armada_375_pinctrl_of_match),
},
.probe = armada_375_pinctrl_probe,
};
builtin_platform_driver(armada_375_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-375.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell MVEBU pinctrl core driver
*
* Authors: Sebastian Hesselbarth <[email protected]>
* Thomas Petazzoni <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-mvebu.h"
#define MPPS_PER_REG 8
#define MPP_BITS 4
#define MPP_MASK 0xf
struct mvebu_pinctrl_function {
const char *name;
const char **groups;
unsigned num_groups;
};
struct mvebu_pinctrl_group {
const char *name;
const struct mvebu_mpp_ctrl *ctrl;
struct mvebu_mpp_ctrl_data *data;
struct mvebu_mpp_ctrl_setting *settings;
unsigned num_settings;
unsigned gid;
unsigned *pins;
unsigned npins;
};
struct mvebu_pinctrl {
struct device *dev;
struct pinctrl_dev *pctldev;
struct pinctrl_desc desc;
struct mvebu_pinctrl_group *groups;
unsigned num_groups;
struct mvebu_pinctrl_function *functions;
unsigned num_functions;
u8 variant;
};
int mvebu_mmio_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
unsigned int pid, unsigned long *config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
*config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK;
return 0;
}
int mvebu_mmio_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
unsigned int pid, unsigned long config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned long reg;
reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift);
writel(reg | (config << shift), data->base + off);
return 0;
}
static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
struct mvebu_pinctrl *pctl, unsigned pid)
{
unsigned n;
for (n = 0; n < pctl->num_groups; n++) {
if (pid >= pctl->groups[n].pins[0] &&
pid < pctl->groups[n].pins[0] +
pctl->groups[n].npins)
return &pctl->groups[n];
}
return NULL;
}
static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
struct mvebu_pinctrl *pctl, const char *name)
{
unsigned n;
for (n = 0; n < pctl->num_groups; n++) {
if (strcmp(name, pctl->groups[n].name) == 0)
return &pctl->groups[n];
}
return NULL;
}
static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
unsigned long config)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (config == grp->settings[n].val) {
if (!pctl->variant || (pctl->variant &
grp->settings[n].variant))
return &grp->settings[n];
}
}
return NULL;
}
static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
const char *name)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (strcmp(name, grp->settings[n].name) == 0) {
if (!pctl->variant || (pctl->variant &
grp->settings[n].variant))
return &grp->settings[n];
}
}
return NULL;
}
static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
{
unsigned n;
for (n = 0; n < grp->num_settings; n++) {
if (grp->settings[n].flags &
(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
if (!pctl->variant || (pctl->variant &
grp->settings[n].variant))
return &grp->settings[n];
}
}
return NULL;
}
static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
struct mvebu_pinctrl *pctl, const char *name)
{
unsigned n;
for (n = 0; n < pctl->num_functions; n++) {
if (strcmp(name, pctl->functions[n].name) == 0)
return &pctl->functions[n];
}
return NULL;
}
static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned gid, unsigned long *config)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
if (!grp->ctrl)
return -EINVAL;
return grp->ctrl->mpp_get(grp->data, grp->pins[0], config);
}
static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned gid, unsigned long *configs,
unsigned num_configs)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
int i, ret;
if (!grp->ctrl)
return -EINVAL;
for (i = 0; i < num_configs; i++) {
ret = grp->ctrl->mpp_set(grp->data, grp->pins[0], configs[i]);
if (ret)
return ret;
} /* for each config */
return 0;
}
static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned gid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
struct mvebu_mpp_ctrl_setting *curr;
unsigned long config;
unsigned n;
if (mvebu_pinconf_group_get(pctldev, gid, &config))
return;
curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
if (curr) {
seq_printf(s, "current: %s", curr->name);
if (curr->subname)
seq_printf(s, "(%s)", curr->subname);
if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
seq_putc(s, '(');
if (curr->flags & MVEBU_SETTING_GPI)
seq_putc(s, 'i');
if (curr->flags & MVEBU_SETTING_GPO)
seq_putc(s, 'o');
seq_putc(s, ')');
}
} else {
seq_puts(s, "current: UNKNOWN");
}
if (grp->num_settings > 1) {
seq_puts(s, ", available = [");
for (n = 0; n < grp->num_settings; n++) {
if (curr == &grp->settings[n])
continue;
/* skip unsupported settings for this variant */
if (pctl->variant &&
!(pctl->variant & grp->settings[n].variant))
continue;
seq_printf(s, " %s", grp->settings[n].name);
if (grp->settings[n].subname)
seq_printf(s, "(%s)", grp->settings[n].subname);
if (grp->settings[n].flags &
(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
seq_putc(s, '(');
if (grp->settings[n].flags & MVEBU_SETTING_GPI)
seq_putc(s, 'i');
if (grp->settings[n].flags & MVEBU_SETTING_GPO)
seq_putc(s, 'o');
seq_putc(s, ')');
}
}
seq_puts(s, " ]");
}
}
static const struct pinconf_ops mvebu_pinconf_ops = {
.pin_config_group_get = mvebu_pinconf_group_get,
.pin_config_group_set = mvebu_pinconf_group_set,
.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
};
static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->num_functions;
}
static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
unsigned fid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->functions[fid].name;
}
static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
const char * const **groups,
unsigned * const num_groups)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->functions[fid].groups;
*num_groups = pctl->functions[fid].num_groups;
return 0;
}
static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid,
unsigned gid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_function *func = &pctl->functions[fid];
struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
struct mvebu_mpp_ctrl_setting *setting;
int ret;
unsigned long config;
setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
func->name);
if (!setting) {
dev_err(pctl->dev,
"unable to find setting %s in group %s\n",
func->name, func->groups[gid]);
return -EINVAL;
}
config = setting->val;
ret = mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1);
if (ret) {
dev_err(pctl->dev, "cannot set group %s to %s\n",
func->groups[gid], func->name);
return ret;
}
return 0;
}
static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp;
struct mvebu_mpp_ctrl_setting *setting;
unsigned long config;
grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
if (!grp)
return -EINVAL;
if (grp->ctrl->mpp_gpio_req)
return grp->ctrl->mpp_gpio_req(grp->data, offset);
setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
if (!setting)
return -ENOTSUPP;
config = setting->val;
return mvebu_pinconf_group_set(pctldev, grp->gid, &config, 1);
}
static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_group *grp;
struct mvebu_mpp_ctrl_setting *setting;
grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
if (!grp)
return -EINVAL;
if (grp->ctrl->mpp_gpio_dir)
return grp->ctrl->mpp_gpio_dir(grp->data, offset, input);
setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
if (!setting)
return -ENOTSUPP;
if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
(!input && (setting->flags & MVEBU_SETTING_GPO)))
return 0;
return -ENOTSUPP;
}
static const struct pinmux_ops mvebu_pinmux_ops = {
.get_functions_count = mvebu_pinmux_get_funcs_count,
.get_function_name = mvebu_pinmux_get_func_name,
.get_function_groups = mvebu_pinmux_get_groups,
.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
.set_mux = mvebu_pinmux_set,
};
static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->num_groups;
}
static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned gid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[gid].name;
}
static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned gid, const unsigned **pins,
unsigned *num_pins)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctl->groups[gid].pins;
*num_pins = pctl->groups[gid].npins;
return 0;
}
static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct property *prop;
const char *function;
const char *group;
int ret, nmaps, n;
*map = NULL;
*num_maps = 0;
ret = of_property_read_string(np, "marvell,function", &function);
if (ret) {
dev_err(pctl->dev,
"missing marvell,function in node %pOFn\n", np);
return 0;
}
nmaps = of_property_count_strings(np, "marvell,pins");
if (nmaps < 0) {
dev_err(pctl->dev,
"missing marvell,pins in node %pOFn\n", np);
return 0;
}
*map = kmalloc_array(nmaps, sizeof(**map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
n = 0;
of_property_for_each_string(np, "marvell,pins", prop, group) {
struct mvebu_pinctrl_group *grp =
mvebu_pinctrl_find_group_by_name(pctl, group);
if (!grp) {
dev_err(pctl->dev, "unknown pin %s", group);
continue;
}
if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
dev_err(pctl->dev, "unsupported function %s on pin %s",
function, group);
continue;
}
(*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[n].data.mux.group = group;
(*map)[n].data.mux.function = function;
n++;
}
*num_maps = nmaps;
return 0;
}
static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops mvebu_pinctrl_ops = {
.get_groups_count = mvebu_pinctrl_get_groups_count,
.get_group_name = mvebu_pinctrl_get_group_name,
.get_group_pins = mvebu_pinctrl_get_group_pins,
.dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
.dt_free_map = mvebu_pinctrl_dt_free_map,
};
static int _add_function(struct mvebu_pinctrl_function *funcs, int *funcsize,
const char *name)
{
if (*funcsize <= 0)
return -EOVERFLOW;
while (funcs->num_groups) {
/* function already there */
if (strcmp(funcs->name, name) == 0) {
funcs->num_groups++;
return -EEXIST;
}
funcs++;
}
/* append new unique function */
funcs->name = name;
funcs->num_groups = 1;
(*funcsize)--;
return 0;
}
static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
struct mvebu_pinctrl *pctl)
{
struct mvebu_pinctrl_function *funcs;
int num = 0, funcsize = pctl->desc.npins;
int n, s;
/* we allocate functions for number of pins and hope
* there are fewer unique functions than pins available */
funcs = devm_kcalloc(&pdev->dev,
funcsize, sizeof(struct mvebu_pinctrl_function),
GFP_KERNEL);
if (!funcs)
return -ENOMEM;
for (n = 0; n < pctl->num_groups; n++) {
struct mvebu_pinctrl_group *grp = &pctl->groups[n];
for (s = 0; s < grp->num_settings; s++) {
int ret;
/* skip unsupported settings on this variant */
if (pctl->variant &&
!(pctl->variant & grp->settings[s].variant))
continue;
/* check for unique functions and count groups */
ret = _add_function(funcs, &funcsize,
grp->settings[s].name);
if (ret == -EOVERFLOW)
dev_err(&pdev->dev,
"More functions than pins(%d)\n",
pctl->desc.npins);
if (ret < 0)
continue;
num++;
}
}
pctl->num_functions = num;
pctl->functions = funcs;
for (n = 0; n < pctl->num_groups; n++) {
struct mvebu_pinctrl_group *grp = &pctl->groups[n];
for (s = 0; s < grp->num_settings; s++) {
struct mvebu_pinctrl_function *f;
const char **groups;
/* skip unsupported settings on this variant */
if (pctl->variant &&
!(pctl->variant & grp->settings[s].variant))
continue;
f = mvebu_pinctrl_find_function_by_name(pctl,
grp->settings[s].name);
/* allocate group name array if not done already */
if (!f->groups) {
f->groups = devm_kcalloc(&pdev->dev,
f->num_groups,
sizeof(char *),
GFP_KERNEL);
if (!f->groups)
return -ENOMEM;
}
/* find next free group name and assign current name */
groups = f->groups;
while (*groups)
groups++;
*groups = grp->name;
}
}
return 0;
}
int mvebu_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct mvebu_pinctrl *pctl;
struct pinctrl_pin_desc *pdesc;
unsigned gid, n, k;
unsigned size, noname = 0;
char *noname_buf;
void *p;
int ret;
if (!soc || !soc->controls || !soc->modes) {
dev_err(&pdev->dev, "wrong pinctrl soc info\n");
return -EINVAL;
}
pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->desc.name = dev_name(&pdev->dev);
pctl->desc.owner = THIS_MODULE;
pctl->desc.pctlops = &mvebu_pinctrl_ops;
pctl->desc.pmxops = &mvebu_pinmux_ops;
pctl->desc.confops = &mvebu_pinconf_ops;
pctl->variant = soc->variant;
pctl->dev = &pdev->dev;
platform_set_drvdata(pdev, pctl);
/* count controls and create names for mvebu generic
register controls; also does sanity checks */
pctl->num_groups = 0;
pctl->desc.npins = 0;
for (n = 0; n < soc->ncontrols; n++) {
const struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
pctl->desc.npins += ctrl->npins;
/* initialize control's pins[] array */
for (k = 0; k < ctrl->npins; k++)
ctrl->pins[k] = ctrl->pid + k;
/*
* We allow to pass controls with NULL name that we treat
* as a range of one-pin groups with generic mvebu register
* controls.
*/
if (!ctrl->name) {
pctl->num_groups += ctrl->npins;
noname += ctrl->npins;
} else {
pctl->num_groups += 1;
}
}
pdesc = devm_kcalloc(&pdev->dev,
pctl->desc.npins,
sizeof(struct pinctrl_pin_desc),
GFP_KERNEL);
if (!pdesc)
return -ENOMEM;
for (n = 0; n < pctl->desc.npins; n++)
pdesc[n].number = n;
pctl->desc.pins = pdesc;
/*
* allocate groups and name buffers for unnamed groups.
*/
size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8;
p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pctl->groups = p;
noname_buf = p + pctl->num_groups * sizeof(*pctl->groups);
/* assign mpp controls to groups */
gid = 0;
for (n = 0; n < soc->ncontrols; n++) {
const struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
struct mvebu_mpp_ctrl_data *data = soc->control_data ?
&soc->control_data[n] : NULL;
pctl->groups[gid].gid = gid;
pctl->groups[gid].ctrl = ctrl;
pctl->groups[gid].data = data;
pctl->groups[gid].name = ctrl->name;
pctl->groups[gid].pins = ctrl->pins;
pctl->groups[gid].npins = ctrl->npins;
/*
* We treat unnamed controls as a range of one-pin groups
* with generic mvebu register controls. Use one group for
* each in this range and assign a default group name.
*/
if (!ctrl->name) {
pctl->groups[gid].name = noname_buf;
pctl->groups[gid].npins = 1;
sprintf(noname_buf, "mpp%d", ctrl->pid+0);
noname_buf += 8;
for (k = 1; k < ctrl->npins; k++) {
gid++;
pctl->groups[gid].gid = gid;
pctl->groups[gid].ctrl = ctrl;
pctl->groups[gid].data = data;
pctl->groups[gid].name = noname_buf;
pctl->groups[gid].pins = &ctrl->pins[k];
pctl->groups[gid].npins = 1;
sprintf(noname_buf, "mpp%d", ctrl->pid+k);
noname_buf += 8;
}
}
gid++;
}
/* assign mpp modes to groups */
for (n = 0; n < soc->nmodes; n++) {
struct mvebu_mpp_mode *mode = &soc->modes[n];
struct mvebu_mpp_ctrl_setting *set = &mode->settings[0];
struct mvebu_pinctrl_group *grp;
unsigned num_settings;
unsigned supp_settings;
for (num_settings = 0, supp_settings = 0; ; set++) {
if (!set->name)
break;
num_settings++;
/* skip unsupported settings for this variant */
if (pctl->variant && !(pctl->variant & set->variant))
continue;
supp_settings++;
/* find gpio/gpo/gpi settings */
if (strcmp(set->name, "gpio") == 0)
set->flags = MVEBU_SETTING_GPI |
MVEBU_SETTING_GPO;
else if (strcmp(set->name, "gpo") == 0)
set->flags = MVEBU_SETTING_GPO;
else if (strcmp(set->name, "gpi") == 0)
set->flags = MVEBU_SETTING_GPI;
}
/* skip modes with no settings for this variant */
if (!supp_settings)
continue;
grp = mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
if (!grp) {
dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
mode->pid);
continue;
}
grp->settings = mode->settings;
grp->num_settings = num_settings;
}
ret = mvebu_pinctrl_build_functions(pdev, pctl);
if (ret) {
dev_err(&pdev->dev, "unable to build functions\n");
return ret;
}
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->desc, pctl);
if (IS_ERR(pctl->pctldev)) {
dev_err(&pdev->dev, "unable to register pinctrl driver\n");
return PTR_ERR(pctl->pctldev);
}
dev_info(&pdev->dev, "registered pinctrl driver\n");
/* register gpio ranges */
for (n = 0; n < soc->ngpioranges; n++)
pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
return 0;
}
/*
* mvebu_pinctrl_simple_mmio_probe - probe a simple mmio pinctrl
* @pdev: platform device (with platform data already attached)
*
* Initialise a simple (single base address) mmio pinctrl driver,
* assigning the MMIO base address to all mvebu mpp ctrl instances.
*/
int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct mvebu_mpp_ctrl_data *mpp_data;
void __iomem *base;
int i;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data),
GFP_KERNEL);
if (!mpp_data)
return -ENOMEM;
for (i = 0; i < soc->ncontrols; i++)
mpp_data[i].base = base;
soc->control_data = mpp_data;
return mvebu_pinctrl_probe(pdev);
}
int mvebu_regmap_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
unsigned int pid, unsigned long *config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned int val;
int err;
err = regmap_read(data->regmap.map, data->regmap.offset + off, &val);
if (err)
return err;
*config = (val >> shift) & MVEBU_MPP_MASK;
return 0;
}
int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
unsigned int pid, unsigned long config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
return regmap_update_bits(data->regmap.map, data->regmap.offset + off,
MVEBU_MPP_MASK << shift, config << shift);
}
int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
struct device *syscon_dev, u32 offset)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct mvebu_mpp_ctrl_data *mpp_data;
struct regmap *regmap;
int i;
regmap = syscon_node_to_regmap(syscon_dev->of_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data),
GFP_KERNEL);
if (!mpp_data)
return -ENOMEM;
for (i = 0; i < soc->ncontrols; i++) {
mpp_data[i].regmap.map = regmap;
mpp_data[i].regmap.offset = offset;
}
soc->control_data = mpp_data;
return mvebu_pinctrl_probe(pdev);
}
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-mvebu.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada XP pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <[email protected]>
*
* This file supports the three variants of Armada XP SoCs that are
* available: mv78230, mv78260 and mv78460. From a pin muxing
* perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
* both have 67 MPP pins (more GPIOs and address lines for the memory
* bus mainly).
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/bitops.h>
#include "pinctrl-mvebu.h"
static u32 *mpp_saved_regs;
enum armada_xp_variant {
V_MV78230 = BIT(0),
V_MV78260 = BIT(1),
V_MV78460 = BIT(2),
V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
V_MV78260_PLUS = (V_MV78260 | V_MV78460),
V_98DX3236 = BIT(3),
V_98DX3336 = BIT(4),
V_98DX4251 = BIT(5),
V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
};
static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
MPP_MODE(20,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
MPP_MODE(21,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
MPP_MODE(23,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
MPP_MODE(24,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
MPP_MODE(29,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)),
MPP_MODE(33,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)),
MPP_MODE(41,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)),
MPP_MODE(42,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)),
MPP_MODE(43,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)),
MPP_MODE(44,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)),
MPP_MODE(45,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)),
MPP_MODE(46,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)),
MPP_MODE(47,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS),
MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)),
MPP_MODE(49,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
MPP_MODE(50,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
MPP_MODE(52,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
MPP_MODE(53,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
MPP_MODE(54,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)),
MPP_MODE(56,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)),
MPP_MODE(57,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)),
MPP_MODE(58,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
MPP_MODE(59,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
MPP_MODE(60,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
MPP_MODE(61,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
MPP_MODE(62,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
MPP_MODE(63,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
MPP_MODE(64,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
MPP_MODE(65,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
MPP_MODE(66,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
};
static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)),
MPP_MODE(13,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)),
MPP_MODE(14,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
MPP_MODE(15,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "i2c0", "sda", V_98DX3236_PLUS)),
MPP_MODE(16,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),
MPP_MODE(17,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)),
MPP_MODE(18,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
MPP_MODE(19,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "nand", "rb", V_98DX3236_PLUS)),
MPP_MODE(20,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
MPP_MODE(21,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad0", V_98DX3236_PLUS)),
MPP_MODE(22,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad1", V_98DX3236_PLUS)),
MPP_MODE(23,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad2", V_98DX3236_PLUS)),
MPP_MODE(24,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad3", V_98DX3236_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad4", V_98DX3236_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad5", V_98DX3236_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad6", V_98DX3236_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "ad7", V_98DX3236_PLUS)),
MPP_MODE(29,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "a0", V_98DX3236_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "a1", V_98DX3236_PLUS)),
MPP_MODE(31,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)),
};
static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
static const struct of_device_id armada_xp_pinctrl_of_match[] = {
{
.compatible = "marvell,mv78230-pinctrl",
.data = (void *) V_MV78230,
},
{
.compatible = "marvell,mv78260-pinctrl",
.data = (void *) V_MV78260,
},
{
.compatible = "marvell,mv78460-pinctrl",
.data = (void *) V_MV78460,
},
{
.compatible = "marvell,98dx3236-pinctrl",
.data = (void *) V_98DX3236,
},
{
.compatible = "marvell,98dx4251-pinctrl",
.data = (void *) V_98DX4251,
},
{ },
};
static const struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
MPP_FUNC_CTRL(0, 48, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 17),
};
static const struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 3),
};
static const struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 3),
};
static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
};
static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct mvebu_pinctrl_soc_info *soc =
platform_get_drvdata(pdev);
int i, nregs;
nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
for (i = 0; i < nregs; i++)
mpp_saved_regs[i] = readl(soc->control_data[0].base + i * 4);
return 0;
}
static int armada_xp_pinctrl_resume(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc =
platform_get_drvdata(pdev);
int i, nregs;
nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
for (i = 0; i < nregs; i++)
writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4);
return 0;
}
static int armada_xp_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
int nregs;
if (!match)
return -ENODEV;
soc->variant = (unsigned) match->data & 0xff;
switch (soc->variant) {
case V_MV78230:
soc->controls = mv78230_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
soc->modes = armada_xp_mpp_modes;
/* We don't necessarily want the full list of the
* armada_xp_mpp_modes, but only the first 'n' ones
* that are available on this SoC */
soc->nmodes = mv78230_mpp_controls[0].npins;
soc->gpioranges = mv78230_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
break;
case V_MV78260:
soc->controls = mv78260_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
soc->modes = armada_xp_mpp_modes;
/* We don't necessarily want the full list of the
* armada_xp_mpp_modes, but only the first 'n' ones
* that are available on this SoC */
soc->nmodes = mv78260_mpp_controls[0].npins;
soc->gpioranges = mv78260_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
break;
case V_MV78460:
soc->controls = mv78460_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
soc->modes = armada_xp_mpp_modes;
/* We don't necessarily want the full list of the
* armada_xp_mpp_modes, but only the first 'n' ones
* that are available on this SoC */
soc->nmodes = mv78460_mpp_controls[0].npins;
soc->gpioranges = mv78460_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
break;
case V_98DX3236:
case V_98DX3336:
case V_98DX4251:
/* fall-through */
soc->controls = mv98dx3236_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls);
soc->modes = mv98dx3236_mpp_modes;
soc->nmodes = mv98dx3236_mpp_controls[0].npins;
soc->gpioranges = mv98dx3236_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges);
break;
}
nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
mpp_saved_regs = devm_kmalloc_array(&pdev->dev, nregs, sizeof(u32),
GFP_KERNEL);
if (!mpp_saved_regs)
return -ENOMEM;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver armada_xp_pinctrl_driver = {
.driver = {
.name = "armada-xp-pinctrl",
.of_match_table = armada_xp_pinctrl_of_match,
},
.probe = armada_xp_pinctrl_probe,
.suspend = armada_xp_pinctrl_suspend,
.resume = armada_xp_pinctrl_resume,
};
builtin_platform_driver(armada_xp_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-xp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "uart0", "rxd")),
MPP_MODE(1,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "uart0", "txd")),
MPP_MODE(2,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c0", "sck"),
MPP_FUNCTION(0x2, "uart0", "txd")),
MPP_MODE(3,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "i2c0", "sda"),
MPP_FUNCTION(0x2, "uart0", "rxd")),
MPP_MODE(4,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "vdd", "cpu-pd")),
MPP_MODE(5,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txclkout"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x4, "spi1", "sck"),
MPP_FUNCTION(0x5, "audio", "mclk")),
MPP_MODE(6,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txd0"),
MPP_FUNCTION(0x2, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "tdm", "rst"),
MPP_FUNCTION(0x5, "audio", "sdo")),
MPP_MODE(7,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd1"),
MPP_FUNCTION(0x4, "tdm", "dtx"),
MPP_FUNCTION(0x5, "audio", "lrclk")),
MPP_MODE(8,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txd2"),
MPP_FUNCTION(0x2, "uart0", "rts"),
MPP_FUNCTION(0x4, "tdm", "drx"),
MPP_FUNCTION(0x5, "audio", "bclk")),
MPP_MODE(9,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd3"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x3, "sd0", "clk"),
MPP_FUNCTION(0x5, "audio", "spdifo")),
MPP_MODE(10,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txctl"),
MPP_FUNCTION(0x2, "uart0", "cts"),
MPP_FUNCTION(0x4, "tdm", "fsync"),
MPP_FUNCTION(0x5, "audio", "sdi")),
MPP_MODE(11,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd0"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "sd0", "cmd"),
MPP_FUNCTION(0x4, "spi0", "cs1"),
MPP_FUNCTION(0x5, "sata1", "prsnt"),
MPP_FUNCTION(0x6, "spi1", "cs1")),
MPP_MODE(12,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd1"),
MPP_FUNCTION(0x2, "i2c1", "sda"),
MPP_FUNCTION(0x3, "sd0", "d0"),
MPP_FUNCTION(0x4, "spi1", "cs0"),
MPP_FUNCTION(0x5, "audio", "spdifi")),
MPP_MODE(13,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd2"),
MPP_FUNCTION(0x2, "i2c1", "sck"),
MPP_FUNCTION(0x3, "sd0", "d1"),
MPP_FUNCTION(0x4, "tdm", "pclk"),
MPP_FUNCTION(0x5, "audio", "rmclk")),
MPP_MODE(14,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd3"),
MPP_FUNCTION(0x2, "pcie", "clkreq0"),
MPP_FUNCTION(0x3, "sd0", "d2"),
MPP_FUNCTION(0x4, "spi1", "mosi"),
MPP_FUNCTION(0x5, "spi0", "cs2")),
MPP_MODE(15,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxctl"),
MPP_FUNCTION(0x2, "pcie", "clkreq1"),
MPP_FUNCTION(0x3, "sd0", "d3"),
MPP_FUNCTION(0x4, "spi1", "miso"),
MPP_FUNCTION(0x5, "spi0", "cs3")),
MPP_MODE(16,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxclk"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x4, "tdm", "int"),
MPP_FUNCTION(0x5, "audio", "extclk")),
MPP_MODE(17,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge", "mdc")),
MPP_MODE(18,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge", "mdio")),
MPP_MODE(19,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "txclk"),
MPP_FUNCTION(0x2, "ge1", "txclkout"),
MPP_FUNCTION(0x4, "tdm", "pclk")),
MPP_MODE(20,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd4"),
MPP_FUNCTION(0x2, "ge1", "txd0")),
MPP_MODE(21,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd5"),
MPP_FUNCTION(0x2, "ge1", "txd1"),
MPP_FUNCTION(0x4, "uart1", "txd")),
MPP_MODE(22,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd6"),
MPP_FUNCTION(0x2, "ge1", "txd2"),
MPP_FUNCTION(0x4, "uart0", "rts")),
MPP_MODE(23,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "ge0", "txd7"),
MPP_FUNCTION(0x2, "ge1", "txd3"),
MPP_FUNCTION(0x4, "spi1", "mosi")),
MPP_MODE(24,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "col"),
MPP_FUNCTION(0x2, "ge1", "txctl"),
MPP_FUNCTION(0x4, "spi1", "cs0")),
MPP_MODE(25,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxerr"),
MPP_FUNCTION(0x2, "ge1", "rxd0"),
MPP_FUNCTION(0x4, "uart1", "rxd")),
MPP_MODE(26,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "crs"),
MPP_FUNCTION(0x2, "ge1", "rxd1"),
MPP_FUNCTION(0x4, "spi1", "miso")),
MPP_MODE(27,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd4"),
MPP_FUNCTION(0x2, "ge1", "rxd2"),
MPP_FUNCTION(0x4, "uart0", "cts")),
MPP_MODE(28,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd5"),
MPP_FUNCTION(0x2, "ge1", "rxd3")),
MPP_MODE(29,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd6"),
MPP_FUNCTION(0x2, "ge1", "rxctl"),
MPP_FUNCTION(0x4, "i2c1", "sda")),
MPP_MODE(30,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "ge0", "rxd7"),
MPP_FUNCTION(0x2, "ge1", "rxclk"),
MPP_FUNCTION(0x4, "i2c1", "sck")),
MPP_MODE(31,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x3, "tclk", NULL),
MPP_FUNCTION(0x4, "ge0", "txerr")),
MPP_MODE(32,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "cs0")),
MPP_MODE(33,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "bootcs"),
MPP_FUNCTION(0x2, "spi0", "cs0")),
MPP_MODE(34,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "we0"),
MPP_FUNCTION(0x2, "spi0", "mosi")),
MPP_MODE(35,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "oe"),
MPP_FUNCTION(0x2, "spi0", "sck")),
MPP_MODE(36,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "a1"),
MPP_FUNCTION(0x2, "spi0", "miso")),
MPP_MODE(37,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "a0"),
MPP_FUNCTION(0x2, "sata0", "prsnt")),
MPP_MODE(38,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ready"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "uart0", "cts")),
MPP_MODE(39,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad0"),
MPP_FUNCTION(0x2, "audio", "spdifo")),
MPP_MODE(40,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad1"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "uart0", "rts")),
MPP_MODE(41,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad2"),
MPP_FUNCTION(0x2, "uart1", "rxd")),
MPP_MODE(42,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad3"),
MPP_FUNCTION(0x2, "uart1", "txd")),
MPP_MODE(43,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad4"),
MPP_FUNCTION(0x2, "audio", "bclk")),
MPP_MODE(44,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad5"),
MPP_FUNCTION(0x2, "audio", "mclk")),
MPP_MODE(45,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad6"),
MPP_FUNCTION(0x2, "audio", "lrclk")),
MPP_MODE(46,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad7"),
MPP_FUNCTION(0x2, "audio", "sdo")),
MPP_MODE(47,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad8"),
MPP_FUNCTION(0x3, "sd0", "clk"),
MPP_FUNCTION(0x5, "audio", "spdifo")),
MPP_MODE(48,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad9"),
MPP_FUNCTION(0x2, "uart0", "rts"),
MPP_FUNCTION(0x3, "sd0", "cmd"),
MPP_FUNCTION(0x4, "sata1", "prsnt"),
MPP_FUNCTION(0x5, "spi0", "cs1")),
MPP_MODE(49,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad10"),
MPP_FUNCTION(0x2, "pcie", "clkreq1"),
MPP_FUNCTION(0x3, "sd0", "d0"),
MPP_FUNCTION(0x4, "spi1", "cs0"),
MPP_FUNCTION(0x5, "audio", "spdifi")),
MPP_MODE(50,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad11"),
MPP_FUNCTION(0x2, "uart0", "cts"),
MPP_FUNCTION(0x3, "sd0", "d1"),
MPP_FUNCTION(0x4, "spi1", "miso"),
MPP_FUNCTION(0x5, "audio", "rmclk")),
MPP_MODE(51,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad12"),
MPP_FUNCTION(0x2, "i2c1", "sda"),
MPP_FUNCTION(0x3, "sd0", "d2"),
MPP_FUNCTION(0x4, "spi1", "mosi")),
MPP_MODE(52,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad13"),
MPP_FUNCTION(0x2, "i2c1", "sck"),
MPP_FUNCTION(0x3, "sd0", "d3"),
MPP_FUNCTION(0x4, "spi1", "sck")),
MPP_MODE(53,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ad14"),
MPP_FUNCTION(0x2, "sd0", "clk"),
MPP_FUNCTION(0x3, "tdm", "pclk"),
MPP_FUNCTION(0x4, "spi0", "cs2"),
MPP_FUNCTION(0x5, "pcie", "clkreq1")),
MPP_MODE(54,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ad15"),
MPP_FUNCTION(0x3, "tdm", "dtx")),
MPP_MODE(55,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs1"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x3, "tdm", "rst"),
MPP_FUNCTION(0x4, "sata1", "prsnt"),
MPP_FUNCTION(0x5, "sata0", "prsnt")),
MPP_MODE(56,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs2"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "uart0", "cts"),
MPP_FUNCTION(0x4, "spi0", "cs3"),
MPP_FUNCTION(0x5, "pcie", "clkreq0"),
MPP_FUNCTION(0x6, "spi1", "cs1")),
MPP_MODE(57,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs3"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "tdm", "fsync"),
MPP_FUNCTION(0x4, "sata0", "prsnt"),
MPP_FUNCTION(0x5, "audio", "sdo")),
MPP_MODE(58,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "cs0"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "tdm", "int"),
MPP_FUNCTION(0x5, "audio", "extclk"),
MPP_FUNCTION(0x6, "uart0", "rts")),
MPP_MODE(59,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "ale0"),
MPP_FUNCTION(0x2, "uart1", "rts"),
MPP_FUNCTION(0x3, "uart0", "rts"),
MPP_FUNCTION(0x5, "audio", "bclk")),
MPP_MODE(60,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "ale1"),
MPP_FUNCTION(0x2, "uart1", "rxd"),
MPP_FUNCTION(0x3, "sata0", "prsnt"),
MPP_FUNCTION(0x4, "pcie", "rstout"),
MPP_FUNCTION(0x5, "audio", "sdi")),
MPP_MODE(61,
MPP_FUNCTION(0x0, "gpo", NULL),
MPP_FUNCTION(0x1, "dev", "we1"),
MPP_FUNCTION(0x2, "uart1", "txd"),
MPP_FUNCTION(0x5, "audio", "lrclk")),
MPP_MODE(62,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "dev", "a2"),
MPP_FUNCTION(0x2, "uart1", "cts"),
MPP_FUNCTION(0x3, "tdm", "drx"),
MPP_FUNCTION(0x4, "pcie", "clkreq0"),
MPP_FUNCTION(0x5, "audio", "mclk"),
MPP_FUNCTION(0x6, "uart0", "cts")),
MPP_MODE(63,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "sck"),
MPP_FUNCTION(0x2, "tclk", NULL)),
MPP_MODE(64,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "miso"),
MPP_FUNCTION(0x2, "spi0", "cs1")),
MPP_MODE(65,
MPP_FUNCTION(0x0, "gpio", NULL),
MPP_FUNCTION(0x1, "spi0", "mosi"),
MPP_FUNCTION(0x2, "spi0", "cs2")),
};
static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
static const struct of_device_id armada_370_pinctrl_of_match[] = {
{ .compatible = "marvell,mv88f6710-pinctrl" },
{ },
};
static const struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
MPP_FUNC_CTRL(0, 65, NULL, mvebu_mmio_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 2),
};
static int armada_370_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
soc->variant = 0; /* no variants for Armada 370 */
soc->controls = mv88f6710_mpp_controls;
soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
soc->modes = mv88f6710_mpp_modes;
soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
soc->gpioranges = mv88f6710_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver armada_370_pinctrl_driver = {
.driver = {
.name = "armada-370-pinctrl",
.of_match_table = armada_370_pinctrl_of_match,
},
.probe = armada_370_pinctrl_probe,
};
builtin_platform_driver(armada_370_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-370.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2017 Marvell
*
* Thomas Petazzoni <[email protected]>
* Hanna Hawa <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "clk"),
MPP_FUNCTION(3, "spi0", "clk")),
MPP_MODE(1,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "cmd"),
MPP_FUNCTION(3, "spi0", "miso")),
MPP_MODE(2,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d0"),
MPP_FUNCTION(3, "spi0", "mosi")),
MPP_MODE(3,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d1"),
MPP_FUNCTION(3, "spi0", "cs0n")),
MPP_MODE(4,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d2"),
MPP_FUNCTION(3, "i2c0", "sda")),
MPP_MODE(5,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d3"),
MPP_FUNCTION(3, "i2c0", "sdk")),
MPP_MODE(6,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "ds")),
MPP_MODE(7,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d4"),
MPP_FUNCTION(3, "uart1", "rxd")),
MPP_MODE(8,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d5"),
MPP_FUNCTION(3, "uart1", "txd")),
MPP_MODE(9,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d6"),
MPP_FUNCTION(3, "spi0", "cs1n")),
MPP_MODE(10,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d7")),
MPP_MODE(11,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "uart0", "txd")),
MPP_MODE(12,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "pw_off"),
MPP_FUNCTION(2, "sdio", "hw_rst")),
MPP_MODE(13,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(14,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(15,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(16,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(17,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(18,
MPP_FUNCTION(0, "gpio", NULL)),
MPP_MODE(19,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "uart0", "rxd"),
MPP_FUNCTION(4, "sdio", "pw_off")),
};
static struct mvebu_pinctrl_soc_info armada_ap806_pinctrl_info;
static const struct of_device_id armada_ap806_pinctrl_of_match[] = {
{
.compatible = "marvell,ap806-pinctrl",
},
{ },
};
static const struct mvebu_mpp_ctrl armada_ap806_mpp_controls[] = {
MPP_FUNC_CTRL(0, 19, NULL, mvebu_regmap_mpp_ctrl),
};
static struct pinctrl_gpio_range armada_ap806_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 20),
};
static int armada_ap806_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_ap806_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_ap806_pinctrl_of_match, &pdev->dev);
if (!match || !pdev->dev.parent)
return -ENODEV;
soc->variant = 0; /* no variants for Armada AP806 */
soc->controls = armada_ap806_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_ap806_mpp_controls);
soc->gpioranges = armada_ap806_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(armada_ap806_mpp_gpio_ranges);
soc->modes = armada_ap806_mpp_modes;
soc->nmodes = armada_ap806_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
}
static struct platform_driver armada_ap806_pinctrl_driver = {
.driver = {
.name = "armada-ap806-pinctrl",
.of_match_table = of_match_ptr(armada_ap806_pinctrl_of_match),
},
.probe = armada_ap806_pinctrl_probe,
};
builtin_platform_driver(armada_ap806_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell ac5 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2021 Marvell
*
* Noam Liron <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
static struct mvebu_mpp_mode ac5_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d0"),
MPP_FUNCTION(2, "nand", "io4")),
MPP_MODE(1,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d1"),
MPP_FUNCTION(2, "nand", "io3")),
MPP_MODE(2,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d2"),
MPP_FUNCTION(2, "nand", "io2")),
MPP_MODE(3,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d3"),
MPP_FUNCTION(2, "nand", "io7")),
MPP_MODE(4,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d4"),
MPP_FUNCTION(2, "nand", "io6"),
MPP_FUNCTION(3, "uart3", "txd"),
MPP_FUNCTION(4, "uart2", "txd")),
MPP_MODE(5,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d5"),
MPP_FUNCTION(2, "nand", "io5"),
MPP_FUNCTION(3, "uart3", "rxd"),
MPP_FUNCTION(4, "uart2", "rxd")),
MPP_MODE(6,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d6"),
MPP_FUNCTION(2, "nand", "io0"),
MPP_FUNCTION(3, "i2c1", "sck")),
MPP_MODE(7,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "d7"),
MPP_FUNCTION(2, "nand", "io1"),
MPP_FUNCTION(3, "i2c1", "sda")),
MPP_MODE(8,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "clk"),
MPP_FUNCTION(2, "nand", "wen")),
MPP_MODE(9,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "cmd"),
MPP_FUNCTION(2, "nand", "ale")),
MPP_MODE(10,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "ds"),
MPP_FUNCTION(2, "nand", "cle")),
MPP_MODE(11,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "rst"),
MPP_FUNCTION(2, "nand", "cen")),
MPP_MODE(12,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "clk")),
MPP_MODE(13,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "csn")),
MPP_MODE(14,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "mosi")),
MPP_MODE(15,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "miso")),
MPP_MODE(16,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "wpn"),
MPP_FUNCTION(2, "nand", "ren"),
MPP_FUNCTION(3, "uart1", "txd")),
MPP_MODE(17,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "spi0", "hold"),
MPP_FUNCTION(2, "nand", "rb"),
MPP_FUNCTION(3, "uart1", "rxd")),
MPP_MODE(18,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "tsen_int", NULL),
MPP_FUNCTION(2, "uart2", "rxd"),
MPP_FUNCTION(3, "wd_int", NULL)),
MPP_MODE(19,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev_init_done", NULL),
MPP_FUNCTION(2, "uart2", "txd")),
MPP_MODE(20,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "i2c1", "sck"),
MPP_FUNCTION(3, "spi1", "clk"),
MPP_FUNCTION(4, "uart3", "txd")),
MPP_MODE(21,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "i2c1", "sda"),
MPP_FUNCTION(3, "spi1", "csn"),
MPP_FUNCTION(4, "uart3", "rxd")),
MPP_MODE(22,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "spi1", "mosi")),
MPP_MODE(23,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(3, "spi1", "miso")),
MPP_MODE(24,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "wd_int", NULL),
MPP_FUNCTION(2, "uart2", "txd"),
MPP_FUNCTION(3, "uartsd", "txd")),
MPP_MODE(25,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "int_out", NULL),
MPP_FUNCTION(2, "uart2", "rxd"),
MPP_FUNCTION(3, "uartsd", "rxd")),
MPP_MODE(26,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "i2c0", "sck"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "uart3", "txd")),
MPP_MODE(27,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "i2c0", "sda"),
MPP_FUNCTION(2, "ptp", "pulse"),
MPP_FUNCTION(3, "uart3", "rxd")),
MPP_MODE(28,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "uart3", "txd")),
MPP_MODE(29,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "uart3", "rxd")),
MPP_MODE(30,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "ge", "mdio")),
MPP_MODE(31,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "xg", "mdio"),
MPP_FUNCTION(2, "ge", "mdio"),
MPP_FUNCTION(3, "ge", "mdio")),
MPP_MODE(32,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart0", "txd")),
MPP_MODE(33,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart0", "rxd"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse")),
MPP_MODE(34,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge", "mdio"),
MPP_FUNCTION(2, "uart3", "rxd")),
MPP_MODE(35,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge", "mdio"),
MPP_FUNCTION(2, "uart3", "txd"),
MPP_FUNCTION(3, "pcie", "rstoutn")),
MPP_MODE(36,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "clk0_tp"),
MPP_FUNCTION(2, "ptp", "clk1_tp")),
MPP_MODE(37,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "pulse_tp"),
MPP_FUNCTION(2, "wd_int", NULL)),
MPP_MODE(38,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "synce", "clk_out0")),
MPP_MODE(39,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "synce", "clk_out1")),
MPP_MODE(40,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "pclk_out0"),
MPP_FUNCTION(2, "ptp", "pclk_out1")),
MPP_MODE(41,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "ref_clk"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "uart2", "txd"),
MPP_FUNCTION(5, "i2c1", "sck")),
MPP_MODE(42,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ptp", "clk0"),
MPP_FUNCTION(2, "ptp", "clk1"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "uart2", "rxd"),
MPP_FUNCTION(5, "i2c1", "sda")),
MPP_MODE(43,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "clk")),
MPP_MODE(44,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "stb")),
MPP_MODE(45,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "led", "data")),
};
static struct mvebu_pinctrl_soc_info ac5_pinctrl_info;
static const struct of_device_id ac5_pinctrl_of_match[] = {
{
.compatible = "marvell,ac5-pinctrl",
},
{ },
};
static const struct mvebu_mpp_ctrl ac5_mpp_controls[] = {
MPP_FUNC_CTRL(0, 45, NULL, mvebu_mmio_mpp_ctrl), };
static struct pinctrl_gpio_range ac5_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 46), };
static int ac5_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &ac5_pinctrl_info;
soc->variant = 0; /* no variants for ac5 */
soc->controls = ac5_mpp_controls;
soc->ncontrols = ARRAY_SIZE(ac5_mpp_controls);
soc->gpioranges = ac5_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(ac5_mpp_gpio_ranges);
soc->modes = ac5_mpp_modes;
soc->nmodes = ac5_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_mmio_probe(pdev);
}
static struct platform_driver ac5_pinctrl_driver = {
.driver = {
.name = "ac5-pinctrl",
.of_match_table = of_match_ptr(ac5_pinctrl_of_match),
},
.probe = ac5_pinctrl_probe,
};
builtin_platform_driver(ac5_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-ac5.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2017 Marvell
*
* Hanna Hawa <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-mvebu.h"
/*
* Even if the pin controller is the same the MMP available depend on the SoC
* integration.
* - In Armada7K (single CP) almost all the MPPs are available (except the
* MMP 39 to 43)
* - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
* CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
* V_ARMADA_8K_CPS) set which MPP is available to the CPx.
* The x_PLUS enum mean that the MPP available for CPx and for Armada70x0
*/
enum {
V_ARMADA_7K = BIT(0),
V_ARMADA_8K_CPM = BIT(1),
V_ARMADA_8K_CPS = BIT(2),
V_CP115_STANDALONE = BIT(3),
V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
};
static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ale1"),
MPP_FUNCTION(2, "au", "i2smclk"),
MPP_FUNCTION(3, "ge0", "rxd3"),
MPP_FUNCTION(4, "tdm", "pclk"),
MPP_FUNCTION(6, "ptp", "pulse"),
MPP_FUNCTION(7, "mss_i2c", "sda"),
MPP_FUNCTION(8, "uart0", "rxd"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "ge", "mdio")),
MPP_MODE(1,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ale0"),
MPP_FUNCTION(2, "au", "i2sdo_spdifo"),
MPP_FUNCTION(3, "ge0", "rxd2"),
MPP_FUNCTION(4, "tdm", "drx"),
MPP_FUNCTION(6, "ptp", "clk"),
MPP_FUNCTION(7, "mss_i2c", "sck"),
MPP_FUNCTION(8, "uart0", "txd"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "ge", "mdc")),
MPP_MODE(2,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad15"),
MPP_FUNCTION(2, "au", "i2sextclk"),
MPP_FUNCTION(3, "ge0", "rxd1"),
MPP_FUNCTION(4, "tdm", "dtx"),
MPP_FUNCTION(5, "mss_uart", "rxd"),
MPP_FUNCTION(6, "ptp", "pclk_out"),
MPP_FUNCTION(7, "i2c1", "sck"),
MPP_FUNCTION(8, "uart1", "rxd"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "xg", "mdc")),
MPP_MODE(3,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad14"),
MPP_FUNCTION(2, "au", "i2slrclk"),
MPP_FUNCTION(3, "ge0", "rxd0"),
MPP_FUNCTION(4, "tdm", "fsync"),
MPP_FUNCTION(5, "mss_uart", "txd"),
MPP_FUNCTION(6, "pcie", "rstoutn"),
MPP_FUNCTION(7, "i2c1", "sda"),
MPP_FUNCTION(8, "uart1", "txd"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "xg", "mdio")),
MPP_MODE(4,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad13"),
MPP_FUNCTION(2, "au", "i2sbclk"),
MPP_FUNCTION(3, "ge0", "rxctl"),
MPP_FUNCTION(4, "tdm", "rstn"),
MPP_FUNCTION(5, "mss_uart", "rxd"),
MPP_FUNCTION(6, "uart1", "cts"),
MPP_FUNCTION(7, "pcie0", "clkreq"),
MPP_FUNCTION(8, "uart3", "rxd"),
MPP_FUNCTION(10, "ge", "mdc")),
MPP_MODE(5,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad12"),
MPP_FUNCTION(2, "au", "i2sdi"),
MPP_FUNCTION(3, "ge0", "rxclk"),
MPP_FUNCTION(4, "tdm", "intn"),
MPP_FUNCTION(5, "mss_uart", "txd"),
MPP_FUNCTION(6, "uart1", "rts"),
MPP_FUNCTION(7, "pcie1", "clkreq"),
MPP_FUNCTION(8, "uart3", "txd"),
MPP_FUNCTION(10, "ge", "mdio")),
MPP_MODE(6,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad11"),
MPP_FUNCTION(3, "ge0", "txd3"),
MPP_FUNCTION(4, "spi0", "csn2"),
MPP_FUNCTION(5, "au", "i2sextclk"),
MPP_FUNCTION(6, "sata1", "present_act"),
MPP_FUNCTION(7, "pcie2", "clkreq"),
MPP_FUNCTION(8, "uart0", "rxd"),
MPP_FUNCTION(9, "ptp", "pulse")),
MPP_MODE(7,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad10"),
MPP_FUNCTION(3, "ge0", "txd2"),
MPP_FUNCTION(4, "spi0", "csn1"),
MPP_FUNCTION(5, "spi1", "csn1"),
MPP_FUNCTION(6, "sata0", "present_act"),
MPP_FUNCTION(7, "led", "data"),
MPP_FUNCTION(8, "uart0", "txd"),
MPP_FUNCTION(9, "ptp", "clk")),
MPP_MODE(8,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad9"),
MPP_FUNCTION(3, "ge0", "txd1"),
MPP_FUNCTION(4, "spi0", "csn0"),
MPP_FUNCTION(5, "spi1", "csn0"),
MPP_FUNCTION(6, "uart0", "cts"),
MPP_FUNCTION(7, "led", "stb"),
MPP_FUNCTION(8, "uart2", "rxd"),
MPP_FUNCTION(9, "ptp", "pclk_out"),
MPP_FUNCTION(10, "synce1", "clk")),
MPP_MODE(9,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad8"),
MPP_FUNCTION(3, "ge0", "txd0"),
MPP_FUNCTION(4, "spi0", "mosi"),
MPP_FUNCTION(5, "spi1", "mosi"),
MPP_FUNCTION(7, "pcie", "rstoutn"),
MPP_FUNCTION(10, "synce2", "clk")),
MPP_MODE(10,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "readyn"),
MPP_FUNCTION(3, "ge0", "txctl"),
MPP_FUNCTION(4, "spi0", "miso"),
MPP_FUNCTION(5, "spi1", "miso"),
MPP_FUNCTION(6, "uart0", "cts"),
MPP_FUNCTION(7, "sata1", "present_act")),
MPP_MODE(11,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "wen1"),
MPP_FUNCTION(3, "ge0", "txclkout"),
MPP_FUNCTION(4, "spi0", "clk"),
MPP_FUNCTION(5, "spi1", "clk"),
MPP_FUNCTION(6, "uart0", "rts"),
MPP_FUNCTION(7, "led", "clk"),
MPP_FUNCTION(8, "uart2", "txd"),
MPP_FUNCTION(9, "sata0", "present_act")),
MPP_MODE(12,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "clk_out"),
MPP_FUNCTION(2, "nf", "rbn1"),
MPP_FUNCTION(3, "spi1", "csn1"),
MPP_FUNCTION(4, "ge0", "rxclk")),
MPP_MODE(13,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "burstn"),
MPP_FUNCTION(2, "nf", "rbn0"),
MPP_FUNCTION(3, "spi1", "miso"),
MPP_FUNCTION(4, "ge0", "rxctl"),
MPP_FUNCTION(8, "mss_spi", "miso")),
MPP_MODE(14,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "bootcsn"),
MPP_FUNCTION(2, "dev", "csn0"),
MPP_FUNCTION(3, "spi1", "csn0"),
MPP_FUNCTION(4, "spi0", "csn3"),
MPP_FUNCTION(5, "au", "i2sextclk"),
MPP_FUNCTION(6, "spi0", "miso"),
MPP_FUNCTION(7, "sata0", "present_act"),
MPP_FUNCTION(8, "mss_spi", "csn")),
MPP_MODE(15,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad7"),
MPP_FUNCTION(3, "spi1", "mosi"),
MPP_FUNCTION(6, "spi0", "mosi"),
MPP_FUNCTION(8, "mss_spi", "mosi"),
MPP_FUNCTION(11, "ptp", "pulse_cp2cp")),
MPP_MODE(16,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad6"),
MPP_FUNCTION(3, "spi1", "clk"),
MPP_FUNCTION(8, "mss_spi", "clk")),
MPP_MODE(17,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad5"),
MPP_FUNCTION(4, "ge0", "txd3")),
MPP_MODE(18,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad4"),
MPP_FUNCTION(4, "ge0", "txd2"),
MPP_FUNCTION(11, "ptp", "clk_cp2cp")),
MPP_MODE(19,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad3"),
MPP_FUNCTION(4, "ge0", "txd1"),
MPP_FUNCTION(11, "wakeup", "out_cp2cp")),
MPP_MODE(20,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad2"),
MPP_FUNCTION(4, "ge0", "txd0")),
MPP_MODE(21,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad1"),
MPP_FUNCTION(4, "ge0", "txctl"),
MPP_FUNCTION(11, "sei", "in_cp2cp")),
MPP_MODE(22,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "ad0"),
MPP_FUNCTION(4, "ge0", "txclkout"),
MPP_FUNCTION(11, "wakeup", "in_cp2cp")),
MPP_MODE(23,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "a1"),
MPP_FUNCTION(5, "au", "i2smclk"),
MPP_FUNCTION(11, "link", "rd_in_cp2cp")),
MPP_MODE(24,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "a0"),
MPP_FUNCTION(5, "au", "i2slrclk")),
MPP_MODE(25,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "oen"),
MPP_FUNCTION(5, "au", "i2sdo_spdifo")),
MPP_MODE(26,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "wen0"),
MPP_FUNCTION(5, "au", "i2sbclk")),
MPP_MODE(27,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "csn0"),
MPP_FUNCTION(2, "spi1", "miso"),
MPP_FUNCTION(3, "mss_gpio4", NULL),
MPP_FUNCTION(4, "ge0", "rxd3"),
MPP_FUNCTION(5, "spi0", "csn4"),
MPP_FUNCTION(8, "ge", "mdio"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "uart0", "rts"),
MPP_FUNCTION(11, "rei", "in_cp2cp")),
MPP_MODE(28,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "csn1"),
MPP_FUNCTION(2, "spi1", "csn0"),
MPP_FUNCTION(3, "mss_gpio5", NULL),
MPP_FUNCTION(4, "ge0", "rxd2"),
MPP_FUNCTION(5, "spi0", "csn5"),
MPP_FUNCTION(6, "pcie2", "clkreq"),
MPP_FUNCTION(7, "ptp", "pulse"),
MPP_FUNCTION(8, "ge", "mdc"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "uart0", "cts"),
MPP_FUNCTION(11, "led", "data")),
MPP_MODE(29,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "csn2"),
MPP_FUNCTION(2, "spi1", "mosi"),
MPP_FUNCTION(3, "mss_gpio6", NULL),
MPP_FUNCTION(4, "ge0", "rxd1"),
MPP_FUNCTION(5, "spi0", "csn6"),
MPP_FUNCTION(6, "pcie1", "clkreq"),
MPP_FUNCTION(7, "ptp", "clk"),
MPP_FUNCTION(8, "mss_i2c", "sda"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "uart0", "rxd"),
MPP_FUNCTION(11, "led", "stb")),
MPP_MODE(30,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "csn3"),
MPP_FUNCTION(2, "spi1", "clk"),
MPP_FUNCTION(3, "mss_gpio7", NULL),
MPP_FUNCTION(4, "ge0", "rxd0"),
MPP_FUNCTION(5, "spi0", "csn7"),
MPP_FUNCTION(6, "pcie0", "clkreq"),
MPP_FUNCTION(7, "ptp", "pclk_out"),
MPP_FUNCTION(8, "mss_i2c", "sck"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "uart0", "txd"),
MPP_FUNCTION(11, "led", "clk")),
MPP_MODE(31,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "dev", "a2"),
MPP_FUNCTION(3, "mss_gpio4", NULL),
MPP_FUNCTION(6, "pcie", "rstoutn"),
MPP_FUNCTION(8, "ge", "mdc")),
MPP_MODE(32,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mii", "col"),
MPP_FUNCTION(2, "mii", "txerr"),
MPP_FUNCTION(3, "mss_spi", "miso"),
MPP_FUNCTION(4, "tdm", "drx"),
MPP_FUNCTION(5, "au", "i2sextclk"),
MPP_FUNCTION(6, "au", "i2sdi"),
MPP_FUNCTION(7, "ge", "mdio"),
MPP_FUNCTION(8, "sdio", "v18_en"),
MPP_FUNCTION(9, "pcie1", "clkreq"),
MPP_FUNCTION(10, "mss_gpio0", NULL)),
MPP_MODE(33,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mii", "txclk"),
MPP_FUNCTION(2, "sdio", "pwr10"),
MPP_FUNCTION(3, "mss_spi", "csn"),
MPP_FUNCTION(4, "tdm", "fsync"),
MPP_FUNCTION(5, "au", "i2smclk"),
MPP_FUNCTION(6, "sdio", "bus_pwr"),
MPP_FUNCTION(8, "xg", "mdio"),
MPP_FUNCTION(9, "pcie2", "clkreq"),
MPP_FUNCTION(10, "mss_gpio1", NULL)),
MPP_MODE(34,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mii", "rxerr"),
MPP_FUNCTION(2, "sdio", "pwr11"),
MPP_FUNCTION(3, "mss_spi", "mosi"),
MPP_FUNCTION(4, "tdm", "dtx"),
MPP_FUNCTION(5, "au", "i2slrclk"),
MPP_FUNCTION(6, "sdio", "wr_protect"),
MPP_FUNCTION(7, "ge", "mdc"),
MPP_FUNCTION(9, "pcie0", "clkreq"),
MPP_FUNCTION(10, "mss_gpio2", NULL)),
MPP_MODE(35,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sata1", "present_act"),
MPP_FUNCTION(2, "i2c1", "sda"),
MPP_FUNCTION(3, "mss_spi", "clk"),
MPP_FUNCTION(4, "tdm", "pclk"),
MPP_FUNCTION(5, "au", "i2sdo_spdifo"),
MPP_FUNCTION(6, "sdio", "card_detect"),
MPP_FUNCTION(7, "xg", "mdio"),
MPP_FUNCTION(8, "ge", "mdio"),
MPP_FUNCTION(9, "pcie", "rstoutn"),
MPP_FUNCTION(10, "mss_gpio3", NULL)),
MPP_MODE(36,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "synce2", "clk"),
MPP_FUNCTION(2, "i2c1", "sck"),
MPP_FUNCTION(3, "ptp", "clk"),
MPP_FUNCTION(4, "synce1", "clk"),
MPP_FUNCTION(5, "au", "i2sbclk"),
MPP_FUNCTION(6, "sata0", "present_act"),
MPP_FUNCTION(7, "xg", "mdc"),
MPP_FUNCTION(8, "ge", "mdc"),
MPP_FUNCTION(9, "pcie2", "clkreq"),
MPP_FUNCTION(10, "mss_gpio5", NULL)),
MPP_MODE(37,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart2", "rxd"),
MPP_FUNCTION(2, "i2c0", "sck"),
MPP_FUNCTION(3, "ptp", "pclk_out"),
MPP_FUNCTION(4, "tdm", "intn"),
MPP_FUNCTION(5, "mss_i2c", "sck"),
MPP_FUNCTION(6, "sata1", "present_act"),
MPP_FUNCTION(7, "ge", "mdc"),
MPP_FUNCTION(8, "xg", "mdc"),
MPP_FUNCTION(9, "pcie1", "clkreq"),
MPP_FUNCTION(10, "mss_gpio6", NULL),
MPP_FUNCTION(11, "link", "rd_out_cp2cp")),
MPP_MODE(38,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "uart2", "txd"),
MPP_FUNCTION(2, "i2c0", "sda"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "tdm", "rstn"),
MPP_FUNCTION(5, "mss_i2c", "sda"),
MPP_FUNCTION(6, "sata0", "present_act"),
MPP_FUNCTION(7, "ge", "mdio"),
MPP_FUNCTION(8, "xg", "mdio"),
MPP_FUNCTION(9, "au", "i2sextclk"),
MPP_FUNCTION(10, "mss_gpio7", NULL),
MPP_FUNCTION(11, "ptp", "pulse_cp2cp")),
MPP_MODE(39,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "wr_protect"),
MPP_FUNCTION(4, "au", "i2sbclk"),
MPP_FUNCTION(5, "ptp", "clk"),
MPP_FUNCTION(6, "spi0", "csn1"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "mss_gpio0", NULL)),
MPP_MODE(40,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "pwr11"),
MPP_FUNCTION(2, "synce1", "clk"),
MPP_FUNCTION(3, "mss_i2c", "sda"),
MPP_FUNCTION(4, "au", "i2sdo_spdifo"),
MPP_FUNCTION(5, "ptp", "pclk_out"),
MPP_FUNCTION(6, "spi0", "clk"),
MPP_FUNCTION(7, "uart1", "txd"),
MPP_FUNCTION(8, "ge", "mdio"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "mss_gpio1", NULL)),
MPP_MODE(41,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "pwr10"),
MPP_FUNCTION(2, "sdio", "bus_pwr"),
MPP_FUNCTION(3, "mss_i2c", "sck"),
MPP_FUNCTION(4, "au", "i2slrclk"),
MPP_FUNCTION(5, "ptp", "pulse"),
MPP_FUNCTION(6, "spi0", "mosi"),
MPP_FUNCTION(7, "uart1", "rxd"),
MPP_FUNCTION(8, "ge", "mdc"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "mss_gpio2", NULL),
MPP_FUNCTION(11, "rei", "out_cp2cp")),
MPP_MODE(42,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "v18_en"),
MPP_FUNCTION(2, "sdio", "wr_protect"),
MPP_FUNCTION(3, "synce2", "clk"),
MPP_FUNCTION(4, "au", "i2smclk"),
MPP_FUNCTION(5, "mss_uart", "txd"),
MPP_FUNCTION(6, "spi0", "miso"),
MPP_FUNCTION(7, "uart1", "cts"),
MPP_FUNCTION(8, "xg", "mdc"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "mss_gpio4", NULL)),
MPP_MODE(43,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "sdio", "card_detect"),
MPP_FUNCTION(3, "synce1", "clk"),
MPP_FUNCTION(4, "au", "i2sextclk"),
MPP_FUNCTION(5, "mss_uart", "rxd"),
MPP_FUNCTION(6, "spi0", "csn0"),
MPP_FUNCTION(7, "uart1", "rts"),
MPP_FUNCTION(8, "xg", "mdio"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "mss_gpio5", NULL),
MPP_FUNCTION(11, "wakeup", "out_cp2cp")),
MPP_MODE(44,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txd2"),
MPP_FUNCTION(7, "uart0", "rts"),
MPP_FUNCTION(11, "ptp", "clk_cp2cp")),
MPP_MODE(45,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txd3"),
MPP_FUNCTION(7, "uart0", "txd"),
MPP_FUNCTION(9, "pcie", "rstoutn")),
MPP_MODE(46,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txd1"),
MPP_FUNCTION(7, "uart1", "rts")),
MPP_MODE(47,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txd0"),
MPP_FUNCTION(5, "spi1", "clk"),
MPP_FUNCTION(7, "uart1", "txd"),
MPP_FUNCTION(8, "ge", "mdc")),
MPP_MODE(48,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txctl_txen"),
MPP_FUNCTION(5, "spi1", "mosi"),
MPP_FUNCTION(8, "xg", "mdc"),
MPP_FUNCTION(11, "wakeup", "in_cp2cp")),
MPP_MODE(49,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "txclkout"),
MPP_FUNCTION(2, "mii", "crs"),
MPP_FUNCTION(5, "spi1", "miso"),
MPP_FUNCTION(7, "uart1", "rxd"),
MPP_FUNCTION(8, "ge", "mdio"),
MPP_FUNCTION(9, "pcie0", "clkreq"),
MPP_FUNCTION(10, "sdio", "v18_en"),
MPP_FUNCTION(11, "sei", "out_cp2cp")),
MPP_MODE(50,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxclk"),
MPP_FUNCTION(2, "mss_i2c", "sda"),
MPP_FUNCTION(5, "spi1", "csn0"),
MPP_FUNCTION(6, "uart2", "txd"),
MPP_FUNCTION(7, "uart0", "rxd"),
MPP_FUNCTION(8, "xg", "mdio"),
MPP_FUNCTION(10, "sdio", "pwr11")),
MPP_MODE(51,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxd0"),
MPP_FUNCTION(2, "mss_i2c", "sck"),
MPP_FUNCTION(5, "spi1", "csn1"),
MPP_FUNCTION(6, "uart2", "rxd"),
MPP_FUNCTION(7, "uart0", "cts"),
MPP_FUNCTION(10, "sdio", "pwr10")),
MPP_MODE(52,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxd1"),
MPP_FUNCTION(2, "synce1", "clk"),
MPP_FUNCTION(4, "synce2", "clk"),
MPP_FUNCTION(5, "spi1", "csn2"),
MPP_FUNCTION(7, "uart1", "cts"),
MPP_FUNCTION(8, "led", "clk"),
MPP_FUNCTION(9, "pcie", "rstoutn"),
MPP_FUNCTION(10, "pcie0", "clkreq")),
MPP_MODE(53,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxd2"),
MPP_FUNCTION(3, "ptp", "clk"),
MPP_FUNCTION(5, "spi1", "csn3"),
MPP_FUNCTION(7, "uart1", "rxd"),
MPP_FUNCTION(8, "led", "stb"),
MPP_FUNCTION(11, "sdio", "led")),
MPP_MODE(54,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxd3"),
MPP_FUNCTION(2, "synce2", "clk"),
MPP_FUNCTION(3, "ptp", "pclk_out"),
MPP_FUNCTION(4, "synce1", "clk"),
MPP_FUNCTION(8, "led", "data"),
MPP_FUNCTION(10, "sdio", "hw_rst"),
MPP_FUNCTION(11, "sdio_wp", "wr_protect")),
MPP_MODE(55,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxctl_rxdv"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(10, "sdio", "led"),
MPP_FUNCTION(11, "sdio_cd", "card_detect")),
MPP_MODE(56,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(4, "tdm", "drx"),
MPP_FUNCTION(5, "au", "i2sdo_spdifo"),
MPP_FUNCTION(6, "spi0", "clk"),
MPP_FUNCTION(7, "uart1", "rxd"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(14, "sdio", "clk")),
MPP_MODE(57,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "mss_i2c", "sda"),
MPP_FUNCTION(3, "ptp", "pclk_out"),
MPP_FUNCTION(4, "tdm", "intn"),
MPP_FUNCTION(5, "au", "i2sbclk"),
MPP_FUNCTION(6, "spi0", "mosi"),
MPP_FUNCTION(7, "uart1", "txd"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(14, "sdio", "cmd")),
MPP_MODE(58,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(2, "mss_i2c", "sck"),
MPP_FUNCTION(3, "ptp", "clk"),
MPP_FUNCTION(4, "tdm", "rstn"),
MPP_FUNCTION(5, "au", "i2sdi"),
MPP_FUNCTION(6, "spi0", "miso"),
MPP_FUNCTION(7, "uart1", "cts"),
MPP_FUNCTION(8, "led", "clk"),
MPP_FUNCTION(14, "sdio", "d0")),
MPP_MODE(59,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mss_gpio7", NULL),
MPP_FUNCTION(2, "synce2", "clk"),
MPP_FUNCTION(4, "tdm", "fsync"),
MPP_FUNCTION(5, "au", "i2slrclk"),
MPP_FUNCTION(6, "spi0", "csn0"),
MPP_FUNCTION(7, "uart0", "cts"),
MPP_FUNCTION(8, "led", "stb"),
MPP_FUNCTION(9, "uart1", "txd"),
MPP_FUNCTION(14, "sdio", "d1")),
MPP_MODE(60,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mss_gpio6", NULL),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(4, "tdm", "dtx"),
MPP_FUNCTION(5, "au", "i2smclk"),
MPP_FUNCTION(6, "spi0", "csn1"),
MPP_FUNCTION(7, "uart0", "rts"),
MPP_FUNCTION(8, "led", "data"),
MPP_FUNCTION(9, "uart1", "rxd"),
MPP_FUNCTION(14, "sdio", "d2")),
MPP_MODE(61,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mss_gpio5", NULL),
MPP_FUNCTION(3, "ptp", "clk"),
MPP_FUNCTION(4, "tdm", "pclk"),
MPP_FUNCTION(5, "au", "i2sextclk"),
MPP_FUNCTION(6, "spi0", "csn2"),
MPP_FUNCTION(7, "uart0", "txd"),
MPP_FUNCTION(8, "uart2", "txd"),
MPP_FUNCTION(9, "sata1", "present_act"),
MPP_FUNCTION(10, "ge", "mdio"),
MPP_FUNCTION(14, "sdio", "d3")),
MPP_MODE(62,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "mss_gpio4", NULL),
MPP_FUNCTION(2, "synce1", "clk"),
MPP_FUNCTION(3, "ptp", "pclk_out"),
MPP_FUNCTION(5, "sata1", "present_act"),
MPP_FUNCTION(6, "spi0", "csn3"),
MPP_FUNCTION(7, "uart0", "rxd"),
MPP_FUNCTION(8, "uart2", "rxd"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "ge", "mdc"),
MPP_FUNCTION(14, "sdio", "ds")),
};
static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
{
.compatible = "marvell,armada-7k-pinctrl",
.data = (void *) V_ARMADA_7K,
},
{
.compatible = "marvell,armada-8k-cpm-pinctrl",
.data = (void *) V_ARMADA_8K_CPM,
},
{
.compatible = "marvell,armada-8k-cps-pinctrl",
.data = (void *) V_ARMADA_8K_CPS,
},
{
.compatible = "marvell,cp115-standalone-pinctrl",
.data = (void *) V_CP115_STANDALONE,
},
{ },
};
static const struct mvebu_mpp_ctrl armada_cp110_mpp_controls[] = {
MPP_FUNC_CTRL(0, 62, NULL, mvebu_regmap_mpp_ctrl),
};
static void mvebu_pinctrl_assign_variant(struct mvebu_mpp_mode *m,
u8 variant)
{
struct mvebu_mpp_ctrl_setting *s;
for (s = m->settings ; s->name ; s++)
s->variant = variant;
}
static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc;
const struct of_device_id *match =
of_match_device(armada_cp110_pinctrl_of_match, &pdev->dev);
int i;
if (!pdev->dev.parent)
return -ENODEV;
soc = devm_kzalloc(&pdev->dev,
sizeof(struct mvebu_pinctrl_soc_info), GFP_KERNEL);
if (!soc)
return -ENOMEM;
soc->variant = (unsigned long) match->data & 0xff;
soc->controls = armada_cp110_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_cp110_mpp_controls);
soc->modes = armada_cp110_mpp_modes;
soc->nmodes = ARRAY_SIZE(armada_cp110_mpp_modes);
for (i = 0; i < ARRAY_SIZE(armada_cp110_mpp_modes); i++) {
struct mvebu_mpp_mode *m = &armada_cp110_mpp_modes[i];
switch (i) {
case 0 ... 31:
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPS |
V_CP115_STANDALONE));
break;
case 32 ... 38:
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
V_CP115_STANDALONE));
break;
case 39 ... 43:
mvebu_pinctrl_assign_variant(m, (V_ARMADA_8K_CPM |
V_CP115_STANDALONE));
break;
case 44 ... 62:
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
V_CP115_STANDALONE));
break;
}
}
pdev->dev.platform_data = soc;
return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
}
static struct platform_driver armada_cp110_pinctrl_driver = {
.driver = {
.name = "armada-cp110-pinctrl",
.of_match_table = of_match_ptr(armada_cp110_pinctrl_of_match),
},
.probe = armada_cp110_pinctrl_probe,
};
builtin_platform_driver(armada_cp110_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Marvell Dove pinctrl driver based on mvebu pinctrl core
*
* Author: Sebastian Hesselbarth <[email protected]>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include "pinctrl-mvebu.h"
/* Internal registers can be configured at any 1 MiB aligned address */
#define INT_REGS_MASK ~(SZ_1M - 1)
#define MPP4_REGS_OFFS 0xd0440
#define PMU_REGS_OFFS 0xd802c
#define GC_REGS_OFFS 0xe802c
/* MPP Base registers */
#define PMU_MPP_GENERAL_CTRL 0x10
#define AU0_AC97_SEL BIT(16)
/* MPP Control 4 register */
#define SPI_GPIO_SEL BIT(5)
#define UART1_GPIO_SEL BIT(4)
#define AU1_GPIO_SEL BIT(3)
#define CAM_GPIO_SEL BIT(2)
#define SD1_GPIO_SEL BIT(1)
#define SD0_GPIO_SEL BIT(0)
/* PMU Signal Select registers */
#define PMU_SIGNAL_SELECT_0 0x00
#define PMU_SIGNAL_SELECT_1 0x04
/* Global Config regmap registers */
#define GLOBAL_CONFIG_1 0x00
#define TWSI_ENABLE_OPTION1 BIT(7)
#define GLOBAL_CONFIG_2 0x04
#define TWSI_ENABLE_OPTION2 BIT(20)
#define TWSI_ENABLE_OPTION3 BIT(21)
#define TWSI_OPTION3_GPIO BIT(22)
#define SSP_CTRL_STATUS_1 0x08
#define SSP_ON_AU1 BIT(0)
#define MPP_GENERAL_CONFIG 0x10
#define AU1_SPDIFO_GPIO_EN BIT(1)
#define NAND_GPIO_EN BIT(0)
#define CONFIG_PMU BIT(4)
static void __iomem *mpp4_base;
static void __iomem *pmu_base;
static struct regmap *gconfmap;
static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
unsigned pid, unsigned long *config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
unsigned long func;
if ((pmu & BIT(pid)) == 0)
return mvebu_mmio_mpp_ctrl_get(data, pid, config);
func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
*config = (func >> shift) & MVEBU_MPP_MASK;
*config |= CONFIG_PMU;
return 0;
}
static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
unsigned pid, unsigned long config)
{
unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
unsigned long func;
if ((config & CONFIG_PMU) == 0) {
writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
return mvebu_mmio_mpp_ctrl_set(data, pid, config);
}
writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
func &= ~(MVEBU_MPP_MASK << shift);
func |= (config & MVEBU_MPP_MASK) << shift;
writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
return 0;
}
static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long *config)
{
unsigned long mpp4 = readl(mpp4_base);
unsigned long mask;
switch (pid) {
case 24: /* mpp_camera */
mask = CAM_GPIO_SEL;
break;
case 40: /* mpp_sdio0 */
mask = SD0_GPIO_SEL;
break;
case 46: /* mpp_sdio1 */
mask = SD1_GPIO_SEL;
break;
case 58: /* mpp_spi0 */
mask = SPI_GPIO_SEL;
break;
case 62: /* mpp_uart1 */
mask = UART1_GPIO_SEL;
break;
default:
return -EINVAL;
}
*config = ((mpp4 & mask) != 0);
return 0;
}
static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long config)
{
unsigned long mpp4 = readl(mpp4_base);
unsigned long mask;
switch (pid) {
case 24: /* mpp_camera */
mask = CAM_GPIO_SEL;
break;
case 40: /* mpp_sdio0 */
mask = SD0_GPIO_SEL;
break;
case 46: /* mpp_sdio1 */
mask = SD1_GPIO_SEL;
break;
case 58: /* mpp_spi0 */
mask = SPI_GPIO_SEL;
break;
case 62: /* mpp_uart1 */
mask = UART1_GPIO_SEL;
break;
default:
return -EINVAL;
}
mpp4 &= ~mask;
if (config)
mpp4 |= mask;
writel(mpp4, mpp4_base);
return 0;
}
static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long *config)
{
unsigned int gmpp;
regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
*config = ((gmpp & NAND_GPIO_EN) != 0);
return 0;
}
static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long config)
{
regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
NAND_GPIO_EN,
(config) ? NAND_GPIO_EN : 0);
return 0;
}
static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long *config)
{
unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
*config = ((pmu & AU0_AC97_SEL) != 0);
return 0;
}
static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long config)
{
unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
pmu &= ~AU0_AC97_SEL;
if (config)
pmu |= AU0_AC97_SEL;
writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
return 0;
}
static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long *config)
{
unsigned int mpp4 = readl(mpp4_base);
unsigned int sspc1;
unsigned int gmpp;
unsigned int gcfg2;
regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
*config = 0;
if (mpp4 & AU1_GPIO_SEL)
*config |= BIT(3);
if (sspc1 & SSP_ON_AU1)
*config |= BIT(2);
if (gmpp & AU1_SPDIFO_GPIO_EN)
*config |= BIT(1);
if (gcfg2 & TWSI_OPTION3_GPIO)
*config |= BIT(0);
/* SSP/TWSI only if I2S1 not set*/
if ((*config & BIT(3)) == 0)
*config &= ~(BIT(2) | BIT(0));
/* TWSI only if SPDIFO not set*/
if ((*config & BIT(1)) == 0)
*config &= ~BIT(0);
return 0;
}
static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long config)
{
unsigned int mpp4 = readl(mpp4_base);
mpp4 &= ~AU1_GPIO_SEL;
if (config & BIT(3))
mpp4 |= AU1_GPIO_SEL;
writel(mpp4, mpp4_base);
regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
SSP_ON_AU1,
(config & BIT(2)) ? SSP_ON_AU1 : 0);
regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
AU1_SPDIFO_GPIO_EN,
(config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
TWSI_OPTION3_GPIO,
(config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
return 0;
}
/* mpp[52:57] gpio pins depend heavily on current config;
* gpio_req does not try to mux in gpio capabilities to not
* break other functions. If you require all mpps as gpio
* enforce gpio setting by pinctrl mapping.
*/
static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data,
unsigned pid)
{
unsigned long config;
dove_audio1_ctrl_get(data, pid, &config);
switch (config) {
case 0x02: /* i2s1 : gpio[56:57] */
case 0x0e: /* ssp : gpio[56:57] */
if (pid >= 56)
return 0;
return -ENOTSUPP;
case 0x08: /* spdifo : gpio[52:55] */
case 0x0b: /* twsi : gpio[52:55] */
if (pid <= 55)
return 0;
return -ENOTSUPP;
case 0x0a: /* all gpio */
return 0;
/* 0x00 : i2s1/spdifo : no gpio */
/* 0x0c : ssp/spdifo : no gpio */
/* 0x0f : ssp/twsi : no gpio */
}
return -ENOTSUPP;
}
/* mpp[52:57] has gpio pins capable of in and out */
static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data,
unsigned pid, bool input)
{
if (pid < 52 || pid > 57)
return -ENOTSUPP;
return 0;
}
static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long *config)
{
unsigned int gcfg1;
unsigned int gcfg2;
regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
*config = 0;
if (gcfg1 & TWSI_ENABLE_OPTION1)
*config = 1;
else if (gcfg2 & TWSI_ENABLE_OPTION2)
*config = 2;
else if (gcfg2 & TWSI_ENABLE_OPTION3)
*config = 3;
return 0;
}
static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
unsigned long config)
{
unsigned int gcfg1 = 0;
unsigned int gcfg2 = 0;
switch (config) {
case 1:
gcfg1 = TWSI_ENABLE_OPTION1;
break;
case 2:
gcfg2 = TWSI_ENABLE_OPTION2;
break;
case 3:
gcfg2 = TWSI_ENABLE_OPTION3;
break;
}
regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
TWSI_ENABLE_OPTION1,
gcfg1);
regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
gcfg2);
return 0;
}
static const struct mvebu_mpp_ctrl dove_mpp_controls[] = {
MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl),
MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
};
static struct mvebu_mpp_mode dove_mpp_modes[] = {
MPP_MODE(0,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart2", "rts"),
MPP_FUNCTION(0x03, "sdio0", "cd"),
MPP_FUNCTION(0x0f, "lcd0", "pwm"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(1,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart2", "cts"),
MPP_FUNCTION(0x03, "sdio0", "wp"),
MPP_FUNCTION(0x0f, "lcd1", "pwm"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(2,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "sata", "prsnt"),
MPP_FUNCTION(0x02, "uart2", "txd"),
MPP_FUNCTION(0x03, "sdio0", "buspwr"),
MPP_FUNCTION(0x04, "uart1", "rts"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(3,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "sata", "act"),
MPP_FUNCTION(0x02, "uart2", "rxd"),
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
MPP_FUNCTION(0x04, "uart1", "cts"),
MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(4,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "rts"),
MPP_FUNCTION(0x03, "sdio1", "cd"),
MPP_FUNCTION(0x04, "spi1", "miso"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(5,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "cts"),
MPP_FUNCTION(0x03, "sdio1", "wp"),
MPP_FUNCTION(0x04, "spi1", "cs"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(6,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "txd"),
MPP_FUNCTION(0x03, "sdio1", "buspwr"),
MPP_FUNCTION(0x04, "spi1", "mosi"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(7,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "rxd"),
MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
MPP_FUNCTION(0x04, "spi1", "sck"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(8,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "watchdog", "rstout"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(9,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x05, "pex1", "clkreq"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(10,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x05, "ssp", "sclk"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(11,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "sata", "prsnt"),
MPP_FUNCTION(0x02, "sata-1", "act"),
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
MPP_FUNCTION(0x05, "pex0", "clkreq"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(12,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "sata", "act"),
MPP_FUNCTION(0x02, "uart2", "rts"),
MPP_FUNCTION(0x03, "audio0", "extclk"),
MPP_FUNCTION(0x04, "sdio1", "cd"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(13,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart2", "cts"),
MPP_FUNCTION(0x03, "audio1", "extclk"),
MPP_FUNCTION(0x04, "sdio1", "wp"),
MPP_FUNCTION(0x05, "ssp", "extclk"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(14,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart2", "txd"),
MPP_FUNCTION(0x04, "sdio1", "buspwr"),
MPP_FUNCTION(0x05, "ssp", "rxd"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(15,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart2", "rxd"),
MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
MPP_FUNCTION(0x05, "ssp", "sfrm"),
MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
MPP_MODE(16,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "rts"),
MPP_FUNCTION(0x03, "sdio0", "cd"),
MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
MPP_FUNCTION(0x05, "ac97", "sdi1")),
MPP_MODE(17,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
MPP_FUNCTION(0x02, "uart3", "cts"),
MPP_FUNCTION(0x03, "sdio0", "wp"),
MPP_FUNCTION(0x04, "twsi", "sda"),
MPP_FUNCTION(0x05, "ac97", "sdi2")),
MPP_MODE(18,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "txd"),
MPP_FUNCTION(0x03, "sdio0", "buspwr"),
MPP_FUNCTION(0x04, "lcd0", "pwm"),
MPP_FUNCTION(0x05, "ac97", "sdi3")),
MPP_MODE(19,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "uart3", "rxd"),
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
MPP_FUNCTION(0x04, "twsi", "sck")),
MPP_MODE(20,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "ac97", "sysclko"),
MPP_FUNCTION(0x02, "lcd-spi", "miso"),
MPP_FUNCTION(0x03, "sdio1", "cd"),
MPP_FUNCTION(0x05, "sdio0", "cd"),
MPP_FUNCTION(0x06, "spi1", "miso")),
MPP_MODE(21,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "uart1", "rts"),
MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
MPP_FUNCTION(0x03, "sdio1", "wp"),
MPP_FUNCTION(0x04, "ssp", "sfrm"),
MPP_FUNCTION(0x05, "sdio0", "wp"),
MPP_FUNCTION(0x06, "spi1", "cs")),
MPP_MODE(22,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x01, "uart1", "cts"),
MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
MPP_FUNCTION(0x03, "sdio1", "buspwr"),
MPP_FUNCTION(0x04, "ssp", "txd"),
MPP_FUNCTION(0x05, "sdio0", "buspwr"),
MPP_FUNCTION(0x06, "spi1", "mosi")),
MPP_MODE(23,
MPP_FUNCTION(0x00, "gpio", NULL),
MPP_FUNCTION(0x02, "lcd-spi", "sck"),
MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
MPP_FUNCTION(0x04, "ssp", "sclk"),
MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
MPP_FUNCTION(0x06, "spi1", "sck")),
MPP_MODE(24,
MPP_FUNCTION(0x00, "camera", NULL),
MPP_FUNCTION(0x01, "gpio", NULL)),
MPP_MODE(40,
MPP_FUNCTION(0x00, "sdio0", NULL),
MPP_FUNCTION(0x01, "gpio", NULL)),
MPP_MODE(46,
MPP_FUNCTION(0x00, "sdio1", NULL),
MPP_FUNCTION(0x01, "gpio", NULL)),
MPP_MODE(52,
MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
MPP_FUNCTION(0x02, "i2s1", NULL),
MPP_FUNCTION(0x08, "spdifo", NULL),
MPP_FUNCTION(0x0a, "gpio", NULL),
MPP_FUNCTION(0x0b, "twsi", NULL),
MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
MPP_FUNCTION(0x0e, "ssp", NULL),
MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
MPP_MODE(58,
MPP_FUNCTION(0x00, "spi0", NULL),
MPP_FUNCTION(0x01, "gpio", NULL)),
MPP_MODE(62,
MPP_FUNCTION(0x00, "uart1", NULL),
MPP_FUNCTION(0x01, "gpio", NULL)),
MPP_MODE(64,
MPP_FUNCTION(0x00, "nand", NULL),
MPP_FUNCTION(0x01, "gpo", NULL)),
MPP_MODE(72,
MPP_FUNCTION(0x00, "i2s", NULL),
MPP_FUNCTION(0x01, "ac97", NULL)),
MPP_MODE(73,
MPP_FUNCTION(0x00, "twsi-none", NULL),
MPP_FUNCTION(0x01, "twsi-opt1", NULL),
MPP_FUNCTION(0x02, "twsi-opt2", NULL),
MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
};
static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
MPP_GPIO_RANGE(1, 32, 32, 32),
MPP_GPIO_RANGE(2, 64, 64, 8),
};
static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
.controls = dove_mpp_controls,
.ncontrols = ARRAY_SIZE(dove_mpp_controls),
.modes = dove_mpp_modes,
.nmodes = ARRAY_SIZE(dove_mpp_modes),
.gpioranges = dove_mpp_gpio_ranges,
.ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
.variant = 0,
};
static struct clk *clk;
static const struct of_device_id dove_pinctrl_of_match[] = {
{ .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
{ }
};
static const struct regmap_config gc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 5,
};
static int dove_pinctrl_probe(struct platform_device *pdev)
{
struct resource *res, *mpp_res;
struct resource fb_res;
const struct of_device_id *match =
of_match_device(dove_pinctrl_of_match, &pdev->dev);
struct mvebu_mpp_ctrl_data *mpp_data;
void __iomem *base;
int i;
pdev->dev.platform_data = (void *)match->data;
/*
* General MPP Configuration Register is part of pdma registers.
* grab clk to make sure it is ticking.
*/
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "Unable to get pdma clock");
return PTR_ERR(clk);
}
clk_prepare_enable(clk);
base = devm_platform_get_and_ioremap_resource(pdev, 0, &mpp_res);
if (IS_ERR(base))
return PTR_ERR(base);
mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
sizeof(*mpp_data), GFP_KERNEL);
if (!mpp_data)
return -ENOMEM;
dove_pinctrl_info.control_data = mpp_data;
for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
mpp_data[i].base = base;
/* prepare fallback resource */
memcpy(&fb_res, mpp_res, sizeof(struct resource));
fb_res.start = 0;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res) {
dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
adjust_resource(&fb_res,
(mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
res = &fb_res;
}
mpp4_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mpp4_base))
return PTR_ERR(mpp4_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
if (!res) {
dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
adjust_resource(&fb_res,
(mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
res = &fb_res;
}
pmu_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmu_base))
return PTR_ERR(pmu_base);
gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
if (IS_ERR(gconfmap)) {
void __iomem *gc_base;
dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
adjust_resource(&fb_res,
(mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
if (IS_ERR(gc_base))
return PTR_ERR(gc_base);
gconfmap = devm_regmap_init_mmio(&pdev->dev,
gc_base, &gc_regmap_config);
if (IS_ERR(gconfmap))
return PTR_ERR(gconfmap);
}
/* Warn on any missing DT resource */
if (fb_res.start)
dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
return mvebu_pinctrl_probe(pdev);
}
static struct platform_driver dove_pinctrl_driver = {
.driver = {
.name = "dove-pinctrl",
.suppress_bind_attrs = true,
.of_match_table = dove_pinctrl_of_match,
},
.probe = dove_pinctrl_probe,
};
builtin_platform_driver(dove_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/mvebu/pinctrl-dove.c
|
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