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// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RPC-IF core driver
*
* Copyright (C) 2018-2019 Renesas Solutions Corp.
* Copyright (C) 2019 Macronix International Co., Ltd.
* Copyright (C) 2019-2020 Cogent Embedded, Inc.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <memory/renesas-rpc-if.h>
#define RPCIF_CMNCR 0x0000 /* R/W */
#define RPCIF_CMNCR_MD BIT(31)
#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
RPCIF_CMNCR_IO3FV(val))
#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
#define RPCIF_SSLDR 0x0004 /* R/W */
#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
#define RPCIF_DRCR 0x000C /* R/W */
#define RPCIF_DRCR_SSLN BIT(24)
#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
#define RPCIF_DRCR_RCF BIT(9)
#define RPCIF_DRCR_RBE BIT(8)
#define RPCIF_DRCR_SSLE BIT(0)
#define RPCIF_DRCMR 0x0010 /* R/W */
#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_DREAR 0x0014 /* R/W */
#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
#define RPCIF_DROPR 0x0018 /* R/W */
#define RPCIF_DRENR 0x001C /* R/W */
#define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
#define RPCIF_DRENR_DME BIT(15)
#define RPCIF_DRENR_CDE BIT(14)
#define RPCIF_DRENR_OCDE BIT(12)
#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMCR 0x0020 /* R/W */
#define RPCIF_SMCR_SSLKP BIT(8)
#define RPCIF_SMCR_SPIRE BIT(2)
#define RPCIF_SMCR_SPIWE BIT(1)
#define RPCIF_SMCR_SPIE BIT(0)
#define RPCIF_SMCMR 0x0024 /* R/W */
#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_SMADR 0x0028 /* R/W */
#define RPCIF_SMOPR 0x002C /* R/W */
#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
#define RPCIF_SMENR 0x0030 /* R/W */
#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
#define RPCIF_SMENR_DME BIT(15)
#define RPCIF_SMENR_CDE BIT(14)
#define RPCIF_SMENR_OCDE BIT(12)
#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
#define RPCIF_SMRDR0 0x0038 /* R */
#define RPCIF_SMRDR1 0x003C /* R */
#define RPCIF_SMWDR0 0x0040 /* W */
#define RPCIF_SMWDR1 0x0044 /* W */
#define RPCIF_CMNSR 0x0048 /* R */
#define RPCIF_CMNSR_SSLF BIT(1)
#define RPCIF_CMNSR_TEND BIT(0)
#define RPCIF_DRDMCR 0x0058 /* R/W */
#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_DRDRENR 0x005C /* R/W */
#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_DRDRENR_ADDRE BIT(8)
#define RPCIF_DRDRENR_OPDRE BIT(4)
#define RPCIF_DRDRENR_DRDRE BIT(0)
#define RPCIF_SMDMCR 0x0060 /* R/W */
#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_SMDRENR 0x0064 /* R/W */
#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_SMDRENR_ADDRE BIT(8)
#define RPCIF_SMDRENR_OPDRE BIT(4)
#define RPCIF_SMDRENR_SPIDRE BIT(0)
#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYCNT 0x007C /* R/W */
#define RPCIF_PHYCNT_CAL BIT(31)
#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
#define RPCIF_PHYCNT_EXDS BIT(21)
#define RPCIF_PHYCNT_OCT BIT(20)
#define RPCIF_PHYCNT_DDRCAL BIT(19)
#define RPCIF_PHYCNT_HS BIT(18)
#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
#define RPCIF_PHYCNT_WBUF2 BIT(4)
#define RPCIF_PHYCNT_WBUF BIT(2)
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
#define RPCIF_PHYINT 0x0088 /* R/W */
#define RPCIF_PHYINT_WPVAL BIT(1)
static const struct regmap_range rpcif_volatile_ranges[] = {
regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
};
static const struct regmap_access_table rpcif_volatile_table = {
.yes_ranges = rpcif_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
};
struct rpcif_info {
enum rpcif_type type;
u8 strtim;
};
struct rpcif_priv {
struct device *dev;
void __iomem *base;
void __iomem *dirmap;
struct regmap *regmap;
struct reset_control *rstc;
struct platform_device *vdev;
size_t size;
const struct rpcif_info *info;
enum rpcif_data_dir dir;
u8 bus_size;
u8 xfer_size;
void *buffer;
u32 xferlen;
u32 smcr;
u32 smadr;
u32 command; /* DRCMR or SMCMR */
u32 option; /* DROPR or SMOPR */
u32 enable; /* DRENR or SMENR */
u32 dummy; /* DRDMCR or SMDMCR */
u32 ddr; /* DRDRENR or SMDRENR */
};
static const struct rpcif_info rpcif_info_r8a7796 = {
.type = RPCIF_RCAR_GEN3,
.strtim = 6,
};
static const struct rpcif_info rpcif_info_gen3 = {
.type = RPCIF_RCAR_GEN3,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_rz_g2l = {
.type = RPCIF_RZ_G2L,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_gen4 = {
.type = RPCIF_RCAR_GEN4,
.strtim = 15,
};
/*
* Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
* proper width. Requires rpcif_priv.xfer_size to be correctly set before!
*/
static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rpcif_priv *rpc = context;
switch (reg) {
case RPCIF_SMRDR0:
case RPCIF_SMWDR0:
switch (rpc->xfer_size) {
case 1:
*val = readb(rpc->base + reg);
return 0;
case 2:
*val = readw(rpc->base + reg);
return 0;
case 4:
case 8:
*val = readl(rpc->base + reg);
return 0;
default:
return -EILSEQ;
}
case RPCIF_SMRDR1:
case RPCIF_SMWDR1:
if (rpc->xfer_size != 8)
return -EILSEQ;
break;
}
*val = readl(rpc->base + reg);
return 0;
}
static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rpcif_priv *rpc = context;
switch (reg) {
case RPCIF_SMWDR0:
switch (rpc->xfer_size) {
case 1:
writeb(val, rpc->base + reg);
return 0;
case 2:
writew(val, rpc->base + reg);
return 0;
case 4:
case 8:
writel(val, rpc->base + reg);
return 0;
default:
return -EILSEQ;
}
case RPCIF_SMWDR1:
if (rpc->xfer_size != 8)
return -EILSEQ;
break;
case RPCIF_SMRDR0:
case RPCIF_SMRDR1:
return -EPERM;
}
writel(val, rpc->base + reg);
return 0;
}
static const struct regmap_config rpcif_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_read = rpcif_reg_read,
.reg_write = rpcif_reg_write,
.fast_io = true,
.max_register = RPCIF_PHYINT,
.volatile_table = &rpcif_volatile_table,
};
int rpcif_sw_init(struct rpcif *rpcif, struct device *dev)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
rpcif->dev = dev;
rpcif->dirmap = rpc->dirmap;
rpcif->size = rpc->size;
return 0;
}
EXPORT_SYMBOL(rpcif_sw_init);
static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc)
{
regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
RPCIF_PHYCNT_CKSEL(3));
regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
}
int rpcif_hw_init(struct device *dev, bool hyperflash)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
u32 dummy;
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
if (rpc->info->type == RPCIF_RZ_G2L) {
ret = reset_control_reset(rpc->rstc);
if (ret)
return ret;
usleep_range(200, 300);
rpcif_rzg2l_timing_adjust_sdr(rpc);
}
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
/* DMA Transfer is not supported */
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
/* create mask with all affected bits set */
RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1),
RPCIF_PHYCNT_STRTIM(rpc->info->strtim));
regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
RPCIF_PHYOFFSET1_DDRTMG(3));
regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
RPCIF_PHYOFFSET2_OCTTMG(4));
if (hyperflash)
regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
RPCIF_PHYINT_WPVAL, 0);
if (rpc->info->type == RPCIF_RZ_G2L)
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
RPCIF_CMNCR_BSZ(3),
RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
else
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
RPCIF_CMNCR_MOIIO(3) |
RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
/* Set RCF after BSZ update */
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
/* Dummy read according to spec */
regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
pm_runtime_put(dev);
rpc->bus_size = hyperflash ? 2 : 1;
return 0;
}
EXPORT_SYMBOL(rpcif_hw_init);
static int wait_msg_xfer_end(struct rpcif_priv *rpc)
{
u32 sts;
return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
sts & RPCIF_CMNSR_TEND, 0,
USEC_PER_SEC);
}
static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes)
{
if (rpc->bus_size == 2)
nbytes /= 2;
nbytes = clamp(nbytes, 1U, 4U);
return GENMASK(3, 4 - nbytes);
}
static u8 rpcif_bit_size(u8 buswidth)
{
return buswidth > 4 ? 2 : ilog2(buswidth);
}
void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
size_t *len)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
rpc->smcr = 0;
rpc->smadr = 0;
rpc->enable = 0;
rpc->command = 0;
rpc->option = 0;
rpc->dummy = 0;
rpc->ddr = 0;
rpc->xferlen = 0;
if (op->cmd.buswidth) {
rpc->enable = RPCIF_SMENR_CDE |
RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
if (op->cmd.ddr)
rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
}
if (op->ocmd.buswidth) {
rpc->enable |= RPCIF_SMENR_OCDE |
RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
}
if (op->addr.buswidth) {
rpc->enable |=
RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
if (op->addr.nbytes == 4)
rpc->enable |= RPCIF_SMENR_ADE(0xF);
else
rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
2, 3 - op->addr.nbytes));
if (op->addr.ddr)
rpc->ddr |= RPCIF_SMDRENR_ADDRE;
if (offs && len)
rpc->smadr = *offs;
else
rpc->smadr = op->addr.val;
}
if (op->dummy.buswidth) {
rpc->enable |= RPCIF_SMENR_DME;
rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles);
}
if (op->option.buswidth) {
rpc->enable |= RPCIF_SMENR_OPDE(
rpcif_bits_set(rpc, op->option.nbytes)) |
RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
if (op->option.ddr)
rpc->ddr |= RPCIF_SMDRENR_OPDRE;
rpc->option = op->option.val;
}
rpc->dir = op->data.dir;
if (op->data.buswidth) {
u32 nbytes;
rpc->buffer = op->data.buf.in;
switch (op->data.dir) {
case RPCIF_DATA_IN:
rpc->smcr = RPCIF_SMCR_SPIRE;
break;
case RPCIF_DATA_OUT:
rpc->smcr = RPCIF_SMCR_SPIWE;
break;
default:
break;
}
if (op->data.ddr)
rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
if (offs && len)
nbytes = *len;
else
nbytes = op->data.nbytes;
rpc->xferlen = nbytes;
rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
}
}
EXPORT_SYMBOL(rpcif_prepare);
int rpcif_manual_xfer(struct device *dev)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
int ret = 0;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
smenr = rpc->enable;
switch (rpc->dir) {
case RPCIF_DATA_OUT:
while (pos < rpc->xferlen) {
u32 bytes_left = rpc->xferlen - pos;
u32 nbytes, data[2], *p = data;
smcr = rpc->smcr | RPCIF_SMCR_SPIE;
/* nbytes may only be 1, 2, 4, or 8 */
nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
if (bytes_left > nbytes)
smcr |= RPCIF_SMCR_SSLKP;
smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
rpc->xfer_size = nbytes;
memcpy(data, rpc->buffer + pos, nbytes);
if (nbytes == 8)
regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++);
regmap_write(rpc->regmap, RPCIF_SMWDR0, *p);
regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
ret = wait_msg_xfer_end(rpc);
if (ret)
goto err_out;
pos += nbytes;
smenr = rpc->enable &
~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
}
break;
case RPCIF_DATA_IN:
/*
* RPC-IF spoils the data for the commands without an address
* phase (like RDID) in the manual mode, so we'll have to work
* around this issue by using the external address space read
* mode instead.
*/
if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
u32 dummy;
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MD, 0);
regmap_write(rpc->regmap, RPCIF_DRCR,
RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
regmap_write(rpc->regmap, RPCIF_DREAR,
RPCIF_DREAR_EAC(1));
regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
regmap_write(rpc->regmap, RPCIF_DRENR,
smenr & ~RPCIF_SMENR_SPIDE(0xF));
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
/* Dummy read according to spec */
regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
break;
}
while (pos < rpc->xferlen) {
u32 bytes_left = rpc->xferlen - pos;
u32 nbytes, data[2], *p = data;
/* nbytes may only be 1, 2, 4, or 8 */
nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
regmap_write(rpc->regmap, RPCIF_SMADR,
rpc->smadr + pos);
smenr &= ~RPCIF_SMENR_SPIDE(0xF);
smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
regmap_write(rpc->regmap, RPCIF_SMCR,
rpc->smcr | RPCIF_SMCR_SPIE);
rpc->xfer_size = nbytes;
ret = wait_msg_xfer_end(rpc);
if (ret)
goto err_out;
if (nbytes == 8)
regmap_read(rpc->regmap, RPCIF_SMRDR1, p++);
regmap_read(rpc->regmap, RPCIF_SMRDR0, p);
memcpy(rpc->buffer + pos, data, nbytes);
pos += nbytes;
}
break;
default:
regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
regmap_write(rpc->regmap, RPCIF_SMCR,
rpc->smcr | RPCIF_SMCR_SPIE);
ret = wait_msg_xfer_end(rpc);
if (ret)
goto err_out;
}
exit:
pm_runtime_put(dev);
return ret;
err_out:
if (reset_control_reset(rpc->rstc))
dev_err(dev, "Failed to reset HW\n");
rpcif_hw_init(dev, rpc->bus_size == 2);
goto exit;
}
EXPORT_SYMBOL(rpcif_manual_xfer);
static void memcpy_fromio_readw(void *to,
const void __iomem *from,
size_t count)
{
const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
u8 buf[2];
if (count && ((unsigned long)from & 1)) {
*(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
*(u8 *)to = buf[1];
from++;
to++;
count--;
}
while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
*(u16 *)to = __raw_readw(from);
from += 2;
to += 2;
count -= 2;
}
while (count >= maxw) {
#ifdef CONFIG_64BIT
*(u64 *)to = __raw_readq(from);
#else
*(u32 *)to = __raw_readl(from);
#endif
from += maxw;
to += maxw;
count -= maxw;
}
while (count >= 2) {
*(u16 *)to = __raw_readw(from);
from += 2;
to += 2;
count -= 2;
}
if (count) {
*(u16 *)buf = __raw_readw(from);
*(u8 *)to = buf[0];
}
}
ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
loff_t from = offs & (rpc->size - 1);
size_t size = rpc->size - from;
int ret;
if (len > size)
len = size;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
regmap_write(rpc->regmap, RPCIF_DRCR, 0);
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
regmap_write(rpc->regmap, RPCIF_DREAR,
RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
regmap_write(rpc->regmap, RPCIF_DRENR,
rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
if (rpc->bus_size == 2)
memcpy_fromio_readw(buf, rpc->dirmap + from, len);
else
memcpy_fromio(buf, rpc->dirmap + from, len);
pm_runtime_put(dev);
return len;
}
EXPORT_SYMBOL(rpcif_dirmap_read);
static int rpcif_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct platform_device *vdev;
struct device_node *flash;
struct rpcif_priv *rpc;
struct resource *res;
const char *name;
int ret;
flash = of_get_next_child(dev->of_node, NULL);
if (!flash) {
dev_warn(dev, "no flash node found\n");
return -ENODEV;
}
if (of_device_is_compatible(flash, "jedec,spi-nor")) {
name = "rpc-if-spi";
} else if (of_device_is_compatible(flash, "cfi-flash")) {
name = "rpc-if-hyperflash";
} else {
of_node_put(flash);
dev_warn(dev, "unknown flash type\n");
return -ENODEV;
}
of_node_put(flash);
rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
if (!rpc)
return -ENOMEM;
rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
if (IS_ERR(rpc->base))
return PTR_ERR(rpc->base);
rpc->regmap = devm_regmap_init(dev, NULL, rpc, &rpcif_regmap_config);
if (IS_ERR(rpc->regmap)) {
dev_err(dev, "failed to init regmap for rpcif, error %ld\n",
PTR_ERR(rpc->regmap));
return PTR_ERR(rpc->regmap);
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
rpc->dirmap = devm_ioremap_resource(dev, res);
if (IS_ERR(rpc->dirmap))
return PTR_ERR(rpc->dirmap);
rpc->size = resource_size(res);
rpc->info = of_device_get_match_data(dev);
rpc->rstc = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(rpc->rstc))
return PTR_ERR(rpc->rstc);
vdev = platform_device_alloc(name, pdev->id);
if (!vdev)
return -ENOMEM;
vdev->dev.parent = dev;
rpc->dev = dev;
rpc->vdev = vdev;
platform_set_drvdata(pdev, rpc);
ret = platform_device_add(vdev);
if (ret) {
platform_device_put(vdev);
return ret;
}
return 0;
}
static int rpcif_remove(struct platform_device *pdev)
{
struct rpcif_priv *rpc = platform_get_drvdata(pdev);
platform_device_unregister(rpc->vdev);
return 0;
}
static const struct of_device_id rpcif_of_match[] = {
{ .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 },
{ .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 },
{ .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 },
{ .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l },
{},
};
MODULE_DEVICE_TABLE(of, rpcif_of_match);
static struct platform_driver rpcif_driver = {
.probe = rpcif_probe,
.remove = rpcif_remove,
.driver = {
.name = "rpc-if",
.of_match_table = rpcif_of_match,
},
};
module_platform_driver(rpcif_driver);
MODULE_DESCRIPTION("Renesas RPC-IF core driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/renesas-rpc-if.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <[email protected]>
*/
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk_sip_svc.h>
#include <soc/mediatek/smi.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/memory/mtk-memory-port.h>
/* SMI COMMON */
#define SMI_L1LEN 0x100
#define SMI_L1_ARB 0x200
#define SMI_BUS_SEL 0x220
#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
/* All are MMU0 defaultly. Only specialize mmu1 here. */
#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
#define SMI_READ_FIFO_TH 0x230
#define SMI_M4U_TH 0x234
#define SMI_FIFO_TH1 0x238
#define SMI_FIFO_TH2 0x23c
#define SMI_DCM 0x300
#define SMI_DUMMY 0x444
/* SMI LARB */
#define SMI_LARB_SLP_CON 0xc
#define SLP_PROT_EN BIT(0)
#define SLP_PROT_RDY BIT(16)
#define SMI_LARB_CMD_THRT_CON 0x24
#define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
#define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
#define SMI_LARB_SW_FLAG 0x40
#define SMI_LARB_SW_FLAG_1 0x1
#define SMI_LARB_OSTDL_PORT 0x200
#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
/* Below are about mmu enable registers, they are different in SoCs */
/* gen1: mt2701 */
#define REG_SMI_SECUR_CON_BASE 0x5c0
/* every register control 8 port, register offset 0x4 */
#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
#define REG_SMI_SECUR_CON_ADDR(id) \
(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
/*
* every port have 4 bit to control, bit[port + 3] control virtual or physical,
* bit[port + 2 : port + 1] control the domain, bit[port] control the security
* or non-security.
*/
#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
/* mt2701 domain should be set to 3 */
#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
/* gen2: */
/* mt8167 */
#define MT8167_SMI_LARB_MMU_EN 0xfc0
/* mt8173 */
#define MT8173_SMI_LARB_MMU_EN 0xf00
/* general */
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
#define BANK_SEL(id) ({ \
u32 _id = (id) & 0x3; \
(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
})
#define SMI_COMMON_INIT_REGS_NR 6
#define SMI_LARB_PORT_NR_MAX 32
#define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
#define MTK_SMI_FLAG_SW_FLAG BIT(1)
#define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
struct mtk_smi_reg_pair {
unsigned int offset;
u32 value;
};
enum mtk_smi_type {
MTK_SMI_GEN1,
MTK_SMI_GEN2, /* gen2 smi common */
MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
};
/* larbs: Require apb/smi clocks while gals is optional. */
static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
#define MTK_SMI_LARB_REQ_CLK_NR 2
#define MTK_SMI_LARB_OPT_CLK_NR 1
/*
* common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
* sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
*/
static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
#define MTK_SMI_COM_REQ_CLK_NR 2
#define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
#define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
struct mtk_smi_common_plat {
enum mtk_smi_type type;
bool has_gals;
u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
const struct mtk_smi_reg_pair *init;
};
struct mtk_smi_larb_gen {
int port_in_larb[MTK_LARB_NR_MAX + 1];
int (*config_port)(struct device *dev);
unsigned int larb_direct_to_common_mask;
unsigned int flags_general;
const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
};
struct mtk_smi {
struct device *dev;
unsigned int clk_num;
struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
struct clk *clk_async; /*only needed by mt2701*/
union {
void __iomem *smi_ao_base; /* only for gen1 */
void __iomem *base; /* only for gen2 */
};
struct device *smi_common_dev; /* for sub common */
const struct mtk_smi_common_plat *plat;
};
struct mtk_smi_larb { /* larb: local arbiter */
struct mtk_smi smi;
void __iomem *base;
struct device *smi_common_dev; /* common or sub-common dev */
const struct mtk_smi_larb_gen *larb_gen;
int larbid;
u32 *mmu;
unsigned char *bank;
};
static int
mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
struct mtk_smi_larb_iommu *larb_mmu = data;
unsigned int i;
for (i = 0; i < MTK_LARB_NR_MAX; i++) {
if (dev == larb_mmu[i].dev) {
larb->larbid = i;
larb->mmu = &larb_mmu[i].mmu;
larb->bank = larb_mmu[i].bank;
return 0;
}
}
return -ENODEV;
}
static void
mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
{
/* Do nothing as the iommu is always enabled. */
}
static const struct component_ops mtk_smi_larb_component_ops = {
.bind = mtk_smi_larb_bind,
.unbind = mtk_smi_larb_unbind,
};
static int mtk_smi_larb_config_port_gen1(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
int i, m4u_port_id, larb_port_num;
u32 sec_con_val, reg_val;
m4u_port_id = larb_gen->port_in_larb[larb->larbid];
larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
- larb_gen->port_in_larb[larb->larbid];
for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
if (*larb->mmu & BIT(i)) {
/* bit[port + 3] controls the virtual or physical */
sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
} else {
/* do not need to enable m4u for this port */
continue;
}
reg_val = readl(common->smi_ao_base
+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
reg_val |= sec_con_val;
reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
writel(reg_val,
common->smi_ao_base
+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
}
return 0;
}
static int mtk_smi_larb_config_port_mt8167(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
return 0;
}
static int mtk_smi_larb_config_port_mt8173(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
return 0;
}
static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
u32 reg, flags_general = larb->larb_gen->flags_general;
const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
struct arm_smccc_res res;
int i;
if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
return 0;
if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
reg |= SMI_LARB_THRT_RD_NU_LMT;
writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
}
if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
/*
* When mmu_en bits are in security world, the bank_sel still is in the
* LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
* effect in this case.
*/
if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
if (res.a0 != 0) {
dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
return -EINVAL;
}
}
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
reg |= F_MMU_EN;
reg |= BANK_SEL(larb->bank[i]);
writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
}
return 0;
}
static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
[4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
[5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
[6] = {0x06, 0x01, 0x06, 0x0a,},
[7] = {0x0c, 0x0c, 0x12,},
[8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
0x03, 0x01, 0x1e, 0x01, 0x05,},
[9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
[10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
[11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
[12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
[13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
[14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
0x02, 0x02, 0x01, 0x01,},
[15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
0x0c, 0x01, 0x01,},
[16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
[17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
[18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
[19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
[20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
[21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
0x01,},
[23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
[24] = {0x12, 0x06, 0x12, 0x06,},
[25] = {0x01},
};
static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
[0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
[1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
[2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
[3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
[4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
[5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
[6] = {0x06, 0x01, 0x06, 0x0a,},
[7] = {0x0c, 0x0c, 0x12,},
[8] = {0x0c, 0x0c, 0x12,},
[9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
[10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
0x0d, 0x06, 0x10, 0x10,},
[11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
[12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
[13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
[14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
0x01, 0x02, 0x02, 0x08, 0x02,},
[15] = {},
[16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
[17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
[18] = {0x12, 0x06, 0x12, 0x06,},
[19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
[20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
[21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
[22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
[23] = {0x18, 0x01,},
[24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
0x01, 0x01,},
[25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0x02, 0x01,},
[26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0x02, 0x01,},
[27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0x02, 0x01,},
[28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
.port_in_larb = {
LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
},
.config_port = mtk_smi_larb_config_port_gen1,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_direct_to_common_mask =
BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
/* DUMMY | IPU0 | IPU1 | CCU | MDLA */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
/* mt8167 do not need the port in larb */
.config_port = mtk_smi_larb_config_port_mt8167,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
/* mt8173 do not need the port in larb */
.config_port = mtk_smi_larb_config_port_mt8173,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
/* IPU0 | IPU1 | CCU */
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.flags_general = MTK_SMI_FLAG_SLEEP_CTL,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
.ostd = mtk_smi_larb_mt8188_ostd,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
MTK_SMI_FLAG_SLEEP_CTL,
.ostd = mtk_smi_larb_mt8195_ostd,
};
static const struct of_device_id mtk_smi_larb_of_ids[] = {
{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
{.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
{.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
{.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
{.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
{.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
{}
};
static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
{
int ret;
u32 tmp;
writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
if (ret) {
/* TODO: Reset this larb if it fails here. */
dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
}
return ret;
}
static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
{
writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
}
static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
{
struct platform_device *smi_com_pdev;
struct device_node *smi_com_node;
struct device *smi_com_dev;
struct device_link *link;
smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
if (!smi_com_node)
return -EINVAL;
smi_com_pdev = of_find_device_by_node(smi_com_node);
of_node_put(smi_com_node);
if (smi_com_pdev) {
/* smi common is the supplier, Make sure it is ready before */
if (!platform_get_drvdata(smi_com_pdev)) {
put_device(&smi_com_pdev->dev);
return -EPROBE_DEFER;
}
smi_com_dev = &smi_com_pdev->dev;
link = device_link_add(dev, smi_com_dev,
DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
if (!link) {
dev_err(dev, "Unable to link smi-common dev\n");
put_device(&smi_com_pdev->dev);
return -ENODEV;
}
*com_dev = smi_com_dev;
} else {
dev_err(dev, "Failed to get the smi_common device\n");
return -EINVAL;
}
return 0;
}
static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
const char * const clks[],
unsigned int clk_nr_required,
unsigned int clk_nr_optional)
{
int i, ret;
for (i = 0; i < clk_nr_required; i++)
smi->clks[i].id = clks[i];
ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
if (ret)
return ret;
for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
smi->clks[i].id = clks[i];
ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
smi->clks + clk_nr_required);
smi->clk_num = clk_nr_required + clk_nr_optional;
return ret;
}
static int mtk_smi_larb_probe(struct platform_device *pdev)
{
struct mtk_smi_larb *larb;
struct device *dev = &pdev->dev;
int ret;
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
return -ENOMEM;
larb->larb_gen = of_device_get_match_data(dev);
larb->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(larb->base))
return PTR_ERR(larb->base);
ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
if (ret)
return ret;
larb->smi.dev = dev;
ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
if (ret < 0)
return ret;
pm_runtime_enable(dev);
platform_set_drvdata(pdev, larb);
ret = component_add(dev, &mtk_smi_larb_component_ops);
if (ret)
goto err_pm_disable;
return 0;
err_pm_disable:
pm_runtime_disable(dev);
device_link_remove(dev, larb->smi_common_dev);
return ret;
}
static int mtk_smi_larb_remove(struct platform_device *pdev)
{
struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
device_link_remove(&pdev->dev, larb->smi_common_dev);
pm_runtime_disable(&pdev->dev);
component_del(&pdev->dev, &mtk_smi_larb_component_ops);
return 0;
}
static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
int ret;
ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
if (ret)
return ret;
if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
mtk_smi_larb_sleep_ctrl_disable(larb);
/* Configure the basic setting for this larb */
return larb_gen->config_port(dev);
}
static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
{
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
int ret;
if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
ret = mtk_smi_larb_sleep_ctrl_enable(larb);
if (ret)
return ret;
}
clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
return 0;
}
static const struct dev_pm_ops smi_larb_pm_ops = {
SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver mtk_smi_larb_driver = {
.probe = mtk_smi_larb_probe,
.remove = mtk_smi_larb_remove,
.driver = {
.name = "mtk-smi-larb",
.of_match_table = mtk_smi_larb_of_ids,
.pm = &smi_larb_pm_ops,
}
};
static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
{SMI_L1_ARB, 0x1b},
{SMI_M4U_TH, 0xce810c85},
{SMI_FIFO_TH1, 0x43214c8},
{SMI_READ_FIFO_TH, 0x191f},
};
static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
{SMI_L1LEN, 0xb},
{SMI_M4U_TH, 0xe100e10},
{SMI_FIFO_TH1, 0x506090a},
{SMI_FIFO_TH2, 0x506090a},
{SMI_DCM, 0x4f1},
{SMI_DUMMY, 0x1},
};
static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
.type = MTK_SMI_GEN1,
};
static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
.type = MTK_SMI_GEN2,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
};
static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
.type = MTK_SMI_GEN2,
.bus_sel = F_MMU1_LARB(0),
.init = mtk_smi_common_mt6795_init,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
F_MMU1_LARB(7),
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
.type = MTK_SMI_GEN2,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
.init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
.type = MTK_SMI_GEN2,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
.init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
F_MMU1_LARB(6),
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
F_MMU1_LARB(7),
.init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
.type = MTK_SMI_GEN2,
.has_gals = true,
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
.init = mtk_smi_common_mt8195_init,
};
static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
.type = MTK_SMI_GEN2_SUB_COMM,
.has_gals = true,
};
static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
.type = MTK_SMI_GEN2,
.bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4),
};
static const struct of_device_id mtk_smi_common_of_ids[] = {
{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
{.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
{.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
{.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
{.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
{.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
{.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
{.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
{.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
{}
};
static int mtk_smi_common_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_smi *common;
int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
if (!common)
return -ENOMEM;
common->dev = dev;
common->plat = of_device_get_match_data(dev);
if (common->plat->has_gals) {
if (common->plat->type == MTK_SMI_GEN2)
clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
}
ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
if (ret)
return ret;
/*
* for mtk smi gen 1, we need to get the ao(always on) base to config
* m4u port, and we need to enable the aync clock for transform the smi
* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
* base.
*/
if (common->plat->type == MTK_SMI_GEN1) {
common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(common->smi_ao_base))
return PTR_ERR(common->smi_ao_base);
common->clk_async = devm_clk_get(dev, "async");
if (IS_ERR(common->clk_async))
return PTR_ERR(common->clk_async);
ret = clk_prepare_enable(common->clk_async);
if (ret)
return ret;
} else {
common->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(common->base))
return PTR_ERR(common->base);
}
/* link its smi-common if this is smi-sub-common */
if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
if (ret < 0)
return ret;
}
pm_runtime_enable(dev);
platform_set_drvdata(pdev, common);
return 0;
}
static int mtk_smi_common_remove(struct platform_device *pdev)
{
struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
device_link_remove(&pdev->dev, common->smi_common_dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
const struct mtk_smi_reg_pair *init = common->plat->init;
u32 bus_sel = common->plat->bus_sel; /* default is 0 */
int ret, i;
ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
if (ret)
return ret;
if (common->plat->type != MTK_SMI_GEN2)
return 0;
for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
writel_relaxed(init[i].value, common->base + init[i].offset);
writel(bus_sel, common->base + SMI_BUS_SEL);
return 0;
}
static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
{
struct mtk_smi *common = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(common->clk_num, common->clks);
return 0;
}
static const struct dev_pm_ops smi_common_pm_ops = {
SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver mtk_smi_common_driver = {
.probe = mtk_smi_common_probe,
.remove = mtk_smi_common_remove,
.driver = {
.name = "mtk-smi-common",
.of_match_table = mtk_smi_common_of_ids,
.pm = &smi_common_pm_ops,
}
};
static struct platform_driver * const smidrivers[] = {
&mtk_smi_common_driver,
&mtk_smi_larb_driver,
};
static int __init mtk_smi_init(void)
{
return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
}
module_init(mtk_smi_init);
static void __exit mtk_smi_exit(void)
{
platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
}
module_exit(mtk_smi_exit);
MODULE_DESCRIPTION("MediaTek SMI driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/mtk-smi.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Freescale Semiconductor, Inc
*
* Freescale Integrated Flash Controller
*
* Author: Dipen Dudhat <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/fsl_ifc.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
/*
* convert_ifc_address - convert the base address
* @addr_base: base address of the memory bank
*/
unsigned int convert_ifc_address(phys_addr_t addr_base)
{
return addr_base & CSPR_BA;
}
EXPORT_SYMBOL(convert_ifc_address);
/*
* fsl_ifc_find - find IFC bank
* @addr_base: base address of the memory bank
*
* This function walks IFC banks comparing "Base address" field of the CSPR
* registers with the supplied addr_base argument. When bases match this
* function returns bank number (starting with 0), otherwise it returns
* appropriate errno value.
*/
int fsl_ifc_find(phys_addr_t addr_base)
{
int i = 0;
if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
return -ENODEV;
for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
if (cspr & CSPR_V && (cspr & CSPR_BA) ==
convert_ifc_address(addr_base))
return i;
}
return -ENOENT;
}
EXPORT_SYMBOL(fsl_ifc_find);
static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
{
struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
/*
* Clear all the common status and event registers
*/
if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
/* enable all error and events */
ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
/* enable all error and event interrupts */
ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
ifc_out32(0x0, &ifc->cm_erattr0);
ifc_out32(0x0, &ifc->cm_erattr1);
return 0;
}
static int fsl_ifc_ctrl_remove(struct platform_device *dev)
{
struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
of_platform_depopulate(&dev->dev);
free_irq(ctrl->nand_irq, ctrl);
free_irq(ctrl->irq, ctrl);
irq_dispose_mapping(ctrl->nand_irq);
irq_dispose_mapping(ctrl->irq);
iounmap(ctrl->gregs);
dev_set_drvdata(&dev->dev, NULL);
return 0;
}
/*
* NAND events are split between an operational interrupt which only
* receives OPC, and an error interrupt that receives everything else,
* including non-NAND errors. Whichever interrupt gets to it first
* records the status and wakes the wait queue.
*/
static DEFINE_SPINLOCK(nand_irq_lock);
static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
{
struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
unsigned long flags;
u32 stat;
spin_lock_irqsave(&nand_irq_lock, flags);
stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (stat) {
ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
ctrl->nand_stat = stat;
wake_up(&ctrl->nand_wait);
}
spin_unlock_irqrestore(&nand_irq_lock, flags);
return stat;
}
static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
{
struct fsl_ifc_ctrl *ctrl = data;
if (check_nand_stat(ctrl))
return IRQ_HANDLED;
return IRQ_NONE;
}
/*
* NOTE: This interrupt is used to report ifc events of various kinds,
* such as transaction errors on the chipselects.
*/
static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
{
struct fsl_ifc_ctrl *ctrl = data;
struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
u32 err_axiid, err_srcid, status, cs_err, err_addr;
irqreturn_t ret = IRQ_NONE;
/* read for chip select error */
cs_err = ifc_in32(&ifc->cm_evter_stat);
if (cs_err) {
dev_err(ctrl->dev, "transaction sent to IFC is not mapped to any memory bank 0x%08X\n",
cs_err);
/* clear the chip select error */
ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
/* read error attribute registers print the error information */
status = ifc_in32(&ifc->cm_erattr0);
err_addr = ifc_in32(&ifc->cm_erattr1);
if (status & IFC_CM_ERATTR0_ERTYP_READ)
dev_err(ctrl->dev, "Read transaction error CM_ERATTR0 0x%08X\n",
status);
else
dev_err(ctrl->dev, "Write transaction error CM_ERATTR0 0x%08X\n",
status);
err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
IFC_CM_ERATTR0_ERAID_SHIFT;
dev_err(ctrl->dev, "AXI ID of the error transaction 0x%08X\n",
err_axiid);
err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
IFC_CM_ERATTR0_ESRCID_SHIFT;
dev_err(ctrl->dev, "SRC ID of the error transaction 0x%08X\n",
err_srcid);
dev_err(ctrl->dev, "Transaction Address corresponding to error ERADDR 0x%08X\n",
err_addr);
ret = IRQ_HANDLED;
}
if (check_nand_stat(ctrl))
ret = IRQ_HANDLED;
return ret;
}
/*
* fsl_ifc_ctrl_probe
*
* called by device layer when it finds a device matching
* one our driver can handled. This code allocates all of
* the resources needed for the controller only. The
* resources for the NAND banks themselves are allocated
* in the chip probe function.
*/
static int fsl_ifc_ctrl_probe(struct platform_device *dev)
{
int ret = 0;
int version, banks;
void __iomem *addr;
dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
fsl_ifc_ctrl_dev = devm_kzalloc(&dev->dev, sizeof(*fsl_ifc_ctrl_dev),
GFP_KERNEL);
if (!fsl_ifc_ctrl_dev)
return -ENOMEM;
dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
/* IOMAP the entire IFC region */
fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
if (!fsl_ifc_ctrl_dev->gregs) {
dev_err(&dev->dev, "failed to get memory region\n");
return -ENODEV;
}
if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
fsl_ifc_ctrl_dev->little_endian = true;
dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
} else {
fsl_ifc_ctrl_dev->little_endian = false;
dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
}
version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
FSL_IFC_VERSION_MASK;
banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
version >> 24, (version >> 16) & 0xf, banks);
fsl_ifc_ctrl_dev->version = version;
fsl_ifc_ctrl_dev->banks = banks;
addr = fsl_ifc_ctrl_dev->gregs;
if (version >= FSL_IFC_VERSION_2_0_0)
addr += PGOFFSET_64K;
else
addr += PGOFFSET_4K;
fsl_ifc_ctrl_dev->rregs = addr;
/* get the Controller level irq */
fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
if (fsl_ifc_ctrl_dev->irq == 0) {
dev_err(&dev->dev, "failed to get irq resource for IFC\n");
ret = -ENODEV;
goto err;
}
/* get the nand machine irq */
fsl_ifc_ctrl_dev->nand_irq =
irq_of_parse_and_map(dev->dev.of_node, 1);
fsl_ifc_ctrl_dev->dev = &dev->dev;
ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
if (ret < 0)
goto err_unmap_nandirq;
init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
"fsl-ifc", fsl_ifc_ctrl_dev);
if (ret != 0) {
dev_err(&dev->dev, "failed to install irq (%d)\n",
fsl_ifc_ctrl_dev->irq);
goto err_unmap_nandirq;
}
if (fsl_ifc_ctrl_dev->nand_irq) {
ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
if (ret != 0) {
dev_err(&dev->dev, "failed to install irq (%d)\n",
fsl_ifc_ctrl_dev->nand_irq);
goto err_free_irq;
}
}
/* legacy dts may still use "simple-bus" compatible */
ret = of_platform_default_populate(dev->dev.of_node, NULL, &dev->dev);
if (ret)
goto err_free_nandirq;
return 0;
err_free_nandirq:
free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
err_free_irq:
free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
err_unmap_nandirq:
irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
err:
iounmap(fsl_ifc_ctrl_dev->gregs);
return ret;
}
static const struct of_device_id fsl_ifc_match[] = {
{
.compatible = "fsl,ifc",
},
{},
};
static struct platform_driver fsl_ifc_ctrl_driver = {
.driver = {
.name = "fsl-ifc",
.of_match_table = fsl_ifc_match,
},
.probe = fsl_ifc_ctrl_probe,
.remove = fsl_ifc_ctrl_remove,
};
static int __init fsl_ifc_init(void)
{
return platform_driver_register(&fsl_ifc_ctrl_driver);
}
subsys_initcall(fsl_ifc_init);
MODULE_AUTHOR("Freescale Semiconductor");
MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
|
linux-master
|
drivers/memory/fsl_ifc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2020
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x0
#define FMC2_BTR1 0x4
#define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
#define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
#define FMC2_PCSCNTR 0x20
#define FMC2_BWTR1 0x104
#define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
/* Register: FMC2_BCR1 */
#define FMC2_BCR1_CCLKEN BIT(20)
#define FMC2_BCR1_FMC2EN BIT(31)
/* Register: FMC2_BCRx */
#define FMC2_BCR_MBKEN BIT(0)
#define FMC2_BCR_MUXEN BIT(1)
#define FMC2_BCR_MTYP GENMASK(3, 2)
#define FMC2_BCR_MWID GENMASK(5, 4)
#define FMC2_BCR_FACCEN BIT(6)
#define FMC2_BCR_BURSTEN BIT(8)
#define FMC2_BCR_WAITPOL BIT(9)
#define FMC2_BCR_WAITCFG BIT(11)
#define FMC2_BCR_WREN BIT(12)
#define FMC2_BCR_WAITEN BIT(13)
#define FMC2_BCR_EXTMOD BIT(14)
#define FMC2_BCR_ASYNCWAIT BIT(15)
#define FMC2_BCR_CPSIZE GENMASK(18, 16)
#define FMC2_BCR_CBURSTRW BIT(19)
#define FMC2_BCR_NBLSET GENMASK(23, 22)
/* Register: FMC2_BTRx/FMC2_BWTRx */
#define FMC2_BXTR_ADDSET GENMASK(3, 0)
#define FMC2_BXTR_ADDHLD GENMASK(7, 4)
#define FMC2_BXTR_DATAST GENMASK(15, 8)
#define FMC2_BXTR_BUSTURN GENMASK(19, 16)
#define FMC2_BTR_CLKDIV GENMASK(23, 20)
#define FMC2_BTR_DATLAT GENMASK(27, 24)
#define FMC2_BXTR_ACCMOD GENMASK(29, 28)
#define FMC2_BXTR_DATAHLD GENMASK(31, 30)
/* Register: FMC2_PCSCNTR */
#define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
#define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
#define FMC2_MAX_EBI_CE 4
#define FMC2_MAX_BANKS 5
#define FMC2_BCR_CPSIZE_0 0x0
#define FMC2_BCR_CPSIZE_128 0x1
#define FMC2_BCR_CPSIZE_256 0x2
#define FMC2_BCR_CPSIZE_512 0x3
#define FMC2_BCR_CPSIZE_1024 0x4
#define FMC2_BCR_MWID_8 0x0
#define FMC2_BCR_MWID_16 0x1
#define FMC2_BCR_MTYP_SRAM 0x0
#define FMC2_BCR_MTYP_PSRAM 0x1
#define FMC2_BCR_MTYP_NOR 0x2
#define FMC2_BXTR_EXTMOD_A 0x0
#define FMC2_BXTR_EXTMOD_B 0x1
#define FMC2_BXTR_EXTMOD_C 0x2
#define FMC2_BXTR_EXTMOD_D 0x3
#define FMC2_BCR_NBLSET_MAX 0x3
#define FMC2_BXTR_ADDSET_MAX 0xf
#define FMC2_BXTR_ADDHLD_MAX 0xf
#define FMC2_BXTR_DATAST_MAX 0xff
#define FMC2_BXTR_BUSTURN_MAX 0xf
#define FMC2_BXTR_DATAHLD_MAX 0x3
#define FMC2_BTR_CLKDIV_MAX 0xf
#define FMC2_BTR_DATLAT_MAX 0xf
#define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
enum stm32_fmc2_ebi_bank {
FMC2_EBI1 = 0,
FMC2_EBI2,
FMC2_EBI3,
FMC2_EBI4,
FMC2_NAND
};
enum stm32_fmc2_ebi_register_type {
FMC2_REG_BCR = 1,
FMC2_REG_BTR,
FMC2_REG_BWTR,
FMC2_REG_PCSCNTR
};
enum stm32_fmc2_ebi_transaction_type {
FMC2_ASYNC_MODE_1_SRAM = 0,
FMC2_ASYNC_MODE_1_PSRAM,
FMC2_ASYNC_MODE_A_SRAM,
FMC2_ASYNC_MODE_A_PSRAM,
FMC2_ASYNC_MODE_2_NOR,
FMC2_ASYNC_MODE_B_NOR,
FMC2_ASYNC_MODE_C_NOR,
FMC2_ASYNC_MODE_D_NOR,
FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
FMC2_SYNC_READ_SYNC_WRITE_NOR,
FMC2_SYNC_READ_ASYNC_WRITE_NOR
};
enum stm32_fmc2_ebi_buswidth {
FMC2_BUSWIDTH_8 = 8,
FMC2_BUSWIDTH_16 = 16
};
enum stm32_fmc2_ebi_cpsize {
FMC2_CPSIZE_0 = 0,
FMC2_CPSIZE_128 = 128,
FMC2_CPSIZE_256 = 256,
FMC2_CPSIZE_512 = 512,
FMC2_CPSIZE_1024 = 1024
};
struct stm32_fmc2_ebi {
struct device *dev;
struct clk *clk;
struct regmap *regmap;
u8 bank_assigned;
u32 bcr[FMC2_MAX_EBI_CE];
u32 btr[FMC2_MAX_EBI_CE];
u32 bwtr[FMC2_MAX_EBI_CE];
u32 pcscntr;
};
/*
* struct stm32_fmc2_prop - STM32 FMC2 EBI property
* @name: the device tree binding name of the property
* @bprop: indicate that it is a boolean property
* @mprop: indicate that it is a mandatory property
* @reg_type: the register that have to be modified
* @reg_mask: the bit that have to be modified in the selected register
* in case of it is a boolean property
* @reset_val: the default value that have to be set in case the property
* has not been defined in the device tree
* @check: this callback ckecks that the property is compliant with the
* transaction type selected
* @calculate: this callback is called to calculate for exemple a timing
* set in nanoseconds in the device tree in clock cycles or in
* clock period
* @set: this callback applies the values in the registers
*/
struct stm32_fmc2_prop {
const char *name;
bool bprop;
bool mprop;
int reg_type;
u32 reg_mask;
u32 reset_val;
int (*check)(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop, int cs);
u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
int (*set)(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup);
};
static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (bcr & FMC2_BCR_MTYP)
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (bcr & FMC2_BCR_BURSTEN)
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (prop->reg_type == FMC2_REG_BWTR)
regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
else
regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
u32 bcr, bcr1;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (cs)
regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
else
bcr1 = bcr;
if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
return 0;
return -EINVAL;
}
static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs)
{
if (cs)
return -EINVAL;
return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
}
static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
int cs, u32 setup)
{
unsigned long hclk = clk_get_rate(ebi->clk);
unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
return DIV_ROUND_UP(setup * 1000, hclkp);
}
static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
int cs, u32 setup)
{
u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
u32 bcr, btr, clk_period;
regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
if (bcr & FMC2_BCR1_CCLKEN || !cs)
regmap_read(ebi->regmap, FMC2_BTR1, &btr);
else
regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
return DIV_ROUND_UP(nb_clk_cycles, clk_period);
}
static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
{
switch (reg_type) {
case FMC2_REG_BCR:
*reg = FMC2_BCR(cs);
break;
case FMC2_REG_BTR:
*reg = FMC2_BTR(cs);
break;
case FMC2_REG_BWTR:
*reg = FMC2_BWTR(cs);
break;
case FMC2_REG_PCSCNTR:
*reg = FMC2_PCSCNTR;
break;
default:
return -EINVAL;
}
return 0;
}
static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 reg;
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
setup ? prop->reg_mask : 0);
return 0;
}
static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 bcr_mask, bcr = FMC2_BCR_WREN;
u32 btr_mask, btr = 0;
u32 bwtr_mask, bwtr = 0;
bwtr_mask = FMC2_BXTR_ACCMOD;
btr_mask = FMC2_BXTR_ACCMOD;
bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
switch (setup) {
case FMC2_ASYNC_MODE_1_SRAM:
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
/*
* MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
*/
break;
case FMC2_ASYNC_MODE_1_PSRAM:
/*
* MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
break;
case FMC2_ASYNC_MODE_A_SRAM:
/*
* MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
bcr |= FMC2_BCR_EXTMOD;
btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
break;
case FMC2_ASYNC_MODE_A_PSRAM:
/*
* MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
bcr |= FMC2_BCR_EXTMOD;
btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
break;
case FMC2_ASYNC_MODE_2_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN;
break;
case FMC2_ASYNC_MODE_B_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
break;
case FMC2_ASYNC_MODE_C_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
break;
case FMC2_ASYNC_MODE_D_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
* WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
break;
case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
/*
* MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
break;
case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
/*
* MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
bcr |= FMC2_BCR_BURSTEN;
break;
case FMC2_SYNC_READ_SYNC_WRITE_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
break;
case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
/*
* MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
* WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
*/
bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
break;
default:
/* Type of transaction not supported */
return -EINVAL;
}
if (bcr & FMC2_BCR_EXTMOD)
regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
bwtr_mask, bwtr);
regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
return 0;
}
static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val;
switch (setup) {
case FMC2_BUSWIDTH_8:
val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
break;
case FMC2_BUSWIDTH_16:
val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
break;
default:
/* Buswidth not supported */
return -EINVAL;
}
regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
return 0;
}
static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val;
switch (setup) {
case FMC2_CPSIZE_0:
val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
break;
case FMC2_CPSIZE_128:
val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
break;
case FMC2_CPSIZE_256:
val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
break;
case FMC2_CPSIZE_512:
val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
break;
case FMC2_CPSIZE_1024:
val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
break;
default:
/* Cpsize not supported */
return -EINVAL;
}
regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
return 0;
}
static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val;
val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
val = FIELD_PREP(FMC2_BCR_NBLSET, val);
regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
return 0;
}
static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 bcr, bxtr, reg;
u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if (prop->reg_type == FMC2_REG_BWTR)
regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
else
regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
else
val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
return 0;
}
static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val, reg;
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
return 0;
}
static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val, reg;
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
val = FIELD_PREP(FMC2_BXTR_DATAST, val);
regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
return 0;
}
static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val, reg;
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
return 0;
}
static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val, reg;
int ret;
ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
if (ret)
return ret;
if (prop->reg_type == FMC2_REG_BWTR)
val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
else
val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
return 0;
}
static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val;
val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
return 0;
}
static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 val;
val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
val = FIELD_PREP(FMC2_BTR_DATLAT, val);
regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
return 0;
}
static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
const struct stm32_fmc2_prop *prop,
int cs, u32 setup)
{
u32 old_val, new_val, pcscntr;
if (setup < 1)
return 0;
regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
/* Enable counter for the bank */
regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
FMC2_PCSCNTR_CNTBEN(cs),
FMC2_PCSCNTR_CNTBEN(cs));
new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
if (old_val && new_val > old_val)
/* Keep current counter value */
return 0;
new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
FMC2_PCSCNTR_CSCOUNT, new_val);
return 0;
}
static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
/* st,fmc2-ebi-cs-trans-type must be the first property */
{
.name = "st,fmc2-ebi-cs-transaction-type",
.mprop = true,
.set = stm32_fmc2_ebi_set_trans_type,
},
{
.name = "st,fmc2-ebi-cs-cclk-enable",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR1_CCLKEN,
.check = stm32_fmc2_ebi_check_cclk,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-mux-enable",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR_MUXEN,
.check = stm32_fmc2_ebi_check_mux,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-buswidth",
.reset_val = FMC2_BUSWIDTH_16,
.set = stm32_fmc2_ebi_set_buswidth,
},
{
.name = "st,fmc2-ebi-cs-waitpol-high",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR_WAITPOL,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-waitcfg-enable",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR_WAITCFG,
.check = stm32_fmc2_ebi_check_waitcfg,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-wait-enable",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR_WAITEN,
.check = stm32_fmc2_ebi_check_sync_trans,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-asyncwait-enable",
.bprop = true,
.reg_type = FMC2_REG_BCR,
.reg_mask = FMC2_BCR_ASYNCWAIT,
.check = stm32_fmc2_ebi_check_async_trans,
.set = stm32_fmc2_ebi_set_bit_field,
},
{
.name = "st,fmc2-ebi-cs-cpsize",
.check = stm32_fmc2_ebi_check_cpsize,
.set = stm32_fmc2_ebi_set_cpsize,
},
{
.name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_bl_setup,
},
{
.name = "st,fmc2-ebi-cs-address-setup-ns",
.reg_type = FMC2_REG_BTR,
.reset_val = FMC2_BXTR_ADDSET_MAX,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_address_setup,
},
{
.name = "st,fmc2-ebi-cs-address-hold-ns",
.reg_type = FMC2_REG_BTR,
.reset_val = FMC2_BXTR_ADDHLD_MAX,
.check = stm32_fmc2_ebi_check_address_hold,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_address_hold,
},
{
.name = "st,fmc2-ebi-cs-data-setup-ns",
.reg_type = FMC2_REG_BTR,
.reset_val = FMC2_BXTR_DATAST_MAX,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_data_setup,
},
{
.name = "st,fmc2-ebi-cs-bus-turnaround-ns",
.reg_type = FMC2_REG_BTR,
.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_bus_turnaround,
},
{
.name = "st,fmc2-ebi-cs-data-hold-ns",
.reg_type = FMC2_REG_BTR,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_data_hold,
},
{
.name = "st,fmc2-ebi-cs-clk-period-ns",
.reset_val = FMC2_BTR_CLKDIV_MAX + 1,
.check = stm32_fmc2_ebi_check_clk_period,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_clk_period,
},
{
.name = "st,fmc2-ebi-cs-data-latency-ns",
.check = stm32_fmc2_ebi_check_sync_trans,
.calculate = stm32_fmc2_ebi_ns_to_clk_period,
.set = stm32_fmc2_ebi_set_data_latency,
},
{
.name = "st,fmc2-ebi-cs-write-address-setup-ns",
.reg_type = FMC2_REG_BWTR,
.reset_val = FMC2_BXTR_ADDSET_MAX,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_address_setup,
},
{
.name = "st,fmc2-ebi-cs-write-address-hold-ns",
.reg_type = FMC2_REG_BWTR,
.reset_val = FMC2_BXTR_ADDHLD_MAX,
.check = stm32_fmc2_ebi_check_address_hold,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_address_hold,
},
{
.name = "st,fmc2-ebi-cs-write-data-setup-ns",
.reg_type = FMC2_REG_BWTR,
.reset_val = FMC2_BXTR_DATAST_MAX,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_data_setup,
},
{
.name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
.reg_type = FMC2_REG_BWTR,
.reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_bus_turnaround,
},
{
.name = "st,fmc2-ebi-cs-write-data-hold-ns",
.reg_type = FMC2_REG_BWTR,
.check = stm32_fmc2_ebi_check_async_trans,
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_data_hold,
},
{
.name = "st,fmc2-ebi-cs-max-low-pulse-ns",
.calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
.set = stm32_fmc2_ebi_set_max_low_pulse,
},
};
static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
struct device_node *dev_node,
const struct stm32_fmc2_prop *prop,
int cs)
{
struct device *dev = ebi->dev;
u32 setup = 0;
if (!prop->set) {
dev_err(dev, "property %s is not well defined\n", prop->name);
return -EINVAL;
}
if (prop->check && prop->check(ebi, prop, cs))
/* Skeep this property */
return 0;
if (prop->bprop) {
bool bprop;
bprop = of_property_read_bool(dev_node, prop->name);
if (prop->mprop && !bprop) {
dev_err(dev, "mandatory property %s not defined in the device tree\n",
prop->name);
return -EINVAL;
}
if (bprop)
setup = 1;
} else {
u32 val;
int ret;
ret = of_property_read_u32(dev_node, prop->name, &val);
if (prop->mprop && ret) {
dev_err(dev, "mandatory property %s not defined in the device tree\n",
prop->name);
return ret;
}
if (ret)
setup = prop->reset_val;
else if (prop->calculate)
setup = prop->calculate(ebi, cs, val);
else
setup = val;
}
return prop->set(ebi, prop, cs, setup);
}
static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
{
regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
}
static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
{
regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
}
static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
{
unsigned int cs;
for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
}
regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
}
static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi)
{
unsigned int cs;
for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);
regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]);
regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]);
}
regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr);
}
static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
{
unsigned int cs;
for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
if (!(ebi->bank_assigned & BIT(cs)))
continue;
stm32_fmc2_ebi_disable_bank(ebi, cs);
}
}
/* NWAIT signal can not be connected to EBI controller and NAND controller */
static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
{
unsigned int cs;
u32 bcr;
for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
if (!(ebi->bank_assigned & BIT(cs)))
continue;
regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
ebi->bank_assigned & BIT(FMC2_NAND))
return true;
}
return false;
}
static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
{
regmap_update_bits(ebi->regmap, FMC2_BCR1,
FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
}
static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
{
regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
}
static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
struct device_node *dev_node,
u32 cs)
{
unsigned int i;
int ret;
stm32_fmc2_ebi_disable_bank(ebi, cs);
for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
if (ret) {
dev_err(ebi->dev, "property %s could not be set: %d\n",
p->name, ret);
return ret;
}
}
stm32_fmc2_ebi_enable_bank(ebi, cs);
return 0;
}
static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
{
struct device *dev = ebi->dev;
struct device_node *child;
bool child_found = false;
u32 bank;
int ret;
for_each_available_child_of_node(dev->of_node, child) {
ret = of_property_read_u32(child, "reg", &bank);
if (ret) {
dev_err(dev, "could not retrieve reg property: %d\n",
ret);
of_node_put(child);
return ret;
}
if (bank >= FMC2_MAX_BANKS) {
dev_err(dev, "invalid reg value: %d\n", bank);
of_node_put(child);
return -EINVAL;
}
if (ebi->bank_assigned & BIT(bank)) {
dev_err(dev, "bank already assigned: %d\n", bank);
of_node_put(child);
return -EINVAL;
}
if (bank < FMC2_MAX_EBI_CE) {
ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
if (ret) {
dev_err(dev, "setup chip select %d failed: %d\n",
bank, ret);
of_node_put(child);
return ret;
}
}
ebi->bank_assigned |= BIT(bank);
child_found = true;
}
if (!child_found) {
dev_warn(dev, "no subnodes found, disable the driver.\n");
return -ENODEV;
}
if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
return -EINVAL;
}
stm32_fmc2_ebi_enable(ebi);
return of_platform_populate(dev->of_node, NULL, NULL, dev);
}
static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct stm32_fmc2_ebi *ebi;
struct reset_control *rstc;
int ret;
ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
if (!ebi)
return -ENOMEM;
ebi->dev = dev;
ebi->regmap = device_node_to_regmap(dev->of_node);
if (IS_ERR(ebi->regmap))
return PTR_ERR(ebi->regmap);
ebi->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ebi->clk))
return PTR_ERR(ebi->clk);
rstc = devm_reset_control_get(dev, NULL);
if (PTR_ERR(rstc) == -EPROBE_DEFER)
return -EPROBE_DEFER;
ret = clk_prepare_enable(ebi->clk);
if (ret)
return ret;
if (!IS_ERR(rstc)) {
reset_control_assert(rstc);
reset_control_deassert(rstc);
}
ret = stm32_fmc2_ebi_parse_dt(ebi);
if (ret)
goto err_release;
stm32_fmc2_ebi_save_setup(ebi);
platform_set_drvdata(pdev, ebi);
return 0;
err_release:
stm32_fmc2_ebi_disable_banks(ebi);
stm32_fmc2_ebi_disable(ebi);
clk_disable_unprepare(ebi->clk);
return ret;
}
static int stm32_fmc2_ebi_remove(struct platform_device *pdev)
{
struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);
of_platform_depopulate(&pdev->dev);
stm32_fmc2_ebi_disable_banks(ebi);
stm32_fmc2_ebi_disable(ebi);
clk_disable_unprepare(ebi->clk);
return 0;
}
static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)
{
struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
stm32_fmc2_ebi_disable(ebi);
clk_disable_unprepare(ebi->clk);
pinctrl_pm_select_sleep_state(dev);
return 0;
}
static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
{
struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
int ret;
pinctrl_pm_select_default_state(dev);
ret = clk_prepare_enable(ebi->clk);
if (ret)
return ret;
stm32_fmc2_ebi_set_setup(ebi);
stm32_fmc2_ebi_enable(ebi);
return 0;
}
static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend,
stm32_fmc2_ebi_resume);
static const struct of_device_id stm32_fmc2_ebi_match[] = {
{.compatible = "st,stm32mp1-fmc2-ebi"},
{}
};
MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
static struct platform_driver stm32_fmc2_ebi_driver = {
.probe = stm32_fmc2_ebi_probe,
.remove = stm32_fmc2_ebi_remove,
.driver = {
.name = "stm32_fmc2_ebi",
.of_match_table = stm32_fmc2_ebi_match,
.pm = &stm32_fmc2_ebi_pm_ops,
},
};
module_platform_driver(stm32_fmc2_ebi_driver);
MODULE_ALIAS("platform:stm32_fmc2_ebi");
MODULE_AUTHOR("Christophe Kerello <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/stm32-fmc2-ebi.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI AEMIF driver
*
* Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
*
* Authors:
* Murali Karicheri <[email protected]>
* Ivan Khoronzhuk <[email protected]>
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/platform_data/ti-aemif.h>
#define TA_SHIFT 2
#define RHOLD_SHIFT 4
#define RSTROBE_SHIFT 7
#define RSETUP_SHIFT 13
#define WHOLD_SHIFT 17
#define WSTROBE_SHIFT 20
#define WSETUP_SHIFT 26
#define EW_SHIFT 30
#define SSTROBE_SHIFT 31
#define TA(x) ((x) << TA_SHIFT)
#define RHOLD(x) ((x) << RHOLD_SHIFT)
#define RSTROBE(x) ((x) << RSTROBE_SHIFT)
#define RSETUP(x) ((x) << RSETUP_SHIFT)
#define WHOLD(x) ((x) << WHOLD_SHIFT)
#define WSTROBE(x) ((x) << WSTROBE_SHIFT)
#define WSETUP(x) ((x) << WSETUP_SHIFT)
#define EW(x) ((x) << EW_SHIFT)
#define SSTROBE(x) ((x) << SSTROBE_SHIFT)
#define ASIZE_MAX 0x1
#define TA_MAX 0x3
#define RHOLD_MAX 0x7
#define RSTROBE_MAX 0x3f
#define RSETUP_MAX 0xf
#define WHOLD_MAX 0x7
#define WSTROBE_MAX 0x3f
#define WSETUP_MAX 0xf
#define EW_MAX 0x1
#define SSTROBE_MAX 0x1
#define NUM_CS 4
#define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
#define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
#define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
#define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
#define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
#define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
#define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
#define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
#define SSTROBE_VAL(x) (((x) & SSTROBE(SSTROBE_MAX)) >> SSTROBE_SHIFT)
#define NRCSR_OFFSET 0x00
#define AWCCR_OFFSET 0x04
#define A1CR_OFFSET 0x10
#define ACR_ASIZE_MASK 0x3
#define ACR_EW_MASK BIT(30)
#define ACR_SSTROBE_MASK BIT(31)
#define ASIZE_16BIT 1
#define CONFIG_MASK (TA(TA_MAX) | \
RHOLD(RHOLD_MAX) | \
RSTROBE(RSTROBE_MAX) | \
RSETUP(RSETUP_MAX) | \
WHOLD(WHOLD_MAX) | \
WSTROBE(WSTROBE_MAX) | \
WSETUP(WSETUP_MAX) | \
EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
ASIZE_MAX)
/**
* struct aemif_cs_data: structure to hold cs parameters
* @cs: chip-select number
* @wstrobe: write strobe width, ns
* @rstrobe: read strobe width, ns
* @wsetup: write setup width, ns
* @whold: write hold width, ns
* @rsetup: read setup width, ns
* @rhold: read hold width, ns
* @ta: minimum turn around time, ns
* @enable_ss: enable/disable select strobe mode
* @enable_ew: enable/disable extended wait mode
* @asize: width of the asynchronous device's data bus
*/
struct aemif_cs_data {
u8 cs;
u16 wstrobe;
u16 rstrobe;
u8 wsetup;
u8 whold;
u8 rsetup;
u8 rhold;
u8 ta;
u8 enable_ss;
u8 enable_ew;
u8 asize;
};
/**
* struct aemif_device: structure to hold device data
* @base: base address of AEMIF registers
* @clk: source clock
* @clk_rate: clock's rate in kHz
* @num_cs: number of assigned chip-selects
* @cs_offset: start number of cs nodes
* @cs_data: array of chip-select settings
*/
struct aemif_device {
void __iomem *base;
struct clk *clk;
unsigned long clk_rate;
u8 num_cs;
int cs_offset;
struct aemif_cs_data cs_data[NUM_CS];
};
/**
* aemif_calc_rate - calculate timing data.
* @pdev: platform device to calculate for
* @wanted: The cycle time needed in nanoseconds.
* @clk: The input clock rate in kHz.
* @max: The maximum divider value that can be programmed.
*
* On success, returns the calculated timing value minus 1 for easy
* programming into AEMIF timing registers, else negative errno.
*/
static int aemif_calc_rate(struct platform_device *pdev, int wanted,
unsigned long clk, int max)
{
int result;
result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
clk, wanted);
/* It is generally OK to have a more relaxed timing than requested... */
if (result < 0)
result = 0;
/* ... But configuring tighter timings is not an option. */
else if (result > max)
result = -EINVAL;
return result;
}
/**
* aemif_config_abus - configure async bus parameters
* @pdev: platform device to configure for
* @csnum: aemif chip select number
*
* This function programs the given timing values (in real clock) into the
* AEMIF registers taking the AEMIF clock into account.
*
* This function does not use any locking while programming the AEMIF
* because it is expected that there is only one user of a given
* chip-select.
*
* Returns 0 on success, else negative errno.
*/
static int aemif_config_abus(struct platform_device *pdev, int csnum)
{
struct aemif_device *aemif = platform_get_drvdata(pdev);
struct aemif_cs_data *data = &aemif->cs_data[csnum];
int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
unsigned long clk_rate = aemif->clk_rate;
unsigned offset;
u32 set, val;
offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
whold < 0 || wstrobe < 0 || wsetup < 0) {
dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
__func__);
return -EINVAL;
}
set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
set |= (data->asize & ACR_ASIZE_MASK);
if (data->enable_ew)
set |= ACR_EW_MASK;
if (data->enable_ss)
set |= ACR_SSTROBE_MASK;
val = readl(aemif->base + offset);
val &= ~CONFIG_MASK;
val |= set;
writel(val, aemif->base + offset);
return 0;
}
static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
{
return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
}
/**
* aemif_get_hw_params - function to read hw register values
* @pdev: platform device to read for
* @csnum: aemif chip select number
*
* This function reads the defaults from the registers and update
* the timing values. Required for get/set commands and also for
* the case when driver needs to use defaults in hardware.
*/
static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
{
struct aemif_device *aemif = platform_get_drvdata(pdev);
struct aemif_cs_data *data = &aemif->cs_data[csnum];
unsigned long clk_rate = aemif->clk_rate;
u32 val, offset;
offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
val = readl(aemif->base + offset);
data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
data->enable_ew = EW_VAL(val);
data->enable_ss = SSTROBE_VAL(val);
data->asize = val & ASIZE_MAX;
}
/**
* of_aemif_parse_abus_config - parse CS configuration from DT
* @pdev: platform device to parse for
* @np: device node ptr
*
* This function update the emif async bus configuration based on the values
* configured in a cs device binding node.
*/
static int of_aemif_parse_abus_config(struct platform_device *pdev,
struct device_node *np)
{
struct aemif_device *aemif = platform_get_drvdata(pdev);
struct aemif_cs_data *data;
u32 cs;
u32 val;
if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
dev_dbg(&pdev->dev, "cs property is required");
return -EINVAL;
}
if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
return -EINVAL;
}
if (aemif->num_cs >= NUM_CS) {
dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
return -EINVAL;
}
data = &aemif->cs_data[aemif->num_cs];
data->cs = cs;
/* read the current value in the hw register */
aemif_get_hw_params(pdev, aemif->num_cs++);
/* override the values from device node */
if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
data->ta = val;
if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
data->rhold = val;
if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
data->rstrobe = val;
if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
data->rsetup = val;
if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
data->whold = val;
if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
data->wstrobe = val;
if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
data->wsetup = val;
if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
if (val == 16)
data->asize = 1;
data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
return 0;
}
static const struct of_device_id aemif_of_match[] = {
{ .compatible = "ti,davinci-aemif", },
{ .compatible = "ti,da850-aemif", },
{},
};
MODULE_DEVICE_TABLE(of, aemif_of_match);
static int aemif_probe(struct platform_device *pdev)
{
int i;
int ret = -ENODEV;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *child_np;
struct aemif_device *aemif;
struct aemif_platform_data *pdata;
struct of_dev_auxdata *dev_lookup;
aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
if (!aemif)
return -ENOMEM;
pdata = dev_get_platdata(&pdev->dev);
dev_lookup = pdata ? pdata->dev_lookup : NULL;
platform_set_drvdata(pdev, aemif);
aemif->clk = devm_clk_get(dev, NULL);
if (IS_ERR(aemif->clk)) {
dev_err(dev, "cannot get clock 'aemif'\n");
return PTR_ERR(aemif->clk);
}
ret = clk_prepare_enable(aemif->clk);
if (ret)
return ret;
aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
if (np && of_device_is_compatible(np, "ti,da850-aemif"))
aemif->cs_offset = 2;
else if (pdata)
aemif->cs_offset = pdata->cs_offset;
aemif->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(aemif->base)) {
ret = PTR_ERR(aemif->base);
goto error;
}
if (np) {
/*
* For every controller device node, there is a cs device node
* that describe the bus configuration parameters. This
* functions iterate over these nodes and update the cs data
* array.
*/
for_each_available_child_of_node(np, child_np) {
ret = of_aemif_parse_abus_config(pdev, child_np);
if (ret < 0) {
of_node_put(child_np);
goto error;
}
}
} else if (pdata && pdata->num_abus_data > 0) {
for (i = 0; i < pdata->num_abus_data; i++, aemif->num_cs++) {
aemif->cs_data[i].cs = pdata->abus_data[i].cs;
aemif_get_hw_params(pdev, i);
}
}
for (i = 0; i < aemif->num_cs; i++) {
ret = aemif_config_abus(pdev, i);
if (ret < 0) {
dev_err(dev, "Error configuring chip select %d\n",
aemif->cs_data[i].cs);
goto error;
}
}
/*
* Create a child devices explicitly from here to guarantee that the
* child will be probed after the AEMIF timing parameters are set.
*/
if (np) {
for_each_available_child_of_node(np, child_np) {
ret = of_platform_populate(child_np, NULL,
dev_lookup, dev);
if (ret < 0) {
of_node_put(child_np);
goto error;
}
}
} else if (pdata) {
for (i = 0; i < pdata->num_sub_devices; i++) {
pdata->sub_devices[i].dev.parent = dev;
ret = platform_device_register(&pdata->sub_devices[i]);
if (ret) {
dev_warn(dev, "Error register sub device %s\n",
pdata->sub_devices[i].name);
}
}
}
return 0;
error:
clk_disable_unprepare(aemif->clk);
return ret;
}
static int aemif_remove(struct platform_device *pdev)
{
struct aemif_device *aemif = platform_get_drvdata(pdev);
clk_disable_unprepare(aemif->clk);
return 0;
}
static struct platform_driver aemif_driver = {
.probe = aemif_probe,
.remove = aemif_remove,
.driver = {
.name = "ti-aemif",
.of_match_table = of_match_ptr(aemif_of_match),
},
};
module_platform_driver(aemif_driver);
MODULE_AUTHOR("Murali Karicheri <[email protected]>");
MODULE_AUTHOR("Ivan Khoronzhuk <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" KBUILD_MODNAME);
|
linux-master
|
drivers/memory/ti-aemif.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
*
* Authors:
* Serge Semin <[email protected]>
*
* Baikal-T1 CM2 L2-cache Control Block driver.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/sysfs.h>
#include <linux/of.h>
#define L2_CTL_REG 0x028
#define L2_CTL_DATA_STALL_FLD 0
#define L2_CTL_DATA_STALL_MASK GENMASK(1, L2_CTL_DATA_STALL_FLD)
#define L2_CTL_TAG_STALL_FLD 2
#define L2_CTL_TAG_STALL_MASK GENMASK(3, L2_CTL_TAG_STALL_FLD)
#define L2_CTL_WS_STALL_FLD 4
#define L2_CTL_WS_STALL_MASK GENMASK(5, L2_CTL_WS_STALL_FLD)
#define L2_CTL_SET_CLKRATIO BIT(13)
#define L2_CTL_CLKRATIO_LOCK BIT(31)
#define L2_CTL_STALL_MIN 0
#define L2_CTL_STALL_MAX 3
#define L2_CTL_STALL_SET_DELAY_US 1
#define L2_CTL_STALL_SET_TOUT_US 1000
/*
* struct l2_ctl - Baikal-T1 L2 Control block private data.
* @dev: Pointer to the device structure.
* @sys_regs: Baikal-T1 System Controller registers map.
*/
struct l2_ctl {
struct device *dev;
struct regmap *sys_regs;
};
/*
* enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
* @L2_WSSTALL: Way-select latency.
* @L2_TAGSTALL: Tag latency.
* @L2_DATASTALL: Data latency.
*/
enum l2_ctl_stall {
L2_WS_STALL,
L2_TAG_STALL,
L2_DATA_STALL
};
/*
* struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
* @dev_attr: Actual sysfs device attribute.
* @id: L2-cache stall field identifier.
*/
struct l2_ctl_device_attribute {
struct device_attribute dev_attr;
enum l2_ctl_stall id;
};
#define to_l2_ctl_dev_attr(_dev_attr) \
container_of(_dev_attr, struct l2_ctl_device_attribute, dev_attr)
#define L2_CTL_ATTR_RW(_name, _prefix, _id) \
struct l2_ctl_device_attribute l2_ctl_attr_##_name = \
{ __ATTR(_name, 0644, _prefix##_show, _prefix##_store), _id }
static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val)
{
u32 data = 0;
int ret;
ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data);
if (ret)
return ret;
switch (id) {
case L2_WS_STALL:
*val = FIELD_GET(L2_CTL_WS_STALL_MASK, data);
break;
case L2_TAG_STALL:
*val = FIELD_GET(L2_CTL_TAG_STALL_MASK, data);
break;
case L2_DATA_STALL:
*val = FIELD_GET(L2_CTL_DATA_STALL_MASK, data);
break;
default:
return -EINVAL;
}
return 0;
}
static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val)
{
u32 mask = 0, data = 0;
int ret;
val = clamp_val(val, L2_CTL_STALL_MIN, L2_CTL_STALL_MAX);
switch (id) {
case L2_WS_STALL:
data = FIELD_PREP(L2_CTL_WS_STALL_MASK, val);
mask = L2_CTL_WS_STALL_MASK;
break;
case L2_TAG_STALL:
data = FIELD_PREP(L2_CTL_TAG_STALL_MASK, val);
mask = L2_CTL_TAG_STALL_MASK;
break;
case L2_DATA_STALL:
data = FIELD_PREP(L2_CTL_DATA_STALL_MASK, val);
mask = L2_CTL_DATA_STALL_MASK;
break;
default:
return -EINVAL;
}
data |= L2_CTL_SET_CLKRATIO;
mask |= L2_CTL_SET_CLKRATIO;
ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data);
if (ret)
return ret;
return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data,
data & L2_CTL_CLKRATIO_LOCK,
L2_CTL_STALL_SET_DELAY_US,
L2_CTL_STALL_SET_TOUT_US);
}
static void l2_ctl_clear_data(void *data)
{
struct l2_ctl *l2 = data;
struct platform_device *pdev = to_platform_device(l2->dev);
platform_set_drvdata(pdev, NULL);
}
static struct l2_ctl *l2_ctl_create_data(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct l2_ctl *l2;
int ret;
l2 = devm_kzalloc(dev, sizeof(*l2), GFP_KERNEL);
if (!l2)
return ERR_PTR(-ENOMEM);
ret = devm_add_action(dev, l2_ctl_clear_data, l2);
if (ret) {
dev_err(dev, "Can't add L2 CTL data clear action\n");
return ERR_PTR(ret);
}
l2->dev = dev;
platform_set_drvdata(pdev, l2);
return l2;
}
static int l2_ctl_find_sys_regs(struct l2_ctl *l2)
{
l2->sys_regs = syscon_node_to_regmap(l2->dev->of_node->parent);
if (IS_ERR(l2->sys_regs)) {
dev_err(l2->dev, "Couldn't get L2 CTL register map\n");
return PTR_ERR(l2->sys_regs);
}
return 0;
}
static int l2_ctl_of_parse_property(struct l2_ctl *l2, enum l2_ctl_stall id,
const char *propname)
{
int ret = 0;
u32 data;
if (!of_property_read_u32(l2->dev->of_node, propname, &data)) {
ret = l2_ctl_set_latency(l2, id, data);
if (ret)
dev_err(l2->dev, "Invalid value of '%s'\n", propname);
}
return ret;
}
static int l2_ctl_of_parse(struct l2_ctl *l2)
{
int ret;
ret = l2_ctl_of_parse_property(l2, L2_WS_STALL, "baikal,l2-ws-latency");
if (ret)
return ret;
ret = l2_ctl_of_parse_property(l2, L2_TAG_STALL, "baikal,l2-tag-latency");
if (ret)
return ret;
return l2_ctl_of_parse_property(l2, L2_DATA_STALL,
"baikal,l2-data-latency");
}
static ssize_t l2_ctl_latency_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct l2_ctl_device_attribute *devattr = to_l2_ctl_dev_attr(attr);
struct l2_ctl *l2 = dev_get_drvdata(dev);
u32 data;
int ret;
ret = l2_ctl_get_latency(l2, devattr->id, &data);
if (ret)
return ret;
return scnprintf(buf, PAGE_SIZE, "%u\n", data);
}
static ssize_t l2_ctl_latency_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct l2_ctl_device_attribute *devattr = to_l2_ctl_dev_attr(attr);
struct l2_ctl *l2 = dev_get_drvdata(dev);
u32 data;
int ret;
if (kstrtouint(buf, 0, &data) < 0)
return -EINVAL;
ret = l2_ctl_set_latency(l2, devattr->id, data);
if (ret)
return ret;
return count;
}
static L2_CTL_ATTR_RW(l2_ws_latency, l2_ctl_latency, L2_WS_STALL);
static L2_CTL_ATTR_RW(l2_tag_latency, l2_ctl_latency, L2_TAG_STALL);
static L2_CTL_ATTR_RW(l2_data_latency, l2_ctl_latency, L2_DATA_STALL);
static struct attribute *l2_ctl_sysfs_attrs[] = {
&l2_ctl_attr_l2_ws_latency.dev_attr.attr,
&l2_ctl_attr_l2_tag_latency.dev_attr.attr,
&l2_ctl_attr_l2_data_latency.dev_attr.attr,
NULL
};
ATTRIBUTE_GROUPS(l2_ctl_sysfs);
static void l2_ctl_remove_sysfs(void *data)
{
struct l2_ctl *l2 = data;
device_remove_groups(l2->dev, l2_ctl_sysfs_groups);
}
static int l2_ctl_init_sysfs(struct l2_ctl *l2)
{
int ret;
ret = device_add_groups(l2->dev, l2_ctl_sysfs_groups);
if (ret) {
dev_err(l2->dev, "Failed to create L2 CTL sysfs nodes\n");
return ret;
}
ret = devm_add_action_or_reset(l2->dev, l2_ctl_remove_sysfs, l2);
if (ret)
dev_err(l2->dev, "Can't add L2 CTL sysfs remove action\n");
return ret;
}
static int l2_ctl_probe(struct platform_device *pdev)
{
struct l2_ctl *l2;
int ret;
l2 = l2_ctl_create_data(pdev);
if (IS_ERR(l2))
return PTR_ERR(l2);
ret = l2_ctl_find_sys_regs(l2);
if (ret)
return ret;
ret = l2_ctl_of_parse(l2);
if (ret)
return ret;
ret = l2_ctl_init_sysfs(l2);
if (ret)
return ret;
return 0;
}
static const struct of_device_id l2_ctl_of_match[] = {
{ .compatible = "baikal,bt1-l2-ctl" },
{ }
};
MODULE_DEVICE_TABLE(of, l2_ctl_of_match);
static struct platform_driver l2_ctl_driver = {
.probe = l2_ctl_probe,
.driver = {
.name = "bt1-l2-ctl",
.of_match_table = l2_ctl_of_match
}
};
module_platform_driver(l2_ctl_driver);
MODULE_AUTHOR("Serge Semin <[email protected]>");
MODULE_DESCRIPTION("Baikal-T1 L2-cache driver");
|
linux-master
|
drivers/memory/bt1-l2-ctl.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI da8xx DDR2/mDDR controller driver
*
* Copyright (C) 2016 BayLibre SAS
*
* Author:
* Bartosz Golaszewski <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
/*
* REVISIT: Linux doesn't have a good framework for the kind of performance
* knobs this driver controls. We can't use device tree properties as it deals
* with hardware configuration rather than description. We also don't want to
* commit to maintaining some random sysfs attributes.
*
* For now we just hardcode the register values for the boards that need
* some changes (as is the case for the LCD controller on da850-lcdk - the
* first board we support here). When linux gets an appropriate framework,
* we'll easily convert the driver to it.
*/
struct da8xx_ddrctl_config_knob {
const char *name;
u32 reg;
u32 mask;
u32 shift;
};
static const struct da8xx_ddrctl_config_knob da8xx_ddrctl_knobs[] = {
{
.name = "da850-pbbpr",
.reg = 0x20,
.mask = 0xffffff00,
.shift = 0,
},
};
struct da8xx_ddrctl_setting {
const char *name;
u32 val;
};
struct da8xx_ddrctl_board_settings {
const char *board;
const struct da8xx_ddrctl_setting *settings;
};
static const struct da8xx_ddrctl_setting da850_lcdk_ddrctl_settings[] = {
{
.name = "da850-pbbpr",
.val = 0x20,
},
{ }
};
static const struct da8xx_ddrctl_board_settings da8xx_ddrctl_board_confs[] = {
{
.board = "ti,da850-lcdk",
.settings = da850_lcdk_ddrctl_settings,
},
};
static const struct da8xx_ddrctl_config_knob *
da8xx_ddrctl_match_knob(const struct da8xx_ddrctl_setting *setting)
{
const struct da8xx_ddrctl_config_knob *knob;
int i;
for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_knobs); i++) {
knob = &da8xx_ddrctl_knobs[i];
if (strcmp(knob->name, setting->name) == 0)
return knob;
}
return NULL;
}
static const struct da8xx_ddrctl_setting *da8xx_ddrctl_get_board_settings(void)
{
const struct da8xx_ddrctl_board_settings *board_settings;
int i;
for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_board_confs); i++) {
board_settings = &da8xx_ddrctl_board_confs[i];
if (of_machine_is_compatible(board_settings->board))
return board_settings->settings;
}
return NULL;
}
static int da8xx_ddrctl_probe(struct platform_device *pdev)
{
const struct da8xx_ddrctl_config_knob *knob;
const struct da8xx_ddrctl_setting *setting;
struct resource *res;
void __iomem *ddrctl;
struct device *dev;
u32 reg;
dev = &pdev->dev;
setting = da8xx_ddrctl_get_board_settings();
if (!setting) {
dev_err(dev, "no settings defined for this board\n");
return -EINVAL;
}
ddrctl = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ddrctl)) {
dev_err(dev, "unable to map memory controller registers\n");
return PTR_ERR(ddrctl);
}
for (; setting->name; setting++) {
knob = da8xx_ddrctl_match_knob(setting);
if (!knob) {
dev_warn(dev,
"no such config option: %s\n", setting->name);
continue;
}
if (knob->reg + sizeof(u32) > resource_size(res)) {
dev_warn(dev,
"register offset of '%s' exceeds mapped memory size\n",
knob->name);
continue;
}
reg = readl(ddrctl + knob->reg);
reg &= knob->mask;
reg |= setting->val << knob->shift;
dev_dbg(dev, "writing 0x%08x to %s\n", reg, setting->name);
writel(reg, ddrctl + knob->reg);
}
return 0;
}
static const struct of_device_id da8xx_ddrctl_of_match[] = {
{ .compatible = "ti,da850-ddr-controller", },
{ },
};
static struct platform_driver da8xx_ddrctl_driver = {
.probe = da8xx_ddrctl_probe,
.driver = {
.name = "da850-ddr-controller",
.of_match_table = da8xx_ddrctl_of_match,
},
};
module_platform_driver(da8xx_ddrctl_driver);
MODULE_AUTHOR("Bartosz Golaszewski <[email protected]>");
MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
|
linux-master
|
drivers/memory/da8xx-ddrctl.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* JZ4780 NAND/external memory controller (NEMC)
*
* Copyright (c) 2015 Imagination Technologies
* Author: Alex Smith <[email protected]>
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/jz4780-nemc.h>
#define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
#define NEMC_NFCSR 0x50
#define NEMC_REG_LEN 0x54
#define NEMC_SMCR_SMT BIT(0)
#define NEMC_SMCR_BW_SHIFT 6
#define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
#define NEMC_SMCR_BW_8 (0 << 6)
#define NEMC_SMCR_TAS_SHIFT 8
#define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT)
#define NEMC_SMCR_TAH_SHIFT 12
#define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT)
#define NEMC_SMCR_TBP_SHIFT 16
#define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT)
#define NEMC_SMCR_TAW_SHIFT 20
#define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT)
#define NEMC_SMCR_TSTRV_SHIFT 24
#define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT)
#define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
#define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
#define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
struct jz_soc_info {
u8 tas_tah_cycles_max;
};
struct jz4780_nemc {
spinlock_t lock;
struct device *dev;
const struct jz_soc_info *soc_info;
void __iomem *base;
struct clk *clk;
uint32_t clk_period;
unsigned long banks_present;
};
/**
* jz4780_nemc_num_banks() - count the number of banks referenced by a device
* @dev: device to count banks for, must be a child of the NEMC.
*
* Return: The number of unique NEMC banks referred to by the specified NEMC
* child device. Unique here means that a device that references the same bank
* multiple times in its "reg" property will only count once.
*/
unsigned int jz4780_nemc_num_banks(struct device *dev)
{
const __be32 *prop;
unsigned int bank, count = 0;
unsigned long referenced = 0;
int i = 0;
while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
bank = of_read_number(prop, 1);
if (!(referenced & BIT(bank))) {
referenced |= BIT(bank);
count++;
}
}
return count;
}
EXPORT_SYMBOL(jz4780_nemc_num_banks);
/**
* jz4780_nemc_set_type() - set the type of device connected to a bank
* @dev: child device of the NEMC.
* @bank: bank number to configure.
* @type: type of device connected to the bank.
*/
void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
enum jz4780_nemc_bank_type type)
{
struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
uint32_t nfcsr;
nfcsr = readl(nemc->base + NEMC_NFCSR);
/* TODO: Support toggle NAND devices. */
switch (type) {
case JZ4780_NEMC_BANK_SRAM:
nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
break;
case JZ4780_NEMC_BANK_NAND:
nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
nfcsr |= NEMC_NFCSR_NFEn(bank);
break;
}
writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_set_type);
/**
* jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
* @dev: child device of the NEMC.
* @bank: bank number of device.
* @assert: whether the chip enable pin should be asserted.
*
* (De-)asserts the chip enable pin for the NAND device connected to the
* specified bank.
*/
void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
{
struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
uint32_t nfcsr;
nfcsr = readl(nemc->base + NEMC_NFCSR);
if (assert)
nfcsr |= NEMC_NFCSR_NFCEn(bank);
else
nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
writel(nfcsr, nemc->base + NEMC_NFCSR);
}
EXPORT_SYMBOL(jz4780_nemc_assert);
static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
{
unsigned long rate;
rate = clk_get_rate(nemc->clk);
if (!rate)
return 0;
/* Return in picoseconds. */
return div64_ul(1000000000000ull, rate);
}
static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
{
return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
}
static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
unsigned int bank,
struct device_node *node)
{
uint32_t smcr, val, cycles;
/*
* Conversion of tBP and tAW cycle counts to values supported by the
* hardware (round up to the next supported value).
*/
static const u8 convert_tBP_tAW[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
/* 11 - 12 -> 12 cycles */
11, 11,
/* 13 - 15 -> 15 cycles */
12, 12, 12,
/* 16 - 20 -> 20 cycles */
13, 13, 13, 13, 13,
/* 21 - 25 -> 25 cycles */
14, 14, 14, 14, 14,
/* 26 - 31 -> 31 cycles */
15, 15, 15, 15, 15, 15
};
smcr = readl(nemc->base + NEMC_SMCRn(bank));
smcr &= ~NEMC_SMCR_SMT;
if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
smcr &= ~NEMC_SMCR_BW_MASK;
switch (val) {
case 8:
smcr |= NEMC_SMCR_BW_8;
break;
default:
/*
* Earlier SoCs support a 16 bit bus width (the 4780
* does not), until those are properly supported, error.
*/
dev_err(nemc->dev, "unsupported bus width: %u\n", val);
return false;
}
}
if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
smcr &= ~NEMC_SMCR_TAS_MASK;
cycles = jz4780_nemc_ns_to_cycles(nemc, val);
if (cycles > nemc->soc_info->tas_tah_cycles_max) {
dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
val, cycles);
return false;
}
smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
}
if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
smcr &= ~NEMC_SMCR_TAH_MASK;
cycles = jz4780_nemc_ns_to_cycles(nemc, val);
if (cycles > nemc->soc_info->tas_tah_cycles_max) {
dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
val, cycles);
return false;
}
smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
}
if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
smcr &= ~NEMC_SMCR_TBP_MASK;
cycles = jz4780_nemc_ns_to_cycles(nemc, val);
if (cycles > 31) {
dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
val, cycles);
return false;
}
smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
}
if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
smcr &= ~NEMC_SMCR_TAW_MASK;
cycles = jz4780_nemc_ns_to_cycles(nemc, val);
if (cycles > 31) {
dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
val, cycles);
return false;
}
smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
}
if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
smcr &= ~NEMC_SMCR_TSTRV_MASK;
cycles = jz4780_nemc_ns_to_cycles(nemc, val);
if (cycles > 63) {
dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
val, cycles);
return false;
}
smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
}
writel(smcr, nemc->base + NEMC_SMCRn(bank));
return true;
}
static int jz4780_nemc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz4780_nemc *nemc;
struct resource *res;
struct device_node *child;
const __be32 *prop;
unsigned int bank;
unsigned long referenced;
int i, ret;
nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
if (!nemc)
return -ENOMEM;
nemc->soc_info = device_get_match_data(dev);
if (!nemc->soc_info)
return -EINVAL;
spin_lock_init(&nemc->lock);
nemc->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
/*
* The driver currently only uses the registers up to offset
* NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
* NEMC registers, we only request the registers we will use for now;
* that way the EFUSE driver can probe too.
*/
if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
dev_err(dev, "unable to request I/O memory region\n");
return -EBUSY;
}
nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
if (!nemc->base) {
dev_err(dev, "failed to get I/O memory\n");
return -ENOMEM;
}
writel(0, nemc->base + NEMC_NFCSR);
nemc->clk = devm_clk_get(dev, NULL);
if (IS_ERR(nemc->clk)) {
dev_err(dev, "failed to get clock\n");
return PTR_ERR(nemc->clk);
}
ret = clk_prepare_enable(nemc->clk);
if (ret) {
dev_err(dev, "failed to enable clock: %d\n", ret);
return ret;
}
nemc->clk_period = jz4780_nemc_clk_period(nemc);
if (!nemc->clk_period) {
dev_err(dev, "failed to calculate clock period\n");
clk_disable_unprepare(nemc->clk);
return -EINVAL;
}
/*
* Iterate over child devices, check that they do not conflict with
* each other, and register child devices for them. If a child device
* has invalid properties, it is ignored and no platform device is
* registered for it.
*/
for_each_child_of_node(nemc->dev->of_node, child) {
referenced = 0;
i = 0;
while ((prop = of_get_address(child, i++, NULL, NULL))) {
bank = of_read_number(prop, 1);
if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
dev_err(nemc->dev,
"%pOF requests invalid bank %u\n",
child, bank);
/* Will continue the outer loop below. */
referenced = 0;
break;
}
referenced |= BIT(bank);
}
if (!referenced) {
dev_err(nemc->dev, "%pOF has no addresses\n",
child);
continue;
} else if (nemc->banks_present & referenced) {
dev_err(nemc->dev, "%pOF conflicts with another node\n",
child);
continue;
}
/* Configure bank parameters. */
for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
referenced = 0;
break;
}
}
if (referenced) {
if (of_platform_device_create(child, NULL, nemc->dev))
nemc->banks_present |= referenced;
}
}
platform_set_drvdata(pdev, nemc);
dev_info(dev, "JZ4780 NEMC initialised\n");
return 0;
}
static int jz4780_nemc_remove(struct platform_device *pdev)
{
struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
clk_disable_unprepare(nemc->clk);
return 0;
}
static const struct jz_soc_info jz4740_soc_info = {
.tas_tah_cycles_max = 7,
};
static const struct jz_soc_info jz4780_soc_info = {
.tas_tah_cycles_max = 15,
};
static const struct of_device_id jz4780_nemc_dt_match[] = {
{ .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
{ .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
{},
};
static struct platform_driver jz4780_nemc_driver = {
.probe = jz4780_nemc_probe,
.remove = jz4780_nemc_remove,
.driver = {
.name = "jz4780-nemc",
.of_match_table = of_match_ptr(jz4780_nemc_dt_match),
},
};
static int __init jz4780_nemc_init(void)
{
return platform_driver_register(&jz4780_nemc_driver);
}
subsys_initcall(jz4780_nemc_init);
|
linux-master
|
drivers/memory/jz4780-nemc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* DFL device driver for EMIF private feature
*
* Copyright (C) 2020 Intel Corporation, Inc.
*
*/
#include <linux/bitfield.h>
#include <linux/dfl.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#define FME_FEATURE_ID_EMIF 0x9
#define EMIF_STAT 0x8
#define EMIF_STAT_INIT_DONE_SFT 0
#define EMIF_STAT_CALC_FAIL_SFT 8
#define EMIF_STAT_CLEAR_BUSY_SFT 16
#define EMIF_CTRL 0x10
#define EMIF_CTRL_CLEAR_EN_SFT 0
#define EMIF_CTRL_CLEAR_EN_MSK GENMASK_ULL(7, 0)
#define EMIF_POLL_INVL 10000 /* us */
#define EMIF_POLL_TIMEOUT 5000000 /* us */
/*
* The Capability Register replaces the Control Register (at the same
* offset) for EMIF feature revisions > 0. The bitmask that indicates
* the presence of memory channels exists in both the Capability Register
* and Control Register definitions. These can be thought of as a C union.
* The Capability Register definitions are used to check for the existence
* of a memory channel, and the Control Register definitions are used for
* managing the memory-clear functionality in revision 0.
*/
#define EMIF_CAPABILITY_BASE 0x10
#define EMIF_CAPABILITY_CHN_MSK_V0 GENMASK_ULL(3, 0)
#define EMIF_CAPABILITY_CHN_MSK GENMASK_ULL(7, 0)
struct dfl_emif {
struct device *dev;
void __iomem *base;
spinlock_t lock; /* Serialises access to EMIF_CTRL reg */
};
struct emif_attr {
struct device_attribute attr;
u32 shift;
u32 index;
};
#define to_emif_attr(dev_attr) \
container_of(dev_attr, struct emif_attr, attr)
static ssize_t emif_state_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct emif_attr *eattr = to_emif_attr(attr);
struct dfl_emif *de = dev_get_drvdata(dev);
u64 val;
val = readq(de->base + EMIF_STAT);
return sysfs_emit(buf, "%u\n",
!!(val & BIT_ULL(eattr->shift + eattr->index)));
}
static ssize_t emif_clear_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct emif_attr *eattr = to_emif_attr(attr);
struct dfl_emif *de = dev_get_drvdata(dev);
u64 clear_busy_msk, clear_en_msk, val;
void __iomem *base = de->base;
if (!sysfs_streq(buf, "1"))
return -EINVAL;
clear_busy_msk = BIT_ULL(EMIF_STAT_CLEAR_BUSY_SFT + eattr->index);
clear_en_msk = BIT_ULL(EMIF_CTRL_CLEAR_EN_SFT + eattr->index);
spin_lock(&de->lock);
/* The CLEAR_EN field is WO, but other fields are RW */
val = readq(base + EMIF_CTRL);
val &= ~EMIF_CTRL_CLEAR_EN_MSK;
val |= clear_en_msk;
writeq(val, base + EMIF_CTRL);
spin_unlock(&de->lock);
if (readq_poll_timeout(base + EMIF_STAT, val,
!(val & clear_busy_msk),
EMIF_POLL_INVL, EMIF_POLL_TIMEOUT)) {
dev_err(de->dev, "timeout, fail to clear\n");
return -ETIMEDOUT;
}
return count;
}
#define emif_state_attr(_name, _shift, _index) \
static struct emif_attr emif_attr_##inf##_index##_##_name = \
{ .attr = __ATTR(inf##_index##_##_name, 0444, \
emif_state_show, NULL), \
.shift = (_shift), .index = (_index) }
#define emif_clear_attr(_index) \
static struct emif_attr emif_attr_##inf##_index##_clear = \
{ .attr = __ATTR(inf##_index##_clear, 0200, \
NULL, emif_clear_store), \
.index = (_index) }
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 0);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 1);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 2);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 3);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 4);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 5);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 6);
emif_state_attr(init_done, EMIF_STAT_INIT_DONE_SFT, 7);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 0);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 1);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 2);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 3);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 4);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 5);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 6);
emif_state_attr(cal_fail, EMIF_STAT_CALC_FAIL_SFT, 7);
emif_clear_attr(0);
emif_clear_attr(1);
emif_clear_attr(2);
emif_clear_attr(3);
emif_clear_attr(4);
emif_clear_attr(5);
emif_clear_attr(6);
emif_clear_attr(7);
static struct attribute *dfl_emif_attrs[] = {
&emif_attr_inf0_init_done.attr.attr,
&emif_attr_inf0_cal_fail.attr.attr,
&emif_attr_inf0_clear.attr.attr,
&emif_attr_inf1_init_done.attr.attr,
&emif_attr_inf1_cal_fail.attr.attr,
&emif_attr_inf1_clear.attr.attr,
&emif_attr_inf2_init_done.attr.attr,
&emif_attr_inf2_cal_fail.attr.attr,
&emif_attr_inf2_clear.attr.attr,
&emif_attr_inf3_init_done.attr.attr,
&emif_attr_inf3_cal_fail.attr.attr,
&emif_attr_inf3_clear.attr.attr,
&emif_attr_inf4_init_done.attr.attr,
&emif_attr_inf4_cal_fail.attr.attr,
&emif_attr_inf4_clear.attr.attr,
&emif_attr_inf5_init_done.attr.attr,
&emif_attr_inf5_cal_fail.attr.attr,
&emif_attr_inf5_clear.attr.attr,
&emif_attr_inf6_init_done.attr.attr,
&emif_attr_inf6_cal_fail.attr.attr,
&emif_attr_inf6_clear.attr.attr,
&emif_attr_inf7_init_done.attr.attr,
&emif_attr_inf7_cal_fail.attr.attr,
&emif_attr_inf7_clear.attr.attr,
NULL,
};
static umode_t dfl_emif_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct dfl_emif *de = dev_get_drvdata(kobj_to_dev(kobj));
struct emif_attr *eattr = container_of(attr, struct emif_attr,
attr.attr);
struct dfl_device *ddev = to_dfl_dev(de->dev);
u64 val;
/*
* This device supports up to 8 memory interfaces, but not all
* interfaces are used on different platforms. The read out value of
* CAPABILITY_CHN_MSK field (which is a bitmap) indicates which
* interfaces are available.
*/
if (ddev->revision > 0 && strstr(attr->name, "_clear"))
return 0;
if (ddev->revision == 0)
val = FIELD_GET(EMIF_CAPABILITY_CHN_MSK_V0,
readq(de->base + EMIF_CAPABILITY_BASE));
else
val = FIELD_GET(EMIF_CAPABILITY_CHN_MSK,
readq(de->base + EMIF_CAPABILITY_BASE));
return (val & BIT_ULL(eattr->index)) ? attr->mode : 0;
}
static const struct attribute_group dfl_emif_group = {
.is_visible = dfl_emif_visible,
.attrs = dfl_emif_attrs,
};
static const struct attribute_group *dfl_emif_groups[] = {
&dfl_emif_group,
NULL,
};
static int dfl_emif_probe(struct dfl_device *ddev)
{
struct device *dev = &ddev->dev;
struct dfl_emif *de;
de = devm_kzalloc(dev, sizeof(*de), GFP_KERNEL);
if (!de)
return -ENOMEM;
de->base = devm_ioremap_resource(dev, &ddev->mmio_res);
if (IS_ERR(de->base))
return PTR_ERR(de->base);
de->dev = dev;
spin_lock_init(&de->lock);
dev_set_drvdata(dev, de);
return 0;
}
static const struct dfl_device_id dfl_emif_ids[] = {
{ FME_ID, FME_FEATURE_ID_EMIF },
{ }
};
MODULE_DEVICE_TABLE(dfl, dfl_emif_ids);
static struct dfl_driver dfl_emif_driver = {
.drv = {
.name = "dfl-emif",
.dev_groups = dfl_emif_groups,
},
.id_table = dfl_emif_ids,
.probe = dfl_emif_probe,
};
module_dfl_driver(dfl_emif_driver);
MODULE_DESCRIPTION("DFL EMIF driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/dfl-emif.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* EMIF driver
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* Aneesh V <[email protected]>
* Santosh Shilimkar <[email protected]>
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/platform_data/emif_plat.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/pm.h>
#include "emif.h"
#include "jedec_ddr.h"
#include "of_memory.h"
/**
* struct emif_data - Per device static data for driver's use
* @duplicate: Whether the DDR devices attached to this EMIF
* instance are exactly same as that on EMIF1. In
* this case we can save some memory and processing
* @temperature_level: Maximum temperature of LPDDR2 devices attached
* to this EMIF - read from MR4 register. If there
* are two devices attached to this EMIF, this
* value is the maximum of the two temperature
* levels.
* @node: node in the device list
* @base: base address of memory-mapped IO registers.
* @dev: device pointer.
* @regs_cache: An array of 'struct emif_regs' that stores
* calculated register values for different
* frequencies, to avoid re-calculating them on
* each DVFS transition.
* @curr_regs: The set of register values used in the last
* frequency change (i.e. corresponding to the
* frequency in effect at the moment)
* @plat_data: Pointer to saved platform data.
* @debugfs_root: dentry to the root folder for EMIF in debugfs
* @np_ddr: Pointer to ddr device tree node
*/
struct emif_data {
u8 duplicate;
u8 temperature_level;
u8 lpmode;
struct list_head node;
unsigned long irq_state;
void __iomem *base;
struct device *dev;
struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
struct emif_regs *curr_regs;
struct emif_platform_data *plat_data;
struct dentry *debugfs_root;
struct device_node *np_ddr;
};
static struct emif_data *emif1;
static DEFINE_SPINLOCK(emif_lock);
static unsigned long irq_state;
static LIST_HEAD(device_list);
#ifdef CONFIG_DEBUG_FS
static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
struct emif_regs *regs)
{
u32 type = emif->plat_data->device_info->type;
u32 ip_rev = emif->plat_data->ip_rev;
seq_printf(s, "EMIF register cache dump for %dMHz\n",
regs->freq/1000000);
seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
if (ip_rev == EMIF_4D) {
seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
regs->read_idle_ctrl_shdw_normal);
seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
regs->read_idle_ctrl_shdw_volt_ramp);
} else if (ip_rev == EMIF_4D5) {
seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
regs->dll_calib_ctrl_shdw_normal);
seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
regs->dll_calib_ctrl_shdw_volt_ramp);
}
if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
regs->ref_ctrl_shdw_derated);
seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
regs->sdram_tim1_shdw_derated);
seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
regs->sdram_tim3_shdw_derated);
}
}
static int emif_regdump_show(struct seq_file *s, void *unused)
{
struct emif_data *emif = s->private;
struct emif_regs **regs_cache;
int i;
if (emif->duplicate)
regs_cache = emif1->regs_cache;
else
regs_cache = emif->regs_cache;
for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
do_emif_regdump_show(s, emif, regs_cache[i]);
seq_putc(s, '\n');
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(emif_regdump);
static int emif_mr4_show(struct seq_file *s, void *unused)
{
struct emif_data *emif = s->private;
seq_printf(s, "MR4=%d\n", emif->temperature_level);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(emif_mr4);
static int __init_or_module emif_debugfs_init(struct emif_data *emif)
{
emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
&emif_regdump_fops);
debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
&emif_mr4_fops);
return 0;
}
static void __exit emif_debugfs_exit(struct emif_data *emif)
{
debugfs_remove_recursive(emif->debugfs_root);
emif->debugfs_root = NULL;
}
#else
static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
{
return 0;
}
static inline void __exit emif_debugfs_exit(struct emif_data *emif)
{
}
#endif
/*
* Get bus width used by EMIF. Note that this may be different from the
* bus width of the DDR devices used. For instance two 16-bit DDR devices
* may be connected to a given CS of EMIF. In this case bus width as far
* as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
*/
static u32 get_emif_bus_width(struct emif_data *emif)
{
u32 width;
void __iomem *base = emif->base;
width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
>> NARROW_MODE_SHIFT;
width = width == 0 ? 32 : 16;
return width;
}
static void set_lpmode(struct emif_data *emif, u8 lpmode)
{
u32 temp;
void __iomem *base = emif->base;
/*
* Workaround for errata i743 - LPDDR2 Power-Down State is Not
* Efficient
*
* i743 DESCRIPTION:
* The EMIF supports power-down state for low power. The EMIF
* automatically puts the SDRAM into power-down after the memory is
* not accessed for a defined number of cycles and the
* EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
* As the EMIF supports automatic output impedance calibration, a ZQ
* calibration long command is issued every time it exits active
* power-down and precharge power-down modes. The EMIF waits and
* blocks any other command during this calibration.
* The EMIF does not allow selective disabling of ZQ calibration upon
* exit of power-down mode. Due to very short periods of power-down
* cycles, ZQ calibration overhead creates bandwidth issues and
* increases overall system power consumption. On the other hand,
* issuing ZQ calibration long commands when exiting self-refresh is
* still required.
*
* WORKAROUND
* Because there is no power consumption benefit of the power-down due
* to the calibration and there is a performance risk, the guideline
* is to not allow power-down state and, therefore, to not have set
* the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
*/
if ((emif->plat_data->ip_rev == EMIF_4D) &&
(lpmode == EMIF_LP_MODE_PWR_DN)) {
WARN_ONCE(1,
"REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
/* rollback LP_MODE to Self-refresh mode */
lpmode = EMIF_LP_MODE_SELF_REFRESH;
}
temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
temp &= ~LP_MODE_MASK;
temp |= (lpmode << LP_MODE_SHIFT);
writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
}
static void do_freq_update(void)
{
struct emif_data *emif;
/*
* Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
*
* i728 DESCRIPTION:
* The EMIF automatically puts the SDRAM into self-refresh mode
* after the EMIF has not performed accesses during
* EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
* and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
* to 0x2. If during a small window the following three events
* occur:
* - The SR_TIMING counter expires
* - And frequency change is requested
* - And OCP access is requested
* Then it causes instable clock on the DDR interface.
*
* WORKAROUND
* To avoid the occurrence of the three events, the workaround
* is to disable the self-refresh when requesting a frequency
* change. Before requesting a frequency change the software must
* program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
* frequency change has been done, the software can reprogram
* EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
*/
list_for_each_entry(emif, &device_list, node) {
if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
set_lpmode(emif, EMIF_LP_MODE_DISABLE);
}
/*
* TODO: Do FREQ_UPDATE here when an API
* is available for this as part of the new
* clock framework
*/
list_for_each_entry(emif, &device_list, node) {
if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
}
}
/* Find addressing table entry based on the device's type and density */
static const struct lpddr2_addressing *get_addressing_table(
const struct ddr_device_info *device_info)
{
u32 index, type, density;
type = device_info->type;
density = device_info->density;
switch (type) {
case DDR_TYPE_LPDDR2_S4:
index = density - 1;
break;
case DDR_TYPE_LPDDR2_S2:
switch (density) {
case DDR_DENSITY_1Gb:
case DDR_DENSITY_2Gb:
index = density + 3;
break;
default:
index = density - 1;
}
break;
default:
return NULL;
}
return &lpddr2_jedec_addressing_table[index];
}
static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
bool cs1_used, bool cal_resistors_per_cs)
{
u32 zq = 0, val = 0;
val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
zq |= val << ZQ_REFINTERVAL_SHIFT;
val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
zq |= val << ZQ_ZQCL_MULT_SHIFT;
val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
zq |= val << ZQ_ZQINIT_MULT_SHIFT;
zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
if (cal_resistors_per_cs)
zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
else
zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
val = cs1_used ? 1 : 0;
zq |= val << ZQ_CS1EN_SHIFT;
return zq;
}
static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
const struct emif_custom_configs *custom_configs, bool cs1_used,
u32 sdram_io_width, u32 emif_bus_width)
{
u32 alert = 0, interval, devcnt;
if (custom_configs && (custom_configs->mask &
EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
interval = custom_configs->temp_alert_poll_interval_ms;
else
interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
interval *= 1000000; /* Convert to ns */
interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
alert |= (interval << TA_REFINTERVAL_SHIFT);
/*
* sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
* also to this form and subtract to get TA_DEVCNT, which is
* in log2(x) form.
*/
emif_bus_width = __fls(emif_bus_width) - 1;
devcnt = emif_bus_width - sdram_io_width;
alert |= devcnt << TA_DEVCNT_SHIFT;
/* DEVWDT is in 'log2(x) - 3' form */
alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
alert |= 1 << TA_SFEXITEN_SHIFT;
alert |= 1 << TA_CS0EN_SHIFT;
alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
return alert;
}
static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
{
u32 pwr_mgmt_ctrl = 0, timeout;
u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
u32 mask;
u8 shift;
struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
lpmode = cust_cfgs->lpmode;
timeout_perf = cust_cfgs->lpmode_timeout_performance;
timeout_pwr = cust_cfgs->lpmode_timeout_power;
freq_threshold = cust_cfgs->lpmode_freq_threshold;
}
/* Timeout based on DDR frequency */
timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
/*
* The value to be set in register is "log2(timeout) - 3"
* if timeout < 16 load 0 in register
* if timeout is not a power of 2, round to next highest power of 2
*/
if (timeout < 16) {
timeout = 0;
} else {
if (timeout & (timeout - 1))
timeout <<= 1;
timeout = __fls(timeout) - 3;
}
switch (lpmode) {
case EMIF_LP_MODE_CLOCK_STOP:
shift = CS_TIM_SHIFT;
mask = CS_TIM_MASK;
break;
case EMIF_LP_MODE_SELF_REFRESH:
/* Workaround for errata i735 */
if (timeout < 6)
timeout = 6;
shift = SR_TIM_SHIFT;
mask = SR_TIM_MASK;
break;
case EMIF_LP_MODE_PWR_DN:
shift = PD_TIM_SHIFT;
mask = PD_TIM_MASK;
break;
case EMIF_LP_MODE_DISABLE:
default:
mask = 0;
shift = 0;
break;
}
/* Round to maximum in case of overflow, BUT warn! */
if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
lpmode,
timeout_perf,
timeout_pwr,
freq_threshold);
WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
timeout, mask >> shift);
timeout = mask >> shift;
}
/* Setup required timing */
pwr_mgmt_ctrl = (timeout << shift) & mask;
/* setup a default mask for rest of the modes */
pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
~mask;
/* No CS_TIM in EMIF_4D5 */
if (ip_rev == EMIF_4D5)
pwr_mgmt_ctrl &= ~CS_TIM_MASK;
pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
return pwr_mgmt_ctrl;
}
/*
* Get the temperature level of the EMIF instance:
* Reads the MR4 register of attached SDRAM parts to find out the temperature
* level. If there are two parts attached(one on each CS), then the temperature
* level for the EMIF instance is the higher of the two temperatures.
*/
static void get_temperature_level(struct emif_data *emif)
{
u32 temp, temperature_level;
void __iomem *base;
base = emif->base;
/* Read mode register 4 */
writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
MR4_SDRAM_REF_RATE_SHIFT;
if (emif->plat_data->device_info->cs1_used) {
writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
temp = (temp & MR4_SDRAM_REF_RATE_MASK)
>> MR4_SDRAM_REF_RATE_SHIFT;
temperature_level = max(temp, temperature_level);
}
/* treat everything less than nominal(3) in MR4 as nominal */
if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
temperature_level = SDRAM_TEMP_NOMINAL;
/* if we get reserved value in MR4 persist with the existing value */
if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
emif->temperature_level = temperature_level;
}
/*
* setup_temperature_sensitive_regs() - set the timings for temperature
* sensitive registers. This happens once at initialisation time based
* on the temperature at boot time and subsequently based on the temperature
* alert interrupt. Temperature alert can happen when the temperature
* increases or drops. So this function can have the effect of either
* derating the timings or going back to nominal values.
*/
static void setup_temperature_sensitive_regs(struct emif_data *emif,
struct emif_regs *regs)
{
u32 tim1, tim3, ref_ctrl, type;
void __iomem *base = emif->base;
u32 temperature;
type = emif->plat_data->device_info->type;
tim1 = regs->sdram_tim1_shdw;
tim3 = regs->sdram_tim3_shdw;
ref_ctrl = regs->ref_ctrl_shdw;
/* No de-rating for non-lpddr2 devices */
if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
goto out;
temperature = emif->temperature_level;
if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
ref_ctrl = regs->ref_ctrl_shdw_derated;
} else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
tim1 = regs->sdram_tim1_shdw_derated;
tim3 = regs->sdram_tim3_shdw_derated;
ref_ctrl = regs->ref_ctrl_shdw_derated;
}
out:
writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
}
static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
{
u32 old_temp_level;
irqreturn_t ret = IRQ_HANDLED;
struct emif_custom_configs *custom_configs;
spin_lock_irqsave(&emif_lock, irq_state);
old_temp_level = emif->temperature_level;
get_temperature_level(emif);
if (unlikely(emif->temperature_level == old_temp_level)) {
goto out;
} else if (!emif->curr_regs) {
dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
goto out;
}
custom_configs = emif->plat_data->custom_configs;
/*
* IF we detect higher than "nominal rating" from DDR sensor
* on an unsupported DDR part, shutdown system
*/
if (custom_configs && !(custom_configs->mask &
EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
dev_err(emif->dev,
"%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n",
__func__, emif->temperature_level);
/*
* Temperature far too high - do kernel_power_off()
* from thread context
*/
emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
ret = IRQ_WAKE_THREAD;
goto out;
}
}
if (emif->temperature_level < old_temp_level ||
emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
/*
* Temperature coming down - defer handling to thread OR
* Temperature far too high - do kernel_power_off() from
* thread context
*/
ret = IRQ_WAKE_THREAD;
} else {
/* Temperature is going up - handle immediately */
setup_temperature_sensitive_regs(emif, emif->curr_regs);
do_freq_update();
}
out:
spin_unlock_irqrestore(&emif_lock, irq_state);
return ret;
}
static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
{
u32 interrupts;
struct emif_data *emif = dev_id;
void __iomem *base = emif->base;
struct device *dev = emif->dev;
irqreturn_t ret = IRQ_HANDLED;
/* Save the status and clear it */
interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
/*
* Handle temperature alert
* Temperature alert should be same for all ports
* So, it's enough to process it only for one of the ports
*/
if (interrupts & TA_SYS_MASK)
ret = handle_temp_alert(base, emif);
if (interrupts & ERR_SYS_MASK)
dev_err(dev, "Access error from SYS port - %x\n", interrupts);
if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
/* Save the status and clear it */
interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
if (interrupts & ERR_LL_MASK)
dev_err(dev, "Access error from LL port - %x\n",
interrupts);
}
return ret;
}
static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
{
struct emif_data *emif = dev_id;
if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
/* If we have Power OFF ability, use it, else try restarting */
if (kernel_can_power_off()) {
kernel_power_off();
} else {
WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
kernel_restart("SDRAM Over-temp Emergency restart");
}
return IRQ_HANDLED;
}
spin_lock_irqsave(&emif_lock, irq_state);
if (emif->curr_regs) {
setup_temperature_sensitive_regs(emif, emif->curr_regs);
do_freq_update();
} else {
dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
}
spin_unlock_irqrestore(&emif_lock, irq_state);
return IRQ_HANDLED;
}
static void clear_all_interrupts(struct emif_data *emif)
{
void __iomem *base = emif->base;
writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
base + EMIF_LL_OCP_INTERRUPT_STATUS);
}
static void disable_and_clear_all_interrupts(struct emif_data *emif)
{
void __iomem *base = emif->base;
/* Disable all interrupts */
writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
/* Clear all interrupts */
clear_all_interrupts(emif);
}
static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
{
u32 interrupts, type;
void __iomem *base = emif->base;
type = emif->plat_data->device_info->type;
clear_all_interrupts(emif);
/* Enable interrupts for SYS interface */
interrupts = EN_ERR_SYS_MASK;
if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
interrupts |= EN_TA_SYS_MASK;
writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
/* Enable interrupts for LL interface */
if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
/* TA need not be enabled for LL */
interrupts = EN_ERR_LL_MASK;
writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
}
/* setup IRQ handlers */
return devm_request_threaded_irq(emif->dev, irq,
emif_interrupt_handler,
emif_threaded_isr,
0, dev_name(emif->dev),
emif);
}
static void __init_or_module emif_onetime_settings(struct emif_data *emif)
{
u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
void __iomem *base = emif->base;
const struct lpddr2_addressing *addressing;
const struct ddr_device_info *device_info;
device_info = emif->plat_data->device_info;
addressing = get_addressing_table(device_info);
/*
* Init power management settings
* We don't know the frequency yet. Use a high frequency
* value for a conservative timeout setting
*/
pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
emif->plat_data->ip_rev);
emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
/* Init ZQ calibration settings */
zq = get_zq_config_reg(addressing, device_info->cs1_used,
device_info->cal_resistors_per_cs);
writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
/* Check temperature level temperature level*/
get_temperature_level(emif);
if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
/* Init temperature polling */
temp_alert_cfg = get_temp_alert_config(addressing,
emif->plat_data->custom_configs, device_info->cs1_used,
device_info->io_width, get_emif_bus_width(emif));
writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
/*
* Program external PHY control registers that are not frequency
* dependent
*/
if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
return;
writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
}
static void get_default_timings(struct emif_data *emif)
{
struct emif_platform_data *pd = emif->plat_data;
pd->timings = lpddr2_jedec_timings;
pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
dev_warn(emif->dev, "%s: using default timings\n", __func__);
}
static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
u32 ip_rev, struct device *dev)
{
int valid;
valid = (type == DDR_TYPE_LPDDR2_S4 ||
type == DDR_TYPE_LPDDR2_S2)
&& (density >= DDR_DENSITY_64Mb
&& density <= DDR_DENSITY_8Gb)
&& (io_width >= DDR_IO_WIDTH_8
&& io_width <= DDR_IO_WIDTH_32);
/* Combinations of EMIF and PHY revisions that we support today */
switch (ip_rev) {
case EMIF_4D:
valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
break;
case EMIF_4D5:
valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
break;
default:
valid = 0;
}
if (!valid)
dev_err(dev, "%s: invalid DDR details\n", __func__);
return valid;
}
static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
struct device *dev)
{
int valid = 1;
if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
(cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
valid = cust_cfgs->lpmode_freq_threshold &&
cust_cfgs->lpmode_timeout_performance &&
cust_cfgs->lpmode_timeout_power;
if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
if (!valid)
dev_warn(dev, "%s: invalid custom configs\n", __func__);
return valid;
}
#if defined(CONFIG_OF)
static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
struct emif_data *emif)
{
struct emif_custom_configs *cust_cfgs = NULL;
int len;
const __be32 *lpmode, *poll_intvl;
lpmode = of_get_property(np_emif, "low-power-mode", &len);
poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
if (lpmode || poll_intvl)
cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
GFP_KERNEL);
if (!cust_cfgs)
return;
if (lpmode) {
cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
cust_cfgs->lpmode = be32_to_cpup(lpmode);
of_property_read_u32(np_emif,
"low-power-mode-timeout-performance",
&cust_cfgs->lpmode_timeout_performance);
of_property_read_u32(np_emif,
"low-power-mode-timeout-power",
&cust_cfgs->lpmode_timeout_power);
of_property_read_u32(np_emif,
"low-power-mode-freq-threshold",
&cust_cfgs->lpmode_freq_threshold);
}
if (poll_intvl) {
cust_cfgs->mask |=
EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
cust_cfgs->temp_alert_poll_interval_ms =
be32_to_cpup(poll_intvl);
}
if (of_find_property(np_emif, "extended-temp-part", &len))
cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
devm_kfree(emif->dev, cust_cfgs);
return;
}
emif->plat_data->custom_configs = cust_cfgs;
}
static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
struct device_node *np_ddr,
struct ddr_device_info *dev_info)
{
u32 density = 0, io_width = 0;
int len;
if (of_find_property(np_emif, "cs1-used", &len))
dev_info->cs1_used = true;
if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
dev_info->cal_resistors_per_cs = true;
if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4"))
dev_info->type = DDR_TYPE_LPDDR2_S4;
else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2"))
dev_info->type = DDR_TYPE_LPDDR2_S2;
of_property_read_u32(np_ddr, "density", &density);
of_property_read_u32(np_ddr, "io-width", &io_width);
/* Convert from density in Mb to the density encoding in jedc_ddr.h */
if (density & (density - 1))
dev_info->density = 0;
else
dev_info->density = __fls(density) - 5;
/* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
if (io_width & (io_width - 1))
dev_info->io_width = 0;
else
dev_info->io_width = __fls(io_width) - 1;
}
static struct emif_data * __init_or_module of_get_memory_device_details(
struct device_node *np_emif, struct device *dev)
{
struct emif_data *emif = NULL;
struct ddr_device_info *dev_info = NULL;
struct emif_platform_data *pd = NULL;
struct device_node *np_ddr;
int len;
np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
if (!np_ddr)
goto error;
emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
if (!emif || !pd || !dev_info) {
dev_err(dev, "%s: Out of memory!!\n",
__func__);
goto error;
}
emif->plat_data = pd;
pd->device_info = dev_info;
emif->dev = dev;
emif->np_ddr = np_ddr;
emif->temperature_level = SDRAM_TEMP_NOMINAL;
if (of_device_is_compatible(np_emif, "ti,emif-4d"))
emif->plat_data->ip_rev = EMIF_4D;
else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
emif->plat_data->ip_rev = EMIF_4D5;
of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
of_get_ddr_info(np_emif, np_ddr, dev_info);
if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
pd->device_info->io_width, pd->phy_type, pd->ip_rev,
emif->dev)) {
dev_err(dev, "%s: invalid device data!!\n", __func__);
goto error;
}
/*
* For EMIF instances other than EMIF1 see if the devices connected
* are exactly same as on EMIF1(which is typically the case). If so,
* mark it as a duplicate of EMIF1. This will save some memory and
* computation.
*/
if (emif1 && emif1->np_ddr == np_ddr) {
emif->duplicate = true;
goto out;
} else if (emif1) {
dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
__func__);
}
of_get_custom_configs(np_emif, emif);
emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
emif->plat_data->device_info->type,
&emif->plat_data->timings_arr_size);
emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
goto out;
error:
return NULL;
out:
return emif;
}
#else
static struct emif_data * __init_or_module of_get_memory_device_details(
struct device_node *np_emif, struct device *dev)
{
return NULL;
}
#endif
static struct emif_data *__init_or_module get_device_details(
struct platform_device *pdev)
{
u32 size;
struct emif_data *emif = NULL;
struct ddr_device_info *dev_info;
struct emif_custom_configs *cust_cfgs;
struct emif_platform_data *pd;
struct device *dev;
void *temp;
pd = pdev->dev.platform_data;
dev = &pdev->dev;
if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
pd->device_info->density, pd->device_info->io_width,
pd->phy_type, pd->ip_rev, dev))) {
dev_err(dev, "%s: invalid device data\n", __func__);
goto error;
}
emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
if (!emif || !temp || !dev_info)
goto error;
memcpy(temp, pd, sizeof(*pd));
pd = temp;
memcpy(dev_info, pd->device_info, sizeof(*dev_info));
pd->device_info = dev_info;
emif->plat_data = pd;
emif->dev = dev;
emif->temperature_level = SDRAM_TEMP_NOMINAL;
/*
* For EMIF instances other than EMIF1 see if the devices connected
* are exactly same as on EMIF1(which is typically the case). If so,
* mark it as a duplicate of EMIF1 and skip copying timings data.
* This will save some memory and some computation later.
*/
emif->duplicate = emif1 && (memcmp(dev_info,
emif1->plat_data->device_info,
sizeof(struct ddr_device_info)) == 0);
if (emif->duplicate) {
pd->timings = NULL;
pd->min_tck = NULL;
goto out;
} else if (emif1) {
dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
__func__);
}
/*
* Copy custom configs - ignore allocation error, if any, as
* custom_configs is not very critical
*/
cust_cfgs = pd->custom_configs;
if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
if (temp)
memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
pd->custom_configs = temp;
}
/*
* Copy timings and min-tck values from platform data. If it is not
* available or if memory allocation fails, use JEDEC defaults
*/
size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
if (pd->timings) {
temp = devm_kzalloc(dev, size, GFP_KERNEL);
if (temp) {
memcpy(temp, pd->timings, size);
pd->timings = temp;
} else {
get_default_timings(emif);
}
} else {
get_default_timings(emif);
}
if (pd->min_tck) {
temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
if (temp) {
memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
pd->min_tck = temp;
} else {
pd->min_tck = &lpddr2_jedec_min_tck;
}
} else {
pd->min_tck = &lpddr2_jedec_min_tck;
}
out:
return emif;
error:
return NULL;
}
static int __init_or_module emif_probe(struct platform_device *pdev)
{
struct emif_data *emif;
int irq, ret;
if (pdev->dev.of_node)
emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
else
emif = get_device_details(pdev);
if (!emif) {
pr_err("%s: error getting device data\n", __func__);
goto error;
}
list_add(&emif->node, &device_list);
/* Save pointers to each other in emif and device structures */
emif->dev = &pdev->dev;
platform_set_drvdata(pdev, emif);
emif->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emif->base))
goto error;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
goto error;
emif_onetime_settings(emif);
emif_debugfs_init(emif);
disable_and_clear_all_interrupts(emif);
ret = setup_interrupts(emif, irq);
if (ret)
goto error;
/* One-time actions taken on probing the first device */
if (!emif1) {
emif1 = emif;
/*
* TODO: register notifiers for frequency and voltage
* change here once the respective frameworks are
* available
*/
}
dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
__func__, emif->base, irq);
return 0;
error:
return -ENODEV;
}
static int __exit emif_remove(struct platform_device *pdev)
{
struct emif_data *emif = platform_get_drvdata(pdev);
emif_debugfs_exit(emif);
return 0;
}
static void emif_shutdown(struct platform_device *pdev)
{
struct emif_data *emif = platform_get_drvdata(pdev);
disable_and_clear_all_interrupts(emif);
}
#if defined(CONFIG_OF)
static const struct of_device_id emif_of_match[] = {
{ .compatible = "ti,emif-4d" },
{ .compatible = "ti,emif-4d5" },
{},
};
MODULE_DEVICE_TABLE(of, emif_of_match);
#endif
static struct platform_driver emif_driver = {
.remove = __exit_p(emif_remove),
.shutdown = emif_shutdown,
.driver = {
.name = "emif",
.of_match_table = of_match_ptr(emif_of_match),
},
};
module_platform_driver_probe(emif_driver, emif_probe);
MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:emif");
MODULE_AUTHOR("Texas Instruments Inc");
|
linux-master
|
drivers/memory/emif.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* OpenFirmware helpers for memory drivers
*
* Copyright (C) 2012 Texas Instruments, Inc.
* Copyright (C) 2019 Samsung Electronics Co., Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <[email protected]>
*/
#include <linux/device.h>
#include <linux/of.h>
#include <linux/gfp.h>
#include <linux/export.h>
#include "jedec_ddr.h"
#include "of_memory.h"
/**
* of_get_min_tck() - extract min timing values for ddr
* @np: pointer to ddr device tree node
* @dev: device requesting for min timing values
*
* Populates the lpddr2_min_tck structure by extracting data
* from device tree node. Returns a pointer to the populated
* structure. If any error in populating the structure, returns
* default min timings provided by JEDEC.
*/
const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np,
struct device *dev)
{
int ret = 0;
struct lpddr2_min_tck *min;
min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
if (!min)
goto default_min_tck;
ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin);
ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
if (ret) {
devm_kfree(dev, min);
goto default_min_tck;
}
return min;
default_min_tck:
dev_warn(dev, "Using default min-tck values\n");
return &lpddr2_jedec_min_tck;
}
EXPORT_SYMBOL(of_get_min_tck);
static int of_do_get_timings(struct device_node *np,
struct lpddr2_timings *tim)
{
int ret;
ret = of_property_read_u32(np, "max-freq", &tim->max_freq);
ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
ret |= of_property_read_u32(np, "tWR", &tim->tWR);
ret |= of_property_read_u32(np, "tRAS-min", &tim->tRAS_min);
ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
ret |= of_property_read_u32(np, "tXP", &tim->tXP);
ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
ret |= of_property_read_u32(np, "tDQSCK-max", &tim->tDQSCK_max);
ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
ret |= of_property_read_u32(np, "tZQCS", &tim->tZQCS);
ret |= of_property_read_u32(np, "tZQCL", &tim->tZQCL);
ret |= of_property_read_u32(np, "tZQinit", &tim->tZQinit);
ret |= of_property_read_u32(np, "tRAS-max-ns", &tim->tRAS_max_ns);
ret |= of_property_read_u32(np, "tDQSCK-max-derated",
&tim->tDQSCK_max_derated);
return ret;
}
/**
* of_get_ddr_timings() - extracts the ddr timings and updates no of
* frequencies available.
* @np_ddr: Pointer to ddr device tree node
* @dev: Device requesting for ddr timings
* @device_type: Type of ddr(LPDDR2 S2/S4)
* @nr_frequencies: No of frequencies available for ddr
* (updated by this function)
*
* Populates lpddr2_timings structure by extracting data from device
* tree node. Returns pointer to populated structure. If any error
* while populating, returns default timings provided by JEDEC.
*/
const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr,
struct device *dev,
u32 device_type,
u32 *nr_frequencies)
{
struct lpddr2_timings *timings = NULL;
u32 arr_sz = 0, i = 0;
struct device_node *np_tim;
char *tim_compat = NULL;
switch (device_type) {
case DDR_TYPE_LPDDR2_S2:
case DDR_TYPE_LPDDR2_S4:
tim_compat = "jedec,lpddr2-timings";
break;
default:
dev_warn(dev, "Unsupported memory type\n");
}
for_each_child_of_node(np_ddr, np_tim)
if (of_device_is_compatible(np_tim, tim_compat))
arr_sz++;
if (arr_sz)
timings = devm_kcalloc(dev, arr_sz, sizeof(*timings),
GFP_KERNEL);
if (!timings)
goto default_timings;
for_each_child_of_node(np_ddr, np_tim) {
if (of_device_is_compatible(np_tim, tim_compat)) {
if (of_do_get_timings(np_tim, &timings[i])) {
of_node_put(np_tim);
devm_kfree(dev, timings);
goto default_timings;
}
i++;
}
}
*nr_frequencies = arr_sz;
return timings;
default_timings:
dev_warn(dev, "Using default memory timings\n");
*nr_frequencies = ARRAY_SIZE(lpddr2_jedec_timings);
return lpddr2_jedec_timings;
}
EXPORT_SYMBOL(of_get_ddr_timings);
/**
* of_lpddr3_get_min_tck() - extract min timing values for lpddr3
* @np: pointer to ddr device tree node
* @dev: device requesting for min timing values
*
* Populates the lpddr3_min_tck structure by extracting data
* from device tree node. Returns a pointer to the populated
* structure. If any error in populating the structure, returns NULL.
*/
const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
struct device *dev)
{
int ret = 0;
struct lpddr3_min_tck *min;
min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
if (!min)
goto default_min_tck;
ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC);
ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb);
ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC);
ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS);
ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C);
ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C);
ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL);
ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK);
ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL);
ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR);
ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD);
if (ret) {
dev_warn(dev, "Errors while parsing min-tck values\n");
devm_kfree(dev, min);
goto default_min_tck;
}
return min;
default_min_tck:
dev_warn(dev, "Using default min-tck values\n");
return NULL;
}
EXPORT_SYMBOL(of_lpddr3_get_min_tck);
static int of_lpddr3_do_get_timings(struct device_node *np,
struct lpddr3_timings *tim)
{
int ret;
ret = of_property_read_u32(np, "max-freq", &tim->max_freq);
if (ret)
/* Deprecated way of passing max-freq as 'reg' */
ret = of_property_read_u32(np, "reg", &tim->max_freq);
ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
ret |= of_property_read_u32(np, "tRFC", &tim->tRFC);
ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb);
ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
ret |= of_property_read_u32(np, "tRC", &tim->tRC);
ret |= of_property_read_u32(np, "tRAS", &tim->tRAS);
ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
ret |= of_property_read_u32(np, "tWR", &tim->tWR);
ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C);
ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C);
ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
ret |= of_property_read_u32(np, "tXSR", &tim->tXSR);
ret |= of_property_read_u32(np, "tXP", &tim->tXP);
ret |= of_property_read_u32(np, "tCKE", &tim->tCKE);
ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
ret |= of_property_read_u32(np, "tMRD", &tim->tMRD);
return ret;
}
/**
* of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of
* frequencies available.
* @np_ddr: Pointer to ddr device tree node
* @dev: Device requesting for ddr timings
* @device_type: Type of ddr
* @nr_frequencies: No of frequencies available for ddr
* (updated by this function)
*
* Populates lpddr3_timings structure by extracting data from device
* tree node. Returns pointer to populated structure. If any error
* while populating, returns NULL.
*/
const struct lpddr3_timings
*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
u32 device_type, u32 *nr_frequencies)
{
struct lpddr3_timings *timings = NULL;
u32 arr_sz = 0, i = 0;
struct device_node *np_tim;
char *tim_compat = NULL;
switch (device_type) {
case DDR_TYPE_LPDDR3:
tim_compat = "jedec,lpddr3-timings";
break;
default:
dev_warn(dev, "Unsupported memory type\n");
}
for_each_child_of_node(np_ddr, np_tim)
if (of_device_is_compatible(np_tim, tim_compat))
arr_sz++;
if (arr_sz)
timings = devm_kcalloc(dev, arr_sz, sizeof(*timings),
GFP_KERNEL);
if (!timings)
goto default_timings;
for_each_child_of_node(np_ddr, np_tim) {
if (of_device_is_compatible(np_tim, tim_compat)) {
if (of_lpddr3_do_get_timings(np_tim, &timings[i])) {
devm_kfree(dev, timings);
of_node_put(np_tim);
goto default_timings;
}
i++;
}
}
*nr_frequencies = arr_sz;
return timings;
default_timings:
dev_warn(dev, "Failed to get timings\n");
*nr_frequencies = 0;
return NULL;
}
EXPORT_SYMBOL(of_lpddr3_get_ddr_timings);
/**
* of_lpddr2_get_info() - extracts information about the lpddr2 chip.
* @np: Pointer to device tree node containing lpddr2 info
* @dev: Device requesting info
*
* Populates lpddr2_info structure by extracting data from device
* tree node. Returns pointer to populated structure. If error
* happened while populating, returns NULL. If property is missing
* in a device-tree, then the corresponding value is set to -ENOENT.
*/
const struct lpddr2_info
*of_lpddr2_get_info(struct device_node *np, struct device *dev)
{
struct lpddr2_info *ret_info, info = {};
struct property *prop;
const char *cp;
int err;
u32 revision_id[2];
err = of_property_read_u32_array(np, "revision-id", revision_id, 2);
if (!err) {
info.revision_id1 = revision_id[0];
info.revision_id2 = revision_id[1];
} else {
err = of_property_read_u32(np, "revision-id1", &info.revision_id1);
if (err)
info.revision_id1 = -ENOENT;
err = of_property_read_u32(np, "revision-id2", &info.revision_id2);
if (err)
info.revision_id2 = -ENOENT;
}
err = of_property_read_u32(np, "io-width", &info.io_width);
if (err)
return NULL;
info.io_width = 32 / info.io_width - 1;
err = of_property_read_u32(np, "density", &info.density);
if (err)
return NULL;
info.density = ffs(info.density) - 7;
if (of_device_is_compatible(np, "jedec,lpddr2-s4"))
info.arch_type = LPDDR2_TYPE_S4;
else if (of_device_is_compatible(np, "jedec,lpddr2-s2"))
info.arch_type = LPDDR2_TYPE_S2;
else if (of_device_is_compatible(np, "jedec,lpddr2-nvm"))
info.arch_type = LPDDR2_TYPE_NVM;
else
return NULL;
prop = of_find_property(np, "compatible", NULL);
for (cp = of_prop_next_string(prop, NULL); cp;
cp = of_prop_next_string(prop, cp)) {
#define OF_LPDDR2_VENDOR_CMP(compat, ID) \
if (!of_compat_cmp(cp, compat ",", strlen(compat ","))) { \
info.manufacturer_id = LPDDR2_MANID_##ID; \
break; \
}
OF_LPDDR2_VENDOR_CMP("samsung", SAMSUNG)
OF_LPDDR2_VENDOR_CMP("qimonda", QIMONDA)
OF_LPDDR2_VENDOR_CMP("elpida", ELPIDA)
OF_LPDDR2_VENDOR_CMP("etron", ETRON)
OF_LPDDR2_VENDOR_CMP("nanya", NANYA)
OF_LPDDR2_VENDOR_CMP("hynix", HYNIX)
OF_LPDDR2_VENDOR_CMP("mosel", MOSEL)
OF_LPDDR2_VENDOR_CMP("winbond", WINBOND)
OF_LPDDR2_VENDOR_CMP("esmt", ESMT)
OF_LPDDR2_VENDOR_CMP("spansion", SPANSION)
OF_LPDDR2_VENDOR_CMP("sst", SST)
OF_LPDDR2_VENDOR_CMP("zmos", ZMOS)
OF_LPDDR2_VENDOR_CMP("intel", INTEL)
OF_LPDDR2_VENDOR_CMP("numonyx", NUMONYX)
OF_LPDDR2_VENDOR_CMP("micron", MICRON)
#undef OF_LPDDR2_VENDOR_CMP
}
if (!info.manufacturer_id)
info.manufacturer_id = -ENOENT;
ret_info = devm_kzalloc(dev, sizeof(*ret_info), GFP_KERNEL);
if (ret_info)
*ret_info = info;
return ret_info;
}
EXPORT_SYMBOL(of_lpddr2_get_info);
|
linux-master
|
drivers/memory/of_memory.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* ARM PL353 SMC driver
*
* Copyright (C) 2012 - 2018 Xilinx, Inc
* Author: Punnaiah Choudary Kalluri <[email protected]>
* Author: Naga Sureshkumar Relli <[email protected]>
*/
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
/**
* struct pl353_smc_data - Private smc driver structure
* @memclk: Pointer to the peripheral clock
* @aclk: Pointer to the AXI peripheral clock
*/
struct pl353_smc_data {
struct clk *memclk;
struct clk *aclk;
};
static int __maybe_unused pl353_smc_suspend(struct device *dev)
{
struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
clk_disable(pl353_smc->memclk);
clk_disable(pl353_smc->aclk);
return 0;
}
static int __maybe_unused pl353_smc_resume(struct device *dev)
{
struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
int ret;
ret = clk_enable(pl353_smc->aclk);
if (ret) {
dev_err(dev, "Cannot enable axi domain clock.\n");
return ret;
}
ret = clk_enable(pl353_smc->memclk);
if (ret) {
dev_err(dev, "Cannot enable memory clock.\n");
clk_disable(pl353_smc->aclk);
return ret;
}
return ret;
}
static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
pl353_smc_resume);
static const struct of_device_id pl353_smc_supported_children[] = {
{
.compatible = "cfi-flash"
},
{
.compatible = "arm,pl353-nand-r2p1",
},
{}
};
static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device_node *of_node = adev->dev.of_node;
const struct of_device_id *match = NULL;
struct pl353_smc_data *pl353_smc;
struct device_node *child;
int err;
pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);
if (!pl353_smc)
return -ENOMEM;
pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");
if (IS_ERR(pl353_smc->aclk)) {
dev_err(&adev->dev, "aclk clock not found.\n");
return PTR_ERR(pl353_smc->aclk);
}
pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk");
if (IS_ERR(pl353_smc->memclk)) {
dev_err(&adev->dev, "memclk clock not found.\n");
return PTR_ERR(pl353_smc->memclk);
}
err = clk_prepare_enable(pl353_smc->aclk);
if (err) {
dev_err(&adev->dev, "Unable to enable AXI clock.\n");
return err;
}
err = clk_prepare_enable(pl353_smc->memclk);
if (err) {
dev_err(&adev->dev, "Unable to enable memory clock.\n");
goto disable_axi_clk;
}
amba_set_drvdata(adev, pl353_smc);
/* Find compatible children. Only a single child is supported */
for_each_available_child_of_node(of_node, child) {
match = of_match_node(pl353_smc_supported_children, child);
if (!match) {
dev_warn(&adev->dev, "unsupported child node\n");
continue;
}
break;
}
if (!match) {
err = -ENODEV;
dev_err(&adev->dev, "no matching children\n");
goto disable_mem_clk;
}
of_platform_device_create(child, NULL, &adev->dev);
of_node_put(child);
return 0;
disable_mem_clk:
clk_disable_unprepare(pl353_smc->memclk);
disable_axi_clk:
clk_disable_unprepare(pl353_smc->aclk);
return err;
}
static void pl353_smc_remove(struct amba_device *adev)
{
struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev);
clk_disable_unprepare(pl353_smc->memclk);
clk_disable_unprepare(pl353_smc->aclk);
}
static const struct amba_id pl353_ids[] = {
{
.id = 0x00041353,
.mask = 0x000fffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl353_ids);
static struct amba_driver pl353_smc_driver = {
.drv = {
.owner = THIS_MODULE,
.name = "pl353-smc",
.pm = &pl353_smc_dev_pm_ops,
},
.id_table = pl353_ids,
.probe = pl353_smc_probe,
.remove = pl353_smc_remove,
};
module_amba_driver(pl353_smc_driver);
MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION("ARM PL353 SMC Driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/memory/pl353-smc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI AM33XX SRAM EMIF Driver
*
* Copyright (C) 2016-2017 Texas Instruments Inc.
* Dave Gerlach
*/
#include <linux/err.h>
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sram.h>
#include <linux/ti-emif-sram.h>
#include "emif.h"
#define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
(unsigned long)&ti_emif_sram)
#define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
struct ti_emif_data {
phys_addr_t ti_emif_sram_phys;
phys_addr_t ti_emif_sram_data_phys;
unsigned long ti_emif_sram_virt;
unsigned long ti_emif_sram_data_virt;
struct gen_pool *sram_pool_code;
struct gen_pool *sram_pool_data;
struct ti_emif_pm_data pm_data;
struct ti_emif_pm_functions pm_functions;
};
static struct ti_emif_data *emif_instance;
static u32 sram_suspend_address(struct ti_emif_data *emif_data,
unsigned long addr)
{
return (emif_data->ti_emif_sram_virt +
TI_EMIF_SRAM_SYMBOL_OFFSET(addr));
}
static phys_addr_t sram_resume_address(struct ti_emif_data *emif_data,
unsigned long addr)
{
return ((unsigned long)emif_data->ti_emif_sram_phys +
TI_EMIF_SRAM_SYMBOL_OFFSET(addr));
}
static void ti_emif_free_sram(struct ti_emif_data *emif_data)
{
gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt,
ti_emif_sram_sz);
gen_pool_free(emif_data->sram_pool_data,
emif_data->ti_emif_sram_data_virt,
sizeof(struct emif_regs_amx3));
}
static int ti_emif_alloc_sram(struct device *dev,
struct ti_emif_data *emif_data)
{
struct device_node *np = dev->of_node;
int ret;
emif_data->sram_pool_code = of_gen_pool_get(np, "sram", 0);
if (!emif_data->sram_pool_code) {
dev_err(dev, "Unable to get sram pool for ocmcram code\n");
return -ENODEV;
}
emif_data->ti_emif_sram_virt =
gen_pool_alloc(emif_data->sram_pool_code,
ti_emif_sram_sz);
if (!emif_data->ti_emif_sram_virt) {
dev_err(dev, "Unable to allocate code memory from ocmcram\n");
return -ENOMEM;
}
/* Save physical address to calculate resume offset during pm init */
emif_data->ti_emif_sram_phys =
gen_pool_virt_to_phys(emif_data->sram_pool_code,
emif_data->ti_emif_sram_virt);
/* Get sram pool for data section and allocate space */
emif_data->sram_pool_data = of_gen_pool_get(np, "sram", 1);
if (!emif_data->sram_pool_data) {
dev_err(dev, "Unable to get sram pool for ocmcram data\n");
ret = -ENODEV;
goto err_free_sram_code;
}
emif_data->ti_emif_sram_data_virt =
gen_pool_alloc(emif_data->sram_pool_data,
sizeof(struct emif_regs_amx3));
if (!emif_data->ti_emif_sram_data_virt) {
dev_err(dev, "Unable to allocate data memory from ocmcram\n");
ret = -ENOMEM;
goto err_free_sram_code;
}
/* Save physical address to calculate resume offset during pm init */
emif_data->ti_emif_sram_data_phys =
gen_pool_virt_to_phys(emif_data->sram_pool_data,
emif_data->ti_emif_sram_data_virt);
/*
* These functions are called during suspend path while MMU is
* still on so add virtual base to offset for absolute address
*/
emif_data->pm_functions.save_context =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_save_context);
emif_data->pm_functions.enter_sr =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_enter_sr);
emif_data->pm_functions.abort_sr =
sram_suspend_address(emif_data,
(unsigned long)ti_emif_abort_sr);
/*
* These are called during resume path when MMU is not enabled
* so physical address is used instead
*/
emif_data->pm_functions.restore_context =
sram_resume_address(emif_data,
(unsigned long)ti_emif_restore_context);
emif_data->pm_functions.exit_sr =
sram_resume_address(emif_data,
(unsigned long)ti_emif_exit_sr);
emif_data->pm_functions.run_hw_leveling =
sram_resume_address(emif_data,
(unsigned long)ti_emif_run_hw_leveling);
emif_data->pm_data.regs_virt =
(struct emif_regs_amx3 *)emif_data->ti_emif_sram_data_virt;
emif_data->pm_data.regs_phys = emif_data->ti_emif_sram_data_phys;
return 0;
err_free_sram_code:
gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt,
ti_emif_sram_sz);
return ret;
}
static int ti_emif_push_sram(struct device *dev, struct ti_emif_data *emif_data)
{
void *copy_addr;
u32 data_addr;
copy_addr = sram_exec_copy(emif_data->sram_pool_code,
(void *)emif_data->ti_emif_sram_virt,
&ti_emif_sram, ti_emif_sram_sz);
if (!copy_addr) {
dev_err(dev, "Cannot copy emif code to sram\n");
return -ENODEV;
}
data_addr = sram_suspend_address(emif_data,
(unsigned long)&ti_emif_pm_sram_data);
copy_addr = sram_exec_copy(emif_data->sram_pool_code,
(void *)data_addr,
&emif_data->pm_data,
sizeof(emif_data->pm_data));
if (!copy_addr) {
dev_err(dev, "Cannot copy emif data to code sram\n");
return -ENODEV;
}
return 0;
}
/*
* Due to Usage Note 3.1.2 "DDR3: JEDEC Compliance for Maximum
* Self-Refresh Command Limit" found in AM335x Silicon Errata
* (Document SPRZ360F Revised November 2013) we must configure
* the self refresh delay timer to 0xA (8192 cycles) to avoid
* generating too many refresh command from the EMIF.
*/
static void ti_emif_configure_sr_delay(struct ti_emif_data *emif_data)
{
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
(emif_data->pm_data.ti_emif_base_addr_virt +
EMIF_POWER_MANAGEMENT_CONTROL));
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
(emif_data->pm_data.ti_emif_base_addr_virt +
EMIF_POWER_MANAGEMENT_CTRL_SHDW));
}
/**
* ti_emif_copy_pm_function_table - copy mapping of pm funcs in sram
* @sram_pool: pointer to struct gen_pool where dst resides
* @dst: void * to address that table should be copied
*
* Returns 0 if success other error code if table is not available
*/
int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst)
{
void *copy_addr;
if (!emif_instance)
return -ENODEV;
copy_addr = sram_exec_copy(sram_pool, dst,
&emif_instance->pm_functions,
sizeof(emif_instance->pm_functions));
if (!copy_addr)
return -ENODEV;
return 0;
}
EXPORT_SYMBOL_GPL(ti_emif_copy_pm_function_table);
/**
* ti_emif_get_mem_type - return type for memory type in use
*
* Returns memory type value read from EMIF or error code if fails
*/
int ti_emif_get_mem_type(void)
{
unsigned long temp;
if (!emif_instance)
return -ENODEV;
temp = readl(emif_instance->pm_data.ti_emif_base_addr_virt +
EMIF_SDRAM_CONFIG);
temp = (temp & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
return temp;
}
EXPORT_SYMBOL_GPL(ti_emif_get_mem_type);
static const struct of_device_id ti_emif_of_match[] = {
{ .compatible = "ti,emif-am3352", .data =
(void *)EMIF_SRAM_AM33_REG_LAYOUT, },
{ .compatible = "ti,emif-am4372", .data =
(void *)EMIF_SRAM_AM43_REG_LAYOUT, },
{},
};
MODULE_DEVICE_TABLE(of, ti_emif_of_match);
#ifdef CONFIG_PM_SLEEP
static int ti_emif_resume(struct device *dev)
{
unsigned long tmp =
__raw_readl((void __iomem *)emif_instance->ti_emif_sram_virt);
/*
* Check to see if what we are copying is already present in the
* first byte at the destination, only copy if it is not which
* indicates we have lost context and sram no longer contains
* the PM code
*/
if (tmp != ti_emif_sram)
ti_emif_push_sram(dev, emif_instance);
return 0;
}
static int ti_emif_suspend(struct device *dev)
{
/*
* The contents will be present in DDR hence no need to
* explicitly save
*/
return 0;
}
#endif /* CONFIG_PM_SLEEP */
static int ti_emif_probe(struct platform_device *pdev)
{
int ret;
struct resource *res;
struct device *dev = &pdev->dev;
struct ti_emif_data *emif_data;
emif_data = devm_kzalloc(dev, sizeof(*emif_data), GFP_KERNEL);
if (!emif_data)
return -ENOMEM;
emif_data->pm_data.ti_emif_sram_config = (unsigned long) device_get_match_data(&pdev->dev);
emif_data->pm_data.ti_emif_base_addr_virt = devm_platform_get_and_ioremap_resource(pdev,
0,
&res);
if (IS_ERR(emif_data->pm_data.ti_emif_base_addr_virt)) {
ret = PTR_ERR(emif_data->pm_data.ti_emif_base_addr_virt);
return ret;
}
emif_data->pm_data.ti_emif_base_addr_phys = res->start;
ti_emif_configure_sr_delay(emif_data);
ret = ti_emif_alloc_sram(dev, emif_data);
if (ret)
return ret;
ret = ti_emif_push_sram(dev, emif_data);
if (ret)
goto fail_free_sram;
emif_instance = emif_data;
return 0;
fail_free_sram:
ti_emif_free_sram(emif_data);
return ret;
}
static int ti_emif_remove(struct platform_device *pdev)
{
struct ti_emif_data *emif_data = emif_instance;
emif_instance = NULL;
ti_emif_free_sram(emif_data);
return 0;
}
static const struct dev_pm_ops ti_emif_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(ti_emif_suspend, ti_emif_resume)
};
static struct platform_driver ti_emif_driver = {
.probe = ti_emif_probe,
.remove = ti_emif_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = ti_emif_of_match,
.pm = &ti_emif_pm_ops,
},
};
module_platform_driver(ti_emif_driver);
MODULE_AUTHOR("Dave Gerlach <[email protected]>");
MODULE_DESCRIPTION("Texas Instruments SRAM EMIF driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/ti-emif-pm.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* CoreNet Coherency Fabric error reporting
*
* Copyright 2014 Freescale Semiconductor Inc.
*/
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
enum ccf_version {
CCF1,
CCF2,
};
struct ccf_info {
enum ccf_version version;
int err_reg_offs;
bool has_brr;
};
static const struct ccf_info ccf1_info = {
.version = CCF1,
.err_reg_offs = 0xa00,
.has_brr = false,
};
static const struct ccf_info ccf2_info = {
.version = CCF2,
.err_reg_offs = 0xe40,
.has_brr = true,
};
/*
* This register is present but not documented, with different values for
* IP_ID, on other chips with fsl,corenet2-cf such as t4240 and b4860.
*/
#define CCF_BRR 0xbf8
#define CCF_BRR_IPID 0xffff0000
#define CCF_BRR_IPID_T1040 0x09310000
static const struct of_device_id ccf_matches[] = {
{
.compatible = "fsl,corenet1-cf",
.data = &ccf1_info,
},
{
.compatible = "fsl,corenet2-cf",
.data = &ccf2_info,
},
{}
};
MODULE_DEVICE_TABLE(of, ccf_matches);
struct ccf_err_regs {
u32 errdet; /* 0x00 Error Detect Register */
/* 0x04 Error Enable (ccf1)/Disable (ccf2) Register */
u32 errdis;
/* 0x08 Error Interrupt Enable Register (ccf2 only) */
u32 errinten;
u32 cecar; /* 0x0c Error Capture Attribute Register */
u32 cecaddrh; /* 0x10 Error Capture Address High */
u32 cecaddrl; /* 0x14 Error Capture Address Low */
u32 cecar2; /* 0x18 Error Capture Attribute Register 2 */
};
/* LAE/CV also valid for errdis and errinten */
#define ERRDET_LAE (1 << 0) /* Local Access Error */
#define ERRDET_CV (1 << 1) /* Coherency Violation */
#define ERRDET_UTID (1 << 2) /* Unavailable Target ID (t1040) */
#define ERRDET_MCST (1 << 3) /* Multicast Stash (t1040) */
#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */
#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT)
#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */
#define CECAR_VAL (1 << 0) /* Valid (ccf1 only) */
#define CECAR_UVT (1 << 15) /* Unavailable target ID (ccf1) */
#define CECAR_SRCID_SHIFT_CCF1 24
#define CECAR_SRCID_MASK_CCF1 (0xff << CECAR_SRCID_SHIFT_CCF1)
#define CECAR_SRCID_SHIFT_CCF2 18
#define CECAR_SRCID_MASK_CCF2 (0xff << CECAR_SRCID_SHIFT_CCF2)
#define CECADDRH_ADDRH 0xff
struct ccf_private {
const struct ccf_info *info;
struct device *dev;
void __iomem *regs;
struct ccf_err_regs __iomem *err_regs;
bool t1040;
};
static irqreturn_t ccf_irq(int irq, void *dev_id)
{
struct ccf_private *ccf = dev_id;
static DEFINE_RATELIMIT_STATE(ratelimit, DEFAULT_RATELIMIT_INTERVAL,
DEFAULT_RATELIMIT_BURST);
u32 errdet, cecar, cecar2;
u64 addr;
u32 src_id;
bool uvt = false;
bool cap_valid = false;
errdet = ioread32be(&ccf->err_regs->errdet);
cecar = ioread32be(&ccf->err_regs->cecar);
cecar2 = ioread32be(&ccf->err_regs->cecar2);
addr = ioread32be(&ccf->err_regs->cecaddrl);
addr |= ((u64)(ioread32be(&ccf->err_regs->cecaddrh) &
CECADDRH_ADDRH)) << 32;
if (!__ratelimit(&ratelimit))
goto out;
switch (ccf->info->version) {
case CCF1:
if (cecar & CECAR_VAL) {
if (cecar & CECAR_UVT)
uvt = true;
src_id = (cecar & CECAR_SRCID_MASK_CCF1) >>
CECAR_SRCID_SHIFT_CCF1;
cap_valid = true;
}
break;
case CCF2:
if (errdet & ERRDET_CAP) {
src_id = (cecar & CECAR_SRCID_MASK_CCF2) >>
CECAR_SRCID_SHIFT_CCF2;
cap_valid = true;
}
break;
}
dev_crit(ccf->dev, "errdet 0x%08x cecar 0x%08x cecar2 0x%08x\n",
errdet, cecar, cecar2);
if (errdet & ERRDET_LAE) {
if (uvt)
dev_crit(ccf->dev, "LAW Unavailable Target ID\n");
else
dev_crit(ccf->dev, "Local Access Window Error\n");
}
if (errdet & ERRDET_CV)
dev_crit(ccf->dev, "Coherency Violation\n");
if (errdet & ERRDET_UTID)
dev_crit(ccf->dev, "Unavailable Target ID\n");
if (errdet & ERRDET_MCST)
dev_crit(ccf->dev, "Multicast Stash\n");
if (cap_valid) {
dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n",
addr, src_id);
}
out:
iowrite32be(errdet, &ccf->err_regs->errdet);
return errdet ? IRQ_HANDLED : IRQ_NONE;
}
static int ccf_probe(struct platform_device *pdev)
{
struct ccf_private *ccf;
const struct of_device_id *match;
u32 errinten;
int ret, irq;
match = of_match_device(ccf_matches, &pdev->dev);
if (WARN_ON(!match))
return -ENODEV;
ccf = devm_kzalloc(&pdev->dev, sizeof(*ccf), GFP_KERNEL);
if (!ccf)
return -ENOMEM;
ccf->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ccf->regs))
return PTR_ERR(ccf->regs);
ccf->dev = &pdev->dev;
ccf->info = match->data;
ccf->err_regs = ccf->regs + ccf->info->err_reg_offs;
if (ccf->info->has_brr) {
u32 brr = ioread32be(ccf->regs + CCF_BRR);
if ((brr & CCF_BRR_IPID) == CCF_BRR_IPID_T1040)
ccf->t1040 = true;
}
dev_set_drvdata(&pdev->dev, ccf);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, ccf_irq, 0, pdev->name, ccf);
if (ret) {
dev_err(&pdev->dev, "%s: can't request irq\n", __func__);
return ret;
}
errinten = ERRDET_LAE | ERRDET_CV;
if (ccf->t1040)
errinten |= ERRDET_UTID | ERRDET_MCST;
switch (ccf->info->version) {
case CCF1:
/* On CCF1 this register enables rather than disables. */
iowrite32be(errinten, &ccf->err_regs->errdis);
break;
case CCF2:
iowrite32be(0, &ccf->err_regs->errdis);
iowrite32be(errinten, &ccf->err_regs->errinten);
break;
}
return 0;
}
static int ccf_remove(struct platform_device *pdev)
{
struct ccf_private *ccf = dev_get_drvdata(&pdev->dev);
switch (ccf->info->version) {
case CCF1:
iowrite32be(0, &ccf->err_regs->errdis);
break;
case CCF2:
/*
* We clear errdis on ccf1 because that's the only way to
* disable interrupts, but on ccf2 there's no need to disable
* detection.
*/
iowrite32be(0, &ccf->err_regs->errinten);
break;
}
return 0;
}
static struct platform_driver ccf_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = ccf_matches,
},
.probe = ccf_probe,
.remove = ccf_remove,
};
module_platform_driver(ccf_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Freescale Semiconductor");
MODULE_DESCRIPTION("Freescale CoreNet Coherency Fabric error reporting");
|
linux-master
|
drivers/memory/fsl-corenet-cf.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* EBI driver for Atmel chips
* inspired by the fsl weim bus driver
*
* Copyright (C) 2013 Jean-Jacques Hiblot <[email protected]>
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/atmel-matrix.h>
#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <soc/at91/atmel-sfr.h>
#define AT91_EBI_NUM_CS 8
struct atmel_ebi_dev_config {
int cs;
struct atmel_smc_cs_conf smcconf;
};
struct atmel_ebi;
struct atmel_ebi_dev {
struct list_head node;
struct atmel_ebi *ebi;
u32 mode;
int numcs;
struct atmel_ebi_dev_config configs[];
};
struct atmel_ebi_caps {
unsigned int available_cs;
unsigned int ebi_csa_offs;
const char *regmap_name;
void (*get_config)(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf);
int (*xlate_config)(struct atmel_ebi_dev *ebid,
struct device_node *configs_np,
struct atmel_ebi_dev_config *conf);
void (*apply_config)(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf);
};
struct atmel_ebi {
struct clk *clk;
struct regmap *regmap;
struct {
struct regmap *regmap;
struct clk *clk;
const struct atmel_hsmc_reg_layout *layout;
} smc;
struct device *dev;
const struct atmel_ebi_caps *caps;
struct list_head devs;
};
struct atmel_smc_timing_xlate {
const char *name;
int (*converter)(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int nycles);
unsigned int shift;
};
#define ATMEL_SMC_SETUP_XLATE(nm, pos) \
{ .name = nm, .converter = atmel_smc_cs_conf_set_setup, .shift = pos}
#define ATMEL_SMC_PULSE_XLATE(nm, pos) \
{ .name = nm, .converter = atmel_smc_cs_conf_set_pulse, .shift = pos}
#define ATMEL_SMC_CYCLE_XLATE(nm, pos) \
{ .name = nm, .converter = atmel_smc_cs_conf_set_cycle, .shift = pos}
static void at91sam9_ebi_get_config(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf)
{
atmel_smc_cs_conf_get(ebid->ebi->smc.regmap, conf->cs,
&conf->smcconf);
}
static void sama5_ebi_get_config(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf)
{
atmel_hsmc_cs_conf_get(ebid->ebi->smc.regmap, ebid->ebi->smc.layout,
conf->cs, &conf->smcconf);
}
static const struct atmel_smc_timing_xlate timings_xlate_table[] = {
ATMEL_SMC_SETUP_XLATE("atmel,smc-ncs-rd-setup-ns",
ATMEL_SMC_NCS_RD_SHIFT),
ATMEL_SMC_SETUP_XLATE("atmel,smc-ncs-wr-setup-ns",
ATMEL_SMC_NCS_WR_SHIFT),
ATMEL_SMC_SETUP_XLATE("atmel,smc-nrd-setup-ns", ATMEL_SMC_NRD_SHIFT),
ATMEL_SMC_SETUP_XLATE("atmel,smc-nwe-setup-ns", ATMEL_SMC_NWE_SHIFT),
ATMEL_SMC_PULSE_XLATE("atmel,smc-ncs-rd-pulse-ns",
ATMEL_SMC_NCS_RD_SHIFT),
ATMEL_SMC_PULSE_XLATE("atmel,smc-ncs-wr-pulse-ns",
ATMEL_SMC_NCS_WR_SHIFT),
ATMEL_SMC_PULSE_XLATE("atmel,smc-nrd-pulse-ns", ATMEL_SMC_NRD_SHIFT),
ATMEL_SMC_PULSE_XLATE("atmel,smc-nwe-pulse-ns", ATMEL_SMC_NWE_SHIFT),
ATMEL_SMC_CYCLE_XLATE("atmel,smc-nrd-cycle-ns", ATMEL_SMC_NRD_SHIFT),
ATMEL_SMC_CYCLE_XLATE("atmel,smc-nwe-cycle-ns", ATMEL_SMC_NWE_SHIFT),
};
static int atmel_ebi_xslate_smc_timings(struct atmel_ebi_dev *ebid,
struct device_node *np,
struct atmel_smc_cs_conf *smcconf)
{
unsigned int clk_rate = clk_get_rate(ebid->ebi->clk);
unsigned int clk_period_ns = NSEC_PER_SEC / clk_rate;
bool required = false;
unsigned int ncycles;
int ret, i;
u32 val;
ret = of_property_read_u32(np, "atmel,smc-tdf-ns", &val);
if (!ret) {
required = true;
ncycles = DIV_ROUND_UP(val, clk_period_ns);
if (ncycles > ATMEL_SMC_MODE_TDF_MAX) {
ret = -EINVAL;
goto out;
}
if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
ncycles = ATMEL_SMC_MODE_TDF_MIN;
smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles);
}
for (i = 0; i < ARRAY_SIZE(timings_xlate_table); i++) {
const struct atmel_smc_timing_xlate *xlate;
xlate = &timings_xlate_table[i];
ret = of_property_read_u32(np, xlate->name, &val);
if (ret) {
if (!required)
continue;
else
break;
}
if (!required) {
ret = -EINVAL;
break;
}
ncycles = DIV_ROUND_UP(val, clk_period_ns);
ret = xlate->converter(smcconf, xlate->shift, ncycles);
if (ret)
goto out;
}
out:
if (ret) {
dev_err(ebid->ebi->dev,
"missing or invalid timings definition in %pOF",
np);
return ret;
}
return required;
}
static int atmel_ebi_xslate_smc_config(struct atmel_ebi_dev *ebid,
struct device_node *np,
struct atmel_ebi_dev_config *conf)
{
struct atmel_smc_cs_conf *smcconf = &conf->smcconf;
bool required = false;
const char *tmp_str;
u32 tmp;
int ret;
ret = of_property_read_u32(np, "atmel,smc-bus-width", &tmp);
if (!ret) {
switch (tmp) {
case 8:
smcconf->mode |= ATMEL_SMC_MODE_DBW_8;
break;
case 16:
smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
break;
case 32:
smcconf->mode |= ATMEL_SMC_MODE_DBW_32;
break;
default:
return -EINVAL;
}
required = true;
}
if (of_property_read_bool(np, "atmel,smc-tdf-optimized")) {
smcconf->mode |= ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
required = true;
}
tmp_str = NULL;
of_property_read_string(np, "atmel,smc-byte-access-type", &tmp_str);
if (tmp_str && !strcmp(tmp_str, "write")) {
smcconf->mode |= ATMEL_SMC_MODE_BAT_WRITE;
required = true;
}
tmp_str = NULL;
of_property_read_string(np, "atmel,smc-read-mode", &tmp_str);
if (tmp_str && !strcmp(tmp_str, "nrd")) {
smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD;
required = true;
}
tmp_str = NULL;
of_property_read_string(np, "atmel,smc-write-mode", &tmp_str);
if (tmp_str && !strcmp(tmp_str, "nwe")) {
smcconf->mode |= ATMEL_SMC_MODE_WRITEMODE_NWE;
required = true;
}
tmp_str = NULL;
of_property_read_string(np, "atmel,smc-exnw-mode", &tmp_str);
if (tmp_str) {
if (!strcmp(tmp_str, "frozen"))
smcconf->mode |= ATMEL_SMC_MODE_EXNWMODE_FROZEN;
else if (!strcmp(tmp_str, "ready"))
smcconf->mode |= ATMEL_SMC_MODE_EXNWMODE_READY;
else if (strcmp(tmp_str, "disabled"))
return -EINVAL;
required = true;
}
ret = of_property_read_u32(np, "atmel,smc-page-mode", &tmp);
if (!ret) {
switch (tmp) {
case 4:
smcconf->mode |= ATMEL_SMC_MODE_PS_4;
break;
case 8:
smcconf->mode |= ATMEL_SMC_MODE_PS_8;
break;
case 16:
smcconf->mode |= ATMEL_SMC_MODE_PS_16;
break;
case 32:
smcconf->mode |= ATMEL_SMC_MODE_PS_32;
break;
default:
return -EINVAL;
}
smcconf->mode |= ATMEL_SMC_MODE_PMEN;
required = true;
}
ret = atmel_ebi_xslate_smc_timings(ebid, np, &conf->smcconf);
if (ret < 0)
return -EINVAL;
if ((ret > 0 && !required) || (!ret && required)) {
dev_err(ebid->ebi->dev, "missing atmel,smc- properties in %pOF",
np);
return -EINVAL;
}
return required;
}
static void at91sam9_ebi_apply_config(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf)
{
atmel_smc_cs_conf_apply(ebid->ebi->smc.regmap, conf->cs,
&conf->smcconf);
}
static void sama5_ebi_apply_config(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf)
{
atmel_hsmc_cs_conf_apply(ebid->ebi->smc.regmap, ebid->ebi->smc.layout,
conf->cs, &conf->smcconf);
}
static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np,
int reg_cells)
{
const struct atmel_ebi_caps *caps = ebi->caps;
struct atmel_ebi_dev_config conf = { };
struct device *dev = ebi->dev;
struct atmel_ebi_dev *ebid;
unsigned long cslines = 0;
int ret, numcs = 0, nentries, i;
bool apply = false;
u32 cs;
nentries = of_property_count_elems_of_size(np, "reg",
reg_cells * sizeof(u32));
for (i = 0; i < nentries; i++) {
ret = of_property_read_u32_index(np, "reg", i * reg_cells,
&cs);
if (ret)
return ret;
if (cs >= AT91_EBI_NUM_CS ||
!(ebi->caps->available_cs & BIT(cs))) {
dev_err(dev, "invalid reg property in %pOF\n", np);
return -EINVAL;
}
if (!test_and_set_bit(cs, &cslines))
numcs++;
}
if (!numcs) {
dev_err(dev, "invalid reg property in %pOF\n", np);
return -EINVAL;
}
ebid = devm_kzalloc(ebi->dev, struct_size(ebid, configs, numcs),
GFP_KERNEL);
if (!ebid)
return -ENOMEM;
ebid->ebi = ebi;
ebid->numcs = numcs;
ret = caps->xlate_config(ebid, np, &conf);
if (ret < 0)
return ret;
else if (ret)
apply = true;
i = 0;
for_each_set_bit(cs, &cslines, AT91_EBI_NUM_CS) {
ebid->configs[i].cs = cs;
if (apply) {
conf.cs = cs;
caps->apply_config(ebid, &conf);
}
caps->get_config(ebid, &ebid->configs[i]);
/*
* Attach the EBI device to the generic SMC logic if at least
* one "atmel,smc-" property is present.
*/
if (ebi->caps->ebi_csa_offs && apply)
regmap_update_bits(ebi->regmap,
ebi->caps->ebi_csa_offs,
BIT(cs), 0);
i++;
}
list_add_tail(&ebid->node, &ebi->devs);
return 0;
}
static const struct atmel_ebi_caps at91sam9260_ebi_caps = {
.available_cs = 0xff,
.ebi_csa_offs = AT91SAM9260_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9261_ebi_caps = {
.available_cs = 0xff,
.ebi_csa_offs = AT91SAM9261_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9263_ebi0_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI0CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9263_ebi1_caps = {
.available_cs = 0x7,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI1CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9rl_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9RL_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9g45_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9G45_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps at91sam9x5_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9X5_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct atmel_ebi_caps sama5d3_ebi_caps = {
.available_cs = 0xf,
.get_config = sama5_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = sama5_ebi_apply_config,
};
static const struct atmel_ebi_caps sam9x60_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91_SFR_CCFG_EBICSA,
.regmap_name = "microchip,sfr",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct of_device_id atmel_ebi_id_table[] = {
{
.compatible = "atmel,at91sam9260-ebi",
.data = &at91sam9260_ebi_caps,
},
{
.compatible = "atmel,at91sam9261-ebi",
.data = &at91sam9261_ebi_caps,
},
{
.compatible = "atmel,at91sam9263-ebi0",
.data = &at91sam9263_ebi0_caps,
},
{
.compatible = "atmel,at91sam9263-ebi1",
.data = &at91sam9263_ebi1_caps,
},
{
.compatible = "atmel,at91sam9rl-ebi",
.data = &at91sam9rl_ebi_caps,
},
{
.compatible = "atmel,at91sam9g45-ebi",
.data = &at91sam9g45_ebi_caps,
},
{
.compatible = "atmel,at91sam9x5-ebi",
.data = &at91sam9x5_ebi_caps,
},
{
.compatible = "atmel,sama5d3-ebi",
.data = &sama5d3_ebi_caps,
},
{
.compatible = "microchip,sam9x60-ebi",
.data = &sam9x60_ebi_caps,
},
{ /* sentinel */ }
};
static int atmel_ebi_dev_disable(struct atmel_ebi *ebi, struct device_node *np)
{
struct device *dev = ebi->dev;
struct property *newprop;
newprop = devm_kzalloc(dev, sizeof(*newprop), GFP_KERNEL);
if (!newprop)
return -ENOMEM;
newprop->name = devm_kstrdup(dev, "status", GFP_KERNEL);
if (!newprop->name)
return -ENOMEM;
newprop->value = devm_kstrdup(dev, "disabled", GFP_KERNEL);
if (!newprop->value)
return -ENOMEM;
newprop->length = sizeof("disabled");
return of_update_property(np, newprop);
}
static int atmel_ebi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node, *smc_np;
const struct of_device_id *match;
struct atmel_ebi *ebi;
int ret, reg_cells;
struct clk *clk;
u32 val;
match = of_match_device(atmel_ebi_id_table, dev);
if (!match || !match->data)
return -EINVAL;
ebi = devm_kzalloc(dev, sizeof(*ebi), GFP_KERNEL);
if (!ebi)
return -ENOMEM;
platform_set_drvdata(pdev, ebi);
INIT_LIST_HEAD(&ebi->devs);
ebi->caps = match->data;
ebi->dev = dev;
clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
ebi->clk = clk;
smc_np = of_parse_phandle(dev->of_node, "atmel,smc", 0);
ebi->smc.regmap = syscon_node_to_regmap(smc_np);
if (IS_ERR(ebi->smc.regmap)) {
ret = PTR_ERR(ebi->smc.regmap);
goto put_node;
}
ebi->smc.layout = atmel_hsmc_get_reg_layout(smc_np);
if (IS_ERR(ebi->smc.layout)) {
ret = PTR_ERR(ebi->smc.layout);
goto put_node;
}
ebi->smc.clk = of_clk_get(smc_np, 0);
if (IS_ERR(ebi->smc.clk)) {
if (PTR_ERR(ebi->smc.clk) != -ENOENT) {
ret = PTR_ERR(ebi->smc.clk);
goto put_node;
}
ebi->smc.clk = NULL;
}
of_node_put(smc_np);
ret = clk_prepare_enable(ebi->smc.clk);
if (ret)
return ret;
/*
* The sama5d3 does not provide an EBICSA register and thus does need
* to access it.
*/
if (ebi->caps->ebi_csa_offs) {
ebi->regmap =
syscon_regmap_lookup_by_phandle(np,
ebi->caps->regmap_name);
if (IS_ERR(ebi->regmap))
return PTR_ERR(ebi->regmap);
}
ret = of_property_read_u32(np, "#address-cells", &val);
if (ret) {
dev_err(dev, "missing #address-cells property\n");
return ret;
}
reg_cells = val;
ret = of_property_read_u32(np, "#size-cells", &val);
if (ret) {
dev_err(dev, "missing #address-cells property\n");
return ret;
}
reg_cells += val;
for_each_available_child_of_node(np, child) {
if (!of_property_present(child, "reg"))
continue;
ret = atmel_ebi_dev_setup(ebi, child, reg_cells);
if (ret) {
dev_err(dev, "failed to configure EBI bus for %pOF, disabling the device",
child);
ret = atmel_ebi_dev_disable(ebi, child);
if (ret) {
of_node_put(child);
return ret;
}
}
}
return of_platform_populate(np, NULL, NULL, dev);
put_node:
of_node_put(smc_np);
return ret;
}
static __maybe_unused int atmel_ebi_resume(struct device *dev)
{
struct atmel_ebi *ebi = dev_get_drvdata(dev);
struct atmel_ebi_dev *ebid;
list_for_each_entry(ebid, &ebi->devs, node) {
int i;
for (i = 0; i < ebid->numcs; i++)
ebid->ebi->caps->apply_config(ebid, &ebid->configs[i]);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(atmel_ebi_pm_ops, NULL, atmel_ebi_resume);
static struct platform_driver atmel_ebi_driver = {
.driver = {
.name = "atmel-ebi",
.of_match_table = atmel_ebi_id_table,
.pm = &atmel_ebi_pm_ops,
},
};
builtin_platform_driver_probe(atmel_ebi_driver, atmel_ebi_probe);
|
linux-master
|
drivers/memory/atmel-ebi.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* DDR Self-Refresh Power Down (SRPD) support for Broadcom STB SoCs
*
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#define REG_MEMC_CNTRLR_CONFIG 0x00
#define CNTRLR_CONFIG_LPDDR4_SHIFT 5
#define CNTRLR_CONFIG_MASK 0xf
#define REG_MEMC_SRPD_CFG_21 0x20
#define REG_MEMC_SRPD_CFG_20 0x34
#define REG_MEMC_SRPD_CFG_1x 0x3c
#define INACT_COUNT_SHIFT 0
#define INACT_COUNT_MASK 0xffff
#define SRPD_EN_SHIFT 16
struct brcmstb_memc_data {
u32 srpd_offset;
};
struct brcmstb_memc {
struct device *dev;
void __iomem *ddr_ctrl;
unsigned int timeout_cycles;
u32 frequency;
u32 srpd_offset;
};
static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc)
{
void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG;
u32 reg;
reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK;
return reg == CNTRLR_CONFIG_LPDDR4_SHIFT;
}
static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
unsigned int cycles)
{
void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
u32 val;
/* Max timeout supported in HW */
if (cycles > INACT_COUNT_MASK)
return -EINVAL;
memc->timeout_cycles = cycles;
val = (cycles << INACT_COUNT_SHIFT) & INACT_COUNT_MASK;
if (cycles)
val |= BIT(SRPD_EN_SHIFT);
writel_relaxed(val, cfg);
/* Ensure the write is committed to the controller */
(void)readl_relaxed(cfg);
return 0;
}
static ssize_t frequency_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct brcmstb_memc *memc = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", memc->frequency);
}
static ssize_t srpd_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct brcmstb_memc *memc = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", memc->timeout_cycles);
}
static ssize_t srpd_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct brcmstb_memc *memc = dev_get_drvdata(dev);
unsigned int val;
int ret;
/*
* Cannot change the inactivity timeout on LPDDR4 chips because the
* dynamic tuning process will also get affected by the inactivity
* timeout, thus making it non functional.
*/
if (brcmstb_memc_uses_lpddr4(memc))
return -EOPNOTSUPP;
ret = kstrtouint(buf, 10, &val);
if (ret < 0)
return ret;
ret = brcmstb_memc_srpd_config(memc, val);
if (ret)
return ret;
return count;
}
static DEVICE_ATTR_RO(frequency);
static DEVICE_ATTR_RW(srpd);
static struct attribute *dev_attrs[] = {
&dev_attr_frequency.attr,
&dev_attr_srpd.attr,
NULL,
};
static struct attribute_group dev_attr_group = {
.attrs = dev_attrs,
};
static const struct of_device_id brcmstb_memc_of_match[];
static int brcmstb_memc_probe(struct platform_device *pdev)
{
const struct brcmstb_memc_data *memc_data;
const struct of_device_id *of_id;
struct device *dev = &pdev->dev;
struct brcmstb_memc *memc;
int ret;
memc = devm_kzalloc(dev, sizeof(*memc), GFP_KERNEL);
if (!memc)
return -ENOMEM;
dev_set_drvdata(dev, memc);
of_id = of_match_device(brcmstb_memc_of_match, dev);
memc_data = of_id->data;
memc->srpd_offset = memc_data->srpd_offset;
memc->ddr_ctrl = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(memc->ddr_ctrl))
return PTR_ERR(memc->ddr_ctrl);
of_property_read_u32(pdev->dev.of_node, "clock-frequency",
&memc->frequency);
ret = sysfs_create_group(&dev->kobj, &dev_attr_group);
if (ret)
return ret;
return 0;
}
static int brcmstb_memc_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
sysfs_remove_group(&dev->kobj, &dev_attr_group);
return 0;
}
enum brcmstb_memc_hwtype {
BRCMSTB_MEMC_V21,
BRCMSTB_MEMC_V20,
BRCMSTB_MEMC_V1X,
};
static const struct brcmstb_memc_data brcmstb_memc_versions[] = {
{ .srpd_offset = REG_MEMC_SRPD_CFG_21 },
{ .srpd_offset = REG_MEMC_SRPD_CFG_20 },
{ .srpd_offset = REG_MEMC_SRPD_CFG_1x },
};
static const struct of_device_id brcmstb_memc_of_match[] = {
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.1.x",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.0",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V20]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.0",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.2",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.3",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.4",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
/* default to the original offset */
{
.compatible = "brcm,brcmstb-memc-ddr",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
},
{}
};
static int brcmstb_memc_suspend(struct device *dev)
{
struct brcmstb_memc *memc = dev_get_drvdata(dev);
void __iomem *cfg = memc->ddr_ctrl + memc->srpd_offset;
u32 val;
if (memc->timeout_cycles == 0)
return 0;
/*
* Disable SRPD prior to suspending the system since that can
* cause issues with other memory clients managed by the ARM
* trusted firmware to access memory.
*/
val = readl_relaxed(cfg);
val &= ~BIT(SRPD_EN_SHIFT);
writel_relaxed(val, cfg);
/* Ensure the write is committed to the controller */
(void)readl_relaxed(cfg);
return 0;
}
static int brcmstb_memc_resume(struct device *dev)
{
struct brcmstb_memc *memc = dev_get_drvdata(dev);
if (memc->timeout_cycles == 0)
return 0;
return brcmstb_memc_srpd_config(memc, memc->timeout_cycles);
}
static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_memc_pm_ops, brcmstb_memc_suspend,
brcmstb_memc_resume);
static struct platform_driver brcmstb_memc_driver = {
.probe = brcmstb_memc_probe,
.remove = brcmstb_memc_remove,
.driver = {
.name = "brcmstb_memc",
.of_match_table = brcmstb_memc_of_match,
.pm = pm_ptr(&brcmstb_memc_pm_ops),
},
};
module_platform_driver(brcmstb_memc_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("DDR SRPD driver for Broadcom STB chips");
|
linux-master
|
drivers/memory/brcmstb_memc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPMC support functions
*
* Copyright (C) 2005-2006 Nokia Corporation
*
* Author: Juha Yrjola
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <[email protected]>
*/
#include <linux/cpu_pm.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/ioport.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h> /* GPIO descriptor enum */
#include <linux/gpio/machine.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/omap-gpmc.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
#include <linux/platform_data/mtd-nand-omap2.h>
#define DEVICE_NAME "omap-gpmc"
/* GPMC register offsets */
#define GPMC_REVISION 0x00
#define GPMC_SYSCONFIG 0x10
#define GPMC_SYSSTATUS 0x14
#define GPMC_IRQSTATUS 0x18
#define GPMC_IRQENABLE 0x1c
#define GPMC_TIMEOUT_CONTROL 0x40
#define GPMC_ERR_ADDRESS 0x44
#define GPMC_ERR_TYPE 0x48
#define GPMC_CONFIG 0x50
#define GPMC_STATUS 0x54
#define GPMC_PREFETCH_CONFIG1 0x1e0
#define GPMC_PREFETCH_CONFIG2 0x1e4
#define GPMC_PREFETCH_CONTROL 0x1ec
#define GPMC_PREFETCH_STATUS 0x1f0
#define GPMC_ECC_CONFIG 0x1f4
#define GPMC_ECC_CONTROL 0x1f8
#define GPMC_ECC_SIZE_CONFIG 0x1fc
#define GPMC_ECC1_RESULT 0x200
#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
/* GPMC ECC control settings */
#define GPMC_ECC_CTRL_ECCCLEAR 0x100
#define GPMC_ECC_CTRL_ECCDISABLE 0x000
#define GPMC_ECC_CTRL_ECCREG1 0x001
#define GPMC_ECC_CTRL_ECCREG2 0x002
#define GPMC_ECC_CTRL_ECCREG3 0x003
#define GPMC_ECC_CTRL_ECCREG4 0x004
#define GPMC_ECC_CTRL_ECCREG5 0x005
#define GPMC_ECC_CTRL_ECCREG6 0x006
#define GPMC_ECC_CTRL_ECCREG7 0x007
#define GPMC_ECC_CTRL_ECCREG8 0x008
#define GPMC_ECC_CTRL_ECCREG9 0x009
#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
#define GPMC_CS0_OFFSET 0x60
#define GPMC_CS_SIZE 0x30
#define GPMC_BCH_SIZE 0x10
/*
* The first 1MB of GPMC address space is typically mapped to
* the internal ROM. Never allocate the first page, to
* facilitate bug detection; even if we didn't boot from ROM.
* As GPMC minimum partition size is 16MB we can only start from
* there.
*/
#define GPMC_MEM_START 0x1000000
#define GPMC_MEM_END 0x3FFFFFFF
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
#define GPMC_SECTION_SHIFT 28 /* 128 MB */
#define CS_NUM_SHIFT 24
#define ENABLE_PREFETCH (0x1 << 7)
#define DMA_MPU_MODE 2
#define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
#define GPMC_REVISION_MINOR(l) ((l) & 0xf)
#define GPMC_HAS_WR_ACCESS 0x1
#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
#define GPMC_HAS_MUX_AAD 0x4
#define GPMC_NR_WAITPINS 4
#define GPMC_CS_CONFIG1 0x00
#define GPMC_CS_CONFIG2 0x04
#define GPMC_CS_CONFIG3 0x08
#define GPMC_CS_CONFIG4 0x0c
#define GPMC_CS_CONFIG5 0x10
#define GPMC_CS_CONFIG6 0x14
#define GPMC_CS_CONFIG7 0x18
#define GPMC_CS_NAND_COMMAND 0x1c
#define GPMC_CS_NAND_ADDRESS 0x20
#define GPMC_CS_NAND_DATA 0x24
/* Control Commands */
#define GPMC_CONFIG_RDY_BSY 0x00000001
#define GPMC_CONFIG_DEV_SIZE 0x00000002
#define GPMC_CONFIG_DEV_TYPE 0x00000003
#define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8)
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
/** CLKACTIVATIONTIME Max Ticks */
#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
#define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
/** ATTACHEDDEVICEPAGELENGTH Max Value */
#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
#define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
/** WAITMONITORINGTIME Max Ticks */
#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
#define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
#define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
/** DEVICESIZE Max Value */
#define GPMC_CONFIG1_DEVICESIZE_MAX 1
#define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
#define GPMC_CONFIG7_CSVALID (1 << 6)
#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
/* All CONFIG7 bits except reserved bits */
#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
GPMC_CONFIG7_CSVALID_MASK | \
GPMC_CONFIG7_MASKADDRESS_MASK)
#define GPMC_DEVICETYPE_NOR 0
#define GPMC_DEVICETYPE_NAND 2
#define GPMC_CONFIG_WRITEPROTECT 0x00000010
#define WR_RD_PIN_MONITORING 0x00600000
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
#define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
enum gpmc_clk_domain {
GPMC_CD_FCLK,
GPMC_CD_CLK
};
struct gpmc_cs_data {
const char *name;
#define GPMC_CS_RESERVED (1 << 0)
u32 flags;
struct resource mem;
};
/* Structure to save gpmc cs context */
struct gpmc_cs_config {
u32 config1;
u32 config2;
u32 config3;
u32 config4;
u32 config5;
u32 config6;
u32 config7;
int is_valid;
};
/*
* Structure to save/restore gpmc context
* to support core off on OMAP3
*/
struct omap3_gpmc_regs {
u32 sysconfig;
u32 irqenable;
u32 timeout_ctrl;
u32 config;
u32 prefetch_config1;
u32 prefetch_config2;
u32 prefetch_control;
struct gpmc_cs_config cs_context[GPMC_CS_NUM];
};
struct gpmc_waitpin {
u32 pin;
u32 polarity;
struct gpio_desc *desc;
};
struct gpmc_device {
struct device *dev;
int irq;
struct irq_chip irq_chip;
struct gpio_chip gpio_chip;
struct notifier_block nb;
struct omap3_gpmc_regs context;
struct gpmc_waitpin *waitpins;
int nirqs;
unsigned int is_suspended:1;
struct resource *data;
};
static struct irq_domain *gpmc_irq_domain;
static struct resource gpmc_mem_root;
static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
/* Define chip-selects as reserved by default until probe completes */
static unsigned int gpmc_cs_num = GPMC_CS_NUM;
static unsigned int gpmc_nr_waitpins;
static unsigned int gpmc_capability;
static void __iomem *gpmc_base;
static struct clk *gpmc_l3_clk;
static irqreturn_t gpmc_handle_irq(int irq, void *dev);
static void gpmc_write_reg(int idx, u32 val)
{
writel_relaxed(val, gpmc_base + idx);
}
static u32 gpmc_read_reg(int idx)
{
return readl_relaxed(gpmc_base + idx);
}
void gpmc_cs_write_reg(int cs, int idx, u32 val)
{
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
writel_relaxed(val, reg_addr);
}
static u32 gpmc_cs_read_reg(int cs, int idx)
{
void __iomem *reg_addr;
reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
return readl_relaxed(reg_addr);
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
static unsigned long gpmc_get_fclk_period(void)
{
unsigned long rate = clk_get_rate(gpmc_l3_clk);
rate /= 1000;
rate = 1000000000 / rate; /* In picoseconds */
return rate;
}
/**
* gpmc_get_clk_period - get period of selected clock domain in ps
* @cs: Chip Select Region.
* @cd: Clock Domain.
*
* GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
* prior to calling this function with GPMC_CD_CLK.
*/
static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
{
unsigned long tick_ps = gpmc_get_fclk_period();
u32 l;
int div;
switch (cd) {
case GPMC_CD_CLK:
/* get current clk divider */
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
div = (l & 0x03) + 1;
/* get GPMC_CLK period */
tick_ps *= div;
break;
case GPMC_CD_FCLK:
default:
break;
}
return tick_ps;
}
static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
enum gpmc_clk_domain cd)
{
unsigned long tick_ps;
/* Calculate in picosecs to yield more exact results */
tick_ps = gpmc_get_clk_period(cs, cd);
return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}
static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
}
static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
{
unsigned long tick_ps;
/* Calculate in picosecs to yield more exact results */
tick_ps = gpmc_get_fclk_period();
return (time_ps + tick_ps - 1) / tick_ps;
}
static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
enum gpmc_clk_domain cd)
{
return ticks * gpmc_get_clk_period(cs, cd) / 1000;
}
unsigned int gpmc_ticks_to_ns(unsigned int ticks)
{
return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
}
static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
{
return ticks * gpmc_get_fclk_period();
}
static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
{
unsigned long ticks = gpmc_ps_to_ticks(time_ps);
return ticks * gpmc_get_fclk_period();
}
static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
{
u32 l;
l = gpmc_cs_read_reg(cs, reg);
if (value)
l |= mask;
else
l &= ~mask;
gpmc_cs_write_reg(cs, reg, l);
}
static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
{
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
GPMC_CONFIG1_TIME_PARA_GRAN,
p->time_para_granularity);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
p->cycle2cyclesamecsen);
gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
p->cycle2cyclediffcsen);
}
#ifdef CONFIG_OMAP_GPMC_DEBUG
/**
* get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
* @cs: Chip Select Region
* @reg: GPMC_CS_CONFIGn register offset.
* @st_bit: Start Bit
* @end_bit: End Bit. Must be >= @st_bit.
* @max: Maximum parameter value (before optional @shift).
* If 0, maximum is as high as @st_bit and @end_bit allow.
* @name: DTS node name, w/o "gpmc,"
* @cd: Clock Domain of timing parameter.
* @shift: Parameter value left shifts @shift, which is then printed instead of value.
* @raw: Raw Format Option.
* raw format: gpmc,name = <value>
* tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
* Where x ns -- y ns result in the same tick value.
* When @max is exceeded, "invalid" is printed inside comment.
* @noval: Parameter values equal to 0 are not printed.
* @return: Specified timing parameter (after optional @shift).
*
*/
static int get_gpmc_timing_reg(
/* timing specifiers */
int cs, int reg, int st_bit, int end_bit, int max,
const char *name, const enum gpmc_clk_domain cd,
/* value transform */
int shift,
/* format specifiers */
bool raw, bool noval)
{
u32 l;
int nr_bits;
int mask;
bool invalid;
l = gpmc_cs_read_reg(cs, reg);
nr_bits = end_bit - st_bit + 1;
mask = (1 << nr_bits) - 1;
l = (l >> st_bit) & mask;
if (!max)
max = mask;
invalid = l > max;
if (shift)
l = (shift << l);
if (noval && (l == 0))
return 0;
if (!raw) {
/* DTS tick format for timings in ns */
unsigned int time_ns;
unsigned int time_ns_min = 0;
if (l)
time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
name, time_ns, time_ns_min, time_ns, l,
invalid ? "; invalid " : " ");
} else {
/* raw format */
pr_info("gpmc,%s = <%u>;%s\n", name, l,
invalid ? " /* invalid */" : "");
}
return l;
}
#define GPMC_PRINT_CONFIG(cs, config) \
pr_info("cs%i %s: 0x%08x\n", cs, #config, \
gpmc_cs_read_reg(cs, config))
#define GPMC_GET_RAW(reg, st, end, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
#define GPMC_GET_TICKS(reg, st, end, field) \
get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
static void gpmc_show_regs(int cs, const char *desc)
{
pr_info("gpmc cs%i %s:\n", cs, desc);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
}
/*
* Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
* see commit c9fb809.
*/
static void gpmc_cs_show_timings(int cs, const char *desc)
{
gpmc_show_regs(cs, desc);
pr_info("gpmc cs%i access configuration:\n", cs);
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
"burst-length");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
pr_info("gpmc cs%i timings configuration:\n", cs);
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
if (gpmc_capability & GPMC_HAS_MUX_AAD) {
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
"adv-aad-mux-rd-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
"adv-aad-mux-wr-off-ns");
}
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
if (gpmc_capability & GPMC_HAS_MUX_AAD) {
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
}
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
"wait-monitoring-ns", GPMC_CD_CLK);
GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
"clk-activation-ns", GPMC_CD_FCLK);
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
}
#else
static inline void gpmc_cs_show_timings(int cs, const char *desc)
{
}
#endif
/**
* set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
* Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
* prior to calling this function with @cd equal to GPMC_CD_CLK.
*
* @cs: Chip Select Region.
* @reg: GPMC_CS_CONFIGn register offset.
* @st_bit: Start Bit
* @end_bit: End Bit. Must be >= @st_bit.
* @max: Maximum parameter value.
* If 0, maximum is as high as @st_bit and @end_bit allow.
* @time: Timing parameter in ns.
* @cd: Timing parameter clock domain.
* @name: Timing parameter name.
* @return: 0 on success, -1 on error.
*/
static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
int time, enum gpmc_clk_domain cd, const char *name)
{
u32 l;
int ticks, mask, nr_bits;
if (time == 0)
ticks = 0;
else
ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
nr_bits = end_bit - st_bit + 1;
mask = (1 << nr_bits) - 1;
if (!max)
max = mask;
if (ticks > max) {
pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
__func__, cs, name, time, ticks, max);
return -1;
}
l = gpmc_cs_read_reg(cs, reg);
#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
(l >> st_bit) & mask, time);
#endif
l &= ~(mask << st_bit);
l |= ticks << st_bit;
gpmc_cs_write_reg(cs, reg, l);
return 0;
}
/**
* gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
* WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
* read --> don't sample bus too early
* write --> data is longer on bus
*
* Formula:
* gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
* / waitmonitoring_ticks)
* WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
* div <= 0 check.
*
* @wait_monitoring: WAITMONITORINGTIME in ns.
* @return: -1 on failure to scale, else proper divider > 0.
*/
static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
{
int div = gpmc_ns_to_ticks(wait_monitoring);
div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
if (div > 4)
return -1;
if (div <= 0)
div = 1;
return div;
}
/**
* gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
* @sync_clk: GPMC_CLK period in ps.
* @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
* Else, returns -1.
*/
int gpmc_calc_divider(unsigned int sync_clk)
{
int div = gpmc_ps_to_ticks(sync_clk);
if (div > 4)
return -1;
if (div <= 0)
div = 1;
return div;
}
/**
* gpmc_cs_set_timings - program timing parameters for Chip Select Region.
* @cs: Chip Select Region.
* @t: GPMC timing parameters.
* @s: GPMC timing settings.
* @return: 0 on success, -1 on error.
*/
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
const struct gpmc_settings *s)
{
int div, ret;
u32 l;
div = gpmc_calc_divider(t->sync_clk);
if (div < 0)
return -EINVAL;
/*
* See if we need to change the divider for waitmonitoringtime.
*
* Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
* pure asynchronous accesses, i.e. both read and write asynchronous.
* However, only do so if WAITMONITORINGTIME is actually used, i.e.
* either WAITREADMONITORING or WAITWRITEMONITORING is set.
*
* This statement must not change div to scale async WAITMONITORINGTIME
* to protect mixed synchronous and asynchronous accesses.
*
* We raise an error later if WAITMONITORINGTIME does not fit.
*/
if (!s->sync_read && !s->sync_write &&
(s->wait_on_read || s->wait_on_write)
) {
div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
if (div < 0) {
pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
__func__,
t->wait_monitoring
);
return -ENXIO;
}
}
ret = 0;
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
GPMC_CD_FCLK, "cs_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
GPMC_CD_FCLK, "cs_rd_off");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
GPMC_CD_FCLK, "cs_wr_off");
if (ret)
return -ENXIO;
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
GPMC_CD_FCLK, "adv_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
GPMC_CD_FCLK, "adv_rd_off");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
GPMC_CD_FCLK, "adv_wr_off");
if (ret)
return -ENXIO;
if (gpmc_capability & GPMC_HAS_MUX_AAD) {
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
t->adv_aad_mux_on, GPMC_CD_FCLK,
"adv_aad_mux_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
"adv_aad_mux_rd_off");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
"adv_aad_mux_wr_off");
if (ret)
return -ENXIO;
}
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
GPMC_CD_FCLK, "oe_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
GPMC_CD_FCLK, "oe_off");
if (gpmc_capability & GPMC_HAS_MUX_AAD) {
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
t->oe_aad_mux_on, GPMC_CD_FCLK,
"oe_aad_mux_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
t->oe_aad_mux_off, GPMC_CD_FCLK,
"oe_aad_mux_off");
}
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
GPMC_CD_FCLK, "we_on");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
GPMC_CD_FCLK, "we_off");
if (ret)
return -ENXIO;
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
GPMC_CD_FCLK, "rd_cycle");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
GPMC_CD_FCLK, "wr_cycle");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
GPMC_CD_FCLK, "access");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
t->page_burst_access, GPMC_CD_FCLK,
"page_burst_access");
if (ret)
return -ENXIO;
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
t->bus_turnaround, GPMC_CD_FCLK,
"bus_turnaround");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
t->cycle2cycle_delay, GPMC_CD_FCLK,
"cycle2cycle_delay");
if (ret)
return -ENXIO;
if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
t->wr_data_mux_bus, GPMC_CD_FCLK,
"wr_data_mux_bus");
if (ret)
return -ENXIO;
}
if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
t->wr_access, GPMC_CD_FCLK,
"wr_access");
if (ret)
return -ENXIO;
}
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
l &= ~0x03;
l |= (div - 1);
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
ret = 0;
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
t->wait_monitoring, GPMC_CD_CLK,
"wait_monitoring");
ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
t->clk_activation, GPMC_CD_FCLK,
"clk_activation");
if (ret)
return -ENXIO;
#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
gpmc_cs_bool_timings(cs, &t->bool_timings);
gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
return 0;
}
static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
{
u32 l;
u32 mask;
/*
* Ensure that base address is aligned on a
* boundary equal to or greater than size.
*/
if (base & (size - 1))
return -EINVAL;
base >>= GPMC_CHUNK_SHIFT;
mask = (1 << GPMC_SECTION_SHIFT) - size;
mask >>= GPMC_CHUNK_SHIFT;
mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
l &= ~GPMC_CONFIG7_MASK;
l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
l |= GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
return 0;
}
static void gpmc_cs_enable_mem(int cs)
{
u32 l;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
l |= GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}
static void gpmc_cs_disable_mem(int cs)
{
u32 l;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
l &= ~GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
}
static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
{
u32 l;
u32 mask;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
mask = (l >> 8) & 0x0f;
*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
}
static int gpmc_cs_mem_enabled(int cs)
{
u32 l;
l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
return l & GPMC_CONFIG7_CSVALID;
}
static void gpmc_cs_set_reserved(int cs, int reserved)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
gpmc->flags |= GPMC_CS_RESERVED;
}
static bool gpmc_cs_reserved(int cs)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
return gpmc->flags & GPMC_CS_RESERVED;
}
static unsigned long gpmc_mem_align(unsigned long size)
{
int order;
size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
order = GPMC_CHUNK_SHIFT - 1;
do {
size >>= 1;
order++;
} while (size);
size = 1 << order;
return size;
}
static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
struct resource *res = &gpmc->mem;
int r;
size = gpmc_mem_align(size);
spin_lock(&gpmc_mem_lock);
res->start = base;
res->end = base + size - 1;
r = request_resource(&gpmc_mem_root, res);
spin_unlock(&gpmc_mem_lock);
return r;
}
static int gpmc_cs_delete_mem(int cs)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
struct resource *res = &gpmc->mem;
int r;
spin_lock(&gpmc_mem_lock);
r = release_resource(res);
res->start = 0;
res->end = 0;
spin_unlock(&gpmc_mem_lock);
return r;
}
int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
struct resource *res = &gpmc->mem;
int r = -1;
if (cs >= gpmc_cs_num) {
pr_err("%s: requested chip-select is disabled\n", __func__);
return -ENODEV;
}
size = gpmc_mem_align(size);
if (size > (1 << GPMC_SECTION_SHIFT))
return -ENOMEM;
spin_lock(&gpmc_mem_lock);
if (gpmc_cs_reserved(cs)) {
r = -EBUSY;
goto out;
}
if (gpmc_cs_mem_enabled(cs))
r = adjust_resource(res, res->start & ~(size - 1), size);
if (r < 0)
r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
size, NULL, NULL);
if (r < 0)
goto out;
/* Disable CS while changing base address and size mask */
gpmc_cs_disable_mem(cs);
r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
if (r < 0) {
release_resource(res);
goto out;
}
/* Enable CS */
gpmc_cs_enable_mem(cs);
*base = res->start;
gpmc_cs_set_reserved(cs, 1);
out:
spin_unlock(&gpmc_mem_lock);
return r;
}
EXPORT_SYMBOL(gpmc_cs_request);
void gpmc_cs_free(int cs)
{
struct gpmc_cs_data *gpmc;
struct resource *res;
spin_lock(&gpmc_mem_lock);
if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
spin_unlock(&gpmc_mem_lock);
return;
}
gpmc = &gpmc_cs[cs];
res = &gpmc->mem;
gpmc_cs_disable_mem(cs);
if (res->flags)
release_resource(res);
gpmc_cs_set_reserved(cs, 0);
spin_unlock(&gpmc_mem_lock);
}
EXPORT_SYMBOL(gpmc_cs_free);
static bool gpmc_is_valid_waitpin(u32 waitpin)
{
return waitpin < gpmc_nr_waitpins;
}
static int gpmc_alloc_waitpin(struct gpmc_device *gpmc,
struct gpmc_settings *p)
{
int ret;
struct gpmc_waitpin *waitpin;
struct gpio_desc *waitpin_desc;
if (!gpmc_is_valid_waitpin(p->wait_pin))
return -EINVAL;
waitpin = &gpmc->waitpins[p->wait_pin];
if (!waitpin->desc) {
/* Reserve the GPIO for wait pin usage.
* GPIO polarity doesn't matter here. Wait pin polarity
* is set in GPMC_CONFIG register.
*/
waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
p->wait_pin, "WAITPIN",
GPIO_ACTIVE_HIGH,
GPIOD_IN);
ret = PTR_ERR(waitpin_desc);
if (IS_ERR(waitpin_desc) && ret != -EBUSY)
return ret;
/* New wait pin */
waitpin->desc = waitpin_desc;
waitpin->pin = p->wait_pin;
waitpin->polarity = p->wait_pin_polarity;
} else {
/* Shared wait pin */
if (p->wait_pin_polarity != waitpin->polarity ||
p->wait_pin != waitpin->pin) {
dev_err(gpmc->dev,
"shared-wait-pin: invalid configuration\n");
return -EINVAL;
}
dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin);
}
return 0;
}
static void gpmc_free_waitpin(struct gpmc_device *gpmc,
int wait_pin)
{
if (gpmc_is_valid_waitpin(wait_pin))
gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc);
}
/**
* gpmc_configure - write request to configure gpmc
* @cmd: command type
* @wval: value to write
* @return status of the operation
*/
int gpmc_configure(int cmd, int wval)
{
u32 regval;
switch (cmd) {
case GPMC_CONFIG_WP:
regval = gpmc_read_reg(GPMC_CONFIG);
if (wval)
regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
else
regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
gpmc_write_reg(GPMC_CONFIG, regval);
break;
default:
pr_err("%s: command not supported\n", __func__);
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL(gpmc_configure);
static bool gpmc_nand_writebuffer_empty(void)
{
if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
return true;
return false;
}
static struct gpmc_nand_ops nand_ops = {
.nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
};
/**
* gpmc_omap_get_nand_ops - Get the GPMC NAND interface
* @reg: the GPMC NAND register map exclusive for NAND use.
* @cs: GPMC chip select number on which the NAND sits. The
* register map returned will be specific to this chip select.
*
* Returns NULL on error e.g. invalid cs.
*/
struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
{
int i;
if (cs >= gpmc_cs_num)
return NULL;
reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
GPMC_BCH_SIZE * i;
reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
GPMC_BCH_SIZE * i;
reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
GPMC_BCH_SIZE * i;
reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
GPMC_BCH_SIZE * i;
reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
i * GPMC_BCH_SIZE;
reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
i * GPMC_BCH_SIZE;
reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
i * GPMC_BCH_SIZE;
}
return &nand_ops;
}
EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
struct gpmc_settings *s,
int freq, int latency)
{
struct gpmc_device_timings dev_t;
const int t_cer = 15;
const int t_avdp = 12;
const int t_cez = 20; /* max of t_cez, t_oez */
const int t_wpl = 40;
const int t_wph = 30;
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
switch (freq) {
case 104:
min_gpmc_clk_period = 9600; /* 104 MHz */
t_ces = 3;
t_avds = 4;
t_avdh = 2;
t_ach = 3;
t_aavdh = 6;
t_rdyo = 6;
break;
case 83:
min_gpmc_clk_period = 12000; /* 83 MHz */
t_ces = 5;
t_avds = 4;
t_avdh = 2;
t_ach = 6;
t_aavdh = 6;
t_rdyo = 9;
break;
case 66:
min_gpmc_clk_period = 15000; /* 66 MHz */
t_ces = 6;
t_avds = 5;
t_avdh = 2;
t_ach = 6;
t_aavdh = 6;
t_rdyo = 11;
break;
default:
min_gpmc_clk_period = 18500; /* 54 MHz */
t_ces = 7;
t_avds = 7;
t_avdh = 7;
t_ach = 9;
t_aavdh = 7;
t_rdyo = 15;
break;
}
/* Set synchronous read timings */
memset(&dev_t, 0, sizeof(dev_t));
if (!s->sync_write) {
dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
dev_t.t_wpl = t_wpl * 1000;
dev_t.t_wph = t_wph * 1000;
dev_t.t_aavdh = t_aavdh * 1000;
}
dev_t.ce_xdelay = true;
dev_t.avd_xdelay = true;
dev_t.oe_xdelay = true;
dev_t.we_xdelay = true;
dev_t.clk = min_gpmc_clk_period;
dev_t.t_bacc = dev_t.clk;
dev_t.t_ces = t_ces * 1000;
dev_t.t_avds = t_avds * 1000;
dev_t.t_avdh = t_avdh * 1000;
dev_t.t_ach = t_ach * 1000;
dev_t.cyc_iaa = (latency + 1);
dev_t.t_cez_r = t_cez * 1000;
dev_t.t_cez_w = dev_t.t_cez_r;
dev_t.cyc_aavdh_oe = 1;
dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
gpmc_calc_timings(t, s, &dev_t);
}
int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
int latency,
struct gpmc_onenand_info *info)
{
int ret;
struct gpmc_timings gpmc_t;
struct gpmc_settings gpmc_s;
gpmc_read_settings_dt(dev->of_node, &gpmc_s);
info->sync_read = gpmc_s.sync_read;
info->sync_write = gpmc_s.sync_write;
info->burst_len = gpmc_s.burst_len;
if (!gpmc_s.sync_read && !gpmc_s.sync_write)
return 0;
gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
ret = gpmc_cs_program_settings(cs, &gpmc_s);
if (ret < 0)
return ret;
return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
}
EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
int gpmc_get_client_irq(unsigned int irq_config)
{
if (!gpmc_irq_domain) {
pr_warn("%s called before GPMC IRQ domain available\n",
__func__);
return 0;
}
/* we restrict this to NAND IRQs only */
if (irq_config >= GPMC_NR_NAND_IRQS)
return 0;
return irq_create_mapping(gpmc_irq_domain, irq_config);
}
static int gpmc_irq_endis(unsigned long hwirq, bool endis)
{
u32 regval;
/* bits GPMC_NR_NAND_IRQS to 8 are reserved */
if (hwirq >= GPMC_NR_NAND_IRQS)
hwirq += 8 - GPMC_NR_NAND_IRQS;
regval = gpmc_read_reg(GPMC_IRQENABLE);
if (endis)
regval |= BIT(hwirq);
else
regval &= ~BIT(hwirq);
gpmc_write_reg(GPMC_IRQENABLE, regval);
return 0;
}
static void gpmc_irq_disable(struct irq_data *p)
{
gpmc_irq_endis(p->hwirq, false);
}
static void gpmc_irq_enable(struct irq_data *p)
{
gpmc_irq_endis(p->hwirq, true);
}
static void gpmc_irq_mask(struct irq_data *d)
{
gpmc_irq_endis(d->hwirq, false);
}
static void gpmc_irq_unmask(struct irq_data *d)
{
gpmc_irq_endis(d->hwirq, true);
}
static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
{
u32 regval;
/* NAND IRQs polarity is not configurable */
if (hwirq < GPMC_NR_NAND_IRQS)
return;
/* WAITPIN starts at BIT 8 */
hwirq += 8 - GPMC_NR_NAND_IRQS;
regval = gpmc_read_reg(GPMC_CONFIG);
if (rising_edge)
regval &= ~BIT(hwirq);
else
regval |= BIT(hwirq);
gpmc_write_reg(GPMC_CONFIG, regval);
}
static void gpmc_irq_ack(struct irq_data *d)
{
unsigned int hwirq = d->hwirq;
/* skip reserved bits */
if (hwirq >= GPMC_NR_NAND_IRQS)
hwirq += 8 - GPMC_NR_NAND_IRQS;
/* Setting bit to 1 clears (or Acks) the interrupt */
gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
}
static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
{
/* can't set type for NAND IRQs */
if (d->hwirq < GPMC_NR_NAND_IRQS)
return -EINVAL;
/* We can support either rising or falling edge at a time */
if (trigger == IRQ_TYPE_EDGE_FALLING)
gpmc_irq_edge_config(d->hwirq, false);
else if (trigger == IRQ_TYPE_EDGE_RISING)
gpmc_irq_edge_config(d->hwirq, true);
else
return -EINVAL;
return 0;
}
static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
struct gpmc_device *gpmc = d->host_data;
irq_set_chip_data(virq, gpmc);
if (hw < GPMC_NR_NAND_IRQS) {
irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
irq_set_chip_and_handler(virq, &gpmc->irq_chip,
handle_simple_irq);
} else {
irq_set_chip_and_handler(virq, &gpmc->irq_chip,
handle_edge_irq);
}
return 0;
}
static const struct irq_domain_ops gpmc_irq_domain_ops = {
.map = gpmc_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static irqreturn_t gpmc_handle_irq(int irq, void *data)
{
int hwirq, virq;
u32 regval, regvalx;
struct gpmc_device *gpmc = data;
regval = gpmc_read_reg(GPMC_IRQSTATUS);
regvalx = regval;
if (!regval)
return IRQ_NONE;
for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
/* skip reserved status bits */
if (hwirq == GPMC_NR_NAND_IRQS)
regvalx >>= 8 - GPMC_NR_NAND_IRQS;
if (regvalx & BIT(hwirq)) {
virq = irq_find_mapping(gpmc_irq_domain, hwirq);
if (!virq) {
dev_warn(gpmc->dev,
"spurious irq detected hwirq %d, virq %d\n",
hwirq, virq);
}
generic_handle_irq(virq);
}
}
gpmc_write_reg(GPMC_IRQSTATUS, regval);
return IRQ_HANDLED;
}
static int gpmc_setup_irq(struct gpmc_device *gpmc)
{
u32 regval;
int rc;
/* Disable interrupts */
gpmc_write_reg(GPMC_IRQENABLE, 0);
/* clear interrupts */
regval = gpmc_read_reg(GPMC_IRQSTATUS);
gpmc_write_reg(GPMC_IRQSTATUS, regval);
gpmc->irq_chip.name = "gpmc";
gpmc->irq_chip.irq_enable = gpmc_irq_enable;
gpmc->irq_chip.irq_disable = gpmc_irq_disable;
gpmc->irq_chip.irq_ack = gpmc_irq_ack;
gpmc->irq_chip.irq_mask = gpmc_irq_mask;
gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
gpmc->nirqs,
&gpmc_irq_domain_ops,
gpmc);
if (!gpmc_irq_domain) {
dev_err(gpmc->dev, "IRQ domain add failed\n");
return -ENODEV;
}
rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
if (rc) {
dev_err(gpmc->dev, "failed to request irq %d: %d\n",
gpmc->irq, rc);
irq_domain_remove(gpmc_irq_domain);
gpmc_irq_domain = NULL;
}
return rc;
}
static int gpmc_free_irq(struct gpmc_device *gpmc)
{
int hwirq;
free_irq(gpmc->irq, gpmc);
for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
irq_domain_remove(gpmc_irq_domain);
gpmc_irq_domain = NULL;
return 0;
}
static void gpmc_mem_exit(void)
{
int cs;
for (cs = 0; cs < gpmc_cs_num; cs++) {
if (!gpmc_cs_mem_enabled(cs))
continue;
gpmc_cs_delete_mem(cs);
}
}
static void gpmc_mem_init(struct gpmc_device *gpmc)
{
int cs;
if (!gpmc->data) {
/* All legacy devices have same data IO window */
gpmc_mem_root.start = GPMC_MEM_START;
gpmc_mem_root.end = GPMC_MEM_END;
} else {
gpmc_mem_root.start = gpmc->data->start;
gpmc_mem_root.end = gpmc->data->end;
}
/* Reserve all regions that has been set up by bootloader */
for (cs = 0; cs < gpmc_cs_num; cs++) {
u32 base, size;
if (!gpmc_cs_mem_enabled(cs))
continue;
gpmc_cs_get_memconf(cs, &base, &size);
if (gpmc_cs_insert_mem(cs, base, size)) {
pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
__func__, cs, base, base + size);
gpmc_cs_disable_mem(cs);
}
}
}
static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
{
u32 temp;
int div;
div = gpmc_calc_divider(sync_clk);
temp = gpmc_ps_to_ticks(time_ps);
temp = (temp + div - 1) / div;
return gpmc_ticks_to_ps(temp * div);
}
/* XXX: can the cycles be avoided ? */
static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t,
bool mux)
{
u32 temp;
/* adv_rd_off */
temp = dev_t->t_avdp_r;
/* XXX: mux check required ? */
if (mux) {
/* XXX: t_avdp not to be required for sync, only added for tusb
* this indirectly necessitates requirement of t_avdp_r and
* t_avdp_w instead of having a single t_avdp
*/
temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
}
gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
/* oe_on */
temp = dev_t->t_oeasu; /* XXX: remove this ? */
if (mux) {
temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
temp = max_t(u32, temp, gpmc_t->adv_rd_off +
gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
}
gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
/* access */
/* XXX: any scope for improvement ?, by combining oe_on
* and clk_activation, need to check whether
* access = clk_activation + round to sync clk ?
*/
temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
temp += gpmc_t->clk_activation;
if (dev_t->cyc_oe)
temp = max_t(u32, temp, gpmc_t->oe_on +
gpmc_ticks_to_ps(dev_t->cyc_oe));
gpmc_t->access = gpmc_round_ps_to_ticks(temp);
gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
gpmc_t->cs_rd_off = gpmc_t->oe_off;
/* rd_cycle */
temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
gpmc_t->access;
/* XXX: barter t_ce_rdyz with t_cez_r ? */
if (dev_t->t_ce_rdyz)
temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
return 0;
}
static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t,
bool mux)
{
u32 temp;
/* adv_wr_off */
temp = dev_t->t_avdp_w;
if (mux) {
temp = max_t(u32, temp,
gpmc_t->clk_activation + dev_t->t_avdh);
temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
}
gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
/* wr_data_mux_bus */
temp = max_t(u32, dev_t->t_weasu,
gpmc_t->clk_activation + dev_t->t_rdyo);
/* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
* and in that case remember to handle we_on properly
*/
if (mux) {
temp = max_t(u32, temp,
gpmc_t->adv_wr_off + dev_t->t_aavdh);
temp = max_t(u32, temp, gpmc_t->adv_wr_off +
gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
}
gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
/* we_on */
if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
else
gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
/* wr_access */
/* XXX: gpmc_capability check reqd ? , even if not, will not harm */
gpmc_t->wr_access = gpmc_t->access;
/* we_off */
temp = gpmc_t->we_on + dev_t->t_wpl;
temp = max_t(u32, temp,
gpmc_t->wr_access + gpmc_ticks_to_ps(1));
temp = max_t(u32, temp,
gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
dev_t->t_wph);
/* wr_cycle */
temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
temp += gpmc_t->wr_access;
/* XXX: barter t_ce_rdyz with t_cez_w ? */
if (dev_t->t_ce_rdyz)
temp = max_t(u32, temp,
gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
return 0;
}
static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t,
bool mux)
{
u32 temp;
/* adv_rd_off */
temp = dev_t->t_avdp_r;
if (mux)
temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
/* oe_on */
temp = dev_t->t_oeasu;
if (mux)
temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
/* access */
temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
gpmc_t->oe_on + dev_t->t_oe);
temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
gpmc_t->access = gpmc_round_ps_to_ticks(temp);
gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
gpmc_t->cs_rd_off = gpmc_t->oe_off;
/* rd_cycle */
temp = max_t(u32, dev_t->t_rd_cycle,
gpmc_t->cs_rd_off + dev_t->t_cez_r);
temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
return 0;
}
static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t,
bool mux)
{
u32 temp;
/* adv_wr_off */
temp = dev_t->t_avdp_w;
if (mux)
temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
/* wr_data_mux_bus */
temp = dev_t->t_weasu;
if (mux) {
temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
temp = max_t(u32, temp, gpmc_t->adv_wr_off +
gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
}
gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
/* we_on */
if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
else
gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
/* we_off */
temp = gpmc_t->we_on + dev_t->t_wpl;
gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
dev_t->t_wph);
/* wr_cycle */
temp = max_t(u32, dev_t->t_wr_cycle,
gpmc_t->cs_wr_off + dev_t->t_cez_w);
gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
return 0;
}
static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t)
{
u32 temp;
gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
gpmc_get_fclk_period();
gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
dev_t->t_bacc,
gpmc_t->sync_clk);
temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
return 0;
if (dev_t->ce_xdelay)
gpmc_t->bool_timings.cs_extra_delay = true;
if (dev_t->avd_xdelay)
gpmc_t->bool_timings.adv_extra_delay = true;
if (dev_t->oe_xdelay)
gpmc_t->bool_timings.oe_extra_delay = true;
if (dev_t->we_xdelay)
gpmc_t->bool_timings.we_extra_delay = true;
return 0;
}
static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
struct gpmc_device_timings *dev_t,
bool sync)
{
u32 temp;
/* cs_on */
gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
/* adv_on */
temp = dev_t->t_avdasu;
if (dev_t->t_ce_avd)
temp = max_t(u32, temp,
gpmc_t->cs_on + dev_t->t_ce_avd);
gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
if (sync)
gpmc_calc_sync_common_timings(gpmc_t, dev_t);
return 0;
}
/*
* TODO: remove this function once all peripherals are confirmed to
* work with generic timing. Simultaneously gpmc_cs_set_timings()
* has to be modified to handle timings in ps instead of ns
*/
static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
{
t->cs_on /= 1000;
t->cs_rd_off /= 1000;
t->cs_wr_off /= 1000;
t->adv_on /= 1000;
t->adv_rd_off /= 1000;
t->adv_wr_off /= 1000;
t->we_on /= 1000;
t->we_off /= 1000;
t->oe_on /= 1000;
t->oe_off /= 1000;
t->page_burst_access /= 1000;
t->access /= 1000;
t->rd_cycle /= 1000;
t->wr_cycle /= 1000;
t->bus_turnaround /= 1000;
t->cycle2cycle_delay /= 1000;
t->wait_monitoring /= 1000;
t->clk_activation /= 1000;
t->wr_access /= 1000;
t->wr_data_mux_bus /= 1000;
}
int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
struct gpmc_settings *gpmc_s,
struct gpmc_device_timings *dev_t)
{
bool mux = false, sync = false;
if (gpmc_s) {
mux = gpmc_s->mux_add_data ? true : false;
sync = (gpmc_s->sync_read || gpmc_s->sync_write);
}
memset(gpmc_t, 0, sizeof(*gpmc_t));
gpmc_calc_common_timings(gpmc_t, dev_t, sync);
if (gpmc_s && gpmc_s->sync_read)
gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
else
gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
if (gpmc_s && gpmc_s->sync_write)
gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
else
gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
/* TODO: remove, see function definition */
gpmc_convert_ps_to_ns(gpmc_t);
return 0;
}
/**
* gpmc_cs_program_settings - programs non-timing related settings
* @cs: GPMC chip-select to program
* @p: pointer to GPMC settings structure
*
* Programs non-timing related settings for a GPMC chip-select, such as
* bus-width, burst configuration, etc. Function should be called once
* for each chip-select that is being used and must be called before
* calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
* register will be initialised to zero by this function. Returns 0 on
* success and appropriate negative error code on failure.
*/
int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
{
u32 config1;
if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
pr_err("%s: invalid width %d!", __func__, p->device_width);
return -EINVAL;
}
/* Address-data multiplexing not supported for NAND devices */
if (p->device_nand && p->mux_add_data) {
pr_err("%s: invalid configuration!\n", __func__);
return -EINVAL;
}
if ((p->mux_add_data > GPMC_MUX_AD) ||
((p->mux_add_data == GPMC_MUX_AAD) &&
!(gpmc_capability & GPMC_HAS_MUX_AAD))) {
pr_err("%s: invalid multiplex configuration!\n", __func__);
return -EINVAL;
}
/* Page/burst mode supports lengths of 4, 8 and 16 bytes */
if (p->burst_read || p->burst_write) {
switch (p->burst_len) {
case GPMC_BURST_4:
case GPMC_BURST_8:
case GPMC_BURST_16:
break;
default:
pr_err("%s: invalid page/burst-length (%d)\n",
__func__, p->burst_len);
return -EINVAL;
}
}
if (p->wait_pin != GPMC_WAITPIN_INVALID &&
p->wait_pin > gpmc_nr_waitpins) {
pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
return -EINVAL;
}
config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
if (p->sync_read)
config1 |= GPMC_CONFIG1_READTYPE_SYNC;
if (p->sync_write)
config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
if (p->wait_on_read)
config1 |= GPMC_CONFIG1_WAIT_READ_MON;
if (p->wait_on_write)
config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
if (p->wait_on_read || p->wait_on_write)
config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
if (p->device_nand)
config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
if (p->mux_add_data)
config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
if (p->burst_read)
config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
if (p->burst_write)
config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
if (p->burst_read || p->burst_write) {
config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
}
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) {
config1 = gpmc_read_reg(GPMC_CONFIG);
if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW)
config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH)
config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
gpmc_write_reg(GPMC_CONFIG, config1);
}
return 0;
}
#ifdef CONFIG_OF
static void gpmc_cs_set_name(int cs, const char *name)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
gpmc->name = name;
}
static const char *gpmc_cs_get_name(int cs)
{
struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
return gpmc->name;
}
/**
* gpmc_cs_remap - remaps a chip-select physical base address
* @cs: chip-select to remap
* @base: physical base address to re-map chip-select to
*
* Re-maps a chip-select to a new physical base address specified by
* "base". Returns 0 on success and appropriate negative error code
* on failure.
*/
static int gpmc_cs_remap(int cs, u32 base)
{
int ret;
u32 old_base, size;
if (cs >= gpmc_cs_num) {
pr_err("%s: requested chip-select is disabled\n", __func__);
return -ENODEV;
}
/*
* Make sure we ignore any device offsets from the GPMC partition
* allocated for the chip select and that the new base confirms
* to the GPMC 16MB minimum granularity.
*/
base &= ~(SZ_16M - 1);
gpmc_cs_get_memconf(cs, &old_base, &size);
if (base == old_base)
return 0;
ret = gpmc_cs_delete_mem(cs);
if (ret < 0)
return ret;
ret = gpmc_cs_insert_mem(cs, base, size);
if (ret < 0)
return ret;
ret = gpmc_cs_set_memconf(cs, base, size);
return ret;
}
/**
* gpmc_read_settings_dt - read gpmc settings from device-tree
* @np: pointer to device-tree node for a gpmc child device
* @p: pointer to gpmc settings structure
*
* Reads the GPMC settings for a GPMC child device from device-tree and
* stores them in the GPMC settings structure passed. The GPMC settings
* structure is initialised to zero by this function and so any
* previously stored settings will be cleared.
*/
void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
{
memset(p, 0, sizeof(struct gpmc_settings));
p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
of_property_read_u32(np, "gpmc,device-width", &p->device_width);
of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
if (!p->burst_read && !p->burst_write)
pr_warn("%s: page/burst-length set but not used!\n",
__func__);
}
p->wait_pin = GPMC_WAITPIN_INVALID;
p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
if (!gpmc_is_valid_waitpin(p->wait_pin)) {
pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin);
p->wait_pin = GPMC_WAITPIN_INVALID;
}
if (!of_property_read_u32(np, "ti,wait-pin-polarity",
&p->wait_pin_polarity)) {
if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH &&
p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) {
pr_err("%s: Invalid wait-pin-polarity (%d)\n",
__func__, p->wait_pin_polarity);
p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
}
}
p->wait_on_read = of_property_read_bool(np,
"gpmc,wait-on-read");
p->wait_on_write = of_property_read_bool(np,
"gpmc,wait-on-write");
if (!p->wait_on_read && !p->wait_on_write)
pr_debug("%s: rd/wr wait monitoring not enabled!\n",
__func__);
}
}
static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
struct gpmc_timings *gpmc_t)
{
struct gpmc_bool_timings *p;
if (!np || !gpmc_t)
return;
memset(gpmc_t, 0, sizeof(*gpmc_t));
/* minimum clock period for syncronous mode */
of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
/* chip select timtings */
of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
/* ADV signal timings */
of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
&gpmc_t->adv_aad_mux_on);
of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
&gpmc_t->adv_aad_mux_rd_off);
of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
&gpmc_t->adv_aad_mux_wr_off);
/* WE signal timings */
of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
/* OE signal timings */
of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
&gpmc_t->oe_aad_mux_on);
of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
&gpmc_t->oe_aad_mux_off);
/* access and cycle timings */
of_property_read_u32(np, "gpmc,page-burst-access-ns",
&gpmc_t->page_burst_access);
of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
of_property_read_u32(np, "gpmc,bus-turnaround-ns",
&gpmc_t->bus_turnaround);
of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
&gpmc_t->cycle2cycle_delay);
of_property_read_u32(np, "gpmc,wait-monitoring-ns",
&gpmc_t->wait_monitoring);
of_property_read_u32(np, "gpmc,clk-activation-ns",
&gpmc_t->clk_activation);
/* only applicable to OMAP3+ */
of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
&gpmc_t->wr_data_mux_bus);
/* bool timing parameters */
p = &gpmc_t->bool_timings;
p->cycle2cyclediffcsen =
of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
p->cycle2cyclesamecsen =
of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
p->time_para_granularity =
of_property_read_bool(np, "gpmc,time-para-granularity");
}
/**
* gpmc_probe_generic_child - configures the gpmc for a child device
* @pdev: pointer to gpmc platform device
* @child: pointer to device-tree node for child device
*
* Allocates and configures a GPMC chip-select for a child device.
* Returns 0 on success and appropriate negative error code on failure.
*/
static int gpmc_probe_generic_child(struct platform_device *pdev,
struct device_node *child)
{
struct gpmc_settings gpmc_s;
struct gpmc_timings gpmc_t;
struct resource res;
unsigned long base;
const char *name;
int ret, cs;
u32 val;
struct gpmc_device *gpmc = platform_get_drvdata(pdev);
if (of_property_read_u32(child, "reg", &cs) < 0) {
dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
child);
return -ENODEV;
}
if (of_address_to_resource(child, 0, &res) < 0) {
dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
child);
return -ENODEV;
}
/*
* Check if we have multiple instances of the same device
* on a single chip select. If so, use the already initialized
* timings.
*/
name = gpmc_cs_get_name(cs);
if (name && of_node_name_eq(child, name))
goto no_timings;
ret = gpmc_cs_request(cs, resource_size(&res), &base);
if (ret < 0) {
dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
return ret;
}
gpmc_cs_set_name(cs, child->full_name);
gpmc_read_settings_dt(child, &gpmc_s);
gpmc_read_timings_dt(child, &gpmc_t);
/*
* For some GPMC devices we still need to rely on the bootloader
* timings because the devices can be connected via FPGA.
* REVISIT: Add timing support from slls644g.pdf.
*/
if (!gpmc_t.cs_rd_off) {
WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
cs);
gpmc_cs_show_timings(cs,
"please add GPMC bootloader timings to .dts");
goto no_timings;
}
/* CS must be disabled while making changes to gpmc configuration */
gpmc_cs_disable_mem(cs);
/*
* FIXME: gpmc_cs_request() will map the CS to an arbitrary
* location in the gpmc address space. When booting with
* device-tree we want the NOR flash to be mapped to the
* location specified in the device-tree blob. So remap the
* CS to this location. Once DT migration is complete should
* just make gpmc_cs_request() map a specific address.
*/
ret = gpmc_cs_remap(cs, res.start);
if (ret < 0) {
dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
cs, &res.start);
if (res.start < GPMC_MEM_START) {
dev_info(&pdev->dev,
"GPMC CS %d start cannot be lesser than 0x%x\n",
cs, GPMC_MEM_START);
} else if (res.end > GPMC_MEM_END) {
dev_info(&pdev->dev,
"GPMC CS %d end cannot be greater than 0x%x\n",
cs, GPMC_MEM_END);
}
goto err;
}
if (of_node_name_eq(child, "nand")) {
/* Warn about older DT blobs with no compatible property */
if (!of_property_read_bool(child, "compatible")) {
dev_warn(&pdev->dev,
"Incompatible NAND node: missing compatible");
ret = -EINVAL;
goto err;
}
}
if (of_node_name_eq(child, "onenand")) {
/* Warn about older DT blobs with no compatible property */
if (!of_property_read_bool(child, "compatible")) {
dev_warn(&pdev->dev,
"Incompatible OneNAND node: missing compatible");
ret = -EINVAL;
goto err;
}
}
if (of_match_node(omap_nand_ids, child)) {
/* NAND specific setup */
val = 8;
of_property_read_u32(child, "nand-bus-width", &val);
switch (val) {
case 8:
gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
break;
case 16:
gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
break;
default:
dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
child);
ret = -EINVAL;
goto err;
}
/* disable write protect */
gpmc_configure(GPMC_CONFIG_WP, 0);
gpmc_s.device_nand = true;
} else {
ret = of_property_read_u32(child, "bank-width",
&gpmc_s.device_width);
if (ret < 0 && !gpmc_s.device_width) {
dev_err(&pdev->dev,
"%pOF has no 'gpmc,device-width' property\n",
child);
goto err;
}
}
/* Reserve wait pin if it is required and valid */
if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
ret = gpmc_alloc_waitpin(gpmc, &gpmc_s);
if (ret < 0)
goto err;
}
gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
ret = gpmc_cs_program_settings(cs, &gpmc_s);
if (ret < 0)
goto err_cs;
ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
if (ret) {
dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
child);
goto err_cs;
}
/* Clear limited address i.e. enable A26-A11 */
val = gpmc_read_reg(GPMC_CONFIG);
val &= ~GPMC_CONFIG_LIMITEDADDRESS;
gpmc_write_reg(GPMC_CONFIG, val);
/* Enable CS region */
gpmc_cs_enable_mem(cs);
no_timings:
/* create platform device, NULL on error or when disabled */
if (!of_platform_device_create(child, NULL, &pdev->dev))
goto err_child_fail;
/* create children and other common bus children */
if (of_platform_default_populate(child, NULL, &pdev->dev))
goto err_child_fail;
return 0;
err_child_fail:
dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
ret = -ENODEV;
err_cs:
gpmc_free_waitpin(gpmc, gpmc_s.wait_pin);
err:
gpmc_cs_free(cs);
return ret;
}
static const struct of_device_id gpmc_dt_ids[];
static int gpmc_probe_dt(struct platform_device *pdev)
{
int ret;
const struct of_device_id *of_id =
of_match_device(gpmc_dt_ids, &pdev->dev);
if (!of_id)
return 0;
ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
&gpmc_cs_num);
if (ret < 0) {
pr_err("%s: number of chip-selects not defined\n", __func__);
return ret;
} else if (gpmc_cs_num < 1) {
pr_err("%s: all chip-selects are disabled\n", __func__);
return -EINVAL;
} else if (gpmc_cs_num > GPMC_CS_NUM) {
pr_err("%s: number of supported chip-selects cannot be > %d\n",
__func__, GPMC_CS_NUM);
return -EINVAL;
}
ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
&gpmc_nr_waitpins);
if (ret < 0) {
pr_err("%s: number of wait pins not found!\n", __func__);
return ret;
}
return 0;
}
static void gpmc_probe_dt_children(struct platform_device *pdev)
{
int ret;
struct device_node *child;
for_each_available_child_of_node(pdev->dev.of_node, child) {
ret = gpmc_probe_generic_child(pdev, child);
if (ret) {
dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
child, ret);
}
}
}
#else
void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
{
memset(p, 0, sizeof(*p));
}
static int gpmc_probe_dt(struct platform_device *pdev)
{
return 0;
}
static void gpmc_probe_dt_children(struct platform_device *pdev)
{
}
#endif /* CONFIG_OF */
static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
return 1; /* we're input only */
}
static int gpmc_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
return 0; /* we're input only */
}
static int gpmc_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
return -EINVAL; /* we're input only */
}
static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
}
static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
u32 reg;
offset += 8;
reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
return !!reg;
}
static int gpmc_gpio_init(struct gpmc_device *gpmc)
{
int ret;
gpmc->gpio_chip.parent = gpmc->dev;
gpmc->gpio_chip.owner = THIS_MODULE;
gpmc->gpio_chip.label = DEVICE_NAME;
gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
gpmc->gpio_chip.set = gpmc_gpio_set;
gpmc->gpio_chip.get = gpmc_gpio_get;
gpmc->gpio_chip.base = -1;
ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
if (ret < 0) {
dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
return ret;
}
return 0;
}
static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
{
struct omap3_gpmc_regs *gpmc_context;
int i;
if (!gpmc || !gpmc_base)
return;
gpmc_context = &gpmc->context;
gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
for (i = 0; i < gpmc_cs_num; i++) {
gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
if (gpmc_context->cs_context[i].is_valid) {
gpmc_context->cs_context[i].config1 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
gpmc_context->cs_context[i].config2 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
gpmc_context->cs_context[i].config3 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
gpmc_context->cs_context[i].config4 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
gpmc_context->cs_context[i].config5 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
gpmc_context->cs_context[i].config6 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
gpmc_context->cs_context[i].config7 =
gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
}
}
}
static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
{
struct omap3_gpmc_regs *gpmc_context;
int i;
if (!gpmc || !gpmc_base)
return;
gpmc_context = &gpmc->context;
gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
for (i = 0; i < gpmc_cs_num; i++) {
if (gpmc_context->cs_context[i].is_valid) {
gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
gpmc_context->cs_context[i].config1);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
gpmc_context->cs_context[i].config2);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
gpmc_context->cs_context[i].config3);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
gpmc_context->cs_context[i].config4);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
gpmc_context->cs_context[i].config5);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
gpmc_context->cs_context[i].config6);
gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
gpmc_context->cs_context[i].config7);
} else {
gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
}
}
}
static int omap_gpmc_context_notifier(struct notifier_block *nb,
unsigned long cmd, void *v)
{
struct gpmc_device *gpmc;
gpmc = container_of(nb, struct gpmc_device, nb);
if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
return NOTIFY_OK;
switch (cmd) {
case CPU_CLUSTER_PM_ENTER:
omap3_gpmc_save_context(gpmc);
break;
case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
break;
case CPU_CLUSTER_PM_EXIT:
omap3_gpmc_restore_context(gpmc);
break;
}
return NOTIFY_OK;
}
static int gpmc_probe(struct platform_device *pdev)
{
int rc, i;
u32 l;
struct resource *res;
struct gpmc_device *gpmc;
gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
if (!gpmc)
return -ENOMEM;
gpmc->dev = &pdev->dev;
platform_set_drvdata(pdev, gpmc);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
if (!res) {
/* legacy DT */
gpmc_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpmc_base))
return PTR_ERR(gpmc_base);
} else {
gpmc_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(gpmc_base))
return PTR_ERR(gpmc_base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
if (!res) {
dev_err(&pdev->dev, "couldn't get data reg resource\n");
return -ENOENT;
}
gpmc->data = res;
}
gpmc->irq = platform_get_irq(pdev, 0);
if (gpmc->irq < 0)
return gpmc->irq;
gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
if (IS_ERR(gpmc_l3_clk)) {
dev_err(&pdev->dev, "Failed to get GPMC fck\n");
return PTR_ERR(gpmc_l3_clk);
}
if (!clk_get_rate(gpmc_l3_clk)) {
dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
return -EINVAL;
}
if (pdev->dev.of_node) {
rc = gpmc_probe_dt(pdev);
if (rc)
return rc;
} else {
gpmc_cs_num = GPMC_CS_NUM;
gpmc_nr_waitpins = GPMC_NR_WAITPINS;
}
gpmc->waitpins = devm_kzalloc(&pdev->dev,
gpmc_nr_waitpins * sizeof(struct gpmc_waitpin),
GFP_KERNEL);
if (!gpmc->waitpins)
return -ENOMEM;
for (i = 0; i < gpmc_nr_waitpins; i++)
gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID;
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
l = gpmc_read_reg(GPMC_REVISION);
/*
* FIXME: Once device-tree migration is complete the below flags
* should be populated based upon the device-tree compatible
* string. For now just use the IP revision. OMAP3+ devices have
* the wr_access and wr_data_mux_bus register fields. OMAP4+
* devices support the addr-addr-data multiplex protocol.
*
* GPMC IP revisions:
* - OMAP24xx = 2.0
* - OMAP3xxx = 5.0
* - OMAP44xx/54xx/AM335x = 6.0
*/
if (GPMC_REVISION_MAJOR(l) > 0x4)
gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
if (GPMC_REVISION_MAJOR(l) > 0x5)
gpmc_capability |= GPMC_HAS_MUX_AAD;
dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
GPMC_REVISION_MINOR(l));
gpmc_mem_init(gpmc);
rc = gpmc_gpio_init(gpmc);
if (rc)
goto gpio_init_failed;
gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
rc = gpmc_setup_irq(gpmc);
if (rc) {
dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
goto gpio_init_failed;
}
gpmc_probe_dt_children(pdev);
gpmc->nb.notifier_call = omap_gpmc_context_notifier;
cpu_pm_register_notifier(&gpmc->nb);
return 0;
gpio_init_failed:
gpmc_mem_exit();
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return rc;
}
static int gpmc_remove(struct platform_device *pdev)
{
int i;
struct gpmc_device *gpmc = platform_get_drvdata(pdev);
cpu_pm_unregister_notifier(&gpmc->nb);
for (i = 0; i < gpmc_nr_waitpins; i++)
gpmc_free_waitpin(gpmc, i);
gpmc_free_irq(gpmc);
gpmc_mem_exit();
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int gpmc_suspend(struct device *dev)
{
struct gpmc_device *gpmc = dev_get_drvdata(dev);
omap3_gpmc_save_context(gpmc);
pm_runtime_put_sync(dev);
gpmc->is_suspended = 1;
return 0;
}
static int gpmc_resume(struct device *dev)
{
struct gpmc_device *gpmc = dev_get_drvdata(dev);
pm_runtime_get_sync(dev);
omap3_gpmc_restore_context(gpmc);
gpmc->is_suspended = 0;
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
#ifdef CONFIG_OF
static const struct of_device_id gpmc_dt_ids[] = {
{ .compatible = "ti,omap2420-gpmc" },
{ .compatible = "ti,omap2430-gpmc" },
{ .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
{ .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
{ .compatible = "ti,am3352-gpmc" }, /* am335x devices */
{ .compatible = "ti,am64-gpmc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
#endif
static struct platform_driver gpmc_driver = {
.probe = gpmc_probe,
.remove = gpmc_remove,
.driver = {
.name = DEVICE_NAME,
.of_match_table = of_match_ptr(gpmc_dt_ids),
.pm = &gpmc_pm_ops,
},
};
module_platform_driver(gpmc_driver);
MODULE_DESCRIPTION("Texas Instruments GPMC driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/memory/omap-gpmc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell EBU SoC Device Bus Controller
* (memory controller for NOR/NAND/SRAM/FPGA devices)
*
* Copyright (C) 2013-2014 Marvell
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
/* Register definitions */
#define ARMADA_DEV_WIDTH_SHIFT 30
#define ARMADA_BADR_SKEW_SHIFT 28
#define ARMADA_RD_HOLD_SHIFT 23
#define ARMADA_ACC_NEXT_SHIFT 17
#define ARMADA_RD_SETUP_SHIFT 12
#define ARMADA_ACC_FIRST_SHIFT 6
#define ARMADA_SYNC_ENABLE_SHIFT 24
#define ARMADA_WR_HIGH_SHIFT 16
#define ARMADA_WR_LOW_SHIFT 8
#define ARMADA_READ_PARAM_OFFSET 0x0
#define ARMADA_WRITE_PARAM_OFFSET 0x4
#define ORION_RESERVED (0x2 << 30)
#define ORION_BADR_SKEW_SHIFT 28
#define ORION_WR_HIGH_EXT_BIT BIT(27)
#define ORION_WR_HIGH_EXT_MASK 0x8
#define ORION_WR_LOW_EXT_BIT BIT(26)
#define ORION_WR_LOW_EXT_MASK 0x8
#define ORION_ALE_WR_EXT_BIT BIT(25)
#define ORION_ALE_WR_EXT_MASK 0x8
#define ORION_ACC_NEXT_EXT_BIT BIT(24)
#define ORION_ACC_NEXT_EXT_MASK 0x10
#define ORION_ACC_FIRST_EXT_BIT BIT(23)
#define ORION_ACC_FIRST_EXT_MASK 0x10
#define ORION_TURN_OFF_EXT_BIT BIT(22)
#define ORION_TURN_OFF_EXT_MASK 0x8
#define ORION_DEV_WIDTH_SHIFT 20
#define ORION_WR_HIGH_SHIFT 17
#define ORION_WR_HIGH_MASK 0x7
#define ORION_WR_LOW_SHIFT 14
#define ORION_WR_LOW_MASK 0x7
#define ORION_ALE_WR_SHIFT 11
#define ORION_ALE_WR_MASK 0x7
#define ORION_ACC_NEXT_SHIFT 7
#define ORION_ACC_NEXT_MASK 0xF
#define ORION_ACC_FIRST_SHIFT 3
#define ORION_ACC_FIRST_MASK 0xF
#define ORION_TURN_OFF_SHIFT 0
#define ORION_TURN_OFF_MASK 0x7
struct devbus_read_params {
u32 bus_width;
u32 badr_skew;
u32 turn_off;
u32 acc_first;
u32 acc_next;
u32 rd_setup;
u32 rd_hold;
};
struct devbus_write_params {
u32 sync_enable;
u32 wr_high;
u32 wr_low;
u32 ale_wr;
};
struct devbus {
struct device *dev;
void __iomem *base;
unsigned long tick_ps;
};
static int get_timing_param_ps(struct devbus *devbus,
struct device_node *node,
const char *name,
u32 *ticks)
{
u32 time_ps;
int err;
err = of_property_read_u32(node, name, &time_ps);
if (err < 0) {
dev_err(devbus->dev, "%pOF has no '%s' property\n",
node, name);
return err;
}
*ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
name, time_ps, *ticks);
return 0;
}
static int devbus_get_timing_params(struct devbus *devbus,
struct device_node *node,
struct devbus_read_params *r,
struct devbus_write_params *w)
{
int err;
err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
if (err < 0) {
dev_err(devbus->dev,
"%pOF has no 'devbus,bus-width' property\n",
node);
return err;
}
/*
* The bus width is encoded into the register as 0 for 8 bits,
* and 1 for 16 bits, so we do the necessary conversion here.
*/
if (r->bus_width == 8) {
r->bus_width = 0;
} else if (r->bus_width == 16) {
r->bus_width = 1;
} else {
dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
return -EINVAL;
}
err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
&r->badr_skew);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
&r->turn_off);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
&r->acc_first);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
&r->acc_next);
if (err < 0)
return err;
if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
&r->rd_setup);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
&r->rd_hold);
if (err < 0)
return err;
err = of_property_read_u32(node, "devbus,sync-enable",
&w->sync_enable);
if (err < 0) {
dev_err(devbus->dev,
"%pOF has no 'devbus,sync-enable' property\n",
node);
return err;
}
}
err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
&w->ale_wr);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
&w->wr_low);
if (err < 0)
return err;
err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
&w->wr_high);
if (err < 0)
return err;
return 0;
}
static void devbus_orion_set_timing_params(struct devbus *devbus,
struct device_node *node,
struct devbus_read_params *r,
struct devbus_write_params *w)
{
u32 value;
/*
* The hardware designers found it would be a good idea to
* split most of the values in the register into two fields:
* one containing all the low-order bits, and another one
* containing just the high-order bit. For all of those
* fields, we have to split the value into these two parts.
*/
value = (r->turn_off & ORION_TURN_OFF_MASK) << ORION_TURN_OFF_SHIFT |
(r->acc_first & ORION_ACC_FIRST_MASK) << ORION_ACC_FIRST_SHIFT |
(r->acc_next & ORION_ACC_NEXT_MASK) << ORION_ACC_NEXT_SHIFT |
(w->ale_wr & ORION_ALE_WR_MASK) << ORION_ALE_WR_SHIFT |
(w->wr_low & ORION_WR_LOW_MASK) << ORION_WR_LOW_SHIFT |
(w->wr_high & ORION_WR_HIGH_MASK) << ORION_WR_HIGH_SHIFT |
r->bus_width << ORION_DEV_WIDTH_SHIFT |
((r->turn_off & ORION_TURN_OFF_EXT_MASK) ? ORION_TURN_OFF_EXT_BIT : 0) |
((r->acc_first & ORION_ACC_FIRST_EXT_MASK) ? ORION_ACC_FIRST_EXT_BIT : 0) |
((r->acc_next & ORION_ACC_NEXT_EXT_MASK) ? ORION_ACC_NEXT_EXT_BIT : 0) |
((w->ale_wr & ORION_ALE_WR_EXT_MASK) ? ORION_ALE_WR_EXT_BIT : 0) |
((w->wr_low & ORION_WR_LOW_EXT_MASK) ? ORION_WR_LOW_EXT_BIT : 0) |
((w->wr_high & ORION_WR_HIGH_EXT_MASK) ? ORION_WR_HIGH_EXT_BIT : 0) |
(r->badr_skew << ORION_BADR_SKEW_SHIFT) |
ORION_RESERVED;
writel(value, devbus->base);
}
static void devbus_armada_set_timing_params(struct devbus *devbus,
struct device_node *node,
struct devbus_read_params *r,
struct devbus_write_params *w)
{
u32 value;
/* Set read timings */
value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT |
r->badr_skew << ARMADA_BADR_SKEW_SHIFT |
r->rd_hold << ARMADA_RD_HOLD_SHIFT |
r->acc_next << ARMADA_ACC_NEXT_SHIFT |
r->rd_setup << ARMADA_RD_SETUP_SHIFT |
r->acc_first << ARMADA_ACC_FIRST_SHIFT |
r->turn_off;
dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
devbus->base + ARMADA_READ_PARAM_OFFSET,
value);
writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
/* Set write timings */
value = w->sync_enable << ARMADA_SYNC_ENABLE_SHIFT |
w->wr_low << ARMADA_WR_LOW_SHIFT |
w->wr_high << ARMADA_WR_HIGH_SHIFT |
w->ale_wr;
dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
devbus->base + ARMADA_WRITE_PARAM_OFFSET,
value);
writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
}
static int mvebu_devbus_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = pdev->dev.of_node;
struct devbus_read_params r;
struct devbus_write_params w;
struct devbus *devbus;
struct clk *clk;
unsigned long rate;
int err;
devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
if (!devbus)
return -ENOMEM;
devbus->dev = dev;
devbus->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(devbus->base))
return PTR_ERR(devbus->base);
clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(clk))
return PTR_ERR(clk);
/*
* Obtain clock period in picoseconds,
* we need this in order to convert timing
* parameters from cycles to picoseconds.
*/
rate = clk_get_rate(clk) / 1000;
devbus->tick_ps = 1000000000 / rate;
dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
devbus->tick_ps);
if (!of_property_read_bool(node, "devbus,keep-config")) {
/* Read the Device Tree node */
err = devbus_get_timing_params(devbus, node, &r, &w);
if (err < 0)
return err;
/* Set the new timing parameters */
if (of_device_is_compatible(node, "marvell,orion-devbus"))
devbus_orion_set_timing_params(devbus, node, &r, &w);
else
devbus_armada_set_timing_params(devbus, node, &r, &w);
}
/*
* We need to create a child device explicitly from here to
* guarantee that the child will be probed after the timing
* parameters for the bus are written.
*/
err = of_platform_populate(node, NULL, NULL, dev);
if (err < 0)
return err;
return 0;
}
static const struct of_device_id mvebu_devbus_of_match[] = {
{ .compatible = "marvell,mvebu-devbus" },
{ .compatible = "marvell,orion-devbus" },
{},
};
MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
static struct platform_driver mvebu_devbus_driver = {
.probe = mvebu_devbus_probe,
.driver = {
.name = "mvebu-devbus",
.of_match_table = mvebu_devbus_of_match,
},
};
static int __init mvebu_devbus_init(void)
{
return platform_driver_register(&mvebu_devbus_driver);
}
module_init(mvebu_devbus_init);
MODULE_AUTHOR("Ezequiel Garcia <[email protected]>");
MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
|
linux-master
|
drivers/memory/mvebu-devbus.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Memory controller driver for ARM PrimeCell PL172
* PrimeCell MultiPort Memory Controller (PL172)
*
* Copyright (C) 2015 Joachim Eastwood <[email protected]>
*
* Based on:
* TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
*/
#include <linux/amba/bus.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/time.h>
#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
#define MPMC_STATIC_CFG_MW_8BIT 0x0
#define MPMC_STATIC_CFG_MW_16BIT 0x1
#define MPMC_STATIC_CFG_MW_32BIT 0x2
#define MPMC_STATIC_CFG_PM BIT(3)
#define MPMC_STATIC_CFG_PC BIT(6)
#define MPMC_STATIC_CFG_PB BIT(7)
#define MPMC_STATIC_CFG_EW BIT(8)
#define MPMC_STATIC_CFG_B BIT(19)
#define MPMC_STATIC_CFG_P BIT(20)
#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
#define MPMC_STATIC_WAIT_RD_MAX 0x1f
#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
#define MPMC_STATIC_WAIT_WR_MAX 0x1f
#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
/* Maximum number of static chip selects */
#define PL172_MAX_CS 4
struct pl172_data {
void __iomem *base;
unsigned long rate;
struct clk *clk;
};
static int pl172_timing_prop(struct amba_device *adev,
const struct device_node *np, const char *name,
u32 reg_offset, u32 max, int start)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
int cycles;
u32 val;
if (!of_property_read_u32(np, name, &val)) {
cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
if (cycles < 0) {
cycles = 0;
} else if (cycles > max) {
dev_err(&adev->dev, "%s timing too tight\n", name);
return -EINVAL;
}
writel(cycles, pl172->base + reg_offset);
}
dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
readl(pl172->base + reg_offset));
return 0;
}
static int pl172_setup_static(struct amba_device *adev,
struct device_node *np, u32 cs)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
u32 cfg;
int ret;
/* MPMC static memory configuration */
if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
if (cfg == 8) {
cfg = MPMC_STATIC_CFG_MW_8BIT;
} else if (cfg == 16) {
cfg = MPMC_STATIC_CFG_MW_16BIT;
} else if (cfg == 32) {
cfg = MPMC_STATIC_CFG_MW_32BIT;
} else {
dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
return -EINVAL;
}
} else {
dev_err(&adev->dev, "memory-width property required\n");
return -EINVAL;
}
if (of_property_read_bool(np, "mpmc,async-page-mode"))
cfg |= MPMC_STATIC_CFG_PM;
if (of_property_read_bool(np, "mpmc,cs-active-high"))
cfg |= MPMC_STATIC_CFG_PC;
if (of_property_read_bool(np, "mpmc,byte-lane-low"))
cfg |= MPMC_STATIC_CFG_PB;
if (of_property_read_bool(np, "mpmc,extended-wait"))
cfg |= MPMC_STATIC_CFG_EW;
if (amba_part(adev) == 0x172 &&
of_property_read_bool(np, "mpmc,buffer-enable"))
cfg |= MPMC_STATIC_CFG_B;
if (of_property_read_bool(np, "mpmc,write-protect"))
cfg |= MPMC_STATIC_CFG_P;
writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
/* MPMC static memory timing */
ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
MPMC_STATIC_WAIT_WEN(cs),
MPMC_STATIC_WAIT_WEN_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
MPMC_STATIC_WAIT_OEN(cs),
MPMC_STATIC_WAIT_OEN_MAX, 0);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
MPMC_STATIC_WAIT_RD(cs),
MPMC_STATIC_WAIT_RD_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
MPMC_STATIC_WAIT_PAGE(cs),
MPMC_STATIC_WAIT_PAGE_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
MPMC_STATIC_WAIT_WR(cs),
MPMC_STATIC_WAIT_WR_MAX, 2);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
MPMC_STATIC_WAIT_TURN(cs),
MPMC_STATIC_WAIT_TURN_MAX, 1);
if (ret)
goto fail;
return 0;
fail:
dev_err(&adev->dev, "failed to configure cs%u\n", cs);
return ret;
}
static int pl172_parse_cs_config(struct amba_device *adev,
struct device_node *np)
{
u32 cs;
if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
if (cs >= PL172_MAX_CS) {
dev_err(&adev->dev, "cs%u invalid\n", cs);
return -EINVAL;
}
return pl172_setup_static(adev, np, cs);
}
dev_err(&adev->dev, "cs property required\n");
return -EINVAL;
}
static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
static const char * const pl175_revisions[] = {"r1"};
static const char * const pl176_revisions[] = {"r0"};
static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device_node *child_np, *np = adev->dev.of_node;
struct device *dev = &adev->dev;
static const char *rev = "?";
struct pl172_data *pl172;
int ret;
if (amba_part(adev) == 0x172) {
if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
rev = pl172_revisions[amba_rev(adev)];
} else if (amba_part(adev) == 0x175) {
if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
rev = pl175_revisions[amba_rev(adev)];
} else if (amba_part(adev) == 0x176) {
if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
rev = pl176_revisions[amba_rev(adev)];
}
dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
if (!pl172)
return -ENOMEM;
pl172->clk = devm_clk_get(dev, "mpmcclk");
if (IS_ERR(pl172->clk)) {
dev_err(dev, "no mpmcclk provided clock\n");
return PTR_ERR(pl172->clk);
}
ret = clk_prepare_enable(pl172->clk);
if (ret) {
dev_err(dev, "unable to mpmcclk enable clock\n");
return ret;
}
pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
if (!pl172->rate) {
dev_err(dev, "unable to get mpmcclk clock rate\n");
ret = -EINVAL;
goto err_clk_enable;
}
ret = amba_request_regions(adev, NULL);
if (ret) {
dev_err(dev, "unable to request AMBA regions\n");
goto err_clk_enable;
}
pl172->base = devm_ioremap(dev, adev->res.start,
resource_size(&adev->res));
if (!pl172->base) {
dev_err(dev, "ioremap failed\n");
ret = -ENOMEM;
goto err_no_ioremap;
}
amba_set_drvdata(adev, pl172);
/*
* Loop through each child node, which represent a chip select, and
* configure parameters and timing. If successful; populate devices
* under that node.
*/
for_each_available_child_of_node(np, child_np) {
ret = pl172_parse_cs_config(adev, child_np);
if (ret)
continue;
of_platform_populate(child_np, NULL, NULL, dev);
}
return 0;
err_no_ioremap:
amba_release_regions(adev);
err_clk_enable:
clk_disable_unprepare(pl172->clk);
return ret;
}
static void pl172_remove(struct amba_device *adev)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
clk_disable_unprepare(pl172->clk);
amba_release_regions(adev);
}
static const struct amba_id pl172_ids[] = {
/* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
{
.id = 0x07041172,
.mask = 0x3f0fffff,
},
/* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
{
.id = 0x07041175,
.mask = 0x3f0fffff,
},
/* PrimeCell MPMC PL176 */
{
.id = 0x89041176,
.mask = 0xff0fffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl172_ids);
static struct amba_driver pl172_driver = {
.drv = {
.name = "memory-pl172",
},
.probe = pl172_probe,
.remove = pl172_remove,
.id_table = pl172_ids,
};
module_amba_driver(pl172_driver);
MODULE_AUTHOR("Joachim Eastwood <[email protected]>");
MODULE_DESCRIPTION("PL172 Memory Controller Driver");
MODULE_LICENSE("GPL v2");
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linux-master
|
drivers/memory/pl172.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
*
* Copyright (c) 2017 Broadcom
*/
/*
* This driver provides access to the DPFE interface of Broadcom STB SoCs.
* The firmware running on the DCPU inside the DDR PHY can provide current
* information about the system's RAM, for instance the DRAM refresh rate.
* This can be used as an indirect indicator for the DRAM's temperature.
* Slower refresh rate means cooler RAM, higher refresh rate means hotter
* RAM.
*
* Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
* already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
*
* Note regarding the loading of the firmware image: we use be32_to_cpu()
* and le_32_to_cpu(), so we can support the following four cases:
* - LE kernel + LE firmware image (the most common case)
* - LE kernel + BE firmware image
* - BE kernel + LE firmware image
* - BE kernel + BE firmware image
*
* The DPCU always runs in big endian mode. The firmware image, however, can
* be in either format. Also, communication between host CPU and DCPU is
* always in little endian.
*/
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#define DRVNAME "brcmstb-dpfe"
/* DCPU register offsets */
#define REG_DCPU_RESET 0x0
#define REG_TO_DCPU_MBOX 0x10
#define REG_TO_HOST_MBOX 0x14
/* Macros to process offsets returned by the DCPU */
#define DRAM_MSG_ADDR_OFFSET 0x0
#define DRAM_MSG_TYPE_OFFSET 0x1c
#define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
#define DRAM_MSG_TYPE_MASK ((1UL << \
(BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
/* Message RAM */
#define DCPU_MSG_RAM_START 0x100
#define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
/* DRAM Info Offsets & Masks */
#define DRAM_INFO_INTERVAL 0x0
#define DRAM_INFO_MR4 0x4
#define DRAM_INFO_ERROR 0x8
#define DRAM_INFO_MR4_MASK 0xff
#define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */
/* DRAM MR4 Offsets & Masks */
#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
#define DRAM_MR4_REFRESH_MASK 0x7
#define DRAM_MR4_SR_ABORT_MASK 0x1
#define DRAM_MR4_PPRE_MASK 0x1
#define DRAM_MR4_TH_OFFS_MASK 0x3
#define DRAM_MR4_TUF_MASK 0x1
/* DRAM Vendor Offsets & Masks (API v2) */
#define DRAM_VENDOR_MR5 0x0
#define DRAM_VENDOR_MR6 0x4
#define DRAM_VENDOR_MR7 0x8
#define DRAM_VENDOR_MR8 0xc
#define DRAM_VENDOR_ERROR 0x10
#define DRAM_VENDOR_MASK 0xff
#define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */
/* DRAM Information Offsets & Masks (API v3) */
#define DRAM_DDR_INFO_MR4 0x0
#define DRAM_DDR_INFO_MR5 0x4
#define DRAM_DDR_INFO_MR6 0x8
#define DRAM_DDR_INFO_MR7 0xc
#define DRAM_DDR_INFO_MR8 0x10
#define DRAM_DDR_INFO_ERROR 0x14
#define DRAM_DDR_INFO_MASK 0xff
/* Reset register bits & masks */
#define DCPU_RESET_SHIFT 0x0
#define DCPU_RESET_MASK 0x1
#define DCPU_CLK_DISABLE_SHIFT 0x2
/* DCPU return codes */
#define DCPU_RET_ERROR_BIT BIT(31)
#define DCPU_RET_SUCCESS 0x1
#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
/* This error code is not firmware defined and only used in the driver. */
#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
/* Firmware magic */
#define DPFE_BE_MAGIC 0xfe1010fe
#define DPFE_LE_MAGIC 0xfe0101fe
/* Error codes */
#define ERR_INVALID_MAGIC -1
#define ERR_INVALID_SIZE -2
#define ERR_INVALID_CHKSUM -3
/* Message types */
#define DPFE_MSG_TYPE_COMMAND 1
#define DPFE_MSG_TYPE_RESPONSE 2
#define DELAY_LOOP_MAX 1000
enum dpfe_msg_fields {
MSG_HEADER,
MSG_COMMAND,
MSG_ARG_COUNT,
MSG_ARG0,
MSG_FIELD_MAX = 16 /* Max number of arguments */
};
enum dpfe_commands {
DPFE_CMD_GET_INFO,
DPFE_CMD_GET_REFRESH,
DPFE_CMD_GET_VENDOR,
DPFE_CMD_MAX /* Last entry */
};
/*
* Format of the binary firmware file:
*
* entry
* 0 header
* value: 0xfe0101fe <== little endian
* 0xfe1010fe <== big endian
* 1 sequence:
* [31:16] total segments on this build
* [15:0] this segment sequence.
* 2 FW version
* 3 IMEM byte size
* 4 DMEM byte size
* IMEM
* DMEM
* last checksum ==> sum of everything
*/
struct dpfe_firmware_header {
u32 magic;
u32 sequence;
u32 version;
u32 imem_size;
u32 dmem_size;
};
/* Things we only need during initialization. */
struct init_data {
unsigned int dmem_len;
unsigned int imem_len;
unsigned int chksum;
bool is_big_endian;
};
/* API version and corresponding commands */
struct dpfe_api {
int version;
const char *fw_name;
const struct attribute_group **sysfs_attrs;
u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
};
/* Things we need for as long as we are active. */
struct brcmstb_dpfe_priv {
void __iomem *regs;
void __iomem *dmem;
void __iomem *imem;
struct device *dev;
const struct dpfe_api *dpfe_api;
struct mutex lock;
};
/*
* Forward declaration of our sysfs attribute functions, so we can declare the
* attribute data structures early.
*/
static ssize_t show_info(struct device *, struct device_attribute *, char *);
static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
static ssize_t store_refresh(struct device *, struct device_attribute *,
const char *, size_t);
static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
static ssize_t show_dram(struct device *, struct device_attribute *, char *);
/*
* Declare our attributes early, so they can be referenced in the API data
* structure. We need to do this, because the attributes depend on the API
* version.
*/
static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
/* API v2 sysfs attributes */
static struct attribute *dpfe_v2_attrs[] = {
&dev_attr_dpfe_info.attr,
&dev_attr_dpfe_refresh.attr,
&dev_attr_dpfe_vendor.attr,
NULL
};
ATTRIBUTE_GROUPS(dpfe_v2);
/* API v3 sysfs attributes */
static struct attribute *dpfe_v3_attrs[] = {
&dev_attr_dpfe_info.attr,
&dev_attr_dpfe_dram.attr,
NULL
};
ATTRIBUTE_GROUPS(dpfe_v3);
/*
* Old API v2 firmware commands, as defined in the rev 0.61 specification, we
* use a version set to 1 to denote that it is not compatible with the new API
* v2 and onwards.
*/
static const struct dpfe_api dpfe_api_old_v2 = {
.version = 1,
.fw_name = "dpfe.bin",
.sysfs_attrs = dpfe_v2_groups,
.command = {
[DPFE_CMD_GET_INFO] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 1,
[MSG_ARG_COUNT] = 1,
[MSG_ARG0] = 1,
},
[DPFE_CMD_GET_REFRESH] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 2,
[MSG_ARG_COUNT] = 1,
[MSG_ARG0] = 1,
},
[DPFE_CMD_GET_VENDOR] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 2,
[MSG_ARG_COUNT] = 1,
[MSG_ARG0] = 2,
},
}
};
/*
* API v2 firmware commands, as defined in the rev 0.8 specification, named new
* v2 here
*/
static const struct dpfe_api dpfe_api_new_v2 = {
.version = 2,
.fw_name = NULL, /* We expect the firmware to have been downloaded! */
.sysfs_attrs = dpfe_v2_groups,
.command = {
[DPFE_CMD_GET_INFO] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 0x101,
},
[DPFE_CMD_GET_REFRESH] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 0x201,
},
[DPFE_CMD_GET_VENDOR] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 0x202,
},
}
};
/* API v3 firmware commands */
static const struct dpfe_api dpfe_api_v3 = {
.version = 3,
.fw_name = NULL, /* We expect the firmware to have been downloaded! */
.sysfs_attrs = dpfe_v3_groups,
.command = {
[DPFE_CMD_GET_INFO] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 0x0101,
[MSG_ARG_COUNT] = 1,
[MSG_ARG0] = 1,
},
[DPFE_CMD_GET_REFRESH] = {
[MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
[MSG_COMMAND] = 0x0202,
[MSG_ARG_COUNT] = 0,
},
/* There's no GET_VENDOR command in API v3. */
},
};
static const char *get_error_text(unsigned int i)
{
static const char * const error_text[] = {
"Success", "Header code incorrect",
"Unknown command or argument", "Incorrect checksum",
"Malformed command", "Timed out", "Unknown error",
};
if (unlikely(i >= ARRAY_SIZE(error_text)))
i = ARRAY_SIZE(error_text) - 1;
return error_text[i];
}
static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
{
u32 val;
mutex_lock(&priv->lock);
val = readl_relaxed(priv->regs + REG_DCPU_RESET);
mutex_unlock(&priv->lock);
return !(val & DCPU_RESET_MASK);
}
static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
{
u32 val;
if (!is_dcpu_enabled(priv))
return;
mutex_lock(&priv->lock);
/* Put DCPU in reset if it's running. */
val = readl_relaxed(priv->regs + REG_DCPU_RESET);
val |= (1 << DCPU_RESET_SHIFT);
writel_relaxed(val, priv->regs + REG_DCPU_RESET);
mutex_unlock(&priv->lock);
}
static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
{
void __iomem *regs = priv->regs;
u32 val;
mutex_lock(&priv->lock);
/* Clear mailbox registers. */
writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
writel_relaxed(0, regs + REG_TO_HOST_MBOX);
/* Disable DCPU clock gating */
val = readl_relaxed(regs + REG_DCPU_RESET);
val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
writel_relaxed(val, regs + REG_DCPU_RESET);
/* Take DCPU out of reset */
val = readl_relaxed(regs + REG_DCPU_RESET);
val &= ~(1 << DCPU_RESET_SHIFT);
writel_relaxed(val, regs + REG_DCPU_RESET);
mutex_unlock(&priv->lock);
}
static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
{
unsigned int sum = 0;
unsigned int i;
/* Don't include the last field in the checksum. */
for (i = 0; i < max; i++)
sum += msg[i];
return sum;
}
static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
char *buf, ssize_t *size)
{
unsigned int msg_type;
unsigned int offset;
void __iomem *ptr = NULL;
/* There is no need to use this function for API v3 or later. */
if (unlikely(priv->dpfe_api->version >= 3))
return NULL;
msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
/*
* msg_type == 1: the offset is relative to the message RAM
* msg_type == 0: the offset is relative to the data RAM (this is the
* previous way of passing data)
* msg_type is anything else: there's critical hardware problem
*/
switch (msg_type) {
case 1:
ptr = priv->regs + DCPU_MSG_RAM_START + offset;
break;
case 0:
ptr = priv->dmem + offset;
break;
default:
dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
response);
if (buf && size)
*size = sprintf(buf,
"FATAL: communication error with DCPU\n");
}
return ptr;
}
static void __finalize_command(struct brcmstb_dpfe_priv *priv)
{
unsigned int release_mbox;
/*
* It depends on the API version which MBOX register we have to write to
* signal we are done.
*/
release_mbox = (priv->dpfe_api->version < 2)
? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
writel_relaxed(0, priv->regs + release_mbox);
}
static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
u32 result[])
{
void __iomem *regs = priv->regs;
unsigned int i, chksum, chksum_idx;
const u32 *msg;
int ret = 0;
u32 resp;
if (cmd >= DPFE_CMD_MAX)
return -1;
msg = priv->dpfe_api->command[cmd];
mutex_lock(&priv->lock);
/* Wait for DCPU to become ready */
for (i = 0; i < DELAY_LOOP_MAX; i++) {
resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
if (resp == 0)
break;
msleep(1);
}
if (resp != 0) {
mutex_unlock(&priv->lock);
return -ffs(DCPU_RET_ERR_TIMEDOUT);
}
/* Compute checksum over the message */
chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
chksum = get_msg_chksum(msg, chksum_idx);
/* Write command and arguments to message area */
for (i = 0; i < MSG_FIELD_MAX; i++) {
if (i == chksum_idx)
writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
else
writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
}
/* Tell DCPU there is a command waiting */
writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
/* Wait for DCPU to process the command */
for (i = 0; i < DELAY_LOOP_MAX; i++) {
/* Read response code */
resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
if (resp > 0)
break;
msleep(1);
}
if (i == DELAY_LOOP_MAX) {
resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
ret = -ffs(resp);
} else {
/* Read response data */
for (i = 0; i < MSG_FIELD_MAX; i++)
result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
}
/* Tell DCPU we are done */
__finalize_command(priv);
mutex_unlock(&priv->lock);
if (ret)
return ret;
/* Verify response */
chksum = get_msg_chksum(result, chksum_idx);
if (chksum != result[chksum_idx])
resp = DCPU_RET_ERR_CHKSUM;
if (resp != DCPU_RET_SUCCESS) {
resp &= ~DCPU_RET_ERROR_BIT;
ret = -ffs(resp);
}
return ret;
}
/* Ensure that the firmware file loaded meets all the requirements. */
static int __verify_firmware(struct init_data *init,
const struct firmware *fw)
{
const struct dpfe_firmware_header *header = (void *)fw->data;
unsigned int dmem_size, imem_size, total_size;
bool is_big_endian = false;
const u32 *chksum_ptr;
if (header->magic == DPFE_BE_MAGIC)
is_big_endian = true;
else if (header->magic != DPFE_LE_MAGIC)
return ERR_INVALID_MAGIC;
if (is_big_endian) {
dmem_size = be32_to_cpu(header->dmem_size);
imem_size = be32_to_cpu(header->imem_size);
} else {
dmem_size = le32_to_cpu(header->dmem_size);
imem_size = le32_to_cpu(header->imem_size);
}
/* Data and instruction sections are 32 bit words. */
if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
return ERR_INVALID_SIZE;
/*
* The header + the data section + the instruction section + the
* checksum must be equal to the total firmware size.
*/
total_size = dmem_size + imem_size + sizeof(*header) +
sizeof(*chksum_ptr);
if (total_size != fw->size)
return ERR_INVALID_SIZE;
/* The checksum comes at the very end. */
chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
init->is_big_endian = is_big_endian;
init->dmem_len = dmem_size;
init->imem_len = imem_size;
init->chksum = (is_big_endian)
? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
return 0;
}
/* Verify checksum by reading back the firmware from co-processor RAM. */
static int __verify_fw_checksum(struct init_data *init,
struct brcmstb_dpfe_priv *priv,
const struct dpfe_firmware_header *header,
u32 checksum)
{
u32 magic, sequence, version, sum;
u32 __iomem *dmem = priv->dmem;
u32 __iomem *imem = priv->imem;
unsigned int i;
if (init->is_big_endian) {
magic = be32_to_cpu(header->magic);
sequence = be32_to_cpu(header->sequence);
version = be32_to_cpu(header->version);
} else {
magic = le32_to_cpu(header->magic);
sequence = le32_to_cpu(header->sequence);
version = le32_to_cpu(header->version);
}
sum = magic + sequence + version + init->dmem_len + init->imem_len;
for (i = 0; i < init->dmem_len / sizeof(u32); i++)
sum += readl_relaxed(dmem + i);
for (i = 0; i < init->imem_len / sizeof(u32); i++)
sum += readl_relaxed(imem + i);
return (sum == checksum) ? 0 : -1;
}
static int __write_firmware(u32 __iomem *mem, const u32 *fw,
unsigned int size, bool is_big_endian)
{
unsigned int i;
/* Convert size to 32-bit words. */
size /= sizeof(u32);
/* It is recommended to clear the firmware area first. */
for (i = 0; i < size; i++)
writel_relaxed(0, mem + i);
/* Now copy it. */
if (is_big_endian) {
for (i = 0; i < size; i++)
writel_relaxed(be32_to_cpu(fw[i]), mem + i);
} else {
for (i = 0; i < size; i++)
writel_relaxed(le32_to_cpu(fw[i]), mem + i);
}
return 0;
}
static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
{
const struct dpfe_firmware_header *header;
unsigned int dmem_size, imem_size;
struct device *dev = priv->dev;
bool is_big_endian = false;
const struct firmware *fw;
const u32 *dmem, *imem;
struct init_data init;
const void *fw_blob;
int ret;
/*
* Skip downloading the firmware if the DCPU is already running and
* responding to commands.
*/
if (is_dcpu_enabled(priv)) {
u32 response[MSG_FIELD_MAX];
ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
if (!ret)
return 0;
}
/*
* If the firmware filename is NULL it means the boot firmware has to
* download the DCPU firmware for us. If that didn't work, we have to
* bail, since downloading it ourselves wouldn't work either.
*/
if (!priv->dpfe_api->fw_name)
return -ENODEV;
ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
/*
* Defer the firmware download if the firmware file couldn't be found.
* The root file system may not be available yet.
*/
if (ret)
return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
ret = __verify_firmware(&init, fw);
if (ret) {
ret = -EFAULT;
goto release_fw;
}
__disable_dcpu(priv);
is_big_endian = init.is_big_endian;
dmem_size = init.dmem_len;
imem_size = init.imem_len;
/* At the beginning of the firmware blob is a header. */
header = (struct dpfe_firmware_header *)fw->data;
/* Void pointer to the beginning of the actual firmware. */
fw_blob = fw->data + sizeof(*header);
/* IMEM comes right after the header. */
imem = fw_blob;
/* DMEM follows after IMEM. */
dmem = fw_blob + imem_size;
ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
if (ret)
goto release_fw;
ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
if (ret)
goto release_fw;
ret = __verify_fw_checksum(&init, priv, header, init.chksum);
if (ret)
goto release_fw;
__enable_dcpu(priv);
release_fw:
release_firmware(fw);
return ret;
}
static ssize_t generic_show(unsigned int command, u32 response[],
struct brcmstb_dpfe_priv *priv, char *buf)
{
int ret;
if (!priv)
return sprintf(buf, "ERROR: driver private data not set\n");
ret = __send_command(priv, command, response);
if (ret < 0)
return sprintf(buf, "ERROR: %s\n", get_error_text(-ret));
return 0;
}
static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
char *buf)
{
u32 response[MSG_FIELD_MAX];
struct brcmstb_dpfe_priv *priv;
unsigned int info;
ssize_t ret;
priv = dev_get_drvdata(dev);
ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
if (ret)
return ret;
info = response[MSG_ARG0];
return sprintf(buf, "%u.%u.%u.%u\n",
(info >> 24) & 0xff,
(info >> 16) & 0xff,
(info >> 8) & 0xff,
info & 0xff);
}
static ssize_t show_refresh(struct device *dev,
struct device_attribute *devattr, char *buf)
{
u32 response[MSG_FIELD_MAX];
void __iomem *info;
struct brcmstb_dpfe_priv *priv;
u8 refresh, sr_abort, ppre, thermal_offs, tuf;
u32 mr4;
ssize_t ret;
priv = dev_get_drvdata(dev);
ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
if (ret)
return ret;
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
if (!info)
return ret;
mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
DRAM_INFO_MR4_MASK;
refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
readl_relaxed(info + DRAM_INFO_INTERVAL),
refresh, sr_abort, ppre, thermal_offs, tuf,
readl_relaxed(info + DRAM_INFO_ERROR));
}
static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
u32 response[MSG_FIELD_MAX];
struct brcmstb_dpfe_priv *priv;
void __iomem *info;
unsigned long val;
int ret;
if (kstrtoul(buf, 0, &val) < 0)
return -EINVAL;
priv = dev_get_drvdata(dev);
ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
if (ret)
return ret;
info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
if (!info)
return -EIO;
writel_relaxed(val, info + DRAM_INFO_INTERVAL);
return count;
}
static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
char *buf)
{
u32 response[MSG_FIELD_MAX];
struct brcmstb_dpfe_priv *priv;
void __iomem *info;
ssize_t ret;
u32 mr5, mr6, mr7, mr8, err;
priv = dev_get_drvdata(dev);
ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
if (ret)
return ret;
info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
if (!info)
return ret;
mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
DRAM_VENDOR_MASK;
mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
DRAM_VENDOR_MASK;
mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
DRAM_VENDOR_MASK;
mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
DRAM_VENDOR_MASK;
err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
}
static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
char *buf)
{
u32 response[MSG_FIELD_MAX];
struct brcmstb_dpfe_priv *priv;
ssize_t ret;
u32 mr4, mr5, mr6, mr7, mr8, err;
priv = dev_get_drvdata(dev);
ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
if (ret)
return ret;
mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
mr8, err);
}
static int brcmstb_dpfe_resume(struct platform_device *pdev)
{
struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
return brcmstb_dpfe_download_firmware(priv);
}
static int brcmstb_dpfe_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct brcmstb_dpfe_priv *priv;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
mutex_init(&priv->lock);
platform_set_drvdata(pdev, priv);
priv->regs = devm_platform_ioremap_resource_byname(pdev, "dpfe-cpu");
if (IS_ERR(priv->regs)) {
dev_err(dev, "couldn't map DCPU registers\n");
return -ENODEV;
}
priv->dmem = devm_platform_ioremap_resource_byname(pdev, "dpfe-dmem");
if (IS_ERR(priv->dmem)) {
dev_err(dev, "Couldn't map DCPU data memory\n");
return -ENOENT;
}
priv->imem = devm_platform_ioremap_resource_byname(pdev, "dpfe-imem");
if (IS_ERR(priv->imem)) {
dev_err(dev, "Couldn't map DCPU instruction memory\n");
return -ENOENT;
}
priv->dpfe_api = of_device_get_match_data(dev);
if (unlikely(!priv->dpfe_api)) {
/*
* It should be impossible to end up here, but to be safe we
* check anyway.
*/
dev_err(dev, "Couldn't determine API\n");
return -ENOENT;
}
ret = brcmstb_dpfe_download_firmware(priv);
if (ret)
return dev_err_probe(dev, ret, "Couldn't download firmware\n");
ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
if (!ret)
dev_info(dev, "registered with API v%d.\n",
priv->dpfe_api->version);
return ret;
}
static int brcmstb_dpfe_remove(struct platform_device *pdev)
{
struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
return 0;
}
static const struct of_device_id brcmstb_dpfe_of_match[] = {
/* Use legacy API v2 for a select number of chips */
{ .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
{ .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
{ .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
{ .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
/* API v3 is the default going forward */
{ .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
{}
};
MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
static struct platform_driver brcmstb_dpfe_driver = {
.driver = {
.name = DRVNAME,
.of_match_table = brcmstb_dpfe_of_match,
},
.probe = brcmstb_dpfe_probe,
.remove = brcmstb_dpfe_remove,
.resume = brcmstb_dpfe_resume,
};
module_platform_driver(brcmstb_dpfe_driver);
MODULE_AUTHOR("Markus Mayer <[email protected]>");
MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/memory/brcmstb_dpfe.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* DDR addressing details and AC timing parameters from JEDEC specs
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* Aneesh V <[email protected]>
*/
#include <linux/export.h>
#include "jedec_ddr.h"
/* LPDDR2 addressing details from JESD209-2 section 2.4 */
const struct lpddr2_addressing
lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
const struct lpddr2_timings
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
/* Speed bin 400(200 MHz) */
[0] = {
.max_freq = 200000000,
.min_freq = 10000000,
.tRPab = 21000,
.tRCD = 18000,
.tWR = 15000,
.tRAS_min = 42000,
.tRRD = 10000,
.tWTR = 10000,
.tXP = 7500,
.tRTP = 7500,
.tCKESR = 15000,
.tDQSCK_max = 5500,
.tFAW = 50000,
.tZQCS = 90000,
.tZQCL = 360000,
.tZQinit = 1000000,
.tRAS_max_ns = 70000,
.tDQSCK_max_derated = 6000,
},
/* Speed bin 533(266 MHz) */
[1] = {
.max_freq = 266666666,
.min_freq = 10000000,
.tRPab = 21000,
.tRCD = 18000,
.tWR = 15000,
.tRAS_min = 42000,
.tRRD = 10000,
.tWTR = 7500,
.tXP = 7500,
.tRTP = 7500,
.tCKESR = 15000,
.tDQSCK_max = 5500,
.tFAW = 50000,
.tZQCS = 90000,
.tZQCL = 360000,
.tZQinit = 1000000,
.tRAS_max_ns = 70000,
.tDQSCK_max_derated = 6000,
},
/* Speed bin 800(400 MHz) */
[2] = {
.max_freq = 400000000,
.min_freq = 10000000,
.tRPab = 21000,
.tRCD = 18000,
.tWR = 15000,
.tRAS_min = 42000,
.tRRD = 10000,
.tWTR = 7500,
.tXP = 7500,
.tRTP = 7500,
.tCKESR = 15000,
.tDQSCK_max = 5500,
.tFAW = 50000,
.tZQCS = 90000,
.tZQCL = 360000,
.tZQinit = 1000000,
.tRAS_max_ns = 70000,
.tDQSCK_max_derated = 6000,
},
/* Speed bin 1066(533 MHz) */
[3] = {
.max_freq = 533333333,
.min_freq = 10000000,
.tRPab = 21000,
.tRCD = 18000,
.tWR = 15000,
.tRAS_min = 42000,
.tRRD = 10000,
.tWTR = 7500,
.tXP = 7500,
.tRTP = 7500,
.tCKESR = 15000,
.tDQSCK_max = 5500,
.tFAW = 50000,
.tZQCS = 90000,
.tZQCL = 360000,
.tZQinit = 1000000,
.tRAS_max_ns = 70000,
.tDQSCK_max_derated = 5620,
},
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
.tRPab = 3,
.tRCD = 3,
.tWR = 3,
.tRASmin = 3,
.tRRD = 2,
.tWTR = 2,
.tXP = 2,
.tRTP = 2,
.tCKE = 3,
.tCKESR = 3,
.tFAW = 8
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id)
{
switch (manufacturer_id) {
case LPDDR2_MANID_SAMSUNG:
return "Samsung";
case LPDDR2_MANID_QIMONDA:
return "Qimonda";
case LPDDR2_MANID_ELPIDA:
return "Elpida";
case LPDDR2_MANID_ETRON:
return "Etron";
case LPDDR2_MANID_NANYA:
return "Nanya";
case LPDDR2_MANID_HYNIX:
return "Hynix";
case LPDDR2_MANID_MOSEL:
return "Mosel";
case LPDDR2_MANID_WINBOND:
return "Winbond";
case LPDDR2_MANID_ESMT:
return "ESMT";
case LPDDR2_MANID_SPANSION:
return "Spansion";
case LPDDR2_MANID_SST:
return "SST";
case LPDDR2_MANID_ZMOS:
return "ZMOS";
case LPDDR2_MANID_INTEL:
return "Intel";
case LPDDR2_MANID_NUMONYX:
return "Numonyx";
case LPDDR2_MANID_MICRON:
return "Micron";
default:
break;
}
return "invalid";
}
EXPORT_SYMBOL_GPL(lpddr2_jedec_manufacturer);
|
linux-master
|
drivers/memory/jedec_ddr_data.c
|
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2015 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// Exynos - SROM Controller support
// Author: Pankaj Dubey <[email protected]>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "exynos-srom.h"
static const unsigned long exynos_srom_offsets[] = {
/* SROM side */
EXYNOS_SROM_BW,
EXYNOS_SROM_BC0,
EXYNOS_SROM_BC1,
EXYNOS_SROM_BC2,
EXYNOS_SROM_BC3,
};
/**
* struct exynos_srom_reg_dump: register dump of SROM Controller registers.
* @offset: srom register offset from the controller base address.
* @value: the value of register under the offset.
*/
struct exynos_srom_reg_dump {
u32 offset;
u32 value;
};
/**
* struct exynos_srom: platform data for exynos srom controller driver.
* @dev: platform device pointer
* @reg_base: srom base address
* @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
*/
struct exynos_srom {
struct device *dev;
void __iomem *reg_base;
struct exynos_srom_reg_dump *reg_offset;
};
static struct exynos_srom_reg_dump *
exynos_srom_alloc_reg_dump(const unsigned long *rdump,
unsigned long nr_rdump)
{
struct exynos_srom_reg_dump *rd;
unsigned int i;
rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
if (!rd)
return NULL;
for (i = 0; i < nr_rdump; ++i)
rd[i].offset = rdump[i];
return rd;
}
static int exynos_srom_configure_bank(struct exynos_srom *srom,
struct device_node *np)
{
u32 bank, width, pmc = 0;
u32 timing[6];
u32 cs, bw;
if (of_property_read_u32(np, "reg", &bank))
return -EINVAL;
if (of_property_read_u32(np, "reg-io-width", &width))
width = 1;
if (of_property_read_bool(np, "samsung,srom-page-mode"))
pmc = 1 << EXYNOS_SROM_BCX__PMC__SHIFT;
if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
ARRAY_SIZE(timing)))
return -EINVAL;
bank *= 4; /* Convert bank into shift/offset */
cs = 1 << EXYNOS_SROM_BW__BYTEENABLE__SHIFT;
if (width == 2)
cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
(timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
(timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
(timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
(timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
(timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
srom->reg_base + EXYNOS_SROM_BC0 + bank);
return 0;
}
static int exynos_srom_probe(struct platform_device *pdev)
{
struct device_node *np, *child;
struct exynos_srom *srom;
struct device *dev = &pdev->dev;
bool bad_bank_config = false;
np = dev->of_node;
if (!np) {
dev_err(&pdev->dev, "could not find device info\n");
return -EINVAL;
}
srom = devm_kzalloc(&pdev->dev,
sizeof(struct exynos_srom), GFP_KERNEL);
if (!srom)
return -ENOMEM;
srom->dev = dev;
srom->reg_base = of_iomap(np, 0);
if (!srom->reg_base) {
dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, srom);
srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
ARRAY_SIZE(exynos_srom_offsets));
if (!srom->reg_offset) {
iounmap(srom->reg_base);
return -ENOMEM;
}
for_each_child_of_node(np, child) {
if (exynos_srom_configure_bank(srom, child)) {
dev_err(dev,
"Could not decode bank configuration for %pOFn\n",
child);
bad_bank_config = true;
}
}
/*
* If any bank failed to configure, we still provide suspend/resume,
* but do not probe child devices
*/
if (bad_bank_config)
return 0;
return of_platform_populate(np, NULL, NULL, dev);
}
#ifdef CONFIG_PM_SLEEP
static void exynos_srom_save(void __iomem *base,
struct exynos_srom_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd)
rd->value = readl(base + rd->offset);
}
static void exynos_srom_restore(void __iomem *base,
const struct exynos_srom_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd)
writel(rd->value, base + rd->offset);
}
static int exynos_srom_suspend(struct device *dev)
{
struct exynos_srom *srom = dev_get_drvdata(dev);
exynos_srom_save(srom->reg_base, srom->reg_offset,
ARRAY_SIZE(exynos_srom_offsets));
return 0;
}
static int exynos_srom_resume(struct device *dev)
{
struct exynos_srom *srom = dev_get_drvdata(dev);
exynos_srom_restore(srom->reg_base, srom->reg_offset,
ARRAY_SIZE(exynos_srom_offsets));
return 0;
}
#endif
static const struct of_device_id of_exynos_srom_ids[] = {
{
.compatible = "samsung,exynos4210-srom",
},
{},
};
static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);
static struct platform_driver exynos_srom_driver = {
.probe = exynos_srom_probe,
.driver = {
.name = "exynos-srom",
.of_match_table = of_exynos_srom_ids,
.pm = &exynos_srom_pm_ops,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver(exynos_srom_driver);
|
linux-master
|
drivers/memory/samsung/exynos-srom.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 Samsung Electronics Co., Ltd.
* Author: Lukasz Luba <[email protected]>
*/
#include <linux/clk.h>
#include <linux/devfreq.h>
#include <linux/devfreq-event.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include "../jedec_ddr.h"
#include "../of_memory.h"
static int irqmode;
module_param(irqmode, int, 0644);
MODULE_PARM_DESC(irqmode, "Enable IRQ mode (0=off [default], 1=on)");
#define EXYNOS5_DREXI_TIMINGAREF (0x0030)
#define EXYNOS5_DREXI_TIMINGROW0 (0x0034)
#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038)
#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C)
#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4)
#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8)
#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC)
#define CDREX_PAUSE (0x2091c)
#define CDREX_LPDDR3PHY_CON3 (0x20a20)
#define CDREX_LPDDR3PHY_CLKM_SRC (0x20700)
#define EXYNOS5_TIMING_SET_SWI BIT(28)
#define USE_MX_MSPLL_TIMINGS (1)
#define USE_BPLL_TIMINGS (0)
#define EXYNOS5_AREF_NORMAL (0x2e)
#define DREX_PPCCLKCON (0x0130)
#define DREX_PEREV2CONFIG (0x013c)
#define DREX_PMNC_PPC (0xE000)
#define DREX_CNTENS_PPC (0xE010)
#define DREX_CNTENC_PPC (0xE020)
#define DREX_INTENS_PPC (0xE030)
#define DREX_INTENC_PPC (0xE040)
#define DREX_FLAG_PPC (0xE050)
#define DREX_PMCNT2_PPC (0xE130)
/*
* A value for register DREX_PMNC_PPC which should be written to reset
* the cycle counter CCNT (a reference wall clock). It sets zero to the
* CCNT counter.
*/
#define CC_RESET BIT(2)
/*
* A value for register DREX_PMNC_PPC which does the reset of all performance
* counters to zero.
*/
#define PPC_COUNTER_RESET BIT(1)
/*
* Enables all configured counters (including cycle counter). The value should
* be written to the register DREX_PMNC_PPC.
*/
#define PPC_ENABLE BIT(0)
/* A value for register DREX_PPCCLKCON which enables performance events clock.
* Must be written before first access to the performance counters register
* set, otherwise it could crash.
*/
#define PEREV_CLK_EN BIT(0)
/*
* Values which are used to enable counters, interrupts or configure flags of
* the performance counters. They configure counter 2 and cycle counter.
*/
#define PERF_CNT2 BIT(2)
#define PERF_CCNT BIT(31)
/*
* Performance event types which are used for setting the preferred event
* to track in the counters.
* There is a set of different types, the values are from range 0 to 0x6f.
* These settings should be written to the configuration register which manages
* the type of the event (register DREX_PEREV2CONFIG).
*/
#define READ_TRANSFER_CH0 (0x6d)
#define READ_TRANSFER_CH1 (0x6f)
#define PERF_COUNTER_START_VALUE 0xff000000
#define PERF_EVENT_UP_DOWN_THRESHOLD 900000000ULL
/**
* struct dmc_opp_table - Operating level desciption
* @freq_hz: target frequency in Hz
* @volt_uv: target voltage in uV
*
* Covers frequency and voltage settings of the DMC operating mode.
*/
struct dmc_opp_table {
u32 freq_hz;
u32 volt_uv;
};
/**
* struct exynos5_dmc - main structure describing DMC device
* @dev: DMC device
* @df: devfreq device structure returned by devfreq framework
* @gov_data: configuration of devfreq governor
* @base_drexi0: DREX0 registers mapping
* @base_drexi1: DREX1 registers mapping
* @clk_regmap: regmap for clock controller registers
* @lock: protects curr_rate and frequency/voltage setting section
* @curr_rate: current frequency
* @curr_volt: current voltage
* @opp: OPP table
* @opp_count: number of 'opp' elements
* @timings_arr_size: number of 'timings' elements
* @timing_row: values for timing row register, for each OPP
* @timing_data: values for timing data register, for each OPP
* @timing_power: balues for timing power register, for each OPP
* @timings: DDR memory timings, from device tree
* @min_tck: DDR memory minimum timing values, from device tree
* @bypass_timing_row: value for timing row register for bypass timings
* @bypass_timing_data: value for timing data register for bypass timings
* @bypass_timing_power: value for timing power register for bypass
* timings
* @vdd_mif: Memory interface regulator
* @fout_spll: clock: SPLL
* @fout_bpll: clock: BPLL
* @mout_spll: clock: mux SPLL
* @mout_bpll: clock: mux BPLL
* @mout_mclk_cdrex: clock: mux mclk_cdrex
* @mout_mx_mspll_ccore: clock: mux mx_mspll_ccore
* @counter: devfreq events
* @num_counters: number of 'counter' elements
* @last_overflow_ts: time (in ns) of last overflow of each DREX
* @load: utilization in percents
* @total: total time between devfreq events
* @in_irq_mode: whether running in interrupt mode (true)
* or polling (false)
*
* The main structure for the Dynamic Memory Controller which covers clocks,
* memory regions, HW information, parameters and current operating mode.
*/
struct exynos5_dmc {
struct device *dev;
struct devfreq *df;
struct devfreq_simple_ondemand_data gov_data;
void __iomem *base_drexi0;
void __iomem *base_drexi1;
struct regmap *clk_regmap;
/* Protects curr_rate and frequency/voltage setting section */
struct mutex lock;
unsigned long curr_rate;
unsigned long curr_volt;
struct dmc_opp_table *opp;
int opp_count;
u32 timings_arr_size;
u32 *timing_row;
u32 *timing_data;
u32 *timing_power;
const struct lpddr3_timings *timings;
const struct lpddr3_min_tck *min_tck;
u32 bypass_timing_row;
u32 bypass_timing_data;
u32 bypass_timing_power;
struct regulator *vdd_mif;
struct clk *fout_spll;
struct clk *fout_bpll;
struct clk *mout_spll;
struct clk *mout_bpll;
struct clk *mout_mclk_cdrex;
struct clk *mout_mx_mspll_ccore;
struct devfreq_event_dev **counter;
int num_counters;
u64 last_overflow_ts[2];
unsigned long load;
unsigned long total;
bool in_irq_mode;
};
#define TIMING_FIELD(t_name, t_bit_beg, t_bit_end) \
{ .name = t_name, .bit_beg = t_bit_beg, .bit_end = t_bit_end }
#define TIMING_VAL2REG(timing, t_val) \
({ \
u32 __val; \
__val = (t_val) << (timing)->bit_beg; \
__val; \
})
struct timing_reg {
char *name;
int bit_beg;
int bit_end;
unsigned int val;
};
static const struct timing_reg timing_row_reg_fields[] = {
TIMING_FIELD("tRFC", 24, 31),
TIMING_FIELD("tRRD", 20, 23),
TIMING_FIELD("tRP", 16, 19),
TIMING_FIELD("tRCD", 12, 15),
TIMING_FIELD("tRC", 6, 11),
TIMING_FIELD("tRAS", 0, 5),
};
static const struct timing_reg timing_data_reg_fields[] = {
TIMING_FIELD("tWTR", 28, 31),
TIMING_FIELD("tWR", 24, 27),
TIMING_FIELD("tRTP", 20, 23),
TIMING_FIELD("tW2W-C2C", 14, 14),
TIMING_FIELD("tR2R-C2C", 12, 12),
TIMING_FIELD("WL", 8, 11),
TIMING_FIELD("tDQSCK", 4, 7),
TIMING_FIELD("RL", 0, 3),
};
static const struct timing_reg timing_power_reg_fields[] = {
TIMING_FIELD("tFAW", 26, 31),
TIMING_FIELD("tXSR", 16, 25),
TIMING_FIELD("tXP", 8, 15),
TIMING_FIELD("tCKE", 4, 7),
TIMING_FIELD("tMRD", 0, 3),
};
#define TIMING_COUNT (ARRAY_SIZE(timing_row_reg_fields) + \
ARRAY_SIZE(timing_data_reg_fields) + \
ARRAY_SIZE(timing_power_reg_fields))
static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
{
int i, ret;
for (i = 0; i < dmc->num_counters; i++) {
if (!dmc->counter[i])
continue;
ret = devfreq_event_set_event(dmc->counter[i]);
if (ret < 0)
return ret;
}
return 0;
}
static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
{
int i, ret;
for (i = 0; i < dmc->num_counters; i++) {
if (!dmc->counter[i])
continue;
ret = devfreq_event_enable_edev(dmc->counter[i]);
if (ret < 0)
return ret;
}
return 0;
}
static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
{
int i, ret;
for (i = 0; i < dmc->num_counters; i++) {
if (!dmc->counter[i])
continue;
ret = devfreq_event_disable_edev(dmc->counter[i]);
if (ret < 0)
return ret;
}
return 0;
}
/**
* find_target_freq_idx() - Finds requested frequency in local DMC configuration
* @dmc: device for which the information is checked
* @target_rate: requested frequency in KHz
*
* Seeks in the local DMC driver structure for the requested frequency value
* and returns index or error value.
*/
static int find_target_freq_idx(struct exynos5_dmc *dmc,
unsigned long target_rate)
{
int i;
for (i = dmc->opp_count - 1; i >= 0; i--)
if (dmc->opp[i].freq_hz <= target_rate)
return i;
return -EINVAL;
}
/**
* exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
* @dmc: device for which the new settings is going to be applied
* @set: boolean variable passing set value
*
* Changes the register set, which holds timing parameters.
* There is two register sets: 0 and 1. The register set 0
* is used in normal operation when the clock is provided from main PLL.
* The bank register set 1 is used when the main PLL frequency is going to be
* changed and the clock is taken from alternative, stable source.
* This function switches between these banks according to the
* currently used clock source.
*/
static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
{
unsigned int reg;
int ret;
ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
if (ret)
return ret;
if (set)
reg |= EXYNOS5_TIMING_SET_SWI;
else
reg &= ~EXYNOS5_TIMING_SET_SWI;
regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
return 0;
}
/**
* exynos5_init_freq_table() - Initialized PM OPP framework
* @dmc: DMC device for which the frequencies are used for OPP init
* @profile: devfreq device's profile
*
* Populate the devfreq device's OPP table based on current frequency, voltage.
*/
static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
struct devfreq_dev_profile *profile)
{
int i, ret;
int idx;
unsigned long freq;
ret = devm_pm_opp_of_add_table(dmc->dev);
if (ret < 0) {
dev_err(dmc->dev, "Failed to get OPP table\n");
return ret;
}
dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
sizeof(struct dmc_opp_table), GFP_KERNEL);
if (!dmc->opp)
return -ENOMEM;
idx = dmc->opp_count - 1;
for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
struct dev_pm_opp *opp;
opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
if (IS_ERR(opp))
return PTR_ERR(opp);
dmc->opp[idx - i].freq_hz = freq;
dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
}
return 0;
}
/**
* exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
* @dmc: device for which the new settings is going to be applied
*
* Low-level function for changing timings for DRAM memory clocking from
* 'bypass' clock source (fixed frequency @400MHz).
* It uses timing bank registers set 1.
*/
static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
{
writel(EXYNOS5_AREF_NORMAL,
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
writel(dmc->bypass_timing_row,
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
writel(dmc->bypass_timing_row,
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
writel(dmc->bypass_timing_data,
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
writel(dmc->bypass_timing_data,
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
writel(dmc->bypass_timing_power,
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
writel(dmc->bypass_timing_power,
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
}
/**
* exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
* @dmc: device for which the new settings is going to be applied
* @target_rate: target frequency of the DMC
*
* Low-level function for changing timings for DRAM memory operating from main
* clock source (BPLL), which can have different frequencies. Thus, each
* frequency must have corresponding timings register values in order to keep
* the needed delays.
* It uses timing bank registers set 0.
*/
static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
unsigned long target_rate)
{
int idx;
for (idx = dmc->opp_count - 1; idx >= 0; idx--)
if (dmc->opp[idx].freq_hz <= target_rate)
break;
if (idx < 0)
return -EINVAL;
writel(EXYNOS5_AREF_NORMAL,
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
writel(dmc->timing_row[idx],
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
writel(dmc->timing_row[idx],
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
writel(dmc->timing_data[idx],
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
writel(dmc->timing_data[idx],
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
writel(dmc->timing_power[idx],
dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
writel(dmc->timing_power[idx],
dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
return 0;
}
/**
* exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
* @dmc: device for which it is going to be set
* @target_volt: new voltage which is chosen to be final
*
* Function tries to align voltage to the safe level for 'normal' mode.
* It checks the need of higher voltage and changes the value. The target
* voltage might be lower that currently set and still the system will be
* stable.
*/
static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
unsigned long target_volt)
{
int ret = 0;
if (dmc->curr_volt <= target_volt)
return 0;
ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
target_volt);
if (!ret)
dmc->curr_volt = target_volt;
return ret;
}
/**
* exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
* @dmc: device for which it is going to be set
* @target_volt: new voltage which is chosen to be final
*
* Function tries to align voltage to the safe level for the 'bypass' mode.
* It checks the need of higher voltage and changes the value.
* The target voltage must not be less than currently needed, because
* for current frequency the device might become unstable.
*/
static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
unsigned long target_volt)
{
int ret = 0;
if (dmc->curr_volt >= target_volt)
return 0;
ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
target_volt);
if (!ret)
dmc->curr_volt = target_volt;
return ret;
}
/**
* exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
* @dmc: device for which it is going to be set
* @target_rate: new frequency which is chosen to be final
*
* Function changes the DRAM timings for the temporary 'bypass' mode.
*/
static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
unsigned long target_rate)
{
int idx = find_target_freq_idx(dmc, target_rate);
if (idx < 0)
return -EINVAL;
exynos5_set_bypass_dram_timings(dmc);
return 0;
}
/**
* exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
* @dmc: DMC device for which the switching is going to happen
* @target_rate: new frequency which is going to be set as a final
* @target_volt: new voltage which is going to be set as a final
*
* Function configures DMC and clocks for operating in temporary 'bypass' mode.
* This mode is used only temporary but if required, changes voltage and timings
* for DRAM chips. It switches the main clock to stable clock source for the
* period of the main PLL reconfiguration.
*/
static int
exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
unsigned long target_rate,
unsigned long target_volt)
{
int ret;
/*
* Having higher voltage for a particular frequency does not harm
* the chip. Use it for the temporary frequency change when one
* voltage manipulation might be avoided.
*/
ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
if (ret)
return ret;
/*
* Longer delays for DRAM does not cause crash, the opposite does.
*/
ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
if (ret)
return ret;
/*
* Delays are long enough, so use them for the new coming clock.
*/
ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
return ret;
}
/**
* exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
* using safe procedure
* @dmc: device for which the frequency is going to be changed
* @target_rate: requested new frequency
* @target_volt: requested voltage which corresponds to the new frequency
*
* The DMC frequency change procedure requires a few steps.
* The main requirement is to change the clock source in the clk mux
* for the time of main clock PLL locking. The assumption is that the
* alternative clock source set as parent is stable.
* The second parent's clock frequency is fixed to 400MHz, it is named 'bypass'
* clock. This requires alignment in DRAM timing parameters for the new
* T-period. There is two bank sets for keeping DRAM
* timings: set 0 and set 1. The set 0 is used when main clock source is
* chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
* the two bank sets is part of the process.
* The voltage must also be aligned to the minimum required level. There is
* this intermediate step with switching to 'bypass' parent clock source.
* if the old voltage is lower, it requires an increase of the voltage level.
* The complexity of the voltage manipulation is hidden in low level function.
* In this function there is last alignment of the voltage level at the end.
*/
static int
exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
unsigned long target_rate,
unsigned long target_volt)
{
int ret;
ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
target_volt);
if (ret)
return ret;
/*
* Voltage is set at least to a level needed for this frequency,
* so switching clock source is safe now.
*/
clk_prepare_enable(dmc->fout_spll);
clk_prepare_enable(dmc->mout_spll);
clk_prepare_enable(dmc->mout_mx_mspll_ccore);
ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
if (ret)
goto disable_clocks;
/*
* We are safe to increase the timings for current bypass frequency.
* Thanks to this the settings will be ready for the upcoming clock
* source change.
*/
exynos5_dram_change_timings(dmc, target_rate);
clk_set_rate(dmc->fout_bpll, target_rate);
ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
if (ret)
goto disable_clocks;
ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
if (ret)
goto disable_clocks;
/*
* Make sure if the voltage is not from 'bypass' settings and align to
* the right level for power efficiency.
*/
ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
disable_clocks:
clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
clk_disable_unprepare(dmc->mout_spll);
clk_disable_unprepare(dmc->fout_spll);
return ret;
}
/**
* exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
* table.
* @dmc: device for which the frequency is going to be changed
* @freq: requested frequency in KHz
* @target_rate: returned frequency which is the same or lower than
* requested
* @target_volt: returned voltage which corresponds to the returned
* frequency
* @flags: devfreq flags provided for this frequency change request
*
* Function gets requested frequency and checks OPP framework for needed
* frequency and voltage. It populates the values 'target_rate' and
* 'target_volt' or returns error value when OPP framework fails.
*/
static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
unsigned long *freq,
unsigned long *target_rate,
unsigned long *target_volt, u32 flags)
{
struct dev_pm_opp *opp;
opp = devfreq_recommended_opp(dmc->dev, freq, flags);
if (IS_ERR(opp))
return PTR_ERR(opp);
*target_rate = dev_pm_opp_get_freq(opp);
*target_volt = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
return 0;
}
/**
* exynos5_dmc_target() - Function responsible for changing frequency of DMC
* @dev: device for which the frequency is going to be changed
* @freq: requested frequency in KHz
* @flags: flags provided for this frequency change request
*
* An entry function provided to the devfreq framework which provides frequency
* change of the DMC. The function gets the possible rate from OPP table based
* on requested frequency. It calls the next function responsible for the
* frequency and voltage change. In case of failure, does not set 'curr_rate'
* and returns error value to the framework.
*/
static int exynos5_dmc_target(struct device *dev, unsigned long *freq,
u32 flags)
{
struct exynos5_dmc *dmc = dev_get_drvdata(dev);
unsigned long target_rate = 0;
unsigned long target_volt = 0;
int ret;
ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
flags);
if (ret)
return ret;
if (target_rate == dmc->curr_rate)
return 0;
mutex_lock(&dmc->lock);
ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
if (ret) {
mutex_unlock(&dmc->lock);
return ret;
}
dmc->curr_rate = target_rate;
mutex_unlock(&dmc->lock);
return 0;
}
/**
* exynos5_counters_get() - Gets the performance counters values.
* @dmc: device for which the counters are going to be checked
* @load_count: variable which is populated with counter value
* @total_count: variable which is used as 'wall clock' reference
*
* Function which provides performance counters values. It sums up counters for
* two DMC channels. The 'total_count' is used as a reference and max value.
* The ratio 'load_count/total_count' shows the busy percentage [0%, 100%].
*/
static int exynos5_counters_get(struct exynos5_dmc *dmc,
unsigned long *load_count,
unsigned long *total_count)
{
unsigned long total = 0;
struct devfreq_event_data event;
int ret, i;
*load_count = 0;
/* Take into account only read+write counters, but stop all */
for (i = 0; i < dmc->num_counters; i++) {
if (!dmc->counter[i])
continue;
ret = devfreq_event_get_event(dmc->counter[i], &event);
if (ret < 0)
return ret;
*load_count += event.load_count;
if (total < event.total_count)
total = event.total_count;
}
*total_count = total;
return 0;
}
/**
* exynos5_dmc_start_perf_events() - Setup and start performance event counters
* @dmc: device for which the counters are going to be checked
* @beg_value: initial value for the counter
*
* Function which enables needed counters, interrupts and sets initial values
* then starts the counters.
*/
static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc,
u32 beg_value)
{
/* Enable interrupts for counter 2 */
writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
/* Enable counter 2 and CCNT */
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
/* Clear overflow flag for all counters */
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
/* Reset all counters */
writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
/*
* Set start value for the counters, the number of samples that
* will be gathered is calculated as: 0xffffffff - beg_value
*/
writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
/* Start all counters */
writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
}
/**
* exynos5_dmc_perf_events_calc() - Calculate utilization
* @dmc: device for which the counters are going to be checked
* @diff_ts: time between last interrupt and current one
*
* Function which calculates needed utilization for the devfreq governor.
* It prepares values for 'busy_time' and 'total_time' based on elapsed time
* between interrupts, which approximates utilization.
*/
static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)
{
/*
* This is a simple algorithm for managing traffic on DMC.
* When there is almost no load the counters overflow every 4s,
* no mater the DMC frequency.
* The high load might be approximated using linear function.
* Knowing that, simple calculation can provide 'busy_time' and
* 'total_time' to the devfreq governor which picks up target
* frequency.
* We want a fast ramp up and slow decay in frequency change function.
*/
if (diff_ts < PERF_EVENT_UP_DOWN_THRESHOLD) {
/*
* Set higher utilization for the simple_ondemand governor.
* The governor should increase the frequency of the DMC.
*/
dmc->load = 70;
dmc->total = 100;
} else {
/*
* Set low utilization for the simple_ondemand governor.
* The governor should decrease the frequency of the DMC.
*/
dmc->load = 35;
dmc->total = 100;
}
dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts);
}
/**
* exynos5_dmc_perf_events_check() - Checks the status of the counters
* @dmc: device for which the counters are going to be checked
*
* Function which is called from threaded IRQ to check the counters state
* and to call approximation for the needed utilization.
*/
static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc)
{
u32 val;
u64 diff_ts, ts;
ts = ktime_get_ns();
/* Stop all counters */
writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
/* Check the source in interrupt flag registers (which channel) */
val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
if (val) {
diff_ts = ts - dmc->last_overflow_ts[0];
dmc->last_overflow_ts[0] = ts;
dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
} else {
val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
diff_ts = ts - dmc->last_overflow_ts[1];
dmc->last_overflow_ts[1] = ts;
dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
}
exynos5_dmc_perf_events_calc(dmc, diff_ts);
exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
}
/**
* exynos5_dmc_enable_perf_events() - Enable performance events
* @dmc: device for which the counters are going to be checked
*
* Function which is setup needed environment and enables counters.
*/
static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc)
{
u64 ts;
/* Enable Performance Event Clock */
writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
/* Select read transfers as performance event2 */
writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
ts = ktime_get_ns();
dmc->last_overflow_ts[0] = ts;
dmc->last_overflow_ts[1] = ts;
/* Devfreq shouldn't be faster than initialization, play safe though. */
dmc->load = 99;
dmc->total = 100;
}
/**
* exynos5_dmc_disable_perf_events() - Disable performance events
* @dmc: device for which the counters are going to be checked
*
* Function which stops, disables performance event counters and interrupts.
*/
static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc)
{
/* Stop all counters */
writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
/* Disable interrupts for counter 2 */
writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
/* Disable counter 2 and CCNT */
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
/* Clear overflow flag for all counters */
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
}
/**
* exynos5_dmc_get_status() - Read current DMC performance statistics.
* @dev: device for which the statistics are requested
* @stat: structure which has statistic fields
*
* Function reads the DMC performance counters and calculates 'busy_time'
* and 'total_time'. To protect from overflow, the values are shifted right
* by 10. After read out the counters are setup to count again.
*/
static int exynos5_dmc_get_status(struct device *dev,
struct devfreq_dev_status *stat)
{
struct exynos5_dmc *dmc = dev_get_drvdata(dev);
unsigned long load, total;
int ret;
if (dmc->in_irq_mode) {
mutex_lock(&dmc->lock);
stat->current_frequency = dmc->curr_rate;
mutex_unlock(&dmc->lock);
stat->busy_time = dmc->load;
stat->total_time = dmc->total;
} else {
ret = exynos5_counters_get(dmc, &load, &total);
if (ret < 0)
return -EINVAL;
/* To protect from overflow, divide by 1024 */
stat->busy_time = load >> 10;
stat->total_time = total >> 10;
ret = exynos5_counters_set_event(dmc);
if (ret < 0) {
dev_err(dev, "could not set event counter\n");
return ret;
}
}
return 0;
}
/**
* exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
* @dev: device for which the framework checks operating frequency
* @freq: returned frequency value
*
* It returns the currently used frequency of the DMC. The real operating
* frequency might be lower when the clock source value could not be divided
* to the requested value.
*/
static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq)
{
struct exynos5_dmc *dmc = dev_get_drvdata(dev);
mutex_lock(&dmc->lock);
*freq = dmc->curr_rate;
mutex_unlock(&dmc->lock);
return 0;
}
/*
* exynos5_dmc_df_profile - Devfreq governor's profile structure
*
* It provides to the devfreq framework needed functions and polling period.
*/
static struct devfreq_dev_profile exynos5_dmc_df_profile = {
.timer = DEVFREQ_TIMER_DELAYED,
.target = exynos5_dmc_target,
.get_dev_status = exynos5_dmc_get_status,
.get_cur_freq = exynos5_dmc_get_cur_freq,
};
/**
* exynos5_dmc_align_init_freq() - Align initial frequency value
* @dmc: device for which the frequency is going to be set
* @bootloader_init_freq: initial frequency set by the bootloader in KHz
*
* The initial bootloader frequency, which is present during boot, might be
* different that supported frequency values in the driver. It is possible
* due to different PLL settings or used PLL as a source.
* This function provides the 'initial_freq' for the devfreq framework
* statistics engine which supports only registered values. Thus, some alignment
* must be made.
*/
static unsigned long
exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
unsigned long bootloader_init_freq)
{
unsigned long aligned_freq;
int idx;
idx = find_target_freq_idx(dmc, bootloader_init_freq);
if (idx >= 0)
aligned_freq = dmc->opp[idx].freq_hz;
else
aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
return aligned_freq;
}
/**
* create_timings_aligned() - Create register values and align with standard
* @dmc: device for which the frequency is going to be set
* @reg_timing_row: array to fill with values for timing row register
* @reg_timing_data: array to fill with values for timing data register
* @reg_timing_power: array to fill with values for timing power register
* @clk_period_ps: the period of the clock, known as tCK
*
* The function calculates timings and creates a register value ready for
* a frequency transition. The register contains a few timings. They are
* shifted by a known offset. The timing value is calculated based on memory
* specyfication: minimal time required and minimal cycles required.
*/
static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
u32 *reg_timing_data, u32 *reg_timing_power,
u32 clk_period_ps)
{
u32 val;
const struct timing_reg *reg;
if (clk_period_ps == 0)
return -EINVAL;
*reg_timing_row = 0;
*reg_timing_data = 0;
*reg_timing_power = 0;
val = dmc->timings->tRFC / clk_period_ps;
val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRFC);
reg = &timing_row_reg_fields[0];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRRD / clk_period_ps;
val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRRD);
reg = &timing_row_reg_fields[1];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRPab / clk_period_ps;
val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRPab);
reg = &timing_row_reg_fields[2];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRCD / clk_period_ps;
val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRCD);
reg = &timing_row_reg_fields[3];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRC / clk_period_ps;
val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRC);
reg = &timing_row_reg_fields[4];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRAS / clk_period_ps;
val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRAS);
reg = &timing_row_reg_fields[5];
*reg_timing_row |= TIMING_VAL2REG(reg, val);
/* data related timings */
val = dmc->timings->tWTR / clk_period_ps;
val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWTR);
reg = &timing_data_reg_fields[0];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tWR / clk_period_ps;
val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWR);
reg = &timing_data_reg_fields[1];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRTP / clk_period_ps;
val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRTP);
reg = &timing_data_reg_fields[2];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tW2W_C2C / clk_period_ps;
val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tW2W_C2C);
reg = &timing_data_reg_fields[3];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tR2R_C2C / clk_period_ps;
val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tR2R_C2C);
reg = &timing_data_reg_fields[4];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tWL / clk_period_ps;
val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tWL);
reg = &timing_data_reg_fields[5];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tDQSCK / clk_period_ps;
val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tDQSCK);
reg = &timing_data_reg_fields[6];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tRL / clk_period_ps;
val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tRL);
reg = &timing_data_reg_fields[7];
*reg_timing_data |= TIMING_VAL2REG(reg, val);
/* power related timings */
val = dmc->timings->tFAW / clk_period_ps;
val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tFAW);
reg = &timing_power_reg_fields[0];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tXSR / clk_period_ps;
val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tXSR);
reg = &timing_power_reg_fields[1];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tXP / clk_period_ps;
val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tXP);
reg = &timing_power_reg_fields[2];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tCKE / clk_period_ps;
val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tCKE);
reg = &timing_power_reg_fields[3];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
val = dmc->timings->tMRD / clk_period_ps;
val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
val = max(val, dmc->min_tck->tMRD);
reg = &timing_power_reg_fields[4];
*reg_timing_power |= TIMING_VAL2REG(reg, val);
return 0;
}
/**
* of_get_dram_timings() - helper function for parsing DT settings for DRAM
* @dmc: device for which the frequency is going to be set
*
* The function parses DT entries with DRAM information.
*/
static int of_get_dram_timings(struct exynos5_dmc *dmc)
{
int ret = 0;
int idx;
struct device_node *np_ddr;
u32 freq_mhz, clk_period_ps;
np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
if (!np_ddr) {
dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
return -EINVAL;
}
dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
sizeof(u32), GFP_KERNEL);
if (!dmc->timing_row) {
ret = -ENOMEM;
goto put_node;
}
dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
sizeof(u32), GFP_KERNEL);
if (!dmc->timing_data) {
ret = -ENOMEM;
goto put_node;
}
dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
sizeof(u32), GFP_KERNEL);
if (!dmc->timing_power) {
ret = -ENOMEM;
goto put_node;
}
dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
DDR_TYPE_LPDDR3,
&dmc->timings_arr_size);
if (!dmc->timings) {
dev_warn(dmc->dev, "could not get timings from DT\n");
ret = -EINVAL;
goto put_node;
}
dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
if (!dmc->min_tck) {
dev_warn(dmc->dev, "could not get tck from DT\n");
ret = -EINVAL;
goto put_node;
}
/* Sorted array of OPPs with frequency ascending */
for (idx = 0; idx < dmc->opp_count; idx++) {
freq_mhz = dmc->opp[idx].freq_hz / 1000000;
clk_period_ps = 1000000 / freq_mhz;
ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
&dmc->timing_data[idx],
&dmc->timing_power[idx],
clk_period_ps);
}
/* Take the highest frequency's timings as 'bypass' */
dmc->bypass_timing_row = dmc->timing_row[idx - 1];
dmc->bypass_timing_data = dmc->timing_data[idx - 1];
dmc->bypass_timing_power = dmc->timing_power[idx - 1];
put_node:
of_node_put(np_ddr);
return ret;
}
/**
* exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
* @dmc: DMC structure containing needed fields
*
* Get the needed clocks defined in DT device, enable and set the right parents.
* Read current frequency and initialize the initial rate for governor.
*/
static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
{
int ret;
unsigned long target_volt = 0;
unsigned long target_rate = 0;
unsigned int tmp;
dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
if (IS_ERR(dmc->fout_spll))
return PTR_ERR(dmc->fout_spll);
dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
if (IS_ERR(dmc->fout_bpll))
return PTR_ERR(dmc->fout_bpll);
dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
if (IS_ERR(dmc->mout_mclk_cdrex))
return PTR_ERR(dmc->mout_mclk_cdrex);
dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
if (IS_ERR(dmc->mout_bpll))
return PTR_ERR(dmc->mout_bpll);
dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
"mout_mx_mspll_ccore");
if (IS_ERR(dmc->mout_mx_mspll_ccore))
return PTR_ERR(dmc->mout_mx_mspll_ccore);
dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
if (IS_ERR(dmc->mout_spll)) {
dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
if (IS_ERR(dmc->mout_spll))
return PTR_ERR(dmc->mout_spll);
}
/*
* Convert frequency to KHz values and set it for the governor.
*/
dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
&target_volt, 0);
if (ret)
return ret;
dmc->curr_volt = target_volt;
ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
if (ret)
return ret;
clk_prepare_enable(dmc->fout_bpll);
clk_prepare_enable(dmc->mout_bpll);
/*
* Some bootloaders do not set clock routes correctly.
* Stop one path in clocks to PHY.
*/
regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp);
tmp &= ~(BIT(1) | BIT(0));
regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp);
return 0;
}
/**
* exynos5_performance_counters_init() - Initializes performance DMC's counters
* @dmc: DMC for which it does the setup
*
* Initialization of performance counters in DMC for estimating usage.
* The counter's values are used for calculation of a memory bandwidth and based
* on that the governor changes the frequency.
* The counters are not used when the governor is GOVERNOR_USERSPACE.
*/
static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
{
int ret, i;
dmc->num_counters = devfreq_event_get_edev_count(dmc->dev,
"devfreq-events");
if (dmc->num_counters < 0) {
dev_err(dmc->dev, "could not get devfreq-event counters\n");
return dmc->num_counters;
}
dmc->counter = devm_kcalloc(dmc->dev, dmc->num_counters,
sizeof(*dmc->counter), GFP_KERNEL);
if (!dmc->counter)
return -ENOMEM;
for (i = 0; i < dmc->num_counters; i++) {
dmc->counter[i] =
devfreq_event_get_edev_by_phandle(dmc->dev,
"devfreq-events", i);
if (IS_ERR_OR_NULL(dmc->counter[i]))
return -EPROBE_DEFER;
}
ret = exynos5_counters_enable_edev(dmc);
if (ret < 0) {
dev_err(dmc->dev, "could not enable event counter\n");
return ret;
}
ret = exynos5_counters_set_event(dmc);
if (ret < 0) {
exynos5_counters_disable_edev(dmc);
dev_err(dmc->dev, "could not set event counter\n");
return ret;
}
return 0;
}
/**
* exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
* @dmc: device which is used for changing this feature
*
* There is a need of pausing DREX DMC when divider or MUX in clock tree
* changes its configuration. In such situation access to the memory is blocked
* in DMC automatically. This feature is used when clock frequency change
* request appears and touches clock tree.
*/
static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
{
unsigned int val;
int ret;
ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
if (ret)
return ret;
val |= 1UL;
regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
return 0;
}
static irqreturn_t dmc_irq_thread(int irq, void *priv)
{
int res;
struct exynos5_dmc *dmc = priv;
mutex_lock(&dmc->df->lock);
exynos5_dmc_perf_events_check(dmc);
res = update_devfreq(dmc->df);
mutex_unlock(&dmc->df->lock);
if (res)
dev_warn(dmc->dev, "devfreq failed with %d\n", res);
return IRQ_HANDLED;
}
/**
* exynos5_dmc_probe() - Probe function for the DMC driver
* @pdev: platform device for which the driver is going to be initialized
*
* Initialize basic components: clocks, regulators, performance counters, etc.
* Read out product version and based on the information setup
* internal structures for the controller (frequency and voltage) and for DRAM
* memory parameters: timings for each operating frequency.
* Register new devfreq device for controlling DVFS of the DMC.
*/
static int exynos5_dmc_probe(struct platform_device *pdev)
{
int ret = 0;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct exynos5_dmc *dmc;
int irq[2];
dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
if (!dmc)
return -ENOMEM;
mutex_init(&dmc->lock);
dmc->dev = dev;
platform_set_drvdata(pdev, dmc);
dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dmc->base_drexi0))
return PTR_ERR(dmc->base_drexi0);
dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(dmc->base_drexi1))
return PTR_ERR(dmc->base_drexi1);
dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
"samsung,syscon-clk");
if (IS_ERR(dmc->clk_regmap))
return PTR_ERR(dmc->clk_regmap);
ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
if (ret) {
dev_warn(dev, "couldn't initialize frequency settings\n");
return ret;
}
dmc->vdd_mif = devm_regulator_get(dev, "vdd");
if (IS_ERR(dmc->vdd_mif)) {
ret = PTR_ERR(dmc->vdd_mif);
return ret;
}
ret = exynos5_dmc_init_clks(dmc);
if (ret)
return ret;
ret = of_get_dram_timings(dmc);
if (ret) {
dev_warn(dev, "couldn't initialize timings settings\n");
goto remove_clocks;
}
ret = exynos5_dmc_set_pause_on_switching(dmc);
if (ret) {
dev_warn(dev, "couldn't get access to PAUSE register\n");
goto remove_clocks;
}
/* There is two modes in which the driver works: polling or IRQ */
irq[0] = platform_get_irq_byname(pdev, "drex_0");
irq[1] = platform_get_irq_byname(pdev, "drex_1");
if (irq[0] > 0 && irq[1] > 0 && irqmode) {
ret = devm_request_threaded_irq(dev, irq[0], NULL,
dmc_irq_thread, IRQF_ONESHOT,
dev_name(dev), dmc);
if (ret) {
dev_err(dev, "couldn't grab IRQ\n");
goto remove_clocks;
}
ret = devm_request_threaded_irq(dev, irq[1], NULL,
dmc_irq_thread, IRQF_ONESHOT,
dev_name(dev), dmc);
if (ret) {
dev_err(dev, "couldn't grab IRQ\n");
goto remove_clocks;
}
/*
* Setup default thresholds for the devfreq governor.
* The values are chosen based on experiments.
*/
dmc->gov_data.upthreshold = 55;
dmc->gov_data.downdifferential = 5;
exynos5_dmc_enable_perf_events(dmc);
dmc->in_irq_mode = 1;
} else {
ret = exynos5_performance_counters_init(dmc);
if (ret) {
dev_warn(dev, "couldn't probe performance counters\n");
goto remove_clocks;
}
/*
* Setup default thresholds for the devfreq governor.
* The values are chosen based on experiments.
*/
dmc->gov_data.upthreshold = 10;
dmc->gov_data.downdifferential = 5;
exynos5_dmc_df_profile.polling_ms = 100;
}
dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
DEVFREQ_GOV_SIMPLE_ONDEMAND,
&dmc->gov_data);
if (IS_ERR(dmc->df)) {
ret = PTR_ERR(dmc->df);
goto err_devfreq_add;
}
if (dmc->in_irq_mode)
exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode);
return 0;
err_devfreq_add:
if (dmc->in_irq_mode)
exynos5_dmc_disable_perf_events(dmc);
else
exynos5_counters_disable_edev(dmc);
remove_clocks:
clk_disable_unprepare(dmc->mout_bpll);
clk_disable_unprepare(dmc->fout_bpll);
return ret;
}
/**
* exynos5_dmc_remove() - Remove function for the platform device
* @pdev: platform device which is going to be removed
*
* The function relies on 'devm' framework function which automatically
* clean the device's resources. It just calls explicitly disable function for
* the performance counters.
*/
static int exynos5_dmc_remove(struct platform_device *pdev)
{
struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
if (dmc->in_irq_mode)
exynos5_dmc_disable_perf_events(dmc);
else
exynos5_counters_disable_edev(dmc);
clk_disable_unprepare(dmc->mout_bpll);
clk_disable_unprepare(dmc->fout_bpll);
return 0;
}
static const struct of_device_id exynos5_dmc_of_match[] = {
{ .compatible = "samsung,exynos5422-dmc", },
{ },
};
MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);
static struct platform_driver exynos5_dmc_platdrv = {
.probe = exynos5_dmc_probe,
.remove = exynos5_dmc_remove,
.driver = {
.name = "exynos5-dmc",
.of_match_table = exynos5_dmc_of_match,
},
};
module_platform_driver(exynos5_dmc_platdrv);
MODULE_DESCRIPTION("Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lukasz Luba");
|
linux-master
|
drivers/memory/samsung/exynos5422-dmc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Tegra20 External Memory Controller driver
*
* Author: Dmitry Osipenko <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/devfreq.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <linux/types.h>
#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
#include "../jedec_ddr.h"
#include "../of_memory.h"
#include "mc.h"
#define EMC_INTSTATUS 0x000
#define EMC_INTMASK 0x004
#define EMC_DBG 0x008
#define EMC_ADR_CFG_0 0x010
#define EMC_TIMING_CONTROL 0x028
#define EMC_RC 0x02c
#define EMC_RFC 0x030
#define EMC_RAS 0x034
#define EMC_RP 0x038
#define EMC_R2W 0x03c
#define EMC_W2R 0x040
#define EMC_R2P 0x044
#define EMC_W2P 0x048
#define EMC_RD_RCD 0x04c
#define EMC_WR_RCD 0x050
#define EMC_RRD 0x054
#define EMC_REXT 0x058
#define EMC_WDV 0x05c
#define EMC_QUSE 0x060
#define EMC_QRST 0x064
#define EMC_QSAFE 0x068
#define EMC_RDV 0x06c
#define EMC_REFRESH 0x070
#define EMC_BURST_REFRESH_NUM 0x074
#define EMC_PDEX2WR 0x078
#define EMC_PDEX2RD 0x07c
#define EMC_PCHG2PDEN 0x080
#define EMC_ACT2PDEN 0x084
#define EMC_AR2PDEN 0x088
#define EMC_RW2PDEN 0x08c
#define EMC_TXSR 0x090
#define EMC_TCKE 0x094
#define EMC_TFAW 0x098
#define EMC_TRPAB 0x09c
#define EMC_TCLKSTABLE 0x0a0
#define EMC_TCLKSTOP 0x0a4
#define EMC_TREFBW 0x0a8
#define EMC_QUSE_EXTRA 0x0ac
#define EMC_ODT_WRITE 0x0b0
#define EMC_ODT_READ 0x0b4
#define EMC_MRR 0x0ec
#define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG6 0x114
#define EMC_STAT_CONTROL 0x160
#define EMC_STAT_LLMC_CONTROL 0x178
#define EMC_STAT_PWR_CLOCK_LIMIT 0x198
#define EMC_STAT_PWR_CLOCKS 0x19c
#define EMC_STAT_PWR_COUNT 0x1a0
#define EMC_AUTO_CAL_INTERVAL 0x2a8
#define EMC_CFG_2 0x2b8
#define EMC_CFG_DIG_DLL 0x2bc
#define EMC_DLL_XFORM_DQS 0x2c0
#define EMC_DLL_XFORM_QUSE 0x2c4
#define EMC_ZCAL_REF_CNT 0x2e0
#define EMC_ZCAL_WAIT_CNT 0x2e4
#define EMC_CFG_CLKTRIM_0 0x2d0
#define EMC_CFG_CLKTRIM_1 0x2d4
#define EMC_CFG_CLKTRIM_2 0x2d8
#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
#define EMC_TIMING_UPDATE BIT(0)
#define EMC_REFRESH_OVERFLOW_INT BIT(3)
#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
#define EMC_MRR_DIVLD_INT BIT(5)
#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
#define EMC_DBG_FORCE_UPDATE BIT(2)
#define EMC_DBG_READ_DQM_CTRL BIT(9)
#define EMC_DBG_CFG_PRIORITY BIT(24)
#define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4)
#define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0)
#define EMC_MRR_DEV_SELECTN GENMASK(31, 30)
#define EMC_MRR_MRR_MA GENMASK(23, 16)
#define EMC_MRR_MRR_DATA GENMASK(15, 0)
#define EMC_ADR_CFG_0_EMEM_NUMDEV GENMASK(25, 24)
#define EMC_PWR_GATHER_CLEAR (1 << 8)
#define EMC_PWR_GATHER_DISABLE (2 << 8)
#define EMC_PWR_GATHER_ENABLE (3 << 8)
enum emc_dram_type {
DRAM_TYPE_RESERVED,
DRAM_TYPE_DDR1,
DRAM_TYPE_LPDDR2,
DRAM_TYPE_DDR2,
};
static const u16 emc_timing_registers[] = {
EMC_RC,
EMC_RFC,
EMC_RAS,
EMC_RP,
EMC_R2W,
EMC_W2R,
EMC_R2P,
EMC_W2P,
EMC_RD_RCD,
EMC_WR_RCD,
EMC_RRD,
EMC_REXT,
EMC_WDV,
EMC_QUSE,
EMC_QRST,
EMC_QSAFE,
EMC_RDV,
EMC_REFRESH,
EMC_BURST_REFRESH_NUM,
EMC_PDEX2WR,
EMC_PDEX2RD,
EMC_PCHG2PDEN,
EMC_ACT2PDEN,
EMC_AR2PDEN,
EMC_RW2PDEN,
EMC_TXSR,
EMC_TCKE,
EMC_TFAW,
EMC_TRPAB,
EMC_TCLKSTABLE,
EMC_TCLKSTOP,
EMC_TREFBW,
EMC_QUSE_EXTRA,
EMC_FBIO_CFG6,
EMC_ODT_WRITE,
EMC_ODT_READ,
EMC_FBIO_CFG5,
EMC_CFG_DIG_DLL,
EMC_DLL_XFORM_DQS,
EMC_DLL_XFORM_QUSE,
EMC_ZCAL_REF_CNT,
EMC_ZCAL_WAIT_CNT,
EMC_AUTO_CAL_INTERVAL,
EMC_CFG_CLKTRIM_0,
EMC_CFG_CLKTRIM_1,
EMC_CFG_CLKTRIM_2,
};
struct emc_timing {
unsigned long rate;
u32 data[ARRAY_SIZE(emc_timing_registers)];
};
enum emc_rate_request_type {
EMC_RATE_DEVFREQ,
EMC_RATE_DEBUG,
EMC_RATE_ICC,
EMC_RATE_TYPE_MAX,
};
struct emc_rate_request {
unsigned long min_rate;
unsigned long max_rate;
};
struct tegra_emc {
struct device *dev;
struct tegra_mc *mc;
struct icc_provider provider;
struct notifier_block clk_nb;
struct clk *clk;
void __iomem *regs;
unsigned int dram_bus_width;
struct emc_timing *timings;
unsigned int num_timings;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
/*
* There are multiple sources in the EMC driver which could request
* a min/max clock rate, these rates are contained in this array.
*/
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
/* protect shared rate-change code path */
struct mutex rate_lock;
struct devfreq_simple_ondemand_data ondemand_data;
/* memory chip identity information */
union lpddr2_basic_config4 basic_conf4;
unsigned int manufacturer_id;
unsigned int revision_id1;
unsigned int revision_id2;
bool mrr_error;
};
static irqreturn_t tegra_emc_isr(int irq, void *data)
{
struct tegra_emc *emc = data;
u32 intmask = EMC_REFRESH_OVERFLOW_INT;
u32 status;
status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
if (!status)
return IRQ_NONE;
/* notify about HW problem */
if (status & EMC_REFRESH_OVERFLOW_INT)
dev_err_ratelimited(emc->dev,
"refresh request overflow timeout\n");
/* clear interrupts */
writel_relaxed(status, emc->regs + EMC_INTSTATUS);
return IRQ_HANDLED;
}
static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = NULL;
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate >= rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu\n", rate);
return NULL;
}
return timing;
}
static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
unsigned int i;
if (!timing)
return -EINVAL;
dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
__func__, timing->rate, rate);
/* program shadow registers */
for (i = 0; i < ARRAY_SIZE(timing->data); i++)
writel_relaxed(timing->data[i],
emc->regs + emc_timing_registers[i]);
/* wait until programming has settled */
readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
return 0;
}
static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
{
int err;
u32 v;
dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
if (flush) {
/* manually initiate memory timing update */
writel_relaxed(EMC_TIMING_UPDATE,
emc->regs + EMC_TIMING_CONTROL);
return 0;
}
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
v & EMC_CLKCHANGE_COMPLETE_INT,
1, 100);
if (err) {
dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
return err;
}
return 0;
}
static int tegra_emc_clk_change_notify(struct notifier_block *nb,
unsigned long msg, void *data)
{
struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
struct clk_notifier_data *cnd = data;
int err;
switch (msg) {
case PRE_RATE_CHANGE:
err = emc_prepare_timing_change(emc, cnd->new_rate);
break;
case ABORT_RATE_CHANGE:
err = emc_prepare_timing_change(emc, cnd->old_rate);
if (err)
break;
err = emc_complete_timing_change(emc, true);
break;
case POST_RATE_CHANGE:
err = emc_complete_timing_change(emc, false);
break;
default:
return NOTIFY_DONE;
}
return notifier_from_errno(err);
}
static int load_one_timing_from_dt(struct tegra_emc *emc,
struct emc_timing *timing,
struct device_node *node)
{
u32 rate;
int err;
if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
return -EINVAL;
}
err = of_property_read_u32(node, "clock-frequency", &rate);
if (err) {
dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
node, err);
return err;
}
err = of_property_read_u32_array(node, "nvidia,emc-registers",
timing->data,
ARRAY_SIZE(emc_timing_registers));
if (err) {
dev_err(emc->dev,
"timing %pOF: failed to read emc timing data: %d\n",
node, err);
return err;
}
/*
* The EMC clock rate is twice the bus rate, and the bus rate is
* measured in kHz.
*/
timing->rate = rate * 2 * 1000;
dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
__func__, node, timing->rate);
return 0;
}
static int cmp_timings(const void *_a, const void *_b)
{
const struct emc_timing *a = _a;
const struct emc_timing *b = _b;
if (a->rate < b->rate)
return -1;
if (a->rate > b->rate)
return 1;
return 0;
}
static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
struct device_node *node)
{
struct device_node *child;
struct emc_timing *timing;
int child_count;
int err;
child_count = of_get_child_count(node);
if (!child_count) {
dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
return -EINVAL;
}
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!emc->timings)
return -ENOMEM;
timing = emc->timings;
for_each_child_of_node(node, child) {
if (of_node_name_eq(child, "lpddr2"))
continue;
err = load_one_timing_from_dt(emc, timing++, child);
if (err) {
of_node_put(child);
return err;
}
emc->num_timings++;
}
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
NULL);
dev_info_once(emc->dev,
"got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
emc->num_timings,
tegra_read_ram_code(),
emc->timings[0].rate / 1000000,
emc->timings[emc->num_timings - 1].rate / 1000000);
return 0;
}
static struct device_node *
tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
{
struct device *dev = emc->dev;
struct device_node *np;
u32 value, ram_code;
int err;
if (emc->mrr_error) {
dev_warn(dev, "memory timings skipped due to MRR error\n");
return NULL;
}
if (of_get_child_count(dev->of_node) == 0) {
dev_info_once(dev, "device-tree doesn't have memory timings\n");
return NULL;
}
if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
return of_node_get(dev->of_node);
ram_code = tegra_read_ram_code();
for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
np = of_find_node_by_name(np, "emc-tables")) {
err = of_property_read_u32(np, "nvidia,ram-code", &value);
if (err || value != ram_code) {
struct device_node *lpddr2_np;
bool cfg_mismatches = false;
lpddr2_np = of_find_node_by_name(np, "lpddr2");
if (lpddr2_np) {
const struct lpddr2_info *info;
info = of_lpddr2_get_info(lpddr2_np, dev);
if (info) {
if (info->manufacturer_id >= 0 &&
info->manufacturer_id != emc->manufacturer_id)
cfg_mismatches = true;
if (info->revision_id1 >= 0 &&
info->revision_id1 != emc->revision_id1)
cfg_mismatches = true;
if (info->revision_id2 >= 0 &&
info->revision_id2 != emc->revision_id2)
cfg_mismatches = true;
if (info->density != emc->basic_conf4.density)
cfg_mismatches = true;
if (info->io_width != emc->basic_conf4.io_width)
cfg_mismatches = true;
if (info->arch_type != emc->basic_conf4.arch_type)
cfg_mismatches = true;
} else {
dev_err(dev, "failed to parse %pOF\n", lpddr2_np);
cfg_mismatches = true;
}
of_node_put(lpddr2_np);
} else {
cfg_mismatches = true;
}
if (cfg_mismatches) {
of_node_put(np);
continue;
}
}
return np;
}
dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
ram_code);
return NULL;
}
static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
unsigned int emem_dev,
unsigned int register_addr,
unsigned int *register_data)
{
u32 memory_dev = emem_dev ? 1 : 2;
u32 val, mr_mask = 0xff;
int err;
/* clear data-valid interrupt status */
writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
/* issue mode register read request */
val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev);
val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr);
writel_relaxed(val, emc->regs + EMC_MRR);
/* wait for the LPDDR2 data-valid interrupt */
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
val & EMC_MRR_DIVLD_INT,
1, 100);
if (err) {
dev_err(emc->dev, "mode register %u read failed: %d\n",
register_addr, err);
emc->mrr_error = true;
return err;
}
/* read out mode register data */
val = readl_relaxed(emc->regs + EMC_MRR);
*register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask;
return 0;
}
static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
unsigned int emem_dev,
bool print_out)
{
/* these registers are standard for all LPDDR JEDEC memory chips */
emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id);
emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1);
emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2);
emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value);
if (!print_out)
return;
dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
emem_dev, emc->manufacturer_id,
lpddr2_jedec_manufacturer(emc->manufacturer_id),
emc->revision_id1, emc->revision_id2,
4 >> emc->basic_conf4.arch_type,
64 << emc->basic_conf4.density,
32 >> emc->basic_conf4.io_width);
}
static int emc_setup_hw(struct tegra_emc *emc)
{
u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg;
u32 intmask = EMC_REFRESH_OVERFLOW_INT;
static bool print_sdram_info_once;
enum emc_dram_type dram_type;
const char *dram_type_str;
unsigned int emem_numdev;
emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
/*
* Depending on a memory type, DRAM should enter either self-refresh
* or power-down state on EMC clock change.
*/
if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
!(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
dev_err(emc->dev,
"bootloader didn't specify DRAM auto-suspend mode\n");
return -EINVAL;
}
/* enable EMC and CAR to handshake on PLL divider/source changes */
emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
/* initialize interrupt */
writel_relaxed(intmask, emc->regs + EMC_INTMASK);
writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
/* ensure that unwanted debug features are disabled */
emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
emc_dbg |= EMC_DBG_CFG_PRIORITY;
emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16)
emc->dram_bus_width = 16;
else
emc->dram_bus_width = 32;
dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio);
switch (dram_type) {
case DRAM_TYPE_RESERVED:
dram_type_str = "INVALID";
break;
case DRAM_TYPE_DDR1:
dram_type_str = "DDR1";
break;
case DRAM_TYPE_LPDDR2:
dram_type_str = "LPDDR2";
break;
case DRAM_TYPE_DDR2:
dram_type_str = "DDR2";
break;
}
emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0);
emem_numdev = FIELD_GET(EMC_ADR_CFG_0_EMEM_NUMDEV, emc_adr_cfg) + 1;
dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n",
emc->dram_bus_width, emem_numdev, dram_type_str,
emem_numdev == 2 ? "devices" : "device");
if (dram_type == DRAM_TYPE_LPDDR2) {
while (emem_numdev--)
emc_read_lpddr_sdram_info(emc, emem_numdev,
!print_sdram_info_once);
print_sdram_info_once = true;
}
return 0;
}
static long emc_round_rate(unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
void *arg)
{
struct emc_timing *timing = NULL;
struct tegra_emc *emc = arg;
unsigned int i;
if (!emc->num_timings)
return clk_get_rate(emc->clk);
min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
continue;
if (emc->timings[i].rate > max_rate) {
i = max(i, 1u) - 1;
if (emc->timings[i].rate < min_rate)
break;
}
if (emc->timings[i].rate < min_rate)
continue;
timing = &emc->timings[i];
break;
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
rate, min_rate, max_rate);
return -EINVAL;
}
return timing->rate;
}
static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
{
unsigned int i;
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
emc->requested_rate[i].min_rate = 0;
emc->requested_rate[i].max_rate = ULONG_MAX;
}
}
static int emc_request_rate(struct tegra_emc *emc,
unsigned long new_min_rate,
unsigned long new_max_rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = emc->requested_rate;
unsigned long min_rate = 0, max_rate = ULONG_MAX;
unsigned int i;
int err;
/* select minimum and maximum rates among the requested rates */
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
if (i == type) {
min_rate = max(new_min_rate, min_rate);
max_rate = min(new_max_rate, max_rate);
} else {
min_rate = max(req->min_rate, min_rate);
max_rate = min(req->max_rate, max_rate);
}
}
if (min_rate > max_rate) {
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
__func__, type, min_rate, max_rate);
return -ERANGE;
}
/*
* EMC rate-changes should go via OPP API because it manages voltage
* changes.
*/
err = dev_pm_opp_set_rate(emc->dev, min_rate);
if (err)
return err;
emc->requested_rate[type].min_rate = new_min_rate;
emc->requested_rate[type].max_rate = new_max_rate;
return 0;
}
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, rate, req->max_rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, req->min_rate, rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (rate == emc->timings[i].rate)
return true;
return false;
}
static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
{
struct tegra_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
tegra_emc_debug_min_rate_get,
tegra_emc_debug_min_rate_set, "%llu\n");
static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
tegra_emc_debug_max_rate_get,
tegra_emc_debug_max_rate_set, "%llu\n");
static void tegra_emc_debugfs_init(struct tegra_emc *emc)
{
struct device *dev = emc->dev;
unsigned int i;
int err;
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->timings[i].rate;
if (emc->timings[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->timings[i].rate;
}
if (!emc->num_timings) {
emc->debugfs.min_rate = clk_get_rate(emc->clk);
emc->debugfs.max_rate = emc->debugfs.min_rate;
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root,
emc, &tegra_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_max_rate_fops);
}
static inline struct tegra_emc *
to_tegra_emc_provider(struct icc_provider *provider)
{
return container_of(provider, struct tegra_emc, provider);
}
static struct icc_node_data *
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct icc_provider *provider = data;
struct icc_node_data *ndata;
struct icc_node *node;
/* External Memory is the only possible ICC route */
list_for_each_entry(node, &provider->nodes, node_list) {
if (node->id != TEGRA_ICC_EMEM)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
/*
* SRC and DST nodes should have matching TAG in order to have
* it set by default for a requested path.
*/
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
ndata->node = node;
return ndata;
}
return ERR_PTR(-EPROBE_DEFER);
}
static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
unsigned long long rate = max(avg_bw, peak_bw);
unsigned int dram_data_bus_width_bytes;
int err;
/*
* Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data
* is sampled on both clock edges. This means that EMC clock rate
* equals to the peak data-rate.
*/
dram_data_bus_width_bytes = emc->dram_bus_width / 8;
do_div(rate, dram_data_bus_width_bytes);
rate = min_t(u64, rate, U32_MAX);
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
if (err)
return err;
return 0;
}
static int tegra_emc_interconnect_init(struct tegra_emc *emc)
{
const struct tegra_mc_soc *soc;
struct icc_node *node;
int err;
emc->mc = devm_tegra_memory_controller_get(emc->dev);
if (IS_ERR(emc->mc))
return PTR_ERR(emc->mc);
soc = emc->mc->soc;
emc->provider.dev = emc->dev;
emc->provider.set = emc_icc_set;
emc->provider.data = &emc->provider;
emc->provider.aggregate = soc->icc_ops->aggregate;
emc->provider.xlate_extended = emc_of_icc_xlate_extended;
icc_provider_init(&emc->provider);
/* create External Memory Controller node */
node = icc_node_create(TEGRA_ICC_EMC);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto err_msg;
}
node->name = "External Memory Controller";
icc_node_add(node, &emc->provider);
/* link External Memory Controller to External Memory (DRAM) */
err = icc_link_create(node, TEGRA_ICC_EMEM);
if (err)
goto remove_nodes;
/* create External Memory node */
node = icc_node_create(TEGRA_ICC_EMEM);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = "External Memory (DRAM)";
icc_node_add(node, &emc->provider);
err = icc_provider_register(&emc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&emc->provider);
err_msg:
dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
return err;
}
static void devm_tegra_emc_unset_callback(void *data)
{
tegra20_clk_set_emc_round_callback(NULL, NULL);
}
static void devm_tegra_emc_unreg_clk_notifier(void *data)
{
struct tegra_emc *emc = data;
clk_notifier_unregister(emc->clk, &emc->clk_nb);
}
static int tegra_emc_init_clk(struct tegra_emc *emc)
{
int err;
tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
NULL);
if (err)
return err;
emc->clk = devm_clk_get(emc->dev, NULL);
if (IS_ERR(emc->clk)) {
dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
return PTR_ERR(emc->clk);
}
err = clk_notifier_register(emc->clk, &emc->clk_nb);
if (err) {
dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
return err;
}
err = devm_add_action_or_reset(emc->dev,
devm_tegra_emc_unreg_clk_notifier, emc);
if (err)
return err;
return 0;
}
static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq,
u32 flags)
{
struct tegra_emc *emc = dev_get_drvdata(dev);
struct dev_pm_opp *opp;
unsigned long rate;
opp = devfreq_recommended_opp(dev, freq, flags);
if (IS_ERR(opp)) {
dev_err(dev, "failed to find opp for %lu Hz\n", *freq);
return PTR_ERR(opp);
}
rate = dev_pm_opp_get_freq(opp);
dev_pm_opp_put(opp);
return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
}
static int tegra_emc_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *stat)
{
struct tegra_emc *emc = dev_get_drvdata(dev);
/* freeze counters */
writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
/*
* busy_time: number of clocks EMC request was accepted
* total_time: number of clocks PWR_GATHER control was set to ENABLE
*/
stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
stat->current_frequency = clk_get_rate(emc->clk);
/* clear counters and restart */
writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
return 0;
}
static struct devfreq_dev_profile tegra_emc_devfreq_profile = {
.polling_ms = 30,
.target = tegra_emc_devfreq_target,
.get_dev_status = tegra_emc_devfreq_get_dev_status,
};
static int tegra_emc_devfreq_init(struct tegra_emc *emc)
{
struct devfreq *devfreq;
/*
* PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold
* should be less than 50. Secondly, multiple active memory clients
* may cause over 20% of lost clock cycles due to stalls caused by
* competing memory accesses. This means that threshold should be
* set to a less than 30 in order to have a properly working governor.
*/
emc->ondemand_data.upthreshold = 20;
/*
* Reset statistic gathers state, select global bandwidth for the
* statistics collection mode and set clocks counter saturation
* limit to maximum.
*/
writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
DEVFREQ_GOV_SIMPLE_ONDEMAND,
&emc->ondemand_data);
if (IS_ERR(devfreq)) {
dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
return PTR_ERR(devfreq);
}
return 0;
}
static int tegra_emc_probe(struct platform_device *pdev)
{
struct tegra_core_opp_params opp_params = {};
struct device_node *np;
struct tegra_emc *emc;
int irq, err;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "please update your device tree\n");
return irq;
}
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
mutex_init(&emc->rate_lock);
emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
emc->dev = &pdev->dev;
emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
err = emc_setup_hw(emc);
if (err)
return err;
np = tegra_emc_find_node_by_ram_code(emc);
if (np) {
err = tegra_emc_load_timings_from_dt(emc, np);
of_node_put(np);
if (err)
return err;
}
err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
dev_name(&pdev->dev), emc);
if (err) {
dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
return err;
}
err = tegra_emc_init_clk(emc);
if (err)
return err;
opp_params.init_state = true;
err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
if (err)
return err;
platform_set_drvdata(pdev, emc);
tegra_emc_rate_requests_init(emc);
tegra_emc_debugfs_init(emc);
tegra_emc_interconnect_init(emc);
tegra_emc_devfreq_init(emc);
/*
* Don't allow the kernel module to be unloaded. Unloading adds some
* extra complexity which doesn't really worth the effort in a case of
* this driver.
*/
try_module_get(THIS_MODULE);
return 0;
}
static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra20-emc", },
{},
};
MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
.driver = {
.name = "tegra20-emc",
.of_match_table = tegra_emc_of_match,
.suppress_bind_attrs = true,
.sync_state = icc_sync_state,
},
};
module_platform_driver(tegra_emc_driver);
MODULE_AUTHOR("Dmitry Osipenko <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");
MODULE_SOFTDEP("pre: governor_simpleondemand");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/tegra/tegra20-emc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <soc/tegra/bpmp.h>
#include "mc.h"
struct tegra186_emc_dvfs {
unsigned long latency;
unsigned long rate;
};
struct tegra186_emc {
struct tegra_bpmp *bpmp;
struct device *dev;
struct clk *clk;
struct tegra186_emc_dvfs *dvfs;
unsigned int num_dvfs;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
struct icc_provider provider;
};
static inline struct tegra186_emc *to_tegra186_emc(struct icc_provider *provider)
{
return container_of(provider, struct tegra186_emc, provider);
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra186_emc_validate_rate(struct tegra186_emc *emc,
unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_dvfs; i++)
if (rate == emc->dvfs[i].rate)
return true;
return false;
}
static int tegra186_emc_debug_available_rates_show(struct seq_file *s,
void *data)
{
struct tegra186_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_dvfs; i++) {
seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates);
static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra186_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra186_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra186_emc *emc = data;
int err;
if (!tegra186_emc_validate_rate(emc, rate))
return -EINVAL;
err = clk_set_min_rate(emc->clk, rate);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops,
tegra186_emc_debug_min_rate_get,
tegra186_emc_debug_min_rate_set, "%llu\n");
static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra186_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra186_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra186_emc *emc = data;
int err;
if (!tegra186_emc_validate_rate(emc, rate))
return -EINVAL;
err = clk_set_max_rate(emc->clk, rate);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
tegra186_emc_debug_max_rate_get,
tegra186_emc_debug_max_rate_set, "%llu\n");
static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
{
struct mrq_emc_dvfs_latency_response response;
struct tegra_bpmp_message msg;
unsigned int i;
int err;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_EMC_DVFS_LATENCY;
msg.tx.data = NULL;
msg.tx.size = 0;
msg.rx.data = &response;
msg.rx.size = sizeof(response);
err = tegra_bpmp_transfer(emc->bpmp, &msg);
if (err < 0) {
dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
return err;
}
if (msg.rx.ret < 0) {
dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
return -EINVAL;
}
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
emc->num_dvfs = response.num_pairs;
emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
if (!emc->dvfs)
return -ENOMEM;
dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
for (i = 0; i < emc->num_dvfs; i++) {
emc->dvfs[i].rate = response.pairs[i].freq * 1000;
emc->dvfs[i].latency = response.pairs[i].latency;
if (emc->dvfs[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->dvfs[i].rate;
if (emc->dvfs[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->dvfs[i].rate;
dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
emc->dvfs[i].rate, emc->dvfs[i].latency);
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
if (err < 0) {
dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
return err;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra186_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
&tegra186_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
&tegra186_emc_debug_max_rate_fops);
return 0;
}
/*
* tegra_emc_icc_set_bw() - Set BW api for EMC provider
* @src: ICC node for External Memory Controller (EMC)
* @dst: ICC node for External Memory (DRAM)
*
* Do nothing here as info to BPMP-FW is now passed in the BW set function
* of the MC driver. BPMP-FW sets the final Freq based on the passed values.
*/
static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst)
{
return 0;
}
static struct icc_node *
tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data)
{
struct icc_provider *provider = data;
struct icc_node *node;
/* External Memory is the only possible ICC route */
list_for_each_entry(node, &provider->nodes, node_list) {
if (node->id != TEGRA_ICC_EMEM)
continue;
return node;
}
return ERR_PTR(-EPROBE_DEFER);
}
static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
{
*avg = 0;
*peak = 0;
return 0;
}
static int tegra_emc_interconnect_init(struct tegra186_emc *emc)
{
struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent);
const struct tegra_mc_soc *soc = mc->soc;
struct icc_node *node;
int err;
emc->provider.dev = emc->dev;
emc->provider.set = tegra_emc_icc_set_bw;
emc->provider.data = &emc->provider;
emc->provider.aggregate = soc->icc_ops->aggregate;
emc->provider.xlate = tegra_emc_of_icc_xlate;
emc->provider.get_bw = tegra_emc_icc_get_init_bw;
icc_provider_init(&emc->provider);
/* create External Memory Controller node */
node = icc_node_create(TEGRA_ICC_EMC);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto err_msg;
}
node->name = "External Memory Controller";
icc_node_add(node, &emc->provider);
/* link External Memory Controller to External Memory (DRAM) */
err = icc_link_create(node, TEGRA_ICC_EMEM);
if (err)
goto remove_nodes;
/* create External Memory node */
node = icc_node_create(TEGRA_ICC_EMEM);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = "External Memory (DRAM)";
icc_node_add(node, &emc->provider);
err = icc_provider_register(&emc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&emc->provider);
err_msg:
dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
return err;
}
static int tegra186_emc_probe(struct platform_device *pdev)
{
struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
struct tegra186_emc *emc;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
emc->bpmp = tegra_bpmp_get(&pdev->dev);
if (IS_ERR(emc->bpmp))
return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), "failed to get BPMP\n");
emc->clk = devm_clk_get(&pdev->dev, "emc");
if (IS_ERR(emc->clk)) {
err = PTR_ERR(emc->clk);
dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
goto put_bpmp;
}
platform_set_drvdata(pdev, emc);
emc->dev = &pdev->dev;
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
err = tegra186_emc_get_emc_dvfs_latency(emc);
if (err)
goto put_bpmp;
}
if (mc && mc->soc->icc_ops) {
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {
mc->bwmgr_mrq_supported = true;
/*
* MC driver probe can't get BPMP reference as it gets probed
* earlier than BPMP. So, save the BPMP ref got from the EMC
* DT node in the mc->bpmp and use it in MC's icc_set hook.
*/
mc->bpmp = emc->bpmp;
barrier();
}
/*
* Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'.
* Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return
* EINVAL instead of passing the request to BPMP-FW later when the BW
* request is made by client with 'icc_set_bw()' call.
*/
err = tegra_emc_interconnect_init(emc);
if (err) {
mc->bpmp = NULL;
goto put_bpmp;
}
}
return 0;
put_bpmp:
tegra_bpmp_put(emc->bpmp);
return err;
}
static int tegra186_emc_remove(struct platform_device *pdev)
{
struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
struct tegra186_emc *emc = platform_get_drvdata(pdev);
debugfs_remove_recursive(emc->debugfs.root);
mc->bpmp = NULL;
tegra_bpmp_put(emc->bpmp);
return 0;
}
static const struct of_device_id tegra186_emc_of_match[] = {
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
{ .compatible = "nvidia,tegra186-emc" },
#endif
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
{ .compatible = "nvidia,tegra194-emc" },
#endif
#if defined(CONFIG_ARCH_TEGRA_234_SOC)
{ .compatible = "nvidia,tegra234-emc" },
#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tegra186_emc_of_match);
static struct platform_driver tegra186_emc_driver = {
.driver = {
.name = "tegra186-emc",
.of_match_table = tegra186_emc_of_match,
.suppress_bind_attrs = true,
.sync_state = icc_sync_state,
},
.probe = tegra186_emc_probe,
.remove = tegra186_emc_remove,
};
module_platform_driver(tegra186_emc_driver);
MODULE_AUTHOR("Thierry Reding <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver");
|
linux-master
|
drivers/memory/tegra/tegra186-emc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
*/
#include <soc/tegra/mc.h>
#include <dt-bindings/memory/tegra194-mc.h>
#include "mc.h"
static const struct tegra_mc_client tegra194_mc_clients[] = {
{
.id = TEGRA194_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x000,
.security = 0x004,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU7R,
.name = "miu7r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x008,
.security = 0x00c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU7W,
.name = "miu7w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x010,
.security = 0x014,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA194_SID_HDA,
.regs = {
.sid = {
.override = 0x0a8,
.security = 0x0ac,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA194_SID_HOST1X,
.regs = {
.sid = {
.override = 0x0b0,
.security = 0x0b4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA194_SID_NVENC,
.regs = {
.sid = {
.override = 0x0e0,
.security = 0x0e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA194_SID_SATA,
.regs = {
.sid = {
.override = 0x0f8,
.security = 0x0fc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x138,
.security = 0x13c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.sid = TEGRA194_SID_NVENC,
.regs = {
.sid = {
.override = 0x158,
.security = 0x15c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.sid = TEGRA194_SID_HDA,
.regs = {
.sid = {
.override = 0x1a8,
.security = 0x1ac,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x1c8,
.security = 0x1cc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SATAW,
.name = "sataw",
.sid = TEGRA194_SID_SATA,
.regs = {
.sid = {
.override = 0x1e8,
.security = 0x1ec,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPRA,
.name = "ispra",
.sid = TEGRA194_SID_ISP,
.regs = {
.sid = {
.override = 0x220,
.security = 0x224,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPFALR,
.name = "ispfalr",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
.sid = {
.override = 0x228,
.security = 0x22c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPWA,
.name = "ispwa",
.sid = TEGRA194_SID_ISP,
.regs = {
.sid = {
.override = 0x230,
.security = 0x234,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPWB,
.name = "ispwb",
.sid = TEGRA194_SID_ISP,
.regs = {
.sid = {
.override = 0x238,
.security = 0x23c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
.name = "xusb_hostr",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
.sid = {
.override = 0x250,
.security = 0x254,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
.name = "xusb_hostw",
.sid = TEGRA194_SID_XUSB_HOST,
.regs = {
.sid = {
.override = 0x258,
.security = 0x25c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
.name = "xusb_devr",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
.sid = {
.override = 0x260,
.security = 0x264,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
.name = "xusb_devw",
.sid = TEGRA194_SID_XUSB_DEV,
.regs = {
.sid = {
.override = 0x268,
.security = 0x26c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
.name = "sdmmcra",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
.sid = {
.override = 0x300,
.security = 0x304,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCR,
.name = "sdmmcr",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
.sid = {
.override = 0x310,
.security = 0x314,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x318,
.security = 0x31c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
.name = "sdmmcwa",
.sid = TEGRA194_SID_SDMMC1,
.regs = {
.sid = {
.override = 0x320,
.security = 0x324,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCW,
.name = "sdmmcw",
.sid = TEGRA194_SID_SDMMC3,
.regs = {
.sid = {
.override = 0x330,
.security = 0x334,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.sid = TEGRA194_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x338,
.security = 0x33c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.sid = TEGRA194_SID_VIC,
.regs = {
.sid = {
.override = 0x360,
.security = 0x364,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.sid = TEGRA194_SID_VIC,
.regs = {
.sid = {
.override = 0x368,
.security = 0x36c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VIW,
.name = "viw",
.sid = TEGRA194_SID_VI,
.regs = {
.sid = {
.override = 0x390,
.security = 0x394,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c0,
.security = 0x3c4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c8,
.security = 0x3cc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_APER,
.name = "aper",
.sid = TEGRA194_SID_APE,
.regs = {
.sid = {
.override = 0x3c0,
.security = 0x3c4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_APEW,
.name = "apew",
.sid = TEGRA194_SID_APE,
.regs = {
.sid = {
.override = 0x3d0,
.security = 0x3d4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.sid = TEGRA194_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f0,
.security = 0x3f4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.sid = TEGRA194_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f0,
.security = 0x3f4,
},
},
}, {
.name = "axiapr",
.id = TEGRA194_MEMORY_CLIENT_AXIAPR,
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x410,
.security = 0x414,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AXIAPW,
.name = "axiapw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x418,
.security = 0x41c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ETRR,
.name = "etrr",
.sid = TEGRA194_SID_ETR,
.regs = {
.sid = {
.override = 0x420,
.security = 0x424,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ETRW,
.name = "etrw",
.sid = TEGRA194_SID_ETR,
.regs = {
.sid = {
.override = 0x428,
.security = 0x42c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AXISR,
.name = "axisr",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x460,
.security = 0x464,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AXISW,
.name = "axisw",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x468,
.security = 0x46c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_EQOSR,
.name = "eqosr",
.sid = TEGRA194_SID_EQOS,
.regs = {
.sid = {
.override = 0x470,
.security = 0x474,
},
},
}, {
.name = "eqosw",
.id = TEGRA194_MEMORY_CLIENT_EQOSW,
.sid = TEGRA194_SID_EQOS,
.regs = {
.sid = {
.override = 0x478,
.security = 0x47c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_UFSHCR,
.name = "ufshcr",
.sid = TEGRA194_SID_UFSHC,
.regs = {
.sid = {
.override = 0x480,
.security = 0x484,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_UFSHCW,
.name = "ufshcw",
.sid = TEGRA194_SID_UFSHC,
.regs = {
.sid = {
.override = 0x488,
.security = 0x48c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
.sid = {
.override = 0x490,
.security = 0x494,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA194_SID_BPMP,
.regs = {
.sid = {
.override = 0x498,
.security = 0x49c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA194_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a0,
.security = 0x4a4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA194_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a8,
.security = 0x4ac,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA194_SID_BPMP,
.regs = {
.sid = {
.override = 0x4b0,
.security = 0x4b4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AONR,
.name = "aonr",
.sid = TEGRA194_SID_AON,
.regs = {
.sid = {
.override = 0x4b8,
.security = 0x4bc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AONW,
.name = "aonw",
.sid = TEGRA194_SID_AON,
.regs = {
.sid = {
.override = 0x4c0,
.security = 0x4c4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AONDMAR,
.name = "aondmar",
.sid = TEGRA194_SID_AON,
.regs = {
.sid = {
.override = 0x4c8,
.security = 0x4cc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_AONDMAW,
.name = "aondmaw",
.sid = TEGRA194_SID_AON,
.regs = {
.sid = {
.override = 0x4d0,
.security = 0x4d4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SCER,
.name = "scer",
.sid = TEGRA194_SID_SCE,
.regs = {
.sid = {
.override = 0x4d8,
.security = 0x4dc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SCEW,
.name = "scew",
.sid = TEGRA194_SID_SCE,
.regs = {
.sid = {
.override = 0x4e0,
.security = 0x4e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
.name = "scedmar",
.sid = TEGRA194_SID_SCE,
.regs = {
.sid = {
.override = 0x4e8,
.security = 0x4ec,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
.name = "scedmaw",
.sid = TEGRA194_SID_SCE,
.regs = {
.sid = {
.override = 0x4f0,
.security = 0x4f4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.sid = TEGRA194_SID_APE,
.regs = {
.sid = {
.override = 0x4f8,
.security = 0x4fc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.sid = TEGRA194_SID_APE,
.regs = {
.sid = {
.override = 0x500,
.security = 0x504,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.sid = TEGRA194_SID_NVDISPLAY,
.regs = {
.sid = {
.override = 0x508,
.security = 0x50c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VICSRD1,
.name = "vicsrd1",
.sid = TEGRA194_SID_VIC,
.regs = {
.sid = {
.override = 0x510,
.security = 0x514,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
.name = "nvdecsrd1",
.sid = TEGRA194_SID_NVDEC,
.regs = {
.sid = {
.override = 0x518,
.security = 0x51c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU0R,
.name = "miu0r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x530,
.security = 0x534,
},
},
}, {
.name = "miu0w",
.id = TEGRA194_MEMORY_CLIENT_MIU0W,
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x538,
.security = 0x53c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU1R,
.name = "miu1r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x540,
.security = 0x544,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU1W,
.name = "miu1w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x548,
.security = 0x54c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU2R,
.name = "miu2r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x570,
.security = 0x574,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU2W,
.name = "miu2w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x578,
.security = 0x57c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU3R,
.name = "miu3r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x580,
.security = 0x584,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU3W,
.name = "miu3w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x588,
.security = 0x58c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU4R,
.name = "miu4r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x590,
.security = 0x594,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU4W,
.name = "miu4w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x598,
.security = 0x59c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DPMUR,
.name = "dpmur",
.sid = TEGRA194_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x598,
.security = 0x59c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VIFALR,
.name = "vifalr",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
.sid = {
.override = 0x5e0,
.security = 0x5e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_VIFALW,
.name = "vifalw",
.sid = TEGRA194_SID_VI_FALCON,
.regs = {
.sid = {
.override = 0x5e8,
.security = 0x5ec,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x5f0,
.security = 0x5f4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
.name = "dla0falrdb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x5f8,
.security = 0x5fc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
.name = "dla0wra",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x600,
.security = 0x604,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x608,
.security = 0x60c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
.name = "dla1rda",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x610,
.security = 0x614,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
.name = "dla1falrdb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x618,
.security = 0x61c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
.name = "dla1wra",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x620,
.security = 0x624,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla1falwrb",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x628,
.security = 0x62c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
.name = "pva0rda",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x630,
.security = 0x634,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
.name = "pva0rdb",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x638,
.security = 0x63c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
.name = "pva0rdc",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x640,
.security = 0x644,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
.name = "pva0wra",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x648,
.security = 0x64c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
.name = "pva0wrb",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x650,
.security = 0x654,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
.name = "pva0wrc",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x658,
.security = 0x65c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
.name = "pva1rda",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x660,
.security = 0x664,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
.name = "pva1rdb",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x668,
.security = 0x66c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
.name = "pva1rdc",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x670,
.security = 0x674,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
.name = "pva1wra",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x678,
.security = 0x67c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
.name = "pva1wrb",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x680,
.security = 0x684,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
.name = "pva1wrc",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x688,
.security = 0x68c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_RCER,
.name = "rcer",
.sid = TEGRA194_SID_RCE,
.regs = {
.sid = {
.override = 0x690,
.security = 0x694,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_RCEW,
.name = "rcew",
.sid = TEGRA194_SID_RCE,
.regs = {
.sid = {
.override = 0x698,
.security = 0x69c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
.name = "rcedmar",
.sid = TEGRA194_SID_RCE,
.regs = {
.sid = {
.override = 0x6a0,
.security = 0x6a4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
.name = "rcedmaw",
.sid = TEGRA194_SID_RCE,
.regs = {
.sid = {
.override = 0x6a8,
.security = 0x6ac,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
.name = "nvenc1srd",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.sid = {
.override = 0x6b0,
.security = 0x6b4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
.name = "nvenc1swr",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.sid = {
.override = 0x6b8,
.security = 0x6bc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.sid = {
.override = 0x6c0,
.security = 0x6c4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE0W,
.name = "pcie0w",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.sid = {
.override = 0x6c8,
.security = 0x6cc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE1R,
.name = "pcie1r",
.sid = TEGRA194_SID_PCIE1,
.regs = {
.sid = {
.override = 0x6d0,
.security = 0x6d4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE1W,
.name = "pcie1w",
.sid = TEGRA194_SID_PCIE1,
.regs = {
.sid = {
.override = 0x6d8,
.security = 0x6dc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
.name = "pcie2ar",
.sid = TEGRA194_SID_PCIE2,
.regs = {
.sid = {
.override = 0x6e0,
.security = 0x6e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
.name = "pcie2aw",
.sid = TEGRA194_SID_PCIE2,
.regs = {
.sid = {
.override = 0x6e8,
.security = 0x6ec,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE3R,
.name = "pcie3r",
.sid = TEGRA194_SID_PCIE3,
.regs = {
.sid = {
.override = 0x6f0,
.security = 0x6f4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE3W,
.name = "pcie3w",
.sid = TEGRA194_SID_PCIE3,
.regs = {
.sid = {
.override = 0x6f8,
.security = 0x6fc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE4R,
.name = "pcie4r",
.sid = TEGRA194_SID_PCIE4,
.regs = {
.sid = {
.override = 0x700,
.security = 0x704,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE4W,
.name = "pcie4w",
.sid = TEGRA194_SID_PCIE4,
.regs = {
.sid = {
.override = 0x708,
.security = 0x70c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE5R,
.name = "pcie5r",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.sid = {
.override = 0x710,
.security = 0x714,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE5W,
.name = "pcie5w",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.sid = {
.override = 0x718,
.security = 0x71c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPFALW,
.name = "ispfalw",
.sid = TEGRA194_SID_ISP_FALCON,
.regs = {
.sid = {
.override = 0x720,
.security = 0x724,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.sid = TEGRA194_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x748,
.security = 0x74c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
.name = "dla1rda1",
.sid = TEGRA194_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x750,
.security = 0x754,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
.name = "pva0rda1",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x758,
.security = 0x75c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
.name = "pva0rdb1",
.sid = TEGRA194_SID_PVA0,
.regs = {
.sid = {
.override = 0x760,
.security = 0x764,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
.name = "pva1rda1",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x768,
.security = 0x76c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
.name = "pva1rdb1",
.sid = TEGRA194_SID_PVA1,
.regs = {
.sid = {
.override = 0x770,
.security = 0x774,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
.name = "pcie5r1",
.sid = TEGRA194_SID_PCIE5,
.regs = {
.sid = {
.override = 0x778,
.security = 0x77c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
.name = "nvencsrd1",
.sid = TEGRA194_SID_NVENC,
.regs = {
.sid = {
.override = 0x780,
.security = 0x784,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
.name = "nvenc1srd1",
.sid = TEGRA194_SID_NVENC1,
.regs = {
.sid = {
.override = 0x788,
.security = 0x78c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_ISPRA1,
.name = "ispra1",
.sid = TEGRA194_SID_ISP,
.regs = {
.sid = {
.override = 0x790,
.security = 0x794,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
.name = "pcie0r1",
.sid = TEGRA194_SID_PCIE0,
.regs = {
.sid = {
.override = 0x798,
.security = 0x79c,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
.name = "nvdec1srd",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.sid = {
.override = 0x7c8,
.security = 0x7cc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
.name = "nvdec1srd1",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.sid = {
.override = 0x7d0,
.security = 0x7d4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
.name = "nvdec1swr",
.sid = TEGRA194_SID_NVDEC1,
.regs = {
.sid = {
.override = 0x7d8,
.security = 0x7dc,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU5R,
.name = "miu5r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x7e0,
.security = 0x7e4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU5W,
.name = "miu5w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x7e8,
.security = 0x7ec,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU6R,
.name = "miu6r",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x7f0,
.security = 0x7f4,
},
},
}, {
.id = TEGRA194_MEMORY_CLIENT_MIU6W,
.name = "miu6w",
.sid = TEGRA194_SID_MIU,
.regs = {
.sid = {
.override = 0x7f8,
.security = 0x7fc,
},
},
},
};
const struct tegra_mc_soc tegra194_mc_soc = {
.num_clients = ARRAY_SIZE(tegra194_mc_clients),
.clients = tegra194_mc_clients,
.num_address_bits = 40,
.num_channels = 16,
.client_id_mask = 0xff,
.intmask = MC_INT_DECERR_ROUTE_SANITY |
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.has_addr_hi_reg = true,
.ops = &tegra186_mc_ops,
.icc_ops = &tegra_mc_icc_ops,
.ch_intmask = 0x00000f00,
.global_intstatus_channel_shift = 8,
};
|
linux-master
|
drivers/memory/tegra/tegra194.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/of_reserved_mem.h>
#include "tegra210-emc.h"
#define TEGRA_EMC_MAX_FREQS 16
static int tegra210_emc_table_device_init(struct reserved_mem *rmem,
struct device *dev)
{
struct tegra210_emc *emc = dev_get_drvdata(dev);
struct tegra210_emc_timing *timings;
unsigned int i, count = 0;
timings = memremap(rmem->base, rmem->size, MEMREMAP_WB);
if (!timings) {
dev_err(dev, "failed to map EMC table\n");
return -ENOMEM;
}
for (i = 0; i < TEGRA_EMC_MAX_FREQS; i++) {
if (timings[i].revision == 0)
break;
count++;
}
/* only the nominal and derated tables are expected */
if (emc->derated) {
dev_warn(dev, "excess EMC table '%s'\n", rmem->name);
goto out;
}
if (emc->nominal) {
if (count != emc->num_timings) {
dev_warn(dev, "%u derated vs. %u nominal entries\n",
count, emc->num_timings);
memunmap(timings);
return -EINVAL;
}
emc->derated = timings;
} else {
emc->num_timings = count;
emc->nominal = timings;
}
out:
/* keep track of which table this is */
rmem->priv = timings;
return 0;
}
static void tegra210_emc_table_device_release(struct reserved_mem *rmem,
struct device *dev)
{
struct tegra210_emc_timing *timings = rmem->priv;
struct tegra210_emc *emc = dev_get_drvdata(dev);
if ((emc->nominal && timings != emc->nominal) &&
(emc->derated && timings != emc->derated))
dev_warn(dev, "trying to release unassigned EMC table '%s'\n",
rmem->name);
memunmap(timings);
}
static const struct reserved_mem_ops tegra210_emc_table_ops = {
.device_init = tegra210_emc_table_device_init,
.device_release = tegra210_emc_table_device_release,
};
static int tegra210_emc_table_init(struct reserved_mem *rmem)
{
pr_debug("Tegra210 EMC table at %pa, size %lu bytes\n", &rmem->base,
(unsigned long)rmem->size);
rmem->ops = &tegra210_emc_table_ops;
return 0;
}
RESERVEDMEM_OF_DECLARE(tegra210_emc_table, "nvidia,tegra210-emc-table",
tegra210_emc_table_init);
|
linux-master
|
drivers/memory/tegra/tegra210-emc-table.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/interconnect-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/sort.h>
#include <linux/string.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
#include "mc.h"
#define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
#define EMC_FBIO_CFG5_DRAM_WIDTH_X64 BIT(4)
#define EMC_INTSTATUS 0x0
#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
#define EMC_CFG 0xc
#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
#define EMC_CFG_DRAM_ACPD BIT(29)
#define EMC_CFG_DYN_SREF BIT(28)
#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
#define EMC_REFCTRL 0x20
#define EMC_REFCTRL_DEV_SEL_SHIFT 0
#define EMC_REFCTRL_ENABLE BIT(31)
#define EMC_TIMING_CONTROL 0x28
#define EMC_RC 0x2c
#define EMC_RFC 0x30
#define EMC_RAS 0x34
#define EMC_RP 0x38
#define EMC_R2W 0x3c
#define EMC_W2R 0x40
#define EMC_R2P 0x44
#define EMC_W2P 0x48
#define EMC_RD_RCD 0x4c
#define EMC_WR_RCD 0x50
#define EMC_RRD 0x54
#define EMC_REXT 0x58
#define EMC_WDV 0x5c
#define EMC_QUSE 0x60
#define EMC_QRST 0x64
#define EMC_QSAFE 0x68
#define EMC_RDV 0x6c
#define EMC_REFRESH 0x70
#define EMC_BURST_REFRESH_NUM 0x74
#define EMC_PDEX2WR 0x78
#define EMC_PDEX2RD 0x7c
#define EMC_PCHG2PDEN 0x80
#define EMC_ACT2PDEN 0x84
#define EMC_AR2PDEN 0x88
#define EMC_RW2PDEN 0x8c
#define EMC_TXSR 0x90
#define EMC_TCKE 0x94
#define EMC_TFAW 0x98
#define EMC_TRPAB 0x9c
#define EMC_TCLKSTABLE 0xa0
#define EMC_TCLKSTOP 0xa4
#define EMC_TREFBW 0xa8
#define EMC_ODT_WRITE 0xb0
#define EMC_ODT_READ 0xb4
#define EMC_WEXT 0xb8
#define EMC_CTT 0xbc
#define EMC_RFC_SLR 0xc0
#define EMC_MRS_WAIT_CNT2 0xc4
#define EMC_MRS_WAIT_CNT 0xc8
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
#define EMC_MRS 0xcc
#define EMC_MODE_SET_DLL_RESET BIT(8)
#define EMC_MODE_SET_LONG_CNT BIT(26)
#define EMC_EMRS 0xd0
#define EMC_REF 0xd4
#define EMC_PRE 0xd8
#define EMC_SELF_REF 0xe0
#define EMC_SELF_REF_CMD_ENABLED BIT(0)
#define EMC_SELF_REF_DEV_SEL_SHIFT 30
#define EMC_MRW 0xe8
#define EMC_MRR 0xec
#define EMC_MRR_MA_SHIFT 16
#define LPDDR2_MR4_TEMP_SHIFT 0
#define EMC_XM2DQSPADCTRL3 0xf8
#define EMC_FBIO_SPARE 0x100
#define EMC_FBIO_CFG6 0x114
#define EMC_EMRS2 0x12c
#define EMC_MRW2 0x134
#define EMC_MRW4 0x13c
#define EMC_EINPUT 0x14c
#define EMC_EINPUT_DURATION 0x150
#define EMC_PUTERM_EXTRA 0x154
#define EMC_TCKESR 0x158
#define EMC_TPD 0x15c
#define EMC_AUTO_CAL_CONFIG 0x2a4
#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
#define EMC_AUTO_CAL_INTERVAL 0x2a8
#define EMC_AUTO_CAL_STATUS 0x2ac
#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
#define EMC_STATUS 0x2b4
#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
#define EMC_CFG_2 0x2b8
#define EMC_CFG_2_MODE_SHIFT 0
#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
#define EMC_CFG_DIG_DLL 0x2bc
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_RDV_MASK 0x2cc
#define EMC_WDV_MASK 0x2d0
#define EMC_CTT_DURATION 0x2d8
#define EMC_CTT_TERM_CTRL 0x2dc
#define EMC_ZCAL_INTERVAL 0x2e0
#define EMC_ZCAL_WAIT_CNT 0x2e4
#define EMC_ZQ_CAL 0x2ec
#define EMC_ZQ_CAL_CMD BIT(0)
#define EMC_ZQ_CAL_LONG BIT(4)
#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_XM2CMDPADCTRL 0x2f0
#define EMC_XM2DQSPADCTRL 0x2f8
#define EMC_XM2DQSPADCTRL2 0x2fc
#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
#define EMC_XM2DQPADCTRL 0x300
#define EMC_XM2DQPADCTRL2 0x304
#define EMC_XM2CLKPADCTRL 0x308
#define EMC_XM2COMPPADCTRL 0x30c
#define EMC_XM2VTTGENPADCTRL 0x310
#define EMC_XM2VTTGENPADCTRL2 0x314
#define EMC_XM2VTTGENPADCTRL3 0x318
#define EMC_XM2DQSPADCTRL4 0x320
#define EMC_DLL_XFORM_DQS0 0x328
#define EMC_DLL_XFORM_DQS1 0x32c
#define EMC_DLL_XFORM_DQS2 0x330
#define EMC_DLL_XFORM_DQS3 0x334
#define EMC_DLL_XFORM_DQS4 0x338
#define EMC_DLL_XFORM_DQS5 0x33c
#define EMC_DLL_XFORM_DQS6 0x340
#define EMC_DLL_XFORM_DQS7 0x344
#define EMC_DLL_XFORM_QUSE0 0x348
#define EMC_DLL_XFORM_QUSE1 0x34c
#define EMC_DLL_XFORM_QUSE2 0x350
#define EMC_DLL_XFORM_QUSE3 0x354
#define EMC_DLL_XFORM_QUSE4 0x358
#define EMC_DLL_XFORM_QUSE5 0x35c
#define EMC_DLL_XFORM_QUSE6 0x360
#define EMC_DLL_XFORM_QUSE7 0x364
#define EMC_DLL_XFORM_DQ0 0x368
#define EMC_DLL_XFORM_DQ1 0x36c
#define EMC_DLL_XFORM_DQ2 0x370
#define EMC_DLL_XFORM_DQ3 0x374
#define EMC_DLI_TRIM_TXDQS0 0x3a8
#define EMC_DLI_TRIM_TXDQS1 0x3ac
#define EMC_DLI_TRIM_TXDQS2 0x3b0
#define EMC_DLI_TRIM_TXDQS3 0x3b4
#define EMC_DLI_TRIM_TXDQS4 0x3b8
#define EMC_DLI_TRIM_TXDQS5 0x3bc
#define EMC_DLI_TRIM_TXDQS6 0x3c0
#define EMC_DLI_TRIM_TXDQS7 0x3c4
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
#define EMC_SEL_DPD_CTRL 0x3d8
#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
#define EMC_SEL_DPD_CTRL_DDR3_MASK \
((0xf << 2) | BIT(8))
#define EMC_SEL_DPD_CTRL_MASK \
((0x3 << 2) | BIT(5) | BIT(8))
#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
#define EMC_DYN_SELF_REF_CONTROL 0x3e0
#define EMC_TXSRDLL 0x3e4
#define EMC_CCFIFO_ADDR 0x3e8
#define EMC_CCFIFO_DATA 0x3ec
#define EMC_CCFIFO_STATUS 0x3f0
#define EMC_CDB_CNTL_1 0x3f4
#define EMC_CDB_CNTL_2 0x3f8
#define EMC_XM2CLKPADCTRL2 0x3fc
#define EMC_AUTO_CAL_CONFIG2 0x458
#define EMC_AUTO_CAL_CONFIG3 0x45c
#define EMC_IBDLY 0x468
#define EMC_DLL_XFORM_ADDR0 0x46c
#define EMC_DLL_XFORM_ADDR1 0x470
#define EMC_DLL_XFORM_ADDR2 0x474
#define EMC_DSR_VTTGEN_DRV 0x47c
#define EMC_TXDSRVTTGEN 0x480
#define EMC_XM2CMDPADCTRL4 0x484
#define EMC_XM2CMDPADCTRL5 0x488
#define EMC_DLL_XFORM_DQS8 0x4a0
#define EMC_DLL_XFORM_DQS9 0x4a4
#define EMC_DLL_XFORM_DQS10 0x4a8
#define EMC_DLL_XFORM_DQS11 0x4ac
#define EMC_DLL_XFORM_DQS12 0x4b0
#define EMC_DLL_XFORM_DQS13 0x4b4
#define EMC_DLL_XFORM_DQS14 0x4b8
#define EMC_DLL_XFORM_DQS15 0x4bc
#define EMC_DLL_XFORM_QUSE8 0x4c0
#define EMC_DLL_XFORM_QUSE9 0x4c4
#define EMC_DLL_XFORM_QUSE10 0x4c8
#define EMC_DLL_XFORM_QUSE11 0x4cc
#define EMC_DLL_XFORM_QUSE12 0x4d0
#define EMC_DLL_XFORM_QUSE13 0x4d4
#define EMC_DLL_XFORM_QUSE14 0x4d8
#define EMC_DLL_XFORM_QUSE15 0x4dc
#define EMC_DLL_XFORM_DQ4 0x4e0
#define EMC_DLL_XFORM_DQ5 0x4e4
#define EMC_DLL_XFORM_DQ6 0x4e8
#define EMC_DLL_XFORM_DQ7 0x4ec
#define EMC_DLI_TRIM_TXDQS8 0x520
#define EMC_DLI_TRIM_TXDQS9 0x524
#define EMC_DLI_TRIM_TXDQS10 0x528
#define EMC_DLI_TRIM_TXDQS11 0x52c
#define EMC_DLI_TRIM_TXDQS12 0x530
#define EMC_DLI_TRIM_TXDQS13 0x534
#define EMC_DLI_TRIM_TXDQS14 0x538
#define EMC_DLI_TRIM_TXDQS15 0x53c
#define EMC_CDB_CNTL_3 0x540
#define EMC_XM2DQSPADCTRL5 0x544
#define EMC_XM2DQSPADCTRL6 0x548
#define EMC_XM2DQPADCTRL3 0x54c
#define EMC_DLL_XFORM_ADDR3 0x550
#define EMC_DLL_XFORM_ADDR4 0x554
#define EMC_DLL_XFORM_ADDR5 0x558
#define EMC_CFG_PIPE 0x560
#define EMC_QPOP 0x564
#define EMC_QUSE_WIDTH 0x568
#define EMC_PUTERM_WIDTH 0x56c
#define EMC_BGBIAS_CTL0 0x570
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
#define EMC_PUTERM_ADJ 0x574
#define DRAM_DEV_SEL_ALL 0
#define DRAM_DEV_SEL_0 BIT(31)
#define DRAM_DEV_SEL_1 BIT(30)
#define EMC_CFG_POWER_FEATURES_MASK \
(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
/* Maximum amount of time in us. to wait for changes to become effective */
#define EMC_STATUS_UPDATE_TIMEOUT 1000
enum emc_dram_type {
DRAM_TYPE_DDR3 = 0,
DRAM_TYPE_DDR1 = 1,
DRAM_TYPE_LPDDR3 = 2,
DRAM_TYPE_DDR2 = 3
};
enum emc_dll_change {
DLL_CHANGE_NONE,
DLL_CHANGE_ON,
DLL_CHANGE_OFF
};
static const unsigned long emc_burst_regs[] = {
EMC_RC,
EMC_RFC,
EMC_RFC_SLR,
EMC_RAS,
EMC_RP,
EMC_R2W,
EMC_W2R,
EMC_R2P,
EMC_W2P,
EMC_RD_RCD,
EMC_WR_RCD,
EMC_RRD,
EMC_REXT,
EMC_WEXT,
EMC_WDV,
EMC_WDV_MASK,
EMC_QUSE,
EMC_QUSE_WIDTH,
EMC_IBDLY,
EMC_EINPUT,
EMC_EINPUT_DURATION,
EMC_PUTERM_EXTRA,
EMC_PUTERM_WIDTH,
EMC_PUTERM_ADJ,
EMC_CDB_CNTL_1,
EMC_CDB_CNTL_2,
EMC_CDB_CNTL_3,
EMC_QRST,
EMC_QSAFE,
EMC_RDV,
EMC_RDV_MASK,
EMC_REFRESH,
EMC_BURST_REFRESH_NUM,
EMC_PRE_REFRESH_REQ_CNT,
EMC_PDEX2WR,
EMC_PDEX2RD,
EMC_PCHG2PDEN,
EMC_ACT2PDEN,
EMC_AR2PDEN,
EMC_RW2PDEN,
EMC_TXSR,
EMC_TXSRDLL,
EMC_TCKE,
EMC_TCKESR,
EMC_TPD,
EMC_TFAW,
EMC_TRPAB,
EMC_TCLKSTABLE,
EMC_TCLKSTOP,
EMC_TREFBW,
EMC_FBIO_CFG6,
EMC_ODT_WRITE,
EMC_ODT_READ,
EMC_FBIO_CFG5,
EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_PERIOD,
EMC_DLL_XFORM_DQS0,
EMC_DLL_XFORM_DQS1,
EMC_DLL_XFORM_DQS2,
EMC_DLL_XFORM_DQS3,
EMC_DLL_XFORM_DQS4,
EMC_DLL_XFORM_DQS5,
EMC_DLL_XFORM_DQS6,
EMC_DLL_XFORM_DQS7,
EMC_DLL_XFORM_DQS8,
EMC_DLL_XFORM_DQS9,
EMC_DLL_XFORM_DQS10,
EMC_DLL_XFORM_DQS11,
EMC_DLL_XFORM_DQS12,
EMC_DLL_XFORM_DQS13,
EMC_DLL_XFORM_DQS14,
EMC_DLL_XFORM_DQS15,
EMC_DLL_XFORM_QUSE0,
EMC_DLL_XFORM_QUSE1,
EMC_DLL_XFORM_QUSE2,
EMC_DLL_XFORM_QUSE3,
EMC_DLL_XFORM_QUSE4,
EMC_DLL_XFORM_QUSE5,
EMC_DLL_XFORM_QUSE6,
EMC_DLL_XFORM_QUSE7,
EMC_DLL_XFORM_ADDR0,
EMC_DLL_XFORM_ADDR1,
EMC_DLL_XFORM_ADDR2,
EMC_DLL_XFORM_ADDR3,
EMC_DLL_XFORM_ADDR4,
EMC_DLL_XFORM_ADDR5,
EMC_DLL_XFORM_QUSE8,
EMC_DLL_XFORM_QUSE9,
EMC_DLL_XFORM_QUSE10,
EMC_DLL_XFORM_QUSE11,
EMC_DLL_XFORM_QUSE12,
EMC_DLL_XFORM_QUSE13,
EMC_DLL_XFORM_QUSE14,
EMC_DLL_XFORM_QUSE15,
EMC_DLI_TRIM_TXDQS0,
EMC_DLI_TRIM_TXDQS1,
EMC_DLI_TRIM_TXDQS2,
EMC_DLI_TRIM_TXDQS3,
EMC_DLI_TRIM_TXDQS4,
EMC_DLI_TRIM_TXDQS5,
EMC_DLI_TRIM_TXDQS6,
EMC_DLI_TRIM_TXDQS7,
EMC_DLI_TRIM_TXDQS8,
EMC_DLI_TRIM_TXDQS9,
EMC_DLI_TRIM_TXDQS10,
EMC_DLI_TRIM_TXDQS11,
EMC_DLI_TRIM_TXDQS12,
EMC_DLI_TRIM_TXDQS13,
EMC_DLI_TRIM_TXDQS14,
EMC_DLI_TRIM_TXDQS15,
EMC_DLL_XFORM_DQ0,
EMC_DLL_XFORM_DQ1,
EMC_DLL_XFORM_DQ2,
EMC_DLL_XFORM_DQ3,
EMC_DLL_XFORM_DQ4,
EMC_DLL_XFORM_DQ5,
EMC_DLL_XFORM_DQ6,
EMC_DLL_XFORM_DQ7,
EMC_XM2CMDPADCTRL,
EMC_XM2CMDPADCTRL4,
EMC_XM2CMDPADCTRL5,
EMC_XM2DQPADCTRL2,
EMC_XM2DQPADCTRL3,
EMC_XM2CLKPADCTRL,
EMC_XM2CLKPADCTRL2,
EMC_XM2COMPPADCTRL,
EMC_XM2VTTGENPADCTRL,
EMC_XM2VTTGENPADCTRL2,
EMC_XM2VTTGENPADCTRL3,
EMC_XM2DQSPADCTRL3,
EMC_XM2DQSPADCTRL4,
EMC_XM2DQSPADCTRL5,
EMC_XM2DQSPADCTRL6,
EMC_DSR_VTTGEN_DRV,
EMC_TXDSRVTTGEN,
EMC_FBIO_SPARE,
EMC_ZCAL_WAIT_CNT,
EMC_MRS_WAIT_CNT2,
EMC_CTT,
EMC_CTT_DURATION,
EMC_CFG_PIPE,
EMC_DYN_SELF_REF_CONTROL,
EMC_QPOP
};
struct emc_timing {
unsigned long rate;
u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
u32 emc_auto_cal_config;
u32 emc_auto_cal_config2;
u32 emc_auto_cal_config3;
u32 emc_auto_cal_interval;
u32 emc_bgbias_ctl0;
u32 emc_cfg;
u32 emc_cfg_2;
u32 emc_ctt_term_ctrl;
u32 emc_mode_1;
u32 emc_mode_2;
u32 emc_mode_4;
u32 emc_mode_reset;
u32 emc_mrs_wait_cnt;
u32 emc_sel_dpd_ctrl;
u32 emc_xm2dqspadctrl2;
u32 emc_zcal_cnt_long;
u32 emc_zcal_interval;
};
enum emc_rate_request_type {
EMC_RATE_DEBUG,
EMC_RATE_ICC,
EMC_RATE_TYPE_MAX,
};
struct emc_rate_request {
unsigned long min_rate;
unsigned long max_rate;
};
struct tegra_emc {
struct device *dev;
struct tegra_mc *mc;
void __iomem *regs;
struct clk *clk;
enum emc_dram_type dram_type;
unsigned int dram_bus_width;
unsigned int dram_num;
struct emc_timing last_timing;
struct emc_timing *timings;
unsigned int num_timings;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
struct icc_provider provider;
/*
* There are multiple sources in the EMC driver which could request
* a min/max clock rate, these rates are contained in this array.
*/
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
/* protect shared rate-change code path */
struct mutex rate_lock;
};
/* Timing change sequence functions */
static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
unsigned long offset)
{
writel(value, emc->regs + EMC_CCFIFO_DATA);
writel(offset, emc->regs + EMC_CCFIFO_ADDR);
}
static void emc_seq_update_timing(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
writel(1, emc->regs + EMC_TIMING_CONTROL);
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_STATUS);
if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
return;
udelay(1);
}
dev_err(emc->dev, "timing update timed out\n");
}
static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
return;
udelay(1);
}
dev_err(emc->dev, "auto cal disable timed out\n");
}
static void emc_seq_wait_clkchange(struct tegra_emc *emc)
{
unsigned int i;
u32 value;
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
value = readl(emc->regs + EMC_INTSTATUS);
if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
return;
udelay(1);
}
dev_err(emc->dev, "clock change timed out\n");
}
static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = NULL;
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate == rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu\n", rate);
return NULL;
}
return timing;
}
static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
enum emc_dll_change dll_change;
unsigned int pre_wait = 0;
u32 val, val2, mask;
bool update = false;
unsigned int i;
if (!timing)
return -ENOENT;
if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
dll_change = DLL_CHANGE_NONE;
else if (timing->emc_mode_1 & 0x1)
dll_change = DLL_CHANGE_ON;
else
dll_change = DLL_CHANGE_OFF;
/* Clear CLKCHANGE_COMPLETE interrupts */
writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
/* Disable dynamic self-refresh */
val = readl(emc->regs + EMC_CFG);
if (val & EMC_CFG_PWR_MASK) {
val &= ~EMC_CFG_POWER_FEATURES_MASK;
writel(val, emc->regs + EMC_CFG);
pre_wait = 5;
}
/* Disable SEL_DPD_CTRL for clock change */
if (emc->dram_type == DRAM_TYPE_DDR3)
mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
else
mask = EMC_SEL_DPD_CTRL_MASK;
val = readl(emc->regs + EMC_SEL_DPD_CTRL);
if (val & mask) {
val &= ~mask;
writel(val, emc->regs + EMC_SEL_DPD_CTRL);
}
/* Prepare DQ/DQS for clock change */
val = readl(emc->regs + EMC_BGBIAS_CTL0);
val2 = last->emc_bgbias_ctl0;
if (!(timing->emc_bgbias_ctl0 &
EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
(val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
update = true;
}
if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
(val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
update = true;
}
if (update) {
writel(val2, emc->regs + EMC_BGBIAS_CTL0);
if (pre_wait < 5)
pre_wait = 5;
}
update = false;
val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
update = true;
}
if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
!(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
update = true;
}
if (update) {
writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
if (pre_wait < 30)
pre_wait = 30;
}
/* Wait to settle */
if (pre_wait) {
emc_seq_update_timing(emc);
udelay(pre_wait);
}
/* Program CTT_TERM control */
if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
emc_seq_disable_auto_cal(emc);
writel(timing->emc_ctt_term_ctrl,
emc->regs + EMC_CTT_TERM_CTRL);
emc_seq_update_timing(emc);
}
/* Program burst shadow registers */
for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
writel(timing->emc_burst_data[i],
emc->regs + emc_burst_regs[i]);
writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
tegra_mc_write_emem_configuration(emc->mc, timing->rate);
val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
emc_ccfifo_writel(emc, val, EMC_CFG);
/* Program AUTO_CAL_CONFIG */
if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
EMC_AUTO_CAL_CONFIG2);
if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
EMC_AUTO_CAL_CONFIG3);
if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
val = timing->emc_auto_cal_config;
val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
}
/* DDR3: predict MRS long wait count */
if (emc->dram_type == DRAM_TYPE_DDR3 &&
dll_change == DLL_CHANGE_ON) {
u32 cnt = 512;
if (timing->emc_zcal_interval != 0 &&
last->emc_zcal_interval == 0)
cnt -= emc->dram_num * 256;
val = (timing->emc_mrs_wait_cnt
& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
if (cnt < val)
cnt = val;
val = timing->emc_mrs_wait_cnt
& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
writel(val, emc->regs + EMC_MRS_WAIT_CNT);
}
val = timing->emc_cfg_2;
val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
emc_ccfifo_writel(emc, val, EMC_CFG_2);
/* DDR3: Turn off DLL and enter self-refresh */
if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
/* Disable refresh controller */
emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
EMC_REFCTRL);
if (emc->dram_type == DRAM_TYPE_DDR3)
emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
EMC_SELF_REF_CMD_ENABLED,
EMC_SELF_REF);
/* Flow control marker */
emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
/* DDR3: Exit self-refresh */
if (emc->dram_type == DRAM_TYPE_DDR3)
emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
EMC_SELF_REF);
emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
EMC_REFCTRL_ENABLE,
EMC_REFCTRL);
/* Set DRAM mode registers */
if (emc->dram_type == DRAM_TYPE_DDR3) {
if (timing->emc_mode_1 != last->emc_mode_1)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
if (timing->emc_mode_2 != last->emc_mode_2)
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
if ((timing->emc_mode_reset != last->emc_mode_reset) ||
dll_change == DLL_CHANGE_ON) {
val = timing->emc_mode_reset;
if (dll_change == DLL_CHANGE_ON) {
val |= EMC_MODE_SET_DLL_RESET;
val |= EMC_MODE_SET_LONG_CNT;
} else {
val &= ~EMC_MODE_SET_DLL_RESET;
}
emc_ccfifo_writel(emc, val, EMC_MRS);
}
} else {
if (timing->emc_mode_2 != last->emc_mode_2)
emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
if (timing->emc_mode_1 != last->emc_mode_1)
emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
if (timing->emc_mode_4 != last->emc_mode_4)
emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
}
/* Issue ZCAL command if turning ZCAL on */
if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
if (emc->dram_num > 1)
emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
EMC_ZQ_CAL);
}
/* Write to RO register to remove stall after change */
emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
/* Disable AUTO_CAL for clock change */
emc_seq_disable_auto_cal(emc);
/* Read register to wait until programming has settled */
readl(emc->regs + EMC_INTSTATUS);
return 0;
}
static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
struct emc_timing *last = &emc->last_timing;
u32 val;
if (!timing)
return;
/* Wait until the state machine has settled */
emc_seq_wait_clkchange(emc);
/* Restore AUTO_CAL */
if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
writel(timing->emc_auto_cal_interval,
emc->regs + EMC_AUTO_CAL_INTERVAL);
/* Restore dynamic self-refresh */
if (timing->emc_cfg & EMC_CFG_PWR_MASK)
writel(timing->emc_cfg, emc->regs + EMC_CFG);
/* Set ZCAL wait count */
writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
/* LPDDR3: Turn off BGBIAS if low frequency */
if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
timing->emc_bgbias_ctl0 &
EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
val = timing->emc_bgbias_ctl0;
val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
writel(val, emc->regs + EMC_BGBIAS_CTL0);
} else {
if (emc->dram_type == DRAM_TYPE_DDR3 &&
readl(emc->regs + EMC_BGBIAS_CTL0) !=
timing->emc_bgbias_ctl0) {
writel(timing->emc_bgbias_ctl0,
emc->regs + EMC_BGBIAS_CTL0);
}
writel(timing->emc_auto_cal_interval,
emc->regs + EMC_AUTO_CAL_INTERVAL);
}
/* Wait for timing to settle */
udelay(2);
/* Reprogram SEL_DPD_CTRL */
writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
emc_seq_update_timing(emc);
emc->last_timing = *timing;
}
/* Initialization and deinitialization */
static void emc_read_current_timing(struct tegra_emc *emc,
struct emc_timing *timing)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
timing->emc_burst_data[i] =
readl(emc->regs + emc_burst_regs[i]);
timing->emc_cfg = readl(emc->regs + EMC_CFG);
timing->emc_auto_cal_interval = 0;
timing->emc_zcal_cnt_long = 0;
timing->emc_mode_1 = 0;
timing->emc_mode_2 = 0;
timing->emc_mode_4 = 0;
timing->emc_mode_reset = 0;
}
static int emc_init(struct tegra_emc *emc)
{
emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64)
emc->dram_bus_width = 64;
else
emc->dram_bus_width = 32;
dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
emc_read_current_timing(emc, &emc->last_timing);
return 0;
}
static int load_one_timing_from_dt(struct tegra_emc *emc,
struct emc_timing *timing,
struct device_node *node)
{
u32 value;
int err;
err = of_property_read_u32(node, "clock-frequency", &value);
if (err) {
dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
node, err);
return err;
}
timing->rate = value;
err = of_property_read_u32_array(node, "nvidia,emc-configuration",
timing->emc_burst_data,
ARRAY_SIZE(timing->emc_burst_data));
if (err) {
dev_err(emc->dev,
"timing %pOFn: failed to read emc burst data: %d\n",
node, err);
return err;
}
#define EMC_READ_PROP(prop, dtprop) { \
err = of_property_read_u32(node, dtprop, &timing->prop); \
if (err) { \
dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
node, err); \
return err; \
} \
}
EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
#undef EMC_READ_PROP
return 0;
}
static int cmp_timings(const void *_a, const void *_b)
{
const struct emc_timing *a = _a;
const struct emc_timing *b = _b;
if (a->rate < b->rate)
return -1;
else if (a->rate == b->rate)
return 0;
else
return 1;
}
static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
struct device_node *node)
{
int child_count = of_get_child_count(node);
struct device_node *child;
struct emc_timing *timing;
unsigned int i = 0;
int err;
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!emc->timings)
return -ENOMEM;
emc->num_timings = child_count;
for_each_child_of_node(node, child) {
timing = &emc->timings[i++];
err = load_one_timing_from_dt(emc, timing, child);
if (err) {
of_node_put(child);
return err;
}
}
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
NULL);
return 0;
}
static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra124-emc" },
{ .compatible = "nvidia,tegra132-emc" },
{}
};
MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct device_node *
tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
{
struct device_node *np;
int err;
for_each_child_of_node(node, np) {
u32 value;
err = of_property_read_u32(np, "nvidia,ram-code", &value);
if (err || (value != ram_code))
continue;
return np;
}
return NULL;
}
static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
{
unsigned int i;
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
emc->requested_rate[i].min_rate = 0;
emc->requested_rate[i].max_rate = ULONG_MAX;
}
}
static int emc_request_rate(struct tegra_emc *emc,
unsigned long new_min_rate,
unsigned long new_max_rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = emc->requested_rate;
unsigned long min_rate = 0, max_rate = ULONG_MAX;
unsigned int i;
int err;
/* select minimum and maximum rates among the requested rates */
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
if (i == type) {
min_rate = max(new_min_rate, min_rate);
max_rate = min(new_max_rate, max_rate);
} else {
min_rate = max(req->min_rate, min_rate);
max_rate = min(req->max_rate, max_rate);
}
}
if (min_rate > max_rate) {
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
__func__, type, min_rate, max_rate);
return -ERANGE;
}
/*
* EMC rate-changes should go via OPP API because it manages voltage
* changes.
*/
err = dev_pm_opp_set_rate(emc->dev, min_rate);
if (err)
return err;
emc->requested_rate[type].min_rate = new_min_rate;
emc->requested_rate[type].max_rate = new_max_rate;
return 0;
}
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, rate, req->max_rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, req->min_rate, rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (rate == emc->timings[i].rate)
return true;
return false;
}
static int tegra_emc_debug_available_rates_show(struct seq_file *s,
void *data)
{
struct tegra_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
tegra_emc_debug_min_rate_get,
tegra_emc_debug_min_rate_set, "%llu\n");
static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
tegra_emc_debug_max_rate_get,
tegra_emc_debug_max_rate_set, "%llu\n");
static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
{
unsigned int i;
int err;
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->timings[i].rate;
if (emc->timings[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->timings[i].rate;
}
if (!emc->num_timings) {
emc->debugfs.min_rate = clk_get_rate(emc->clk);
emc->debugfs.max_rate = emc->debugfs.min_rate;
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
return;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_max_rate_fops);
}
static inline struct tegra_emc *
to_tegra_emc_provider(struct icc_provider *provider)
{
return container_of(provider, struct tegra_emc, provider);
}
static struct icc_node_data *
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct icc_provider *provider = data;
struct icc_node_data *ndata;
struct icc_node *node;
/* External Memory is the only possible ICC route */
list_for_each_entry(node, &provider->nodes, node_list) {
if (node->id != TEGRA_ICC_EMEM)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
/*
* SRC and DST nodes should have matching TAG in order to have
* it set by default for a requested path.
*/
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
ndata->node = node;
return ndata;
}
return ERR_PTR(-EPROBE_DEFER);
}
static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
unsigned long long rate = max(avg_bw, peak_bw);
unsigned int dram_data_bus_width_bytes;
const unsigned int ddr = 2;
int err;
/*
* Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
* EMC clock rate is twice smaller than the peak data rate because
* data is sampled on both EMC clock edges.
*/
dram_data_bus_width_bytes = emc->dram_bus_width / 8;
do_div(rate, ddr * dram_data_bus_width_bytes);
rate = min_t(u64, rate, U32_MAX);
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
if (err)
return err;
return 0;
}
static int tegra_emc_interconnect_init(struct tegra_emc *emc)
{
const struct tegra_mc_soc *soc = emc->mc->soc;
struct icc_node *node;
int err;
emc->provider.dev = emc->dev;
emc->provider.set = emc_icc_set;
emc->provider.data = &emc->provider;
emc->provider.aggregate = soc->icc_ops->aggregate;
emc->provider.xlate_extended = emc_of_icc_xlate_extended;
icc_provider_init(&emc->provider);
/* create External Memory Controller node */
node = icc_node_create(TEGRA_ICC_EMC);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto err_msg;
}
node->name = "External Memory Controller";
icc_node_add(node, &emc->provider);
/* link External Memory Controller to External Memory (DRAM) */
err = icc_link_create(node, TEGRA_ICC_EMEM);
if (err)
goto remove_nodes;
/* create External Memory node */
node = icc_node_create(TEGRA_ICC_EMEM);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = "External Memory (DRAM)";
icc_node_add(node, &emc->provider);
err = icc_provider_register(&emc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&emc->provider);
err_msg:
dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
return err;
}
static int tegra_emc_opp_table_init(struct tegra_emc *emc)
{
u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
int opp_token, err;
err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
if (err < 0) {
dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
return err;
}
opp_token = err;
err = dev_pm_opp_of_add_table(emc->dev);
if (err) {
if (err == -ENODEV)
dev_err(emc->dev, "OPP table not found, please update your device tree\n");
else
dev_err(emc->dev, "failed to add OPP table: %d\n", err);
goto put_hw_table;
}
dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
hw_version, clk_get_rate(emc->clk) / 1000000);
/* first dummy rate-set initializes voltage state */
err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
if (err) {
dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
goto remove_table;
}
return 0;
remove_table:
dev_pm_opp_of_remove_table(emc->dev);
put_hw_table:
dev_pm_opp_put_supported_hw(opp_token);
return err;
}
static void devm_tegra_emc_unset_callback(void *data)
{
tegra124_clk_set_emc_callbacks(NULL, NULL);
}
static int tegra_emc_probe(struct platform_device *pdev)
{
struct device_node *np;
struct tegra_emc *emc;
u32 ram_code;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
mutex_init(&emc->rate_lock);
emc->dev = &pdev->dev;
emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
if (IS_ERR(emc->mc))
return PTR_ERR(emc->mc);
ram_code = tegra_read_ram_code();
np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
if (np) {
err = tegra_emc_load_timings_from_dt(emc, np);
of_node_put(np);
if (err)
return err;
} else {
dev_info_once(&pdev->dev,
"no memory timings for RAM code %u found in DT\n",
ram_code);
}
err = emc_init(emc);
if (err) {
dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
return err;
}
platform_set_drvdata(pdev, emc);
tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
tegra_emc_complete_timing_change);
err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback,
NULL);
if (err)
return err;
emc->clk = devm_clk_get(&pdev->dev, "emc");
if (IS_ERR(emc->clk)) {
err = PTR_ERR(emc->clk);
dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
return err;
}
err = tegra_emc_opp_table_init(emc);
if (err)
return err;
tegra_emc_rate_requests_init(emc);
if (IS_ENABLED(CONFIG_DEBUG_FS))
emc_debugfs_init(&pdev->dev, emc);
tegra_emc_interconnect_init(emc);
/*
* Don't allow the kernel module to be unloaded. Unloading adds some
* extra complexity which doesn't really worth the effort in a case of
* this driver.
*/
try_module_get(THIS_MODULE);
return 0;
};
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
.driver = {
.name = "tegra-emc",
.of_match_table = tegra_emc_of_match,
.suppress_bind_attrs = true,
.sync_state = icc_sync_state,
},
};
module_platform_driver(tegra_emc_driver);
MODULE_AUTHOR("Mikko Perttunen <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/tegra/tegra124-emc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <soc/tegra/mc.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <linux/interconnect.h>
#include <linux/tegra-icc.h>
#include <soc/tegra/bpmp.h>
#include "mc.h"
/*
* MC Client entries are sorted in the increasing order of the
* override and security register offsets.
*/
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
.id = TEGRA234_MEMORY_CLIENT_HDAR,
.name = "hdar",
.bpmp_id = TEGRA_ICC_BPMP_HDA,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_HDA,
.regs = {
.sid = {
.override = 0xa8,
.security = 0xac,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVENC,
.regs = {
.sid = {
.override = 0xe0,
.security = 0xe4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
.name = "pcie6ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x140,
.security = 0x144,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
.name = "pcie6aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x148,
.security = 0x14c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
.name = "pcie7ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x150,
.security = 0x154,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVENC,
.regs = {
.sid = {
.override = 0x158,
.security = 0x15c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x160,
.security = 0x164,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x168,
.security = 0x16c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x170,
.security = 0x174,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
.name = "dla0rdb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x178,
.security = 0x17c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
.name = "pcie7aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x180,
.security = 0x184,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
.name = "pcie8ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x190,
.security = 0x194,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.bpmp_id = TEGRA_ICC_BPMP_HDA,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_HDA,
.regs = {
.sid = {
.override = 0x1a8,
.security = 0x1ac,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
.name = "pcie8aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE8,
.regs = {
.sid = {
.override = 0x1d8,
.security = 0x1dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
.name = "pcie9ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1e0,
.security = 0x1e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
.name = "pcie6ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE6,
.regs = {
.sid = {
.override = 0x1e8,
.security = 0x1ec,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
.name = "pcie9aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE9,
.regs = {
.sid = {
.override = 0x1f0,
.security = 0x1f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
.name = "pcie10ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x1f8,
.security = 0x1fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
.name = "pcie10aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x200,
.security = 0x204,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
.name = "pcie10ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE10,
.regs = {
.sid = {
.override = 0x240,
.security = 0x244,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
.name = "pcie7ar1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE7,
.regs = {
.sid = {
.override = 0x248,
.security = 0x24c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
.name = "mgbeard",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE,
.regs = {
.sid = {
.override = 0x2c0,
.security = 0x2c4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
.name = "mgbebrd",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF1,
.regs = {
.sid = {
.override = 0x2c8,
.security = 0x2cc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBECRD,
.name = "mgbecrd",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF2,
.regs = {
.sid = {
.override = 0x2d0,
.security = 0x2d4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
.name = "mgbedrd",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF3,
.regs = {
.sid = {
.override = 0x2d8,
.security = 0x2dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.name = "mgbeawr",
.sid = TEGRA234_SID_MGBE,
.regs = {
.sid = {
.override = 0x2e0,
.security = 0x2e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
.name = "mgbebwr",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF1,
.regs = {
.sid = {
.override = 0x2f8,
.security = 0x2fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBECWR,
.name = "mgbecwr",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF2,
.regs = {
.sid = {
.override = 0x308,
.security = 0x30c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x318,
.security = 0x31c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
.name = "mgbedwr",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_MGBE_VF3,
.regs = {
.sid = {
.override = 0x328,
.security = 0x32c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x338,
.security = 0x33c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.bpmp_id = TEGRA_ICC_BPMP_VIC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_VIC,
.regs = {
.sid = {
.override = 0x360,
.security = 0x364,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.bpmp_id = TEGRA_ICC_BPMP_VIC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_VIC,
.regs = {
.sid = {
.override = 0x368,
.security = 0x36c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
.name = "dla0rdb1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x370,
.security = 0x374,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
.name = "dla0wrb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x378,
.security = 0x37c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2W,
.name = "vi2w",
.bpmp_id = TEGRA_ICC_BPMP_VI2,
.type = TEGRA_ICC_ISO_VI,
.sid = TEGRA234_SID_ISO_VI2,
.regs = {
.sid = {
.override = 0x380,
.security = 0x384,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2FALR,
.name = "vi2falr",
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
.type = TEGRA_ICC_ISO_VIFAL,
.sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
.override = 0x388,
.security = 0x38c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c0,
.security = 0x3c4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c8,
.security = 0x3cc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_APER,
.name = "aper",
.bpmp_id = TEGRA_ICC_BPMP_APE,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_APE,
.regs = {
.sid = {
.override = 0x3d0,
.security = 0x3d4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_APEW,
.name = "apew",
.bpmp_id = TEGRA_ICC_BPMP_APE,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_APE,
.regs = {
.sid = {
.override = 0x3d8,
.security = 0x3dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
.name = "vi2falw",
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
.type = TEGRA_ICC_ISO_VIFAL,
.sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
.override = 0x3e0,
.security = 0x3e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f0,
.security = 0x3f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f8,
.security = 0x3fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
.override = 0x490,
.security = 0x494,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA234_SID_BPMP,
.regs = {
.sid = {
.override = 0x498,
.security = 0x49c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA234_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a0,
.security = 0x4a4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA234_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a8,
.security = 0x4ac,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA234_SID_BPMP,
.regs = {
.sid = {
.override = 0x4b0,
.security = 0x4b4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_APE,
.regs = {
.sid = {
.override = 0x4f8,
.security = 0x4fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
.type = TEGRA_ICC_ISO_AUDIO,
.sid = TEGRA234_SID_APE,
.regs = {
.sid = {
.override = 0x500,
.security = 0x504,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
.override = 0x508,
.security = 0x50c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x5f0,
.security = 0x5f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
.name = "dla0falrdb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x5f8,
.security = 0x5fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
.name = "dla0wra",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x600,
.security = 0x604,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x608,
.security = 0x60c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x610,
.security = 0x614,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
.name = "dla0falrdb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x618,
.security = 0x61c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
.name = "dla0wra",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x620,
.security = 0x624,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x628,
.security = 0x62c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE0,
.regs = {
.sid = {
.override = 0x6c0,
.security = 0x6c4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
.name = "pcie0w",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE0,
.regs = {
.sid = {
.override = 0x6c8,
.security = 0x6cc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
.name = "pcie1r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE1,
.regs = {
.sid = {
.override = 0x6d0,
.security = 0x6d4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
.name = "pcie1w",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE1,
.regs = {
.sid = {
.override = 0x6d8,
.security = 0x6dc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
.name = "pcie2ar",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE2,
.regs = {
.sid = {
.override = 0x6e0,
.security = 0x6e4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
.name = "pcie2aw",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE2,
.regs = {
.sid = {
.override = 0x6e8,
.security = 0x6ec,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
.name = "pcie3r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE3,
.regs = {
.sid = {
.override = 0x6f0,
.security = 0x6f4,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
.name = "pcie3w",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE3,
.regs = {
.sid = {
.override = 0x6f8,
.security = 0x6fc,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE4R,
.name = "pcie4r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE4,
.regs = {
.sid = {
.override = 0x700,
.security = 0x704,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE4W,
.name = "pcie4w",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE4,
.regs = {
.sid = {
.override = 0x708,
.security = 0x70c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE5R,
.name = "pcie5r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
.override = 0x710,
.security = 0x714,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE5W,
.name = "pcie5w",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
.override = 0x718,
.security = 0x71c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
.override = 0x748,
.security = 0x74c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
.name = "dla0rda1",
.sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
.override = 0x750,
.security = 0x754,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
.name = "pcie5r1",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
.override = 0x778,
.security = 0x77c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
.name = "nvjpg1srd",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
.override = 0x918,
.security = 0x91c,
},
},
}, {
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
.name = "nvjpg1swr",
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
.type = TEGRA_ICC_NISO,
.sid = TEGRA234_SID_NVJPG1,
.regs = {
.sid = {
.override = 0x920,
.security = 0x924,
},
},
}, {
.id = TEGRA_ICC_MC_CPU_CLUSTER0,
.name = "sw_cluster0",
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA_ICC_MC_CPU_CLUSTER1,
.name = "sw_cluster1",
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA_ICC_MC_CPU_CLUSTER2,
.name = "sw_cluster2",
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA234_MEMORY_CLIENT_NVL1R,
.name = "nvl1r",
.bpmp_id = TEGRA_ICC_BPMP_GPU,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA234_MEMORY_CLIENT_NVL1W,
.name = "nvl1w",
.bpmp_id = TEGRA_ICC_BPMP_GPU,
.type = TEGRA_ICC_NISO,
},
};
/*
* tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
* @src: ICC node for Memory Controller's (MC) Client
* @dst: ICC node for Memory Controller (MC)
*
* Passing the current request info from the MC to the BPMP-FW where
* LA and PTSA registers are accessed and the final EMC freq is set
* based on client_id, type, latency and bandwidth.
* icc_set_bw() makes set_bw calls for both MC and EMC providers in
* sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
* So, the data passed won't be updated by concurrent set calls from
* other clients.
*/
static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
struct mrq_bwmgr_int_request bwmgr_req = { 0 };
struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
const struct tegra_mc_client *pclient = src->data;
struct tegra_bpmp_message msg;
int ret;
/*
* Same Src and Dst node will happen during boot from icc_node_add().
* This can be used to pre-initialize and set bandwidth for all clients
* before their drivers are loaded. We are skipping this case as for us,
* the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
*/
if (src->id == dst->id)
return 0;
if (!mc->bwmgr_mrq_supported)
return 0;
if (!mc->bpmp) {
dev_err(mc->dev, "BPMP reference NULL\n");
return -ENOENT;
}
if (pclient->type == TEGRA_ICC_NISO)
bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
else
bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
memset(&msg, 0, sizeof(msg));
msg.mrq = MRQ_BWMGR_INT;
msg.tx.data = &bwmgr_req;
msg.tx.size = sizeof(bwmgr_req);
msg.rx.data = &bwmgr_resp;
msg.rx.size = sizeof(bwmgr_resp);
ret = tegra_bpmp_transfer(mc->bpmp, &msg);
if (ret < 0) {
dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
goto error;
}
if (msg.rx.ret < 0) {
pr_err("failed to set bandwidth for %u: %d\n",
bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
ret = -EINVAL;
}
error:
return ret;
}
static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{
struct icc_provider *p = node->provider;
struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
if (!mc->bwmgr_mrq_supported)
return 0;
if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 ||
node->id == TEGRA_ICC_MC_CPU_CLUSTER1 ||
node->id == TEGRA_ICC_MC_CPU_CLUSTER2) {
if (mc)
peak_bw = peak_bw * mc->num_channels;
}
*agg_avg += avg_bw;
*agg_peak = max(*agg_peak, peak_bw);
return 0;
}
static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
{
*avg = 0;
*peak = 0;
return 0;
}
static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
.xlate = tegra_mc_icc_xlate,
.aggregate = tegra234_mc_icc_aggregate,
.get_bw = tegra234_mc_icc_get_init_bw,
.set = tegra234_mc_icc_set,
};
const struct tegra_mc_soc tegra234_mc_soc = {
.num_clients = ARRAY_SIZE(tegra234_mc_clients),
.clients = tegra234_mc_clients,
.num_address_bits = 40,
.num_channels = 16,
.client_id_mask = 0x1ff,
.intmask = MC_INT_DECERR_ROUTE_SANITY |
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.has_addr_hi_reg = true,
.ops = &tegra186_mc_ops,
.icc_ops = &tegra234_mc_icc_ops,
.ch_intmask = 0x0000ff00,
.global_intstatus_channel_shift = 8,
/*
* Additionally, there are lite carveouts but those are not currently
* supported.
*/
.num_carveouts = 32,
};
|
linux-master
|
drivers/memory/tegra/tegra234.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/of.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra124-mc.h>
#include "mc.h"
static const struct tegra_mc_client tegra124_mc_clients[] = {
{
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
.regs = {
.la = {
.reg = 0x34c,
.shift = 0,
.mask = 0xff,
.def = 0x0,
},
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 1,
},
.la = {
.reg = 0x2e8,
.shift = 0,
.mask = 0xff,
.def = 0xc2,
},
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 2,
},
.la = {
.reg = 0x2f4,
.shift = 0,
.mask = 0xff,
.def = 0xc6,
},
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 3,
},
.la = {
.reg = 0x2e8,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 4,
},
.la = {
.reg = 0x2f4,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 5,
},
.la = {
.reg = 0x2ec,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 6,
},
.la = {
.reg = 0x2f8,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 14,
},
.la = {
.reg = 0x2e0,
.shift = 0,
.mask = 0xff,
.def = 0x13,
},
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 15,
},
.la = {
.reg = 0x2e4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 16,
},
.la = {
.reg = 0x2f0,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 17,
},
.la = {
.reg = 0x2fc,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 0,
.mask = 0xff,
.def = 0x24,
},
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 22,
},
.la = {
.reg = 0x310,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 23,
},
.la = {
.reg = 0x310,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 28,
},
.la = {
.reg = 0x328,
.shift = 0,
.mask = 0xff,
.def = 0x23,
},
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 29,
},
.la = {
.reg = 0x344,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 30,
},
.la = {
.reg = 0x344,
.shift = 16,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 31,
},
.la = {
.reg = 0x350,
.shift = 0,
.mask = 0xff,
.def = 0x65,
},
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 2,
},
.la = {
.reg = 0x354,
.shift = 0,
.mask = 0xff,
.def = 0x4f,
},
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 3,
},
.la = {
.reg = 0x354,
.shift = 16,
.mask = 0xff,
.def = 0x3d,
},
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 4,
},
.la = {
.reg = 0x358,
.shift = 0,
.mask = 0xff,
.def = 0x66,
},
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 5,
},
.la = {
.reg = 0x358,
.shift = 16,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 11,
},
.la = {
.reg = 0x328,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 17,
},
.la = {
.reg = 0x2e0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 18,
},
.la = {
.reg = 0x2e4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 22,
},
.la = {
.reg = 0x314,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 27,
},
.la = {
.reg = 0x348,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 28,
},
.la = {
.reg = 0x348,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 29,
},
.la = {
.reg = 0x350,
.shift = 16,
.mask = 0xff,
.def = 0x65,
},
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 30,
},
.la = {
.reg = 0x35c,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 31,
},
.la = {
.reg = 0x35c,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 0,
},
.la = {
.reg = 0x360,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 1,
},
.la = {
.reg = 0x360,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 4,
},
.la = {
.reg = 0x370,
.shift = 0,
.mask = 0xff,
.def = 0x18,
},
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 6,
},
.la = {
.reg = 0x374,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 7,
},
.la = {
.reg = 0x374,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 10,
},
.la = {
.reg = 0x37c,
.shift = 0,
.mask = 0xff,
.def = 0x39,
},
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 11,
},
.la = {
.reg = 0x37c,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 12,
},
.la = {
.reg = 0x380,
.shift = 0,
.mask = 0xff,
.def = 0x39,
},
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 13,
},
.la = {
.reg = 0x380,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 14,
},
.la = {
.reg = 0x384,
.shift = 0,
.mask = 0xff,
.def = 0x18,
},
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 16,
},
.la = {
.reg = 0x388,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 17,
},
.la = {
.reg = 0x388,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 20,
},
.la = {
.reg = 0x390,
.shift = 0,
.mask = 0xff,
.def = 0x9b,
},
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 21,
},
.la = {
.reg = 0x390,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 22,
},
.la = {
.reg = 0x3a4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 23,
},
.la = {
.reg = 0x3a4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0x230,
.bit = 24,
},
.la = {
.reg = 0x3c8,
.shift = 0,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0x230,
.bit = 25,
},
.la = {
.reg = 0x3c8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 26,
},
.la = {
.reg = 0x2f0,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 0,
},
.la = {
.reg = 0x3b8,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 1,
},
.la = {
.reg = 0x3bc,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 2,
},
.la = {
.reg = 0x3c0,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
.regs = {
.smmu = {
.reg = 0x234,
.bit = 3,
},
.la = {
.reg = 0x3c4,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 4,
},
.la = {
.reg = 0x3b8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 5,
},
.la = {
.reg = 0x3bc,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 6,
},
.la = {
.reg = 0x3c0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 7,
},
.la = {
.reg = 0x3c4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 12,
},
.la = {
.reg = 0x394,
.shift = 0,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 13,
},
.la = {
.reg = 0x394,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 18,
},
.la = {
.reg = 0x398,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 19,
},
.la = {
.reg = 0x3c8,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
},
};
static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
};
static const unsigned int tegra124_group_drm[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
TEGRA_SWGROUP_VIC,
};
static const struct tegra_smmu_group_soc tegra124_groups[] = {
{
.name = "drm",
.swgroups = tegra124_group_drm,
.num_swgroups = ARRAY_SIZE(tegra124_group_drm),
},
};
#define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
{ \
.name = #_name, \
.id = TEGRA124_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra124_mc_resets[] = {
TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
};
static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
{
/* TODO: program PTSA */
return 0;
}
static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{
/*
* ISO clients need to reserve extra bandwidth up-front because
* there could be high bandwidth pressure during initial filling
* of the client's FIFO buffers. Secondly, we need to take into
* account impurities of the memory subsystem.
*/
if (tag & TEGRA_MC_ICC_TAG_ISO)
peak_bw = tegra_mc_scale_percents(peak_bw, 400);
*agg_avg += avg_bw;
*agg_peak = max(*agg_peak, peak_bw);
return 0;
}
static struct icc_node_data *
tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
const struct tegra_mc_client *client;
unsigned int i, idx = spec->args[0];
struct icc_node_data *ndata;
struct icc_node *node;
list_for_each_entry(node, &mc->provider.nodes, node_list) {
if (node->id != idx)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
client = &mc->soc->clients[idx];
ndata->node = node;
switch (client->swgroup) {
case TEGRA_SWGROUP_DC:
case TEGRA_SWGROUP_DCB:
case TEGRA_SWGROUP_PTC:
case TEGRA_SWGROUP_VI:
/* these clients are isochronous by default */
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
break;
default:
ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
break;
}
return ndata;
}
for (i = 0; i < mc->soc->num_clients; i++) {
if (mc->soc->clients[i].id == idx)
return ERR_PTR(-EPROBE_DEFER);
}
dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
return ERR_PTR(-EINVAL);
}
static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
.xlate_extended = tegra124_mc_of_icc_xlate_extended,
.aggregate = tegra124_mc_icc_aggreate,
.set = tegra124_mc_icc_set,
};
#ifdef CONFIG_ARCH_TEGRA_124_SOC
static const unsigned long tegra124_mc_emem_regs[] = {
MC_EMEM_ARB_CFG,
MC_EMEM_ARB_OUTSTANDING_REQ,
MC_EMEM_ARB_TIMING_RCD,
MC_EMEM_ARB_TIMING_RP,
MC_EMEM_ARB_TIMING_RC,
MC_EMEM_ARB_TIMING_RAS,
MC_EMEM_ARB_TIMING_FAW,
MC_EMEM_ARB_TIMING_RRD,
MC_EMEM_ARB_TIMING_RAP2PRE,
MC_EMEM_ARB_TIMING_WAP2PRE,
MC_EMEM_ARB_TIMING_R2R,
MC_EMEM_ARB_TIMING_W2W,
MC_EMEM_ARB_TIMING_R2W,
MC_EMEM_ARB_TIMING_W2R,
MC_EMEM_ARB_DA_TURNS,
MC_EMEM_ARB_DA_COVERS,
MC_EMEM_ARB_MISC0,
MC_EMEM_ARB_MISC1,
MC_EMEM_ARB_RING1_THROTTLE
};
static const struct tegra_smmu_soc tegra124_smmu_soc = {
.clients = tegra124_mc_clients,
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.swgroups = tegra124_swgroups,
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
.groups = tegra124_groups,
.num_groups = ARRAY_SIZE(tegra124_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 32,
.num_asids = 128,
};
const struct tegra_mc_soc tegra124_mc_soc = {
.clients = tegra124_mc_clients,
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.num_address_bits = 34,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra124_smmu_soc,
.emem_regs = tegra124_mc_emem_regs,
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
.ops = &tegra30_mc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
#ifdef CONFIG_ARCH_TEGRA_132_SOC
static const struct tegra_smmu_soc tegra132_smmu_soc = {
.clients = tegra124_mc_clients,
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.swgroups = tegra124_swgroups,
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
.groups = tegra124_groups,
.num_groups = ARRAY_SIZE(tegra124_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 32,
.num_asids = 128,
};
const struct tegra_mc_soc tegra132_mc_soc = {
.clients = tegra124_mc_clients,
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.num_address_bits = 34,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra132_smmu_soc,
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
.ops = &tegra30_mc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
|
linux-master
|
drivers/memory/tegra/tegra124.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
*/
#include <dt-bindings/memory/tegra210-mc.h>
#include "mc.h"
static const struct tegra_mc_client tegra210_mc_clients[] = {
{
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 1,
},
.la = {
.reg = 0x2e8,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 2,
},
.la = {
.reg = 0x2f4,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 3,
},
.la = {
.reg = 0x2e8,
.shift = 16,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 4,
},
.la = {
.reg = 0x2f4,
.shift = 16,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 5,
},
.la = {
.reg = 0x2ec,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 6,
},
.la = {
.reg = 0x2f8,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 14,
},
.la = {
.reg = 0x2e0,
.shift = 0,
.mask = 0xff,
.def = 0x2e,
},
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 15,
},
.la = {
.reg = 0x2e4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 16,
},
.la = {
.reg = 0x2f0,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 17,
},
.la = {
.reg = 0x2fc,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 0,
.mask = 0xff,
.def = 0x24,
},
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 22,
},
.la = {
.reg = 0x310,
.shift = 0,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 23,
},
.la = {
.reg = 0x310,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x1c,
.name = "nvencsrd",
.swgroup = TEGRA_SWGROUP_NVENC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 28,
},
.la = {
.reg = 0x328,
.shift = 0,
.mask = 0xff,
.def = 0x23,
},
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 29,
},
.la = {
.reg = 0x344,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 30,
},
.la = {
.reg = 0x344,
.shift = 16,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 31,
},
.la = {
.reg = 0x350,
.shift = 0,
.mask = 0xff,
.def = 0x65,
},
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x2b,
.name = "nvencswr",
.swgroup = TEGRA_SWGROUP_NVENC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 11,
},
.la = {
.reg = 0x328,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 17,
},
.la = {
.reg = 0x2e0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 18,
},
.la = {
.reg = 0x2e4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 22,
},
.la = {
.reg = 0x314,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 27,
},
.la = {
.reg = 0x348,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 28,
},
.la = {
.reg = 0x348,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 29,
},
.la = {
.reg = 0x350,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 4,
},
.la = {
.reg = 0x370,
.shift = 0,
.mask = 0xff,
.def = 0x18,
},
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 6,
},
.la = {
.reg = 0x374,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 7,
},
.la = {
.reg = 0x374,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 10,
},
.la = {
.reg = 0x37c,
.shift = 0,
.mask = 0xff,
.def = 0x7a,
},
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 11,
},
.la = {
.reg = 0x37c,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 12,
},
.la = {
.reg = 0x380,
.shift = 0,
.mask = 0xff,
.def = 0x39,
},
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 13,
},
.la = {
.reg = 0x380,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 14,
},
.la = {
.reg = 0x384,
.shift = 0,
.mask = 0xff,
.def = 0x18,
},
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 16,
},
.la = {
.reg = 0x388,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 17,
},
.la = {
.reg = 0x388,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 20,
},
.la = {
.reg = 0x390,
.shift = 0,
.mask = 0xff,
.def = 0x9b,
},
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 21,
},
.la = {
.reg = 0x390,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 22,
},
.la = {
.reg = 0x3a4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 23,
},
.la = {
.reg = 0x3a4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0x230,
.bit = 24,
},
.la = {
.reg = 0x3c8,
.shift = 0,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0x230,
.bit = 25,
},
.la = {
.reg = 0x3c8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 26,
},
.la = {
.reg = 0x2f0,
.shift = 16,
.mask = 0xff,
.def = 0x1e,
},
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 0,
},
.la = {
.reg = 0x3b8,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 1,
},
.la = {
.reg = 0x3bc,
.shift = 0,
.mask = 0xff,
.def = 0x5a,
},
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 2,
},
.la = {
.reg = 0x3c0,
.shift = 0,
.mask = 0xff,
.def = 0x49,
},
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
.regs = {
.smmu = {
.reg = 0x234,
.bit = 3,
},
.la = {
.reg = 0x3c4,
.shift = 0,
.mask = 0xff,
.def = 0x5a,
},
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 4,
},
.la = {
.reg = 0x3b8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 5,
},
.la = {
.reg = 0x3bc,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 6,
},
.la = {
.reg = 0x3c0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 7,
},
.la = {
.reg = 0x3c4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 12,
},
.la = {
.reg = 0x394,
.shift = 0,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 13,
},
.la = {
.reg = 0x394,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 18,
},
.la = {
.reg = 0x398,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 19,
},
.la = {
.reg = 0x3c8,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x78,
.name = "nvdecsrd",
.swgroup = TEGRA_SWGROUP_NVDEC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 24,
},
.la = {
.reg = 0x3d8,
.shift = 0,
.mask = 0xff,
.def = 0x23,
},
},
}, {
.id = 0x79,
.name = "nvdecswr",
.swgroup = TEGRA_SWGROUP_NVDEC,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 25,
},
.la = {
.reg = 0x3d8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x7a,
.name = "aper",
.swgroup = TEGRA_SWGROUP_APE,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 26,
},
.la = {
.reg = 0x3dc,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x7b,
.name = "apew",
.swgroup = TEGRA_SWGROUP_APE,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 27,
},
.la = {
.reg = 0x3dc,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x7e,
.name = "nvjpgsrd",
.swgroup = TEGRA_SWGROUP_NVJPG,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 30,
},
.la = {
.reg = 0x3e4,
.shift = 0,
.mask = 0xff,
.def = 0x23,
},
},
}, {
.id = 0x7f,
.name = "nvjpgswr",
.swgroup = TEGRA_SWGROUP_NVJPG,
.regs = {
.smmu = {
.reg = 0x234,
.bit = 31,
},
.la = {
.reg = 0x3e4,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x80,
.name = "sesrd",
.swgroup = TEGRA_SWGROUP_SE,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 0,
},
.la = {
.reg = 0x3e0,
.shift = 0,
.mask = 0xff,
.def = 0x2e,
},
},
}, {
.id = 0x81,
.name = "seswr",
.swgroup = TEGRA_SWGROUP_SE,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 1,
},
.la = {
.reg = 0x3e0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x82,
.name = "axiapr",
.swgroup = TEGRA_SWGROUP_AXIAP,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 2,
},
.la = {
.reg = 0x3a0,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x83,
.name = "axiapw",
.swgroup = TEGRA_SWGROUP_AXIAP,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 3,
},
.la = {
.reg = 0x3a0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x84,
.name = "etrr",
.swgroup = TEGRA_SWGROUP_ETR,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 4,
},
.la = {
.reg = 0x3ec,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x85,
.name = "etrw",
.swgroup = TEGRA_SWGROUP_ETR,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 5,
},
.la = {
.reg = 0x3ec,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x86,
.name = "tsecsrdb",
.swgroup = TEGRA_SWGROUP_TSECB,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 6,
},
.la = {
.reg = 0x3f0,
.shift = 0,
.mask = 0xff,
.def = 0x9b,
},
},
}, {
.id = 0x87,
.name = "tsecswrb",
.swgroup = TEGRA_SWGROUP_TSECB,
.regs = {
.smmu = {
.reg = 0xb98,
.bit = 7,
},
.la = {
.reg = 0x3f0,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x88,
.name = "gpusrd2",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0xb98,
.bit = 8,
},
.la = {
.reg = 0x3e8,
.shift = 0,
.mask = 0xff,
.def = 0x1a,
},
},
}, {
.id = 0x89,
.name = "gpuswr2",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
.smmu = {
/* read-only */
.reg = 0xb98,
.bit = 9,
},
.la = {
.reg = 0x3e8,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
},
};
static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
{ .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
{ .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
{ .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
{ .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
{ .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
{ .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
{ .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
{ .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
{ .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
{ .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
{ .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
{ .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
};
static const unsigned int tegra210_group_display[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
};
static const struct tegra_smmu_group_soc tegra210_groups[] = {
{
.name = "display",
.swgroups = tegra210_group_display,
.num_swgroups = ARRAY_SIZE(tegra210_group_display),
},
};
static const struct tegra_smmu_soc tegra210_smmu_soc = {
.clients = tegra210_mc_clients,
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
.swgroups = tegra210_swgroups,
.num_swgroups = ARRAY_SIZE(tegra210_swgroups),
.groups = tegra210_groups,
.num_groups = ARRAY_SIZE(tegra210_groups),
.supports_round_robin_arbitration = true,
.supports_request_limit = true,
.num_tlb_lines = 48,
.num_asids = 128,
};
#define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
{ \
.name = #_name, \
.id = TEGRA210_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra210_mc_resets[] = {
TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
};
const struct tegra_mc_soc tegra210_mc_soc = {
.clients = tegra210_mc_clients,
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
.num_address_bits = 34,
.atom_size = 64,
.client_id_mask = 0xff,
.smmu = &tegra210_smmu_soc,
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra210_mc_resets,
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
.ops = &tegra30_mc_ops,
};
|
linux-master
|
drivers/memory/tegra/tegra210.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <dt-bindings/memory/tegra30-mc.h>
#include "mc.h"
static const unsigned long tegra30_mc_emem_regs[] = {
MC_EMEM_ARB_CFG,
MC_EMEM_ARB_OUTSTANDING_REQ,
MC_EMEM_ARB_TIMING_RCD,
MC_EMEM_ARB_TIMING_RP,
MC_EMEM_ARB_TIMING_RC,
MC_EMEM_ARB_TIMING_RAS,
MC_EMEM_ARB_TIMING_FAW,
MC_EMEM_ARB_TIMING_RRD,
MC_EMEM_ARB_TIMING_RAP2PRE,
MC_EMEM_ARB_TIMING_WAP2PRE,
MC_EMEM_ARB_TIMING_R2R,
MC_EMEM_ARB_TIMING_W2W,
MC_EMEM_ARB_TIMING_R2W,
MC_EMEM_ARB_TIMING_W2R,
MC_EMEM_ARB_DA_TURNS,
MC_EMEM_ARB_DA_COVERS,
MC_EMEM_ARB_MISC0,
MC_EMEM_ARB_RING1_THROTTLE,
};
static const struct tegra_mc_client tegra30_mc_clients[] = {
{
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
.regs = {
.la = {
.reg = 0x34c,
.shift = 0,
.mask = 0xff,
.def = 0x0,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 1,
},
.la = {
.reg = 0x2e8,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 128,
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 2,
},
.la = {
.reg = 0x2f4,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 128,
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 3,
},
.la = {
.reg = 0x2e8,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 4,
},
.la = {
.reg = 0x2f4,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 5,
},
.la = {
.reg = 0x2ec,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 128,
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 6,
},
.la = {
.reg = 0x2f8,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 128,
}, {
.id = 0x07,
.name = "display1b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 7,
},
.la = {
.reg = 0x2ec,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x08,
.name = "display1bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 8,
},
.la = {
.reg = 0x2f8,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 9,
},
.la = {
.reg = 0x300,
.shift = 0,
.mask = 0xff,
.def = 0x17,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 10,
},
.la = {
.reg = 0x308,
.shift = 0,
.mask = 0xff,
.def = 0x09,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 11,
},
.la = {
.reg = 0x308,
.shift = 16,
.mask = 0xff,
.def = 0x09,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x0c,
.name = "mpeunifbr",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 12,
},
.la = {
.reg = 0x328,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x0d,
.name = "viruv",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 13,
},
.la = {
.reg = 0x364,
.shift = 0,
.mask = 0xff,
.def = 0x2c,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 14,
},
.la = {
.reg = 0x2e0,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
.fifo_size = 16 * 32,
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 15,
},
.la = {
.reg = 0x2e4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 16,
},
.la = {
.reg = 0x2f0,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 17,
},
.la = {
.reg = 0x2fc,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 18,
},
.la = {
.reg = 0x334,
.shift = 0,
.mask = 0xff,
.def = 0x0a,
},
},
.fifo_size = 16 * 48,
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 19,
},
.la = {
.reg = 0x33c,
.shift = 0,
.mask = 0xff,
.def = 0x0a,
},
},
.fifo_size = 16 * 48,
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 20,
},
.la = {
.reg = 0x30c,
.shift = 0,
.mask = 0xff,
.def = 0x0a,
},
},
.fifo_size = 16 * 48,
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 22,
},
.la = {
.reg = 0x310,
.shift = 0,
.mask = 0xff,
.def = 0x05,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 23,
},
.la = {
.reg = 0x310,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 24,
},
.la = {
.reg = 0x334,
.shift = 16,
.mask = 0xff,
.def = 0x13,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x19,
.name = "idxsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 25,
},
.la = {
.reg = 0x33c,
.shift = 16,
.mask = 0xff,
.def = 0x13,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x1a,
.name = "mpe_ipred",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 26,
},
.la = {
.reg = 0x328,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x1b,
.name = "mpeamemrd",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 27,
},
.la = {
.reg = 0x32c,
.shift = 0,
.mask = 0xff,
.def = 0x42,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x1c,
.name = "mpecsrd",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 28,
},
.la = {
.reg = 0x32c,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 29,
},
.la = {
.reg = 0x344,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 30,
},
.la = {
.reg = 0x344,
.shift = 16,
.mask = 0xff,
.def = 0x12,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 31,
},
.la = {
.reg = 0x350,
.shift = 0,
.mask = 0xff,
.def = 0x33,
},
},
.fifo_size = 16 * 32,
}, {
.id = 0x20,
.name = "texsrd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 0,
},
.la = {
.reg = 0x338,
.shift = 0,
.mask = 0xff,
.def = 0x13,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x21,
.name = "texsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 1,
},
.la = {
.reg = 0x340,
.shift = 0,
.mask = 0xff,
.def = 0x13,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 2,
},
.la = {
.reg = 0x354,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 3,
},
.la = {
.reg = 0x354,
.shift = 16,
.mask = 0xff,
.def = 0xd0,
},
},
.fifo_size = 16 * 4,
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 4,
},
.la = {
.reg = 0x358,
.shift = 0,
.mask = 0xff,
.def = 0x2a,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 5,
},
.la = {
.reg = 0x358,
.shift = 16,
.mask = 0xff,
.def = 0x74,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
.fifo_size = 16 * 14,
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
.fifo_size = 16 * 14,
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 8,
},
.la = {
.reg = 0x300,
.shift = 16,
.mask = 0xff,
.def = 0x6c,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 9,
},
.la = {
.reg = 0x304,
.shift = 0,
.mask = 0xff,
.def = 0x6c,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 10,
},
.la = {
.reg = 0x304,
.shift = 16,
.mask = 0xff,
.def = 0x6c,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x2b,
.name = "mpeunifbw",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 11,
},
.la = {
.reg = 0x330,
.shift = 0,
.mask = 0xff,
.def = 0x13,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 12,
},
.la = {
.reg = 0x364,
.shift = 16,
.mask = 0xff,
.def = 0x12,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 13,
},
.la = {
.reg = 0x368,
.shift = 0,
.mask = 0xff,
.def = 0xb2,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 14,
},
.la = {
.reg = 0x368,
.shift = 16,
.mask = 0xff,
.def = 0xb2,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 15,
},
.la = {
.reg = 0x36c,
.shift = 0,
.mask = 0xff,
.def = 0x12,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 16,
},
.la = {
.reg = 0x30c,
.shift = 16,
.mask = 0xff,
.def = 0x9,
},
},
.fifo_size = 16 * 128,
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 17,
},
.la = {
.reg = 0x2e0,
.shift = 16,
.mask = 0xff,
.def = 0x0c,
},
},
.fifo_size = 16 * 32,
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 18,
},
.la = {
.reg = 0x2e4,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 19,
},
.la = {
.reg = 0x338,
.shift = 16,
.mask = 0xff,
.def = 0x0a,
},
},
.fifo_size = 16 * 48,
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV2,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 20,
},
.la = {
.reg = 0x340,
.shift = 16,
.mask = 0xff,
.def = 0x0a,
},
},
.fifo_size = 16 * 48,
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 22,
},
.la = {
.reg = 0x314,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
.fifo_size = 16 * 32,
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 23,
},
.la = {
.reg = 0x31c,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 64,
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
.fifo_size = 16 * 24,
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
.fifo_size = 16 * 24,
}, {
.id = 0x3a,
.name = "mpecswr",
.swgroup = TEGRA_SWGROUP_MPE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 26,
},
.la = {
.reg = 0x330,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 8,
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 27,
},
.la = {
.reg = 0x348,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 28,
},
.la = {
.reg = 0x348,
.shift = 16,
.mask = 0xff,
.def = 0x06,
},
},
.fifo_size = 16 * 4,
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 29,
},
.la = {
.reg = 0x350,
.shift = 16,
.mask = 0xff,
.def = 0x33,
},
},
.fifo_size = 16 * 32,
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 30,
},
.la = {
.reg = 0x35c,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 4,
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 31,
},
.la = {
.reg = 0x35c,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
.fifo_size = 16 * 16,
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 0,
},
.la = {
.reg = 0x360,
.shift = 0,
.mask = 0xff,
.def = 0x42,
},
},
.fifo_size = 16 * 2,
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 1,
},
.la = {
.reg = 0x360,
.shift = 16,
.mask = 0xff,
.def = 0x2a,
},
},
.fifo_size = 16 * 16,
},
};
static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
};
static const unsigned int tegra30_group_drm[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
TEGRA_SWGROUP_G2,
TEGRA_SWGROUP_NV,
TEGRA_SWGROUP_NV2,
};
static const struct tegra_smmu_group_soc tegra30_groups[] = {
{
.name = "drm",
.swgroups = tegra30_group_drm,
.num_swgroups = ARRAY_SIZE(tegra30_group_drm),
},
};
static const struct tegra_smmu_soc tegra30_smmu_soc = {
.clients = tegra30_mc_clients,
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
.swgroups = tegra30_swgroups,
.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
.groups = tegra30_groups,
.num_groups = ARRAY_SIZE(tegra30_groups),
.supports_round_robin_arbitration = false,
.supports_request_limit = false,
.num_tlb_lines = 16,
.num_asids = 4,
};
#define TEGRA30_MC_RESET(_name, _control, _status, _bit) \
{ \
.name = #_name, \
.id = TEGRA30_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra30_mc_resets[] = {
TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
};
static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,
const struct tegra_mc_client *client,
unsigned int bandwidth_mbytes_sec)
{
u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
unsigned int fifo_size = client->fifo_size;
u32 arb_nsec, la_ticks, value;
/* see 18.4.1 Client Configuration in Tegra3 TRM v03p */
if (bandwidth_mbytes_sec)
arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;
else
arb_nsec = U32_MAX;
/*
* Latency allowness should be set with consideration for the module's
* latency tolerance and internal buffering capabilities.
*
* Display memory clients use isochronous transfers and have very low
* tolerance to a belated transfers. Hence we need to compensate the
* memory arbitration imperfection for them in order to prevent FIFO
* underflow condition when memory bus is busy.
*
* VI clients also need a stronger compensation.
*/
switch (client->swgroup) {
case TEGRA_SWGROUP_MPCORE:
case TEGRA_SWGROUP_PTC:
/*
* We always want lower latency for these clients, hence
* don't touch them.
*/
return;
case TEGRA_SWGROUP_DC:
case TEGRA_SWGROUP_DCB:
arb_tolerance_compensation_nsec = 1050;
arb_tolerance_compensation_div = 2;
break;
case TEGRA_SWGROUP_VI:
arb_tolerance_compensation_nsec = 1050;
arb_tolerance_compensation_div = 1;
break;
default:
arb_tolerance_compensation_nsec = 150;
arb_tolerance_compensation_div = 1;
break;
}
if (arb_nsec > arb_tolerance_compensation_nsec)
arb_nsec -= arb_tolerance_compensation_nsec;
else
arb_nsec = 0;
arb_nsec /= arb_tolerance_compensation_div;
/*
* Latency allowance is a number of ticks a request from a particular
* client may wait in the EMEM arbiter before it becomes a high-priority
* request.
*/
la_ticks = arb_nsec / mc->tick;
la_ticks = min(la_ticks, client->regs.la.mask);
value = mc_readl(mc, client->regs.la.reg);
value &= ~(client->regs.la.mask << client->regs.la.shift);
value |= la_ticks << client->regs.la.shift;
mc_writel(mc, value, client->regs.la.reg);
}
static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);
const struct tegra_mc_client *client = &mc->soc->clients[src->id];
u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);
/*
* Skip pre-initialization that is done by icc_node_add(), which sets
* bandwidth to maximum for all clients before drivers are loaded.
*
* This doesn't make sense for us because we don't have drivers for all
* clients and it's okay to keep configuration left from bootloader
* during boot, at least for today.
*/
if (src == dst)
return 0;
/* convert bytes/sec to megabytes/sec */
do_div(peak_bandwidth, 1000000);
tegra30_mc_tune_client_latency(mc, client, peak_bandwidth);
return 0;
}
static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{
/*
* ISO clients need to reserve extra bandwidth up-front because
* there could be high bandwidth pressure during initial filling
* of the client's FIFO buffers. Secondly, we need to take into
* account impurities of the memory subsystem.
*/
if (tag & TEGRA_MC_ICC_TAG_ISO)
peak_bw = tegra_mc_scale_percents(peak_bw, 400);
*agg_avg += avg_bw;
*agg_peak = max(*agg_peak, peak_bw);
return 0;
}
static struct icc_node_data *
tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
const struct tegra_mc_client *client;
unsigned int i, idx = spec->args[0];
struct icc_node_data *ndata;
struct icc_node *node;
list_for_each_entry(node, &mc->provider.nodes, node_list) {
if (node->id != idx)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
client = &mc->soc->clients[idx];
ndata->node = node;
switch (client->swgroup) {
case TEGRA_SWGROUP_DC:
case TEGRA_SWGROUP_DCB:
case TEGRA_SWGROUP_PTC:
case TEGRA_SWGROUP_VI:
/* these clients are isochronous by default */
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
break;
default:
ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
break;
}
return ndata;
}
for (i = 0; i < mc->soc->num_clients; i++) {
if (mc->soc->clients[i].id == idx)
return ERR_PTR(-EPROBE_DEFER);
}
dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
return ERR_PTR(-EINVAL);
}
static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = {
.xlate_extended = tegra30_mc_of_icc_xlate_extended,
.aggregate = tegra30_mc_icc_aggreate,
.set = tegra30_mc_icc_set,
};
const struct tegra_mc_soc tegra30_mc_soc = {
.clients = tegra30_mc_clients,
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
.num_address_bits = 32,
.atom_size = 16,
.client_id_mask = 0x7f,
.smmu = &tegra30_smmu_soc,
.emem_regs = tegra30_mc_emem_regs,
.num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM,
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra30_mc_resets,
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
.icc_ops = &tegra30_mc_icc_ops,
.ops = &tegra30_mc_ops,
};
|
linux-master
|
drivers/memory/tegra/tegra30.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Tegra30 External Memory Controller driver
*
* Based on downstream driver from NVIDIA and tegra124-emc.c
* Copyright (C) 2011-2014 NVIDIA Corporation
*
* Author: Dmitry Osipenko <[email protected]>
* Copyright (C) 2019 GRATE-DRIVER project
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interconnect-provider.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <linux/types.h>
#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
#include "../jedec_ddr.h"
#include "../of_memory.h"
#include "mc.h"
#define EMC_INTSTATUS 0x000
#define EMC_INTMASK 0x004
#define EMC_DBG 0x008
#define EMC_ADR_CFG 0x010
#define EMC_CFG 0x00c
#define EMC_REFCTRL 0x020
#define EMC_TIMING_CONTROL 0x028
#define EMC_RC 0x02c
#define EMC_RFC 0x030
#define EMC_RAS 0x034
#define EMC_RP 0x038
#define EMC_R2W 0x03c
#define EMC_W2R 0x040
#define EMC_R2P 0x044
#define EMC_W2P 0x048
#define EMC_RD_RCD 0x04c
#define EMC_WR_RCD 0x050
#define EMC_RRD 0x054
#define EMC_REXT 0x058
#define EMC_WDV 0x05c
#define EMC_QUSE 0x060
#define EMC_QRST 0x064
#define EMC_QSAFE 0x068
#define EMC_RDV 0x06c
#define EMC_REFRESH 0x070
#define EMC_BURST_REFRESH_NUM 0x074
#define EMC_PDEX2WR 0x078
#define EMC_PDEX2RD 0x07c
#define EMC_PCHG2PDEN 0x080
#define EMC_ACT2PDEN 0x084
#define EMC_AR2PDEN 0x088
#define EMC_RW2PDEN 0x08c
#define EMC_TXSR 0x090
#define EMC_TCKE 0x094
#define EMC_TFAW 0x098
#define EMC_TRPAB 0x09c
#define EMC_TCLKSTABLE 0x0a0
#define EMC_TCLKSTOP 0x0a4
#define EMC_TREFBW 0x0a8
#define EMC_QUSE_EXTRA 0x0ac
#define EMC_ODT_WRITE 0x0b0
#define EMC_ODT_READ 0x0b4
#define EMC_WEXT 0x0b8
#define EMC_CTT 0x0bc
#define EMC_MRS_WAIT_CNT 0x0c8
#define EMC_MRS 0x0cc
#define EMC_EMRS 0x0d0
#define EMC_SELF_REF 0x0e0
#define EMC_MRW 0x0e8
#define EMC_MRR 0x0ec
#define EMC_XM2DQSPADCTRL3 0x0f8
#define EMC_FBIO_SPARE 0x100
#define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG6 0x114
#define EMC_CFG_RSV 0x120
#define EMC_AUTO_CAL_CONFIG 0x2a4
#define EMC_AUTO_CAL_INTERVAL 0x2a8
#define EMC_AUTO_CAL_STATUS 0x2ac
#define EMC_STATUS 0x2b4
#define EMC_CFG_2 0x2b8
#define EMC_CFG_DIG_DLL 0x2bc
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_CTT_DURATION 0x2d8
#define EMC_CTT_TERM_CTRL 0x2dc
#define EMC_ZCAL_INTERVAL 0x2e0
#define EMC_ZCAL_WAIT_CNT 0x2e4
#define EMC_ZQ_CAL 0x2ec
#define EMC_XM2CMDPADCTRL 0x2f0
#define EMC_XM2DQSPADCTRL2 0x2fc
#define EMC_XM2DQPADCTRL2 0x304
#define EMC_XM2CLKPADCTRL 0x308
#define EMC_XM2COMPPADCTRL 0x30c
#define EMC_XM2VTTGENPADCTRL 0x310
#define EMC_XM2VTTGENPADCTRL2 0x314
#define EMC_XM2QUSEPADCTRL 0x318
#define EMC_DLL_XFORM_DQS0 0x328
#define EMC_DLL_XFORM_DQS1 0x32c
#define EMC_DLL_XFORM_DQS2 0x330
#define EMC_DLL_XFORM_DQS3 0x334
#define EMC_DLL_XFORM_DQS4 0x338
#define EMC_DLL_XFORM_DQS5 0x33c
#define EMC_DLL_XFORM_DQS6 0x340
#define EMC_DLL_XFORM_DQS7 0x344
#define EMC_DLL_XFORM_QUSE0 0x348
#define EMC_DLL_XFORM_QUSE1 0x34c
#define EMC_DLL_XFORM_QUSE2 0x350
#define EMC_DLL_XFORM_QUSE3 0x354
#define EMC_DLL_XFORM_QUSE4 0x358
#define EMC_DLL_XFORM_QUSE5 0x35c
#define EMC_DLL_XFORM_QUSE6 0x360
#define EMC_DLL_XFORM_QUSE7 0x364
#define EMC_DLL_XFORM_DQ0 0x368
#define EMC_DLL_XFORM_DQ1 0x36c
#define EMC_DLL_XFORM_DQ2 0x370
#define EMC_DLL_XFORM_DQ3 0x374
#define EMC_DLI_TRIM_TXDQS0 0x3a8
#define EMC_DLI_TRIM_TXDQS1 0x3ac
#define EMC_DLI_TRIM_TXDQS2 0x3b0
#define EMC_DLI_TRIM_TXDQS3 0x3b4
#define EMC_DLI_TRIM_TXDQS4 0x3b8
#define EMC_DLI_TRIM_TXDQS5 0x3bc
#define EMC_DLI_TRIM_TXDQS6 0x3c0
#define EMC_DLI_TRIM_TXDQS7 0x3c4
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
#define EMC_SEL_DPD_CTRL 0x3d8
#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
#define EMC_DYN_SELF_REF_CONTROL 0x3e0
#define EMC_TXSRDLL 0x3e4
#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
#define EMC_MODE_SET_DLL_RESET BIT(8)
#define EMC_MODE_SET_LONG_CNT BIT(26)
#define EMC_SELF_REF_CMD_ENABLED BIT(0)
#define DRAM_DEV_SEL_ALL (0 << 30)
#define DRAM_DEV_SEL_0 BIT(31)
#define DRAM_DEV_SEL_1 BIT(30)
#define DRAM_BROADCAST(num) \
((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
#define EMC_ZQ_CAL_CMD BIT(0)
#define EMC_ZQ_CAL_LONG BIT(4)
#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
#define EMC_DBG_FORCE_UPDATE BIT(2)
#define EMC_DBG_CFG_PRIORITY BIT(24)
#define EMC_CFG5_QUSE_MODE_SHIFT 13
#define EMC_CFG5_QUSE_MODE_MASK (7 << EMC_CFG5_QUSE_MODE_SHIFT)
#define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK 2
#define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3
#define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE BIT(9)
#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE BIT(10)
#define EMC_XM2QUSEPADCTRL_IVREF_ENABLE BIT(4)
#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
#define EMC_XM2DQSPADCTRL3_VREF_ENABLE BIT(5)
#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff
#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
(0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
#define EMC_REFCTRL_DEV_SEL_MASK 0x3
#define EMC_REFCTRL_ENABLE BIT(31)
#define EMC_REFCTRL_ENABLE_ALL(num) \
(((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
#define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
#define EMC_CFG_PERIODIC_QRST BIT(21)
#define EMC_CFG_DYN_SREF_ENABLE BIT(28)
#define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
#define EMC_CLKCHANGE_PD_ENABLE BIT(1)
#define EMC_CLKCHANGE_SR_ENABLE BIT(2)
#define EMC_TIMING_UPDATE BIT(0)
#define EMC_REFRESH_OVERFLOW_INT BIT(3)
#define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
#define EMC_MRR_DIVLD_INT BIT(5)
#define EMC_MRR_DEV_SELECTN GENMASK(31, 30)
#define EMC_MRR_MRR_MA GENMASK(23, 16)
#define EMC_MRR_MRR_DATA GENMASK(15, 0)
#define EMC_ADR_CFG_EMEM_NUMDEV BIT(0)
enum emc_dram_type {
DRAM_TYPE_DDR3,
DRAM_TYPE_DDR1,
DRAM_TYPE_LPDDR2,
DRAM_TYPE_DDR2,
};
enum emc_dll_change {
DLL_CHANGE_NONE,
DLL_CHANGE_ON,
DLL_CHANGE_OFF
};
static const u16 emc_timing_registers[] = {
[0] = EMC_RC,
[1] = EMC_RFC,
[2] = EMC_RAS,
[3] = EMC_RP,
[4] = EMC_R2W,
[5] = EMC_W2R,
[6] = EMC_R2P,
[7] = EMC_W2P,
[8] = EMC_RD_RCD,
[9] = EMC_WR_RCD,
[10] = EMC_RRD,
[11] = EMC_REXT,
[12] = EMC_WEXT,
[13] = EMC_WDV,
[14] = EMC_QUSE,
[15] = EMC_QRST,
[16] = EMC_QSAFE,
[17] = EMC_RDV,
[18] = EMC_REFRESH,
[19] = EMC_BURST_REFRESH_NUM,
[20] = EMC_PRE_REFRESH_REQ_CNT,
[21] = EMC_PDEX2WR,
[22] = EMC_PDEX2RD,
[23] = EMC_PCHG2PDEN,
[24] = EMC_ACT2PDEN,
[25] = EMC_AR2PDEN,
[26] = EMC_RW2PDEN,
[27] = EMC_TXSR,
[28] = EMC_TXSRDLL,
[29] = EMC_TCKE,
[30] = EMC_TFAW,
[31] = EMC_TRPAB,
[32] = EMC_TCLKSTABLE,
[33] = EMC_TCLKSTOP,
[34] = EMC_TREFBW,
[35] = EMC_QUSE_EXTRA,
[36] = EMC_FBIO_CFG6,
[37] = EMC_ODT_WRITE,
[38] = EMC_ODT_READ,
[39] = EMC_FBIO_CFG5,
[40] = EMC_CFG_DIG_DLL,
[41] = EMC_CFG_DIG_DLL_PERIOD,
[42] = EMC_DLL_XFORM_DQS0,
[43] = EMC_DLL_XFORM_DQS1,
[44] = EMC_DLL_XFORM_DQS2,
[45] = EMC_DLL_XFORM_DQS3,
[46] = EMC_DLL_XFORM_DQS4,
[47] = EMC_DLL_XFORM_DQS5,
[48] = EMC_DLL_XFORM_DQS6,
[49] = EMC_DLL_XFORM_DQS7,
[50] = EMC_DLL_XFORM_QUSE0,
[51] = EMC_DLL_XFORM_QUSE1,
[52] = EMC_DLL_XFORM_QUSE2,
[53] = EMC_DLL_XFORM_QUSE3,
[54] = EMC_DLL_XFORM_QUSE4,
[55] = EMC_DLL_XFORM_QUSE5,
[56] = EMC_DLL_XFORM_QUSE6,
[57] = EMC_DLL_XFORM_QUSE7,
[58] = EMC_DLI_TRIM_TXDQS0,
[59] = EMC_DLI_TRIM_TXDQS1,
[60] = EMC_DLI_TRIM_TXDQS2,
[61] = EMC_DLI_TRIM_TXDQS3,
[62] = EMC_DLI_TRIM_TXDQS4,
[63] = EMC_DLI_TRIM_TXDQS5,
[64] = EMC_DLI_TRIM_TXDQS6,
[65] = EMC_DLI_TRIM_TXDQS7,
[66] = EMC_DLL_XFORM_DQ0,
[67] = EMC_DLL_XFORM_DQ1,
[68] = EMC_DLL_XFORM_DQ2,
[69] = EMC_DLL_XFORM_DQ3,
[70] = EMC_XM2CMDPADCTRL,
[71] = EMC_XM2DQSPADCTRL2,
[72] = EMC_XM2DQPADCTRL2,
[73] = EMC_XM2CLKPADCTRL,
[74] = EMC_XM2COMPPADCTRL,
[75] = EMC_XM2VTTGENPADCTRL,
[76] = EMC_XM2VTTGENPADCTRL2,
[77] = EMC_XM2QUSEPADCTRL,
[78] = EMC_XM2DQSPADCTRL3,
[79] = EMC_CTT_TERM_CTRL,
[80] = EMC_ZCAL_INTERVAL,
[81] = EMC_ZCAL_WAIT_CNT,
[82] = EMC_MRS_WAIT_CNT,
[83] = EMC_AUTO_CAL_CONFIG,
[84] = EMC_CTT,
[85] = EMC_CTT_DURATION,
[86] = EMC_DYN_SELF_REF_CONTROL,
[87] = EMC_FBIO_SPARE,
[88] = EMC_CFG_RSV,
};
struct emc_timing {
unsigned long rate;
u32 data[ARRAY_SIZE(emc_timing_registers)];
u32 emc_auto_cal_interval;
u32 emc_mode_1;
u32 emc_mode_2;
u32 emc_mode_reset;
u32 emc_zcal_cnt_long;
bool emc_cfg_periodic_qrst;
bool emc_cfg_dyn_self_ref;
};
enum emc_rate_request_type {
EMC_RATE_DEBUG,
EMC_RATE_ICC,
EMC_RATE_TYPE_MAX,
};
struct emc_rate_request {
unsigned long min_rate;
unsigned long max_rate;
};
struct tegra_emc {
struct device *dev;
struct tegra_mc *mc;
struct icc_provider provider;
struct notifier_block clk_nb;
struct clk *clk;
void __iomem *regs;
unsigned int irq;
bool bad_state;
struct emc_timing *new_timing;
struct emc_timing *timings;
unsigned int num_timings;
u32 mc_override;
u32 emc_cfg;
u32 emc_mode_1;
u32 emc_mode_2;
u32 emc_mode_reset;
bool vref_cal_toggle : 1;
bool zcal_long : 1;
bool dll_on : 1;
struct {
struct dentry *root;
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
/*
* There are multiple sources in the EMC driver which could request
* a min/max clock rate, these rates are contained in this array.
*/
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
/* protect shared rate-change code path */
struct mutex rate_lock;
bool mrr_error;
};
static int emc_seq_update_timing(struct tegra_emc *emc)
{
u32 val;
int err;
writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
!(val & EMC_STATUS_TIMING_UPDATE_STALLED),
1, 200);
if (err) {
dev_err(emc->dev, "failed to update timing: %d\n", err);
return err;
}
return 0;
}
static irqreturn_t tegra_emc_isr(int irq, void *data)
{
struct tegra_emc *emc = data;
u32 intmask = EMC_REFRESH_OVERFLOW_INT;
u32 status;
status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
if (!status)
return IRQ_NONE;
/* notify about HW problem */
if (status & EMC_REFRESH_OVERFLOW_INT)
dev_err_ratelimited(emc->dev,
"refresh request overflow timeout\n");
/* clear interrupts */
writel_relaxed(status, emc->regs + EMC_INTSTATUS);
return IRQ_HANDLED;
}
static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = NULL;
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate >= rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu\n", rate);
return NULL;
}
return timing;
}
static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
bool *schmitt_to_vref)
{
bool preset = false;
u32 val;
if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
preset = true;
}
}
if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) {
val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE;
writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
preset = true;
}
}
if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) {
val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE;
writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
*schmitt_to_vref = true;
preset = true;
}
}
return preset;
}
static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
{
struct tegra_mc *mc = emc->mc;
unsigned int misc0_index = 16;
unsigned int i;
bool same;
for (i = 0; i < mc->num_timings; i++) {
if (mc->timings[i].rate != rate)
continue;
if (mc->timings[i].emem_data[misc0_index] & BIT(27))
same = true;
else
same = false;
return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
}
return -EINVAL;
}
static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
{
struct emc_timing *timing = emc_find_timing(emc, rate);
enum emc_dll_change dll_change;
enum emc_dram_type dram_type;
bool schmitt_to_vref = false;
unsigned int pre_wait = 0;
bool qrst_used = false;
unsigned int dram_num;
unsigned int i;
u32 fbio_cfg5;
u32 emc_dbg;
u32 val;
int err;
if (!timing || emc->bad_state)
return -EINVAL;
dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
__func__, timing->rate, rate);
emc->bad_state = true;
err = emc_prepare_mc_clk_cfg(emc, rate);
if (err) {
dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
return err;
}
emc->vref_cal_toggle = false;
emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
dll_change = DLL_CHANGE_NONE;
else if (timing->emc_mode_1 & 0x1)
dll_change = DLL_CHANGE_ON;
else
dll_change = DLL_CHANGE_OFF;
emc->dll_on = !!(timing->emc_mode_1 & 0x1);
if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
emc->zcal_long = true;
else
emc->zcal_long = false;
fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
dram_num = tegra_mc_get_emem_device_count(emc->mc);
/* disable dynamic self-refresh */
if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
pre_wait = 5;
}
/* update MC arbiter settings */
val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) ||
((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) {
val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE |
MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50;
mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
}
if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
mc_writel(emc->mc,
emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
MC_EMEM_ARB_OVERRIDE);
/* check DQ/DQS VREF delay */
if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
if (pre_wait < 3)
pre_wait = 3;
}
if (pre_wait) {
err = emc_seq_update_timing(emc);
if (err)
return err;
udelay(pre_wait);
}
/* disable auto-calibration if VREF mode is switching */
if (timing->emc_auto_cal_interval) {
val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
val ^= timing->data[74];
if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) {
writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
err = readl_relaxed_poll_timeout_atomic(
emc->regs + EMC_AUTO_CAL_STATUS, val,
!(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300);
if (err) {
dev_err(emc->dev,
"auto-cal finish timeout: %d\n", err);
return err;
}
emc->vref_cal_toggle = true;
}
}
/* program shadow registers */
for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
/* EMC_XM2CLKPADCTRL should be programmed separately */
if (i != 73)
writel_relaxed(timing->data[i],
emc->regs + emc_timing_registers[i]);
}
err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
if (err)
return err;
/* DDR3: predict MRS long wait count */
if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) {
u32 cnt = 512;
if (emc->zcal_long)
cnt -= dram_num * 256;
val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
if (cnt < val)
cnt = val;
val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
}
/* this read also completes the writes */
val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) {
u32 cur_mode, new_mode;
cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK;
cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) ||
(new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK))
qrst_used = true;
}
/* flow control marker 1 */
writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
/* enable periodic reset */
if (qrst_used) {
writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
emc->regs + EMC_DBG);
writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
emc->regs + EMC_CFG);
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
}
/* disable auto-refresh to save time after clock change */
writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
emc->regs + EMC_REFCTRL);
/* turn off DLL and enter self-refresh on DDR3 */
if (dram_type == DRAM_TYPE_DDR3) {
if (dll_change == DLL_CHANGE_OFF)
writel_relaxed(timing->emc_mode_1,
emc->regs + EMC_EMRS);
writel_relaxed(DRAM_BROADCAST(dram_num) |
EMC_SELF_REF_CMD_ENABLED,
emc->regs + EMC_SELF_REF);
}
/* flow control marker 2 */
writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
/* enable write-active MUX, update unshadowed pad control */
writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
/* restore periodic QRST and disable write-active MUX */
val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
if (timing->emc_cfg_periodic_qrst)
emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
else
emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
}
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
/* exit self-refresh on DDR3 */
if (dram_type == DRAM_TYPE_DDR3)
writel_relaxed(DRAM_BROADCAST(dram_num),
emc->regs + EMC_SELF_REF);
/* set DRAM-mode registers */
if (dram_type == DRAM_TYPE_DDR3) {
if (timing->emc_mode_1 != emc->emc_mode_1)
writel_relaxed(timing->emc_mode_1,
emc->regs + EMC_EMRS);
if (timing->emc_mode_2 != emc->emc_mode_2)
writel_relaxed(timing->emc_mode_2,
emc->regs + EMC_EMRS);
if (timing->emc_mode_reset != emc->emc_mode_reset ||
dll_change == DLL_CHANGE_ON) {
val = timing->emc_mode_reset;
if (dll_change == DLL_CHANGE_ON) {
val |= EMC_MODE_SET_DLL_RESET;
val |= EMC_MODE_SET_LONG_CNT;
} else {
val &= ~EMC_MODE_SET_DLL_RESET;
}
writel_relaxed(val, emc->regs + EMC_MRS);
}
} else {
if (timing->emc_mode_2 != emc->emc_mode_2)
writel_relaxed(timing->emc_mode_2,
emc->regs + EMC_MRW);
if (timing->emc_mode_1 != emc->emc_mode_1)
writel_relaxed(timing->emc_mode_1,
emc->regs + EMC_MRW);
}
emc->emc_mode_1 = timing->emc_mode_1;
emc->emc_mode_2 = timing->emc_mode_2;
emc->emc_mode_reset = timing->emc_mode_reset;
/* issue ZCAL command if turning ZCAL on */
if (emc->zcal_long) {
writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
emc->regs + EMC_ZQ_CAL);
if (dram_num > 1)
writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
emc->regs + EMC_ZQ_CAL);
}
/* flow control marker 3 */
writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
/*
* Read and discard an arbitrary MC register (Note: EMC registers
* can't be used) to ensure the register writes are completed.
*/
mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
return 0;
}
static int emc_complete_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
struct emc_timing *timing = emc_find_timing(emc, rate);
unsigned int dram_num;
int err;
u32 v;
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
v & EMC_CLKCHANGE_COMPLETE_INT,
1, 100);
if (err) {
dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
return err;
}
/* re-enable auto-refresh */
dram_num = tegra_mc_get_emem_device_count(emc->mc);
writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
emc->regs + EMC_REFCTRL);
/* restore auto-calibration */
if (emc->vref_cal_toggle)
writel_relaxed(timing->emc_auto_cal_interval,
emc->regs + EMC_AUTO_CAL_INTERVAL);
/* restore dynamic self-refresh */
if (timing->emc_cfg_dyn_self_ref) {
emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
}
/* set number of clocks to wait after each ZQ command */
if (emc->zcal_long)
writel_relaxed(timing->emc_zcal_cnt_long,
emc->regs + EMC_ZCAL_WAIT_CNT);
/* wait for writes to settle */
udelay(2);
/* update restored timing */
err = emc_seq_update_timing(emc);
if (!err)
emc->bad_state = false;
/* restore early ACK */
mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
return err;
}
static int emc_unprepare_timing_change(struct tegra_emc *emc,
unsigned long rate)
{
if (!emc->bad_state) {
/* shouldn't ever happen in practice */
dev_err(emc->dev, "timing configuration can't be reverted\n");
emc->bad_state = true;
}
return 0;
}
static int emc_clk_change_notify(struct notifier_block *nb,
unsigned long msg, void *data)
{
struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
struct clk_notifier_data *cnd = data;
int err;
switch (msg) {
case PRE_RATE_CHANGE:
/*
* Disable interrupt since read accesses are prohibited after
* stalling.
*/
disable_irq(emc->irq);
err = emc_prepare_timing_change(emc, cnd->new_rate);
enable_irq(emc->irq);
break;
case ABORT_RATE_CHANGE:
err = emc_unprepare_timing_change(emc, cnd->old_rate);
break;
case POST_RATE_CHANGE:
err = emc_complete_timing_change(emc, cnd->new_rate);
break;
default:
return NOTIFY_DONE;
}
return notifier_from_errno(err);
}
static int load_one_timing_from_dt(struct tegra_emc *emc,
struct emc_timing *timing,
struct device_node *node)
{
u32 value;
int err;
err = of_property_read_u32(node, "clock-frequency", &value);
if (err) {
dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
node, err);
return err;
}
timing->rate = value;
err = of_property_read_u32_array(node, "nvidia,emc-configuration",
timing->data,
ARRAY_SIZE(emc_timing_registers));
if (err) {
dev_err(emc->dev,
"timing %pOF: failed to read emc timing data: %d\n",
node, err);
return err;
}
#define EMC_READ_BOOL(prop, dtprop) \
timing->prop = of_property_read_bool(node, dtprop);
#define EMC_READ_U32(prop, dtprop) \
err = of_property_read_u32(node, dtprop, &timing->prop); \
if (err) { \
dev_err(emc->dev, \
"timing %pOFn: failed to read " #prop ": %d\n", \
node, err); \
return err; \
}
EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
#undef EMC_READ_U32
#undef EMC_READ_BOOL
dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
return 0;
}
static int cmp_timings(const void *_a, const void *_b)
{
const struct emc_timing *a = _a;
const struct emc_timing *b = _b;
if (a->rate < b->rate)
return -1;
if (a->rate > b->rate)
return 1;
return 0;
}
static int emc_check_mc_timings(struct tegra_emc *emc)
{
struct tegra_mc *mc = emc->mc;
unsigned int i;
if (emc->num_timings != mc->num_timings) {
dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
emc->num_timings, mc->num_timings);
return -EINVAL;
}
for (i = 0; i < mc->num_timings; i++) {
if (emc->timings[i].rate != mc->timings[i].rate) {
dev_err(emc->dev,
"emc/mc timing rate mismatch: %lu %lu\n",
emc->timings[i].rate, mc->timings[i].rate);
return -EINVAL;
}
}
return 0;
}
static int emc_load_timings_from_dt(struct tegra_emc *emc,
struct device_node *node)
{
struct device_node *child;
struct emc_timing *timing;
int child_count;
int err;
child_count = of_get_child_count(node);
if (!child_count) {
dev_err(emc->dev, "no memory timings in: %pOF\n", node);
return -EINVAL;
}
emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!emc->timings)
return -ENOMEM;
emc->num_timings = child_count;
timing = emc->timings;
for_each_child_of_node(node, child) {
err = load_one_timing_from_dt(emc, timing++, child);
if (err) {
of_node_put(child);
return err;
}
}
sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
NULL);
err = emc_check_mc_timings(emc);
if (err)
return err;
dev_info_once(emc->dev,
"got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
emc->num_timings,
tegra_read_ram_code(),
emc->timings[0].rate / 1000000,
emc->timings[emc->num_timings - 1].rate / 1000000);
return 0;
}
static struct device_node *emc_find_node_by_ram_code(struct tegra_emc *emc)
{
struct device *dev = emc->dev;
struct device_node *np;
u32 value, ram_code;
int err;
if (emc->mrr_error) {
dev_warn(dev, "memory timings skipped due to MRR error\n");
return NULL;
}
if (of_get_child_count(dev->of_node) == 0) {
dev_info_once(dev, "device-tree doesn't have memory timings\n");
return NULL;
}
ram_code = tegra_read_ram_code();
for_each_child_of_node(dev->of_node, np) {
err = of_property_read_u32(np, "nvidia,ram-code", &value);
if (err || value != ram_code)
continue;
return np;
}
dev_err(dev, "no memory timings for RAM code %u found in device-tree\n",
ram_code);
return NULL;
}
static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
unsigned int emem_dev,
unsigned int register_addr,
unsigned int *register_data)
{
u32 memory_dev = emem_dev ? 1 : 2;
u32 val, mr_mask = 0xff;
int err;
/* clear data-valid interrupt status */
writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
/* issue mode register read request */
val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev);
val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr);
writel_relaxed(val, emc->regs + EMC_MRR);
/* wait for the LPDDR2 data-valid interrupt */
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
val & EMC_MRR_DIVLD_INT,
1, 100);
if (err) {
dev_err(emc->dev, "mode register %u read failed: %d\n",
register_addr, err);
emc->mrr_error = true;
return err;
}
/* read out mode register data */
val = readl_relaxed(emc->regs + EMC_MRR);
*register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask;
return 0;
}
static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
unsigned int emem_dev)
{
union lpddr2_basic_config4 basic_conf4;
unsigned int manufacturer_id;
unsigned int revision_id1;
unsigned int revision_id2;
/* these registers are standard for all LPDDR JEDEC memory chips */
emc_read_lpddr_mode_register(emc, emem_dev, 5, &manufacturer_id);
emc_read_lpddr_mode_register(emc, emem_dev, 6, &revision_id1);
emc_read_lpddr_mode_register(emc, emem_dev, 7, &revision_id2);
emc_read_lpddr_mode_register(emc, emem_dev, 8, &basic_conf4.value);
dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
emem_dev, manufacturer_id,
lpddr2_jedec_manufacturer(manufacturer_id),
revision_id1, revision_id2,
4 >> basic_conf4.arch_type,
64 << basic_conf4.density,
32 >> basic_conf4.io_width);
}
static int emc_setup_hw(struct tegra_emc *emc)
{
u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg;
u32 intmask = EMC_REFRESH_OVERFLOW_INT;
static bool print_sdram_info_once;
enum emc_dram_type dram_type;
const char *dram_type_str;
unsigned int emem_numdev;
fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
/* enable EMC and CAR to handshake on PLL divider/source changes */
emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
/* configure clock change mode accordingly to DRAM type */
switch (dram_type) {
case DRAM_TYPE_LPDDR2:
emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;
emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
break;
default:
emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;
break;
}
writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
/* initialize interrupt */
writel_relaxed(intmask, emc->regs + EMC_INTMASK);
writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
/* ensure that unwanted debug features are disabled */
emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
emc_dbg |= EMC_DBG_CFG_PRIORITY;
emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
switch (dram_type) {
case DRAM_TYPE_DDR1:
dram_type_str = "DDR1";
break;
case DRAM_TYPE_LPDDR2:
dram_type_str = "LPDDR2";
break;
case DRAM_TYPE_DDR2:
dram_type_str = "DDR2";
break;
case DRAM_TYPE_DDR3:
dram_type_str = "DDR3";
break;
}
emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG);
emem_numdev = FIELD_GET(EMC_ADR_CFG_EMEM_NUMDEV, emc_adr_cfg) + 1;
dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev,
dram_type_str, emem_numdev == 2 ? "devices" : "device");
if (dram_type == DRAM_TYPE_LPDDR2 && !print_sdram_info_once) {
while (emem_numdev--)
emc_read_lpddr_sdram_info(emc, emem_numdev);
print_sdram_info_once = true;
}
return 0;
}
static long emc_round_rate(unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
void *arg)
{
struct emc_timing *timing = NULL;
struct tegra_emc *emc = arg;
unsigned int i;
if (!emc->num_timings)
return clk_get_rate(emc->clk);
min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
continue;
if (emc->timings[i].rate > max_rate) {
i = max(i, 1u) - 1;
if (emc->timings[i].rate < min_rate)
break;
}
if (emc->timings[i].rate < min_rate)
continue;
timing = &emc->timings[i];
break;
}
if (!timing) {
dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
rate, min_rate, max_rate);
return -EINVAL;
}
return timing->rate;
}
static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
{
unsigned int i;
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
emc->requested_rate[i].min_rate = 0;
emc->requested_rate[i].max_rate = ULONG_MAX;
}
}
static int emc_request_rate(struct tegra_emc *emc,
unsigned long new_min_rate,
unsigned long new_max_rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = emc->requested_rate;
unsigned long min_rate = 0, max_rate = ULONG_MAX;
unsigned int i;
int err;
/* select minimum and maximum rates among the requested rates */
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
if (i == type) {
min_rate = max(new_min_rate, min_rate);
max_rate = min(new_max_rate, max_rate);
} else {
min_rate = max(req->min_rate, min_rate);
max_rate = min(req->max_rate, max_rate);
}
}
if (min_rate > max_rate) {
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
__func__, type, min_rate, max_rate);
return -ERANGE;
}
/*
* EMC rate-changes should go via OPP API because it manages voltage
* changes.
*/
err = dev_pm_opp_set_rate(emc->dev, min_rate);
if (err)
return err;
emc->requested_rate[type].min_rate = new_min_rate;
emc->requested_rate[type].max_rate = new_max_rate;
return 0;
}
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, rate, req->max_rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
enum emc_rate_request_type type)
{
struct emc_rate_request *req = &emc->requested_rate[type];
int ret;
mutex_lock(&emc->rate_lock);
ret = emc_request_rate(emc, req->min_rate, rate, type);
mutex_unlock(&emc->rate_lock);
return ret;
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (rate == emc->timings[i].rate)
return true;
return false;
}
static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
{
struct tegra_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
tegra_emc_debug_min_rate_get,
tegra_emc_debug_min_rate_set, "%llu\n");
static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra_emc *emc = data;
int err;
if (!tegra_emc_validate_rate(emc, rate))
return -EINVAL;
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
tegra_emc_debug_max_rate_get,
tegra_emc_debug_max_rate_set, "%llu\n");
static void tegra_emc_debugfs_init(struct tegra_emc *emc)
{
struct device *dev = emc->dev;
unsigned int i;
int err;
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->timings[i].rate;
if (emc->timings[i].rate > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->timings[i].rate;
}
if (!emc->num_timings) {
emc->debugfs.min_rate = clk_get_rate(emc->clk);
emc->debugfs.max_rate = emc->debugfs.min_rate;
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root,
emc, &tegra_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root,
emc, &tegra_emc_debug_max_rate_fops);
}
static inline struct tegra_emc *
to_tegra_emc_provider(struct icc_provider *provider)
{
return container_of(provider, struct tegra_emc, provider);
}
static struct icc_node_data *
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct icc_provider *provider = data;
struct icc_node_data *ndata;
struct icc_node *node;
/* External Memory is the only possible ICC route */
list_for_each_entry(node, &provider->nodes, node_list) {
if (node->id != TEGRA_ICC_EMEM)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
/*
* SRC and DST nodes should have matching TAG in order to have
* it set by default for a requested path.
*/
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
ndata->node = node;
return ndata;
}
return ERR_PTR(-EPROBE_DEFER);
}
static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
unsigned long long rate = max(avg_bw, peak_bw);
const unsigned int dram_data_bus_width_bytes = 4;
const unsigned int ddr = 2;
int err;
/*
* Tegra30 EMC runs on a clock rate of SDRAM bus. This means that
* EMC clock rate is twice smaller than the peak data rate because
* data is sampled on both EMC clock edges.
*/
do_div(rate, ddr * dram_data_bus_width_bytes);
rate = min_t(u64, rate, U32_MAX);
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
if (err)
return err;
return 0;
}
static int tegra_emc_interconnect_init(struct tegra_emc *emc)
{
const struct tegra_mc_soc *soc = emc->mc->soc;
struct icc_node *node;
int err;
emc->provider.dev = emc->dev;
emc->provider.set = emc_icc_set;
emc->provider.data = &emc->provider;
emc->provider.aggregate = soc->icc_ops->aggregate;
emc->provider.xlate_extended = emc_of_icc_xlate_extended;
icc_provider_init(&emc->provider);
/* create External Memory Controller node */
node = icc_node_create(TEGRA_ICC_EMC);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto err_msg;
}
node->name = "External Memory Controller";
icc_node_add(node, &emc->provider);
/* link External Memory Controller to External Memory (DRAM) */
err = icc_link_create(node, TEGRA_ICC_EMEM);
if (err)
goto remove_nodes;
/* create External Memory node */
node = icc_node_create(TEGRA_ICC_EMEM);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = "External Memory (DRAM)";
icc_node_add(node, &emc->provider);
err = icc_provider_register(&emc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&emc->provider);
err_msg:
dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
return err;
}
static void devm_tegra_emc_unset_callback(void *data)
{
tegra20_clk_set_emc_round_callback(NULL, NULL);
}
static void devm_tegra_emc_unreg_clk_notifier(void *data)
{
struct tegra_emc *emc = data;
clk_notifier_unregister(emc->clk, &emc->clk_nb);
}
static int tegra_emc_init_clk(struct tegra_emc *emc)
{
int err;
tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
NULL);
if (err)
return err;
emc->clk = devm_clk_get(emc->dev, NULL);
if (IS_ERR(emc->clk)) {
dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
return PTR_ERR(emc->clk);
}
err = clk_notifier_register(emc->clk, &emc->clk_nb);
if (err) {
dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
return err;
}
err = devm_add_action_or_reset(emc->dev,
devm_tegra_emc_unreg_clk_notifier, emc);
if (err)
return err;
return 0;
}
static int tegra_emc_probe(struct platform_device *pdev)
{
struct tegra_core_opp_params opp_params = {};
struct device_node *np;
struct tegra_emc *emc;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
if (IS_ERR(emc->mc))
return PTR_ERR(emc->mc);
mutex_init(&emc->rate_lock);
emc->clk_nb.notifier_call = emc_clk_change_notify;
emc->dev = &pdev->dev;
emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
err = emc_setup_hw(emc);
if (err)
return err;
np = emc_find_node_by_ram_code(emc);
if (np) {
err = emc_load_timings_from_dt(emc, np);
of_node_put(np);
if (err)
return err;
}
err = platform_get_irq(pdev, 0);
if (err < 0)
return err;
emc->irq = err;
err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
dev_name(&pdev->dev), emc);
if (err) {
dev_err(&pdev->dev, "failed to request irq: %d\n", err);
return err;
}
err = tegra_emc_init_clk(emc);
if (err)
return err;
opp_params.init_state = true;
err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
if (err)
return err;
platform_set_drvdata(pdev, emc);
tegra_emc_rate_requests_init(emc);
tegra_emc_debugfs_init(emc);
tegra_emc_interconnect_init(emc);
/*
* Don't allow the kernel module to be unloaded. Unloading adds some
* extra complexity which doesn't really worth the effort in a case of
* this driver.
*/
try_module_get(THIS_MODULE);
return 0;
}
static int tegra_emc_suspend(struct device *dev)
{
struct tegra_emc *emc = dev_get_drvdata(dev);
int err;
/* take exclusive control over the clock's rate */
err = clk_rate_exclusive_get(emc->clk);
if (err) {
dev_err(emc->dev, "failed to acquire clk: %d\n", err);
return err;
}
/* suspending in a bad state will hang machine */
if (WARN(emc->bad_state, "hardware in a bad state\n"))
return -EINVAL;
emc->bad_state = true;
return 0;
}
static int tegra_emc_resume(struct device *dev)
{
struct tegra_emc *emc = dev_get_drvdata(dev);
emc_setup_hw(emc);
emc->bad_state = false;
clk_rate_exclusive_put(emc->clk);
return 0;
}
static const struct dev_pm_ops tegra_emc_pm_ops = {
.suspend = tegra_emc_suspend,
.resume = tegra_emc_resume,
};
static const struct of_device_id tegra_emc_of_match[] = {
{ .compatible = "nvidia,tegra30-emc", },
{},
};
MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
static struct platform_driver tegra_emc_driver = {
.probe = tegra_emc_probe,
.driver = {
.name = "tegra30-emc",
.of_match_table = tegra_emc_of_match,
.pm = &tegra_emc_pm_ops,
.suppress_bind_attrs = true,
.sync_state = icc_sync_state,
},
};
module_platform_driver(tegra_emc_driver);
MODULE_AUTHOR("Dmitry Osipenko <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/tegra/tegra30-emc.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/of.h>
#include <linux/mm.h>
#include <dt-bindings/memory/tegra114-mc.h>
#include "mc.h"
static const struct tegra_mc_client tegra114_mc_clients[] = {
{
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
.regs = {
.la = {
.reg = 0x34c,
.shift = 0,
.mask = 0xff,
.def = 0x0,
},
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 1,
},
.la = {
.reg = 0x2e8,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 2,
},
.la = {
.reg = 0x2f4,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 3,
},
.la = {
.reg = 0x2e8,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 4,
},
.la = {
.reg = 0x2f4,
.shift = 16,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 5,
},
.la = {
.reg = 0x2ec,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 6,
},
.la = {
.reg = 0x2f8,
.shift = 0,
.mask = 0xff,
.def = 0x4e,
},
},
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 9,
},
.la = {
.reg = 0x300,
.shift = 0,
.mask = 0xff,
.def = 0x33,
},
},
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 10,
},
.la = {
.reg = 0x308,
.shift = 0,
.mask = 0xff,
.def = 0x09,
},
},
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 11,
},
.la = {
.reg = 0x308,
.shift = 16,
.mask = 0xff,
.def = 0x09,
},
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 15,
},
.la = {
.reg = 0x2e4,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 16,
},
.la = {
.reg = 0x2f0,
.shift = 0,
.mask = 0xff,
.def = 0x68,
},
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 17,
},
.la = {
.reg = 0x2fc,
.shift = 0,
.mask = 0xff,
.def = 0x68,
},
},
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 18,
},
.la = {
.reg = 0x334,
.shift = 0,
.mask = 0xff,
.def = 0x0c,
},
},
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 19,
},
.la = {
.reg = 0x33c,
.shift = 0,
.mask = 0xff,
.def = 0x0c,
},
},
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 20,
},
.la = {
.reg = 0x30c,
.shift = 0,
.mask = 0xff,
.def = 0x0a,
},
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 22,
},
.la = {
.reg = 0x310,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 23,
},
.la = {
.reg = 0x310,
.shift = 16,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 24,
},
.la = {
.reg = 0x334,
.shift = 16,
.mask = 0xff,
.def = 0x0b,
},
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 28,
},
.la = {
.reg = 0x328,
.shift = 0,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 29,
},
.la = {
.reg = 0x344,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x228,
.bit = 30,
},
.la = {
.reg = 0x344,
.shift = 16,
.mask = 0xff,
.def = 0xe8,
},
},
}, {
.id = 0x20,
.name = "texl2srd",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 0,
},
.la = {
.reg = 0x338,
.shift = 0,
.mask = 0xff,
.def = 0x0c,
},
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 2,
},
.la = {
.reg = 0x354,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 3,
},
.la = {
.reg = 0x354,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 4,
},
.la = {
.reg = 0x358,
.shift = 0,
.mask = 0xff,
.def = 0xb8,
},
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 5,
},
.la = {
.reg = 0x358,
.shift = 16,
.mask = 0xff,
.def = 0xee,
},
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 8,
},
.la = {
.reg = 0x300,
.shift = 16,
.mask = 0xff,
.def = 0x33,
},
},
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 9,
},
.la = {
.reg = 0x304,
.shift = 0,
.mask = 0xff,
.def = 0x6c,
},
},
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 10,
},
.la = {
.reg = 0x304,
.shift = 16,
.mask = 0xff,
.def = 0x6c,
},
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 11,
},
.la = {
.reg = 0x328,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 12,
},
.la = {
.reg = 0x364,
.shift = 0,
.mask = 0xff,
.def = 0x47,
},
},
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 13,
},
.la = {
.reg = 0x368,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 14,
},
.la = {
.reg = 0x368,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 15,
},
.la = {
.reg = 0x36c,
.shift = 0,
.mask = 0xff,
.def = 0x47,
},
},
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 16,
},
.la = {
.reg = 0x30c,
.shift = 16,
.mask = 0xff,
.def = 0x9,
},
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 18,
},
.la = {
.reg = 0x2e4,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 19,
},
.la = {
.reg = 0x338,
.shift = 16,
.mask = 0xff,
.def = 0x10,
},
},
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 20,
},
.la = {
.reg = 0x340,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 21,
},
.la = {
.reg = 0x318,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 22,
},
.la = {
.reg = 0x314,
.shift = 0,
.mask = 0xff,
.def = 0x25,
},
},
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 23,
},
.la = {
.reg = 0x31c,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
.regs = {
.la = {
.reg = 0x324,
.shift = 16,
.mask = 0xff,
.def = 0x80,
},
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
.la = {
.reg = 0x320,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 27,
},
.la = {
.reg = 0x348,
.shift = 0,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 28,
},
.la = {
.reg = 0x348,
.shift = 16,
.mask = 0xff,
.def = 0xe8,
},
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 30,
},
.la = {
.reg = 0x35c,
.shift = 0,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x22c,
.bit = 31,
},
.la = {
.reg = 0x35c,
.shift = 16,
.mask = 0xff,
.def = 0xff,
},
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 0,
},
.la = {
.reg = 0x360,
.shift = 0,
.mask = 0xff,
.def = 0x89,
},
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 1,
},
.la = {
.reg = 0x360,
.shift = 16,
.mask = 0xff,
.def = 0x59,
},
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 10,
},
.la = {
.reg = 0x37c,
.shift = 0,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 11,
},
.la = {
.reg = 0x37c,
.shift = 16,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 12,
},
.la = {
.reg = 0x380,
.shift = 0,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 13,
},
.la = {
.reg = 0x380,
.shift = 16,
.mask = 0xff,
.def = 0xa5,
},
},
}, {
.id = 0x4e,
.name = "fdcdwr3",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 14,
},
.la = {
.reg = 0x388,
.shift = 0,
.mask = 0xff,
.def = 0x10,
},
},
}, {
.id = 0x4f,
.name = "fdcdrd3",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 15,
},
.la = {
.reg = 0x384,
.shift = 0,
.mask = 0xff,
.def = 0x0c,
},
},
}, {
.id = 0x50,
.name = "fdcwr4",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 16,
},
.la = {
.reg = 0x388,
.shift = 16,
.mask = 0xff,
.def = 0x10,
},
},
}, {
.id = 0x51,
.name = "fdcrd4",
.swgroup = TEGRA_SWGROUP_NV,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 17,
},
.la = {
.reg = 0x384,
.shift = 16,
.mask = 0xff,
.def = 0x0c,
},
},
}, {
.id = 0x52,
.name = "emucifr",
.swgroup = TEGRA_SWGROUP_EMUCIF,
.regs = {
.la = {
.reg = 0x38c,
.shift = 0,
.mask = 0xff,
.def = 0x04,
},
},
}, {
.id = 0x53,
.name = "emucifw",
.swgroup = TEGRA_SWGROUP_EMUCIF,
.regs = {
.la = {
.reg = 0x38c,
.shift = 16,
.mask = 0xff,
.def = 0x0e,
},
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 20,
},
.la = {
.reg = 0x390,
.shift = 0,
.mask = 0xff,
.def = 0x50,
},
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
.smmu = {
.reg = 0x230,
.bit = 21,
},
.la = {
.reg = 0x390,
.shift = 16,
.mask = 0xff,
.def = 0x50,
},
},
},
};
static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
};
static const unsigned int tegra114_group_drm[] = {
TEGRA_SWGROUP_DC,
TEGRA_SWGROUP_DCB,
TEGRA_SWGROUP_G2,
TEGRA_SWGROUP_NV,
};
static const struct tegra_smmu_group_soc tegra114_groups[] = {
{
.name = "drm",
.swgroups = tegra114_group_drm,
.num_swgroups = ARRAY_SIZE(tegra114_group_drm),
},
};
static const struct tegra_smmu_soc tegra114_smmu_soc = {
.clients = tegra114_mc_clients,
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
.swgroups = tegra114_swgroups,
.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
.groups = tegra114_groups,
.num_groups = ARRAY_SIZE(tegra114_groups),
.supports_round_robin_arbitration = false,
.supports_request_limit = false,
.num_tlb_lines = 32,
.num_asids = 4,
};
#define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
{ \
.name = #_name, \
.id = TEGRA114_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra114_mc_resets[] = {
TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
};
const struct tegra_mc_soc tegra114_mc_soc = {
.clients = tegra114_mc_clients,
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
.num_address_bits = 32,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra114_smmu_soc,
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM,
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra114_mc_resets,
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
.ops = &tegra30_mc_ops,
};
|
linux-master
|
drivers/memory/tegra/tegra114.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <dt-bindings/memory/tegra20-mc.h>
#include "mc.h"
#define MC_STAT_CONTROL 0x90
#define MC_STAT_EMC_CLOCK_LIMIT 0xa0
#define MC_STAT_EMC_CLOCKS 0xa4
#define MC_STAT_EMC_CONTROL_0 0xa8
#define MC_STAT_EMC_CONTROL_1 0xac
#define MC_STAT_EMC_COUNT_0 0xb8
#define MC_STAT_EMC_COUNT_1 0xbc
#define MC_STAT_CONTROL_CLIENT_ID GENMASK(13, 8)
#define MC_STAT_CONTROL_EVENT GENMASK(23, 16)
#define MC_STAT_CONTROL_PRI_EVENT GENMASK(25, 24)
#define MC_STAT_CONTROL_FILTER_CLIENT_ENABLE GENMASK(26, 26)
#define MC_STAT_CONTROL_FILTER_PRI GENMASK(29, 28)
#define MC_STAT_CONTROL_PRI_EVENT_HP 0
#define MC_STAT_CONTROL_PRI_EVENT_TM 1
#define MC_STAT_CONTROL_PRI_EVENT_BW 2
#define MC_STAT_CONTROL_FILTER_PRI_DISABLE 0
#define MC_STAT_CONTROL_FILTER_PRI_NO 1
#define MC_STAT_CONTROL_FILTER_PRI_YES 2
#define MC_STAT_CONTROL_EVENT_QUALIFIED 0
#define MC_STAT_CONTROL_EVENT_ANY_READ 1
#define MC_STAT_CONTROL_EVENT_ANY_WRITE 2
#define MC_STAT_CONTROL_EVENT_RD_WR_CHANGE 3
#define MC_STAT_CONTROL_EVENT_SUCCESSIVE 4
#define MC_STAT_CONTROL_EVENT_ARB_BANK_AA 5
#define MC_STAT_CONTROL_EVENT_ARB_BANK_BB 6
#define MC_STAT_CONTROL_EVENT_PAGE_MISS 7
#define MC_STAT_CONTROL_EVENT_AUTO_PRECHARGE 8
#define EMC_GATHER_RST (0 << 8)
#define EMC_GATHER_CLEAR (1 << 8)
#define EMC_GATHER_DISABLE (2 << 8)
#define EMC_GATHER_ENABLE (3 << 8)
#define MC_STAT_SAMPLE_TIME_USEC 16000
/* we store collected statistics as a fixed point values */
#define MC_FX_FRAC_SCALE 100
static DEFINE_MUTEX(tegra20_mc_stat_lock);
struct tegra20_mc_stat_gather {
unsigned int pri_filter;
unsigned int pri_event;
unsigned int result;
unsigned int client;
unsigned int event;
bool client_enb;
};
struct tegra20_mc_stat {
struct tegra20_mc_stat_gather gather0;
struct tegra20_mc_stat_gather gather1;
unsigned int sample_time_usec;
const struct tegra_mc *mc;
};
struct tegra20_mc_client_stat {
unsigned int events;
unsigned int arb_high_prio;
unsigned int arb_timeout;
unsigned int arb_bandwidth;
unsigned int rd_wr_change;
unsigned int successive;
unsigned int page_miss;
unsigned int auto_precharge;
unsigned int arb_bank_aa;
unsigned int arb_bank_bb;
};
static const struct tegra_mc_client tegra20_mc_clients[] = {
{
.id = 0x00,
.name = "display0a",
}, {
.id = 0x01,
.name = "display0ab",
}, {
.id = 0x02,
.name = "display0b",
}, {
.id = 0x03,
.name = "display0bb",
}, {
.id = 0x04,
.name = "display0c",
}, {
.id = 0x05,
.name = "display0cb",
}, {
.id = 0x06,
.name = "display1b",
}, {
.id = 0x07,
.name = "display1bb",
}, {
.id = 0x08,
.name = "eppup",
}, {
.id = 0x09,
.name = "g2pr",
}, {
.id = 0x0a,
.name = "g2sr",
}, {
.id = 0x0b,
.name = "mpeunifbr",
}, {
.id = 0x0c,
.name = "viruv",
}, {
.id = 0x0d,
.name = "avpcarm7r",
}, {
.id = 0x0e,
.name = "displayhc",
}, {
.id = 0x0f,
.name = "displayhcb",
}, {
.id = 0x10,
.name = "fdcdrd",
}, {
.id = 0x11,
.name = "g2dr",
}, {
.id = 0x12,
.name = "host1xdmar",
}, {
.id = 0x13,
.name = "host1xr",
}, {
.id = 0x14,
.name = "idxsrd",
}, {
.id = 0x15,
.name = "mpcorer",
}, {
.id = 0x16,
.name = "mpe_ipred",
}, {
.id = 0x17,
.name = "mpeamemrd",
}, {
.id = 0x18,
.name = "mpecsrd",
}, {
.id = 0x19,
.name = "ppcsahbdmar",
}, {
.id = 0x1a,
.name = "ppcsahbslvr",
}, {
.id = 0x1b,
.name = "texsrd",
}, {
.id = 0x1c,
.name = "vdebsevr",
}, {
.id = 0x1d,
.name = "vdember",
}, {
.id = 0x1e,
.name = "vdemcer",
}, {
.id = 0x1f,
.name = "vdetper",
}, {
.id = 0x20,
.name = "eppu",
}, {
.id = 0x21,
.name = "eppv",
}, {
.id = 0x22,
.name = "eppy",
}, {
.id = 0x23,
.name = "mpeunifbw",
}, {
.id = 0x24,
.name = "viwsb",
}, {
.id = 0x25,
.name = "viwu",
}, {
.id = 0x26,
.name = "viwv",
}, {
.id = 0x27,
.name = "viwy",
}, {
.id = 0x28,
.name = "g2dw",
}, {
.id = 0x29,
.name = "avpcarm7w",
}, {
.id = 0x2a,
.name = "fdcdwr",
}, {
.id = 0x2b,
.name = "host1xw",
}, {
.id = 0x2c,
.name = "ispw",
}, {
.id = 0x2d,
.name = "mpcorew",
}, {
.id = 0x2e,
.name = "mpecswr",
}, {
.id = 0x2f,
.name = "ppcsahbdmaw",
}, {
.id = 0x30,
.name = "ppcsahbslvw",
}, {
.id = 0x31,
.name = "vdebsevw",
}, {
.id = 0x32,
.name = "vdembew",
}, {
.id = 0x33,
.name = "vdetpmw",
},
};
#define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \
{ \
.name = #_name, \
.id = TEGRA20_MC_RESET_##_name, \
.control = _control, \
.status = _status, \
.reset = _reset, \
.bit = _bit, \
}
static const struct tegra_mc_reset tegra20_mc_resets[] = {
TEGRA20_MC_RESET(AVPC, 0x100, 0x140, 0x104, 0),
TEGRA20_MC_RESET(DC, 0x100, 0x144, 0x104, 1),
TEGRA20_MC_RESET(DCB, 0x100, 0x148, 0x104, 2),
TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
TEGRA20_MC_RESET(2D, 0x100, 0x150, 0x104, 4),
TEGRA20_MC_RESET(HC, 0x100, 0x154, 0x104, 5),
TEGRA20_MC_RESET(ISP, 0x100, 0x158, 0x104, 6),
TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104, 7),
TEGRA20_MC_RESET(MPEA, 0x100, 0x160, 0x104, 8),
TEGRA20_MC_RESET(MPEB, 0x100, 0x164, 0x104, 9),
TEGRA20_MC_RESET(MPEC, 0x100, 0x168, 0x104, 10),
TEGRA20_MC_RESET(3D, 0x100, 0x16c, 0x104, 11),
TEGRA20_MC_RESET(PPCS, 0x100, 0x170, 0x104, 12),
TEGRA20_MC_RESET(VDE, 0x100, 0x174, 0x104, 13),
TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
};
static int tegra20_mc_hotreset_assert(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->reset);
mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->reset);
mc_writel(mc, value | BIT(rst->bit), rst->reset);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static int tegra20_mc_block_dma(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
mc_writel(mc, value, rst->control);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static bool tegra20_mc_dma_idling(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
return mc_readl(mc, rst->status) == 0;
}
static int tegra20_mc_reset_status(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
}
static int tegra20_mc_unblock_dma(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->control) | BIT(rst->bit);
mc_writel(mc, value, rst->control);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = {
.hotreset_assert = tegra20_mc_hotreset_assert,
.hotreset_deassert = tegra20_mc_hotreset_deassert,
.block_dma = tegra20_mc_block_dma,
.dma_idling = tegra20_mc_dma_idling,
.unblock_dma = tegra20_mc_unblock_dma,
.reset_status = tegra20_mc_reset_status,
};
static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst)
{
/*
* It should be possible to tune arbitration knobs here, but the
* default values are known to work well on all devices. Hence
* nothing to do here so far.
*/
return 0;
}
static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{
/*
* ISO clients need to reserve extra bandwidth up-front because
* there could be high bandwidth pressure during initial filling
* of the client's FIFO buffers. Secondly, we need to take into
* account impurities of the memory subsystem.
*/
if (tag & TEGRA_MC_ICC_TAG_ISO)
peak_bw = tegra_mc_scale_percents(peak_bw, 300);
*agg_avg += avg_bw;
*agg_peak = max(*agg_peak, peak_bw);
return 0;
}
static struct icc_node_data *
tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
unsigned int i, idx = spec->args[0];
struct icc_node_data *ndata;
struct icc_node *node;
list_for_each_entry(node, &mc->provider.nodes, node_list) {
if (node->id != idx)
continue;
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
ndata->node = node;
/* these clients are isochronous by default */
if (strstarts(node->name, "display") ||
strstarts(node->name, "vi"))
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
else
ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
return ndata;
}
for (i = 0; i < mc->soc->num_clients; i++) {
if (mc->soc->clients[i].id == idx)
return ERR_PTR(-EPROBE_DEFER);
}
dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
return ERR_PTR(-EINVAL);
}
static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = {
.xlate_extended = tegra20_mc_of_icc_xlate_extended,
.aggregate = tegra20_mc_icc_aggreate,
.set = tegra20_mc_icc_set,
};
static u32 tegra20_mc_stat_gather_control(const struct tegra20_mc_stat_gather *g)
{
u32 control;
control = FIELD_PREP(MC_STAT_CONTROL_EVENT, g->event);
control |= FIELD_PREP(MC_STAT_CONTROL_CLIENT_ID, g->client);
control |= FIELD_PREP(MC_STAT_CONTROL_PRI_EVENT, g->pri_event);
control |= FIELD_PREP(MC_STAT_CONTROL_FILTER_PRI, g->pri_filter);
control |= FIELD_PREP(MC_STAT_CONTROL_FILTER_CLIENT_ENABLE, g->client_enb);
return control;
}
static void tegra20_mc_stat_gather(struct tegra20_mc_stat *stat)
{
u32 clocks, count0, count1, control_0, control_1;
const struct tegra_mc *mc = stat->mc;
control_0 = tegra20_mc_stat_gather_control(&stat->gather0);
control_1 = tegra20_mc_stat_gather_control(&stat->gather1);
/*
* Reset statistic gathers state, select statistics collection mode
* and set clocks counter saturation limit to maximum.
*/
mc_writel(mc, 0x00000000, MC_STAT_CONTROL);
mc_writel(mc, control_0, MC_STAT_EMC_CONTROL_0);
mc_writel(mc, control_1, MC_STAT_EMC_CONTROL_1);
mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT);
mc_writel(mc, EMC_GATHER_ENABLE, MC_STAT_CONTROL);
fsleep(stat->sample_time_usec);
mc_writel(mc, EMC_GATHER_DISABLE, MC_STAT_CONTROL);
count0 = mc_readl(mc, MC_STAT_EMC_COUNT_0);
count1 = mc_readl(mc, MC_STAT_EMC_COUNT_1);
clocks = mc_readl(mc, MC_STAT_EMC_CLOCKS);
clocks = max(clocks / 100 / MC_FX_FRAC_SCALE, 1u);
stat->gather0.result = DIV_ROUND_UP(count0, clocks);
stat->gather1.result = DIV_ROUND_UP(count1, clocks);
}
static void tegra20_mc_stat_events(const struct tegra_mc *mc,
const struct tegra_mc_client *client0,
const struct tegra_mc_client *client1,
unsigned int pri_filter,
unsigned int pri_event,
unsigned int event,
unsigned int *result0,
unsigned int *result1)
{
struct tegra20_mc_stat stat = {};
stat.gather0.client = client0 ? client0->id : 0;
stat.gather0.pri_filter = pri_filter;
stat.gather0.client_enb = !!client0;
stat.gather0.pri_event = pri_event;
stat.gather0.event = event;
stat.gather1.client = client1 ? client1->id : 0;
stat.gather1.pri_filter = pri_filter;
stat.gather1.client_enb = !!client1;
stat.gather1.pri_event = pri_event;
stat.gather1.event = event;
stat.sample_time_usec = MC_STAT_SAMPLE_TIME_USEC;
stat.mc = mc;
tegra20_mc_stat_gather(&stat);
*result0 = stat.gather0.result;
*result1 = stat.gather1.result;
}
static void tegra20_mc_collect_stats(const struct tegra_mc *mc,
struct tegra20_mc_client_stat *stats)
{
const struct tegra_mc_client *client0, *client1;
unsigned int i;
/* collect memory controller utilization percent for each client */
for (i = 0; i < mc->soc->num_clients; i += 2) {
client0 = &mc->soc->clients[i];
client1 = &mc->soc->clients[i + 1];
if (i + 1 == mc->soc->num_clients)
client1 = NULL;
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_DISABLE,
MC_STAT_CONTROL_PRI_EVENT_HP,
MC_STAT_CONTROL_EVENT_QUALIFIED,
&stats[i + 0].events,
&stats[i + 1].events);
}
/* collect more info from active clients */
for (i = 0; i < mc->soc->num_clients; i++) {
unsigned int clienta, clientb = mc->soc->num_clients;
for (client0 = NULL; i < mc->soc->num_clients; i++) {
if (stats[i].events) {
client0 = &mc->soc->clients[i];
clienta = i++;
break;
}
}
for (client1 = NULL; i < mc->soc->num_clients; i++) {
if (stats[i].events) {
client1 = &mc->soc->clients[i];
clientb = i;
break;
}
}
if (!client0 && !client1)
break;
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_YES,
MC_STAT_CONTROL_PRI_EVENT_HP,
MC_STAT_CONTROL_EVENT_QUALIFIED,
&stats[clienta].arb_high_prio,
&stats[clientb].arb_high_prio);
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_YES,
MC_STAT_CONTROL_PRI_EVENT_TM,
MC_STAT_CONTROL_EVENT_QUALIFIED,
&stats[clienta].arb_timeout,
&stats[clientb].arb_timeout);
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_YES,
MC_STAT_CONTROL_PRI_EVENT_BW,
MC_STAT_CONTROL_EVENT_QUALIFIED,
&stats[clienta].arb_bandwidth,
&stats[clientb].arb_bandwidth);
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_DISABLE,
MC_STAT_CONTROL_PRI_EVENT_HP,
MC_STAT_CONTROL_EVENT_RD_WR_CHANGE,
&stats[clienta].rd_wr_change,
&stats[clientb].rd_wr_change);
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_DISABLE,
MC_STAT_CONTROL_PRI_EVENT_HP,
MC_STAT_CONTROL_EVENT_SUCCESSIVE,
&stats[clienta].successive,
&stats[clientb].successive);
tegra20_mc_stat_events(mc, client0, client1,
MC_STAT_CONTROL_FILTER_PRI_DISABLE,
MC_STAT_CONTROL_PRI_EVENT_HP,
MC_STAT_CONTROL_EVENT_PAGE_MISS,
&stats[clienta].page_miss,
&stats[clientb].page_miss);
}
}
static void tegra20_mc_printf_percents(struct seq_file *s,
const char *fmt,
unsigned int percents_fx)
{
char percents_str[8];
snprintf(percents_str, ARRAY_SIZE(percents_str), "%3u.%02u%%",
percents_fx / MC_FX_FRAC_SCALE, percents_fx % MC_FX_FRAC_SCALE);
seq_printf(s, fmt, percents_str);
}
static int tegra20_mc_stats_show(struct seq_file *s, void *unused)
{
const struct tegra_mc *mc = dev_get_drvdata(s->private);
struct tegra20_mc_client_stat *stats;
unsigned int i;
stats = kcalloc(mc->soc->num_clients + 1, sizeof(*stats), GFP_KERNEL);
if (!stats)
return -ENOMEM;
mutex_lock(&tegra20_mc_stat_lock);
tegra20_mc_collect_stats(mc, stats);
mutex_unlock(&tegra20_mc_stat_lock);
seq_puts(s, "Memory client Events Timeout High priority Bandwidth ARB RW change Successive Page miss\n");
seq_puts(s, "-----------------------------------------------------------------------------------------------------\n");
for (i = 0; i < mc->soc->num_clients; i++) {
seq_printf(s, "%-14s ", mc->soc->clients[i].name);
/* An event is generated when client performs R/W request. */
tegra20_mc_printf_percents(s, "%-9s", stats[i].events);
/*
* An event is generated based on the timeout (TM) signal
* accompanying a request for arbitration.
*/
tegra20_mc_printf_percents(s, "%-10s", stats[i].arb_timeout);
/*
* An event is generated based on the high-priority (HP) signal
* accompanying a request for arbitration.
*/
tegra20_mc_printf_percents(s, "%-16s", stats[i].arb_high_prio);
/*
* An event is generated based on the bandwidth (BW) signal
* accompanying a request for arbitration.
*/
tegra20_mc_printf_percents(s, "%-16s", stats[i].arb_bandwidth);
/*
* An event is generated when the memory controller switches
* between making a read request to making a write request.
*/
tegra20_mc_printf_percents(s, "%-12s", stats[i].rd_wr_change);
/*
* An even generated when the chosen client has wins arbitration
* when it was also the winner at the previous request. If a
* client makes N requests in a row that are honored, SUCCESSIVE
* will be counted (N-1) times. Large values for this event
* imply that if we were patient enough, all of those requests
* could have been coalesced.
*/
tegra20_mc_printf_percents(s, "%-13s", stats[i].successive);
/*
* An event is generated when the memory controller detects a
* page miss for the current request.
*/
tegra20_mc_printf_percents(s, "%-12s\n", stats[i].page_miss);
}
kfree(stats);
return 0;
}
static int tegra20_mc_probe(struct tegra_mc *mc)
{
debugfs_create_devm_seqfile(mc->dev, "stats", mc->debugfs.root,
tegra20_mc_stats_show);
return 0;
}
static int tegra20_mc_suspend(struct tegra_mc *mc)
{
int err;
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
err = tegra_gart_suspend(mc->gart);
if (err < 0)
return err;
}
return 0;
}
static int tegra20_mc_resume(struct tegra_mc *mc)
{
int err;
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
err = tegra_gart_resume(mc->gart);
if (err < 0)
return err;
}
return 0;
}
static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
{
struct tegra_mc *mc = data;
unsigned long status;
unsigned int bit;
/* mask all interrupts to avoid flooding */
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
if (!status)
return IRQ_NONE;
for_each_set_bit(bit, &status, 32) {
const char *error = tegra_mc_status_names[bit];
const char *direction = "read", *secure = "";
const char *client, *desc;
phys_addr_t addr;
u32 value, reg;
u8 id, type;
switch (BIT(bit)) {
case MC_INT_DECERR_EMEM:
reg = MC_DECERR_EMEM_OTHERS_STATUS;
value = mc_readl(mc, reg);
id = value & mc->soc->client_id_mask;
desc = tegra_mc_error_names[2];
if (value & BIT(31))
direction = "write";
break;
case MC_INT_INVALID_GART_PAGE:
reg = MC_GART_ERROR_REQ;
value = mc_readl(mc, reg);
id = (value >> 1) & mc->soc->client_id_mask;
desc = tegra_mc_error_names[2];
if (value & BIT(0))
direction = "write";
break;
case MC_INT_SECURITY_VIOLATION:
reg = MC_SECURITY_VIOLATION_STATUS;
value = mc_readl(mc, reg);
id = value & mc->soc->client_id_mask;
type = (value & BIT(30)) ? 4 : 3;
desc = tegra_mc_error_names[type];
secure = "secure ";
if (value & BIT(31))
direction = "write";
break;
default:
continue;
}
client = mc->soc->clients[id].name;
addr = mc_readl(mc, reg + sizeof(u32));
dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
client, secure, direction, &addr, error,
desc);
}
/* clear interrupts */
mc_writel(mc, status, MC_INTSTATUS);
return IRQ_HANDLED;
}
static const struct tegra_mc_ops tegra20_mc_ops = {
.probe = tegra20_mc_probe,
.suspend = tegra20_mc_suspend,
.resume = tegra20_mc_resume,
.handle_irq = tegra20_mc_handle_irq,
};
const struct tegra_mc_soc tegra20_mc_soc = {
.clients = tegra20_mc_clients,
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
.num_address_bits = 32,
.client_id_mask = 0x3f,
.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
MC_INT_DECERR_EMEM,
.reset_ops = &tegra20_mc_reset_ops,
.resets = tegra20_mc_resets,
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
.icc_ops = &tegra20_mc_icc_ops,
.ops = &tegra20_mc_ops,
};
|
linux-master
|
drivers/memory/tegra/tegra20.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
#include "tegra210-emc.h"
#include "tegra210-mc.h"
/* CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT 29
#define EMC_CLK_EMC_2X_CLK_SRC_MASK \
(0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
#define EMC_CLK_SOURCE_PLLM_LJ 0x4
#define EMC_CLK_SOURCE_PLLMB_LJ 0x5
#define EMC_CLK_FORCE_CC_TRIGGER BIT(27)
#define EMC_CLK_MC_EMC_SAME_FREQ BIT(16)
#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0
#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK \
(0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL */
#define DLL_CLK_EMC_DLL_CLK_SRC_SHIFT 29
#define DLL_CLK_EMC_DLL_CLK_SRC_MASK \
(0x7 << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT)
#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT 10
#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_MASK \
(0x3 << DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT)
#define PLLM_VCOA 0
#define PLLM_VCOB 1
#define EMC_DLL_SWITCH_OUT 2
#define DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT 0
#define DLL_CLK_EMC_DLL_CLK_DIVISOR_MASK \
(0xff << DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT)
/* MC_EMEM_ARB_MISC0 */
#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ BIT(27)
/* EMC_DATA_BRLSHFT_X */
#define EMC0_EMC_DATA_BRLSHFT_0_INDEX 2
#define EMC1_EMC_DATA_BRLSHFT_0_INDEX 3
#define EMC0_EMC_DATA_BRLSHFT_1_INDEX 4
#define EMC1_EMC_DATA_BRLSHFT_1_INDEX 5
#define TRIM_REG(chan, rank, reg, byte) \
(((EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte ## _MASK & \
next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
rank ## _ ## reg ## _INDEX]) >> \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte ## _SHIFT) \
+ \
(((EMC_DATA_BRLSHFT_ ## rank ## _RANK ## rank ## _BYTE ## \
byte ## _DATA_BRLSHFT_MASK & \
next->trim_perch_regs[EMC ## chan ## \
_EMC_DATA_BRLSHFT_ ## rank ## _INDEX]) >> \
EMC_DATA_BRLSHFT_ ## rank ## _RANK ## rank ## _BYTE ## \
byte ## _DATA_BRLSHFT_SHIFT) * 64))
#define CALC_TEMP(rank, reg, byte1, byte2, n) \
(((new[n] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## \
reg ## _OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte1 ## _SHIFT) & \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte1 ## _MASK) \
| \
((new[n + 1] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ##\
reg ## _OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte2 ## _SHIFT) & \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte2 ## _MASK))
#define REFRESH_SPEEDUP(value, speedup) \
(((value) & 0xffff0000) | ((value) & 0xffff) * (speedup))
#define LPDDR2_MR4_SRR GENMASK(2, 0)
static const struct tegra210_emc_sequence *tegra210_emc_sequences[] = {
&tegra210_emc_r21021,
};
static const struct tegra210_emc_table_register_offsets
tegra210_emc_table_register_offsets = {
.burst = {
EMC_RC,
EMC_RFC,
EMC_RFCPB,
EMC_REFCTRL2,
EMC_RFC_SLR,
EMC_RAS,
EMC_RP,
EMC_R2W,
EMC_W2R,
EMC_R2P,
EMC_W2P,
EMC_R2R,
EMC_TPPD,
EMC_CCDMW,
EMC_RD_RCD,
EMC_WR_RCD,
EMC_RRD,
EMC_REXT,
EMC_WEXT,
EMC_WDV_CHK,
EMC_WDV,
EMC_WSV,
EMC_WEV,
EMC_WDV_MASK,
EMC_WS_DURATION,
EMC_WE_DURATION,
EMC_QUSE,
EMC_QUSE_WIDTH,
EMC_IBDLY,
EMC_OBDLY,
EMC_EINPUT,
EMC_MRW6,
EMC_EINPUT_DURATION,
EMC_PUTERM_EXTRA,
EMC_PUTERM_WIDTH,
EMC_QRST,
EMC_QSAFE,
EMC_RDV,
EMC_RDV_MASK,
EMC_RDV_EARLY,
EMC_RDV_EARLY_MASK,
EMC_REFRESH,
EMC_BURST_REFRESH_NUM,
EMC_PRE_REFRESH_REQ_CNT,
EMC_PDEX2WR,
EMC_PDEX2RD,
EMC_PCHG2PDEN,
EMC_ACT2PDEN,
EMC_AR2PDEN,
EMC_RW2PDEN,
EMC_CKE2PDEN,
EMC_PDEX2CKE,
EMC_PDEX2MRR,
EMC_TXSR,
EMC_TXSRDLL,
EMC_TCKE,
EMC_TCKESR,
EMC_TPD,
EMC_TFAW,
EMC_TRPAB,
EMC_TCLKSTABLE,
EMC_TCLKSTOP,
EMC_MRW7,
EMC_TREFBW,
EMC_ODT_WRITE,
EMC_FBIO_CFG5,
EMC_FBIO_CFG7,
EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_PERIOD,
EMC_PMACRO_IB_RXRT,
EMC_CFG_PIPE_1,
EMC_CFG_PIPE_2,
EMC_PMACRO_QUSE_DDLL_RANK0_4,
EMC_PMACRO_QUSE_DDLL_RANK0_5,
EMC_PMACRO_QUSE_DDLL_RANK1_4,
EMC_PMACRO_QUSE_DDLL_RANK1_5,
EMC_MRW8,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5,
EMC_PMACRO_DDLL_LONG_CMD_0,
EMC_PMACRO_DDLL_LONG_CMD_1,
EMC_PMACRO_DDLL_LONG_CMD_2,
EMC_PMACRO_DDLL_LONG_CMD_3,
EMC_PMACRO_DDLL_LONG_CMD_4,
EMC_PMACRO_DDLL_SHORT_CMD_0,
EMC_PMACRO_DDLL_SHORT_CMD_1,
EMC_PMACRO_DDLL_SHORT_CMD_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3,
EMC_TXDSRVTTGEN,
EMC_FDPD_CTRL_DQ,
EMC_FDPD_CTRL_CMD,
EMC_FBIO_SPARE,
EMC_ZCAL_INTERVAL,
EMC_ZCAL_WAIT_CNT,
EMC_MRS_WAIT_CNT,
EMC_MRS_WAIT_CNT2,
EMC_AUTO_CAL_CHANNEL,
EMC_DLL_CFG_0,
EMC_DLL_CFG_1,
EMC_PMACRO_AUTOCAL_CFG_COMMON,
EMC_PMACRO_ZCTRL,
EMC_CFG,
EMC_CFG_PIPE,
EMC_DYN_SELF_REF_CONTROL,
EMC_QPOP,
EMC_DQS_BRLSHFT_0,
EMC_DQS_BRLSHFT_1,
EMC_CMD_BRLSHFT_2,
EMC_CMD_BRLSHFT_3,
EMC_PMACRO_PAD_CFG_CTRL,
EMC_PMACRO_DATA_PAD_RX_CTRL,
EMC_PMACRO_CMD_PAD_RX_CTRL,
EMC_PMACRO_DATA_RX_TERM_MODE,
EMC_PMACRO_CMD_RX_TERM_MODE,
EMC_PMACRO_CMD_PAD_TX_CTRL,
EMC_PMACRO_DATA_PAD_TX_CTRL,
EMC_PMACRO_COMMON_PAD_TX_CTRL,
EMC_PMACRO_VTTGEN_CTRL_0,
EMC_PMACRO_VTTGEN_CTRL_1,
EMC_PMACRO_VTTGEN_CTRL_2,
EMC_PMACRO_BRICK_CTRL_RFU1,
EMC_PMACRO_CMD_BRICK_CTRL_FDPD,
EMC_PMACRO_BRICK_CTRL_RFU2,
EMC_PMACRO_DATA_BRICK_CTRL_FDPD,
EMC_PMACRO_BG_BIAS_CTRL_0,
EMC_CFG_3,
EMC_PMACRO_TX_PWRD_0,
EMC_PMACRO_TX_PWRD_1,
EMC_PMACRO_TX_PWRD_2,
EMC_PMACRO_TX_PWRD_3,
EMC_PMACRO_TX_PWRD_4,
EMC_PMACRO_TX_PWRD_5,
EMC_CONFIG_SAMPLE_DELAY,
EMC_PMACRO_TX_SEL_CLK_SRC_0,
EMC_PMACRO_TX_SEL_CLK_SRC_1,
EMC_PMACRO_TX_SEL_CLK_SRC_2,
EMC_PMACRO_TX_SEL_CLK_SRC_3,
EMC_PMACRO_TX_SEL_CLK_SRC_4,
EMC_PMACRO_TX_SEL_CLK_SRC_5,
EMC_PMACRO_DDLL_BYPASS,
EMC_PMACRO_DDLL_PWRD_0,
EMC_PMACRO_DDLL_PWRD_1,
EMC_PMACRO_DDLL_PWRD_2,
EMC_PMACRO_CMD_CTRL_0,
EMC_PMACRO_CMD_CTRL_1,
EMC_PMACRO_CMD_CTRL_2,
EMC_TR_TIMING_0,
EMC_TR_DVFS,
EMC_TR_CTRL_1,
EMC_TR_RDV,
EMC_TR_QPOP,
EMC_TR_RDV_MASK,
EMC_MRW14,
EMC_TR_QSAFE,
EMC_TR_QRST,
EMC_TRAINING_CTRL,
EMC_TRAINING_SETTLE,
EMC_TRAINING_VREF_SETTLE,
EMC_TRAINING_CA_FINE_CTRL,
EMC_TRAINING_CA_CTRL_MISC,
EMC_TRAINING_CA_CTRL_MISC1,
EMC_TRAINING_CA_VREF_CTRL,
EMC_TRAINING_QUSE_CORS_CTRL,
EMC_TRAINING_QUSE_FINE_CTRL,
EMC_TRAINING_QUSE_CTRL_MISC,
EMC_TRAINING_QUSE_VREF_CTRL,
EMC_TRAINING_READ_FINE_CTRL,
EMC_TRAINING_READ_CTRL_MISC,
EMC_TRAINING_READ_VREF_CTRL,
EMC_TRAINING_WRITE_FINE_CTRL,
EMC_TRAINING_WRITE_CTRL_MISC,
EMC_TRAINING_WRITE_VREF_CTRL,
EMC_TRAINING_MPC,
EMC_MRW15,
},
.trim = {
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2,
EMC_PMACRO_IB_VREF_DQS_0,
EMC_PMACRO_IB_VREF_DQS_1,
EMC_PMACRO_IB_VREF_DQ_0,
EMC_PMACRO_IB_VREF_DQ_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2,
EMC_PMACRO_QUSE_DDLL_RANK0_0,
EMC_PMACRO_QUSE_DDLL_RANK0_1,
EMC_PMACRO_QUSE_DDLL_RANK0_2,
EMC_PMACRO_QUSE_DDLL_RANK0_3,
EMC_PMACRO_QUSE_DDLL_RANK1_0,
EMC_PMACRO_QUSE_DDLL_RANK1_1,
EMC_PMACRO_QUSE_DDLL_RANK1_2,
EMC_PMACRO_QUSE_DDLL_RANK1_3
},
.burst_mc = {
MC_EMEM_ARB_CFG,
MC_EMEM_ARB_OUTSTANDING_REQ,
MC_EMEM_ARB_REFPB_HP_CTRL,
MC_EMEM_ARB_REFPB_BANK_CTRL,
MC_EMEM_ARB_TIMING_RCD,
MC_EMEM_ARB_TIMING_RP,
MC_EMEM_ARB_TIMING_RC,
MC_EMEM_ARB_TIMING_RAS,
MC_EMEM_ARB_TIMING_FAW,
MC_EMEM_ARB_TIMING_RRD,
MC_EMEM_ARB_TIMING_RAP2PRE,
MC_EMEM_ARB_TIMING_WAP2PRE,
MC_EMEM_ARB_TIMING_R2R,
MC_EMEM_ARB_TIMING_W2W,
MC_EMEM_ARB_TIMING_R2W,
MC_EMEM_ARB_TIMING_CCDMW,
MC_EMEM_ARB_TIMING_W2R,
MC_EMEM_ARB_TIMING_RFCPB,
MC_EMEM_ARB_DA_TURNS,
MC_EMEM_ARB_DA_COVERS,
MC_EMEM_ARB_MISC0,
MC_EMEM_ARB_MISC1,
MC_EMEM_ARB_MISC2,
MC_EMEM_ARB_RING1_THROTTLE,
MC_EMEM_ARB_DHYST_CTRL,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7,
},
.la_scale = {
MC_MLL_MPCORER_PTSA_RATE,
MC_FTOP_PTSA_RATE,
MC_PTSA_GRANT_DECREMENT,
MC_LATENCY_ALLOWANCE_XUSB_0,
MC_LATENCY_ALLOWANCE_XUSB_1,
MC_LATENCY_ALLOWANCE_TSEC_0,
MC_LATENCY_ALLOWANCE_SDMMCA_0,
MC_LATENCY_ALLOWANCE_SDMMCAA_0,
MC_LATENCY_ALLOWANCE_SDMMC_0,
MC_LATENCY_ALLOWANCE_SDMMCAB_0,
MC_LATENCY_ALLOWANCE_PPCS_0,
MC_LATENCY_ALLOWANCE_PPCS_1,
MC_LATENCY_ALLOWANCE_MPCORE_0,
MC_LATENCY_ALLOWANCE_HC_0,
MC_LATENCY_ALLOWANCE_HC_1,
MC_LATENCY_ALLOWANCE_AVPC_0,
MC_LATENCY_ALLOWANCE_GPU_0,
MC_LATENCY_ALLOWANCE_GPU2_0,
MC_LATENCY_ALLOWANCE_NVENC_0,
MC_LATENCY_ALLOWANCE_NVDEC_0,
MC_LATENCY_ALLOWANCE_VIC_0,
MC_LATENCY_ALLOWANCE_VI2_0,
MC_LATENCY_ALLOWANCE_ISP2_0,
MC_LATENCY_ALLOWANCE_ISP2_1,
},
.burst_per_channel = {
{ .bank = 0, .offset = EMC_MRW10, },
{ .bank = 1, .offset = EMC_MRW10, },
{ .bank = 0, .offset = EMC_MRW11, },
{ .bank = 1, .offset = EMC_MRW11, },
{ .bank = 0, .offset = EMC_MRW12, },
{ .bank = 1, .offset = EMC_MRW12, },
{ .bank = 0, .offset = EMC_MRW13, },
{ .bank = 1, .offset = EMC_MRW13, },
},
.trim_per_channel = {
{ .bank = 0, .offset = EMC_CMD_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_CMD_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_DATA_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_DATA_BRLSHFT_0, },
{ .bank = 0, .offset = EMC_DATA_BRLSHFT_1, },
{ .bank = 1, .offset = EMC_DATA_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_2, },
{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_3, },
},
.vref_per_channel = {
{
.bank = 0,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK0,
}, {
.bank = 1,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK0,
}, {
.bank = 0,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK1,
}, {
.bank = 1,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK1,
},
},
};
static void tegra210_emc_train(struct timer_list *timer)
{
struct tegra210_emc *emc = from_timer(emc, timer, training);
unsigned long flags;
if (!emc->last)
return;
spin_lock_irqsave(&emc->lock, flags);
if (emc->sequence->periodic_compensation)
emc->sequence->periodic_compensation(emc);
spin_unlock_irqrestore(&emc->lock, flags);
mod_timer(&emc->training,
jiffies + msecs_to_jiffies(emc->training_interval));
}
static void tegra210_emc_training_start(struct tegra210_emc *emc)
{
mod_timer(&emc->training,
jiffies + msecs_to_jiffies(emc->training_interval));
}
static void tegra210_emc_training_stop(struct tegra210_emc *emc)
{
del_timer(&emc->training);
}
static unsigned int tegra210_emc_get_temperature(struct tegra210_emc *emc)
{
unsigned long flags;
u32 value, max = 0;
unsigned int i;
spin_lock_irqsave(&emc->lock, flags);
for (i = 0; i < emc->num_devices; i++) {
value = tegra210_emc_mrr_read(emc, i, 4);
if (value & BIT(7))
dev_dbg(emc->dev,
"sensor reading changed for device %u: %08x\n",
i, value);
value = FIELD_GET(LPDDR2_MR4_SRR, value);
if (value > max)
max = value;
}
spin_unlock_irqrestore(&emc->lock, flags);
return max;
}
static void tegra210_emc_poll_refresh(struct timer_list *timer)
{
struct tegra210_emc *emc = from_timer(emc, timer, refresh_timer);
unsigned int temperature;
if (!emc->debugfs.temperature)
temperature = tegra210_emc_get_temperature(emc);
else
temperature = emc->debugfs.temperature;
if (temperature == emc->temperature)
goto reset;
switch (temperature) {
case 0 ... 3:
/* temperature is fine, using regular refresh */
dev_dbg(emc->dev, "switching to nominal refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_NOMINAL);
break;
case 4:
dev_dbg(emc->dev, "switching to 2x refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_2X);
break;
case 5:
dev_dbg(emc->dev, "switching to 4x refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_4X);
break;
case 6 ... 7:
dev_dbg(emc->dev, "switching to throttle refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_THROTTLE);
break;
default:
WARN(1, "invalid DRAM temperature state %u\n", temperature);
return;
}
emc->temperature = temperature;
reset:
if (atomic_read(&emc->refresh_poll) > 0) {
unsigned int interval = emc->refresh_poll_interval;
unsigned int timeout = msecs_to_jiffies(interval);
mod_timer(&emc->refresh_timer, jiffies + timeout);
}
}
static void tegra210_emc_poll_refresh_stop(struct tegra210_emc *emc)
{
atomic_set(&emc->refresh_poll, 0);
del_timer_sync(&emc->refresh_timer);
}
static void tegra210_emc_poll_refresh_start(struct tegra210_emc *emc)
{
atomic_set(&emc->refresh_poll, 1);
mod_timer(&emc->refresh_timer,
jiffies + msecs_to_jiffies(emc->refresh_poll_interval));
}
static int tegra210_emc_cd_max_state(struct thermal_cooling_device *cd,
unsigned long *state)
{
*state = 1;
return 0;
}
static int tegra210_emc_cd_get_state(struct thermal_cooling_device *cd,
unsigned long *state)
{
struct tegra210_emc *emc = cd->devdata;
*state = atomic_read(&emc->refresh_poll);
return 0;
}
static int tegra210_emc_cd_set_state(struct thermal_cooling_device *cd,
unsigned long state)
{
struct tegra210_emc *emc = cd->devdata;
if (state == atomic_read(&emc->refresh_poll))
return 0;
if (state)
tegra210_emc_poll_refresh_start(emc);
else
tegra210_emc_poll_refresh_stop(emc);
return 0;
}
static const struct thermal_cooling_device_ops tegra210_emc_cd_ops = {
.get_max_state = tegra210_emc_cd_max_state,
.get_cur_state = tegra210_emc_cd_get_state,
.set_cur_state = tegra210_emc_cd_set_state,
};
static void tegra210_emc_set_clock(struct tegra210_emc *emc, u32 clksrc)
{
emc->sequence->set_clock(emc, clksrc);
if (emc->next->periodic_training)
tegra210_emc_training_start(emc);
else
tegra210_emc_training_stop(emc);
}
static void tegra210_change_dll_src(struct tegra210_emc *emc,
u32 clksrc)
{
u32 dll_setting = emc->next->dll_clk_src;
u32 emc_clk_src;
u32 emc_clk_div;
emc_clk_src = (clksrc & EMC_CLK_EMC_2X_CLK_SRC_MASK) >>
EMC_CLK_EMC_2X_CLK_SRC_SHIFT;
emc_clk_div = (clksrc & EMC_CLK_EMC_2X_CLK_DIVISOR_MASK) >>
EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT;
dll_setting &= ~(DLL_CLK_EMC_DLL_CLK_SRC_MASK |
DLL_CLK_EMC_DLL_CLK_DIVISOR_MASK);
dll_setting |= emc_clk_src << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT;
dll_setting |= emc_clk_div << DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT;
dll_setting &= ~DLL_CLK_EMC_DLL_DDLL_CLK_SEL_MASK;
if (emc_clk_src == EMC_CLK_SOURCE_PLLMB_LJ)
dll_setting |= (PLLM_VCOB <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
else if (emc_clk_src == EMC_CLK_SOURCE_PLLM_LJ)
dll_setting |= (PLLM_VCOA <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
else
dll_setting |= (EMC_DLL_SWITCH_OUT <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
tegra210_clk_emc_dll_update_setting(dll_setting);
if (emc->next->clk_out_enb_x_0_clk_enb_emc_dll)
tegra210_clk_emc_dll_enable(true);
else
tegra210_clk_emc_dll_enable(false);
}
int tegra210_emc_set_refresh(struct tegra210_emc *emc,
enum tegra210_emc_refresh refresh)
{
struct tegra210_emc_timing *timings;
unsigned long flags;
if ((emc->dram_type != DRAM_TYPE_LPDDR2 &&
emc->dram_type != DRAM_TYPE_LPDDR4) ||
!emc->last)
return -ENODEV;
if (refresh > TEGRA210_EMC_REFRESH_THROTTLE)
return -EINVAL;
if (refresh == emc->refresh)
return 0;
spin_lock_irqsave(&emc->lock, flags);
if (refresh == TEGRA210_EMC_REFRESH_THROTTLE && emc->derated)
timings = emc->derated;
else
timings = emc->nominal;
if (timings != emc->timings) {
unsigned int index = emc->last - emc->timings;
u32 clksrc;
clksrc = emc->provider.configs[index].value |
EMC_CLK_FORCE_CC_TRIGGER;
emc->next = &timings[index];
emc->timings = timings;
tegra210_emc_set_clock(emc, clksrc);
} else {
tegra210_emc_adjust_timing(emc, emc->last);
tegra210_emc_timing_update(emc);
if (refresh != TEGRA210_EMC_REFRESH_NOMINAL)
emc_writel(emc, EMC_REF_REF_CMD, EMC_REF);
}
spin_unlock_irqrestore(&emc->lock, flags);
return 0;
}
u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip,
unsigned int address)
{
u32 value, ret = 0;
unsigned int i;
value = (chip & EMC_MRR_DEV_SEL_MASK) << EMC_MRR_DEV_SEL_SHIFT |
(address & EMC_MRR_MA_MASK) << EMC_MRR_MA_SHIFT;
emc_writel(emc, value, EMC_MRR);
for (i = 0; i < emc->num_channels; i++)
WARN(tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_MRR_DIVLD, 1),
"Timed out waiting for MRR %u (ch=%u)\n", address, i);
for (i = 0; i < emc->num_channels; i++) {
value = emc_channel_readl(emc, i, EMC_MRR);
value &= EMC_MRR_DATA_MASK;
ret = (ret << 16) | value;
}
return ret;
}
void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc)
{
int err;
mc_readl(emc->mc, MC_EMEM_ADR_CFG);
emc_readl(emc, EMC_INTSTATUS);
tegra210_clk_emc_update_setting(clksrc);
err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS,
EMC_INTSTATUS_CLKCHANGE_COMPLETE,
true);
if (err)
dev_warn(emc->dev, "clock change completion error: %d\n", err);
}
struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc,
unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (emc->timings[i].rate * 1000UL == rate)
return &emc->timings[i];
return NULL;
}
int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel,
unsigned int offset, u32 bit_mask, bool state)
{
unsigned int i;
u32 value;
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) {
value = emc_channel_readl(emc, channel, offset);
if (!!(value & bit_mask) == state)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set)
{
u32 emc_dbg = emc_readl(emc, EMC_DBG);
if (set)
emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG);
else
emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG);
}
u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next)
{
if (next->emc_emrs & 0x1)
return 0;
return 1;
}
void tegra210_emc_timing_update(struct tegra210_emc *emc)
{
unsigned int i;
int err = 0;
emc_writel(emc, 0x1, EMC_TIMING_CONTROL);
for (i = 0; i < emc->num_channels; i++) {
err |= tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_TIMING_UPDATE_STALLED,
false);
}
if (err)
dev_warn(emc->dev, "timing update error: %d\n", err);
}
unsigned long tegra210_emc_actual_osc_clocks(u32 in)
{
if (in < 0x40)
return in * 16;
else if (in < 0x80)
return 2048;
else if (in < 0xc0)
return 4096;
else
return 8192;
}
void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc)
{
u32 mpc_req = 0x4b;
emc_writel(emc, mpc_req, EMC_MPC);
mpc_req = emc_readl(emc, EMC_MPC);
}
u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset)
{
u32 temp = 0, rate = next->rate / 1000;
s32 delta[4], delta_taps[4];
s32 new[] = {
TRIM_REG(0, 0, 0, 0),
TRIM_REG(0, 0, 0, 1),
TRIM_REG(0, 0, 1, 2),
TRIM_REG(0, 0, 1, 3),
TRIM_REG(1, 0, 2, 4),
TRIM_REG(1, 0, 2, 5),
TRIM_REG(1, 0, 3, 6),
TRIM_REG(1, 0, 3, 7),
TRIM_REG(0, 1, 0, 0),
TRIM_REG(0, 1, 0, 1),
TRIM_REG(0, 1, 1, 2),
TRIM_REG(0, 1, 1, 3),
TRIM_REG(1, 1, 2, 4),
TRIM_REG(1, 1, 2, 5),
TRIM_REG(1, 1, 3, 6),
TRIM_REG(1, 1, 3, 7)
};
unsigned i;
switch (offset) {
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3:
case EMC_DATA_BRLSHFT_0:
delta[0] = 128 * (next->current_dram_clktree[C0D0U0] -
next->trained_dram_clktree[C0D0U0]);
delta[1] = 128 * (next->current_dram_clktree[C0D0U1] -
next->trained_dram_clktree[C0D0U1]);
delta[2] = 128 * (next->current_dram_clktree[C1D0U0] -
next->trained_dram_clktree[C1D0U0]);
delta[3] = 128 * (next->current_dram_clktree[C1D0U1] -
next->trained_dram_clktree[C1D0U1]);
delta_taps[0] = (delta[0] * (s32)rate) / 1000000;
delta_taps[1] = (delta[1] * (s32)rate) / 1000000;
delta_taps[2] = (delta[2] * (s32)rate) / 1000000;
delta_taps[3] = (delta[3] * (s32)rate) / 1000000;
for (i = 0; i < 4; i++) {
if ((delta_taps[i] > next->tree_margin) ||
(delta_taps[i] < (-1 * next->tree_margin))) {
new[i * 2] = new[i * 2] + delta_taps[i];
new[i * 2 + 1] = new[i * 2 + 1] +
delta_taps[i];
}
}
if (offset == EMC_DATA_BRLSHFT_0) {
for (i = 0; i < 8; i++)
new[i] = new[i] / 64;
} else {
for (i = 0; i < 8; i++)
new[i] = new[i] % 64;
}
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3:
case EMC_DATA_BRLSHFT_1:
delta[0] = 128 * (next->current_dram_clktree[C0D1U0] -
next->trained_dram_clktree[C0D1U0]);
delta[1] = 128 * (next->current_dram_clktree[C0D1U1] -
next->trained_dram_clktree[C0D1U1]);
delta[2] = 128 * (next->current_dram_clktree[C1D1U0] -
next->trained_dram_clktree[C1D1U0]);
delta[3] = 128 * (next->current_dram_clktree[C1D1U1] -
next->trained_dram_clktree[C1D1U1]);
delta_taps[0] = (delta[0] * (s32)rate) / 1000000;
delta_taps[1] = (delta[1] * (s32)rate) / 1000000;
delta_taps[2] = (delta[2] * (s32)rate) / 1000000;
delta_taps[3] = (delta[3] * (s32)rate) / 1000000;
for (i = 0; i < 4; i++) {
if ((delta_taps[i] > next->tree_margin) ||
(delta_taps[i] < (-1 * next->tree_margin))) {
new[8 + i * 2] = new[8 + i * 2] +
delta_taps[i];
new[8 + i * 2 + 1] = new[8 + i * 2 + 1] +
delta_taps[i];
}
}
if (offset == EMC_DATA_BRLSHFT_1) {
for (i = 0; i < 8; i++)
new[i + 8] = new[i + 8] / 64;
} else {
for (i = 0; i < 8; i++)
new[i + 8] = new[i + 8] % 64;
}
break;
}
switch (offset) {
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0:
temp = CALC_TEMP(0, 0, 0, 1, 0);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1:
temp = CALC_TEMP(0, 1, 2, 3, 2);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2:
temp = CALC_TEMP(0, 2, 4, 5, 4);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3:
temp = CALC_TEMP(0, 3, 6, 7, 6);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0:
temp = CALC_TEMP(1, 0, 0, 1, 8);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1:
temp = CALC_TEMP(1, 1, 2, 3, 10);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2:
temp = CALC_TEMP(1, 2, 4, 5, 12);
break;
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3:
temp = CALC_TEMP(1, 3, 6, 7, 14);
break;
case EMC_DATA_BRLSHFT_0:
temp = ((new[0] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK) |
((new[1] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK) |
((new[2] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK) |
((new[3] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK) |
((new[4] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK) |
((new[5] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK) |
((new[6] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK) |
((new[7] <<
EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK);
break;
case EMC_DATA_BRLSHFT_1:
temp = ((new[8] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK) |
((new[9] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK) |
((new[10] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK) |
((new[11] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK) |
((new[12] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK) |
((new[13] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK) |
((new[14] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK) |
((new[15] <<
EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) &
EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK);
break;
default:
break;
}
return temp;
}
u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc)
{
unsigned int i;
u32 value;
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK;
value |= (3 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT);
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK;
value |= (3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT);
value |= EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK;
emc_writel(emc, value, EMC_CFG_DIG_DLL);
emc_writel(emc, 1, EMC_TIMING_CONTROL);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_TIMING_UPDATE_STALLED,
0);
for (i = 0; i < emc->num_channels; i++) {
while (true) {
value = emc_channel_readl(emc, i, EMC_CFG_DIG_DLL);
if ((value & EMC_CFG_DIG_DLL_CFG_DLL_EN) == 0)
break;
}
}
value = emc->next->burst_regs[EMC_DLL_CFG_0_INDEX];
emc_writel(emc, value, EMC_DLL_CFG_0);
value = emc_readl(emc, EMC_DLL_CFG_1);
value &= EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK;
if (emc->next->rate >= 400000 && emc->next->rate < 600000)
value |= 150;
else if (emc->next->rate >= 600000 && emc->next->rate < 800000)
value |= 100;
else if (emc->next->rate >= 800000 && emc->next->rate < 1000000)
value |= 70;
else if (emc->next->rate >= 1000000 && emc->next->rate < 1200000)
value |= 30;
else
value |= 20;
emc_writel(emc, value, EMC_DLL_CFG_1);
tegra210_change_dll_src(emc, clksrc);
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value |= EMC_CFG_DIG_DLL_CFG_DLL_EN;
emc_writel(emc, value, EMC_CFG_DIG_DLL);
tegra210_emc_timing_update(emc);
for (i = 0; i < emc->num_channels; i++) {
while (true) {
value = emc_channel_readl(emc, 0, EMC_CFG_DIG_DLL);
if (value & EMC_CFG_DIG_DLL_CFG_DLL_EN)
break;
}
}
while (true) {
value = emc_readl(emc, EMC_DIG_DLL_STATUS);
if ((value & EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED) == 0)
continue;
if ((value & EMC_DIG_DLL_STATUS_DLL_LOCK) == 0)
continue;
break;
}
value = emc_readl(emc, EMC_DIG_DLL_STATUS);
return value & EMC_DIG_DLL_STATUS_DLL_OUT_MASK;
}
u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk,
bool flip_backward)
{
u32 cmd_pad, dq_pad, rfu1, cfg5, common_tx, ramp_up_wait = 0;
const struct tegra210_emc_timing *timing;
if (flip_backward)
timing = emc->last;
else
timing = emc->next;
cmd_pad = timing->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX];
dq_pad = timing->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
rfu1 = timing->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX];
cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX];
common_tx = timing->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX];
cmd_pad |= EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON;
if (clk < 1000000 / DVFS_FGCG_MID_SPEED_THRESHOLD) {
ccfifo_writel(emc, common_tx & 0xa,
EMC_PMACRO_COMMON_PAD_TX_CTRL, 0);
ccfifo_writel(emc, common_tx & 0xf,
EMC_PMACRO_COMMON_PAD_TX_CTRL,
(100000 / clk) + 1);
ramp_up_wait += 100000;
} else {
ccfifo_writel(emc, common_tx | 0x8,
EMC_PMACRO_COMMON_PAD_TX_CTRL, 0);
}
if (clk < 1000000 / DVFS_FGCG_HIGH_SPEED_THRESHOLD) {
if (clk < 1000000 / IOBRICK_DCC_THRESHOLD) {
cmd_pad |=
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC;
cmd_pad &=
~(EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC);
ccfifo_writel(emc, cmd_pad,
EMC_PMACRO_CMD_PAD_TX_CTRL,
(100000 / clk) + 1);
ramp_up_wait += 100000;
dq_pad |=
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC;
dq_pad &=
~(EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC);
ccfifo_writel(emc, dq_pad,
EMC_PMACRO_DATA_PAD_TX_CTRL, 0);
ccfifo_writel(emc, rfu1 & 0xfe40fe40,
EMC_PMACRO_BRICK_CTRL_RFU1, 0);
} else {
ccfifo_writel(emc, rfu1 & 0xfe40fe40,
EMC_PMACRO_BRICK_CTRL_RFU1,
(100000 / clk) + 1);
ramp_up_wait += 100000;
}
ccfifo_writel(emc, rfu1 & 0xfeedfeed,
EMC_PMACRO_BRICK_CTRL_RFU1, (100000 / clk) + 1);
ramp_up_wait += 100000;
if (clk < 1000000 / IOBRICK_DCC_THRESHOLD) {
cmd_pad |=
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC;
ccfifo_writel(emc, cmd_pad,
EMC_PMACRO_CMD_PAD_TX_CTRL,
(100000 / clk) + 1);
ramp_up_wait += 100000;
dq_pad |=
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC;
ccfifo_writel(emc, dq_pad,
EMC_PMACRO_DATA_PAD_TX_CTRL, 0);
ccfifo_writel(emc, rfu1,
EMC_PMACRO_BRICK_CTRL_RFU1, 0);
} else {
ccfifo_writel(emc, rfu1,
EMC_PMACRO_BRICK_CTRL_RFU1,
(100000 / clk) + 1);
ramp_up_wait += 100000;
}
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
EMC_FBIO_CFG5, (100000 / clk) + 10);
ramp_up_wait += 100000 + (10 * clk);
} else if (clk < 1000000 / DVFS_FGCG_MID_SPEED_THRESHOLD) {
ccfifo_writel(emc, rfu1 | 0x06000600,
EMC_PMACRO_BRICK_CTRL_RFU1, (100000 / clk) + 1);
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
EMC_FBIO_CFG5, (100000 / clk) + 10);
ramp_up_wait += 100000 + 10 * clk;
} else {
ccfifo_writel(emc, rfu1 | 0x00000600,
EMC_PMACRO_BRICK_CTRL_RFU1, 0);
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
EMC_FBIO_CFG5, 12);
ramp_up_wait += 12 * clk;
}
cmd_pad &= ~EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON;
ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 5);
return ramp_up_wait;
}
u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk,
bool flip_backward)
{
u32 ramp_down_wait = 0, cmd_pad, dq_pad, rfu1, cfg5, common_tx;
const struct tegra210_emc_timing *entry;
u32 seq_wait;
if (flip_backward)
entry = emc->next;
else
entry = emc->last;
cmd_pad = entry->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX];
dq_pad = entry->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
rfu1 = entry->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX];
cfg5 = entry->burst_regs[EMC_FBIO_CFG5_INDEX];
common_tx = entry->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX];
cmd_pad |= EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON;
ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 0);
ccfifo_writel(emc, cfg5 | EMC_FBIO_CFG5_CMD_TX_DIS,
EMC_FBIO_CFG5, 12);
ramp_down_wait = 12 * clk;
seq_wait = (100000 / clk) + 1;
if (clk < (1000000 / DVFS_FGCG_HIGH_SPEED_THRESHOLD)) {
if (clk < (1000000 / IOBRICK_DCC_THRESHOLD)) {
cmd_pad &=
~(EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC);
cmd_pad |=
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC;
ccfifo_writel(emc, cmd_pad,
EMC_PMACRO_CMD_PAD_TX_CTRL, seq_wait);
ramp_down_wait += 100000;
dq_pad &=
~(EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC);
dq_pad |=
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC;
ccfifo_writel(emc, dq_pad,
EMC_PMACRO_DATA_PAD_TX_CTRL, 0);
ccfifo_writel(emc, rfu1 & ~0x01120112,
EMC_PMACRO_BRICK_CTRL_RFU1, 0);
} else {
ccfifo_writel(emc, rfu1 & ~0x01120112,
EMC_PMACRO_BRICK_CTRL_RFU1, seq_wait);
ramp_down_wait += 100000;
}
ccfifo_writel(emc, rfu1 & ~0x01bf01bf,
EMC_PMACRO_BRICK_CTRL_RFU1, seq_wait);
ramp_down_wait += 100000;
if (clk < (1000000 / IOBRICK_DCC_THRESHOLD)) {
cmd_pad &=
~(EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC);
ccfifo_writel(emc, cmd_pad,
EMC_PMACRO_CMD_PAD_TX_CTRL, seq_wait);
ramp_down_wait += 100000;
dq_pad &=
~(EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC);
ccfifo_writel(emc, dq_pad,
EMC_PMACRO_DATA_PAD_TX_CTRL, 0);
ccfifo_writel(emc, rfu1 & ~0x07ff07ff,
EMC_PMACRO_BRICK_CTRL_RFU1, 0);
} else {
ccfifo_writel(emc, rfu1 & ~0x07ff07ff,
EMC_PMACRO_BRICK_CTRL_RFU1, seq_wait);
ramp_down_wait += 100000;
}
} else {
ccfifo_writel(emc, rfu1 & ~0xffff07ff,
EMC_PMACRO_BRICK_CTRL_RFU1, seq_wait + 19);
ramp_down_wait += 100000 + (20 * clk);
}
if (clk < (1000000 / DVFS_FGCG_MID_SPEED_THRESHOLD)) {
ramp_down_wait += 100000;
ccfifo_writel(emc, common_tx & ~0x5,
EMC_PMACRO_COMMON_PAD_TX_CTRL, seq_wait);
ramp_down_wait += 100000;
ccfifo_writel(emc, common_tx & ~0xf,
EMC_PMACRO_COMMON_PAD_TX_CTRL, seq_wait);
ramp_down_wait += 100000;
ccfifo_writel(emc, 0, 0, seq_wait);
ramp_down_wait += 100000;
} else {
ccfifo_writel(emc, common_tx & ~0xf,
EMC_PMACRO_COMMON_PAD_TX_CTRL, seq_wait);
}
return ramp_down_wait;
}
void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing)
{
timing->current_dram_clktree[C0D0U0] =
timing->trained_dram_clktree[C0D0U0];
timing->current_dram_clktree[C0D0U1] =
timing->trained_dram_clktree[C0D0U1];
timing->current_dram_clktree[C1D0U0] =
timing->trained_dram_clktree[C1D0U0];
timing->current_dram_clktree[C1D0U1] =
timing->trained_dram_clktree[C1D0U1];
timing->current_dram_clktree[C1D1U0] =
timing->trained_dram_clktree[C1D1U0];
timing->current_dram_clktree[C1D1U1] =
timing->trained_dram_clktree[C1D1U1];
}
static void update_dll_control(struct tegra210_emc *emc, u32 value, bool state)
{
unsigned int i;
emc_writel(emc, value, EMC_CFG_DIG_DLL);
tegra210_emc_timing_update(emc);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_CFG_DLL_EN,
state);
}
void tegra210_emc_dll_disable(struct tegra210_emc *emc)
{
u32 value;
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;
update_dll_control(emc, value, false);
}
void tegra210_emc_dll_enable(struct tegra210_emc *emc)
{
u32 value;
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value |= EMC_CFG_DIG_DLL_CFG_DLL_EN;
update_dll_control(emc, value, true);
}
void tegra210_emc_adjust_timing(struct tegra210_emc *emc,
struct tegra210_emc_timing *timing)
{
u32 dsr_cntrl = timing->burst_regs[EMC_DYN_SELF_REF_CONTROL_INDEX];
u32 pre_ref = timing->burst_regs[EMC_PRE_REFRESH_REQ_CNT_INDEX];
u32 ref = timing->burst_regs[EMC_REFRESH_INDEX];
switch (emc->refresh) {
case TEGRA210_EMC_REFRESH_NOMINAL:
case TEGRA210_EMC_REFRESH_THROTTLE:
break;
case TEGRA210_EMC_REFRESH_2X:
ref = REFRESH_SPEEDUP(ref, 2);
pre_ref = REFRESH_SPEEDUP(pre_ref, 2);
dsr_cntrl = REFRESH_SPEEDUP(dsr_cntrl, 2);
break;
case TEGRA210_EMC_REFRESH_4X:
ref = REFRESH_SPEEDUP(ref, 4);
pre_ref = REFRESH_SPEEDUP(pre_ref, 4);
dsr_cntrl = REFRESH_SPEEDUP(dsr_cntrl, 4);
break;
default:
dev_warn(emc->dev, "failed to set refresh: %d\n", emc->refresh);
return;
}
emc_writel(emc, ref, emc->offsets->burst[EMC_REFRESH_INDEX]);
emc_writel(emc, pre_ref,
emc->offsets->burst[EMC_PRE_REFRESH_REQ_CNT_INDEX]);
emc_writel(emc, dsr_cntrl,
emc->offsets->burst[EMC_DYN_SELF_REF_CONTROL_INDEX]);
}
static int tegra210_emc_set_rate(struct device *dev,
const struct tegra210_clk_emc_config *config)
{
struct tegra210_emc *emc = dev_get_drvdata(dev);
struct tegra210_emc_timing *timing = NULL;
unsigned long rate = config->rate;
s64 last_change_delay;
unsigned long flags;
unsigned int i;
if (rate == emc->last->rate * 1000UL)
return 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate * 1000UL == rate) {
timing = &emc->timings[i];
break;
}
}
if (!timing)
return -EINVAL;
if (rate > 204000000 && !timing->trained)
return -EINVAL;
emc->next = timing;
last_change_delay = ktime_us_delta(ktime_get(), emc->clkchange_time);
/* XXX use non-busy-looping sleep? */
if ((last_change_delay >= 0) &&
(last_change_delay < emc->clkchange_delay))
udelay(emc->clkchange_delay - (int)last_change_delay);
spin_lock_irqsave(&emc->lock, flags);
tegra210_emc_set_clock(emc, config->value);
emc->clkchange_time = ktime_get();
emc->last = timing;
spin_unlock_irqrestore(&emc->lock, flags);
return 0;
}
/*
* debugfs interface
*
* The memory controller driver exposes some files in debugfs that can be used
* to control the EMC frequency. The top-level directory can be found here:
*
* /sys/kernel/debug/emc
*
* It contains the following files:
*
* - available_rates: This file contains a list of valid, space-separated
* EMC frequencies.
*
* - min_rate: Writing a value to this file sets the given frequency as the
* floor of the permitted range. If this is higher than the currently
* configured EMC frequency, this will cause the frequency to be
* increased so that it stays within the valid range.
*
* - max_rate: Similarily to the min_rate file, writing a value to this file
* sets the given frequency as the ceiling of the permitted range. If
* the value is lower than the currently configured EMC frequency, this
* will cause the frequency to be decreased so that it stays within the
* valid range.
*/
static bool tegra210_emc_validate_rate(struct tegra210_emc *emc,
unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (rate == emc->timings[i].rate * 1000UL)
return true;
return false;
}
static int tegra210_emc_debug_available_rates_show(struct seq_file *s,
void *data)
{
struct tegra210_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
seq_printf(s, "%s%u", prefix, emc->timings[i].rate * 1000);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(tegra210_emc_debug_available_rates);
static int tegra210_emc_debug_min_rate_get(void *data, u64 *rate)
{
struct tegra210_emc *emc = data;
*rate = emc->debugfs.min_rate;
return 0;
}
static int tegra210_emc_debug_min_rate_set(void *data, u64 rate)
{
struct tegra210_emc *emc = data;
int err;
if (!tegra210_emc_validate_rate(emc, rate))
return -EINVAL;
err = clk_set_min_rate(emc->clk, rate);
if (err < 0)
return err;
emc->debugfs.min_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_min_rate_fops,
tegra210_emc_debug_min_rate_get,
tegra210_emc_debug_min_rate_set, "%llu\n");
static int tegra210_emc_debug_max_rate_get(void *data, u64 *rate)
{
struct tegra210_emc *emc = data;
*rate = emc->debugfs.max_rate;
return 0;
}
static int tegra210_emc_debug_max_rate_set(void *data, u64 rate)
{
struct tegra210_emc *emc = data;
int err;
if (!tegra210_emc_validate_rate(emc, rate))
return -EINVAL;
err = clk_set_max_rate(emc->clk, rate);
if (err < 0)
return err;
emc->debugfs.max_rate = rate;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_max_rate_fops,
tegra210_emc_debug_max_rate_get,
tegra210_emc_debug_max_rate_set, "%llu\n");
static int tegra210_emc_debug_temperature_get(void *data, u64 *temperature)
{
struct tegra210_emc *emc = data;
unsigned int value;
if (!emc->debugfs.temperature)
value = tegra210_emc_get_temperature(emc);
else
value = emc->debugfs.temperature;
*temperature = value;
return 0;
}
static int tegra210_emc_debug_temperature_set(void *data, u64 temperature)
{
struct tegra210_emc *emc = data;
if (temperature > 7)
return -EINVAL;
emc->debugfs.temperature = temperature;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(tegra210_emc_debug_temperature_fops,
tegra210_emc_debug_temperature_get,
tegra210_emc_debug_temperature_set, "%llu\n");
static void tegra210_emc_debugfs_init(struct tegra210_emc *emc)
{
struct device *dev = emc->dev;
unsigned int i;
int err;
emc->debugfs.min_rate = ULONG_MAX;
emc->debugfs.max_rate = 0;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate * 1000UL < emc->debugfs.min_rate)
emc->debugfs.min_rate = emc->timings[i].rate * 1000UL;
if (emc->timings[i].rate * 1000UL > emc->debugfs.max_rate)
emc->debugfs.max_rate = emc->timings[i].rate * 1000UL;
}
if (!emc->num_timings) {
emc->debugfs.min_rate = clk_get_rate(emc->clk);
emc->debugfs.max_rate = emc->debugfs.min_rate;
}
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
emc->debugfs.max_rate);
if (err < 0) {
dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
emc->debugfs.min_rate, emc->debugfs.max_rate,
emc->clk);
return;
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra210_emc_debug_available_rates_fops);
debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
&tegra210_emc_debug_min_rate_fops);
debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
&tegra210_emc_debug_max_rate_fops);
debugfs_create_file("temperature", 0644, emc->debugfs.root, emc,
&tegra210_emc_debug_temperature_fops);
}
static void tegra210_emc_detect(struct tegra210_emc *emc)
{
u32 value;
/* probe the number of connected DRAM devices */
value = mc_readl(emc->mc, MC_EMEM_ADR_CFG);
if (value & MC_EMEM_ADR_CFG_EMEM_NUMDEV)
emc->num_devices = 2;
else
emc->num_devices = 1;
/* probe the type of DRAM */
value = emc_readl(emc, EMC_FBIO_CFG5);
emc->dram_type = value & 0x3;
/* probe the number of channels */
value = emc_readl(emc, EMC_FBIO_CFG7);
if ((value & EMC_FBIO_CFG7_CH1_ENABLE) &&
(value & EMC_FBIO_CFG7_CH0_ENABLE))
emc->num_channels = 2;
else
emc->num_channels = 1;
}
static int tegra210_emc_validate_timings(struct tegra210_emc *emc,
struct tegra210_emc_timing *timings,
unsigned int num_timings)
{
unsigned int i;
for (i = 0; i < num_timings; i++) {
u32 min_volt = timings[i].min_volt;
u32 rate = timings[i].rate;
if (!rate)
return -EINVAL;
if ((i > 0) && ((rate <= timings[i - 1].rate) ||
(min_volt < timings[i - 1].min_volt)))
return -EINVAL;
if (timings[i].revision != timings[0].revision)
continue;
}
return 0;
}
static int tegra210_emc_probe(struct platform_device *pdev)
{
struct thermal_cooling_device *cd;
unsigned long current_rate;
struct tegra210_emc *emc;
struct device_node *np;
unsigned int i;
int err;
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
if (!emc)
return -ENOMEM;
emc->clk = devm_clk_get(&pdev->dev, "emc");
if (IS_ERR(emc->clk))
return PTR_ERR(emc->clk);
platform_set_drvdata(pdev, emc);
spin_lock_init(&emc->lock);
emc->dev = &pdev->dev;
emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
if (IS_ERR(emc->mc))
return PTR_ERR(emc->mc);
emc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(emc->regs))
return PTR_ERR(emc->regs);
for (i = 0; i < 2; i++) {
emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i);
if (IS_ERR(emc->channel[i]))
return PTR_ERR(emc->channel[i]);
}
tegra210_emc_detect(emc);
np = pdev->dev.of_node;
/* attach to the nominal and (optional) derated tables */
err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal");
if (err < 0) {
dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err);
return err;
}
err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated");
if (err < 0 && err != -ENODEV) {
dev_err(emc->dev, "failed to get derated EMC table: %d\n", err);
goto release;
}
/* validate the tables */
if (emc->nominal) {
err = tegra210_emc_validate_timings(emc, emc->nominal,
emc->num_timings);
if (err < 0)
goto release;
}
if (emc->derated) {
err = tegra210_emc_validate_timings(emc, emc->derated,
emc->num_timings);
if (err < 0)
goto release;
}
/* default to the nominal table */
emc->timings = emc->nominal;
/* pick the current timing based on the current EMC clock rate */
current_rate = clk_get_rate(emc->clk) / 1000;
for (i = 0; i < emc->num_timings; i++) {
if (emc->timings[i].rate == current_rate) {
emc->last = &emc->timings[i];
break;
}
}
if (i == emc->num_timings) {
dev_err(emc->dev, "no EMC table entry found for %lu kHz\n",
current_rate);
err = -ENOENT;
goto release;
}
/* pick a compatible clock change sequence for the EMC table */
for (i = 0; i < ARRAY_SIZE(tegra210_emc_sequences); i++) {
const struct tegra210_emc_sequence *sequence =
tegra210_emc_sequences[i];
if (emc->timings[0].revision == sequence->revision) {
emc->sequence = sequence;
break;
}
}
if (!emc->sequence) {
dev_err(&pdev->dev, "sequence %u not supported\n",
emc->timings[0].revision);
err = -ENOTSUPP;
goto release;
}
emc->offsets = &tegra210_emc_table_register_offsets;
emc->refresh = TEGRA210_EMC_REFRESH_NOMINAL;
emc->provider.owner = THIS_MODULE;
emc->provider.dev = &pdev->dev;
emc->provider.set_rate = tegra210_emc_set_rate;
emc->provider.configs = devm_kcalloc(&pdev->dev, emc->num_timings,
sizeof(*emc->provider.configs),
GFP_KERNEL);
if (!emc->provider.configs) {
err = -ENOMEM;
goto release;
}
emc->provider.num_configs = emc->num_timings;
for (i = 0; i < emc->provider.num_configs; i++) {
struct tegra210_emc_timing *timing = &emc->timings[i];
struct tegra210_clk_emc_config *config =
&emc->provider.configs[i];
u32 value;
config->rate = timing->rate * 1000UL;
config->value = timing->clk_src_emc;
value = timing->burst_mc_regs[MC_EMEM_ARB_MISC0_INDEX];
if ((value & MC_EMEM_ARB_MISC0_EMC_SAME_FREQ) == 0)
config->same_freq = false;
else
config->same_freq = true;
}
err = tegra210_clk_emc_attach(emc->clk, &emc->provider);
if (err < 0) {
dev_err(&pdev->dev, "failed to attach to EMC clock: %d\n", err);
goto release;
}
emc->clkchange_delay = 100;
emc->training_interval = 100;
dev_set_drvdata(emc->dev, emc);
timer_setup(&emc->refresh_timer, tegra210_emc_poll_refresh,
TIMER_DEFERRABLE);
atomic_set(&emc->refresh_poll, 0);
emc->refresh_poll_interval = 1000;
timer_setup(&emc->training, tegra210_emc_train, 0);
tegra210_emc_debugfs_init(emc);
cd = devm_thermal_of_cooling_device_register(emc->dev, np, "emc", emc,
&tegra210_emc_cd_ops);
if (IS_ERR(cd)) {
err = PTR_ERR(cd);
dev_err(emc->dev, "failed to register cooling device: %d\n",
err);
goto detach;
}
return 0;
detach:
debugfs_remove_recursive(emc->debugfs.root);
tegra210_clk_emc_detach(emc->clk);
release:
of_reserved_mem_device_release(emc->dev);
return err;
}
static int tegra210_emc_remove(struct platform_device *pdev)
{
struct tegra210_emc *emc = platform_get_drvdata(pdev);
debugfs_remove_recursive(emc->debugfs.root);
tegra210_clk_emc_detach(emc->clk);
of_reserved_mem_device_release(emc->dev);
return 0;
}
static int __maybe_unused tegra210_emc_suspend(struct device *dev)
{
struct tegra210_emc *emc = dev_get_drvdata(dev);
int err;
err = clk_rate_exclusive_get(emc->clk);
if (err < 0) {
dev_err(emc->dev, "failed to acquire clock: %d\n", err);
return err;
}
emc->resume_rate = clk_get_rate(emc->clk);
clk_set_rate(emc->clk, 204000000);
tegra210_clk_emc_detach(emc->clk);
dev_dbg(dev, "suspending at %lu Hz\n", clk_get_rate(emc->clk));
return 0;
}
static int __maybe_unused tegra210_emc_resume(struct device *dev)
{
struct tegra210_emc *emc = dev_get_drvdata(dev);
int err;
err = tegra210_clk_emc_attach(emc->clk, &emc->provider);
if (err < 0) {
dev_err(dev, "failed to attach to EMC clock: %d\n", err);
return err;
}
clk_set_rate(emc->clk, emc->resume_rate);
clk_rate_exclusive_put(emc->clk);
dev_dbg(dev, "resuming at %lu Hz\n", clk_get_rate(emc->clk));
return 0;
}
static const struct dev_pm_ops tegra210_emc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra210_emc_suspend, tegra210_emc_resume)
};
static const struct of_device_id tegra210_emc_of_match[] = {
{ .compatible = "nvidia,tegra210-emc", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra210_emc_of_match);
static struct platform_driver tegra210_emc_driver = {
.driver = {
.name = "tegra210-emc",
.of_match_table = tegra210_emc_of_match,
.pm = &tegra210_emc_pm_ops,
},
.probe = tegra210_emc_probe,
.remove = tegra210_emc_remove,
};
module_platform_driver(tegra210_emc_driver);
MODULE_AUTHOR("Thierry Reding <[email protected]>");
MODULE_AUTHOR("Joseph Lo <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra210 EMC driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/memory/tegra/tegra210-emc-core.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <soc/tegra/mc.h>
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
#include <dt-bindings/memory/tegra186-mc.h>
#endif
#include "mc.h"
#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
static int tegra186_mc_probe(struct tegra_mc *mc)
{
struct platform_device *pdev = to_platform_device(mc->dev);
unsigned int i;
char name[8];
int err;
mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
if (IS_ERR(mc->bcast_ch_regs)) {
if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
dev_warn(&pdev->dev,
"Broadcast channel is missing, please update your device-tree\n");
mc->bcast_ch_regs = NULL;
goto populate;
}
return PTR_ERR(mc->bcast_ch_regs);
}
mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
GFP_KERNEL);
if (!mc->ch_regs)
return -ENOMEM;
for (i = 0; i < mc->soc->num_channels; i++) {
snprintf(name, sizeof(name), "ch%u", i);
mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
if (IS_ERR(mc->ch_regs[i]))
return PTR_ERR(mc->ch_regs[i]);
}
populate:
err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
if (err < 0)
return err;
return 0;
}
static void tegra186_mc_remove(struct tegra_mc *mc)
{
of_platform_depopulate(mc->dev);
}
#if IS_ENABLED(CONFIG_IOMMU_API)
static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
const struct tegra_mc_client *client,
unsigned int sid)
{
u32 value, old;
value = readl(mc->regs + client->regs.sid.security);
if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
/*
* If the secure firmware has locked this down the override
* for this memory client, there's nothing we can do here.
*/
if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
return;
/*
* Otherwise, try to set the override itself. Typically the
* secure firmware will never have set this configuration.
* Instead, it will either have disabled write access to
* this field, or it will already have set an explicit
* override itself.
*/
WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
writel(value, mc->regs + client->regs.sid.security);
}
value = readl(mc->regs + client->regs.sid.override);
old = value & MC_SID_STREAMID_OVERRIDE_MASK;
if (old != sid) {
dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
client->name, sid);
writel(sid, mc->regs + client->regs.sid.override);
}
}
#endif
static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
#if IS_ENABLED(CONFIG_IOMMU_API)
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
struct of_phandle_args args;
unsigned int i, index = 0;
while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
index, &args)) {
if (args.np == mc->dev->of_node && args.args_count != 0) {
for (i = 0; i < mc->soc->num_clients; i++) {
const struct tegra_mc_client *client = &mc->soc->clients[i];
if (client->id == args.args[0]) {
u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
tegra186_mc_client_sid_override(mc, client, sid);
}
}
}
index++;
}
#endif
return 0;
}
const struct tegra_mc_ops tegra186_mc_ops = {
.probe = tegra186_mc_probe,
.remove = tegra186_mc_remove,
.probe_device = tegra186_mc_probe_device,
.handle_irq = tegra30_mc_handle_irq,
};
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
static const struct tegra_mc_client tegra186_mc_clients[] = {
{
.id = TEGRA186_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x000,
.security = 0x004,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AFIR,
.name = "afir",
.sid = TEGRA186_SID_AFI,
.regs = {
.sid = {
.override = 0x070,
.security = 0x074,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA186_SID_HDA,
.regs = {
.sid = {
.override = 0x0a8,
.security = 0x0ac,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA186_SID_HOST1X,
.regs = {
.sid = {
.override = 0x0b0,
.security = 0x0b4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA186_SID_NVENC,
.regs = {
.sid = {
.override = 0x0e0,
.security = 0x0e4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA186_SID_SATA,
.regs = {
.sid = {
.override = 0x0f8,
.security = 0x0fc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x138,
.security = 0x13c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.sid = TEGRA186_SID_NVENC,
.regs = {
.sid = {
.override = 0x158,
.security = 0x15c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AFIW,
.name = "afiw",
.sid = TEGRA186_SID_AFI,
.regs = {
.sid = {
.override = 0x188,
.security = 0x18c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.sid = TEGRA186_SID_HDA,
.regs = {
.sid = {
.override = 0x1a8,
.security = 0x1ac,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
.sid = {
.override = 0x1c8,
.security = 0x1cc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SATAW,
.name = "sataw",
.sid = TEGRA186_SID_SATA,
.regs = {
.sid = {
.override = 0x1e8,
.security = 0x1ec,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_ISPRA,
.name = "ispra",
.sid = TEGRA186_SID_ISP,
.regs = {
.sid = {
.override = 0x220,
.security = 0x224,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_ISPWA,
.name = "ispwa",
.sid = TEGRA186_SID_ISP,
.regs = {
.sid = {
.override = 0x230,
.security = 0x234,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_ISPWB,
.name = "ispwb",
.sid = TEGRA186_SID_ISP,
.regs = {
.sid = {
.override = 0x238,
.security = 0x23c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
.name = "xusb_hostr",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
.sid = {
.override = 0x250,
.security = 0x254,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
.name = "xusb_hostw",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
.sid = {
.override = 0x258,
.security = 0x25c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
.name = "xusb_devr",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
.sid = {
.override = 0x260,
.security = 0x264,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
.name = "xusb_devw",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
.sid = {
.override = 0x268,
.security = 0x26c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_TSECSRD,
.name = "tsecsrd",
.sid = TEGRA186_SID_TSEC,
.regs = {
.sid = {
.override = 0x2a0,
.security = 0x2a4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_TSECSWR,
.name = "tsecswr",
.sid = TEGRA186_SID_TSEC,
.regs = {
.sid = {
.override = 0x2a8,
.security = 0x2ac,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_GPUSRD,
.name = "gpusrd",
.sid = TEGRA186_SID_GPU,
.regs = {
.sid = {
.override = 0x2c0,
.security = 0x2c4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_GPUSWR,
.name = "gpuswr",
.sid = TEGRA186_SID_GPU,
.regs = {
.sid = {
.override = 0x2c8,
.security = 0x2cc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
.name = "sdmmcra",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
.sid = {
.override = 0x300,
.security = 0x304,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
.name = "sdmmcraa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
.sid = {
.override = 0x308,
.security = 0x30c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCR,
.name = "sdmmcr",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
.sid = {
.override = 0x310,
.security = 0x314,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x318,
.security = 0x31c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
.name = "sdmmcwa",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
.sid = {
.override = 0x320,
.security = 0x324,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
.name = "sdmmcwaa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
.sid = {
.override = 0x328,
.security = 0x32c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCW,
.name = "sdmmcw",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
.sid = {
.override = 0x330,
.security = 0x334,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
.sid = {
.override = 0x338,
.security = 0x33c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.sid = TEGRA186_SID_VIC,
.regs = {
.sid = {
.override = 0x360,
.security = 0x364,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.sid = TEGRA186_SID_VIC,
.regs = {
.sid = {
.override = 0x368,
.security = 0x36c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_VIW,
.name = "viw",
.sid = TEGRA186_SID_VI,
.regs = {
.sid = {
.override = 0x390,
.security = 0x394,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c0,
.security = 0x3c4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.sid = {
.override = 0x3c8,
.security = 0x3cc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_APER,
.name = "aper",
.sid = TEGRA186_SID_APE,
.regs = {
.sid = {
.override = 0x3d0,
.security = 0x3d4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_APEW,
.name = "apew",
.sid = TEGRA186_SID_APE,
.regs = {
.sid = {
.override = 0x3d8,
.security = 0x3dc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.sid = TEGRA186_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f0,
.security = 0x3f4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.sid = TEGRA186_SID_NVJPG,
.regs = {
.sid = {
.override = 0x3f8,
.security = 0x3fc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SESRD,
.name = "sesrd",
.sid = TEGRA186_SID_SE,
.regs = {
.sid = {
.override = 0x400,
.security = 0x404,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SESWR,
.name = "seswr",
.sid = TEGRA186_SID_SE,
.regs = {
.sid = {
.override = 0x408,
.security = 0x40c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_ETRR,
.name = "etrr",
.sid = TEGRA186_SID_ETR,
.regs = {
.sid = {
.override = 0x420,
.security = 0x424,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_ETRW,
.name = "etrw",
.sid = TEGRA186_SID_ETR,
.regs = {
.sid = {
.override = 0x428,
.security = 0x42c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
.name = "tsecsrdb",
.sid = TEGRA186_SID_TSECB,
.regs = {
.sid = {
.override = 0x430,
.security = 0x434,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
.name = "tsecswrb",
.sid = TEGRA186_SID_TSECB,
.regs = {
.sid = {
.override = 0x438,
.security = 0x43c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
.name = "gpusrd2",
.sid = TEGRA186_SID_GPU,
.regs = {
.sid = {
.override = 0x440,
.security = 0x444,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
.name = "gpuswr2",
.sid = TEGRA186_SID_GPU,
.regs = {
.sid = {
.override = 0x448,
.security = 0x44c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AXISR,
.name = "axisr",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
.sid = {
.override = 0x460,
.security = 0x464,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AXISW,
.name = "axisw",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
.sid = {
.override = 0x468,
.security = 0x46c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_EQOSR,
.name = "eqosr",
.sid = TEGRA186_SID_EQOS,
.regs = {
.sid = {
.override = 0x470,
.security = 0x474,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_EQOSW,
.name = "eqosw",
.sid = TEGRA186_SID_EQOS,
.regs = {
.sid = {
.override = 0x478,
.security = 0x47c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_UFSHCR,
.name = "ufshcr",
.sid = TEGRA186_SID_UFSHC,
.regs = {
.sid = {
.override = 0x480,
.security = 0x484,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_UFSHCW,
.name = "ufshcw",
.sid = TEGRA186_SID_UFSHC,
.regs = {
.sid = {
.override = 0x488,
.security = 0x48c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
.sid = {
.override = 0x490,
.security = 0x494,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA186_SID_BPMP,
.regs = {
.sid = {
.override = 0x498,
.security = 0x49c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA186_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a0,
.security = 0x4a4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA186_SID_BPMP,
.regs = {
.sid = {
.override = 0x4a8,
.security = 0x4ac,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA186_SID_BPMP,
.regs = {
.sid = {
.override = 0x4b0,
.security = 0x4b4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AONR,
.name = "aonr",
.sid = TEGRA186_SID_AON,
.regs = {
.sid = {
.override = 0x4b8,
.security = 0x4bc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AONW,
.name = "aonw",
.sid = TEGRA186_SID_AON,
.regs = {
.sid = {
.override = 0x4c0,
.security = 0x4c4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AONDMAR,
.name = "aondmar",
.sid = TEGRA186_SID_AON,
.regs = {
.sid = {
.override = 0x4c8,
.security = 0x4cc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_AONDMAW,
.name = "aondmaw",
.sid = TEGRA186_SID_AON,
.regs = {
.sid = {
.override = 0x4d0,
.security = 0x4d4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SCER,
.name = "scer",
.sid = TEGRA186_SID_SCE,
.regs = {
.sid = {
.override = 0x4d8,
.security = 0x4dc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SCEW,
.name = "scew",
.sid = TEGRA186_SID_SCE,
.regs = {
.sid = {
.override = 0x4e0,
.security = 0x4e4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
.name = "scedmar",
.sid = TEGRA186_SID_SCE,
.regs = {
.sid = {
.override = 0x4e8,
.security = 0x4ec,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
.name = "scedmaw",
.sid = TEGRA186_SID_SCE,
.regs = {
.sid = {
.override = 0x4f0,
.security = 0x4f4,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.sid = TEGRA186_SID_APE,
.regs = {
.sid = {
.override = 0x4f8,
.security = 0x4fc,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.sid = TEGRA186_SID_APE,
.regs = {
.sid = {
.override = 0x500,
.security = 0x504,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
.sid = {
.override = 0x508,
.security = 0x50c,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_VICSRD1,
.name = "vicsrd1",
.sid = TEGRA186_SID_VIC,
.regs = {
.sid = {
.override = 0x510,
.security = 0x514,
},
},
}, {
.id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
.name = "nvdecsrd1",
.sid = TEGRA186_SID_NVDEC,
.regs = {
.sid = {
.override = 0x518,
.security = 0x51c,
},
},
},
};
const struct tegra_mc_soc tegra186_mc_soc = {
.num_clients = ARRAY_SIZE(tegra186_mc_clients),
.clients = tegra186_mc_clients,
.num_address_bits = 40,
.num_channels = 4,
.client_id_mask = 0xff,
.intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
.ops = &tegra186_mc_ops,
.ch_intmask = 0x0000000f,
.global_intstatus_channel_shift = 0,
};
#endif
|
linux-master
|
drivers/memory/tegra/tegra186.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sort.h>
#include <linux/tegra-icc.h>
#include <soc/tegra/fuse.h>
#include "mc.h"
static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_114_SOC
{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_124_SOC
{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_132_SOC
{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_186_SOC
{ .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_194_SOC
{ .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_234_SOC
{ .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
static void tegra_mc_devm_action_put_device(void *data)
{
struct tegra_mc *mc = data;
put_device(mc->dev);
}
/**
* devm_tegra_memory_controller_get() - get Tegra Memory Controller handle
* @dev: device pointer for the consumer device
*
* This function will search for the Memory Controller node in a device-tree
* and retrieve the Memory Controller handle.
*
* Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc.
*/
struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
{
struct platform_device *pdev;
struct device_node *np;
struct tegra_mc *mc;
int err;
np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0);
if (!np)
return ERR_PTR(-ENOENT);
pdev = of_find_device_by_node(np);
of_node_put(np);
if (!pdev)
return ERR_PTR(-ENODEV);
mc = platform_get_drvdata(pdev);
if (!mc) {
put_device(&pdev->dev);
return ERR_PTR(-EPROBE_DEFER);
}
err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc);
if (err)
return ERR_PTR(err);
return mc;
}
EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
{
if (mc->soc->ops && mc->soc->ops->probe_device)
return mc->soc->ops->probe_device(mc, dev);
return 0;
}
EXPORT_SYMBOL_GPL(tegra_mc_probe_device);
int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
phys_addr_t *base, u64 *size)
{
u32 offset;
if (id < 1 || id >= mc->soc->num_carveouts)
return -EINVAL;
if (id < 6)
offset = 0xc0c + 0x50 * (id - 1);
else
offset = 0x2004 + 0x50 * (id - 6);
*base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0);
#ifdef CONFIG_PHYS_ADDR_T_64BIT
*base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32;
#endif
if (size)
*size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17;
return 0;
}
EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info);
static int tegra_mc_block_dma_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->control) | BIT(rst->bit);
mc_writel(mc, value, rst->control);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
}
static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
unsigned long flags;
u32 value;
spin_lock_irqsave(&mc->lock, flags);
value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
mc_writel(mc, value, rst->control);
spin_unlock_irqrestore(&mc->lock, flags);
return 0;
}
static int tegra_mc_reset_status_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
}
const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
.block_dma = tegra_mc_block_dma_common,
.dma_idling = tegra_mc_dma_idling_common,
.unblock_dma = tegra_mc_unblock_dma_common,
.reset_status = tegra_mc_reset_status_common,
};
static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct tegra_mc, reset);
}
static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
unsigned long id)
{
unsigned int i;
for (i = 0; i < mc->soc->num_resets; i++)
if (mc->soc->resets[i].id == id)
return &mc->soc->resets[i];
return NULL;
}
static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct tegra_mc *mc = reset_to_mc(rcdev);
const struct tegra_mc_reset_ops *rst_ops;
const struct tegra_mc_reset *rst;
int retries = 500;
int err;
rst = tegra_mc_reset_find(mc, id);
if (!rst)
return -ENODEV;
rst_ops = mc->soc->reset_ops;
if (!rst_ops)
return -ENODEV;
/* DMA flushing will fail if reset is already asserted */
if (rst_ops->reset_status) {
/* check whether reset is asserted */
if (rst_ops->reset_status(mc, rst))
return 0;
}
if (rst_ops->block_dma) {
/* block clients DMA requests */
err = rst_ops->block_dma(mc, rst);
if (err) {
dev_err(mc->dev, "failed to block %s DMA: %d\n",
rst->name, err);
return err;
}
}
if (rst_ops->dma_idling) {
/* wait for completion of the outstanding DMA requests */
while (!rst_ops->dma_idling(mc, rst)) {
if (!retries--) {
dev_err(mc->dev, "failed to flush %s DMA\n",
rst->name);
return -EBUSY;
}
usleep_range(10, 100);
}
}
if (rst_ops->hotreset_assert) {
/* clear clients DMA requests sitting before arbitration */
err = rst_ops->hotreset_assert(mc, rst);
if (err) {
dev_err(mc->dev, "failed to hot reset %s: %d\n",
rst->name, err);
return err;
}
}
return 0;
}
static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct tegra_mc *mc = reset_to_mc(rcdev);
const struct tegra_mc_reset_ops *rst_ops;
const struct tegra_mc_reset *rst;
int err;
rst = tegra_mc_reset_find(mc, id);
if (!rst)
return -ENODEV;
rst_ops = mc->soc->reset_ops;
if (!rst_ops)
return -ENODEV;
if (rst_ops->hotreset_deassert) {
/* take out client from hot reset */
err = rst_ops->hotreset_deassert(mc, rst);
if (err) {
dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
rst->name, err);
return err;
}
}
if (rst_ops->unblock_dma) {
/* allow new DMA requests to proceed to arbitration */
err = rst_ops->unblock_dma(mc, rst);
if (err) {
dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
rst->name, err);
return err;
}
}
return 0;
}
static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct tegra_mc *mc = reset_to_mc(rcdev);
const struct tegra_mc_reset_ops *rst_ops;
const struct tegra_mc_reset *rst;
rst = tegra_mc_reset_find(mc, id);
if (!rst)
return -ENODEV;
rst_ops = mc->soc->reset_ops;
if (!rst_ops)
return -ENODEV;
return rst_ops->reset_status(mc, rst);
}
static const struct reset_control_ops tegra_mc_reset_ops = {
.assert = tegra_mc_hotreset_assert,
.deassert = tegra_mc_hotreset_deassert,
.status = tegra_mc_hotreset_status,
};
static int tegra_mc_reset_setup(struct tegra_mc *mc)
{
int err;
mc->reset.ops = &tegra_mc_reset_ops;
mc->reset.owner = THIS_MODULE;
mc->reset.of_node = mc->dev->of_node;
mc->reset.of_reset_n_cells = 1;
mc->reset.nr_resets = mc->soc->num_resets;
err = reset_controller_register(&mc->reset);
if (err < 0)
return err;
return 0;
}
int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
{
unsigned int i;
struct tegra_mc_timing *timing = NULL;
for (i = 0; i < mc->num_timings; i++) {
if (mc->timings[i].rate == rate) {
timing = &mc->timings[i];
break;
}
}
if (!timing) {
dev_err(mc->dev, "no memory timing registered for rate %lu\n",
rate);
return -EINVAL;
}
for (i = 0; i < mc->soc->num_emem_regs; ++i)
mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
return 0;
}
EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration);
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
{
u8 dram_count;
dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
dram_count++;
return dram_count;
}
EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count);
#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
defined(CONFIG_ARCH_TEGRA_114_SOC) || \
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
defined(CONFIG_ARCH_TEGRA_132_SOC) || \
defined(CONFIG_ARCH_TEGRA_210_SOC)
static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
{
unsigned long long tick;
unsigned int i;
u32 value;
/* compute the number of MC clock cycles per tick */
tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
do_div(tick, NSEC_PER_SEC);
value = mc_readl(mc, MC_EMEM_ARB_CFG);
value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
mc_writel(mc, value, MC_EMEM_ARB_CFG);
/* write latency allowance defaults */
for (i = 0; i < mc->soc->num_clients; i++) {
const struct tegra_mc_client *client = &mc->soc->clients[i];
u32 value;
value = mc_readl(mc, client->regs.la.reg);
value &= ~(client->regs.la.mask << client->regs.la.shift);
value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;
mc_writel(mc, value, client->regs.la.reg);
}
/* latch new values */
mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
return 0;
}
static int load_one_timing(struct tegra_mc *mc,
struct tegra_mc_timing *timing,
struct device_node *node)
{
int err;
u32 tmp;
err = of_property_read_u32(node, "clock-frequency", &tmp);
if (err) {
dev_err(mc->dev,
"timing %pOFn: failed to read rate\n", node);
return err;
}
timing->rate = tmp;
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
sizeof(u32), GFP_KERNEL);
if (!timing->emem_data)
return -ENOMEM;
err = of_property_read_u32_array(node, "nvidia,emem-configuration",
timing->emem_data,
mc->soc->num_emem_regs);
if (err) {
dev_err(mc->dev,
"timing %pOFn: failed to read EMEM configuration\n",
node);
return err;
}
return 0;
}
static int load_timings(struct tegra_mc *mc, struct device_node *node)
{
struct device_node *child;
struct tegra_mc_timing *timing;
int child_count = of_get_child_count(node);
int i = 0, err;
mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
GFP_KERNEL);
if (!mc->timings)
return -ENOMEM;
mc->num_timings = child_count;
for_each_child_of_node(node, child) {
timing = &mc->timings[i++];
err = load_one_timing(mc, timing, child);
if (err) {
of_node_put(child);
return err;
}
}
return 0;
}
static int tegra_mc_setup_timings(struct tegra_mc *mc)
{
struct device_node *node;
u32 ram_code, node_ram_code;
int err;
ram_code = tegra_read_ram_code();
mc->num_timings = 0;
for_each_child_of_node(mc->dev->of_node, node) {
err = of_property_read_u32(node, "nvidia,ram-code",
&node_ram_code);
if (err || (node_ram_code != ram_code))
continue;
err = load_timings(mc, node);
of_node_put(node);
if (err)
return err;
break;
}
if (mc->num_timings == 0)
dev_warn(mc->dev,
"no memory timings for RAM code %u registered\n",
ram_code);
return 0;
}
int tegra30_mc_probe(struct tegra_mc *mc)
{
int err;
mc->clk = devm_clk_get_optional(mc->dev, "mc");
if (IS_ERR(mc->clk)) {
dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk));
return PTR_ERR(mc->clk);
}
/* ensure that debug features are disabled */
mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
err = tegra_mc_setup_latency_allowance(mc);
if (err < 0) {
dev_err(mc->dev, "failed to setup latency allowance: %d\n", err);
return err;
}
err = tegra_mc_setup_timings(mc);
if (err < 0) {
dev_err(mc->dev, "failed to setup timings: %d\n", err);
return err;
}
return 0;
}
const struct tegra_mc_ops tegra30_mc_ops = {
.probe = tegra30_mc_probe,
.handle_irq = tegra30_mc_handle_irq,
};
#endif
static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status,
unsigned int *mc_channel)
{
if ((status & mc->soc->ch_intmask) == 0)
return -EINVAL;
*mc_channel = __ffs((status & mc->soc->ch_intmask) >>
mc->soc->global_intstatus_channel_shift);
return 0;
}
static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc,
unsigned int channel)
{
return BIT(channel) << mc->soc->global_intstatus_channel_shift;
}
irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
{
struct tegra_mc *mc = data;
unsigned int bit, channel;
unsigned long status;
if (mc->soc->num_channels) {
u32 global_status;
int err;
global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);
err = mc_global_intstatus_to_channel(mc, global_status, &channel);
if (err < 0) {
dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n",
global_status);
return IRQ_NONE;
}
/* mask all interrupts to avoid flooding */
status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask;
} else {
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
}
if (!status)
return IRQ_NONE;
for_each_set_bit(bit, &status, 32) {
const char *error = tegra_mc_status_names[bit] ?: "unknown";
const char *client = "unknown", *desc;
const char *direction, *secure;
u32 status_reg, addr_reg;
u32 intmask = BIT(bit);
phys_addr_t addr = 0;
#ifdef CONFIG_PHYS_ADDR_T_64BIT
u32 addr_hi_reg = 0;
#endif
unsigned int i;
char perm[7];
u8 id, type;
u32 value;
switch (intmask) {
case MC_INT_DECERR_VPR:
status_reg = MC_ERR_VPR_STATUS;
addr_reg = MC_ERR_VPR_ADR;
break;
case MC_INT_SECERR_SEC:
status_reg = MC_ERR_SEC_STATUS;
addr_reg = MC_ERR_SEC_ADR;
break;
case MC_INT_DECERR_MTS:
status_reg = MC_ERR_MTS_STATUS;
addr_reg = MC_ERR_MTS_ADR;
break;
case MC_INT_DECERR_GENERALIZED_CARVEOUT:
status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
break;
case MC_INT_DECERR_ROUTE_SANITY:
status_reg = MC_ERR_ROUTE_SANITY_STATUS;
addr_reg = MC_ERR_ROUTE_SANITY_ADR;
break;
default:
status_reg = MC_ERR_STATUS;
addr_reg = MC_ERR_ADR;
#ifdef CONFIG_PHYS_ADDR_T_64BIT
if (mc->soc->has_addr_hi_reg)
addr_hi_reg = MC_ERR_ADR_HI;
#endif
break;
}
if (mc->soc->num_channels)
value = mc_ch_readl(mc, channel, status_reg);
else
value = mc_readl(mc, status_reg);
#ifdef CONFIG_PHYS_ADDR_T_64BIT
if (mc->soc->num_address_bits > 32) {
if (addr_hi_reg) {
if (mc->soc->num_channels)
addr = mc_ch_readl(mc, channel, addr_hi_reg);
else
addr = mc_readl(mc, addr_hi_reg);
} else {
addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
MC_ERR_STATUS_ADR_HI_MASK);
}
addr <<= 32;
}
#endif
if (value & MC_ERR_STATUS_RW)
direction = "write";
else
direction = "read";
if (value & MC_ERR_STATUS_SECURITY)
secure = "secure ";
else
secure = "";
id = value & mc->soc->client_id_mask;
for (i = 0; i < mc->soc->num_clients; i++) {
if (mc->soc->clients[i].id == id) {
client = mc->soc->clients[i].name;
break;
}
}
type = (value & MC_ERR_STATUS_TYPE_MASK) >>
MC_ERR_STATUS_TYPE_SHIFT;
desc = tegra_mc_error_names[type];
switch (value & MC_ERR_STATUS_TYPE_MASK) {
case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
perm[0] = ' ';
perm[1] = '[';
if (value & MC_ERR_STATUS_READABLE)
perm[2] = 'R';
else
perm[2] = '-';
if (value & MC_ERR_STATUS_WRITABLE)
perm[3] = 'W';
else
perm[3] = '-';
if (value & MC_ERR_STATUS_NONSECURE)
perm[4] = '-';
else
perm[4] = 'S';
perm[5] = ']';
perm[6] = '\0';
break;
default:
perm[0] = '\0';
break;
}
if (mc->soc->num_channels)
value = mc_ch_readl(mc, channel, addr_reg);
else
value = mc_readl(mc, addr_reg);
addr |= value;
dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
client, secure, direction, &addr, error,
desc, perm);
}
/* clear interrupts */
if (mc->soc->num_channels) {
mc_ch_writel(mc, channel, status, MC_INTSTATUS);
mc_ch_writel(mc, MC_BROADCAST_CHANNEL,
mc_channel_to_global_intstatus(mc, channel),
MC_GLOBAL_INTSTATUS);
} else {
mc_writel(mc, status, MC_INTSTATUS);
}
return IRQ_HANDLED;
}
const char *const tegra_mc_status_names[32] = {
[ 1] = "External interrupt",
[ 6] = "EMEM address decode error",
[ 7] = "GART page fault",
[ 8] = "Security violation",
[ 9] = "EMEM arbitration error",
[10] = "Page fault",
[11] = "Invalid APB ASID update",
[12] = "VPR violation",
[13] = "Secure carveout violation",
[16] = "MTS carveout violation",
[17] = "Generalized carveout violation",
[20] = "Route Sanity error",
};
const char *const tegra_mc_error_names[8] = {
[2] = "EMEM decode error",
[3] = "TrustZone violation",
[4] = "Carveout violation",
[6] = "SMMU translation error",
};
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data)
{
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
struct icc_node *node;
list_for_each_entry(node, &mc->provider.nodes, node_list) {
if (node->id == spec->args[0])
return node;
}
/*
* If a client driver calls devm_of_icc_get() before the MC driver
* is probed, then return EPROBE_DEFER to the client driver.
*/
return ERR_PTR(-EPROBE_DEFER);
}
static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak)
{
*average = 0;
*peak = 0;
return 0;
}
static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst)
{
return 0;
}
const struct tegra_mc_icc_ops tegra_mc_icc_ops = {
.xlate = tegra_mc_icc_xlate,
.aggregate = icc_std_aggregate,
.get_bw = tegra_mc_icc_get,
.set = tegra_mc_icc_set,
};
/*
* Memory Controller (MC) has few Memory Clients that are issuing memory
* bandwidth allocation requests to the MC interconnect provider. The MC
* provider aggregates the requests and then sends the aggregated request
* up to the External Memory Controller (EMC) interconnect provider which
* re-configures hardware interface to External Memory (EMEM) in accordance
* to the required bandwidth. Each MC interconnect node represents an
* individual Memory Client.
*
* Memory interconnect topology:
*
* +----+
* +--------+ | |
* | TEXSRD +--->+ |
* +--------+ | |
* | | +-----+ +------+
* ... | MC +--->+ EMC +--->+ EMEM |
* | | +-----+ +------+
* +--------+ | |
* | DISP.. +--->+ |
* +--------+ | |
* +----+
*/
static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
{
struct icc_node *node;
unsigned int i;
int err;
/* older device-trees don't have interconnect properties */
if (!device_property_present(mc->dev, "#interconnect-cells") ||
!mc->soc->icc_ops)
return 0;
mc->provider.dev = mc->dev;
mc->provider.data = &mc->provider;
mc->provider.set = mc->soc->icc_ops->set;
mc->provider.aggregate = mc->soc->icc_ops->aggregate;
mc->provider.get_bw = mc->soc->icc_ops->get_bw;
mc->provider.xlate = mc->soc->icc_ops->xlate;
mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended;
icc_provider_init(&mc->provider);
/* create Memory Controller node */
node = icc_node_create(TEGRA_ICC_MC);
if (IS_ERR(node))
return PTR_ERR(node);
node->name = "Memory Controller";
icc_node_add(node, &mc->provider);
/* link Memory Controller to External Memory Controller */
err = icc_link_create(node, TEGRA_ICC_EMC);
if (err)
goto remove_nodes;
for (i = 0; i < mc->soc->num_clients; i++) {
/* create MC client node */
node = icc_node_create(mc->soc->clients[i].id);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto remove_nodes;
}
node->name = mc->soc->clients[i].name;
icc_node_add(node, &mc->provider);
/* link Memory Client to Memory Controller */
err = icc_link_create(node, TEGRA_ICC_MC);
if (err)
goto remove_nodes;
node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]);
}
err = icc_provider_register(&mc->provider);
if (err)
goto remove_nodes;
return 0;
remove_nodes:
icc_nodes_remove(&mc->provider);
return err;
}
static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
{
unsigned int i;
u32 value;
value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE);
if (value <= 0) {
mc->num_channels = mc->soc->num_channels;
return;
}
for (i = 0; i < 32; i++) {
if (value & BIT(i))
mc->num_channels++;
}
}
static int tegra_mc_probe(struct platform_device *pdev)
{
struct tegra_mc *mc;
u64 mask;
int err;
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
if (!mc)
return -ENOMEM;
platform_set_drvdata(pdev, mc);
spin_lock_init(&mc->lock);
mc->soc = of_device_get_match_data(&pdev->dev);
mc->dev = &pdev->dev;
mask = DMA_BIT_MASK(mc->soc->num_address_bits);
err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
if (err < 0) {
dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
return err;
}
/* length of MC tick in nanoseconds */
mc->tick = 30;
mc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mc->regs))
return PTR_ERR(mc->regs);
mc->debugfs.root = debugfs_create_dir("mc", NULL);
if (mc->soc->ops && mc->soc->ops->probe) {
err = mc->soc->ops->probe(mc);
if (err < 0)
return err;
}
tegra_mc_num_channel_enabled(mc);
if (mc->soc->ops && mc->soc->ops->handle_irq) {
mc->irq = platform_get_irq(pdev, 0);
if (mc->irq < 0)
return mc->irq;
WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
if (mc->soc->num_channels)
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
MC_INTMASK);
else
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0,
dev_name(&pdev->dev), mc);
if (err < 0) {
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
err);
return err;
}
}
if (mc->soc->reset_ops) {
err = tegra_mc_reset_setup(mc);
if (err < 0)
dev_err(&pdev->dev, "failed to register reset controller: %d\n", err);
}
err = tegra_mc_interconnect_setup(mc);
if (err < 0)
dev_err(&pdev->dev, "failed to initialize interconnect: %d\n",
err);
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
if (IS_ERR(mc->smmu)) {
dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
PTR_ERR(mc->smmu));
mc->smmu = NULL;
}
}
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
mc->gart = tegra_gart_probe(&pdev->dev, mc);
if (IS_ERR(mc->gart)) {
dev_err(&pdev->dev, "failed to probe GART: %ld\n",
PTR_ERR(mc->gart));
mc->gart = NULL;
}
}
return 0;
}
static int __maybe_unused tegra_mc_suspend(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
if (mc->soc->ops && mc->soc->ops->suspend)
return mc->soc->ops->suspend(mc);
return 0;
}
static int __maybe_unused tegra_mc_resume(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
if (mc->soc->ops && mc->soc->ops->resume)
return mc->soc->ops->resume(mc);
return 0;
}
static void tegra_mc_sync_state(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
/* check whether ICC provider is registered */
if (mc->provider.dev == dev)
icc_sync_state(dev);
}
static const struct dev_pm_ops tegra_mc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume)
};
static struct platform_driver tegra_mc_driver = {
.driver = {
.name = "tegra-mc",
.of_match_table = tegra_mc_of_match,
.pm = &tegra_mc_pm_ops,
.suppress_bind_attrs = true,
.sync_state = tegra_mc_sync_state,
},
.prevent_deferred_probe = true,
.probe = tegra_mc_probe,
};
static int tegra_mc_init(void)
{
return platform_driver_register(&tegra_mc_driver);
}
arch_initcall(tegra_mc_init);
MODULE_AUTHOR("Thierry Reding <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
|
linux-master
|
drivers/memory/tegra/mc.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <soc/tegra/mc.h>
#include "tegra210-emc.h"
#include "tegra210-mc.h"
/*
* Enable flags for specifying verbosity.
*/
#define INFO (1 << 0)
#define STEPS (1 << 1)
#define SUB_STEPS (1 << 2)
#define PRELOCK (1 << 3)
#define PRELOCK_STEPS (1 << 4)
#define ACTIVE_EN (1 << 5)
#define PRAMP_UP (1 << 6)
#define PRAMP_DN (1 << 7)
#define EMA_WRITES (1 << 10)
#define EMA_UPDATES (1 << 11)
#define PER_TRAIN (1 << 16)
#define CC_PRINT (1 << 17)
#define CCFIFO (1 << 29)
#define REGS (1 << 30)
#define REG_LISTS (1 << 31)
#define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
#define DVFS_CLOCK_CHANGE_VERSION 21021
#define EMC_PRELOCK_VERSION 2101
enum {
DVFS_SEQUENCE = 1,
WRITE_TRAINING_SEQUENCE = 2,
PERIODIC_TRAINING_SEQUENCE = 3,
DVFS_PT1 = 10,
DVFS_UPDATE = 11,
TRAINING_PT1 = 12,
TRAINING_UPDATE = 13,
PERIODIC_TRAINING_UPDATE = 14
};
/*
* PTFV defines - basically just indexes into the per table PTFV array.
*/
#define PTFV_DQSOSC_MOVAVG_C0D0U0_INDEX 0
#define PTFV_DQSOSC_MOVAVG_C0D0U1_INDEX 1
#define PTFV_DQSOSC_MOVAVG_C0D1U0_INDEX 2
#define PTFV_DQSOSC_MOVAVG_C0D1U1_INDEX 3
#define PTFV_DQSOSC_MOVAVG_C1D0U0_INDEX 4
#define PTFV_DQSOSC_MOVAVG_C1D0U1_INDEX 5
#define PTFV_DQSOSC_MOVAVG_C1D1U0_INDEX 6
#define PTFV_DQSOSC_MOVAVG_C1D1U1_INDEX 7
#define PTFV_DVFS_SAMPLES_INDEX 9
#define PTFV_MOVAVG_WEIGHT_INDEX 10
#define PTFV_CONFIG_CTRL_INDEX 11
#define PTFV_CONFIG_CTRL_USE_PREVIOUS_EMA (1 << 0)
/*
* Do arithmetic in fixed point.
*/
#define MOVAVG_PRECISION_FACTOR 100
/*
* The division portion of the average operation.
*/
#define __AVERAGE_PTFV(dev) \
({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
/*
* Convert val to fixed point and add it to the temporary average.
*/
#define __INCREMENT_PTFV(dev, val) \
({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
((val) * MOVAVG_PRECISION_FACTOR); })
/*
* Convert a moving average back to integral form and return the value.
*/
#define __MOVAVG_AC(timing, dev) \
((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
MOVAVG_PRECISION_FACTOR)
/* Weighted update. */
#define __WEIGHTED_UPDATE_PTFV(dev, nval) \
do { \
int w = PTFV_MOVAVG_WEIGHT_INDEX; \
int dqs = PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX; \
\
next->ptfv_list[dqs] = \
((nval * MOVAVG_PRECISION_FACTOR) + \
(next->ptfv_list[dqs] * \
next->ptfv_list[w])) / \
(next->ptfv_list[w] + 1); \
\
emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
__stringify(dev), nval, next->ptfv_list[dqs]); \
} while (0)
/* Access a particular average. */
#define __MOVAVG(timing, dev) \
((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX])
static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type)
{
bool periodic_training_update = type == PERIODIC_TRAINING_UPDATE;
struct tegra210_emc_timing *last = emc->last;
struct tegra210_emc_timing *next = emc->next;
u32 last_timing_rate_mhz = last->rate / 1000;
u32 next_timing_rate_mhz = next->rate / 1000;
bool dvfs_update = type == DVFS_UPDATE;
s32 tdel = 0, tmdel = 0, adel = 0;
bool dvfs_pt1 = type == DVFS_PT1;
unsigned long cval = 0;
u32 temp[2][2], value;
unsigned int i;
/*
* Dev0 MSB.
*/
if (dvfs_pt1 || periodic_training_update) {
value = tegra210_emc_mrr_read(emc, 2, 19);
for (i = 0; i < emc->num_channels; i++) {
temp[i][0] = (value & 0x00ff) << 8;
temp[i][1] = (value & 0xff00) << 0;
value >>= 16;
}
/*
* Dev0 LSB.
*/
value = tegra210_emc_mrr_read(emc, 2, 18);
for (i = 0; i < emc->num_channels; i++) {
temp[i][0] |= (value & 0x00ff) >> 0;
temp[i][1] |= (value & 0xff00) >> 8;
value >>= 16;
}
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[0][0];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C0D0U0, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C0D0U0);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C0D0U0, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C0D0U0] -
__MOVAVG_AC(next, C0D0U0);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C0D0U0] =
__MOVAVG_AC(next, C0D0U0);
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[0][1];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C0D0U1, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C0D0U1);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C0D0U1, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C0D0U1] -
__MOVAVG_AC(next, C0D0U1);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C0D0U1] =
__MOVAVG_AC(next, C0D0U1);
}
if (emc->num_channels > 1) {
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[1][0];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C1D0U0, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C1D0U0);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C1D0U0, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C1D0U0] -
__MOVAVG_AC(next, C1D0U0);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C1D0U0] =
__MOVAVG_AC(next, C1D0U0);
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[1][1];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C1D0U1, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C1D0U1);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C1D0U1, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C1D0U1] -
__MOVAVG_AC(next, C1D0U1);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C1D0U1] =
__MOVAVG_AC(next, C1D0U1);
}
}
if (emc->num_devices < 2)
goto done;
/*
* Dev1 MSB.
*/
if (dvfs_pt1 || periodic_training_update) {
value = tegra210_emc_mrr_read(emc, 1, 19);
for (i = 0; i < emc->num_channels; i++) {
temp[i][0] = (value & 0x00ff) << 8;
temp[i][1] = (value & 0xff00) << 0;
value >>= 16;
}
/*
* Dev1 LSB.
*/
value = tegra210_emc_mrr_read(emc, 1, 18);
for (i = 0; i < emc->num_channels; i++) {
temp[i][0] |= (value & 0x00ff) >> 0;
temp[i][1] |= (value & 0xff00) >> 8;
value >>= 16;
}
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[0][0];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C0D1U0, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C0D1U0);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C0D1U0, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C0D1U0] -
__MOVAVG_AC(next, C0D1U0);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C0D1U0] =
__MOVAVG_AC(next, C0D1U0);
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[0][1];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C0D1U1, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C0D1U1);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C0D1U1, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C0D1U1] -
__MOVAVG_AC(next, C0D1U1);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C0D1U1] =
__MOVAVG_AC(next, C0D1U1);
}
if (emc->num_channels > 1) {
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[1][0];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C1D1U0, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C1D1U0);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C1D1U0, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C1D1U0] -
__MOVAVG_AC(next, C1D1U0);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C1D1U0] =
__MOVAVG_AC(next, C1D1U0);
}
if (dvfs_pt1 || periodic_training_update) {
cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[1][1];
}
if (dvfs_pt1)
__INCREMENT_PTFV(C1D1U1, cval);
else if (dvfs_update)
__AVERAGE_PTFV(C1D1U1);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(C1D1U1, cval);
if (dvfs_update || periodic_training_update) {
tdel = next->current_dram_clktree[C1D1U1] -
__MOVAVG_AC(next, C1D1U1);
tmdel = (tdel < 0) ? -1 * tdel : tdel;
if (tmdel > adel)
adel = tmdel;
if (tmdel * 128 * next_timing_rate_mhz / 1000000 >
next->tree_margin)
next->current_dram_clktree[C1D1U1] =
__MOVAVG_AC(next, C1D1U1);
}
}
done:
return adel;
}
static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 type,
struct tegra210_emc_timing *last,
struct tegra210_emc_timing *next)
{
#define __COPY_EMA(nt, lt, dev) \
({ __MOVAVG(nt, dev) = __MOVAVG(lt, dev) * \
(nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
u32 i, adel = 0, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX];
u32 delay;
delay = tegra210_emc_actual_osc_clocks(last->run_clocks);
delay *= 1000;
delay = 2 + (delay / last->rate);
if (!next->periodic_training)
return 0;
if (type == DVFS_SEQUENCE) {
if (last->periodic_training &&
(next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] &
PTFV_CONFIG_CTRL_USE_PREVIOUS_EMA)) {
/*
* If the previous frequency was using periodic
* calibration then we can reuse the previous
* frequencies EMA data.
*/
__COPY_EMA(next, last, C0D0U0);
__COPY_EMA(next, last, C0D0U1);
__COPY_EMA(next, last, C1D0U0);
__COPY_EMA(next, last, C1D0U1);
__COPY_EMA(next, last, C0D1U0);
__COPY_EMA(next, last, C0D1U1);
__COPY_EMA(next, last, C1D1U0);
__COPY_EMA(next, last, C1D1U1);
} else {
/* Reset the EMA.*/
__MOVAVG(next, C0D0U0) = 0;
__MOVAVG(next, C0D0U1) = 0;
__MOVAVG(next, C1D0U0) = 0;
__MOVAVG(next, C1D0U1) = 0;
__MOVAVG(next, C0D1U0) = 0;
__MOVAVG(next, C0D1U1) = 0;
__MOVAVG(next, C1D1U0) = 0;
__MOVAVG(next, C1D1U1) = 0;
for (i = 0; i < samples; i++) {
tegra210_emc_start_periodic_compensation(emc);
udelay(delay);
/*
* Generate next sample of data.
*/
adel = update_clock_tree_delay(emc, DVFS_PT1);
}
}
/*
* Seems like it should be part of the
* 'if (last_timing->periodic_training)' conditional
* since is already done for the else clause.
*/
adel = update_clock_tree_delay(emc, DVFS_UPDATE);
}
if (type == PERIODIC_TRAINING_SEQUENCE) {
tegra210_emc_start_periodic_compensation(emc);
udelay(delay);
adel = update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE);
}
return adel;
}
static u32 tegra210_emc_r21021_periodic_compensation(struct tegra210_emc *emc)
{
u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value;
static const u32 list[] = {
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3,
EMC_DATA_BRLSHFT_0,
EMC_DATA_BRLSHFT_1
};
struct tegra210_emc_timing *last = emc->last;
unsigned int items = ARRAY_SIZE(list), i;
unsigned long delay;
if (last->periodic_training) {
emc_dbg(emc, PER_TRAIN, "Periodic training starting\n");
value = emc_readl(emc, EMC_DBG);
emc_cfg_o = emc_readl(emc, EMC_CFG);
emc_cfg = emc_cfg_o & ~(EMC_CFG_DYN_SELF_REF |
EMC_CFG_DRAM_ACPD |
EMC_CFG_DRAM_CLKSTOP_PD);
/*
* 1. Power optimizations should be off.
*/
emc_writel(emc, emc_cfg, EMC_CFG);
/* Does emc_timing_update() for above changes. */
tegra210_emc_dll_disable(emc);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK,
0);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK,
0);
emc_cfg_update = value = emc_readl(emc, EMC_CFG_UPDATE);
value &= ~EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK;
value |= (2 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT);
emc_writel(emc, value, EMC_CFG_UPDATE);
/*
* 2. osc kick off - this assumes training and dvfs have set
* correct MR23.
*/
tegra210_emc_start_periodic_compensation(emc);
/*
* 3. Let dram capture its clock tree delays.
*/
delay = tegra210_emc_actual_osc_clocks(last->run_clocks);
delay *= 1000;
delay /= last->rate + 1;
udelay(delay);
/*
* 4. Check delta wrt previous values (save value if margin
* exceeds what is set in table).
*/
del = periodic_compensation_handler(emc,
PERIODIC_TRAINING_SEQUENCE,
last, last);
/*
* 5. Apply compensation w.r.t. trained values (if clock tree
* has drifted more than the set margin).
*/
if (last->tree_margin < ((del * 128 * (last->rate / 1000)) / 1000000)) {
for (i = 0; i < items; i++) {
value = tegra210_emc_compensate(last, list[i]);
emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n",
list[i], value);
emc_writel(emc, value, list[i]);
}
}
emc_writel(emc, emc_cfg_o, EMC_CFG);
/*
* 6. Timing update actally applies the new trimmers.
*/
tegra210_emc_timing_update(emc);
/* 6.1. Restore the UPDATE_DLL_IN_UPDATE field. */
emc_writel(emc, emc_cfg_update, EMC_CFG_UPDATE);
/* 6.2. Restore the DLL. */
tegra210_emc_dll_enable(emc);
}
return 0;
}
/*
* Do the clock change sequence.
*/
static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc)
{
/* state variables */
static bool fsp_for_next_freq;
/* constant configuration parameters */
const bool save_restore_clkstop_pd = true;
const u32 zqcal_before_cc_cutoff = 2400;
const bool cya_allow_ref_cc = false;
const bool cya_issue_pc_ref = false;
const bool opt_cc_short_zcal = true;
const bool ref_b4_sref_en = false;
const u32 tZQCAL_lpddr4 = 1000000;
const bool opt_short_zcal = true;
const bool opt_do_sw_qrst = true;
const u32 opt_dvfs_mode = MAN_SR;
/*
* This is the timing table for the source frequency. It does _not_
* necessarily correspond to the actual timing values in the EMC at the
* moment. If the boot BCT differs from the table then this can happen.
* However, we need it for accessing the dram_timings (which are not
* really registers) array for the current frequency.
*/
struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next;
u32 tRTM, RP_war, R2P_war, TRPab_war, deltaTWATM, W2P_war, tRPST;
u32 mr13_flip_fspwr, mr13_flip_fspop, ramp_up_wait, ramp_down_wait;
u32 zq_wait_long, zq_latch_dvfs_wait_time, tZQCAL_lpddr4_fc_adj;
u32 emc_auto_cal_config, auto_cal_en, emc_cfg, emc_sel_dpd_ctrl;
u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4];
u32 bg_reg_mode_change, enable_bglp_reg, enable_bg_reg;
bool opt_zcal_en_cc = false, is_lpddr3 = false;
bool compensate_trimmer_applicable = false;
u32 emc_dbg, emc_cfg_pipe_clk, emc_pin;
u32 src_clk_period, dst_clk_period; /* in picoseconds */
bool shared_zq_resistor = false;
u32 value, dram_type;
u32 opt_dll_mode = 0;
unsigned long delay;
unsigned int i;
emc_dbg(emc, INFO, "Running clock change.\n");
/* XXX fake == last */
fake = tegra210_emc_find_timing(emc, last->rate * 1000UL);
fsp_for_next_freq = !fsp_for_next_freq;
value = emc_readl(emc, EMC_FBIO_CFG5) & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
dram_type = value >> EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
if (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31))
shared_zq_resistor = true;
if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 &&
last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) ||
dram_type == DRAM_TYPE_LPDDR4)
opt_zcal_en_cc = true;
if (dram_type == DRAM_TYPE_DDR3)
opt_dll_mode = tegra210_emc_get_dll_state(next);
if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) &&
(dram_type == DRAM_TYPE_LPDDR2))
is_lpddr3 = true;
emc_readl(emc, EMC_CFG);
emc_readl(emc, EMC_AUTO_CAL_CONFIG);
src_clk_period = 1000000000 / last->rate;
dst_clk_period = 1000000000 / next->rate;
if (dst_clk_period <= zqcal_before_cc_cutoff)
tZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4 - tFC_lpddr4;
else
tZQCAL_lpddr4_fc_adj = tZQCAL_lpddr4;
tZQCAL_lpddr4_fc_adj /= dst_clk_period;
emc_dbg = emc_readl(emc, EMC_DBG);
emc_pin = emc_readl(emc, EMC_PIN);
emc_cfg_pipe_clk = emc_readl(emc, EMC_CFG_PIPE_CLK);
emc_cfg = next->burst_regs[EMC_CFG_INDEX];
emc_cfg &= ~(EMC_CFG_DYN_SELF_REF | EMC_CFG_DRAM_ACPD |
EMC_CFG_DRAM_CLKSTOP_SR | EMC_CFG_DRAM_CLKSTOP_PD);
emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl;
emc_sel_dpd_ctrl &= ~(EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN |
EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN |
EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN |
EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN |
EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN);
emc_dbg(emc, INFO, "Clock change version: %d\n",
DVFS_CLOCK_CHANGE_VERSION);
emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type);
emc_dbg(emc, INFO, "DRAM dev #: %u\n", emc->num_devices);
emc_dbg(emc, INFO, "Next EMC clksrc: 0x%08x\n", clksrc);
emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src);
emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate,
next->rate);
emc_dbg(emc, INFO, "last period: %u, next period: %u\n",
src_clk_period, dst_clk_period);
emc_dbg(emc, INFO, " shared_zq_resistor: %d\n", !!shared_zq_resistor);
emc_dbg(emc, INFO, " num_channels: %u\n", emc->num_channels);
emc_dbg(emc, INFO, " opt_dll_mode: %d\n", opt_dll_mode);
/*
* Step 1:
* Pre DVFS SW sequence.
*/
emc_dbg(emc, STEPS, "Step 1\n");
emc_dbg(emc, STEPS, "Step 1.1: Disable DLL temporarily.\n");
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;
emc_writel(emc, value, EMC_CFG_DIG_DLL);
tegra210_emc_timing_update(emc);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_CFG_DLL_EN, 0);
emc_dbg(emc, STEPS, "Step 1.2: Disable AUTOCAL temporarily.\n");
emc_auto_cal_config = next->emc_auto_cal_config;
auto_cal_en = emc_auto_cal_config & EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
emc_auto_cal_config &= ~EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
emc_auto_cal_config |= EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL;
emc_auto_cal_config |= EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL;
emc_auto_cal_config |= auto_cal_en;
emc_writel(emc, emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);
emc_readl(emc, EMC_AUTO_CAL_CONFIG); /* Flush write. */
emc_dbg(emc, STEPS, "Step 1.3: Disable other power features.\n");
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc, emc_cfg, EMC_CFG);
emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
if (next->periodic_training) {
tegra210_emc_reset_dram_clktree_values(next);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK,
0);
for (i = 0; i < emc->num_channels; i++)
tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK,
0);
tegra210_emc_start_periodic_compensation(emc);
delay = 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks);
udelay((delay / last->rate) + 2);
value = periodic_compensation_handler(emc, DVFS_SEQUENCE, fake,
next);
value = (value * 128 * next->rate / 1000) / 1000000;
if (next->periodic_training && value > next->tree_margin)
compensate_trimmer_applicable = true;
}
emc_writel(emc, EMC_INTSTATUS_CLKCHANGE_COMPLETE, EMC_INTSTATUS);
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc, emc_cfg, EMC_CFG);
emc_writel(emc, emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);
emc_writel(emc, emc_cfg_pipe_clk | EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON,
EMC_CFG_PIPE_CLK);
emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp &
~EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE,
EMC_FDPD_CTRL_CMD_NO_RAMP);
bg_reg_mode_change =
((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) ^
(last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD)) ||
((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) ^
(last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD));
enable_bglp_reg =
(next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD) == 0;
enable_bg_reg =
(next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD) == 0;
if (bg_reg_mode_change) {
if (enable_bg_reg)
emc_writel(emc, last->burst_regs
[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,
EMC_PMACRO_BG_BIAS_CTRL_0);
if (enable_bglp_reg)
emc_writel(emc, last->burst_regs
[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,
EMC_PMACRO_BG_BIAS_CTRL_0);
}
/* Check if we need to turn on VREF generator. */
if ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF) == 0) &&
((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF) == 1)) ||
(((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) == 0) &&
((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) != 0))) {
u32 pad_tx_ctrl =
next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
u32 last_pad_tx_ctrl =
last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
u32 next_dq_e_ivref, next_dqs_e_ivref;
next_dqs_e_ivref = pad_tx_ctrl &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF;
next_dq_e_ivref = pad_tx_ctrl &
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF;
value = (last_pad_tx_ctrl &
~EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF &
~EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF) |
next_dq_e_ivref | next_dqs_e_ivref;
emc_writel(emc, value, EMC_PMACRO_DATA_PAD_TX_CTRL);
udelay(1);
} else if (bg_reg_mode_change) {
udelay(1);
}
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
/*
* Step 2:
* Prelock the DLL.
*/
emc_dbg(emc, STEPS, "Step 2\n");
if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] &
EMC_CFG_DIG_DLL_CFG_DLL_EN) {
emc_dbg(emc, INFO, "Prelock enabled for target frequency.\n");
value = tegra210_emc_dll_prelock(emc, clksrc);
emc_dbg(emc, INFO, "DLL out: 0x%03x\n", value);
} else {
emc_dbg(emc, INFO, "Disabling DLL for target frequency.\n");
tegra210_emc_dll_disable(emc);
}
/*
* Step 3:
* Prepare autocal for the clock change.
*/
emc_dbg(emc, STEPS, "Step 3\n");
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2);
emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3);
emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4);
emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5);
emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6);
emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7);
emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
emc_auto_cal_config |= (EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START |
auto_cal_en);
emc_writel(emc, emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);
/*
* Step 4:
* Update EMC_CFG. (??)
*/
emc_dbg(emc, STEPS, "Step 4\n");
if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4)
ccfifo_writel(emc, 1, EMC_SELF_REF, 0);
else
emc_writel(emc, next->emc_cfg_2, EMC_CFG_2);
/*
* Step 5:
* Prepare reference variables for ZQCAL regs.
*/
emc_dbg(emc, STEPS, "Step 5\n");
if (dram_type == DRAM_TYPE_LPDDR4)
zq_wait_long = max((u32)1, div_o3(1000000, dst_clk_period));
else if (dram_type == DRAM_TYPE_LPDDR2 || is_lpddr3)
zq_wait_long = max(next->min_mrs_wait,
div_o3(360000, dst_clk_period)) + 4;
else if (dram_type == DRAM_TYPE_DDR3)
zq_wait_long = max((u32)256,
div_o3(320000, dst_clk_period) + 2);
else
zq_wait_long = 0;
/*
* Step 6:
* Training code - removed.
*/
emc_dbg(emc, STEPS, "Step 6\n");
/*
* Step 7:
* Program FSP reference registers and send MRWs to new FSPWR.
*/
emc_dbg(emc, STEPS, "Step 7\n");
emc_dbg(emc, SUB_STEPS, "Step 7.1: Bug 200024907 - Patch RP R2P");
/* WAR 200024907 */
if (dram_type == DRAM_TYPE_LPDDR4) {
u32 nRTP = 16;
if (src_clk_period >= 1000000 / 1866) /* 535.91 ps */
nRTP = 14;
if (src_clk_period >= 1000000 / 1600) /* 625.00 ps */
nRTP = 12;
if (src_clk_period >= 1000000 / 1333) /* 750.19 ps */
nRTP = 10;
if (src_clk_period >= 1000000 / 1066) /* 938.09 ps */
nRTP = 8;
deltaTWATM = max_t(u32, div_o3(7500, src_clk_period), 8);
/*
* Originally there was a + .5 in the tRPST calculation.
* However since we can't do FP in the kernel and the tRTM
* computation was in a floating point ceiling function, adding
* one to tRTP should be ok. There is no other source of non
* integer values, so the result was always going to be
* something for the form: f_ceil(N + .5) = N + 1;
*/
tRPST = (last->emc_mrw & 0x80) >> 7;
tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) +
max_t(u32, div_o3(7500, src_clk_period), 8) + tRPST +
1 + nRTP;
emc_dbg(emc, INFO, "tRTM = %u, EMC_RP = %u\n", tRTM,
next->burst_regs[EMC_RP_INDEX]);
if (last->burst_regs[EMC_RP_INDEX] < tRTM) {
if (tRTM > (last->burst_regs[EMC_R2P_INDEX] +
last->burst_regs[EMC_RP_INDEX])) {
R2P_war = tRTM - last->burst_regs[EMC_RP_INDEX];
RP_war = last->burst_regs[EMC_RP_INDEX];
TRPab_war = last->burst_regs[EMC_TRPAB_INDEX];
if (R2P_war > 63) {
RP_war = R2P_war +
last->burst_regs[EMC_RP_INDEX] - 63;
if (TRPab_war < RP_war)
TRPab_war = RP_war;
R2P_war = 63;
}
} else {
R2P_war = last->burst_regs[EMC_R2P_INDEX];
RP_war = last->burst_regs[EMC_RP_INDEX];
TRPab_war = last->burst_regs[EMC_TRPAB_INDEX];
}
if (RP_war < deltaTWATM) {
W2P_war = last->burst_regs[EMC_W2P_INDEX]
+ deltaTWATM - RP_war;
if (W2P_war > 63) {
RP_war = RP_war + W2P_war - 63;
if (TRPab_war < RP_war)
TRPab_war = RP_war;
W2P_war = 63;
}
} else {
W2P_war = last->burst_regs[
EMC_W2P_INDEX];
}
if ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) ||
(last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) ||
(last->burst_regs[EMC_RP_INDEX] ^ RP_war) ||
(last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) {
emc_writel(emc, RP_war, EMC_RP);
emc_writel(emc, R2P_war, EMC_R2P);
emc_writel(emc, W2P_war, EMC_W2P);
emc_writel(emc, TRPab_war, EMC_TRPAB);
}
tegra210_emc_timing_update(emc);
} else {
emc_dbg(emc, INFO, "Skipped WAR\n");
}
}
if (!fsp_for_next_freq) {
mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80;
mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00;
} else {
mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40;
mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0;
}
if (dram_type == DRAM_TYPE_LPDDR4) {
emc_writel(emc, mr13_flip_fspwr, EMC_MRW3);
emc_writel(emc, next->emc_mrw, EMC_MRW);
emc_writel(emc, next->emc_mrw2, EMC_MRW2);
}
/*
* Step 8:
* Program the shadow registers.
*/
emc_dbg(emc, STEPS, "Step 8\n");
emc_dbg(emc, SUB_STEPS, "Writing burst_regs\n");
for (i = 0; i < next->num_burst; i++) {
const u16 *offsets = emc->offsets->burst;
u16 offset;
if (!offsets[i])
continue;
value = next->burst_regs[i];
offset = offsets[i];
if (dram_type != DRAM_TYPE_LPDDR4 &&
(offset == EMC_MRW6 || offset == EMC_MRW7 ||
offset == EMC_MRW8 || offset == EMC_MRW9 ||
offset == EMC_MRW10 || offset == EMC_MRW11 ||
offset == EMC_MRW12 || offset == EMC_MRW13 ||
offset == EMC_MRW14 || offset == EMC_MRW15 ||
offset == EMC_TRAINING_CTRL))
continue;
/* Pain... And suffering. */
if (offset == EMC_CFG) {
value &= ~EMC_CFG_DRAM_ACPD;
value &= ~EMC_CFG_DYN_SELF_REF;
if (dram_type == DRAM_TYPE_LPDDR4) {
value &= ~EMC_CFG_DRAM_CLKSTOP_SR;
value &= ~EMC_CFG_DRAM_CLKSTOP_PD;
}
} else if (offset == EMC_MRS_WAIT_CNT &&
dram_type == DRAM_TYPE_LPDDR2 &&
opt_zcal_en_cc && !opt_cc_short_zcal &&
opt_short_zcal) {
value = (value & ~(EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK <<
EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)) |
((zq_wait_long & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) <<
EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT);
} else if (offset == EMC_ZCAL_WAIT_CNT &&
dram_type == DRAM_TYPE_DDR3 && opt_zcal_en_cc &&
!opt_cc_short_zcal && opt_short_zcal) {
value = (value & ~(EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK <<
EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT)) |
((zq_wait_long & EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK) <<
EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT);
} else if (offset == EMC_ZCAL_INTERVAL && opt_zcal_en_cc) {
value = 0; /* EMC_ZCAL_INTERVAL reset value. */
} else if (offset == EMC_PMACRO_AUTOCAL_CFG_COMMON) {
value |= EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS;
} else if (offset == EMC_PMACRO_DATA_PAD_TX_CTRL) {
value &= ~(EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC |
EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC);
} else if (offset == EMC_PMACRO_CMD_PAD_TX_CTRL) {
value |= EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON;
value &= ~(EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC |
EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC);
} else if (offset == EMC_PMACRO_BRICK_CTRL_RFU1) {
value &= 0xf800f800;
} else if (offset == EMC_PMACRO_COMMON_PAD_TX_CTRL) {
value &= 0xfffffff0;
}
emc_writel(emc, value, offset);
}
/* SW addition: do EMC refresh adjustment here. */
tegra210_emc_adjust_timing(emc, next);
if (dram_type == DRAM_TYPE_LPDDR4) {
value = (23 << EMC_MRW_MRW_MA_SHIFT) |
(next->run_clocks & EMC_MRW_MRW_OP_MASK);
emc_writel(emc, value, EMC_MRW);
}
/* Per channel burst registers. */
emc_dbg(emc, SUB_STEPS, "Writing burst_regs_per_ch\n");
for (i = 0; i < next->num_burst_per_ch; i++) {
const struct tegra210_emc_per_channel_regs *burst =
emc->offsets->burst_per_channel;
if (!burst[i].offset)
continue;
if (dram_type != DRAM_TYPE_LPDDR4 &&
(burst[i].offset == EMC_MRW6 ||
burst[i].offset == EMC_MRW7 ||
burst[i].offset == EMC_MRW8 ||
burst[i].offset == EMC_MRW9 ||
burst[i].offset == EMC_MRW10 ||
burst[i].offset == EMC_MRW11 ||
burst[i].offset == EMC_MRW12 ||
burst[i].offset == EMC_MRW13 ||
burst[i].offset == EMC_MRW14 ||
burst[i].offset == EMC_MRW15))
continue;
/* Filter out second channel if not in DUAL_CHANNEL mode. */
if (emc->num_channels < 2 && burst[i].bank >= 1)
continue;
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
next->burst_reg_per_ch[i], burst[i].offset);
emc_channel_writel(emc, burst[i].bank,
next->burst_reg_per_ch[i],
burst[i].offset);
}
/* Vref regs. */
emc_dbg(emc, SUB_STEPS, "Writing vref_regs\n");
for (i = 0; i < next->vref_num; i++) {
const struct tegra210_emc_per_channel_regs *vref =
emc->offsets->vref_per_channel;
if (!vref[i].offset)
continue;
if (emc->num_channels < 2 && vref[i].bank >= 1)
continue;
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
next->vref_perch_regs[i], vref[i].offset);
emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i],
vref[i].offset);
}
/* Trimmers. */
emc_dbg(emc, SUB_STEPS, "Writing trim_regs\n");
for (i = 0; i < next->num_trim; i++) {
const u16 *offsets = emc->offsets->trim;
if (!offsets[i])
continue;
if (compensate_trimmer_applicable &&
(offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 ||
offsets[i] == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 ||
offsets[i] == EMC_DATA_BRLSHFT_0 ||
offsets[i] == EMC_DATA_BRLSHFT_1)) {
value = tegra210_emc_compensate(next, offsets[i]);
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
value, offsets[i]);
emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n",
(u32)(u64)offsets[i], value);
emc_writel(emc, value, offsets[i]);
} else {
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
next->trim_regs[i], offsets[i]);
emc_writel(emc, next->trim_regs[i], offsets[i]);
}
}
/* Per channel trimmers. */
emc_dbg(emc, SUB_STEPS, "Writing trim_regs_per_ch\n");
for (i = 0; i < next->num_trim_per_ch; i++) {
const struct tegra210_emc_per_channel_regs *trim =
&emc->offsets->trim_per_channel[0];
unsigned int offset;
if (!trim[i].offset)
continue;
if (emc->num_channels < 2 && trim[i].bank >= 1)
continue;
offset = trim[i].offset;
if (compensate_trimmer_applicable &&
(offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 ||
offset == EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 ||
offset == EMC_DATA_BRLSHFT_0 ||
offset == EMC_DATA_BRLSHFT_1)) {
value = tegra210_emc_compensate(next, offset);
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
value, offset);
emc_dbg(emc, EMA_WRITES, "0x%08x <= 0x%08x\n", offset,
value);
emc_channel_writel(emc, trim[i].bank, value, offset);
} else {
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
next->trim_perch_regs[i], offset);
emc_channel_writel(emc, trim[i].bank,
next->trim_perch_regs[i], offset);
}
}
emc_dbg(emc, SUB_STEPS, "Writing burst_mc_regs\n");
for (i = 0; i < next->num_mc_regs; i++) {
const u16 *offsets = emc->offsets->burst_mc;
u32 *values = next->burst_mc_regs;
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
values[i], offsets[i]);
mc_writel(emc->mc, values[i], offsets[i]);
}
/* Registers to be programmed on the faster clock. */
if (next->rate < last->rate) {
const u16 *la = emc->offsets->la_scale;
emc_dbg(emc, SUB_STEPS, "Writing la_scale_regs\n");
for (i = 0; i < next->num_up_down; i++) {
emc_dbg(emc, REG_LISTS, "(%u) 0x%08x => 0x%08x\n", i,
next->la_scale_regs[i], la[i]);
mc_writel(emc->mc, next->la_scale_regs[i], la[i]);
}
}
/* Flush all the burst register writes. */
mc_readl(emc->mc, MC_EMEM_ADR_CFG);
/*
* Step 9:
* LPDDR4 section A.
*/
emc_dbg(emc, STEPS, "Step 9\n");
value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX];
value &= ~EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK;
if (dram_type == DRAM_TYPE_LPDDR4) {
emc_writel(emc, 0, EMC_ZCAL_INTERVAL);
emc_writel(emc, value, EMC_ZCAL_WAIT_CNT);
value = emc_dbg | (EMC_DBG_WRITE_MUX_ACTIVE |
EMC_DBG_WRITE_ACTIVE_ONLY);
emc_writel(emc, value, EMC_DBG);
emc_writel(emc, 0, EMC_ZCAL_INTERVAL);
emc_writel(emc, emc_dbg, EMC_DBG);
}
/*
* Step 10:
* LPDDR4 and DDR3 common section.
*/
emc_dbg(emc, STEPS, "Step 10\n");
if (opt_dvfs_mode == MAN_SR || dram_type == DRAM_TYPE_LPDDR4) {
if (dram_type == DRAM_TYPE_LPDDR4)
ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0);
else
ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0);
if (dram_type == DRAM_TYPE_LPDDR4 &&
dst_clk_period <= zqcal_before_cc_cutoff) {
ccfifo_writel(emc, mr13_flip_fspwr ^ 0x40, EMC_MRW3, 0);
ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &
0xFFFF3F3F) |
(last->burst_regs[EMC_MRW6_INDEX] &
0x0000C0C0), EMC_MRW6, 0);
ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &
0xFFFF0707) |
(last->burst_regs[EMC_MRW14_INDEX] &
0x00003838), EMC_MRW14, 0);
if (emc->num_devices > 1) {
ccfifo_writel(emc,
(next->burst_regs[EMC_MRW7_INDEX] &
0xFFFF3F3F) |
(last->burst_regs[EMC_MRW7_INDEX] &
0x0000C0C0), EMC_MRW7, 0);
ccfifo_writel(emc,
(next->burst_regs[EMC_MRW15_INDEX] &
0xFFFF0707) |
(last->burst_regs[EMC_MRW15_INDEX] &
0x00003838), EMC_MRW15, 0);
}
if (opt_zcal_en_cc) {
if (emc->num_devices < 2)
ccfifo_writel(emc,
2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT
| EMC_ZQ_CAL_ZQ_CAL_CMD,
EMC_ZQ_CAL, 0);
else if (shared_zq_resistor)
ccfifo_writel(emc,
2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT
| EMC_ZQ_CAL_ZQ_CAL_CMD,
EMC_ZQ_CAL, 0);
else
ccfifo_writel(emc,
EMC_ZQ_CAL_ZQ_CAL_CMD,
EMC_ZQ_CAL, 0);
}
}
}
if (dram_type == DRAM_TYPE_LPDDR4) {
value = (1000 * fake->dram_timings[T_RP]) / src_clk_period;
ccfifo_writel(emc, mr13_flip_fspop | 0x8, EMC_MRW3, value);
ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);
}
if (dram_type == DRAM_TYPE_LPDDR4 || opt_dvfs_mode != MAN_SR) {
delay = 30;
if (cya_allow_ref_cc) {
delay += (1000 * fake->dram_timings[T_RP]) /
src_clk_period;
delay += 4000 * fake->dram_timings[T_RFC];
}
ccfifo_writel(emc, emc_pin & ~(EMC_PIN_PIN_CKE_PER_DEV |
EMC_PIN_PIN_CKEB |
EMC_PIN_PIN_CKE),
EMC_PIN, delay);
}
/* calculate reference delay multiplier */
value = 1;
if (ref_b4_sref_en)
value++;
if (cya_allow_ref_cc)
value++;
if (cya_issue_pc_ref)
value++;
if (dram_type != DRAM_TYPE_LPDDR4) {
delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) +
(1000 * fake->dram_timings[T_RFC] / src_clk_period));
delay = value * delay + 20;
} else {
delay = 0;
}
/*
* Step 11:
* Ramp down.
*/
emc_dbg(emc, STEPS, "Step 11\n");
ccfifo_writel(emc, 0x0, EMC_CFG_SYNC, delay);
value = emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE | EMC_DBG_WRITE_ACTIVE_ONLY;
ccfifo_writel(emc, value, EMC_DBG, 0);
ramp_down_wait = tegra210_emc_dvfs_power_ramp_down(emc, src_clk_period,
0);
/*
* Step 12:
* And finally - trigger the clock change.
*/
emc_dbg(emc, STEPS, "Step 12\n");
ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE, 0);
value &= ~EMC_DBG_WRITE_ACTIVE_ONLY;
ccfifo_writel(emc, value, EMC_DBG, 0);
/*
* Step 13:
* Ramp up.
*/
emc_dbg(emc, STEPS, "Step 13\n");
ramp_up_wait = tegra210_emc_dvfs_power_ramp_up(emc, dst_clk_period, 0);
ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
/*
* Step 14:
* Bringup CKE pins.
*/
emc_dbg(emc, STEPS, "Step 14\n");
if (dram_type == DRAM_TYPE_LPDDR4) {
value = emc_pin | EMC_PIN_PIN_CKE;
if (emc->num_devices <= 1)
value &= ~(EMC_PIN_PIN_CKEB | EMC_PIN_PIN_CKE_PER_DEV);
else
value |= EMC_PIN_PIN_CKEB | EMC_PIN_PIN_CKE_PER_DEV;
ccfifo_writel(emc, value, EMC_PIN, 0);
}
/*
* Step 15: (two step 15s ??)
* Calculate zqlatch wait time; has dependency on ramping times.
*/
emc_dbg(emc, STEPS, "Step 15\n");
if (dst_clk_period <= zqcal_before_cc_cutoff) {
s32 t = (s32)(ramp_up_wait + ramp_down_wait) /
(s32)dst_clk_period;
zq_latch_dvfs_wait_time = (s32)tZQCAL_lpddr4_fc_adj - t;
} else {
zq_latch_dvfs_wait_time = tZQCAL_lpddr4_fc_adj -
div_o3(1000 * next->dram_timings[T_PDEX],
dst_clk_period);
}
emc_dbg(emc, INFO, "tZQCAL_lpddr4_fc_adj = %u\n", tZQCAL_lpddr4_fc_adj);
emc_dbg(emc, INFO, "dst_clk_period = %u\n",
dst_clk_period);
emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n",
next->dram_timings[T_PDEX]);
emc_dbg(emc, INFO, "zq_latch_dvfs_wait_time = %d\n",
max_t(s32, 0, zq_latch_dvfs_wait_time));
if (dram_type == DRAM_TYPE_LPDDR4 && opt_zcal_en_cc) {
delay = div_o3(1000 * next->dram_timings[T_PDEX],
dst_clk_period);
if (emc->num_devices < 2) {
if (dst_clk_period > zqcal_before_cc_cutoff)
ccfifo_writel(emc,
2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,
delay);
value = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;
ccfifo_writel(emc, value, EMC_MRW3, delay);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_LATCH_CMD,
EMC_ZQ_CAL,
max_t(s32, 0, zq_latch_dvfs_wait_time));
} else if (shared_zq_resistor) {
if (dst_clk_period > zqcal_before_cc_cutoff)
ccfifo_writel(emc,
2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,
delay);
ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,
max_t(s32, 0, zq_latch_dvfs_wait_time) +
delay);
ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_LATCH_CMD,
EMC_ZQ_CAL, 0);
value = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;
ccfifo_writel(emc, value, EMC_MRW3, 0);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,
tZQCAL_lpddr4 / dst_clk_period);
} else {
if (dst_clk_period > zqcal_before_cc_cutoff)
ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_CAL_CMD,
EMC_ZQ_CAL, delay);
value = (mr13_flip_fspop & 0xfffffff7) | 0x0c000000;
ccfifo_writel(emc, value, EMC_MRW3, delay);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,
max_t(s32, 0, zq_latch_dvfs_wait_time));
}
}
/* WAR: delay for zqlatch */
ccfifo_writel(emc, 0, 0, 10);
/*
* Step 16:
* LPDDR4 Conditional Training Kickoff. Removed.
*/
/*
* Step 17:
* MANSR exit self refresh.
*/
emc_dbg(emc, STEPS, "Step 17\n");
if (opt_dvfs_mode == MAN_SR && dram_type != DRAM_TYPE_LPDDR4)
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
/*
* Step 18:
* Send MRWs to LPDDR3/DDR3.
*/
emc_dbg(emc, STEPS, "Step 18\n");
if (dram_type == DRAM_TYPE_LPDDR2) {
ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);
ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0);
if (is_lpddr3)
ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);
} else if (dram_type == DRAM_TYPE_DDR3) {
if (opt_dll_mode)
ccfifo_writel(emc, next->emc_emrs &
~EMC_EMRS_USE_EMRS_LONG_CNT, EMC_EMRS, 0);
ccfifo_writel(emc, next->emc_emrs2 &
~EMC_EMRS2_USE_EMRS2_LONG_CNT, EMC_EMRS2, 0);
ccfifo_writel(emc, next->emc_mrs |
EMC_EMRS_USE_EMRS_LONG_CNT, EMC_MRS, 0);
}
/*
* Step 19:
* ZQCAL for LPDDR3/DDR3
*/
emc_dbg(emc, STEPS, "Step 19\n");
if (opt_zcal_en_cc) {
if (dram_type == DRAM_TYPE_LPDDR2) {
value = opt_cc_short_zcal ? 90000 : 360000;
value = div_o3(value, dst_clk_period);
value = value <<
EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT |
value <<
EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT;
ccfifo_writel(emc, value, EMC_MRS_WAIT_CNT2, 0);
value = opt_cc_short_zcal ? 0x56 : 0xab;
ccfifo_writel(emc, 2 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |
EMC_MRW_USE_MRW_EXT_CNT |
10 << EMC_MRW_MRW_MA_SHIFT |
value << EMC_MRW_MRW_OP_SHIFT,
EMC_MRW, 0);
if (emc->num_devices > 1) {
value = 1 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |
EMC_MRW_USE_MRW_EXT_CNT |
10 << EMC_MRW_MRW_MA_SHIFT |
value << EMC_MRW_MRW_OP_SHIFT;
ccfifo_writel(emc, value, EMC_MRW, 0);
}
} else if (dram_type == DRAM_TYPE_DDR3) {
value = opt_cc_short_zcal ? 0 : EMC_ZQ_CAL_LONG;
ccfifo_writel(emc, value |
2 << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_CAL_CMD, EMC_ZQ_CAL,
0);
if (emc->num_devices > 1) {
value = value | 1 << EMC_ZQ_CAL_DEV_SEL_SHIFT |
EMC_ZQ_CAL_ZQ_CAL_CMD;
ccfifo_writel(emc, value, EMC_ZQ_CAL, 0);
}
}
}
if (bg_reg_mode_change) {
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
if (ramp_up_wait <= 1250000)
delay = (1250000 - ramp_up_wait) / dst_clk_period;
else
delay = 0;
ccfifo_writel(emc,
next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX],
EMC_PMACRO_BG_BIAS_CTRL_0, delay);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
}
/*
* Step 20:
* Issue ref and optional QRST.
*/
emc_dbg(emc, STEPS, "Step 20\n");
if (dram_type != DRAM_TYPE_LPDDR4)
ccfifo_writel(emc, 0, EMC_REF, 0);
if (opt_do_sw_qrst) {
ccfifo_writel(emc, 1, EMC_ISSUE_QRST, 0);
ccfifo_writel(emc, 0, EMC_ISSUE_QRST, 2);
}
/*
* Step 21:
* Restore ZCAL and ZCAL interval.
*/
emc_dbg(emc, STEPS, "Step 21\n");
if (save_restore_clkstop_pd || opt_zcal_en_cc) {
ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
EMC_DBG, 0);
if (opt_zcal_en_cc && dram_type != DRAM_TYPE_LPDDR4)
ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
EMC_ZCAL_INTERVAL, 0);
if (save_restore_clkstop_pd)
ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &
~EMC_CFG_DYN_SELF_REF,
EMC_CFG, 0);
ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
}
/*
* Step 22:
* Restore EMC_CFG_PIPE_CLK.
*/
emc_dbg(emc, STEPS, "Step 22\n");
ccfifo_writel(emc, emc_cfg_pipe_clk, EMC_CFG_PIPE_CLK, 0);
if (bg_reg_mode_change) {
if (enable_bg_reg)
emc_writel(emc,
next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
~EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD,
EMC_PMACRO_BG_BIAS_CTRL_0);
else
emc_writel(emc,
next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
~EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD,
EMC_PMACRO_BG_BIAS_CTRL_0);
}
/*
* Step 23:
*/
emc_dbg(emc, STEPS, "Step 23\n");
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value |= EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_EN;
value = (value & ~EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK) |
(2 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT);
emc_writel(emc, value, EMC_CFG_DIG_DLL);
tegra210_emc_do_clock_change(emc, clksrc);
/*
* Step 24:
* Save training results. Removed.
*/
/*
* Step 25:
* Program MC updown registers.
*/
emc_dbg(emc, STEPS, "Step 25\n");
if (next->rate > last->rate) {
for (i = 0; i < next->num_up_down; i++)
mc_writel(emc->mc, next->la_scale_regs[i],
emc->offsets->la_scale[i]);
tegra210_emc_timing_update(emc);
}
/*
* Step 26:
* Restore ZCAL registers.
*/
emc_dbg(emc, STEPS, "Step 26\n");
if (dram_type == DRAM_TYPE_LPDDR4) {
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],
EMC_ZCAL_WAIT_CNT);
emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
EMC_ZCAL_INTERVAL);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
}
if (dram_type != DRAM_TYPE_LPDDR4 && opt_zcal_en_cc &&
!opt_short_zcal && opt_cc_short_zcal) {
udelay(2);
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
if (dram_type == DRAM_TYPE_LPDDR2)
emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX],
EMC_MRS_WAIT_CNT);
else if (dram_type == DRAM_TYPE_DDR3)
emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],
EMC_ZCAL_WAIT_CNT);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
}
/*
* Step 27:
* Restore EMC_CFG, FDPD registers.
*/
emc_dbg(emc, STEPS, "Step 27\n");
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp,
EMC_FDPD_CTRL_CMD_NO_RAMP);
emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);
/*
* Step 28:
* Training recover. Removed.
*/
emc_dbg(emc, STEPS, "Step 28\n");
tegra210_emc_set_shadow_bypass(emc, ACTIVE);
emc_writel(emc,
next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX],
EMC_PMACRO_AUTOCAL_CFG_COMMON);
tegra210_emc_set_shadow_bypass(emc, ASSEMBLY);
/*
* Step 29:
* Power fix WAR.
*/
emc_dbg(emc, STEPS, "Step 29\n");
emc_writel(emc, EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 |
EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7,
EMC_PMACRO_CFG_PM_GLOBAL_0);
emc_writel(emc, EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR,
EMC_PMACRO_TRAINING_CTRL_0);
emc_writel(emc, EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR,
EMC_PMACRO_TRAINING_CTRL_1);
emc_writel(emc, 0, EMC_PMACRO_CFG_PM_GLOBAL_0);
/*
* Step 30:
* Re-enable autocal.
*/
emc_dbg(emc, STEPS, "Step 30: Re-enable DLL and AUTOCAL\n");
if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) {
value = emc_readl(emc, EMC_CFG_DIG_DLL);
value |= EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC;
value |= EMC_CFG_DIG_DLL_CFG_DLL_EN;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK;
value &= ~EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK;
value = (value & ~EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK) |
(2 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT);
emc_writel(emc, value, EMC_CFG_DIG_DLL);
tegra210_emc_timing_update(emc);
}
emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);
/* Done! Yay. */
}
const struct tegra210_emc_sequence tegra210_emc_r21021 = {
.revision = 0x7,
.set_clock = tegra210_emc_r21021_set_clock,
.periodic_compensation = tegra210_emc_r21021_periodic_compensation,
};
|
linux-master
|
drivers/memory/tegra/tegra210-emc-cc-r21021.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* non-coherent cache functions for Andes AX45MP
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include <linux/cacheflush.h>
#include <linux/cacheinfo.h>
#include <linux/dma-direction.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/dma-noncoherent.h>
/* L2 cache registers */
#define AX45MP_L2C_REG_CTL_OFFSET 0x8
#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40
#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48
#define AX45MP_L2C_REG_STATUS_OFFSET 0x80
/* D-cache operation */
#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */
#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
/* L2 CCTL status */
#define AX45MP_CCTL_L2_STATUS_IDLE 0
/* L2 CCTL status cores mask */
#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf
/* L2 cache operation */
#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */
#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10
#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4
#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \
(AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \
(AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \
(AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b
#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c
#define AX45MP_CACHE_LINE_SIZE 64
struct ax45mp_priv {
void __iomem *l2c_base;
u32 ax45mp_cache_line_size;
};
static struct ax45mp_priv ax45mp_priv;
/* L2 Cache operations */
static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
{
return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
}
static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
unsigned int l1_op, unsigned int l2_op)
{
unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
void __iomem *base = ax45mp_priv.l2c_base;
int mhartid = smp_processor_id();
unsigned long pa;
while (end > start) {
csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
pa = virt_to_phys((void *)start);
writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
while ((ax45mp_cpu_l2c_get_cctl_status() &
AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
AX45MP_CCTL_L2_STATUS_IDLE)
;
start += line_size;
}
}
/* Write-back L1 and L2 cache entry */
static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
{
ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
AX45MP_CCTL_L2_PA_WB);
}
/* Invalidate the L1 and L2 cache entry */
static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
{
ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
AX45MP_CCTL_L2_PA_INVAL);
}
static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
unsigned long line_size;
unsigned long flags;
if (unlikely(start == end))
return;
line_size = ax45mp_priv.ax45mp_cache_line_size;
start = start & (~(line_size - 1));
end = ((end + line_size - 1) & (~(line_size - 1)));
local_irq_save(flags);
ax45mp_cpu_dcache_inval_range(start, end);
local_irq_restore(flags);
}
static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
{
unsigned long start = (unsigned long)phys_to_virt(paddr);
unsigned long end = start + size;
unsigned long line_size;
unsigned long flags;
line_size = ax45mp_priv.ax45mp_cache_line_size;
start = start & (~(line_size - 1));
local_irq_save(flags);
ax45mp_cpu_dcache_wb_range(start, end);
local_irq_restore(flags);
}
static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
{
ax45mp_dma_cache_wback(paddr, size);
ax45mp_dma_cache_inv(paddr, size);
}
static int ax45mp_get_l2_line_size(struct device_node *np)
{
int ret;
ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
if (ret) {
pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
return ret;
}
if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
ax45mp_priv.ax45mp_cache_line_size);
return -EINVAL;
}
return 0;
}
static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
.wback = &ax45mp_dma_cache_wback,
.inv = &ax45mp_dma_cache_inv,
.wback_inv = &ax45mp_dma_cache_wback_inv,
};
static const struct of_device_id ax45mp_cache_ids[] = {
{ .compatible = "andestech,ax45mp-cache" },
{ /* sentinel */ }
};
static int __init ax45mp_cache_init(void)
{
struct device_node *np;
struct resource res;
int ret;
np = of_find_matching_node(NULL, ax45mp_cache_ids);
if (!of_device_is_available(np))
return -ENODEV;
ret = of_address_to_resource(np, 0, &res);
if (ret)
return ret;
/*
* If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
* will be 0 for sure, so we can definitely rely on it. If
* riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
* more so we just return success here and only if its being set we
* continue further in the probe path.
*/
if (!riscv_cbom_block_size)
return 0;
ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
if (!ax45mp_priv.l2c_base)
return -ENOMEM;
ret = ax45mp_get_l2_line_size(np);
if (ret) {
iounmap(ax45mp_priv.l2c_base);
return ret;
}
riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops);
return 0;
}
early_initcall(ax45mp_cache_init);
|
linux-master
|
drivers/cache/ax45mp_cache.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Zynq pin controller
*
* Copyright (C) 2014 Xilinx
*
* Sören Brinkmann <[email protected]>
*/
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
#include "pinctrl-utils.h"
#include "core.h"
#define ZYNQ_NUM_MIOS 54
#define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
#define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
#define ZYNQ_PINMUX_MUX_SHIFT 1
#define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
/**
* struct zynq_pinctrl - driver data
* @pctrl: Pinctrl device
* @syscon: Syscon regmap
* @pctrl_offset: Offset for pinctrl into the @syscon space
* @groups: Pingroups
* @ngroups: Number of @groups
* @funcs: Pinmux functions
* @nfuncs: Number of @funcs
*/
struct zynq_pinctrl {
struct pinctrl_dev *pctrl;
struct regmap *syscon;
u32 pctrl_offset;
const struct zynq_pctrl_group *groups;
unsigned int ngroups;
const struct zynq_pinmux_function *funcs;
unsigned int nfuncs;
};
struct zynq_pctrl_group {
const char *name;
const unsigned int *pins;
const unsigned int npins;
};
/**
* struct zynq_pinmux_function - a pinmux function
* @name: Name of the pinmux function.
* @groups: List of pingroups for this function.
* @ngroups: Number of entries in @groups.
* @mux_val: Selector for this function
* @mux: Offset of function specific mux
* @mux_mask: Mask for function specific selector
* @mux_shift: Shift for function specific selector
*/
struct zynq_pinmux_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
unsigned int mux_val;
u32 mux;
u32 mux_mask;
u8 mux_shift;
};
enum zynq_pinmux_functions {
ZYNQ_PMUX_can0,
ZYNQ_PMUX_can1,
ZYNQ_PMUX_ethernet0,
ZYNQ_PMUX_ethernet1,
ZYNQ_PMUX_gpio0,
ZYNQ_PMUX_i2c0,
ZYNQ_PMUX_i2c1,
ZYNQ_PMUX_mdio0,
ZYNQ_PMUX_mdio1,
ZYNQ_PMUX_qspi0,
ZYNQ_PMUX_qspi1,
ZYNQ_PMUX_qspi_fbclk,
ZYNQ_PMUX_qspi_cs1,
ZYNQ_PMUX_spi0,
ZYNQ_PMUX_spi1,
ZYNQ_PMUX_spi0_ss,
ZYNQ_PMUX_spi1_ss,
ZYNQ_PMUX_sdio0,
ZYNQ_PMUX_sdio0_pc,
ZYNQ_PMUX_sdio0_cd,
ZYNQ_PMUX_sdio0_wp,
ZYNQ_PMUX_sdio1,
ZYNQ_PMUX_sdio1_pc,
ZYNQ_PMUX_sdio1_cd,
ZYNQ_PMUX_sdio1_wp,
ZYNQ_PMUX_smc0_nor,
ZYNQ_PMUX_smc0_nor_cs1,
ZYNQ_PMUX_smc0_nor_addr25,
ZYNQ_PMUX_smc0_nand,
ZYNQ_PMUX_ttc0,
ZYNQ_PMUX_ttc1,
ZYNQ_PMUX_uart0,
ZYNQ_PMUX_uart1,
ZYNQ_PMUX_usb0,
ZYNQ_PMUX_usb1,
ZYNQ_PMUX_swdt0,
ZYNQ_PMUX_MAX_FUNC
};
static const struct pinctrl_pin_desc zynq_pins[] = {
PINCTRL_PIN(0, "MIO0"),
PINCTRL_PIN(1, "MIO1"),
PINCTRL_PIN(2, "MIO2"),
PINCTRL_PIN(3, "MIO3"),
PINCTRL_PIN(4, "MIO4"),
PINCTRL_PIN(5, "MIO5"),
PINCTRL_PIN(6, "MIO6"),
PINCTRL_PIN(7, "MIO7"),
PINCTRL_PIN(8, "MIO8"),
PINCTRL_PIN(9, "MIO9"),
PINCTRL_PIN(10, "MIO10"),
PINCTRL_PIN(11, "MIO11"),
PINCTRL_PIN(12, "MIO12"),
PINCTRL_PIN(13, "MIO13"),
PINCTRL_PIN(14, "MIO14"),
PINCTRL_PIN(15, "MIO15"),
PINCTRL_PIN(16, "MIO16"),
PINCTRL_PIN(17, "MIO17"),
PINCTRL_PIN(18, "MIO18"),
PINCTRL_PIN(19, "MIO19"),
PINCTRL_PIN(20, "MIO20"),
PINCTRL_PIN(21, "MIO21"),
PINCTRL_PIN(22, "MIO22"),
PINCTRL_PIN(23, "MIO23"),
PINCTRL_PIN(24, "MIO24"),
PINCTRL_PIN(25, "MIO25"),
PINCTRL_PIN(26, "MIO26"),
PINCTRL_PIN(27, "MIO27"),
PINCTRL_PIN(28, "MIO28"),
PINCTRL_PIN(29, "MIO29"),
PINCTRL_PIN(30, "MIO30"),
PINCTRL_PIN(31, "MIO31"),
PINCTRL_PIN(32, "MIO32"),
PINCTRL_PIN(33, "MIO33"),
PINCTRL_PIN(34, "MIO34"),
PINCTRL_PIN(35, "MIO35"),
PINCTRL_PIN(36, "MIO36"),
PINCTRL_PIN(37, "MIO37"),
PINCTRL_PIN(38, "MIO38"),
PINCTRL_PIN(39, "MIO39"),
PINCTRL_PIN(40, "MIO40"),
PINCTRL_PIN(41, "MIO41"),
PINCTRL_PIN(42, "MIO42"),
PINCTRL_PIN(43, "MIO43"),
PINCTRL_PIN(44, "MIO44"),
PINCTRL_PIN(45, "MIO45"),
PINCTRL_PIN(46, "MIO46"),
PINCTRL_PIN(47, "MIO47"),
PINCTRL_PIN(48, "MIO48"),
PINCTRL_PIN(49, "MIO49"),
PINCTRL_PIN(50, "MIO50"),
PINCTRL_PIN(51, "MIO51"),
PINCTRL_PIN(52, "MIO52"),
PINCTRL_PIN(53, "MIO53"),
PINCTRL_PIN(54, "EMIO_SD0_WP"),
PINCTRL_PIN(55, "EMIO_SD0_CD"),
PINCTRL_PIN(56, "EMIO_SD1_WP"),
PINCTRL_PIN(57, "EMIO_SD1_CD"),
};
/* pin groups */
static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27};
static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39};
static const unsigned int mdio0_0_pins[] = {52, 53};
static const unsigned int mdio1_0_pins[] = {52, 53};
static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
static const unsigned int qspi_cs1_pins[] = {0};
static const unsigned int qspi_fbclk_pins[] = {8};
static const unsigned int spi0_0_pins[] = {16, 17, 21};
static const unsigned int spi0_0_ss0_pins[] = {18};
static const unsigned int spi0_0_ss1_pins[] = {19};
static const unsigned int spi0_0_ss2_pins[] = {20,};
static const unsigned int spi0_1_pins[] = {28, 29, 33};
static const unsigned int spi0_1_ss0_pins[] = {30};
static const unsigned int spi0_1_ss1_pins[] = {31};
static const unsigned int spi0_1_ss2_pins[] = {32};
static const unsigned int spi0_2_pins[] = {40, 41, 45};
static const unsigned int spi0_2_ss0_pins[] = {42};
static const unsigned int spi0_2_ss1_pins[] = {43};
static const unsigned int spi0_2_ss2_pins[] = {44};
static const unsigned int spi1_0_pins[] = {10, 11, 12};
static const unsigned int spi1_0_ss0_pins[] = {13};
static const unsigned int spi1_0_ss1_pins[] = {14};
static const unsigned int spi1_0_ss2_pins[] = {15};
static const unsigned int spi1_1_pins[] = {22, 23, 24};
static const unsigned int spi1_1_ss0_pins[] = {25};
static const unsigned int spi1_1_ss1_pins[] = {26};
static const unsigned int spi1_1_ss2_pins[] = {27};
static const unsigned int spi1_2_pins[] = {34, 35, 36};
static const unsigned int spi1_2_ss0_pins[] = {37};
static const unsigned int spi1_2_ss1_pins[] = {38};
static const unsigned int spi1_2_ss2_pins[] = {39};
static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
static const unsigned int spi1_3_ss0_pins[] = {49};
static const unsigned int spi1_3_ss1_pins[] = {50};
static const unsigned int spi1_3_ss2_pins[] = {51};
static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
static const unsigned int sdio0_emio_wp_pins[] = {54};
static const unsigned int sdio0_emio_cd_pins[] = {55};
static const unsigned int sdio1_emio_wp_pins[] = {56};
static const unsigned int sdio1_emio_cd_pins[] = {57};
static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
15, 16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39};
static const unsigned int smc0_nor_cs1_pins[] = {1};
static const unsigned int smc0_nor_addr25_pins[] = {1};
static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12, 13, 14, 16, 17, 18, 19, 20,
21, 22, 23};
static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14};
/* Note: CAN MIO clock inputs are modeled in the clock framework */
static const unsigned int can0_0_pins[] = {10, 11};
static const unsigned int can0_1_pins[] = {14, 15};
static const unsigned int can0_2_pins[] = {18, 19};
static const unsigned int can0_3_pins[] = {22, 23};
static const unsigned int can0_4_pins[] = {26, 27};
static const unsigned int can0_5_pins[] = {30, 31};
static const unsigned int can0_6_pins[] = {34, 35};
static const unsigned int can0_7_pins[] = {38, 39};
static const unsigned int can0_8_pins[] = {42, 43};
static const unsigned int can0_9_pins[] = {46, 47};
static const unsigned int can0_10_pins[] = {50, 51};
static const unsigned int can1_0_pins[] = {8, 9};
static const unsigned int can1_1_pins[] = {12, 13};
static const unsigned int can1_2_pins[] = {16, 17};
static const unsigned int can1_3_pins[] = {20, 21};
static const unsigned int can1_4_pins[] = {24, 25};
static const unsigned int can1_5_pins[] = {28, 29};
static const unsigned int can1_6_pins[] = {32, 33};
static const unsigned int can1_7_pins[] = {36, 37};
static const unsigned int can1_8_pins[] = {40, 41};
static const unsigned int can1_9_pins[] = {44, 45};
static const unsigned int can1_10_pins[] = {48, 49};
static const unsigned int can1_11_pins[] = {52, 53};
static const unsigned int uart0_0_pins[] = {10, 11};
static const unsigned int uart0_1_pins[] = {14, 15};
static const unsigned int uart0_2_pins[] = {18, 19};
static const unsigned int uart0_3_pins[] = {22, 23};
static const unsigned int uart0_4_pins[] = {26, 27};
static const unsigned int uart0_5_pins[] = {30, 31};
static const unsigned int uart0_6_pins[] = {34, 35};
static const unsigned int uart0_7_pins[] = {38, 39};
static const unsigned int uart0_8_pins[] = {42, 43};
static const unsigned int uart0_9_pins[] = {46, 47};
static const unsigned int uart0_10_pins[] = {50, 51};
static const unsigned int uart1_0_pins[] = {8, 9};
static const unsigned int uart1_1_pins[] = {12, 13};
static const unsigned int uart1_2_pins[] = {16, 17};
static const unsigned int uart1_3_pins[] = {20, 21};
static const unsigned int uart1_4_pins[] = {24, 25};
static const unsigned int uart1_5_pins[] = {28, 29};
static const unsigned int uart1_6_pins[] = {32, 33};
static const unsigned int uart1_7_pins[] = {36, 37};
static const unsigned int uart1_8_pins[] = {40, 41};
static const unsigned int uart1_9_pins[] = {44, 45};
static const unsigned int uart1_10_pins[] = {48, 49};
static const unsigned int uart1_11_pins[] = {52, 53};
static const unsigned int i2c0_0_pins[] = {10, 11};
static const unsigned int i2c0_1_pins[] = {14, 15};
static const unsigned int i2c0_2_pins[] = {18, 19};
static const unsigned int i2c0_3_pins[] = {22, 23};
static const unsigned int i2c0_4_pins[] = {26, 27};
static const unsigned int i2c0_5_pins[] = {30, 31};
static const unsigned int i2c0_6_pins[] = {34, 35};
static const unsigned int i2c0_7_pins[] = {38, 39};
static const unsigned int i2c0_8_pins[] = {42, 43};
static const unsigned int i2c0_9_pins[] = {46, 47};
static const unsigned int i2c0_10_pins[] = {50, 51};
static const unsigned int i2c1_0_pins[] = {12, 13};
static const unsigned int i2c1_1_pins[] = {16, 17};
static const unsigned int i2c1_2_pins[] = {20, 21};
static const unsigned int i2c1_3_pins[] = {24, 25};
static const unsigned int i2c1_4_pins[] = {28, 29};
static const unsigned int i2c1_5_pins[] = {32, 33};
static const unsigned int i2c1_6_pins[] = {36, 37};
static const unsigned int i2c1_7_pins[] = {40, 41};
static const unsigned int i2c1_8_pins[] = {44, 45};
static const unsigned int i2c1_9_pins[] = {48, 49};
static const unsigned int i2c1_10_pins[] = {52, 53};
static const unsigned int ttc0_0_pins[] = {18, 19};
static const unsigned int ttc0_1_pins[] = {30, 31};
static const unsigned int ttc0_2_pins[] = {42, 43};
static const unsigned int ttc1_0_pins[] = {16, 17};
static const unsigned int ttc1_1_pins[] = {28, 29};
static const unsigned int ttc1_2_pins[] = {40, 41};
static const unsigned int swdt0_0_pins[] = {14, 15};
static const unsigned int swdt0_1_pins[] = {26, 27};
static const unsigned int swdt0_2_pins[] = {38, 39};
static const unsigned int swdt0_3_pins[] = {50, 51};
static const unsigned int swdt0_4_pins[] = {52, 53};
static const unsigned int gpio0_0_pins[] = {0};
static const unsigned int gpio0_1_pins[] = {1};
static const unsigned int gpio0_2_pins[] = {2};
static const unsigned int gpio0_3_pins[] = {3};
static const unsigned int gpio0_4_pins[] = {4};
static const unsigned int gpio0_5_pins[] = {5};
static const unsigned int gpio0_6_pins[] = {6};
static const unsigned int gpio0_7_pins[] = {7};
static const unsigned int gpio0_8_pins[] = {8};
static const unsigned int gpio0_9_pins[] = {9};
static const unsigned int gpio0_10_pins[] = {10};
static const unsigned int gpio0_11_pins[] = {11};
static const unsigned int gpio0_12_pins[] = {12};
static const unsigned int gpio0_13_pins[] = {13};
static const unsigned int gpio0_14_pins[] = {14};
static const unsigned int gpio0_15_pins[] = {15};
static const unsigned int gpio0_16_pins[] = {16};
static const unsigned int gpio0_17_pins[] = {17};
static const unsigned int gpio0_18_pins[] = {18};
static const unsigned int gpio0_19_pins[] = {19};
static const unsigned int gpio0_20_pins[] = {20};
static const unsigned int gpio0_21_pins[] = {21};
static const unsigned int gpio0_22_pins[] = {22};
static const unsigned int gpio0_23_pins[] = {23};
static const unsigned int gpio0_24_pins[] = {24};
static const unsigned int gpio0_25_pins[] = {25};
static const unsigned int gpio0_26_pins[] = {26};
static const unsigned int gpio0_27_pins[] = {27};
static const unsigned int gpio0_28_pins[] = {28};
static const unsigned int gpio0_29_pins[] = {29};
static const unsigned int gpio0_30_pins[] = {30};
static const unsigned int gpio0_31_pins[] = {31};
static const unsigned int gpio0_32_pins[] = {32};
static const unsigned int gpio0_33_pins[] = {33};
static const unsigned int gpio0_34_pins[] = {34};
static const unsigned int gpio0_35_pins[] = {35};
static const unsigned int gpio0_36_pins[] = {36};
static const unsigned int gpio0_37_pins[] = {37};
static const unsigned int gpio0_38_pins[] = {38};
static const unsigned int gpio0_39_pins[] = {39};
static const unsigned int gpio0_40_pins[] = {40};
static const unsigned int gpio0_41_pins[] = {41};
static const unsigned int gpio0_42_pins[] = {42};
static const unsigned int gpio0_43_pins[] = {43};
static const unsigned int gpio0_44_pins[] = {44};
static const unsigned int gpio0_45_pins[] = {45};
static const unsigned int gpio0_46_pins[] = {46};
static const unsigned int gpio0_47_pins[] = {47};
static const unsigned int gpio0_48_pins[] = {48};
static const unsigned int gpio0_49_pins[] = {49};
static const unsigned int gpio0_50_pins[] = {50};
static const unsigned int gpio0_51_pins[] = {51};
static const unsigned int gpio0_52_pins[] = {52};
static const unsigned int gpio0_53_pins[] = {53};
static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
37, 38, 39};
static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
49, 50, 51};
#define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
{ \
.name = #nm "_grp", \
.pins = nm ## _pins, \
.npins = ARRAY_SIZE(nm ## _pins), \
}
static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
};
/* function groups */
static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
static const char * const usb0_groups[] = {"usb0_0_grp"};
static const char * const usb1_groups[] = {"usb1_0_grp"};
static const char * const mdio0_groups[] = {"mdio0_0_grp"};
static const char * const mdio1_groups[] = {"mdio1_0_grp"};
static const char * const qspi0_groups[] = {"qspi0_0_grp"};
static const char * const qspi1_groups[] = {"qspi1_0_grp"};
static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
"spi0_2_grp"};
static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
"spi1_2_grp", "spi1_3_grp"};
static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
"spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
"spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
"spi0_2_ss1_grp", "spi0_2_ss2_grp"};
static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
"spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
"spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
"spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
"spi1_3_ss1_grp", "spi1_3_ss2_grp"};
static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
"sdio0_2_grp"};
static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
"sdio1_2_grp", "sdio1_3_grp"};
static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp"};
static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp"};
static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
"smc0_nand8_grp"};
static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
"can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
"can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
"can0_10_grp"};
static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
"can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
"can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
"can1_10_grp", "can1_11_grp"};
static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
"uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
"uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
"uart0_10_grp"};
static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
"uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
"uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
"uart1_10_grp", "uart1_11_grp"};
static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
"i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
"i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
"i2c0_10_grp"};
static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
"i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
"i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
"i2c1_10_grp"};
static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
"ttc0_2_grp"};
static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
"ttc1_2_grp"};
static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
"swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
static const char * const gpio0_groups[] = {"gpio0_0_grp",
"gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
"gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
"gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
"gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
"gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
"gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
"gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
"gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
"gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
"gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
"gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
"gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
"gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
"gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
"gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
"gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
"gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
"gpio0_51_grp", "gpio0_53_grp"};
#define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
[ZYNQ_PMUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
.mux_val = mval, \
}
#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
[ZYNQ_PMUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
.mux_val = mval, \
.mux = offset, \
.mux_mask = mask, \
.mux_shift = shift, \
}
#define ZYNQ_SDIO_WP_SHIFT 0
#define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
#define ZYNQ_SDIO_CD_SHIFT 16
#define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
static const struct zynq_pinmux_function zynq_pmux_functions[] = {
DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
};
/* pinctrl */
static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->ngroups;
}
static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->groups[selector].name;
}
static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->groups[selector].pins;
*num_pins = pctrl->groups[selector].npins;
return 0;
}
static const struct pinctrl_ops zynq_pctrl_ops = {
.get_groups_count = zynq_pctrl_get_groups_count,
.get_group_name = zynq_pctrl_get_group_name,
.get_group_pins = zynq_pctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
/* pinmux */
static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->nfuncs;
}
static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->funcs[selector].name;
}
static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->funcs[selector].groups;
*num_groups = pctrl->funcs[selector].ngroups;
return 0;
}
static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
int i, ret;
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
const struct zynq_pinmux_function *func = &pctrl->funcs[function];
/*
* SD WP & CD are special. They have dedicated registers
* to mux them in
*/
if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
function == ZYNQ_PMUX_sdio1_cd ||
function == ZYNQ_PMUX_sdio1_wp) {
u32 reg;
ret = regmap_read(pctrl->syscon,
pctrl->pctrl_offset + func->mux, ®);
if (ret)
return ret;
reg &= ~func->mux_mask;
reg |= pgrp->pins[0] << func->mux_shift;
ret = regmap_write(pctrl->syscon,
pctrl->pctrl_offset + func->mux, reg);
if (ret)
return ret;
} else {
for (i = 0; i < pgrp->npins; i++) {
unsigned int pin = pgrp->pins[i];
u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
ret = regmap_read(pctrl->syscon, addr, ®);
if (ret)
return ret;
reg &= ~ZYNQ_PINMUX_MUX_MASK;
reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
ret = regmap_write(pctrl->syscon, addr, reg);
if (ret)
return ret;
}
}
return 0;
}
static const struct pinmux_ops zynq_pinmux_ops = {
.get_functions_count = zynq_pmux_get_functions_count,
.get_function_name = zynq_pmux_get_function_name,
.get_function_groups = zynq_pmux_get_function_groups,
.set_mux = zynq_pinmux_set_mux,
};
/* pinconfig */
#define ZYNQ_PINCONF_TRISTATE BIT(0)
#define ZYNQ_PINCONF_SPEED BIT(8)
#define ZYNQ_PINCONF_PULLUP BIT(12)
#define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
#define ZYNQ_PINCONF_IOTYPE_SHIFT 9
#define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
enum zynq_io_standards {
zynq_iostd_min,
zynq_iostd_lvcmos18,
zynq_iostd_lvcmos25,
zynq_iostd_lvcmos33,
zynq_iostd_hstl,
zynq_iostd_max
};
/*
* PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
* this parameter (on a custom format) tells the driver which alternative
* IO standard to use.
*/
#define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params zynq_dt_params[] = {
{"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
= { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
};
#endif
static unsigned int zynq_pinconf_iostd_get(u32 reg)
{
return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
}
static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *config)
{
u32 reg;
int ret;
unsigned int arg = 0;
unsigned int param = pinconf_to_config_param(*config);
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
if (pin >= ZYNQ_NUM_MIOS)
return -ENOTSUPP;
ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
if (ret)
return -EIO;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
if (!(reg & ZYNQ_PINCONF_PULLUP))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
if (!(reg & ZYNQ_PINCONF_TRISTATE))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
return -EINVAL;
break;
case PIN_CONFIG_SLEW_RATE:
arg = !!(reg & ZYNQ_PINCONF_SPEED);
break;
case PIN_CONFIG_MODE_LOW_POWER:
{
enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
if (iostd != zynq_iostd_hstl)
return -EINVAL;
if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
return -EINVAL;
arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
break;
}
case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
arg = zynq_pinconf_iostd_get(reg);
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
u32 reg;
u32 pullup = 0;
u32 tristate = 0;
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
if (pin >= ZYNQ_NUM_MIOS)
return -ENOTSUPP;
ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
if (ret)
return -EIO;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
pullup = ZYNQ_PINCONF_PULLUP;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
tristate = ZYNQ_PINCONF_TRISTATE;
break;
case PIN_CONFIG_BIAS_DISABLE:
reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
break;
case PIN_CONFIG_SLEW_RATE:
if (arg)
reg |= ZYNQ_PINCONF_SPEED;
else
reg &= ~ZYNQ_PINCONF_SPEED;
break;
case PIN_CONFIG_IOSTANDARD:
case PIN_CONFIG_POWER_SOURCE:
if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
dev_warn(pctldev->dev,
"unsupported IO standard '%u'\n",
param);
break;
}
reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
break;
case PIN_CONFIG_MODE_LOW_POWER:
if (arg)
reg |= ZYNQ_PINCONF_DISABLE_RECVR;
else
reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter '%u'\n",
param);
continue;
}
}
if (tristate || pullup) {
reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
reg |= tristate | pullup;
}
ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
if (ret)
return -EIO;
return 0;
}
static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
for (i = 0; i < pgrp->npins; i++) {
ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops zynq_pinconf_ops = {
.is_generic = true,
.pin_config_get = zynq_pinconf_cfg_get,
.pin_config_set = zynq_pinconf_cfg_set,
.pin_config_group_set = zynq_pinconf_group_set,
};
static struct pinctrl_desc zynq_desc = {
.name = "zynq_pinctrl",
.pins = zynq_pins,
.npins = ARRAY_SIZE(zynq_pins),
.pctlops = &zynq_pctrl_ops,
.pmxops = &zynq_pinmux_ops,
.confops = &zynq_pinconf_ops,
.num_custom_params = ARRAY_SIZE(zynq_dt_params),
.custom_params = zynq_dt_params,
#ifdef CONFIG_DEBUG_FS
.custom_conf_items = zynq_conf_items,
#endif
.owner = THIS_MODULE,
};
static int zynq_pinctrl_probe(struct platform_device *pdev)
{
struct resource *res;
struct zynq_pinctrl *pctrl;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"syscon");
if (IS_ERR(pctrl->syscon)) {
dev_err(&pdev->dev, "unable to get syscon\n");
return PTR_ERR(pctrl->syscon);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENODEV;
}
pctrl->pctrl_offset = res->start;
pctrl->groups = zynq_pctrl_groups;
pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
pctrl->funcs = zynq_pmux_functions;
pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
platform_set_drvdata(pdev, pctrl);
dev_info(&pdev->dev, "zynq pinctrl initialized\n");
return 0;
}
static const struct of_device_id zynq_pinctrl_of_match[] = {
{ .compatible = "xlnx,pinctrl-zynq" },
{ }
};
static struct platform_driver zynq_pinctrl_driver = {
.driver = {
.name = "zynq-pinctrl",
.of_match_table = zynq_pinctrl_of_match,
},
.probe = zynq_pinctrl_probe,
};
module_platform_driver(zynq_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/pinctrl-zynq.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Microsemi/Microchip SoCs serial gpio driver
*
* Author: Lars Povlsen <[email protected]>
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/mfd/ocelot.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#define SGPIO_BITS_PER_WORD 32
#define SGPIO_MAX_BITS 4
#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
enum {
REG_INPUT_DATA,
REG_PORT_CONFIG,
REG_PORT_ENABLE,
REG_SIO_CONFIG,
REG_SIO_CLOCK,
REG_INT_POLARITY,
REG_INT_TRIGGER,
REG_INT_ACK,
REG_INT_ENABLE,
REG_INT_IDENT,
MAXREG
};
enum {
SGPIO_ARCH_LUTON,
SGPIO_ARCH_OCELOT,
SGPIO_ARCH_SPARX5,
};
enum {
SGPIO_FLAGS_HAS_IRQ = BIT(0),
};
struct sgpio_properties {
int arch;
int flags;
u8 regoff[MAXREG];
};
#define SGPIO_LUTON_AUTO_REPEAT BIT(5)
#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
#define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
#define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
#define SGPIO_MASTER_INTR_ENA BIT(0)
#define SGPIO_INT_TRG_LEVEL 0
#define SGPIO_INT_TRG_EDGE 1
#define SGPIO_INT_TRG_EDGE_FALL 2
#define SGPIO_INT_TRG_EDGE_RISE 3
#define SGPIO_TRG_LEVEL_HIGH 0
#define SGPIO_TRG_LEVEL_LOW 1
static const struct sgpio_properties properties_luton = {
.arch = SGPIO_ARCH_LUTON,
.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
};
static const struct sgpio_properties properties_ocelot = {
.arch = SGPIO_ARCH_OCELOT,
.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
};
static const struct sgpio_properties properties_sparx5 = {
.arch = SGPIO_ARCH_SPARX5,
.flags = SGPIO_FLAGS_HAS_IRQ,
.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
};
static const char * const functions[] = { "gpio" };
struct sgpio_bank {
struct sgpio_priv *priv;
bool is_input;
struct gpio_chip gpio;
struct pinctrl_desc pctl_desc;
};
struct sgpio_priv {
struct device *dev;
struct sgpio_bank in;
struct sgpio_bank out;
u32 bitcount;
u32 ports;
u32 clock;
struct regmap *regs;
const struct sgpio_properties *properties;
spinlock_t lock;
/* protects the config register and single shot mode */
struct mutex poll_lock;
};
struct sgpio_port_addr {
u8 port;
u8 bit;
};
static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
struct sgpio_port_addr *addr)
{
addr->port = pin / priv->bitcount;
addr->bit = pin % priv->bitcount;
}
static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
{
return bit + port * priv->bitcount;
}
static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
{
return (priv->properties->regoff[rno] + off) *
regmap_get_reg_stride(priv->regs);
}
static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
{
u32 addr = sgpio_get_addr(priv, rno, off);
u32 val = 0;
int ret;
ret = regmap_read(priv->regs, addr, &val);
WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
return val;
}
static void sgpio_writel(struct sgpio_priv *priv,
u32 val, u32 rno, u32 off)
{
u32 addr = sgpio_get_addr(priv, rno, off);
int ret;
ret = regmap_write(priv->regs, addr, val);
WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
}
static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
u32 rno, u32 off, u32 clear, u32 set)
{
u32 addr = sgpio_get_addr(priv, rno, off);
int ret;
ret = regmap_update_bits(priv->regs, addr, clear | set, set);
WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
}
static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
{
int width = priv->bitcount - 1;
u32 clr, set;
switch (priv->properties->arch) {
case SGPIO_ARCH_LUTON:
clr = SGPIO_LUTON_PORT_WIDTH;
set = SGPIO_LUTON_AUTO_REPEAT |
FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
break;
case SGPIO_ARCH_OCELOT:
clr = SGPIO_OCELOT_PORT_WIDTH;
set = SGPIO_OCELOT_AUTO_REPEAT |
FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
break;
case SGPIO_ARCH_SPARX5:
clr = SGPIO_SPARX5_PORT_WIDTH;
set = SGPIO_SPARX5_AUTO_REPEAT |
FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
break;
default:
return;
}
sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
}
static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
{
u32 clr, set;
switch (priv->properties->arch) {
case SGPIO_ARCH_LUTON:
clr = SGPIO_LUTON_CLK_FREQ;
set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
break;
case SGPIO_ARCH_OCELOT:
clr = SGPIO_OCELOT_CLK_FREQ;
set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
break;
case SGPIO_ARCH_SPARX5:
clr = SGPIO_SPARX5_CLK_FREQ;
set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
break;
default:
return;
}
sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
}
static int sgpio_single_shot(struct sgpio_priv *priv)
{
u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
int ret, ret2;
u32 ctrl;
unsigned int single_shot;
unsigned int auto_repeat;
switch (priv->properties->arch) {
case SGPIO_ARCH_LUTON:
/* not supported for now */
return 0;
case SGPIO_ARCH_OCELOT:
single_shot = SGPIO_OCELOT_SINGLE_SHOT;
auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
break;
case SGPIO_ARCH_SPARX5:
single_shot = SGPIO_SPARX5_SINGLE_SHOT;
auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
break;
default:
return -EINVAL;
}
/*
* Trigger immediate burst. This only works when auto repeat is turned
* off. Otherwise, the single shot bit will never be cleared by the
* hardware. Measurements showed that an update might take as long as
* the burst gap. On a LAN9668 this is about 50ms for the largest
* setting.
* After the manual burst, reenable the auto repeat mode again.
*/
mutex_lock(&priv->poll_lock);
ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
single_shot);
if (ret)
goto out;
ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
!(ctrl & single_shot), 100, 60000);
/* reenable auto repeat mode even if there was an error */
ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
out:
mutex_unlock(&priv->poll_lock);
return ret ?: ret2;
}
static int sgpio_output_set(struct sgpio_priv *priv,
struct sgpio_port_addr *addr,
int value)
{
unsigned int bit = SGPIO_SRC_BITS * addr->bit;
u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
bool changed;
u32 clr, set;
int ret;
switch (priv->properties->arch) {
case SGPIO_ARCH_LUTON:
clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
break;
case SGPIO_ARCH_OCELOT:
clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
break;
case SGPIO_ARCH_SPARX5:
clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
break;
default:
return -EINVAL;
}
ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
&changed);
if (ret)
return ret;
if (changed) {
ret = sgpio_single_shot(priv);
if (ret)
return ret;
}
return 0;
}
static int sgpio_output_get(struct sgpio_priv *priv,
struct sgpio_port_addr *addr)
{
u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
unsigned int bit = SGPIO_SRC_BITS * addr->bit;
switch (priv->properties->arch) {
case SGPIO_ARCH_LUTON:
val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
break;
case SGPIO_ARCH_OCELOT:
val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
break;
case SGPIO_ARCH_SPARX5:
val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
break;
default:
val = 0;
break;
}
return !!(val & BIT(bit));
}
static int sgpio_input_get(struct sgpio_priv *priv,
struct sgpio_port_addr *addr)
{
return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
}
static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
struct sgpio_priv *priv = bank->priv;
struct sgpio_port_addr addr;
int val;
sgpio_pin_to_addr(priv, pin, &addr);
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
val = bank->is_input;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
val = !bank->is_input;
break;
case PIN_CONFIG_OUTPUT:
if (bank->is_input)
return -EINVAL;
val = sgpio_output_get(priv, &addr);
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, val);
return 0;
}
static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
struct sgpio_priv *priv = bank->priv;
struct sgpio_port_addr addr;
int cfg, err = 0;
u32 param, arg;
sgpio_pin_to_addr(priv, pin, &addr);
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_OUTPUT:
if (bank->is_input)
return -EINVAL;
err = sgpio_output_set(priv, &addr, arg);
break;
default:
err = -ENOTSUPP;
}
}
return err;
}
static const struct pinconf_ops sgpio_confops = {
.is_generic = true,
.pin_config_get = sgpio_pinconf_get,
.pin_config_set = sgpio_pinconf_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
{
return 1;
}
static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return functions[0];
}
static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char *const **groups,
unsigned *const num_groups)
{
*groups = functions;
*num_groups = ARRAY_SIZE(functions);
return 0;
}
static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
return 0;
}
static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
return (input == bank->is_input) ? 0 : -EINVAL;
}
static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
struct sgpio_priv *priv = bank->priv;
struct sgpio_port_addr addr;
sgpio_pin_to_addr(priv, offset, &addr);
if ((priv->ports & BIT(addr.port)) == 0) {
dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
addr.port, addr.bit);
return -EINVAL;
}
return 0;
}
static const struct pinmux_ops sgpio_pmx_ops = {
.get_functions_count = sgpio_get_functions_count,
.get_function_name = sgpio_get_function_name,
.get_function_groups = sgpio_get_function_groups,
.set_mux = sgpio_pinmux_set_mux,
.gpio_set_direction = sgpio_gpio_set_direction,
.gpio_request_enable = sgpio_gpio_request_enable,
};
static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
return bank->pctl_desc.npins;
}
static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
return bank->pctl_desc.pins[group].name;
}
static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
*pins = &bank->pctl_desc.pins[group].number;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops sgpio_pctl_ops = {
.get_groups_count = sgpio_pctl_get_groups_count,
.get_group_name = sgpio_pctl_get_group_name,
.get_group_pins = sgpio_pctl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
{
struct sgpio_bank *bank = gpiochip_get_data(gc);
/* Fixed-position function */
return bank->is_input ? 0 : -EINVAL;
}
static int microchip_sgpio_direction_output(struct gpio_chip *gc,
unsigned int gpio, int value)
{
struct sgpio_bank *bank = gpiochip_get_data(gc);
struct sgpio_priv *priv = bank->priv;
struct sgpio_port_addr addr;
/* Fixed-position function */
if (bank->is_input)
return -EINVAL;
sgpio_pin_to_addr(priv, gpio, &addr);
return sgpio_output_set(priv, &addr, value);
}
static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
struct sgpio_bank *bank = gpiochip_get_data(gc);
return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
}
static void microchip_sgpio_set_value(struct gpio_chip *gc,
unsigned int gpio, int value)
{
microchip_sgpio_direction_output(gc, gpio, value);
}
static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
{
struct sgpio_bank *bank = gpiochip_get_data(gc);
struct sgpio_priv *priv = bank->priv;
struct sgpio_port_addr addr;
sgpio_pin_to_addr(priv, gpio, &addr);
return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
}
static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
const struct of_phandle_args *gpiospec,
u32 *flags)
{
struct sgpio_bank *bank = gpiochip_get_data(gc);
struct sgpio_priv *priv = bank->priv;
int pin;
/*
* Note that the SGIO pin is defined by *2* numbers, a port
* number between 0 and 31, and a bit index, 0 to 3.
*/
if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
gpiospec->args[1] > priv->bitcount)
return -EINVAL;
pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
if (pin > gc->ngpio)
return -EINVAL;
if (flags)
*flags = gpiospec->args[2];
return pin;
}
static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
{
const char *range_property_name = "microchip,sgpio-port-ranges";
struct device *dev = priv->dev;
u32 range_params[64];
int i, nranges, ret;
/* Calculate port mask */
nranges = device_property_count_u32(dev, range_property_name);
if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
dev_err(dev, "%s port range: '%s' property\n",
nranges == -EINVAL ? "Missing" : "Invalid",
range_property_name);
return -EINVAL;
}
ret = device_property_read_u32_array(dev, range_property_name,
range_params, nranges);
if (ret) {
dev_err(dev, "failed to parse '%s' property: %d\n",
range_property_name, ret);
return ret;
}
for (i = 0; i < nranges; i += 2) {
int start, end;
start = range_params[i];
end = range_params[i + 1];
if (start > end || end >= SGPIO_BITS_PER_WORD) {
dev_err(dev, "Ill-formed port-range [%d:%d]\n",
start, end);
}
priv->ports |= GENMASK(end, start);
}
return 0;
}
static void microchip_sgpio_irq_settype(struct irq_data *data,
int type,
int polarity)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sgpio_bank *bank = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
struct sgpio_port_addr addr;
unsigned long flags;
u32 ena;
sgpio_pin_to_addr(bank->priv, gpio, &addr);
spin_lock_irqsave(&bank->priv->lock, flags);
/* Disable interrupt while changing type */
ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
/* Type value spread over 2 registers sets: low, high bit */
sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
BIT(addr.port), (!!(type & 0x1)) << addr.port);
sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
BIT(addr.port), (!!(type & 0x2)) << addr.port);
if (type == SGPIO_INT_TRG_LEVEL)
sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
BIT(addr.port), polarity << addr.port);
/* Possibly re-enable interrupts */
sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
spin_unlock_irqrestore(&bank->priv->lock, flags);
}
static void microchip_sgpio_irq_setreg(struct irq_data *data,
int reg,
bool clear)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sgpio_bank *bank = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
struct sgpio_port_addr addr;
sgpio_pin_to_addr(bank->priv, gpio, &addr);
if (clear)
sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
else
sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
}
static void microchip_sgpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
gpiochip_disable_irq(chip, data->hwirq);
}
static void microchip_sgpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
gpiochip_enable_irq(chip, data->hwirq);
microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
}
static void microchip_sgpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sgpio_bank *bank = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
struct sgpio_port_addr addr;
sgpio_pin_to_addr(bank->priv, gpio, &addr);
sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
}
static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
irq_set_handler_locked(data, handle_edge_irq);
microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
break;
case IRQ_TYPE_EDGE_RISING:
irq_set_handler_locked(data, handle_edge_irq);
microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
break;
case IRQ_TYPE_EDGE_FALLING:
irq_set_handler_locked(data, handle_edge_irq);
microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_set_handler_locked(data, handle_level_irq);
microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
break;
case IRQ_TYPE_LEVEL_LOW:
irq_set_handler_locked(data, handle_level_irq);
microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct irq_chip microchip_sgpio_irqchip = {
.name = "gpio",
.irq_mask = microchip_sgpio_irq_mask,
.irq_ack = microchip_sgpio_irq_ack,
.irq_unmask = microchip_sgpio_irq_unmask,
.irq_set_type = microchip_sgpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void sgpio_irq_handler(struct irq_desc *desc)
{
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct sgpio_bank *bank = gpiochip_get_data(chip);
struct sgpio_priv *priv = bank->priv;
int bit, port, gpio;
long val;
for (bit = 0; bit < priv->bitcount; bit++) {
val = sgpio_readl(priv, REG_INT_IDENT, bit);
if (!val)
continue;
chained_irq_enter(parent_chip, desc);
for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
gpio = sgpio_addr_to_pin(priv, port, bit);
generic_handle_domain_irq(chip->irq.domain, gpio);
}
chained_irq_exit(parent_chip, desc);
}
}
static int microchip_sgpio_register_bank(struct device *dev,
struct sgpio_priv *priv,
struct fwnode_handle *fwnode,
int bankno)
{
struct pinctrl_pin_desc *pins;
struct pinctrl_desc *pctl_desc;
struct pinctrl_dev *pctldev;
struct sgpio_bank *bank;
struct gpio_chip *gc;
u32 ngpios;
int i, ret;
/* Get overall bank struct */
bank = (bankno == 0) ? &priv->in : &priv->out;
bank->priv = priv;
if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
dev_info(dev, "failed to get number of gpios for bank%d\n",
bankno);
ngpios = 64;
}
priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
if (priv->bitcount > SGPIO_MAX_BITS) {
dev_err(dev, "Bit width exceeds maximum (%d)\n",
SGPIO_MAX_BITS);
return -EINVAL;
}
pctl_desc = &bank->pctl_desc;
pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
dev_name(dev),
bank->is_input ? "in" : "out");
if (!pctl_desc->name)
return -ENOMEM;
pctl_desc->pctlops = &sgpio_pctl_ops;
pctl_desc->pmxops = &sgpio_pmx_ops;
pctl_desc->confops = &sgpio_confops;
pctl_desc->owner = THIS_MODULE;
pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
if (!pins)
return -ENOMEM;
pctl_desc->npins = ngpios;
pctl_desc->pins = pins;
for (i = 0; i < ngpios; i++) {
struct sgpio_port_addr addr;
sgpio_pin_to_addr(priv, i, &addr);
pins[i].number = i;
pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
"SGPIO_%c_p%db%d",
bank->is_input ? 'I' : 'O',
addr.port, addr.bit);
if (!pins[i].name)
return -ENOMEM;
}
pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
if (IS_ERR(pctldev))
return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
gc = &bank->gpio;
gc->label = pctl_desc->name;
gc->parent = dev;
gc->fwnode = fwnode;
gc->owner = THIS_MODULE;
gc->get_direction = microchip_sgpio_get_direction;
gc->direction_input = microchip_sgpio_direction_input;
gc->direction_output = microchip_sgpio_direction_output;
gc->get = microchip_sgpio_get_value;
gc->set = microchip_sgpio_set_value;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->of_xlate = microchip_sgpio_of_xlate;
gc->of_gpio_n_cells = 3;
gc->base = -1;
gc->ngpio = ngpios;
gc->can_sleep = !bank->is_input;
if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
int irq;
irq = fwnode_irq_get(fwnode, 0);
if (irq > 0) {
struct gpio_irq_chip *girq = &gc->irq;
gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip);
girq->parent_handler = sgpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
/* Disable all individual pins */
for (i = 0; i < SGPIO_MAX_BITS; i++)
sgpio_writel(priv, 0, REG_INT_ENABLE, i);
/* Master enable */
sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
}
}
ret = devm_gpiochip_add_data(dev, gc, bank);
if (ret)
dev_err(dev, "Failed to register: ret %d\n", ret);
return ret;
}
static int microchip_sgpio_probe(struct platform_device *pdev)
{
int div_clock = 0, ret, port, i, nbanks;
struct device *dev = &pdev->dev;
struct fwnode_handle *fwnode;
struct reset_control *reset;
struct sgpio_priv *priv;
struct clk *clk;
u32 val;
struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
spin_lock_init(&priv->lock);
mutex_init(&priv->poll_lock);
reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
if (IS_ERR(reset))
return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
reset_control_reset(reset);
clk = devm_clk_get(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
div_clock = clk_get_rate(clk);
if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
priv->clock = 12500000;
if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
dev_err(dev, "Invalid frequency %d\n", priv->clock);
return -EINVAL;
}
priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
priv->properties = device_get_match_data(dev);
priv->in.is_input = true;
/* Get rest of device properties */
ret = microchip_sgpio_get_ports(priv);
if (ret)
return ret;
nbanks = device_get_child_node_count(dev);
if (nbanks != 2) {
dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
return -EINVAL;
}
i = 0;
device_for_each_child_node(dev, fwnode) {
ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
if (ret) {
fwnode_handle_put(fwnode);
return ret;
}
}
if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
dev_err(dev, "Banks must have same GPIO count\n");
return -ERANGE;
}
sgpio_configure_bitstream(priv);
val = max(2U, div_clock / priv->clock);
sgpio_configure_clock(priv, val);
for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
return 0;
}
static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
{
.compatible = "microchip,sparx5-sgpio",
.data = &properties_sparx5,
}, {
.compatible = "mscc,luton-sgpio",
.data = &properties_luton,
}, {
.compatible = "mscc,ocelot-sgpio",
.data = &properties_ocelot,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
static struct platform_driver microchip_sgpio_pinctrl_driver = {
.driver = {
.name = "pinctrl-microchip-sgpio",
.of_match_table = microchip_sgpio_gpio_of_match,
.suppress_bind_attrs = true,
},
.probe = microchip_sgpio_probe,
};
module_platform_driver(microchip_sgpio_pinctrl_driver);
MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-microchip-sgpio.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* GPIO driver for AMD
*
* Copyright (c) 2014,2015 AMD Corporation.
* Authors: Ken Xue <[email protected]>
* Wu, Jeff <[email protected]>
*
*/
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/acpi.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/bitops.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/suspend.h>
#include "core.h"
#include "pinctrl-utils.h"
#include "pinctrl-amd.h"
static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
u32 pin_reg;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
u32 pin_reg;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
}
static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
u32 pin_reg;
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg |= BIT(OUTPUT_ENABLE_OFF);
if (value)
pin_reg |= BIT(OUTPUT_VALUE_OFF);
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0;
}
static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
{
u32 pin_reg;
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return !!(pin_reg & BIT(PIN_STS_OFF));
}
static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
u32 pin_reg;
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
if (value)
pin_reg |= BIT(OUTPUT_VALUE_OFF);
else
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
unsigned int debounce)
{
u32 time;
u32 pin_reg;
int ret = 0;
/* Use special handling for Pin0 debounce */
if (offset == 0) {
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
debounce = 0;
}
pin_reg = readl(gpio_dev->base + offset * 4);
if (debounce) {
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg &= ~DB_TMR_OUT_MASK;
/*
Debounce Debounce Timer Max
TmrLarge TmrOutUnit Unit Debounce
Time
0 0 61 usec (2 RtcClk) 976 usec
0 1 244 usec (8 RtcClk) 3.9 msec
1 0 15.6 msec (512 RtcClk) 250 msec
1 1 62.5 msec (2048 RtcClk) 1 sec
*/
if (debounce < 61) {
pin_reg |= 1;
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
} else if (debounce < 976) {
time = debounce / 61;
pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
} else if (debounce < 3900) {
time = debounce / 244;
pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
} else if (debounce < 250000) {
time = debounce / 15625;
pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= BIT(DB_TMR_LARGE_OFF);
} else if (debounce < 1000000) {
time = debounce / 62500;
pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= BIT(DB_TMR_LARGE_OFF);
} else {
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
ret = -EINVAL;
}
} else {
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg &= ~DB_TMR_OUT_MASK;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
u32 pin_reg;
u32 db_cntrl;
unsigned long flags;
unsigned int bank, i, pin_num;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
bool tmr_out_unit;
bool tmr_large;
char *level_trig;
char *active_level;
char *interrupt_mask;
char *wake_cntrl0;
char *wake_cntrl1;
char *wake_cntrl2;
char *pin_sts;
char *interrupt_sts;
char *wake_sts;
char *orientation;
char debounce_value[40];
char *debounce_enable;
char *wake_cntrlz;
seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
unsigned int time = 0;
unsigned int unit = 0;
switch (bank) {
case 0:
i = 0;
pin_num = AMD_GPIO_PINS_BANK0;
break;
case 1:
i = 64;
pin_num = AMD_GPIO_PINS_BANK1 + i;
break;
case 2:
i = 128;
pin_num = AMD_GPIO_PINS_BANK2 + i;
break;
case 3:
i = 192;
pin_num = AMD_GPIO_PINS_BANK3 + i;
break;
default:
/* Illegal bank number, ignore */
continue;
}
seq_printf(s, "GPIO bank%d\n", bank);
seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
for (; i < pin_num; i++) {
seq_printf(s, "#%d\t", i);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
ACTIVE_LEVEL_MASK;
if (level == ACTIVE_LEVEL_HIGH)
active_level = "↑";
else if (level == ACTIVE_LEVEL_LOW)
active_level = "↓";
else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
level == ACTIVE_LEVEL_BOTH)
active_level = "b";
else
active_level = "?";
if (pin_reg & BIT(LEVEL_TRIG_OFF))
level_trig = "level";
else
level_trig = " edge";
if (pin_reg & BIT(INTERRUPT_MASK_OFF))
interrupt_mask = "😛";
else
interrupt_mask = "😷";
if (pin_reg & BIT(INTERRUPT_STS_OFF))
interrupt_sts = "🔥";
else
interrupt_sts = " ";
seq_printf(s, "%s %s| %s| %s|",
interrupt_sts,
interrupt_mask,
active_level,
level_trig);
} else
seq_puts(s, " ∅| | |");
if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
wake_cntrl0 = "⏰";
else
wake_cntrl0 = " ";
seq_printf(s, " %s| ", wake_cntrl0);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
wake_cntrl1 = "⏰";
else
wake_cntrl1 = " ";
seq_printf(s, "%s|", wake_cntrl1);
if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
wake_cntrl2 = "⏰";
else
wake_cntrl2 = " ";
seq_printf(s, " %s|", wake_cntrl2);
if (pin_reg & BIT(WAKECNTRL_Z_OFF))
wake_cntrlz = "⏰";
else
wake_cntrlz = " ";
seq_printf(s, "%s|", wake_cntrlz);
if (pin_reg & BIT(WAKE_STS_OFF))
wake_sts = "🔥";
else
wake_sts = " ";
seq_printf(s, " %s|", wake_sts);
if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
seq_puts(s, " ↑ |");
} else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
seq_puts(s, " ↓ |");
} else {
seq_puts(s, " |");
}
if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
pin_sts = "output";
if (pin_reg & BIT(OUTPUT_VALUE_OFF))
orientation = "↑";
else
orientation = "↓";
} else {
pin_sts = "input ";
if (pin_reg & BIT(PIN_STS_OFF))
orientation = "↑";
else
orientation = "↓";
}
seq_printf(s, "%s %s|", pin_sts, orientation);
db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
if (db_cntrl) {
tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
time = pin_reg & DB_TMR_OUT_MASK;
if (tmr_large) {
if (tmr_out_unit)
unit = 62500;
else
unit = 15625;
} else {
if (tmr_out_unit)
unit = 244;
else
unit = 61;
}
if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
debounce_enable = "b";
else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
debounce_enable = "↓";
else
debounce_enable = "↑";
snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
seq_printf(s, "%s (🕑 %sus)|", debounce_enable, debounce_value);
} else {
seq_puts(s, " |");
}
seq_printf(s, "0x%x\n", pin_reg);
}
}
}
#else
#define amd_gpio_dbg_show NULL
#endif
static void amd_gpio_irq_enable(struct irq_data *d)
{
u32 pin_reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
gpiochip_enable_irq(gc, d->hwirq);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_disable(struct irq_data *d)
{
u32 pin_reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
gpiochip_disable_irq(gc, d->hwirq);
}
static void amd_gpio_irq_mask(struct irq_data *d)
{
u32 pin_reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_unmask(struct irq_data *d)
{
u32 pin_reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
u32 pin_reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
int err;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
if (on)
pin_reg |= wake_mask;
else
pin_reg &= ~wake_mask;
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (on)
err = enable_irq_wake(gpio_dev->irq);
else
err = disable_irq_wake(gpio_dev->irq);
if (err)
dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
on ? "enable" : "disable");
return 0;
}
static void amd_gpio_irq_eoi(struct irq_data *d)
{
u32 reg;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
reg |= EOI_MASK;
writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
int ret = 0;
u32 pin_reg, pin_reg_irq_en, mask;
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
case IRQ_TYPE_NONE:
break;
default:
dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
ret = -EINVAL;
}
pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
/*
* If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
* debounce registers of any GPIO will block wake/interrupt status
* generation for *all* GPIOs for a length of time that depends on
* WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
* INTERRUPT_ENABLE bit will read as 0.
*
* We temporarily enable irq for the GPIO whose configuration is
* changing, and then wait for it to read back as 1 to know when
* debounce has settled and then disable the irq again.
* We do this polling with the spinlock held to ensure other GPIO
* access routines do not read an incorrect value for the irq enable
* bit of other GPIOs. We keep the GPIO masked while polling to avoid
* spurious irqs, and disable the irq again after polling.
*/
mask = BIT(INTERRUPT_ENABLE_OFF);
pin_reg_irq_en = pin_reg;
pin_reg_irq_en |= mask;
pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
continue;
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
static void amd_irq_ack(struct irq_data *d)
{
/*
* based on HW design,there is no need to ack HW
* before handle current irq. But this routine is
* necessary for handle_edge_irq
*/
}
static const struct irq_chip amd_gpio_irqchip = {
.name = "amd_gpio",
.irq_ack = amd_irq_ack,
.irq_enable = amd_gpio_irq_enable,
.irq_disable = amd_gpio_irq_disable,
.irq_mask = amd_gpio_irq_mask,
.irq_unmask = amd_gpio_irq_unmask,
.irq_set_wake = amd_gpio_irq_set_wake,
.irq_eoi = amd_gpio_irq_eoi,
.irq_set_type = amd_gpio_irq_set_type,
/*
* We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
* also generates an IRQ. We need the IRQ so the irq_handler can clear
* the wake event. Otherwise the wake event will never clear and
* prevent the system from suspending.
*/
.flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
{
struct amd_gpio *gpio_dev = dev_id;
struct gpio_chip *gc = &gpio_dev->gc;
unsigned int i, irqnr;
unsigned long flags;
u32 __iomem *regs;
bool ret = false;
u32 regval;
u64 status, mask;
/* Read the wake status */
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
status <<= 32;
status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
/* Bit 0-45 contain the relevant status bits */
status &= (1ULL << 46) - 1;
regs = gpio_dev->base;
for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
if (!(status & mask))
continue;
status &= ~mask;
/* Each status bit covers four pins */
for (i = 0; i < 4; i++) {
regval = readl(regs + i);
if (regval & PIN_IRQ_PENDING)
pm_pr_dbg("GPIO %d is active: 0x%x",
irqnr + i, regval);
/* caused wake on resume context for shared IRQ */
if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
return true;
if (!(regval & PIN_IRQ_PENDING) ||
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
/* Clear interrupt.
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_domain_irq() above.
* If the line is not an irq, disable it in order to
* avoid a system hang caused by an interrupt storm.
*/
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(regs + i);
if (!gpiochip_line_is_irq(gc, irqnr + i)) {
regval &= ~BIT(INTERRUPT_MASK_OFF);
dev_dbg(&gpio_dev->pdev->dev,
"Disabling spurious GPIO IRQ %d\n",
irqnr + i);
} else {
ret = true;
}
writel(regval, regs + i);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
}
/* did not cause wake on resume context for shared IRQ */
if (irq < 0)
return false;
/* Signal EOI to the GPIO unit */
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
regval |= EOI_MASK;
writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
{
return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
}
static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
{
return do_amd_gpio_irq_handler(-1, dev_id);
}
static int amd_get_groups_count(struct pinctrl_dev *pctldev)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
return gpio_dev->ngroups;
}
static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
return gpio_dev->groups[group].name;
}
static int amd_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
*pins = gpio_dev->groups[group].pins;
*num_pins = gpio_dev->groups[group].npins;
return 0;
}
static const struct pinctrl_ops amd_pinctrl_ops = {
.get_groups_count = amd_get_groups_count,
.get_group_name = amd_get_group_name,
.get_group_pins = amd_get_group_pins,
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinctrl_utils_free_map,
#endif
};
static int amd_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *config)
{
u32 pin_reg;
unsigned arg;
unsigned long flags;
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin*4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
arg = pin_reg & DB_TMR_OUT_MASK;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
break;
default:
dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
param);
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
int i;
u32 arg;
int ret = 0;
u32 pin_reg;
unsigned long flags;
enum pin_config_param param;
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
pin_reg = readl(gpio_dev->base + pin*4);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
goto out_unlock;
case PIN_CONFIG_BIAS_PULL_DOWN:
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
break;
case PIN_CONFIG_BIAS_PULL_UP:
pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
pin_reg &= ~(DRV_STRENGTH_SEL_MASK
<< DRV_STRENGTH_SEL_OFF);
pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
<< DRV_STRENGTH_SEL_OFF;
break;
default:
dev_dbg(&gpio_dev->pdev->dev,
"Invalid config param %04x\n", param);
ret = -ENOTSUPP;
}
writel(pin_reg, gpio_dev->base + pin*4);
}
out_unlock:
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret;
}
static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
const unsigned *pins;
unsigned npins;
int ret;
ret = amd_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
if (amd_pinconf_get(pctldev, pins[0], config))
return -ENOTSUPP;
return 0;
}
static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
const unsigned *pins;
unsigned npins;
int i, ret;
ret = amd_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
return -ENOTSUPP;
}
return 0;
}
static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
unsigned long config)
{
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
}
static const struct pinconf_ops amd_pinconf_ops = {
.pin_config_get = amd_pinconf_get,
.pin_config_set = amd_pinconf_set,
.pin_config_group_get = amd_pinconf_group_get,
.pin_config_group_set = amd_pinconf_group_set,
};
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
{
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
u32 pin_reg, mask;
int i;
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
BIT(WAKE_CNTRL_OFF_S4);
for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number;
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
if (!pd)
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + pin * 4);
pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
}
#ifdef CONFIG_PM_SLEEP
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
{
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
if (!pd)
return false;
/*
* Only restore the pin if it is actually in use by the kernel (or
* by userspace).
*/
if (pd->mux_owner || pd->gpio_owner ||
gpiochip_line_is_irq(&gpio_dev->gc, pin))
return true;
return false;
}
static int amd_gpio_suspend(struct device *dev)
{
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
int i;
for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number;
if (!amd_gpio_should_save(gpio_dev, pin))
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
return 0;
}
static int amd_gpio_resume(struct device *dev)
{
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
int i;
for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number;
if (!amd_gpio_should_save(gpio_dev, pin))
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
return 0;
}
static const struct dev_pm_ops amd_gpio_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
amd_gpio_resume)
};
#endif
static int amd_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(pmx_functions);
}
static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
{
return pmx_functions[selector].name;
}
static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
if (!gpio_dev->iomux_base) {
dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
return -EINVAL;
}
*groups = pmx_functions[selector].groups;
*num_groups = pmx_functions[selector].ngroups;
return 0;
}
static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
{
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
struct device *dev = &gpio_dev->pdev->dev;
struct pin_desc *pd;
int ind, index;
if (!gpio_dev->iomux_base)
return -EINVAL;
for (index = 0; index < NSELECTS; index++) {
if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
continue;
if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
FUNCTION_INVALID) {
dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
pmx_functions[function].index);
return -EINVAL;
}
writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
FUNCTION_MASK)) {
dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
pmx_functions[function].index);
return -EINVAL;
}
for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
continue;
pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
pd->mux_owner = gpio_dev->groups[group].name;
}
break;
}
return 0;
}
static const struct pinmux_ops amd_pmxops = {
.get_functions_count = amd_get_functions_count,
.get_function_name = amd_get_fname,
.get_function_groups = amd_get_groups,
.set_mux = amd_set_mux,
};
static struct pinctrl_desc amd_pinctrl_desc = {
.pins = kerncz_pins,
.npins = ARRAY_SIZE(kerncz_pins),
.pctlops = &amd_pinctrl_ops,
.pmxops = &amd_pmxops,
.confops = &amd_pinconf_ops,
.owner = THIS_MODULE,
};
static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
{
struct pinctrl_desc *desc = &amd_pinctrl_desc;
struct device *dev = &gpio_dev->pdev->dev;
int index;
index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
if (index < 0) {
dev_dbg(dev, "iomux not supported\n");
goto out_no_pinmux;
}
gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
if (IS_ERR(gpio_dev->iomux_base)) {
dev_dbg(dev, "iomux not supported %d io resource\n", index);
goto out_no_pinmux;
}
return;
out_no_pinmux:
desc->pmxops = NULL;
}
static int amd_gpio_probe(struct platform_device *pdev)
{
int ret = 0;
struct resource *res;
struct amd_gpio *gpio_dev;
struct gpio_irq_chip *girq;
gpio_dev = devm_kzalloc(&pdev->dev,
sizeof(struct amd_gpio), GFP_KERNEL);
if (!gpio_dev)
return -ENOMEM;
raw_spin_lock_init(&gpio_dev->lock);
gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(gpio_dev->base)) {
dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
return PTR_ERR(gpio_dev->base);
}
gpio_dev->irq = platform_get_irq(pdev, 0);
if (gpio_dev->irq < 0)
return gpio_dev->irq;
#ifdef CONFIG_PM_SLEEP
gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
sizeof(*gpio_dev->saved_regs),
GFP_KERNEL);
if (!gpio_dev->saved_regs)
return -ENOMEM;
#endif
gpio_dev->pdev = pdev;
gpio_dev->gc.get_direction = amd_gpio_get_direction;
gpio_dev->gc.direction_input = amd_gpio_direction_input;
gpio_dev->gc.direction_output = amd_gpio_direction_output;
gpio_dev->gc.get = amd_gpio_get_value;
gpio_dev->gc.set = amd_gpio_set_value;
gpio_dev->gc.set_config = amd_gpio_set_config;
gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
gpio_dev->gc.base = -1;
gpio_dev->gc.label = pdev->name;
gpio_dev->gc.owner = THIS_MODULE;
gpio_dev->gc.parent = &pdev->dev;
gpio_dev->gc.ngpio = resource_size(res) / 4;
gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
gpio_dev->groups = kerncz_groups;
gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
amd_pinctrl_desc.name = dev_name(&pdev->dev);
amd_get_iomux_res(gpio_dev);
gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
gpio_dev);
if (IS_ERR(gpio_dev->pctrl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(gpio_dev->pctrl);
}
/* Disable and mask interrupts */
amd_gpio_irq_init(gpio_dev);
girq = &gpio_dev->gc.irq;
gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
if (ret)
return ret;
ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
0, 0, gpio_dev->gc.ngpio);
if (ret) {
dev_err(&pdev->dev, "Failed to add pin range\n");
goto out2;
}
ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
if (ret)
goto out2;
platform_set_drvdata(pdev, gpio_dev);
acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
return ret;
out2:
gpiochip_remove(&gpio_dev->gc);
return ret;
}
static int amd_gpio_remove(struct platform_device *pdev)
{
struct amd_gpio *gpio_dev;
gpio_dev = platform_get_drvdata(pdev);
gpiochip_remove(&gpio_dev->gc);
acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id amd_gpio_acpi_match[] = {
{ "AMD0030", 0 },
{ "AMDI0030", 0},
{ "AMDI0031", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
#endif
static struct platform_driver amd_gpio_driver = {
.driver = {
.name = "amd_gpio",
.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
#ifdef CONFIG_PM_SLEEP
.pm = &amd_gpio_pm_ops,
#endif
},
.probe = amd_gpio_probe,
.remove = amd_gpio_remove,
};
module_platform_driver(amd_gpio_driver);
MODULE_AUTHOR("Ken Xue <[email protected]>, Jeff Wu <[email protected]>");
MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
|
linux-master
|
drivers/pinctrl/pinctrl-amd.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* pinctrl-palmas.c -- TI PALMAS series pin control driver.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <[email protected]>
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mfd/palmas.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#define PALMAS_PIN_GPIO0_ID 0
#define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1
#define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2
#define PALMAS_PIN_GPIO3_CHRG_DET 3
#define PALMAS_PIN_GPIO4_SYSEN1 4
#define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5
#define PALMAS_PIN_GPIO6_SYSEN2 6
#define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7
#define PALMAS_PIN_GPIO8_SIM1RSTI 8
#define PALMAS_PIN_GPIO9_LOW_VBAT 9
#define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10
#define PALMAS_PIN_GPIO11_RCM 11
#define PALMAS_PIN_GPIO12_SIM2RSTO 12
#define PALMAS_PIN_GPIO13 13
#define PALMAS_PIN_GPIO14 14
#define PALMAS_PIN_GPIO15_SIM2RSTI 15
#define PALMAS_PIN_VAC 16
#define PALMAS_PIN_POWERGOOD_USB_PSEL 17
#define PALMAS_PIN_NRESWARM 18
#define PALMAS_PIN_PWRDOWN 19
#define PALMAS_PIN_GPADC_START 20
#define PALMAS_PIN_RESET_IN 21
#define PALMAS_PIN_NSLEEP 22
#define PALMAS_PIN_ENABLE1 23
#define PALMAS_PIN_ENABLE2 24
#define PALMAS_PIN_INT 25
#define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1)
struct palmas_pin_function {
const char *name;
const char * const *groups;
unsigned ngroups;
};
struct palmas_pctrl_chip_info {
struct device *dev;
struct pinctrl_dev *pctl;
struct palmas *palmas;
int pins_current_opt[PALMAS_PIN_NUM];
const struct palmas_pin_function *functions;
unsigned num_functions;
const struct palmas_pingroup *pin_groups;
int num_pin_groups;
const struct pinctrl_pin_desc *pins;
unsigned num_pins;
};
static const struct pinctrl_pin_desc palmas_pins_desc[] = {
PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
PINCTRL_PIN(PALMAS_PIN_INT, "int"),
};
static const char * const opt0_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"vac",
"powergood",
"nreswarm",
"pwrdown",
"gpadc_start",
"reset_in",
"nsleep",
"enable1",
"enable2",
"int",
};
static const char * const opt1_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio15",
"vac",
"powergood",
};
static const char * const opt2_groups[] = {
"gpio1",
"gpio2",
"gpio5",
"gpio7",
};
static const char * const opt3_groups[] = {
"gpio1",
"gpio2",
};
static const char * const gpio_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
};
static const char * const led_groups[] = {
"gpio1",
"gpio2",
};
static const char * const pwm_groups[] = {
"gpio1",
"gpio2",
};
static const char * const regen_groups[] = {
"gpio2",
};
static const char * const sysen_groups[] = {
"gpio4",
"gpio6",
};
static const char * const clk32kgaudio_groups[] = {
"gpio5",
};
static const char * const id_groups[] = {
"gpio0",
};
static const char * const vbus_det_groups[] = {
"gpio1",
};
static const char * const chrg_det_groups[] = {
"gpio3",
};
static const char * const vac_groups[] = {
"vac",
};
static const char * const vacok_groups[] = {
"vac",
};
static const char * const powergood_groups[] = {
"powergood",
};
static const char * const usb_psel_groups[] = {
"gpio5",
"powergood",
};
static const char * const msecure_groups[] = {
"gpio7",
};
static const char * const pwrhold_groups[] = {
"gpio7",
};
static const char * const int_groups[] = {
"int",
};
static const char * const nreswarm_groups[] = {
"nreswarm",
};
static const char * const simrsto_groups[] = {
"gpio12",
};
static const char * const simrsti_groups[] = {
"gpio8",
"gpio15",
};
static const char * const low_vbat_groups[] = {
"gpio9",
};
static const char * const wireless_chrg1_groups[] = {
"gpio10",
};
static const char * const rcm_groups[] = {
"gpio11",
};
static const char * const pwrdown_groups[] = {
"pwrdown",
};
static const char * const gpadc_start_groups[] = {
"gpadc_start",
};
static const char * const reset_in_groups[] = {
"reset_in",
};
static const char * const nsleep_groups[] = {
"nsleep",
};
static const char * const enable_groups[] = {
"enable1",
"enable2",
};
#define FUNCTION_GROUPS \
FUNCTION_GROUP(opt0, OPTION0), \
FUNCTION_GROUP(opt1, OPTION1), \
FUNCTION_GROUP(opt2, OPTION2), \
FUNCTION_GROUP(opt3, OPTION3), \
FUNCTION_GROUP(gpio, GPIO), \
FUNCTION_GROUP(led, LED), \
FUNCTION_GROUP(pwm, PWM), \
FUNCTION_GROUP(regen, REGEN), \
FUNCTION_GROUP(sysen, SYSEN), \
FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \
FUNCTION_GROUP(id, ID), \
FUNCTION_GROUP(vbus_det, VBUS_DET), \
FUNCTION_GROUP(chrg_det, CHRG_DET), \
FUNCTION_GROUP(vac, VAC), \
FUNCTION_GROUP(vacok, VACOK), \
FUNCTION_GROUP(powergood, POWERGOOD), \
FUNCTION_GROUP(usb_psel, USB_PSEL), \
FUNCTION_GROUP(msecure, MSECURE), \
FUNCTION_GROUP(pwrhold, PWRHOLD), \
FUNCTION_GROUP(int, INT), \
FUNCTION_GROUP(nreswarm, NRESWARM), \
FUNCTION_GROUP(simrsto, SIMRSTO), \
FUNCTION_GROUP(simrsti, SIMRSTI), \
FUNCTION_GROUP(low_vbat, LOW_VBAT), \
FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
FUNCTION_GROUP(rcm, RCM), \
FUNCTION_GROUP(pwrdown, PWRDOWN), \
FUNCTION_GROUP(gpadc_start, GPADC_START), \
FUNCTION_GROUP(reset_in, RESET_IN), \
FUNCTION_GROUP(nsleep, NSLEEP), \
FUNCTION_GROUP(enable, ENABLE)
static const struct palmas_pin_function palmas_pin_function[] = {
#undef FUNCTION_GROUP
#define FUNCTION_GROUP(fname, mux) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
FUNCTION_GROUPS,
};
enum palmas_pinmux {
#undef FUNCTION_GROUP
#define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux
FUNCTION_GROUPS,
PALMAS_PINMUX_NA = 0xFFFF,
};
struct palmas_pins_pullup_dn_info {
int pullup_dn_reg_base;
int pullup_dn_reg_add;
int pullup_dn_mask;
int normal_val;
int pull_up_val;
int pull_dn_val;
};
struct palmas_pins_od_info {
int od_reg_base;
int od_reg_add;
int od_mask;
int od_enable;
int od_disable;
};
struct palmas_pin_info {
enum palmas_pinmux mux_opt;
const struct palmas_pins_pullup_dn_info *pud_info;
const struct palmas_pins_od_info *od_info;
};
struct palmas_pingroup {
const char *name;
const unsigned pins[1];
unsigned npins;
unsigned mux_reg_base;
unsigned mux_reg_add;
unsigned mux_reg_mask;
unsigned mux_bit_shift;
const struct palmas_pin_info *opt[4];
};
#define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \
static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \
.pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \
.pullup_dn_reg_add = _add, \
.pullup_dn_mask = _mask, \
.normal_val = _nv, \
.pull_up_val = _uv, \
.pull_dn_val = _dv, \
}
PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);
PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);
PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10);
PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);
PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);
PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);
PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);
PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40);
PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10);
PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4);
PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1);
PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);
PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);
PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);
PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);
PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);
PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);
PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);
PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);
PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);
PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);
PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);
PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);
PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);
PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);
#define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \
static const struct palmas_pins_od_info od_##_name##_info = { \
.od_reg_base = PALMAS_##_rbase##_BASE, \
.od_reg_add = _add, \
.od_mask = _mask, \
.od_enable = _ev, \
.od_disable = _dv, \
}
OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);
OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);
OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);
OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);
OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);
OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);
OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);
OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);
OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);
#define PIN_INFO(_name, _id, _pud_info, _od_info) \
static const struct palmas_pin_info pin_##_name##_info = { \
.mux_opt = PALMAS_PINMUX_##_id, \
.pud_info = _pud_info, \
.od_info = _od_info \
}
PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL);
PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info);
PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info);
PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL);
PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL);
PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info);
PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL);
PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL);
PIN_INFO(gpio8, GPIO, NULL, NULL);
PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL);
PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info);
PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL);
PIN_INFO(gpio12, GPIO, NULL, NULL);
PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info);
PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL);
PIN_INFO(gpio15, GPIO, NULL, NULL);
PIN_INFO(id, ID, &pud_id_info, NULL);
PIN_INFO(led1, LED, NULL, NULL);
PIN_INFO(led2, LED, NULL, NULL);
PIN_INFO(regen, REGEN, NULL, NULL);
PIN_INFO(sysen1, SYSEN, NULL, NULL);
PIN_INFO(sysen2, SYSEN, NULL, NULL);
PIN_INFO(int, INT, NULL, &od_int_info);
PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL);
PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL);
PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL);
PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL);
PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL);
PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL);
PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL);
PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL);
PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL);
PIN_INFO(enable1, NA, &pud_enable1_info, NULL);
PIN_INFO(enable2, NA, &pud_enable2_info, NULL);
PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL);
PIN_INFO(usb_psel, USB_PSEL, NULL, NULL);
PIN_INFO(vac, VAC, NULL, NULL);
PIN_INFO(powergood, POWERGOOD, NULL, NULL);
PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info);
PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL);
PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL);
PIN_INFO(rcm, RCM, NULL, NULL);
PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL);
PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL);
PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL);
#define PALMAS_PRIMARY_SECONDARY_NONE 0
#define PALMAS_NONE_BASE 0
#define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
#define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \
{ \
.name = #pg_name, \
.pins = {PALMAS_PIN_##pin_id}, \
.npins = 1, \
.mux_reg_base = PALMAS_##base##_BASE, \
.mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \
.mux_reg_mask = _mask, \
.mux_bit_shift = _bshift, \
.opt = { \
o0, \
o1, \
o2, \
o3, \
}, \
}
static const struct palmas_pingroup tps65913_pingroups[] = {
PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
};
static const struct palmas_pingroup tps80036_pingroups[] = {
PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL),
PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL),
PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL),
PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL),
PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL),
PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL),
PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL),
PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL),
PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
};
static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
{
const struct palmas_pingroup *g;
unsigned int val;
int ret;
int i;
for (i = 0; i < pci->num_pin_groups; ++i) {
g = &pci->pin_groups[i];
if (g->mux_reg_base == PALMAS_NONE_BASE) {
pci->pins_current_opt[i] = 0;
continue;
}
ret = palmas_read(pci->palmas, g->mux_reg_base,
g->mux_reg_add, &val);
if (ret < 0) {
dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
g->mux_reg_add, ret);
return ret;
}
val &= g->mux_reg_mask;
pci->pins_current_opt[i] = val >> g->mux_bit_shift;
}
return 0;
}
static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
bool enable)
{
int ret;
int val;
val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD3,
PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
if (ret < 0)
dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
return ret;
}
static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
bool enable)
{
int ret;
int val;
val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD3,
PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
if (ret < 0)
dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
return ret;
}
static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->num_pin_groups;
}
static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->pin_groups[group].name;
}
static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins, unsigned *num_pins)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
*pins = pci->pin_groups[group].pins;
*num_pins = pci->pin_groups[group].npins;
return 0;
}
static const struct pinctrl_ops palmas_pinctrl_ops = {
.get_groups_count = palmas_pinctrl_get_groups_count,
.get_group_name = palmas_pinctrl_get_group_name,
.get_group_pins = palmas_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->num_functions;
}
static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->functions[function].name;
}
static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function, const char * const **groups,
unsigned * const num_groups)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
*groups = pci->functions[function].groups;
*num_groups = pci->functions[function].ngroups;
return 0;
}
static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
const struct palmas_pingroup *g;
int i;
int ret;
g = &pci->pin_groups[group];
/* If direct option is provided here */
if (function <= PALMAS_PINMUX_OPTION3) {
if (!g->opt[function]) {
dev_err(pci->dev, "Pin %s does not support option %d\n",
g->name, function);
return -EINVAL;
}
i = function;
} else {
for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
if (!g->opt[i])
continue;
if (g->opt[i]->mux_opt == function)
break;
}
if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
dev_err(pci->dev, "Pin %s does not support option %d\n",
g->name, function);
return -EINVAL;
}
}
if (g->mux_reg_base == PALMAS_NONE_BASE) {
if (WARN_ON(i != 0))
return -EINVAL;
return 0;
}
dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
__func__, g->mux_reg_base, g->mux_reg_add,
g->mux_reg_mask, i << g->mux_bit_shift);
ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
g->mux_reg_mask, i << g->mux_bit_shift);
if (ret < 0) {
dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
g->mux_reg_add, ret);
return ret;
}
pci->pins_current_opt[group] = i;
return 0;
}
static const struct pinmux_ops palmas_pinmux_ops = {
.get_functions_count = palmas_pinctrl_get_funcs_count,
.get_function_name = palmas_pinctrl_get_func_name,
.get_function_groups = palmas_pinctrl_get_func_groups,
.set_mux = palmas_pinctrl_set_mux,
};
static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
const struct palmas_pingroup *g;
const struct palmas_pin_info *opt;
unsigned int val;
int ret;
int base, add;
int rval;
int arg;
int group_nr;
for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
if (pci->pin_groups[group_nr].pins[0] == pin)
break;
}
if (group_nr == pci->num_pin_groups) {
dev_err(pci->dev,
"Pinconf is not supported for pin-id %d\n", pin);
return -ENOTSUPP;
}
g = &pci->pin_groups[group_nr];
opt = g->opt[pci->pins_current_opt[group_nr]];
if (!opt) {
dev_err(pci->dev,
"Pinconf is not supported for pin %s\n", g->name);
return -ENOTSUPP;
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!opt->pud_info) {
dev_err(pci->dev,
"PULL control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
base = opt->pud_info->pullup_dn_reg_base;
add = opt->pud_info->pullup_dn_reg_add;
ret = palmas_read(pci->palmas, base, add, &val);
if (ret < 0) {
dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
add, ret);
return ret;
}
rval = val & opt->pud_info->pullup_dn_mask;
arg = 0;
if ((opt->pud_info->normal_val >= 0) &&
(opt->pud_info->normal_val == rval) &&
(param == PIN_CONFIG_BIAS_DISABLE))
arg = 1;
else if ((opt->pud_info->pull_up_val >= 0) &&
(opt->pud_info->pull_up_val == rval) &&
(param == PIN_CONFIG_BIAS_PULL_UP))
arg = 1;
else if ((opt->pud_info->pull_dn_val >= 0) &&
(opt->pud_info->pull_dn_val == rval) &&
(param == PIN_CONFIG_BIAS_PULL_DOWN))
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!opt->od_info) {
dev_err(pci->dev,
"OD control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
base = opt->od_info->od_reg_base;
add = opt->od_info->od_reg_add;
ret = palmas_read(pci->palmas, base, add, &val);
if (ret < 0) {
dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
add, ret);
return ret;
}
rval = val & opt->od_info->od_mask;
arg = -1;
if ((opt->od_info->od_disable >= 0) &&
(opt->od_info->od_disable == rval))
arg = 0;
else if ((opt->od_info->od_enable >= 0) &&
(opt->od_info->od_enable == rval))
arg = 1;
if (arg < 0) {
dev_err(pci->dev,
"OD control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
break;
default:
dev_err(pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, (u16)arg);
return 0;
}
static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 param_val;
const struct palmas_pingroup *g;
const struct palmas_pin_info *opt;
int ret;
int base, add, mask;
int rval;
int group_nr;
int i;
for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
if (pci->pin_groups[group_nr].pins[0] == pin)
break;
}
if (group_nr == pci->num_pin_groups) {
dev_err(pci->dev,
"Pinconf is not supported for pin-id %d\n", pin);
return -ENOTSUPP;
}
g = &pci->pin_groups[group_nr];
opt = g->opt[pci->pins_current_opt[group_nr]];
if (!opt) {
dev_err(pci->dev,
"Pinconf is not supported for pin %s\n", g->name);
return -ENOTSUPP;
}
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!opt->pud_info) {
dev_err(pci->dev,
"PULL control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
base = opt->pud_info->pullup_dn_reg_base;
add = opt->pud_info->pullup_dn_reg_add;
mask = opt->pud_info->pullup_dn_mask;
if (param == PIN_CONFIG_BIAS_DISABLE)
rval = opt->pud_info->normal_val;
else if (param == PIN_CONFIG_BIAS_PULL_UP)
rval = opt->pud_info->pull_up_val;
else
rval = opt->pud_info->pull_dn_val;
if (rval < 0) {
dev_err(pci->dev,
"PULL control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!opt->od_info) {
dev_err(pci->dev,
"OD control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
base = opt->od_info->od_reg_base;
add = opt->od_info->od_reg_add;
mask = opt->od_info->od_mask;
if (param_val == 0)
rval = opt->od_info->od_disable;
else
rval = opt->od_info->od_enable;
if (rval < 0) {
dev_err(pci->dev,
"OD control not supported for pin %s\n",
g->name);
return -ENOTSUPP;
}
break;
default:
dev_err(pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
__func__, base, add, mask, rval);
ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
if (ret < 0) {
dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
add, ret);
return ret;
}
} /* for each config */
return 0;
}
static const struct pinconf_ops palmas_pinconf_ops = {
.pin_config_get = palmas_pinconf_get,
.pin_config_set = palmas_pinconf_set,
};
static struct pinctrl_desc palmas_pinctrl_desc = {
.pctlops = &palmas_pinctrl_ops,
.pmxops = &palmas_pinmux_ops,
.confops = &palmas_pinconf_ops,
.owner = THIS_MODULE,
};
struct palmas_pinctrl_data {
const struct palmas_pingroup *pin_groups;
int num_pin_groups;
};
static struct palmas_pinctrl_data tps65913_pinctrl_data = {
.pin_groups = tps65913_pingroups,
.num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
};
static struct palmas_pinctrl_data tps80036_pinctrl_data = {
.pin_groups = tps80036_pingroups,
.num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
};
static const struct of_device_id palmas_pinctrl_of_match[] = {
{ .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
{ .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
{ .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
{ },
};
MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
static int palmas_pinctrl_probe(struct platform_device *pdev)
{
struct palmas_pctrl_chip_info *pci;
const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
int ret;
bool enable_dvfs1 = false;
bool enable_dvfs2 = false;
if (pdev->dev.of_node) {
pinctrl_data = of_device_get_match_data(&pdev->dev);
enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
"ti,palmas-enable-dvfs1");
enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
"ti,palmas-enable-dvfs2");
}
pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
if (!pci)
return -ENOMEM;
pci->dev = &pdev->dev;
pci->palmas = dev_get_drvdata(pdev->dev.parent);
pci->pins = palmas_pins_desc;
pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
pci->functions = palmas_pin_function;
pci->num_functions = ARRAY_SIZE(palmas_pin_function);
pci->pin_groups = pinctrl_data->pin_groups;
pci->num_pin_groups = pinctrl_data->num_pin_groups;
platform_set_drvdata(pdev, pci);
palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
ret = palmas_pinctrl_get_pin_mux(pci);
if (ret < 0) {
dev_err(&pdev->dev,
"Reading pinctrol option register failed: %d\n", ret);
return ret;
}
palmas_pinctrl_desc.name = dev_name(&pdev->dev);
palmas_pinctrl_desc.pins = palmas_pins_desc;
palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
pci);
if (IS_ERR(pci->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(pci->pctl);
}
return 0;
}
static struct platform_driver palmas_pinctrl_driver = {
.driver = {
.name = "palmas-pinctrl",
.of_match_table = palmas_pinctrl_of_match,
},
.probe = palmas_pinctrl_probe,
};
module_platform_driver(palmas_pinctrl_driver);
MODULE_DESCRIPTION("Palmas pin control driver");
MODULE_AUTHOR("Laxman Dewangan<[email protected]>");
MODULE_ALIAS("platform:palmas-pinctrl");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-palmas.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, BayLibre, SAS. All rights reserved.
* Author: Neil Armstrong <[email protected]>
*
* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* Driver for Semtech SX150X I2C GPIO Expanders
* The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
*
* Author: Gregory Bean <[email protected]>
*/
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
/* The chip models of sx150x */
enum {
SX150X_123 = 0,
SX150X_456,
SX150X_789,
};
enum {
SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
SX150X_MAX_REGISTER = 0xad,
SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
SX150X_789_RESET_KEY1 = 0x12,
SX150X_789_RESET_KEY2 = 0x34,
};
struct sx150x_123_pri {
u8 reg_pld_mode;
u8 reg_pld_table0;
u8 reg_pld_table1;
u8 reg_pld_table2;
u8 reg_pld_table3;
u8 reg_pld_table4;
u8 reg_advanced;
};
struct sx150x_456_pri {
u8 reg_pld_mode;
u8 reg_pld_table0;
u8 reg_pld_table1;
u8 reg_pld_table2;
u8 reg_pld_table3;
u8 reg_pld_table4;
u8 reg_advanced;
};
struct sx150x_789_pri {
u8 reg_drain;
u8 reg_polarity;
u8 reg_clock;
u8 reg_misc;
u8 reg_reset;
u8 ngpios;
};
struct sx150x_device_data {
u8 model;
u8 reg_pullup;
u8 reg_pulldn;
u8 reg_dir;
u8 reg_data;
u8 reg_irq_mask;
u8 reg_irq_src;
u8 reg_sense;
u8 ngpios;
union {
struct sx150x_123_pri x123;
struct sx150x_456_pri x456;
struct sx150x_789_pri x789;
} pri;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
};
struct sx150x_pinctrl {
struct device *dev;
struct i2c_client *client;
struct pinctrl_dev *pctldev;
struct pinctrl_desc pinctrl_desc;
struct gpio_chip gpio;
struct regmap *regmap;
struct {
u32 sense;
u32 masked;
} irq;
struct mutex lock;
const struct sx150x_device_data *data;
};
static const struct pinctrl_pin_desc sx150x_4_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "oscio"),
};
static const struct pinctrl_pin_desc sx150x_8_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "oscio"),
};
static const struct pinctrl_pin_desc sx150x_16_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "oscio"),
};
static const struct sx150x_device_data sx1501q_device_data = {
.model = SX150X_123,
.reg_pullup = 0x02,
.reg_pulldn = 0x03,
.reg_dir = 0x01,
.reg_data = 0x00,
.reg_irq_mask = 0x05,
.reg_irq_src = 0x08,
.reg_sense = 0x07,
.pri.x123 = {
.reg_pld_mode = 0x10,
.reg_pld_table0 = 0x11,
.reg_pld_table2 = 0x13,
.reg_advanced = 0xad,
},
.ngpios = 4,
.pins = sx150x_4_pins,
.npins = 4, /* oscio not available */
};
static const struct sx150x_device_data sx1502q_device_data = {
.model = SX150X_123,
.reg_pullup = 0x02,
.reg_pulldn = 0x03,
.reg_dir = 0x01,
.reg_data = 0x00,
.reg_irq_mask = 0x05,
.reg_irq_src = 0x08,
.reg_sense = 0x06,
.pri.x123 = {
.reg_pld_mode = 0x10,
.reg_pld_table0 = 0x11,
.reg_pld_table1 = 0x12,
.reg_pld_table2 = 0x13,
.reg_pld_table3 = 0x14,
.reg_pld_table4 = 0x15,
.reg_advanced = 0xad,
},
.ngpios = 8,
.pins = sx150x_8_pins,
.npins = 8, /* oscio not available */
};
static const struct sx150x_device_data sx1503q_device_data = {
.model = SX150X_123,
.reg_pullup = 0x04,
.reg_pulldn = 0x06,
.reg_dir = 0x02,
.reg_data = 0x00,
.reg_irq_mask = 0x08,
.reg_irq_src = 0x0e,
.reg_sense = 0x0a,
.pri.x123 = {
.reg_pld_mode = 0x20,
.reg_pld_table0 = 0x22,
.reg_pld_table1 = 0x24,
.reg_pld_table2 = 0x26,
.reg_pld_table3 = 0x28,
.reg_pld_table4 = 0x2a,
.reg_advanced = 0xad,
},
.ngpios = 16,
.pins = sx150x_16_pins,
.npins = 16, /* oscio not available */
};
static const struct sx150x_device_data sx1504q_device_data = {
.model = SX150X_456,
.reg_pullup = 0x02,
.reg_pulldn = 0x03,
.reg_dir = 0x01,
.reg_data = 0x00,
.reg_irq_mask = 0x05,
.reg_irq_src = 0x08,
.reg_sense = 0x07,
.pri.x456 = {
.reg_pld_mode = 0x10,
.reg_pld_table0 = 0x11,
.reg_pld_table2 = 0x13,
},
.ngpios = 4,
.pins = sx150x_4_pins,
.npins = 4, /* oscio not available */
};
static const struct sx150x_device_data sx1505q_device_data = {
.model = SX150X_456,
.reg_pullup = 0x02,
.reg_pulldn = 0x03,
.reg_dir = 0x01,
.reg_data = 0x00,
.reg_irq_mask = 0x05,
.reg_irq_src = 0x08,
.reg_sense = 0x06,
.pri.x456 = {
.reg_pld_mode = 0x10,
.reg_pld_table0 = 0x11,
.reg_pld_table1 = 0x12,
.reg_pld_table2 = 0x13,
.reg_pld_table3 = 0x14,
.reg_pld_table4 = 0x15,
},
.ngpios = 8,
.pins = sx150x_8_pins,
.npins = 8, /* oscio not available */
};
static const struct sx150x_device_data sx1506q_device_data = {
.model = SX150X_456,
.reg_pullup = 0x04,
.reg_pulldn = 0x06,
.reg_dir = 0x02,
.reg_data = 0x00,
.reg_irq_mask = 0x08,
.reg_irq_src = 0x0e,
.reg_sense = 0x0a,
.pri.x456 = {
.reg_pld_mode = 0x20,
.reg_pld_table0 = 0x22,
.reg_pld_table1 = 0x24,
.reg_pld_table2 = 0x26,
.reg_pld_table3 = 0x28,
.reg_pld_table4 = 0x2a,
.reg_advanced = 0xad,
},
.ngpios = 16,
.pins = sx150x_16_pins,
.npins = 16, /* oscio not available */
};
static const struct sx150x_device_data sx1507q_device_data = {
.model = SX150X_789,
.reg_pullup = 0x03,
.reg_pulldn = 0x04,
.reg_dir = 0x07,
.reg_data = 0x08,
.reg_irq_mask = 0x09,
.reg_irq_src = 0x0b,
.reg_sense = 0x0a,
.pri.x789 = {
.reg_drain = 0x05,
.reg_polarity = 0x06,
.reg_clock = 0x0d,
.reg_misc = 0x0e,
.reg_reset = 0x7d,
},
.ngpios = 4,
.pins = sx150x_4_pins,
.npins = ARRAY_SIZE(sx150x_4_pins),
};
static const struct sx150x_device_data sx1508q_device_data = {
.model = SX150X_789,
.reg_pullup = 0x03,
.reg_pulldn = 0x04,
.reg_dir = 0x07,
.reg_data = 0x08,
.reg_irq_mask = 0x09,
.reg_irq_src = 0x0c,
.reg_sense = 0x0a,
.pri.x789 = {
.reg_drain = 0x05,
.reg_polarity = 0x06,
.reg_clock = 0x0f,
.reg_misc = 0x10,
.reg_reset = 0x7d,
},
.ngpios = 8,
.pins = sx150x_8_pins,
.npins = ARRAY_SIZE(sx150x_8_pins),
};
static const struct sx150x_device_data sx1509q_device_data = {
.model = SX150X_789,
.reg_pullup = 0x06,
.reg_pulldn = 0x08,
.reg_dir = 0x0e,
.reg_data = 0x10,
.reg_irq_mask = 0x12,
.reg_irq_src = 0x18,
.reg_sense = 0x14,
.pri.x789 = {
.reg_drain = 0x0a,
.reg_polarity = 0x0c,
.reg_clock = 0x1e,
.reg_misc = 0x1f,
.reg_reset = 0x7d,
},
.ngpios = 16,
.pins = sx150x_16_pins,
.npins = ARRAY_SIZE(sx150x_16_pins),
};
static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return 0;
}
static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return NULL;
}
static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
return -ENOTSUPP;
}
static const struct pinctrl_ops sx150x_pinctrl_ops = {
.get_groups_count = sx150x_pinctrl_get_groups_count,
.get_group_name = sx150x_pinctrl_get_group_name,
.get_group_pins = sx150x_pinctrl_get_group_pins,
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
#endif
};
static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
{
if (pin >= pctl->data->npins)
return false;
/* OSCIO pin is only present in 789 devices */
if (pctl->data->model != SX150X_789)
return false;
return !strcmp(pctl->data->pins[pin].name, "oscio");
}
static int sx150x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
unsigned int value;
int ret;
if (sx150x_pin_is_oscio(pctl, offset))
return GPIO_LINE_DIRECTION_OUT;
ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
if (ret < 0)
return ret;
if (value & BIT(offset))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
unsigned int value;
int ret;
if (sx150x_pin_is_oscio(pctl, offset))
return -EINVAL;
ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
if (ret < 0)
return ret;
return !!(value & BIT(offset));
}
static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
int value)
{
return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
BIT(offset), value ? BIT(offset) : 0);
}
static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
int value)
{
return regmap_write(pctl->regmap,
pctl->data->pri.x789.reg_clock,
(value ? 0x1f : 0x10));
}
static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
if (sx150x_pin_is_oscio(pctl, offset))
sx150x_gpio_oscio_set(pctl, value);
else
__sx150x_gpio_set(pctl, offset, value);
}
static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
unsigned long *mask,
unsigned long *bits)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
}
static int sx150x_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
if (sx150x_pin_is_oscio(pctl, offset))
return -EINVAL;
return regmap_write_bits(pctl->regmap,
pctl->data->reg_dir,
BIT(offset), BIT(offset));
}
static int sx150x_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
int ret;
if (sx150x_pin_is_oscio(pctl, offset))
return sx150x_gpio_oscio_set(pctl, value);
ret = __sx150x_gpio_set(pctl, offset, value);
if (ret < 0)
return ret;
return regmap_write_bits(pctl->regmap,
pctl->data->reg_dir,
BIT(offset), 0);
}
static void sx150x_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
unsigned int n = irqd_to_hwirq(d);
pctl->irq.masked |= BIT(n);
gpiochip_disable_irq(gc, n);
}
static void sx150x_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
unsigned int n = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, n);
pctl->irq.masked &= ~BIT(n);
}
static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
unsigned int line, unsigned int sense)
{
/*
* Every interrupt line is represented by two bits shifted
* proportionally to the line number
*/
const unsigned int n = line * 2;
const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
SX150X_IRQ_TYPE_EDGE_FALLING) << n);
pctl->irq.sense &= mask;
pctl->irq.sense |= sense << n;
}
static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
unsigned int n, val = 0;
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
return -EINVAL;
n = irqd_to_hwirq(d);
if (flow_type & IRQ_TYPE_EDGE_RISING)
val |= SX150X_IRQ_TYPE_EDGE_RISING;
if (flow_type & IRQ_TYPE_EDGE_FALLING)
val |= SX150X_IRQ_TYPE_EDGE_FALLING;
sx150x_irq_set_sense(pctl, n, val);
return 0;
}
static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
{
struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
unsigned long n, status;
unsigned int val;
int err;
err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
if (err < 0)
return IRQ_NONE;
err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
if (err < 0)
return IRQ_NONE;
status = val;
for_each_set_bit(n, &status, pctl->data->ngpios)
handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
return IRQ_HANDLED;
}
static void sx150x_irq_bus_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
mutex_lock(&pctl->lock);
}
static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
mutex_unlock(&pctl->lock);
}
static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct sx150x_pinctrl *pctl = gpiochip_get_data(gc);
seq_printf(p, pctl->client->name);
}
static const struct irq_chip sx150x_irq_chip = {
.irq_mask = sx150x_irq_mask,
.irq_unmask = sx150x_irq_unmask,
.irq_set_type = sx150x_irq_set_type,
.irq_bus_lock = sx150x_irq_bus_lock,
.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock,
.irq_print_chip = sx150x_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
int ret;
u32 arg;
unsigned int data;
if (sx150x_pin_is_oscio(pctl, pin)) {
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
case PIN_CONFIG_OUTPUT:
ret = regmap_read(pctl->regmap,
pctl->data->pri.x789.reg_clock,
&data);
if (ret < 0)
return ret;
if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
arg = (data & 0x1f) ? 1 : 0;
else {
if ((data & 0x1f) == 0x1f)
arg = 1;
else if ((data & 0x1f) == 0x10)
arg = 0;
else
return -EINVAL;
}
break;
default:
return -ENOTSUPP;
}
goto out;
}
switch (param) {
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = regmap_read(pctl->regmap,
pctl->data->reg_pulldn,
&data);
data &= BIT(pin);
if (ret < 0)
return ret;
if (!ret)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_read(pctl->regmap,
pctl->data->reg_pullup,
&data);
data &= BIT(pin);
if (ret < 0)
return ret;
if (!ret)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (pctl->data->model != SX150X_789)
return -ENOTSUPP;
ret = regmap_read(pctl->regmap,
pctl->data->pri.x789.reg_drain,
&data);
data &= BIT(pin);
if (ret < 0)
return ret;
if (!data)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (pctl->data->model != SX150X_789)
arg = true;
else {
ret = regmap_read(pctl->regmap,
pctl->data->pri.x789.reg_drain,
&data);
data &= BIT(pin);
if (ret < 0)
return ret;
if (data)
return -EINVAL;
arg = 1;
}
break;
case PIN_CONFIG_OUTPUT:
ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
if (ret < 0)
return ret;
if (ret == GPIO_LINE_DIRECTION_IN)
return -EINVAL;
ret = sx150x_gpio_get(&pctl->gpio, pin);
if (ret < 0)
return ret;
arg = ret;
break;
default:
return -ENOTSUPP;
}
out:
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 arg;
int i;
int ret;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
if (sx150x_pin_is_oscio(pctl, pin)) {
if (param == PIN_CONFIG_OUTPUT) {
ret = sx150x_gpio_direction_output(&pctl->gpio,
pin, arg);
if (ret < 0)
return ret;
continue;
} else
return -ENOTSUPP;
}
switch (param) {
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_DISABLE:
ret = regmap_write_bits(pctl->regmap,
pctl->data->reg_pulldn,
BIT(pin), 0);
if (ret < 0)
return ret;
ret = regmap_write_bits(pctl->regmap,
pctl->data->reg_pullup,
BIT(pin), 0);
if (ret < 0)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_write_bits(pctl->regmap,
pctl->data->reg_pullup,
BIT(pin), BIT(pin));
if (ret < 0)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = regmap_write_bits(pctl->regmap,
pctl->data->reg_pulldn,
BIT(pin), BIT(pin));
if (ret < 0)
return ret;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (pctl->data->model != SX150X_789 ||
sx150x_pin_is_oscio(pctl, pin))
return -ENOTSUPP;
ret = regmap_write_bits(pctl->regmap,
pctl->data->pri.x789.reg_drain,
BIT(pin), BIT(pin));
if (ret < 0)
return ret;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (pctl->data->model != SX150X_789 ||
sx150x_pin_is_oscio(pctl, pin))
return 0;
ret = regmap_write_bits(pctl->regmap,
pctl->data->pri.x789.reg_drain,
BIT(pin), 0);
if (ret < 0)
return ret;
break;
case PIN_CONFIG_OUTPUT:
ret = sx150x_gpio_direction_output(&pctl->gpio,
pin, arg);
if (ret < 0)
return ret;
break;
default:
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
static const struct pinconf_ops sx150x_pinconf_ops = {
.pin_config_get = sx150x_pinconf_get,
.pin_config_set = sx150x_pinconf_set,
.is_generic = true,
};
static const struct i2c_device_id sx150x_id[] = {
{"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
{"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
{"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
{"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
{"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
{"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
{"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
{"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
{"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
{}
};
static const struct of_device_id sx150x_of_match[] = {
{ .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
{ .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
{ .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
{ .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
{ .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
{ .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
{ .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
{ .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
{},
};
static int sx150x_reset(struct sx150x_pinctrl *pctl)
{
int err;
err = i2c_smbus_write_byte_data(pctl->client,
pctl->data->pri.x789.reg_reset,
SX150X_789_RESET_KEY1);
if (err < 0)
return err;
err = i2c_smbus_write_byte_data(pctl->client,
pctl->data->pri.x789.reg_reset,
SX150X_789_RESET_KEY2);
return err;
}
static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
{
u8 reg, value;
switch (pctl->data->model) {
case SX150X_789:
reg = pctl->data->pri.x789.reg_misc;
value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
break;
case SX150X_456:
reg = pctl->data->pri.x456.reg_advanced;
value = 0x00;
/*
* Only SX1506 has RegAdvanced, SX1504/5 are expected
* to initialize this offset to zero
*/
if (!reg)
return 0;
break;
case SX150X_123:
reg = pctl->data->pri.x123.reg_advanced;
value = 0x00;
break;
default:
WARN(1, "Unknown chip model %d\n", pctl->data->model);
return -EINVAL;
}
return regmap_write(pctl->regmap, reg, value);
}
static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
{
const u8 reg[] = {
[SX150X_789] = pctl->data->pri.x789.reg_polarity,
[SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
[SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
};
int err;
if (pctl->data->model == SX150X_789 &&
of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
err = sx150x_reset(pctl);
if (err < 0)
return err;
}
err = sx150x_init_misc(pctl);
if (err < 0)
return err;
/* Set all pins to work in normal mode */
return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
}
static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
unsigned int reg)
{
const struct sx150x_device_data *data = pctl->data;
if (reg == data->reg_sense) {
/*
* RegSense packs two bits of configuration per GPIO,
* so we'd need to read twice as many bits as there
* are GPIO in our chip
*/
return 2 * data->ngpios;
} else if ((data->model == SX150X_789 &&
(reg == data->pri.x789.reg_misc ||
reg == data->pri.x789.reg_clock ||
reg == data->pri.x789.reg_reset))
||
(data->model == SX150X_123 &&
reg == data->pri.x123.reg_advanced)
||
(data->model == SX150X_456 &&
data->pri.x456.reg_advanced &&
reg == data->pri.x456.reg_advanced)) {
return 8;
} else {
return data->ngpios;
}
}
static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
unsigned int reg, unsigned int val)
{
unsigned int a, b;
const struct sx150x_device_data *data = pctl->data;
/*
* Whereas SX1509 presents RegSense in a simple layout as such:
* reg [ f f e e d d c c ]
* reg + 1 [ b b a a 9 9 8 8 ]
* reg + 2 [ 7 7 6 6 5 5 4 4 ]
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
*
* SX1503 and SX1506 deviate from that data layout, instead storing
* their contents as follows:
*
* reg [ f f e e d d c c ]
* reg + 1 [ 7 7 6 6 5 5 4 4 ]
* reg + 2 [ b b a a 9 9 8 8 ]
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
*
* so, taking that into account, we swap two
* inner bytes of a 4-byte result
*/
if (reg == data->reg_sense &&
data->ngpios == 16 &&
(data->model == SX150X_123 ||
data->model == SX150X_456)) {
a = val & 0x00ff0000;
b = val & 0x0000ff00;
val &= 0xff0000ff;
val |= b << 8;
val |= a >> 8;
}
return val;
}
/*
* In order to mask the differences between 16 and 8 bit expander
* devices we set up a sligthly ficticious regmap that pretends to be
* a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
* pair/quartet) registers and transparently reconstructs those
* registers via multiple I2C/SMBus reads
*
* This way the rest of the driver code, interfacing with the chip via
* regmap API, can work assuming that each GPIO pin is represented by
* a group of bits at an offset proportional to GPIO number within a
* given register.
*/
static int sx150x_regmap_reg_read(void *context, unsigned int reg,
unsigned int *result)
{
int ret, n;
struct sx150x_pinctrl *pctl = context;
struct i2c_client *i2c = pctl->client;
const int width = sx150x_regmap_reg_width(pctl, reg);
unsigned int idx, val;
/*
* There are four potential cases covered by this function:
*
* 1) 8-pin chip, single configuration bit register
*
* This is trivial the code below just needs to read:
* reg [ 7 6 5 4 3 2 1 0 ]
*
* 2) 8-pin chip, double configuration bit register (RegSense)
*
* The read will be done as follows:
* reg [ 7 7 6 6 5 5 4 4 ]
* reg + 1 [ 3 3 2 2 1 1 0 0 ]
*
* 3) 16-pin chip, single configuration bit register
*
* The read will be done as follows:
* reg [ f e d c b a 9 8 ]
* reg + 1 [ 7 6 5 4 3 2 1 0 ]
*
* 4) 16-pin chip, double configuration bit register (RegSense)
*
* The read will be done as follows:
* reg [ f f e e d d c c ]
* reg + 1 [ b b a a 9 9 8 8 ]
* reg + 2 [ 7 7 6 6 5 5 4 4 ]
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
*/
for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
val <<= 8;
ret = i2c_smbus_read_byte_data(i2c, idx);
if (ret < 0)
return ret;
val |= ret;
}
*result = sx150x_maybe_swizzle(pctl, reg, val);
return 0;
}
static int sx150x_regmap_reg_write(void *context, unsigned int reg,
unsigned int val)
{
int ret, n;
struct sx150x_pinctrl *pctl = context;
struct i2c_client *i2c = pctl->client;
const int width = sx150x_regmap_reg_width(pctl, reg);
val = sx150x_maybe_swizzle(pctl, reg, val);
n = (width - 1) & ~7;
do {
const u8 byte = (val >> n) & 0xff;
ret = i2c_smbus_write_byte_data(i2c, reg, byte);
if (ret < 0)
return ret;
reg++;
n -= 8;
} while (n >= 0);
return 0;
}
static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
{
struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
}
static const struct regmap_config sx150x_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
.cache_type = REGCACHE_RBTREE,
.reg_read = sx150x_regmap_reg_read,
.reg_write = sx150x_regmap_reg_write,
.max_register = SX150X_MAX_REGISTER,
.volatile_reg = sx150x_reg_volatile,
};
static int sx150x_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_WRITE_WORD_DATA;
struct device *dev = &client->dev;
struct sx150x_pinctrl *pctl;
int ret;
if (!i2c_check_functionality(client->adapter, i2c_funcs))
return -ENOSYS;
pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
i2c_set_clientdata(client, pctl);
pctl->dev = dev;
pctl->client = client;
if (dev->of_node)
pctl->data = of_device_get_match_data(dev);
else
pctl->data = (struct sx150x_device_data *)id->driver_data;
if (!pctl->data)
return -EINVAL;
pctl->regmap = devm_regmap_init(dev, NULL, pctl,
&sx150x_regmap_config);
if (IS_ERR(pctl->regmap)) {
ret = PTR_ERR(pctl->regmap);
dev_err(dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
mutex_init(&pctl->lock);
ret = sx150x_init_hw(pctl);
if (ret)
return ret;
/* Pinctrl_desc */
pctl->pinctrl_desc.name = "sx150x-pinctrl";
pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
pctl->pinctrl_desc.pins = pctl->data->pins;
pctl->pinctrl_desc.npins = pctl->data->npins;
pctl->pinctrl_desc.owner = THIS_MODULE;
ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
pctl, &pctl->pctldev);
if (ret) {
dev_err(dev, "Failed to register pinctrl device\n");
return ret;
}
/* Register GPIO controller */
pctl->gpio.base = -1;
pctl->gpio.ngpio = pctl->data->npins;
pctl->gpio.get_direction = sx150x_gpio_get_direction;
pctl->gpio.direction_input = sx150x_gpio_direction_input;
pctl->gpio.direction_output = sx150x_gpio_direction_output;
pctl->gpio.get = sx150x_gpio_get;
pctl->gpio.set = sx150x_gpio_set;
pctl->gpio.set_config = gpiochip_generic_config;
pctl->gpio.parent = dev;
pctl->gpio.can_sleep = true;
pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
if (!pctl->gpio.label)
return -ENOMEM;
/*
* Setting multiple pins is not safe when all pins are not
* handled by the same regmap register. The oscio pin (present
* on the SX150X_789 chips) lives in its own register, so
* would require locking that is not in place at this time.
*/
if (pctl->data->model != SX150X_789)
pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
/* Add Interrupt support if an irq is specified */
if (client->irq > 0) {
struct gpio_irq_chip *girq;
pctl->irq.masked = ~0;
pctl->irq.sense = 0;
/*
* Because sx150x_irq_threaded_fn invokes all of the
* nested interrupt handlers via handle_nested_irq,
* any "handler" assigned to struct gpio_irq_chip
* below is going to be ignored, so the choice of the
* function does not matter that much.
*
* We set it to handle_bad_irq to avoid confusion,
* plus it will be instantly noticeable if it is ever
* called (should not happen)
*/
girq = &pctl->gpio.irq;
gpio_irq_chip_set_chip(girq, &sx150x_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->threaded = true;
ret = devm_request_threaded_irq(dev, client->irq, NULL,
sx150x_irq_thread_fn,
IRQF_ONESHOT | IRQF_SHARED |
IRQF_TRIGGER_FALLING,
client->name, pctl);
if (ret < 0)
return ret;
}
ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
if (ret)
return ret;
/*
* Pin control functions need to be enabled AFTER registering the
* GPIO chip because sx150x_pinconf_set() calls
* sx150x_gpio_direction_output().
*/
ret = pinctrl_enable(pctl->pctldev);
if (ret) {
dev_err(dev, "Failed to enable pinctrl device\n");
return ret;
}
ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
0, 0, pctl->data->npins);
if (ret)
return ret;
return 0;
}
static struct i2c_driver sx150x_driver = {
.driver = {
.name = "sx150x-pinctrl",
.of_match_table = sx150x_of_match,
},
.probe = sx150x_probe,
.id_table = sx150x_id,
};
static int __init sx150x_init(void)
{
return i2c_add_driver(&sx150x_driver);
}
subsys_initcall(sx150x_init);
|
linux-master
|
drivers/pinctrl/pinctrl-sx150x.c
|
/*
* Driver for the Axis ARTPEC-6 pin controller
*
* Author: Chris Paterson <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
#define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
/* Pinmux control register bit definitions */
#define ARTPEC6_PINMUX_UDC0_MASK 0x00000001
#define ARTPEC6_PINMUX_UDC0_SHIFT 0
#define ARTPEC6_PINMUX_UDC1_MASK 0x00000002
#define ARTPEC6_PINMUX_UDC1_SHIFT 1
#define ARTPEC6_PINMUX_DRV_MASK 0x00000060
#define ARTPEC6_PINMUX_DRV_SHIFT 5
#define ARTPEC6_PINMUX_SEL_MASK 0x00003000
#define ARTPEC6_PINMUX_SEL_SHIFT 12
/* Pinmux configurations */
#define ARTPEC6_CONFIG_0 0
#define ARTPEC6_CONFIG_1 1
#define ARTPEC6_CONFIG_2 2
#define ARTPEC6_CONFIG_3 3
/* Pin drive strength options */
#define ARTPEC6_DRIVE_4mA 4
#define ARTPEC6_DRIVE_4mA_SET 0
#define ARTPEC6_DRIVE_6mA 6
#define ARTPEC6_DRIVE_6mA_SET 1
#define ARTPEC6_DRIVE_8mA 8
#define ARTPEC6_DRIVE_8mA_SET 2
#define ARTPEC6_DRIVE_9mA 9
#define ARTPEC6_DRIVE_9mA_SET 3
struct artpec6_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct pinctrl_pin_desc *pins;
unsigned int num_pins;
const struct artpec6_pin_group *pin_groups;
unsigned int num_pin_groups;
const struct artpec6_pmx_func *functions;
unsigned int num_functions;
};
struct artpec6_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
unsigned char config;
};
struct artpec6_pmx_func {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
/* pins */
static struct pinctrl_pin_desc artpec6_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
PINCTRL_PIN(3, "GPIO3"),
PINCTRL_PIN(4, "GPIO4"),
PINCTRL_PIN(5, "GPIO5"),
PINCTRL_PIN(6, "GPIO6"),
PINCTRL_PIN(7, "GPIO7"),
PINCTRL_PIN(8, "GPIO8"),
PINCTRL_PIN(9, "GPIO9"),
PINCTRL_PIN(10, "GPIO10"),
PINCTRL_PIN(11, "GPIO11"),
PINCTRL_PIN(12, "GPIO12"),
PINCTRL_PIN(13, "GPIO13"),
PINCTRL_PIN(14, "GPIO14"),
PINCTRL_PIN(15, "GPIO15"),
PINCTRL_PIN(16, "GPIO16"),
PINCTRL_PIN(17, "GPIO17"),
PINCTRL_PIN(18, "GPIO18"),
PINCTRL_PIN(19, "GPIO19"),
PINCTRL_PIN(20, "GPIO20"),
PINCTRL_PIN(21, "GPIO21"),
PINCTRL_PIN(22, "GPIO22"),
PINCTRL_PIN(23, "GPIO23"),
PINCTRL_PIN(24, "GPIO24"),
PINCTRL_PIN(25, "GPIO25"),
PINCTRL_PIN(26, "GPIO26"),
PINCTRL_PIN(27, "GPIO27"),
PINCTRL_PIN(28, "GPIO28"),
PINCTRL_PIN(29, "GPIO29"),
PINCTRL_PIN(30, "GPIO30"),
PINCTRL_PIN(31, "GPIO31"),
PINCTRL_PIN(32, "UART3_TXD"),
PINCTRL_PIN(33, "UART3_RXD"),
PINCTRL_PIN(34, "UART3_RTS"),
PINCTRL_PIN(35, "UART3_CTS"),
PINCTRL_PIN(36, "NF_ALE"),
PINCTRL_PIN(37, "NF_CE0_N"),
PINCTRL_PIN(38, "NF_CE1_N"),
PINCTRL_PIN(39, "NF_CLE"),
PINCTRL_PIN(40, "NF_RE_N"),
PINCTRL_PIN(41, "NF_WE_N"),
PINCTRL_PIN(42, "NF_WP0_N"),
PINCTRL_PIN(43, "NF_WP1_N"),
PINCTRL_PIN(44, "NF_IO0"),
PINCTRL_PIN(45, "NF_IO1"),
PINCTRL_PIN(46, "NF_IO2"),
PINCTRL_PIN(47, "NF_IO3"),
PINCTRL_PIN(48, "NF_IO4"),
PINCTRL_PIN(49, "NF_IO5"),
PINCTRL_PIN(50, "NF_IO6"),
PINCTRL_PIN(51, "NF_IO7"),
PINCTRL_PIN(52, "NF_RB0_N"),
PINCTRL_PIN(53, "SDIO0_CLK"),
PINCTRL_PIN(54, "SDIO0_CMD"),
PINCTRL_PIN(55, "SDIO0_DAT0"),
PINCTRL_PIN(56, "SDIO0_DAT1"),
PINCTRL_PIN(57, "SDIO0_DAT2"),
PINCTRL_PIN(58, "SDIO0_DAT3"),
PINCTRL_PIN(59, "SDI0_CD"),
PINCTRL_PIN(60, "SDI0_WP"),
PINCTRL_PIN(61, "SDIO1_CLK"),
PINCTRL_PIN(62, "SDIO1_CMD"),
PINCTRL_PIN(63, "SDIO1_DAT0"),
PINCTRL_PIN(64, "SDIO1_DAT1"),
PINCTRL_PIN(65, "SDIO1_DAT2"),
PINCTRL_PIN(66, "SDIO1_DAT3"),
PINCTRL_PIN(67, "SDIO1_CD"),
PINCTRL_PIN(68, "SDIO1_WP"),
PINCTRL_PIN(69, "GBE_REFCLk"),
PINCTRL_PIN(70, "GBE_GTX_CLK"),
PINCTRL_PIN(71, "GBE_TX_CLK"),
PINCTRL_PIN(72, "GBE_TX_EN"),
PINCTRL_PIN(73, "GBE_TX_ER"),
PINCTRL_PIN(74, "GBE_TXD0"),
PINCTRL_PIN(75, "GBE_TXD1"),
PINCTRL_PIN(76, "GBE_TXD2"),
PINCTRL_PIN(77, "GBE_TXD3"),
PINCTRL_PIN(78, "GBE_TXD4"),
PINCTRL_PIN(79, "GBE_TXD5"),
PINCTRL_PIN(80, "GBE_TXD6"),
PINCTRL_PIN(81, "GBE_TXD7"),
PINCTRL_PIN(82, "GBE_RX_CLK"),
PINCTRL_PIN(83, "GBE_RX_DV"),
PINCTRL_PIN(84, "GBE_RX_ER"),
PINCTRL_PIN(85, "GBE_RXD0"),
PINCTRL_PIN(86, "GBE_RXD1"),
PINCTRL_PIN(87, "GBE_RXD2"),
PINCTRL_PIN(88, "GBE_RXD3"),
PINCTRL_PIN(89, "GBE_RXD4"),
PINCTRL_PIN(90, "GBE_RXD5"),
PINCTRL_PIN(91, "GBE_RXD6"),
PINCTRL_PIN(92, "GBE_RXD7"),
PINCTRL_PIN(93, "GBE_CRS"),
PINCTRL_PIN(94, "GBE_COL"),
PINCTRL_PIN(95, "GBE_MDC"),
PINCTRL_PIN(96, "GBE_MDIO"),
};
static const unsigned int cpuclkout_pins0[] = { 0 };
static const unsigned int udlclkout_pins0[] = { 1 };
static const unsigned int i2c1_pins0[] = { 2, 3 };
static const unsigned int i2c2_pins0[] = { 4, 5 };
static const unsigned int i2c3_pins0[] = { 6, 7 };
static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
static const unsigned int i2s1_pins0[] = { 12, 13, 14, 15 };
static const unsigned int i2srefclk_pins0[] = { 19 };
static const unsigned int spi0_pins0[] = { 12, 13, 14, 15 };
static const unsigned int spi1_pins0[] = { 16, 17, 18, 19 };
static const unsigned int pciedebug_pins0[] = { 12, 13, 14, 15 };
static const unsigned int uart0_pins0[] = { 16, 17, 18, 19, 20,
21, 22, 23, 24, 25 };
static const unsigned int uart0_pins1[] = { 20, 21, 22, 23 };
static const unsigned int uart1_pins0[] = { 24, 25, 26, 27 };
static const unsigned int uart2_pins0[] = { 26, 27, 28, 29, 30,
31, 32, 33, 34, 35 };
static const unsigned int uart2_pins1[] = { 28, 29, 30, 31 };
static const unsigned int uart3_pins0[] = { 32, 33, 34, 35 };
static const unsigned int uart4_pins0[] = { 20, 21, 22, 23 };
static const unsigned int uart5_pins0[] = { 28, 29, 30, 31 };
static const unsigned int nand_pins0[] = { 36, 37, 38, 39, 40, 41,
42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52 };
static const unsigned int sdio0_pins0[] = { 53, 54, 55, 56, 57, 58, 59, 60 };
static const unsigned int sdio1_pins0[] = { 61, 62, 63, 64, 65, 66, 67, 68 };
static const unsigned int ethernet_pins0[] = { 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 79, 80, 81, 82,
83, 84, 85, 86, 87, 88, 89,
90, 91, 92, 93, 94, 95, 96 };
static const struct artpec6_pin_group artpec6_pin_groups[] = {
{
.name = "cpuclkoutgrp0",
.pins = cpuclkout_pins0,
.num_pins = ARRAY_SIZE(cpuclkout_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "udlclkoutgrp0",
.pins = udlclkout_pins0,
.num_pins = ARRAY_SIZE(udlclkout_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2c1grp0",
.pins = i2c1_pins0,
.num_pins = ARRAY_SIZE(i2c1_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2c2grp0",
.pins = i2c2_pins0,
.num_pins = ARRAY_SIZE(i2c2_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2c3grp0",
.pins = i2c3_pins0,
.num_pins = ARRAY_SIZE(i2c3_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2s0grp0",
.pins = i2s0_pins0,
.num_pins = ARRAY_SIZE(i2s0_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2s1grp0",
.pins = i2s1_pins0,
.num_pins = ARRAY_SIZE(i2s1_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "i2srefclkgrp0",
.pins = i2srefclk_pins0,
.num_pins = ARRAY_SIZE(i2srefclk_pins0),
.config = ARTPEC6_CONFIG_3,
},
{
.name = "spi0grp0",
.pins = spi0_pins0,
.num_pins = ARRAY_SIZE(spi0_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "spi1grp0",
.pins = spi1_pins0,
.num_pins = ARRAY_SIZE(spi1_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "pciedebuggrp0",
.pins = pciedebug_pins0,
.num_pins = ARRAY_SIZE(pciedebug_pins0),
.config = ARTPEC6_CONFIG_3,
},
{
.name = "uart0grp0", /* All pins. */
.pins = uart0_pins0,
.num_pins = ARRAY_SIZE(uart0_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart0grp1", /* RX/TX and RTS/CTS */
.pins = uart0_pins1,
.num_pins = ARRAY_SIZE(uart0_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart0grp2", /* Only RX/TX pins. */
.pins = uart0_pins1,
.num_pins = ARRAY_SIZE(uart0_pins1) - 2,
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart1grp0", /* RX/TX and RTS/CTS */
.pins = uart1_pins0,
.num_pins = ARRAY_SIZE(uart1_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart1grp1", /* Only RX/TX pins. */
.pins = uart1_pins0,
.num_pins = 2,
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart2grp0", /* Full pinout */
.pins = uart2_pins0,
.num_pins = ARRAY_SIZE(uart2_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart2grp1", /* RX/TX and RTS/CTS */
.pins = uart2_pins1,
.num_pins = ARRAY_SIZE(uart2_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart2grp2", /* Only RX/TX */
.pins = uart2_pins1,
.num_pins = 2,
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart3grp0", /* RX/TX and CTS/RTS */
.pins = uart3_pins0,
.num_pins = ARRAY_SIZE(uart3_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "uart3grp1", /* Only RX/TX */
.pins = uart3_pins0,
.num_pins = ARRAY_SIZE(uart3_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "uart4grp0",
.pins = uart4_pins0,
.num_pins = ARRAY_SIZE(uart4_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5grp0", /* TX/RX and RTS/CTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5grp1", /* Only TX/RX */
.pins = uart5_pins0,
.num_pins = 2,
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5nocts", /* TX/RX/RTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0) - 1,
.config = ARTPEC6_CONFIG_2,
},
{
.name = "nandgrp0",
.pins = nand_pins0,
.num_pins = ARRAY_SIZE(nand_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "sdio0grp0",
.pins = sdio0_pins0,
.num_pins = ARRAY_SIZE(sdio0_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "sdio1grp0",
.pins = sdio1_pins0,
.num_pins = ARRAY_SIZE(sdio1_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "ethernetgrp0",
.pins = ethernet_pins0,
.num_pins = ARRAY_SIZE(ethernet_pins0),
.config = ARTPEC6_CONFIG_0,
},
};
struct pin_register {
unsigned int start;
unsigned int end;
unsigned int reg_base;
};
/*
* The register map has two holes where the pin number
* no longer fits directly with the register offset.
* This table allows us to map this easily.
*/
static const struct pin_register pin_register[] = {
{ 0, 35, 0x0 }, /* 0x0 - 0x8c */
{ 36, 52, 0x100 }, /* 0x100 - 0x140 */
{ 53, 96, 0x180 }, /* 0x180 - 0x22c */
};
static unsigned int artpec6_pmx_reg_offset(unsigned int pin)
{
int i;
for (i = 0; i < ARRAY_SIZE(pin_register); i++) {
if (pin <= pin_register[i].end) {
return (pin - pin_register[i].start) * 4 +
pin_register[i].reg_base;
}
}
/*
* Anything we return here is wrong, but we can only
* get here if pin is outside registered range.
*/
pr_err("%s: Impossible pin %d\n", __func__, pin);
return 0;
}
static int artpec6_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(artpec6_pin_groups);
}
static const char *artpec6_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return artpec6_pin_groups[group].name;
}
static int artpec6_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = (unsigned int *)artpec6_pin_groups[group].pins;
*num_pins = artpec6_pin_groups[group].num_pins;
return 0;
}
static int artpec6_pconf_drive_mA_to_field(unsigned int mA)
{
switch (mA) {
case ARTPEC6_DRIVE_4mA:
return ARTPEC6_DRIVE_4mA_SET;
case ARTPEC6_DRIVE_6mA:
return ARTPEC6_DRIVE_6mA_SET;
case ARTPEC6_DRIVE_8mA:
return ARTPEC6_DRIVE_8mA_SET;
case ARTPEC6_DRIVE_9mA:
return ARTPEC6_DRIVE_9mA_SET;
default:
return -EINVAL;
}
}
static unsigned int artpec6_pconf_drive_field_to_mA(int field)
{
switch (field) {
case ARTPEC6_DRIVE_4mA_SET:
return ARTPEC6_DRIVE_4mA;
case ARTPEC6_DRIVE_6mA_SET:
return ARTPEC6_DRIVE_6mA;
case ARTPEC6_DRIVE_8mA_SET:
return ARTPEC6_DRIVE_8mA;
case ARTPEC6_DRIVE_9mA_SET:
return ARTPEC6_DRIVE_9mA;
default:
/* Shouldn't happen */
return 0;
}
}
static const struct pinctrl_ops artpec6_pctrl_ops = {
.get_group_pins = artpec6_get_group_pins,
.get_groups_count = artpec6_get_groups_count,
.get_group_name = artpec6_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static const char * const gpiogrps[] = {
"cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
"i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
"spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
"uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
"uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
"uart5grp1", "uart5nocts",
};
static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
static const char * const i2c1grps[] = { "i2c1grp0" };
static const char * const i2c2grps[] = { "i2c2grp0" };
static const char * const i2c3grps[] = { "i2c3grp0" };
static const char * const i2s0grps[] = { "i2s0grp0" };
static const char * const i2s1grps[] = { "i2s1grp0" };
static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
static const char * const spi0grps[] = { "spi0grp0" };
static const char * const spi1grps[] = { "spi1grp0" };
static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
static const char * const uart0grps[] = { "uart0grp0", "uart0grp1",
"uart0grp2" };
static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" };
static const char * const uart2grps[] = { "uart2grp0", "uart2grp1",
"uart2grp2" };
static const char * const uart3grps[] = { "uart3grp0" };
static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" };
static const char * const uart5grps[] = { "uart5grp0", "uart5grp1",
"uart5nocts" };
static const char * const nandgrps[] = { "nandgrp0" };
static const char * const sdio0grps[] = { "sdio0grp0" };
static const char * const sdio1grps[] = { "sdio1grp0" };
static const char * const ethernetgrps[] = { "ethernetgrp0" };
static const struct artpec6_pmx_func artpec6_pmx_functions[] = {
{
.name = "gpio",
.groups = gpiogrps,
.num_groups = ARRAY_SIZE(gpiogrps),
},
{
.name = "cpuclkout",
.groups = cpuclkoutgrps,
.num_groups = ARRAY_SIZE(cpuclkoutgrps),
},
{
.name = "udlclkout",
.groups = udlclkoutgrps,
.num_groups = ARRAY_SIZE(udlclkoutgrps),
},
{
.name = "i2c1",
.groups = i2c1grps,
.num_groups = ARRAY_SIZE(i2c1grps),
},
{
.name = "i2c2",
.groups = i2c2grps,
.num_groups = ARRAY_SIZE(i2c2grps),
},
{
.name = "i2c3",
.groups = i2c3grps,
.num_groups = ARRAY_SIZE(i2c3grps),
},
{
.name = "i2s0",
.groups = i2s0grps,
.num_groups = ARRAY_SIZE(i2s0grps),
},
{
.name = "i2s1",
.groups = i2s1grps,
.num_groups = ARRAY_SIZE(i2s1grps),
},
{
.name = "i2srefclk",
.groups = i2srefclkgrps,
.num_groups = ARRAY_SIZE(i2srefclkgrps),
},
{
.name = "spi0",
.groups = spi0grps,
.num_groups = ARRAY_SIZE(spi0grps),
},
{
.name = "spi1",
.groups = spi1grps,
.num_groups = ARRAY_SIZE(spi1grps),
},
{
.name = "pciedebug",
.groups = pciedebuggrps,
.num_groups = ARRAY_SIZE(pciedebuggrps),
},
{
.name = "uart0",
.groups = uart0grps,
.num_groups = ARRAY_SIZE(uart0grps),
},
{
.name = "uart1",
.groups = uart1grps,
.num_groups = ARRAY_SIZE(uart1grps),
},
{
.name = "uart2",
.groups = uart2grps,
.num_groups = ARRAY_SIZE(uart2grps),
},
{
.name = "uart3",
.groups = uart3grps,
.num_groups = ARRAY_SIZE(uart3grps),
},
{
.name = "uart4",
.groups = uart4grps,
.num_groups = ARRAY_SIZE(uart4grps),
},
{
.name = "uart5",
.groups = uart5grps,
.num_groups = ARRAY_SIZE(uart5grps),
},
{
.name = "nand",
.groups = nandgrps,
.num_groups = ARRAY_SIZE(nandgrps),
},
{
.name = "sdio0",
.groups = sdio0grps,
.num_groups = ARRAY_SIZE(sdio0grps),
},
{
.name = "sdio1",
.groups = sdio1grps,
.num_groups = ARRAY_SIZE(sdio1grps),
},
{
.name = "ethernet",
.groups = ethernetgrps,
.num_groups = ARRAY_SIZE(ethernetgrps),
},
};
static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(artpec6_pmx_functions);
}
static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
unsigned int function)
{
return artpec6_pmx_functions[function].name;
}
static int artpec6_pmx_get_fgroups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = artpec6_pmx_functions[function].groups;
*num_groups = artpec6_pmx_functions[function].num_groups;
return 0;
}
static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group,
bool enable)
{
unsigned int regval, val;
unsigned int reg;
int i;
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
for (i = 0; i < artpec6_pin_groups[group].num_pins; i++) {
/*
* Registers for pins above a ARTPEC6_MAX_MUXABLE
* do not have a SEL field and are always selected.
*/
if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
continue;
if (!strcmp(artpec6_pmx_get_fname(pctldev, function), "gpio")) {
/* GPIO is always config 0 */
val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
} else {
if (enable)
val = artpec6_pin_groups[group].config
<< ARTPEC6_PINMUX_SEL_SHIFT;
else
val = ARTPEC6_CONFIG_0
<< ARTPEC6_PINMUX_SEL_SHIFT;
}
reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
regval = readl(pmx->base + reg);
regval &= ~ARTPEC6_PINMUX_SEL_MASK;
regval |= val;
writel(regval, pmx->base + reg);
}
}
static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(pmx->dev, "enabling %s function for pin group %s\n",
artpec6_pmx_get_fname(pctldev, function),
artpec6_get_group_name(pctldev, group));
artpec6_pmx_select_func(pctldev, function, group, true);
return 0;
}
static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
unsigned int reg = artpec6_pmx_reg_offset(pin);
u32 val;
if (pin >= 32)
return -EINVAL;
val = readl_relaxed(pmx->base + reg);
val &= ~ARTPEC6_PINMUX_SEL_MASK;
val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
writel_relaxed(val, pmx->base + reg);
return 0;
}
static const struct pinmux_ops artpec6_pmx_ops = {
.get_functions_count = artpec6_pmx_get_functions_count,
.get_function_name = artpec6_pmx_get_fname,
.get_function_groups = artpec6_pmx_get_fgroups,
.set_mux = artpec6_pmx_set,
.gpio_request_enable = artpec6_pmx_request_gpio,
};
static int artpec6_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int regval;
/* Check for valid pin */
if (pin >= pmx->num_pins) {
dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
pmx->pins[pin].name);
return -ENOTSUPP;
}
dev_dbg(pmx->dev, "getting configuration for pin %s\n",
pmx->pins[pin].name);
/* Read pin register values */
regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));
/* If valid, get configuration for parameter */
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (regval & ARTPEC6_PINMUX_UDC1_MASK)
return -EINVAL;
regval = regval & ARTPEC6_PINMUX_UDC0_MASK;
if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||
(param == PIN_CONFIG_BIAS_PULL_DOWN && regval))
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
regval = (regval & ARTPEC6_PINMUX_DRV_MASK)
>> ARTPEC6_PINMUX_DRV_SHIFT;
regval = artpec6_pconf_drive_field_to_mA(regval);
*config = pinconf_to_config_packed(param, regval);
break;
default:
return -ENOTSUPP;
}
return 0;
}
/*
* Valid combinations of param and arg:
*
* param arg
* PIN_CONFIG_BIAS_DISABLE: x (disable bias)
* PIN_CONFIG_BIAS_PULL_UP: 1 (pull up bias + enable)
* PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
* PIN_CONFIG_DRIVE_STRENGTH: x (4mA, 6mA, 8mA, 9mA)
*
* All other args are invalid. All other params are not supported.
*/
static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
unsigned int arg;
unsigned int regval;
void __iomem *reg;
int i;
/* Check for valid pin */
if (pin >= pmx->num_pins) {
dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
pmx->pins[pin].name);
return -ENOTSUPP;
}
dev_dbg(pmx->dev, "setting configuration for pin %s\n",
pmx->pins[pin].name);
reg = pmx->base + artpec6_pmx_reg_offset(pin);
/* For each config */
for (i = 0; i < num_configs; i++) {
int drive;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
regval = readl(reg);
regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);
writel(regval, reg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (arg != 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
regval = readl(reg);
regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);
regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
writel(regval, reg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (arg != 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
regval = readl(reg);
regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);
regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
writel(regval, reg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
drive = artpec6_pconf_drive_mA_to_field(arg);
if (drive < 0) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
regval = readl(reg);
regval &= ~ARTPEC6_PINMUX_DRV_MASK;
regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);
writel(regval, reg);
break;
default:
dev_dbg(pmx->dev, "parameter not supported\n");
return -ENOTSUPP;
}
}
return 0;
}
static int artpec6_pconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
unsigned int num_pins, current_pin;
int ret;
dev_dbg(pctldev->dev, "setting group %s configuration\n",
artpec6_get_group_name(pctldev, group));
num_pins = artpec6_pin_groups[group].num_pins;
for (current_pin = 0; current_pin < num_pins; current_pin++) {
ret = artpec6_pconf_set(pctldev,
artpec6_pin_groups[group].pins[current_pin],
configs, num_configs);
if (ret < 0)
return ret;
}
return 0;
}
static const struct pinconf_ops artpec6_pconf_ops = {
.is_generic = true,
.pin_config_get = artpec6_pconf_get,
.pin_config_set = artpec6_pconf_set,
.pin_config_group_set = artpec6_pconf_group_set,
};
static struct pinctrl_desc artpec6_desc = {
.name = "artpec6-pinctrl",
.owner = THIS_MODULE,
.pins = artpec6_pins,
.npins = ARRAY_SIZE(artpec6_pins),
.pctlops = &artpec6_pctrl_ops,
.pmxops = &artpec6_pmx_ops,
.confops = &artpec6_pconf_ops,
};
/* The reset values say 4mA, but we want 8mA as default. */
static void artpec6_pmx_reset(struct artpec6_pmx *pmx)
{
void __iomem *base = pmx->base;
int i;
for (i = 0; i < ARTPEC6_LAST_PIN; i++) {
u32 val;
val = readl_relaxed(base + artpec6_pmx_reg_offset(i));
val &= ~ARTPEC6_PINMUX_DRV_MASK;
val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT;
writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
}
}
static int artpec6_pmx_probe(struct platform_device *pdev)
{
struct artpec6_pmx *pmx;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
pmx->dev = &pdev->dev;
pmx->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pmx->base))
return PTR_ERR(pmx->base);
artpec6_pmx_reset(pmx);
pmx->pins = artpec6_pins;
pmx->num_pins = ARRAY_SIZE(artpec6_pins);
pmx->functions = artpec6_pmx_functions;
pmx->num_functions = ARRAY_SIZE(artpec6_pmx_functions);
pmx->pin_groups = artpec6_pin_groups;
pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups);
pmx->pctl = pinctrl_register(&artpec6_desc, &pdev->dev, pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
return PTR_ERR(pmx->pctl);
}
platform_set_drvdata(pdev, pmx);
dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n");
return 0;
}
static int artpec6_pmx_remove(struct platform_device *pdev)
{
struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
pinctrl_unregister(pmx->pctl);
return 0;
}
static const struct of_device_id artpec6_pinctrl_match[] = {
{ .compatible = "axis,artpec6-pinctrl" },
{},
};
static struct platform_driver artpec6_pmx_driver = {
.driver = {
.name = "artpec6-pinctrl",
.of_match_table = artpec6_pinctrl_match,
},
.probe = artpec6_pmx_probe,
.remove = artpec6_pmx_remove,
};
static int __init artpec6_pmx_init(void)
{
return platform_driver_register(&artpec6_pmx_driver);
}
arch_initcall(artpec6_pmx_init);
|
linux-master
|
drivers/pinctrl/pinctrl-artpec6.c
|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2020 Intel Corporation */
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include "core.h"
#include "pinmux.h"
/* GPIO data registers' offsets */
#define KEEMBAY_GPIO_DATA_OUT 0x000
#define KEEMBAY_GPIO_DATA_IN 0x020
#define KEEMBAY_GPIO_DATA_IN_RAW 0x040
#define KEEMBAY_GPIO_DATA_HIGH 0x060
#define KEEMBAY_GPIO_DATA_LOW 0x080
/* GPIO Interrupt and mode registers' offsets */
#define KEEMBAY_GPIO_INT_CFG 0x000
#define KEEMBAY_GPIO_MODE 0x070
/* GPIO mode register bit fields */
#define KEEMBAY_GPIO_MODE_PULLUP_MASK GENMASK(13, 12)
#define KEEMBAY_GPIO_MODE_DRIVE_MASK GENMASK(8, 7)
#define KEEMBAY_GPIO_MODE_INV_MASK GENMASK(5, 4)
#define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0)
#define KEEMBAY_GPIO_MODE_DIR_OVR BIT(15)
#define KEEMBAY_GPIO_MODE_REN BIT(11)
#define KEEMBAY_GPIO_MODE_SCHMITT_EN BIT(10)
#define KEEMBAY_GPIO_MODE_SLEW_RATE BIT(9)
#define KEEMBAY_GPIO_IRQ_ENABLE BIT(7)
#define KEEMBAY_GPIO_MODE_DIR BIT(3)
#define KEEMBAY_GPIO_MODE_DEFAULT 0x7
#define KEEMBAY_GPIO_MODE_INV_VAL 0x3
#define KEEMBAY_GPIO_DISABLE 0
#define KEEMBAY_GPIO_PULL_UP 1
#define KEEMBAY_GPIO_PULL_DOWN 2
#define KEEMBAY_GPIO_BUS_HOLD 3
#define KEEMBAY_GPIO_NUM_IRQ 8
#define KEEMBAY_GPIO_MAX_PER_IRQ 4
#define KEEMBAY_GPIO_MAX_PER_REG 32
#define KEEMBAY_GPIO_MIN_STRENGTH 2
#define KEEMBAY_GPIO_MAX_STRENGTH 12
#define KEEMBAY_GPIO_SENSE_LOW (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)
/* GPIO reg address calculation */
#define KEEMBAY_GPIO_REG_OFFSET(pin) ((pin) * 4)
/**
* struct keembay_mux_desc - Mux properties of each GPIO pin
* @mode: Pin mode when operating in this function
* @name: Pin function name
*/
struct keembay_mux_desc {
u8 mode;
const char *name;
};
#define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) { \
.number = pin_number, \
.name = pin_name, \
.drv_data = &(struct keembay_mux_desc[]) { \
__VA_ARGS__, { } }, \
} \
#define KEEMBAY_MUX(pin_mode, pin_function) { \
.mode = pin_mode, \
.name = pin_function, \
} \
/**
* struct keembay_gpio_irq - Config of each GPIO Interrupt sources
* @source: Interrupt source number (0 - 7)
* @line: Actual Interrupt line number
* @pins: Array of GPIO pins using this Interrupt line
* @trigger: Interrupt trigger type for this line
* @num_share: Number of pins currently using this Interrupt line
*/
struct keembay_gpio_irq {
unsigned int source;
unsigned int line;
unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ];
unsigned int trigger;
unsigned int num_share;
};
/**
* struct keembay_pinctrl - Intel Keembay pinctrl structure
* @pctrl: Pointer to the pin controller device
* @base0: First register base address
* @base1: Second register base address
* @dev: Pointer to the device structure
* @chip: GPIO chip used by this pin controller
* @soc: Pin control configuration data based on SoC
* @lock: Spinlock to protect various gpio config register access
* @ngroups: Number of pin groups available
* @nfuncs: Number of pin functions available
* @npins: Number of GPIO pins available
* @irq: Store Interrupt source
* @max_gpios_level_type: Store max level trigger type
* @max_gpios_edge_type: Store max edge trigger type
*/
struct keembay_pinctrl {
struct pinctrl_dev *pctrl;
void __iomem *base0;
void __iomem *base1;
struct device *dev;
struct gpio_chip chip;
const struct keembay_pin_soc *soc;
raw_spinlock_t lock;
unsigned int ngroups;
unsigned int nfuncs;
unsigned int npins;
struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ];
int max_gpios_level_type;
int max_gpios_edge_type;
};
/**
* struct keembay_pin_soc - Pin control config data based on SoC
* @pins: Pin description structure
*/
struct keembay_pin_soc {
const struct pinctrl_pin_desc *pins;
};
static const struct pinctrl_pin_desc keembay_pins[] = {
KEEMBAY_PIN_DESC(0, "GPIO0",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(1, "GPIO1",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(2, "GPIO2",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(3, "GPIO3",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(4, "GPIO4",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C2_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(5, "GPIO5",
KEEMBAY_MUX(0x0, "I2S0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C2_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(6, "GPIO6",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C3_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(7, "GPIO7",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "I2C3_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(8, "GPIO8",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "SLVDS0_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(9, "GPIO9",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(10, "GPIO10",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(11, "GPIO11",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SD0_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "UART0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(12, "GPIO12",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "I2S2_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SPI0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(13, "GPIO13",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "I2S2_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SPI0_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(14, "GPIO14",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "PWM_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "ETH_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(15, "GPIO15",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(16, "GPIO16",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(17, "GPIO17",
KEEMBAY_MUX(0x0, "UART0_M0"),
KEEMBAY_MUX(0x1, "I2S3_M1"),
KEEMBAY_MUX(0x2, "I2S3_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(18, "GPIO18",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "I2S3_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(19, "GPIO19",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "SD1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "LCD_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(20, "GPIO20",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "SPI1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(21, "GPIO21",
KEEMBAY_MUX(0x0, "UART1_M0"),
KEEMBAY_MUX(0x1, "LCD_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(22, "GPIO22",
KEEMBAY_MUX(0x0, "I2C0_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(23, "GPIO23",
KEEMBAY_MUX(0x0, "I2C0_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(24, "GPIO24",
KEEMBAY_MUX(0x0, "I2C1_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "DEBUG_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(25, "GPIO25",
KEEMBAY_MUX(0x0, "I2C1_M0"),
KEEMBAY_MUX(0x1, "UART2_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(26, "GPIO26",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "DSU_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(27, "GPIO27",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "DSU_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C0_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(28, "GPIO28",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C1_M5"),
KEEMBAY_MUX(0x6, "SLVDS0_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(29, "GPIO29",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2C3_M1"),
KEEMBAY_MUX(0x2, "UART0_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I3C2_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(30, "GPIO30",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "I2C4_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(31, "GPIO31",
KEEMBAY_MUX(0x0, "SPI0_M0"),
KEEMBAY_MUX(0x1, "I2S0_M1"),
KEEMBAY_MUX(0x2, "I2C4_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "UART1_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(32, "GPIO32",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "UART1_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "PCIE_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(33, "GPIO33",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "UART1_M2"),
KEEMBAY_MUX(0x3, "PWM_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "PCIE_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(34, "GPIO34",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI0_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "UART1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(35, "GPIO35",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "PCIE_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "UART1_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(36, "GPIO36",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(37, "GPIO37",
KEEMBAY_MUX(0x0, "SD0_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "I2S0_M5"),
KEEMBAY_MUX(0x6, "SLVDS1_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(38, "GPIO38",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(39, "GPIO39",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(40, "GPIO40",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "UART3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(41, "GPIO41",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI3_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "DEBUG_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(42, "GPIO42",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "CAM_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C4_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(43, "GPIO43",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI3_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2C4_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(44, "GPIO44",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(45, "GPIO45",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "CPR_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(46, "GPIO46",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(47, "GPIO47",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SD1_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(48, "GPIO48",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(49, "GPIO49",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(50, "GPIO50",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(51, "GPIO51",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "UART2_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(52, "GPIO52",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(53, "GPIO53",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(54, "GPIO54",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(55, "GPIO55",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(56, "GPIO56",
KEEMBAY_MUX(0x0, "ETH_M0"),
KEEMBAY_MUX(0x1, "SPI2_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I2S2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(57, "GPIO57",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "I2S1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(58, "GPIO58",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(59, "GPIO59",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(60, "GPIO60",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I3C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(61, "GPIO61",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(62, "GPIO62",
KEEMBAY_MUX(0x0, "SPI1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(63, "GPIO63",
KEEMBAY_MUX(0x0, "I2S1_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(64, "GPIO64",
KEEMBAY_MUX(0x0, "I2S2_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "ETH_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "UART1_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(65, "GPIO65",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "SPI1_M1"),
KEEMBAY_MUX(0x2, "SD1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(66, "GPIO66",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "CAM_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(67, "GPIO67",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(68, "GPIO68",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(69, "GPIO69",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "I2C1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SPI0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(70, "GPIO70",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SPI0_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(71, "GPIO71",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "I2S3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(72, "GPIO72",
KEEMBAY_MUX(0x0, "I3C1_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(73, "GPIO73",
KEEMBAY_MUX(0x0, "I3C2_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(74, "GPIO74",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(75, "GPIO75",
KEEMBAY_MUX(0x0, "I3C0_M0"),
KEEMBAY_MUX(0x1, "ETH_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "SD0_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART2_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(76, "GPIO76",
KEEMBAY_MUX(0x0, "I2C2_M0"),
KEEMBAY_MUX(0x1, "I3C0_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "ETH_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(77, "GPIO77",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I3C1_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(78, "GPIO78",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I3C2_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
KEEMBAY_PIN_DESC(79, "GPIO79",
KEEMBAY_MUX(0x0, "PCIE_M0"),
KEEMBAY_MUX(0x1, "I2C2_M1"),
KEEMBAY_MUX(0x2, "SLVDS1_M2"),
KEEMBAY_MUX(0x3, "TPIU_M3"),
KEEMBAY_MUX(0x4, "I3C2_M4"),
KEEMBAY_MUX(0x5, "LCD_M5"),
KEEMBAY_MUX(0x6, "UART3_M6"),
KEEMBAY_MUX(0x7, "GPIO_M7")),
};
static inline u32 keembay_read_reg(void __iomem *base, unsigned int pin)
{
return readl(base + KEEMBAY_GPIO_REG_OFFSET(pin));
}
static inline u32 keembay_read_gpio_reg(void __iomem *base, unsigned int pin)
{
return keembay_read_reg(base, pin / KEEMBAY_GPIO_MAX_PER_REG);
}
static inline u32 keembay_read_pin(void __iomem *base, unsigned int pin)
{
u32 val = keembay_read_gpio_reg(base, pin);
return !!(val & BIT(pin % KEEMBAY_GPIO_MAX_PER_REG));
}
static inline void keembay_write_reg(u32 val, void __iomem *base, unsigned int pin)
{
writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin));
}
static inline void keembay_write_gpio_reg(u32 val, void __iomem *base, unsigned int pin)
{
keembay_write_reg(val, base, pin / KEEMBAY_GPIO_MAX_PER_REG);
}
static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
/*
* This IP doesn't support the falling edge and low level interrupt
* trigger. Invert API is used to mimic the falling edge and low
* level support
*/
val |= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, KEEMBAY_GPIO_MODE_INV_VAL);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
}
static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val &= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, 0);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
}
static int keembay_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned int pin)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
unsigned int val;
if (pin >= kpc->npins)
return -EINVAL;
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = FIELD_GET(KEEMBAY_GPIO_MODE_SELECT_MASK, val);
/* As per Pin Mux Map, Modes 0 to 6 are for peripherals */
if (val != KEEMBAY_GPIO_MODE_DEFAULT)
return -EBUSY;
return 0;
}
static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel,
unsigned int grp_sel)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
unsigned int val;
u8 pin_mode;
int pin;
grp = pinctrl_generic_get_group(pctldev, grp_sel);
if (!grp)
return -EINVAL;
func = pinmux_generic_get_function(pctldev, fun_sel);
if (!func)
return -EINVAL;
/* Change modes for pins in the selected group */
pin = *grp->pins;
pin_mode = *(u8 *)(func->data);
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return FIELD_GET(KEEMBAY_GPIO_MODE_PULLUP_MASK, val);
}
static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int pull)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = u32_replace_bits(val, pull, KEEMBAY_GPIO_MODE_PULLUP_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val = FIELD_GET(KEEMBAY_GPIO_MODE_DRIVE_MASK, val) * 4;
if (val)
return val;
return KEEMBAY_GPIO_MIN_STRENGTH;
}
static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int drive)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
unsigned int strength = clamp_val(drive, KEEMBAY_GPIO_MIN_STRENGTH,
KEEMBAY_GPIO_MAX_STRENGTH) / 4;
val = u32_replace_bits(val, strength, KEEMBAY_GPIO_MODE_DRIVE_MASK);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return !!(val & KEEMBAY_GPIO_MODE_SLEW_RATE);
}
static int keembay_pinconf_set_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int slew_rate)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
if (slew_rate)
val |= KEEMBAY_GPIO_MODE_SLEW_RATE;
else
val &= ~KEEMBAY_GPIO_MODE_SLEW_RATE;
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get_schmitt(struct keembay_pinctrl *kpc, unsigned int pin)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return !!(val & KEEMBAY_GPIO_MODE_SCHMITT_EN);
}
static int keembay_pinconf_set_schmitt(struct keembay_pinctrl *kpc, unsigned int pin,
unsigned int schmitt_en)
{
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
if (schmitt_en)
val |= KEEMBAY_GPIO_MODE_SCHMITT_EN;
else
val &= ~KEEMBAY_GPIO_MODE_SCHMITT_EN;
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *cfg)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*cfg);
unsigned int val;
if (pin >= kpc->npins)
return -EINVAL;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_DISABLE)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_UP)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_DOWN)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_BUS_HOLD)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!keembay_pinconf_get_schmitt(kpc, pin))
return -EINVAL;
break;
case PIN_CONFIG_SLEW_RATE:
val = keembay_pinconf_get_slew_rate(kpc, pin);
*cfg = pinconf_to_config_packed(param, val);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
val = keembay_pinconf_get_drive(kpc, pin);
*cfg = pinconf_to_config_packed(param, val);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int keembay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *cfg, unsigned int num_configs)
{
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
unsigned int arg, i;
int ret = 0;
if (pin >= kpc->npins)
return -EINVAL;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(cfg[i]);
arg = pinconf_to_config_argument(cfg[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_DISABLE);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_UP);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_DOWN);
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_BUS_HOLD);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
ret = keembay_pinconf_set_schmitt(kpc, pin, arg);
break;
case PIN_CONFIG_SLEW_RATE:
ret = keembay_pinconf_set_slew_rate(kpc, pin, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
ret = keembay_pinconf_set_drive(kpc, pin, arg);
break;
default:
return -ENOTSUPP;
}
if (ret)
return ret;
}
return ret;
}
static const struct pinctrl_ops keembay_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static const struct pinmux_ops keembay_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.gpio_request_enable = keembay_request_gpio,
.set_mux = keembay_set_mux,
};
static const struct pinconf_ops keembay_confops = {
.is_generic = true,
.pin_config_get = keembay_pinconf_get,
.pin_config_set = keembay_pinconf_set,
};
static struct pinctrl_desc keembay_pinctrl_desc = {
.name = "keembay-pinmux",
.pctlops = &keembay_pctlops,
.pmxops = &keembay_pmxops,
.confops = &keembay_confops,
.owner = THIS_MODULE,
};
static int keembay_gpio_get(struct gpio_chip *gc, unsigned int pin)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int val, offset;
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
offset = (val & KEEMBAY_GPIO_MODE_DIR) ? KEEMBAY_GPIO_DATA_IN : KEEMBAY_GPIO_DATA_OUT;
return keembay_read_pin(kpc->base0 + offset, pin);
}
static void keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int reg_val;
reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin);
if (val)
keembay_write_gpio_reg(reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),
kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin);
else
keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),
kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin);
}
static int keembay_gpio_get_direction(struct gpio_chip *gc, unsigned int pin)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return !!(val & KEEMBAY_GPIO_MODE_DIR);
}
static int keembay_gpio_set_direction_in(struct gpio_chip *gc, unsigned int pin)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int val;
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val |= KEEMBAY_GPIO_MODE_DIR;
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
return 0;
}
static int keembay_gpio_set_direction_out(struct gpio_chip *gc,
unsigned int pin, int value)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int val;
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
val &= ~KEEMBAY_GPIO_MODE_DIR;
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
keembay_gpio_set(gc, pin, value);
return 0;
}
static void keembay_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
unsigned int kmb_irq = irq_desc_get_irq(desc);
unsigned long reg, clump = 0, bit = 0;
struct irq_chip *parent_chip;
struct keembay_pinctrl *kpc;
unsigned int src, pin, val;
/* Identify GPIO interrupt number from GIC interrupt number */
for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
if (kmb_irq == gc->irq.parents[src])
break;
}
if (src == KEEMBAY_GPIO_NUM_IRQ)
return;
parent_chip = irq_desc_get_chip(desc);
kpc = gpiochip_get_data(gc);
chained_irq_enter(parent_chip, desc);
reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
/*
* Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
* and input values were checked to identify the source of the
* Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
*/
for_each_set_clump8(bit, clump, ®, BITS_PER_TYPE(typeof(reg))) {
pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
/* Checks if the interrupt is enabled */
if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
generic_handle_irq(kmb_irq);
}
chained_irq_exit(parent_chip, desc);
}
static void keembay_gpio_clear_irq(struct irq_data *data, unsigned long pos,
u32 src, irq_hw_number_t pin)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned long trig = irqd_get_trigger_type(data);
struct keembay_gpio_irq *irq = &kpc->irq[src];
unsigned long val;
/* Check if the value of pos/KEEMBAY_GPIO_NUM_IRQ is in valid range. */
if ((pos / KEEMBAY_GPIO_NUM_IRQ) >= KEEMBAY_GPIO_MAX_PER_IRQ)
return;
/* Retains val register as it handles other interrupts as well. */
val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
bitmap_set_value8(&val, 0, pos);
keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
irq->num_share--;
irq->pins[pos / KEEMBAY_GPIO_NUM_IRQ] = 0;
if (trig & IRQ_TYPE_LEVEL_MASK)
keembay_gpio_restore_default(kpc, pin);
if (irq->trigger == IRQ_TYPE_LEVEL_HIGH)
kpc->max_gpios_level_type++;
else if (irq->trigger == IRQ_TYPE_EDGE_RISING)
kpc->max_gpios_edge_type++;
}
static int keembay_find_free_slot(struct keembay_pinctrl *kpc, unsigned int src)
{
unsigned long val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
return bitmap_find_free_region(&val, KEEMBAY_GPIO_MAX_PER_REG, 3) / KEEMBAY_GPIO_NUM_IRQ;
}
static int keembay_find_free_src(struct keembay_pinctrl *kpc, unsigned int trig)
{
int src, type = 0;
if (trig & IRQ_TYPE_LEVEL_MASK)
type = IRQ_TYPE_LEVEL_HIGH;
else if (trig & IRQ_TYPE_EDGE_BOTH)
type = IRQ_TYPE_EDGE_RISING;
for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
if (kpc->irq[src].trigger != type)
continue;
if (!keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src) ||
kpc->irq[src].num_share < KEEMBAY_GPIO_MAX_PER_IRQ)
return src;
}
return -EBUSY;
}
static void keembay_gpio_set_irq(struct keembay_pinctrl *kpc, int src,
int slot, irq_hw_number_t pin)
{
unsigned long val = pin | KEEMBAY_GPIO_IRQ_ENABLE;
struct keembay_gpio_irq *irq = &kpc->irq[src];
unsigned long flags, reg;
raw_spin_lock_irqsave(&kpc->lock, flags);
reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
bitmap_set_value8(®, val, slot * 8);
keembay_write_reg(reg, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
raw_spin_unlock_irqrestore(&kpc->lock, flags);
if (irq->trigger == IRQ_TYPE_LEVEL_HIGH)
kpc->max_gpios_level_type--;
else if (irq->trigger == IRQ_TYPE_EDGE_RISING)
kpc->max_gpios_edge_type--;
irq->source = src;
irq->pins[slot] = pin;
irq->num_share++;
}
static void keembay_gpio_irq_enable(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
unsigned int trig = irqd_get_trigger_type(data);
irq_hw_number_t pin = irqd_to_hwirq(data);
int src, slot;
/* Check which Interrupt source and slot is available */
src = keembay_find_free_src(kpc, trig);
slot = keembay_find_free_slot(kpc, src);
if (src < 0 || slot < 0)
return;
if (trig & KEEMBAY_GPIO_SENSE_LOW)
keembay_gpio_invert(kpc, pin);
keembay_gpio_set_irq(kpc, src, slot, pin);
}
static void keembay_gpio_irq_ack(struct irq_data *data)
{
/*
* The keembay_gpio_irq_ack function is needed to handle_edge_irq.
* IRQ ack is not possible from the SOC perspective. The IP by itself
* is used for handling interrupts which do not come in short-time and
* not used as protocol or communication interrupts. All the interrupts
* are threaded IRQ interrupts. But this function is expected to be
* present as the gpio IP is registered with irq framework. Otherwise
* handle_edge_irq() fails.
*/
}
static void keembay_gpio_irq_disable(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
irq_hw_number_t pin = irqd_to_hwirq(data);
unsigned long reg, clump = 0, pos = 0;
unsigned int src;
for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
for_each_set_clump8(pos, clump, ®, BITS_PER_TYPE(typeof(reg))) {
if ((clump & ~KEEMBAY_GPIO_IRQ_ENABLE) == pin) {
keembay_gpio_clear_irq(data, pos, src, pin);
return;
}
}
}
}
static int keembay_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
/* Change EDGE_BOTH as EDGE_RISING in order to claim the IRQ for power button */
if (!kpc->max_gpios_edge_type && (type & IRQ_TYPE_EDGE_BOTH))
type = IRQ_TYPE_EDGE_RISING;
if (!kpc->max_gpios_level_type && (type & IRQ_TYPE_LEVEL_MASK))
type = IRQ_TYPE_NONE;
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(data, handle_edge_irq);
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(data, handle_level_irq);
else
return -EINVAL;
return 0;
}
static int keembay_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct keembay_pinctrl *kpc = gpiochip_get_data(chip);
int ret;
ret = gpiochip_add_pin_range(chip, dev_name(kpc->dev), 0, 0, chip->ngpio);
if (ret)
dev_err_probe(kpc->dev, ret, "failed to add GPIO pin range\n");
return ret;
}
static struct irq_chip keembay_gpio_irqchip = {
.name = "keembay-gpio",
.irq_enable = keembay_gpio_irq_enable,
.irq_disable = keembay_gpio_irq_disable,
.irq_set_type = keembay_gpio_irq_set_type,
.irq_ack = keembay_gpio_irq_ack,
};
static int keembay_gpiochip_probe(struct keembay_pinctrl *kpc,
struct platform_device *pdev)
{
unsigned int i, level_line = 0, edge_line = 0;
struct gpio_chip *gc = &kpc->chip;
struct gpio_irq_chip *girq;
/* Setup GPIO IRQ chip */
girq = &kpc->chip.irq;
girq->chip = &keembay_gpio_irqchip;
girq->parent_handler = keembay_gpio_irq_handler;
girq->num_parents = KEEMBAY_GPIO_NUM_IRQ;
girq->parents = devm_kcalloc(kpc->dev, girq->num_parents,
sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
/* Setup GPIO chip */
gc->label = dev_name(kpc->dev);
gc->parent = kpc->dev;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->get_direction = keembay_gpio_get_direction;
gc->direction_input = keembay_gpio_set_direction_in;
gc->direction_output = keembay_gpio_set_direction_out;
gc->get = keembay_gpio_get;
gc->set = keembay_gpio_set;
gc->set_config = gpiochip_generic_config;
gc->base = -1;
gc->ngpio = kpc->npins;
gc->add_pin_ranges = keembay_gpio_add_pin_ranges;
for (i = 0; i < KEEMBAY_GPIO_NUM_IRQ; i++) {
struct keembay_gpio_irq *kmb_irq = &kpc->irq[i];
int irq;
irq = platform_get_irq_optional(pdev, i);
if (irq <= 0)
continue;
girq->parents[i] = irq;
kmb_irq->line = girq->parents[i];
kmb_irq->source = i;
kmb_irq->trigger = irq_get_trigger_type(girq->parents[i]);
kmb_irq->num_share = 0;
if (kmb_irq->trigger == IRQ_TYPE_LEVEL_HIGH)
level_line++;
else
edge_line++;
}
kpc->max_gpios_level_type = level_line * KEEMBAY_GPIO_MAX_PER_IRQ;
kpc->max_gpios_edge_type = edge_line * KEEMBAY_GPIO_MAX_PER_IRQ;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
return devm_gpiochip_add_data(kpc->dev, gc, kpc);
}
static int keembay_build_groups(struct keembay_pinctrl *kpc)
{
struct group_desc *grp;
unsigned int i;
kpc->ngroups = kpc->npins;
grp = devm_kcalloc(kpc->dev, kpc->ngroups, sizeof(*grp), GFP_KERNEL);
if (!grp)
return -ENOMEM;
/* Each pin is categorised as one group */
for (i = 0; i < kpc->ngroups; i++) {
const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
struct group_desc *kmb_grp = grp + i;
kmb_grp->name = pdesc->name;
kmb_grp->pins = (int *)&pdesc->number;
pinctrl_generic_add_group(kpc->pctrl, kmb_grp->name,
kmb_grp->pins, 1, NULL);
}
return 0;
}
static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc, struct device *dev)
{
int ret;
keembay_pinctrl_desc.pins = keembay_pins;
ret = of_property_read_u32(dev->of_node, "ngpios", &kpc->npins);
if (ret < 0)
return ret;
keembay_pinctrl_desc.npins = kpc->npins;
kpc->pctrl = devm_pinctrl_register(kpc->dev, &keembay_pinctrl_desc, kpc);
return PTR_ERR_OR_ZERO(kpc->pctrl);
}
static int keembay_add_functions(struct keembay_pinctrl *kpc,
struct function_desc *functions)
{
unsigned int i;
/* Assign the groups for each function */
for (i = 0; i < kpc->nfuncs; i++) {
struct function_desc *func = &functions[i];
const char **group_names;
unsigned int grp_idx = 0;
int j;
group_names = devm_kcalloc(kpc->dev, func->num_group_names,
sizeof(*group_names), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
for (j = 0; j < kpc->npins; j++) {
const struct pinctrl_pin_desc *pdesc = &keembay_pins[j];
struct keembay_mux_desc *mux;
for (mux = pdesc->drv_data; mux->name; mux++) {
if (!strcmp(mux->name, func->name))
group_names[grp_idx++] = pdesc->name;
}
}
func->group_names = group_names;
}
/* Add all functions */
for (i = 0; i < kpc->nfuncs; i++) {
pinmux_generic_add_function(kpc->pctrl,
functions[i].name,
functions[i].group_names,
functions[i].num_group_names,
functions[i].data);
}
return 0;
}
static int keembay_build_functions(struct keembay_pinctrl *kpc)
{
struct function_desc *keembay_funcs, *new_funcs;
int i;
/*
* Allocate maximum possible number of functions. Assume every pin
* being part of 8 (hw maximum) globally unique muxes.
*/
kpc->nfuncs = 0;
keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL);
if (!keembay_funcs)
return -ENOMEM;
/* Setup 1 function for each unique mux */
for (i = 0; i < kpc->npins; i++) {
const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
struct keembay_mux_desc *mux;
for (mux = pdesc->drv_data; mux->name; mux++) {
struct function_desc *fdesc;
/* Check if we already have function for this mux */
for (fdesc = keembay_funcs; fdesc->name; fdesc++) {
if (!strcmp(mux->name, fdesc->name)) {
fdesc->num_group_names++;
break;
}
}
/* Setup new function for this mux we didn't see before */
if (!fdesc->name) {
fdesc->name = mux->name;
fdesc->num_group_names = 1;
fdesc->data = &mux->mode;
kpc->nfuncs++;
}
}
}
/* Reallocate memory based on actual number of functions */
new_funcs = krealloc(keembay_funcs, kpc->nfuncs * sizeof(*new_funcs), GFP_KERNEL);
if (!new_funcs) {
kfree(keembay_funcs);
return -ENOMEM;
}
return keembay_add_functions(kpc, new_funcs);
}
static const struct keembay_pin_soc keembay_data = {
.pins = keembay_pins,
};
static const struct of_device_id keembay_pinctrl_match[] = {
{ .compatible = "intel,keembay-pinctrl", .data = &keembay_data },
{ }
};
MODULE_DEVICE_TABLE(of, keembay_pinctrl_match);
static int keembay_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct keembay_pinctrl *kpc;
int ret;
kpc = devm_kzalloc(dev, sizeof(*kpc), GFP_KERNEL);
if (!kpc)
return -ENOMEM;
kpc->dev = dev;
kpc->soc = device_get_match_data(dev);
kpc->base0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(kpc->base0))
return PTR_ERR(kpc->base0);
kpc->base1 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(kpc->base1))
return PTR_ERR(kpc->base1);
raw_spin_lock_init(&kpc->lock);
ret = keembay_pinctrl_reg(kpc, dev);
if (ret)
return ret;
ret = keembay_build_groups(kpc);
if (ret)
return ret;
ret = keembay_build_functions(kpc);
if (ret)
return ret;
ret = keembay_gpiochip_probe(kpc, pdev);
if (ret)
return ret;
platform_set_drvdata(pdev, kpc);
return 0;
}
static struct platform_driver keembay_pinctrl_driver = {
.probe = keembay_pinctrl_probe,
.driver = {
.name = "keembay-pinctrl",
.of_match_table = keembay_pinctrl_match,
},
};
module_platform_driver(keembay_pinctrl_driver);
MODULE_AUTHOR("Muhammad Husaini Zulkifli <[email protected]>");
MODULE_AUTHOR("Vijayakannan Ayyathurai <[email protected]>");
MODULE_AUTHOR("Lakshmi Sowjanya D <[email protected]>");
MODULE_DESCRIPTION("Intel Keem Bay SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-keembay.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Utils functions to implement the pincontrol driver.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <[email protected]>
*/
#include <linux/device.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "core.h"
#include "pinctrl-utils.h"
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, unsigned reserve)
{
unsigned old_num = *reserved_maps;
unsigned new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc_array(*map, new_num, sizeof(*new_map), GFP_KERNEL);
if (!new_map) {
dev_err(pctldev->dev, "krealloc(map) failed\n");
return -ENOMEM;
}
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_reserve_map);
int pinctrl_utils_add_map_mux(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function)
{
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = group;
(*map)[*num_maps].data.mux.function = function;
(*num_maps)++;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_mux);
int pinctrl_utils_add_map_configs(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
unsigned long *configs, unsigned num_configs,
enum pinctrl_map_type type)
{
unsigned long *dup_configs;
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;
(*map)[*num_maps].type = type;
(*map)[*num_maps].data.configs.group_or_pin = group;
(*map)[*num_maps].data.configs.configs = dup_configs;
(*map)[*num_maps].data.configs.num_configs = num_configs;
(*num_maps)++;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_map_configs);
int pinctrl_utils_add_config(struct pinctrl_dev *pctldev,
unsigned long **configs, unsigned *num_configs,
unsigned long config)
{
unsigned old_num = *num_configs;
unsigned new_num = old_num + 1;
unsigned long *new_configs;
new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
GFP_KERNEL);
if (!new_configs) {
dev_err(pctldev->dev, "krealloc(configs) failed\n");
return -ENOMEM;
}
new_configs[old_num] = config;
*configs = new_configs;
*num_configs = new_num;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_utils_add_config);
void pinctrl_utils_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++) {
switch (map[i].type) {
case PIN_MAP_TYPE_CONFIGS_GROUP:
case PIN_MAP_TYPE_CONFIGS_PIN:
kfree(map[i].data.configs.configs);
break;
default:
break;
}
}
kfree(map);
}
EXPORT_SYMBOL_GPL(pinctrl_utils_free_map);
|
linux-master
|
drivers/pinctrl/pinctrl-utils.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinconf driver for TI DA850/OMAP-L138/AM18XX pullup/pulldown groups
*
* Copyright (C) 2016 David Lechner
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#define DA850_PUPD_ENA 0x00
#define DA850_PUPD_SEL 0x04
struct da850_pupd_data {
void __iomem *base;
struct pinctrl_desc desc;
struct pinctrl_dev *pinctrl;
};
static const char * const da850_pupd_group_names[] = {
"cp0", "cp1", "cp2", "cp3", "cp4", "cp5", "cp6", "cp7",
"cp8", "cp9", "cp10", "cp11", "cp12", "cp13", "cp14", "cp15",
"cp16", "cp17", "cp18", "cp19", "cp20", "cp21", "cp22", "cp23",
"cp24", "cp25", "cp26", "cp27", "cp28", "cp29", "cp30", "cp31",
};
static int da850_pupd_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(da850_pupd_group_names);
}
static const char *da850_pupd_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return da850_pupd_group_names[selector];
}
static int da850_pupd_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
*num_pins = 0;
return 0;
}
static const struct pinctrl_ops da850_pupd_pctlops = {
.get_groups_count = da850_pupd_get_groups_count,
.get_group_name = da850_pupd_get_group_name,
.get_group_pins = da850_pupd_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int da850_pupd_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *config)
{
struct da850_pupd_data *data = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 val;
u16 arg;
val = readl(data->base + DA850_PUPD_ENA);
arg = !!(~val & BIT(selector));
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (arg) {
/* bias is disabled */
arg = 0;
break;
}
val = readl(data->base + DA850_PUPD_SEL);
if (param == PIN_CONFIG_BIAS_PULL_DOWN)
val = ~val;
arg = !!(val & BIT(selector));
break;
default:
return -EINVAL;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int da850_pupd_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
struct da850_pupd_data *data = pinctrl_dev_get_drvdata(pctldev);
u32 ena, sel;
enum pin_config_param param;
int i;
ena = readl(data->base + DA850_PUPD_ENA);
sel = readl(data->base + DA850_PUPD_SEL);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ena &= ~BIT(selector);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ena |= BIT(selector);
sel |= BIT(selector);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ena |= BIT(selector);
sel &= ~BIT(selector);
break;
default:
return -EINVAL;
}
}
writel(sel, data->base + DA850_PUPD_SEL);
writel(ena, data->base + DA850_PUPD_ENA);
return 0;
}
static const struct pinconf_ops da850_pupd_confops = {
.is_generic = true,
.pin_config_group_get = da850_pupd_pin_config_group_get,
.pin_config_group_set = da850_pupd_pin_config_group_set,
};
static int da850_pupd_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct da850_pupd_data *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->base)) {
dev_err(dev, "Could not map resource\n");
return PTR_ERR(data->base);
}
data->desc.name = dev_name(dev);
data->desc.pctlops = &da850_pupd_pctlops;
data->desc.confops = &da850_pupd_confops;
data->desc.owner = THIS_MODULE;
data->pinctrl = devm_pinctrl_register(dev, &data->desc, data);
if (IS_ERR(data->pinctrl)) {
dev_err(dev, "Failed to register pinctrl\n");
return PTR_ERR(data->pinctrl);
}
platform_set_drvdata(pdev, data);
return 0;
}
static const struct of_device_id da850_pupd_of_match[] = {
{ .compatible = "ti,da850-pupd" },
{ }
};
MODULE_DEVICE_TABLE(of, da850_pupd_of_match);
static struct platform_driver da850_pupd_driver = {
.driver = {
.name = "ti-da850-pupd",
.of_match_table = da850_pupd_of_match,
},
.probe = da850_pupd_probe,
};
module_platform_driver(da850_pupd_driver);
MODULE_AUTHOR("David Lechner <[email protected]>");
MODULE_DESCRIPTION("TI DA850/OMAP-L138/AM18XX pullup/pulldown configuration");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-da850-pupd.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Dialog DA9062 pinctrl and GPIO driver.
* Based on DA9055 GPIO driver.
*
* TODO:
* - add pinmux and pinctrl support (gpio alternate mode)
*
* Documents:
* [1] https://www.dialog-semiconductor.com/sites/default/files/da9062_datasheet_3v6.pdf
*
* Copyright (C) 2019 Pengutronix, Marco Felsch <[email protected]>
*/
#include <linux/bits.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/da9062/core.h>
#include <linux/mfd/da9062/registers.h>
/*
* We need this get the gpio_desc from a <gpio_chip,offset> tuple to decide if
* the gpio is active low without a vendor specific dt-binding.
*/
#include "../gpio/gpiolib.h"
#define DA9062_TYPE(offset) (4 * (offset % 2))
#define DA9062_PIN_SHIFT(offset) (4 * (offset % 2))
#define DA9062_PIN_ALTERNATE 0x00 /* gpio alternate mode */
#define DA9062_PIN_GPI 0x01 /* gpio in */
#define DA9062_PIN_GPO_OD 0x02 /* gpio out open-drain */
#define DA9062_PIN_GPO_PP 0x03 /* gpio out push-pull */
#define DA9062_GPIO_NUM 5
struct da9062_pctl {
struct da9062 *da9062;
struct gpio_chip gc;
unsigned int pin_config[DA9062_GPIO_NUM];
};
static int da9062_pctl_get_pin_mode(struct da9062_pctl *pctl,
unsigned int offset)
{
struct regmap *regmap = pctl->da9062->regmap;
int ret, val;
ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val);
if (ret < 0)
return ret;
val >>= DA9062_PIN_SHIFT(offset);
val &= DA9062AA_GPIO0_PIN_MASK;
return val;
}
static int da9062_pctl_set_pin_mode(struct da9062_pctl *pctl,
unsigned int offset, unsigned int mode_req)
{
struct regmap *regmap = pctl->da9062->regmap;
unsigned int mode = mode_req;
unsigned int mask;
int ret;
mode &= DA9062AA_GPIO0_PIN_MASK;
mode <<= DA9062_PIN_SHIFT(offset);
mask = DA9062AA_GPIO0_PIN_MASK << DA9062_PIN_SHIFT(offset);
ret = regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1),
mask, mode);
if (!ret)
pctl->pin_config[offset] = mode_req;
return ret;
}
static int da9062_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
struct regmap *regmap = pctl->da9062->regmap;
int gpio_mode, val;
int ret;
gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
if (gpio_mode < 0)
return gpio_mode;
switch (gpio_mode) {
case DA9062_PIN_ALTERNATE:
return -ENOTSUPP;
case DA9062_PIN_GPI:
ret = regmap_read(regmap, DA9062AA_STATUS_B, &val);
if (ret < 0)
return ret;
break;
case DA9062_PIN_GPO_OD:
case DA9062_PIN_GPO_PP:
ret = regmap_read(regmap, DA9062AA_GPIO_MODE0_4, &val);
if (ret < 0)
return ret;
}
return !!(val & BIT(offset));
}
static void da9062_gpio_set(struct gpio_chip *gc, unsigned int offset,
int value)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
struct regmap *regmap = pctl->da9062->regmap;
regmap_update_bits(regmap, DA9062AA_GPIO_MODE0_4, BIT(offset),
value << offset);
}
static int da9062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
int gpio_mode;
gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
if (gpio_mode < 0)
return gpio_mode;
switch (gpio_mode) {
case DA9062_PIN_ALTERNATE:
return -ENOTSUPP;
case DA9062_PIN_GPI:
return GPIO_LINE_DIRECTION_IN;
case DA9062_PIN_GPO_OD:
case DA9062_PIN_GPO_PP:
return GPIO_LINE_DIRECTION_OUT;
}
return -EINVAL;
}
static int da9062_gpio_direction_input(struct gpio_chip *gc,
unsigned int offset)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
struct regmap *regmap = pctl->da9062->regmap;
struct gpio_desc *desc = gpiochip_get_desc(gc, offset);
unsigned int gpi_type;
int ret;
ret = da9062_pctl_set_pin_mode(pctl, offset, DA9062_PIN_GPI);
if (ret)
return ret;
/*
* If the gpio is active low we should set it in hw too. No worries
* about gpio_get() because we read and return the gpio-level. So the
* gpiolib active_low handling is still correct.
*
* 0 - active low, 1 - active high
*/
gpi_type = !gpiod_is_active_low(desc);
return regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1),
DA9062AA_GPIO0_TYPE_MASK << DA9062_TYPE(offset),
gpi_type << DA9062_TYPE(offset));
}
static int da9062_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
unsigned int pin_config = pctl->pin_config[offset];
int ret;
ret = da9062_pctl_set_pin_mode(pctl, offset, pin_config);
if (ret)
return ret;
da9062_gpio_set(gc, offset, value);
return 0;
}
static int da9062_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
struct regmap *regmap = pctl->da9062->regmap;
int gpio_mode;
/*
* We need to meet the following restrictions [1, Figure 18]:
* - PIN_CONFIG_BIAS_PULL_DOWN -> only allowed if the pin is used as
* gpio input
* - PIN_CONFIG_BIAS_PULL_UP -> only allowed if the pin is used as
* gpio output open-drain.
*/
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_BIAS_DISABLE:
return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
BIT(offset), 0);
case PIN_CONFIG_BIAS_PULL_DOWN:
gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
if (gpio_mode < 0)
return -EINVAL;
else if (gpio_mode != DA9062_PIN_GPI)
return -ENOTSUPP;
return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
BIT(offset), BIT(offset));
case PIN_CONFIG_BIAS_PULL_UP:
gpio_mode = da9062_pctl_get_pin_mode(pctl, offset);
if (gpio_mode < 0)
return -EINVAL;
else if (gpio_mode != DA9062_PIN_GPO_OD)
return -ENOTSUPP;
return regmap_update_bits(regmap, DA9062AA_CONFIG_K,
BIT(offset), BIT(offset));
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return da9062_pctl_set_pin_mode(pctl, offset,
DA9062_PIN_GPO_OD);
case PIN_CONFIG_DRIVE_PUSH_PULL:
return da9062_pctl_set_pin_mode(pctl, offset,
DA9062_PIN_GPO_PP);
default:
return -ENOTSUPP;
}
}
static int da9062_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
{
struct da9062_pctl *pctl = gpiochip_get_data(gc);
struct da9062 *da9062 = pctl->da9062;
return regmap_irq_get_virq(da9062->regmap_irq,
DA9062_IRQ_GPI0 + offset);
}
static const struct gpio_chip reference_gc = {
.owner = THIS_MODULE,
.get = da9062_gpio_get,
.set = da9062_gpio_set,
.get_direction = da9062_gpio_get_direction,
.direction_input = da9062_gpio_direction_input,
.direction_output = da9062_gpio_direction_output,
.set_config = da9062_gpio_set_config,
.to_irq = da9062_gpio_to_irq,
.can_sleep = true,
.ngpio = DA9062_GPIO_NUM,
.base = -1,
};
static int da9062_pctl_probe(struct platform_device *pdev)
{
struct device *parent = pdev->dev.parent;
struct da9062_pctl *pctl;
int i;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->da9062 = dev_get_drvdata(parent);
if (!pctl->da9062)
return -EINVAL;
if (!device_property_present(parent, "gpio-controller"))
return 0;
for (i = 0; i < ARRAY_SIZE(pctl->pin_config); i++)
pctl->pin_config[i] = DA9062_PIN_GPO_PP;
/*
* Currently the driver handles only the GPIO support. The
* pinctrl/pinmux support can be added later if needed.
*/
pctl->gc = reference_gc;
pctl->gc.label = dev_name(&pdev->dev);
pctl->gc.parent = &pdev->dev;
platform_set_drvdata(pdev, pctl);
return devm_gpiochip_add_data(&pdev->dev, &pctl->gc, pctl);
}
static struct platform_driver da9062_pctl_driver = {
.probe = da9062_pctl_probe,
.driver = {
.name = "da9062-gpio",
},
};
module_platform_driver(da9062_pctl_driver);
MODULE_AUTHOR("Marco Felsch <[email protected]>");
MODULE_DESCRIPTION("DA9062 PMIC pinctrl and GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:da9062-gpio");
|
linux-master
|
drivers/pinctrl/pinctrl-da9062.c
|
/*
* Driver for the Gemini pin controller
*
* Copyright (C) 2017 Linus Walleij <[email protected]>
*
* This is a group-only pin controller.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-utils.h"
#define DRIVER_NAME "pinctrl-gemini"
/**
* struct gemini_pin_conf - information about configuring a pin
* @pin: the pin number
* @reg: config register
* @mask: the bits affecting the configuration of the pin
*/
struct gemini_pin_conf {
unsigned int pin;
u32 reg;
u32 mask;
};
/**
* struct gemini_pmx - state holder for the gemini pin controller
* @dev: a pointer back to containing device
* @virtbase: the offset to the controller in virtual memory
* @map: regmap to access registers
* @is_3512: whether the SoC/package is the 3512 variant
* @is_3516: whether the SoC/package is the 3516 variant
* @flash_pin: whether the flash pin (extended pins for parallel
* flash) is set
* @confs: pin config information
* @nconfs: number of pin config information items
*/
struct gemini_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
struct regmap *map;
bool is_3512;
bool is_3516;
bool flash_pin;
const struct gemini_pin_conf *confs;
unsigned int nconfs;
};
/**
* struct gemini_pin_group - describes a Gemini pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @mask: bits to clear to enable this when doing pin muxing
* @value: bits to set to enable this when doing pin muxing
* @driving_mask: bitmask for the IO Pad driving register for this
* group, if it supports altering the driving strength of
* its lines.
*/
struct gemini_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
u32 mask;
u32 value;
u32 driving_mask;
};
/* Some straight-forward control registers */
#define GLOBAL_WORD_ID 0x00
#define GLOBAL_STATUS 0x04
#define GLOBAL_STATUS_FLPIN BIT(20)
#define GLOBAL_IODRIVE 0x10
#define GLOBAL_GMAC_CTRL_SKEW 0x1c
#define GLOBAL_GMAC0_DATA_SKEW 0x20
#define GLOBAL_GMAC1_DATA_SKEW 0x24
/*
* Global Miscellaneous Control Register
* This register controls all Gemini pad/pin multiplexing
*
* It is a tricky register though:
* - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
* be brought back online, so it means permanent disablement of the
* corresponding pads.
* - For the bits named *_DISABLE, once you enable something, it cannot be
* DISABLED again. So you select a flash configuration once, and then
* you are stuck with it.
*/
#define GLOBAL_MISC_CTRL 0x30
#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
/* Not really used */
#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
/* Activated with GMAC1 */
#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
/* This will be the default */
#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
#define TVC_CLK_PAD_ENABLE BIT(20)
#define PCI_CLK_PAD_ENABLE BIT(17)
#define LPC_CLK_PAD_ENABLE BIT(16)
#define TVC_PADS_ENABLE BIT(9)
#define SSP_PADS_ENABLE BIT(8)
#define LCD_PADS_ENABLE BIT(7)
#define LPC_PADS_ENABLE BIT(6)
#define PCI_PADS_ENABLE BIT(5)
#define IDE_PADS_ENABLE BIT(4)
#define DRAM_PADS_POWERDOWN BIT(3)
#define NAND_PADS_DISABLE BIT(2)
#define PFLASH_PADS_DISABLE BIT(1)
#define SFLASH_PADS_DISABLE BIT(0)
#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
#define PADS_MAXBIT 27
/* Ordered by bit index */
static const char * const gemini_padgroups[] = {
"serial flash",
"parallel flash",
"NAND flash",
"DRAM",
"IDE",
"PCI",
"LPC",
"LCD",
"SSP",
"TVC",
NULL, NULL, NULL, NULL, NULL, NULL,
"LPC CLK",
"PCI CLK",
NULL, NULL,
"TVC CLK",
NULL, NULL, NULL, NULL, NULL,
"GMAC1",
};
static const struct pinctrl_pin_desc gemini_3512_pins[] = {
/* Row A */
PINCTRL_PIN(0, "A1 VREF CTRL"),
PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
PINCTRL_PIN(2, "A3 DRAM CK"),
PINCTRL_PIN(3, "A4 DRAM CK N"),
PINCTRL_PIN(4, "A5 DRAM A5"),
PINCTRL_PIN(5, "A6 DRAM CKE"),
PINCTRL_PIN(6, "A7 DRAM DQ11"),
PINCTRL_PIN(7, "A8 DRAM DQ0"),
PINCTRL_PIN(8, "A9 DRAM DQ5"),
PINCTRL_PIN(9, "A10 DRAM DQ6"),
PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
PINCTRL_PIN(11, "A12 DRAM BA1"),
PINCTRL_PIN(12, "A13 DRAM A2"),
PINCTRL_PIN(13, "A14 PCI GNT1 N"),
PINCTRL_PIN(14, "A15 PCI REQ9 N"),
PINCTRL_PIN(15, "A16 PCI REQ2 N"),
PINCTRL_PIN(16, "A17 PCI REQ3 N"),
PINCTRL_PIN(17, "A18 PCI AD31"),
/* Row B */
PINCTRL_PIN(18, "B1 VCCK CTRL"),
PINCTRL_PIN(19, "B2 PWR EN"),
PINCTRL_PIN(20, "B3 RTC CLKI"),
PINCTRL_PIN(21, "B4 DRAM A4"),
PINCTRL_PIN(22, "B5 DRAM A6"),
PINCTRL_PIN(23, "B6 DRAM A12"),
PINCTRL_PIN(24, "B7 DRAM DQS1"),
PINCTRL_PIN(25, "B8 DRAM DQ15"),
PINCTRL_PIN(26, "B9 DRAM DQ4"),
PINCTRL_PIN(27, "B10 DRAM DQS0"),
PINCTRL_PIN(28, "B11 DRAM WE N"),
PINCTRL_PIN(29, "B12 DRAM A10"),
PINCTRL_PIN(30, "B13 DRAM A3"),
PINCTRL_PIN(31, "B14 PCI GNT0 N"),
PINCTRL_PIN(32, "B15 PCI GNT3 N"),
PINCTRL_PIN(33, "B16 PCI REQ1 N"),
PINCTRL_PIN(34, "B17 PCI AD30"),
PINCTRL_PIN(35, "B18 PCI AD29"),
/* Row C */
PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
PINCTRL_PIN(37, "C2 XTALI"),
PINCTRL_PIN(38, "C3 PWR BTN"),
PINCTRL_PIN(39, "C4 RTC CLKO"),
PINCTRL_PIN(40, "C5 DRAM A7"),
PINCTRL_PIN(41, "C6 DRAM A11"),
PINCTRL_PIN(42, "C7 DRAM DQ10"),
PINCTRL_PIN(43, "C8 DRAM DQ14"),
PINCTRL_PIN(44, "C9 DRAM DQ3"),
PINCTRL_PIN(45, "C10 DRAM DQ7"),
PINCTRL_PIN(46, "C11 DRAM CAS N"),
PINCTRL_PIN(47, "C12 DRAM A0"),
PINCTRL_PIN(48, "C13 PCI INT0 N"),
PINCTRL_PIN(49, "C14 EXT RESET N"),
PINCTRL_PIN(50, "C15 PCI GNT2 N"),
PINCTRL_PIN(51, "C16 PCI AD28"),
PINCTRL_PIN(52, "C17 PCI AD27"),
PINCTRL_PIN(53, "C18 PCI AD26"),
/* Row D */
PINCTRL_PIN(54, "D1 AVCCKHA"),
PINCTRL_PIN(55, "D2 AGNDIOHA"),
PINCTRL_PIN(56, "D3 XTALO"),
PINCTRL_PIN(57, "D4 AVCC3IOHA"),
PINCTRL_PIN(58, "D5 DRAM A8"),
PINCTRL_PIN(59, "D6 DRAM A9"),
PINCTRL_PIN(60, "D7 DRAM DQ9"),
PINCTRL_PIN(61, "D8 DRAM DQ13"),
PINCTRL_PIN(62, "D9 DRAM DQ2"),
PINCTRL_PIN(63, "D10 DRAM A13"),
PINCTRL_PIN(64, "D11 DRAM RAS N"),
PINCTRL_PIN(65, "D12 DRAM A1"),
PINCTRL_PIN(66, "D13 PCI INTC N"),
PINCTRL_PIN(67, "D14 PCI CLK"),
PINCTRL_PIN(68, "D15 PCI AD25"),
PINCTRL_PIN(69, "D16 PCI AD24"),
PINCTRL_PIN(70, "D17 PCI CBE3 N"),
PINCTRL_PIN(71, "D18 PCI AD23"),
/* Row E */
PINCTRL_PIN(72, "E1 AVCC3IOHA"),
PINCTRL_PIN(73, "E2 EBG"),
PINCTRL_PIN(74, "E3 AVCC3IOHB"),
PINCTRL_PIN(75, "E4 REXT"),
PINCTRL_PIN(76, "E5 GND"),
PINCTRL_PIN(77, "E6 DRAM DQM1"),
PINCTRL_PIN(78, "E7 DRAM DQ8"),
PINCTRL_PIN(79, "E8 DRAM DQ12"),
PINCTRL_PIN(80, "E9 DRAM DQ1"),
PINCTRL_PIN(81, "E10 DRAM DQM0"),
PINCTRL_PIN(82, "E11 DRAM BA0"),
PINCTRL_PIN(83, "E12 PCI INTA N"),
PINCTRL_PIN(84, "E13 PCI INTB N"),
PINCTRL_PIN(85, "E14 GND"),
PINCTRL_PIN(86, "E15 PCI AD22"),
PINCTRL_PIN(87, "E16 PCI AD21"),
PINCTRL_PIN(88, "E17 PCI AD20"),
PINCTRL_PIN(89, "E18 PCI AD19"),
/* Row F */
PINCTRL_PIN(90, "F1 SATA0 RXDP"),
PINCTRL_PIN(91, "F2 SATA0 RXDN"),
PINCTRL_PIN(92, "F3 AGNDK 0"),
PINCTRL_PIN(93, "F4 AVCC3 S"),
PINCTRL_PIN(94, "F5 AVCCK P"),
PINCTRL_PIN(95, "F6 GND"),
PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
PINCTRL_PIN(98, "F9 V1"),
PINCTRL_PIN(99, "F10 V1"),
PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
PINCTRL_PIN(102, "F13 GND"),
PINCTRL_PIN(103, "F14 PCI AD18"),
PINCTRL_PIN(104, "F15 PCI AD17"),
PINCTRL_PIN(105, "F16 PCI AD16"),
PINCTRL_PIN(106, "F17 PCI CBE2 N"),
PINCTRL_PIN(107, "F18 PCI FRAME N"),
/* Row G */
PINCTRL_PIN(108, "G1 SATA0 TXDP"),
PINCTRL_PIN(109, "G2 SATA0 TXDN"),
PINCTRL_PIN(110, "G3 AGNDK 1"),
PINCTRL_PIN(111, "G4 AVCCK 0"),
PINCTRL_PIN(112, "G5 TEST CLKOUT"),
PINCTRL_PIN(113, "G6 AGND"),
PINCTRL_PIN(114, "G7 GND"),
PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
PINCTRL_PIN(116, "G9 V1"),
PINCTRL_PIN(117, "G10 V1"),
PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
PINCTRL_PIN(119, "G12 GND"),
PINCTRL_PIN(120, "G13 VCC3IOHA"),
PINCTRL_PIN(121, "G14 PCI IRDY N"),
PINCTRL_PIN(122, "G15 PCI TRDY N"),
PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
PINCTRL_PIN(124, "G17 PCI STOP N"),
PINCTRL_PIN(125, "G18 PCI PAR"),
/* Row H */
PINCTRL_PIN(126, "H1 SATA1 TXDP"),
PINCTRL_PIN(127, "H2 SATA1 TXDN"),
PINCTRL_PIN(128, "H3 AGNDK 2"),
PINCTRL_PIN(129, "H4 AVCCK 1"),
PINCTRL_PIN(130, "H5 AVCCK S"),
PINCTRL_PIN(131, "H6 AVCCKHB"),
PINCTRL_PIN(132, "H7 AGND"),
PINCTRL_PIN(133, "H8 GND"),
PINCTRL_PIN(134, "H9 GND"),
PINCTRL_PIN(135, "H10 GND"),
PINCTRL_PIN(136, "H11 GND"),
PINCTRL_PIN(137, "H12 VCC3IOHA"),
PINCTRL_PIN(138, "H13 VCC3IOHA"),
PINCTRL_PIN(139, "H14 PCI CBE1 N"),
PINCTRL_PIN(140, "H15 PCI AD15"),
PINCTRL_PIN(141, "H16 PCI AD14"),
PINCTRL_PIN(142, "H17 PCI AD13"),
PINCTRL_PIN(143, "H18 PCI AD12"),
/* Row J (for some reason I is skipped) */
PINCTRL_PIN(144, "J1 SATA1 RXDP"),
PINCTRL_PIN(145, "J2 SATA1 RXDN"),
PINCTRL_PIN(146, "J3 AGNDK 3"),
PINCTRL_PIN(147, "J4 AVCCK 2"),
PINCTRL_PIN(148, "J5 IDE DA1"),
PINCTRL_PIN(149, "J6 V1"),
PINCTRL_PIN(150, "J7 V1"),
PINCTRL_PIN(151, "J8 GND"),
PINCTRL_PIN(152, "J9 GND"),
PINCTRL_PIN(153, "J10 GND"),
PINCTRL_PIN(154, "J11 GND"),
PINCTRL_PIN(155, "J12 V1"),
PINCTRL_PIN(156, "J13 V1"),
PINCTRL_PIN(157, "J14 PCI AD11"),
PINCTRL_PIN(158, "J15 PCI AD10"),
PINCTRL_PIN(159, "J16 PCI AD9"),
PINCTRL_PIN(160, "J17 PCI AD8"),
PINCTRL_PIN(161, "J18 PCI CBE0 N"),
/* Row K */
PINCTRL_PIN(162, "K1 IDE CS1 N"),
PINCTRL_PIN(163, "K2 IDE CS0 N"),
PINCTRL_PIN(164, "K3 AVCCK 3"),
PINCTRL_PIN(165, "K4 IDE DA2"),
PINCTRL_PIN(166, "K5 IDE DA0"),
PINCTRL_PIN(167, "K6 V1"),
PINCTRL_PIN(168, "K7 V1"),
PINCTRL_PIN(169, "K8 GND"),
PINCTRL_PIN(170, "K9 GND"),
PINCTRL_PIN(171, "K10 GND"),
PINCTRL_PIN(172, "K11 GND"),
PINCTRL_PIN(173, "K12 V1"),
PINCTRL_PIN(174, "K13 V1"),
PINCTRL_PIN(175, "K14 PCI AD3"),
PINCTRL_PIN(176, "K15 PCI AD4"),
PINCTRL_PIN(177, "K16 PCI AD5"),
PINCTRL_PIN(178, "K17 PCI AD6"),
PINCTRL_PIN(179, "K18 PCI AD7"),
/* Row L */
PINCTRL_PIN(180, "L1 IDE INTRQ"),
PINCTRL_PIN(181, "L2 IDE DMACK N"),
PINCTRL_PIN(182, "L3 IDE IORDY"),
PINCTRL_PIN(183, "L4 IDE DIOR N"),
PINCTRL_PIN(184, "L5 IDE DIOW N"),
PINCTRL_PIN(185, "L6 VCC3IOHA"),
PINCTRL_PIN(186, "L7 VCC3IOHA"),
PINCTRL_PIN(187, "L8 GND"),
PINCTRL_PIN(188, "L9 GND"),
PINCTRL_PIN(189, "L10 GND"),
PINCTRL_PIN(190, "L11 GND"),
PINCTRL_PIN(191, "L12 VCC3IOHA"),
PINCTRL_PIN(192, "L13 VCC3IOHA"),
PINCTRL_PIN(193, "L14 GPIO0 30"),
PINCTRL_PIN(194, "L15 GPIO0 31"),
PINCTRL_PIN(195, "L16 PCI AD0"),
PINCTRL_PIN(196, "L17 PCI AD1"),
PINCTRL_PIN(197, "L18 PCI AD2"),
/* Row M */
PINCTRL_PIN(198, "M1 IDE DMARQ"),
PINCTRL_PIN(199, "M2 IDE DD15"),
PINCTRL_PIN(200, "M3 IDE DD0"),
PINCTRL_PIN(201, "M4 IDE DD14"),
PINCTRL_PIN(202, "M5 IDE DD1"),
PINCTRL_PIN(203, "M6 VCC3IOHA"),
PINCTRL_PIN(204, "M7 GND"),
PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
PINCTRL_PIN(206, "M9 V1"),
PINCTRL_PIN(207, "M10 V1"),
PINCTRL_PIN(208, "M11 VCC3IOHA"),
PINCTRL_PIN(209, "M12 GND"),
PINCTRL_PIN(210, "M13 VCC3IOHA"),
PINCTRL_PIN(211, "M14 GPIO0 25"),
PINCTRL_PIN(212, "M15 GPIO0 26"),
PINCTRL_PIN(213, "M16 GPIO0 27"),
PINCTRL_PIN(214, "M17 GPIO0 28"),
PINCTRL_PIN(215, "M18 GPIO0 29"),
/* Row N */
PINCTRL_PIN(216, "N1 IDE DD13"),
PINCTRL_PIN(217, "N2 IDE DD2"),
PINCTRL_PIN(218, "N3 IDE DD12"),
PINCTRL_PIN(219, "N4 IDE DD3"),
PINCTRL_PIN(220, "N5 IDE DD11"),
PINCTRL_PIN(221, "N6 GND"),
PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
PINCTRL_PIN(224, "N9 V1"),
PINCTRL_PIN(225, "N10 V1"),
PINCTRL_PIN(226, "N11 VCC3IOHA"),
PINCTRL_PIN(227, "N12 VCC3IOHA"),
PINCTRL_PIN(228, "N13 GND"),
PINCTRL_PIN(229, "N14 GPIO0 20"),
PINCTRL_PIN(230, "N15 GPIO0 21"),
PINCTRL_PIN(231, "N16 GPIO0 22"),
PINCTRL_PIN(232, "N17 GPIO0 23"),
PINCTRL_PIN(233, "N18 GPIO0 24"),
/* Row P (for some reason O is skipped) */
PINCTRL_PIN(234, "P1 IDE DD4"),
PINCTRL_PIN(235, "P2 IDE DD10"),
PINCTRL_PIN(236, "P3 IDE DD5"),
PINCTRL_PIN(237, "P4 IDE DD9"),
PINCTRL_PIN(238, "P5 GND"),
PINCTRL_PIN(239, "P6 USB XSCO"),
PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
PINCTRL_PIN(243, "P10 GMAC1 TXC"),
PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
PINCTRL_PIN(245, "P12 MODE SEL 1"),
PINCTRL_PIN(246, "P13 GPIO1 28"),
PINCTRL_PIN(247, "P14 GND"),
PINCTRL_PIN(248, "P15 GPIO0 5"),
PINCTRL_PIN(249, "P16 GPIO0 17"),
PINCTRL_PIN(250, "P17 GPIO0 18"),
PINCTRL_PIN(251, "P18 GPIO0 19"),
/* Row R (for some reason Q is skipped) */
PINCTRL_PIN(252, "R1 IDE DD6"),
PINCTRL_PIN(253, "R2 IDE DD8"),
PINCTRL_PIN(254, "R3 IDE DD7"),
PINCTRL_PIN(255, "R4 IDE RESET N"),
PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
PINCTRL_PIN(257, "R6 USB XSCI"),
PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
PINCTRL_PIN(263, "R12 MODE SEL 0"),
PINCTRL_PIN(264, "R13 MODE SEL 3"),
PINCTRL_PIN(265, "R14 GPIO0 0"),
PINCTRL_PIN(266, "R15 GPIO0 4"),
PINCTRL_PIN(267, "R16 GPIO0 9"),
PINCTRL_PIN(268, "R17 GPIO0 15"),
PINCTRL_PIN(269, "R18 GPIO0 16"),
/* Row T (for some reason S is skipped) */
PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
PINCTRL_PIN(271, "T2 ICE0 IDO"),
PINCTRL_PIN(272, "T3 ICE0 ICK"),
PINCTRL_PIN(273, "T4 ICE0 IMS"),
PINCTRL_PIN(274, "T5 ICE0 IDI"),
PINCTRL_PIN(275, "T6 USB RREF"),
PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
PINCTRL_PIN(277, "T8 GMAC0 RXC"),
PINCTRL_PIN(278, "T9 GMAC0 CRS"),
PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
PINCTRL_PIN(280, "T11 GMAC1 RXC"),
PINCTRL_PIN(281, "T12 GMAC1 CRS"),
PINCTRL_PIN(282, "T13 EXT CLK"),
PINCTRL_PIN(283, "T14 GPIO1 31"),
PINCTRL_PIN(284, "T15 GPIO0 3"),
PINCTRL_PIN(285, "T16 GPIO0 8"),
PINCTRL_PIN(286, "T17 GPIO0 12"),
PINCTRL_PIN(287, "T18 GPIO0 14"),
/* Row U */
PINCTRL_PIN(288, "U1 ICE0 IRST N"),
PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
PINCTRL_PIN(290, "U3 USB0 DP"),
PINCTRL_PIN(291, "U4 USB VCCA U20"),
PINCTRL_PIN(292, "U5 USB1 DP"),
PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
PINCTRL_PIN(296, "U9 GMAC1 COL"),
PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
PINCTRL_PIN(300, "U13 MODE SEL 2"),
PINCTRL_PIN(301, "U14 GPIO1 30"),
PINCTRL_PIN(302, "U15 GPIO0 2"),
PINCTRL_PIN(303, "U16 GPIO0 7"),
PINCTRL_PIN(304, "U17 GPIO0 11"),
PINCTRL_PIN(305, "U18 GPIO0 13"),
/* Row V */
PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
PINCTRL_PIN(307, "V2 USB0 DM"),
PINCTRL_PIN(308, "V3 USB GNDA U20"),
PINCTRL_PIN(309, "V4 USB1 DM"),
PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
PINCTRL_PIN(311, "V6 GMAC0 COL"),
PINCTRL_PIN(312, "V7 GMAC0 TXC"),
PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
PINCTRL_PIN(314, "V9 REF CLK"),
PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
PINCTRL_PIN(318, "V13 M30 CLK"),
PINCTRL_PIN(319, "V14 GPIO1 29"),
PINCTRL_PIN(320, "V15 GPIO0 1"),
PINCTRL_PIN(321, "V16 GPIO0 6"),
PINCTRL_PIN(322, "V17 GPIO0 10"),
PINCTRL_PIN(323, "V18 SYS RESET N"),
};
/* Digital ground */
static const unsigned int gnd_3512_pins[] = {
76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
};
static const unsigned int dram_3512_pins[] = {
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
78, 79, 80, 81, 82
};
static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
static const unsigned int system_3512_pins[] = {
318, 264, 300, 245, 263, 282, 314, 323, 49,
};
static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
static const unsigned int ide_3512_pins[] = {
162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
};
static const unsigned int sata_3512_pins[] = {
75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
128, 127, 126, 147, 146, 145, 144, 164
};
static const unsigned int usb_3512_pins[] = {
306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
};
/* GMII, ethernet pins */
static const unsigned int gmii_gmac0_3512_pins[] = {
240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
};
static const unsigned int gmii_gmac1_3512_pins[] = {
243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
};
static const unsigned int pci_3512_pins[] = {
13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
178, 179, 195, 196, 197
};
/*
* Apparently the LPC interface is using the PCICLK for the clocking so
* PCI needs to be active at the same time.
*/
static const unsigned int lpc_3512_pins[] = {
285, /* LPC_LAD[0] */
304, /* LPC_SERIRQ */
286, /* LPC_LAD[2] */
305, /* LPC_LFRAME# */
287, /* LPC_LAD[3] */
268, /* LPC_LAD[1] */
};
/* Character LCD */
static const unsigned int lcd_3512_pins[] = {
262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
};
static const unsigned int ssp_3512_pins[] = {
285, /* SSP_97RST# SSP AC97 Reset, active low */
304, /* SSP_FSC */
286, /* SSP_ECLK */
305, /* SSP_TXD */
287, /* SSP_RXD */
268, /* SSP_SCLK */
};
static const unsigned int uart_rxtx_3512_pins[] = {
267, /* UART_SIN serial input, RX */
322, /* UART_SOUT serial output, TX */
};
static const unsigned int uart_modem_3512_pins[] = {
285, /* UART_NDCD DCD carrier detect */
304, /* UART_NDTR DTR data terminal ready */
286, /* UART_NDSR DSR data set ready */
305, /* UART_NRTS RTS request to send */
287, /* UART_NCTS CTS clear to send */
268, /* UART_NRI RI ring indicator */
};
static const unsigned int tvc_3512_pins[] = {
246, /* TVC_DATA[0] */
319, /* TVC_DATA[1] */
301, /* TVC_DATA[2] */
283, /* TVC_DATA[3] */
320, /* TVC_DATA[4] */
302, /* TVC_DATA[5] */
284, /* TVC_DATA[6] */
266, /* TVC_DATA[7] */
};
static const unsigned int tvc_clk_3512_pins[] = {
265, /* TVC_CLK */
};
/* NAND flash pins */
static const unsigned int nflash_3512_pins[] = {
199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
253, 254, 249, 250, 232, 233, 211, 193, 194
};
/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
static const unsigned int pflash_3512_pins[] = {
162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
214, 215, 193, 194
};
/*
* The parallel flash can be set up in a 26-bit address bus mode exposing
* A[0-15] (A[15] takes the place of ALE), but it has the
* side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
* used at the same time.
*/
static const unsigned int pflash_3512_pins_extended[] = {
162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
214, 215, 193, 194,
/* The extra pins */
296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
265,
};
/* Serial flash pins CE0, CE1, DI, DO, CK */
static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
/* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */
static const unsigned int gpio0a_3512_pins[] = { 265 };
/* The GPIO0B (1-4) pins overlap with TVC and ICE */
static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
/* The GPIO0C (5-7) pins overlap with ICE */
static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
/* The GPIO0D (9,10) pins overlap with UART RX/TX */
static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
/* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
/* The GPIO0F (16) pins overlap with LCD */
static const unsigned int gpio0f_3512_pins[] = { 269 };
/* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
/* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
/* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
/* The GPIO0J (23) pins overlap with all flash */
static const unsigned int gpio0j_3512_pins[] = { 232 };
/* The GPIO0K (24,25) pins overlap with all flash and LCD */
static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
/* The GPIO0L (26-29) pins overlap with parallel flash */
static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
/* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
/* The GPIO1B (5-10, 27) pins overlap with just IDE */
static const unsigned int gpio1b_3512_pins[] = {
180, 181, 182, 183, 184, 198, 255
};
/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
static const unsigned int gpio1c_3512_pins[] = {
199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
252, 253, 254
};
/* The GPIO1D (28-31) pins overlap with LCD and TVC */
static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
/* The GPIO2C (8-31) pins overlap with PCI */
static const unsigned int gpio2c_3512_pins[] = {
17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
140, 141, 142, 143, 157, 158, 159, 160
};
/* Groups for the 3512 SoC/package */
static const struct gemini_pin_group gemini_3512_pin_groups[] = {
{
.name = "gndgrp",
.pins = gnd_3512_pins,
.num_pins = ARRAY_SIZE(gnd_3512_pins),
},
{
.name = "dramgrp",
.pins = dram_3512_pins,
.num_pins = ARRAY_SIZE(dram_3512_pins),
.mask = DRAM_PADS_POWERDOWN,
},
{
.name = "rtcgrp",
.pins = rtc_3512_pins,
.num_pins = ARRAY_SIZE(rtc_3512_pins),
},
{
.name = "powergrp",
.pins = power_3512_pins,
.num_pins = ARRAY_SIZE(power_3512_pins),
},
{
.name = "systemgrp",
.pins = system_3512_pins,
.num_pins = ARRAY_SIZE(system_3512_pins),
},
{
.name = "vcontrolgrp",
.pins = vcontrol_3512_pins,
.num_pins = ARRAY_SIZE(vcontrol_3512_pins),
},
{
.name = "icegrp",
.pins = ice_3512_pins,
.num_pins = ARRAY_SIZE(ice_3512_pins),
/* Conflict with some GPIO groups */
},
{
.name = "idegrp",
.pins = ide_3512_pins,
.num_pins = ARRAY_SIZE(ide_3512_pins),
/* Conflict with all flash usage */
.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
.driving_mask = GENMASK(21, 20),
},
{
.name = "satagrp",
.pins = sata_3512_pins,
.num_pins = ARRAY_SIZE(sata_3512_pins),
},
{
.name = "usbgrp",
.pins = usb_3512_pins,
.num_pins = ARRAY_SIZE(usb_3512_pins),
},
{
.name = "gmii_gmac0_grp",
.pins = gmii_gmac0_3512_pins,
.num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
.driving_mask = GENMASK(17, 16),
},
{
.name = "gmii_gmac1_grp",
.pins = gmii_gmac1_3512_pins,
.num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
/* Bring out RGMII on the GMAC1 pins */
.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
.driving_mask = GENMASK(19, 18),
},
{
.name = "pcigrp",
.pins = pci_3512_pins,
.num_pins = ARRAY_SIZE(pci_3512_pins),
/* Conflict only with GPIO2 */
.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
.driving_mask = GENMASK(23, 22),
},
{
.name = "lpcgrp",
.pins = lpc_3512_pins,
.num_pins = ARRAY_SIZE(lpc_3512_pins),
/* Conflict with SSP and UART modem pins */
.mask = SSP_PADS_ENABLE,
.value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
},
{
.name = "lcdgrp",
.pins = lcd_3512_pins,
.num_pins = ARRAY_SIZE(lcd_3512_pins),
/* Conflict with TVC and ICE */
.mask = TVC_PADS_ENABLE,
.value = LCD_PADS_ENABLE,
},
{
.name = "sspgrp",
.pins = ssp_3512_pins,
.num_pins = ARRAY_SIZE(ssp_3512_pins),
/* Conflict with LPC and UART modem pins */
.mask = LPC_PADS_ENABLE,
.value = SSP_PADS_ENABLE,
},
{
.name = "uartrxtxgrp",
.pins = uart_rxtx_3512_pins,
.num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
/* No conflicts except GPIO */
},
{
.name = "uartmodemgrp",
.pins = uart_modem_3512_pins,
.num_pins = ARRAY_SIZE(uart_modem_3512_pins),
/*
* Conflict with LPC and SSP,
* so when those are both disabled, modem UART can thrive.
*/
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "tvcgrp",
.pins = tvc_3512_pins,
.num_pins = ARRAY_SIZE(tvc_3512_pins),
/* Conflict with character LCD and ICE */
.mask = LCD_PADS_ENABLE,
.value = TVC_PADS_ENABLE,
},
{
.name = "tvcclkgrp",
.pins = tvc_clk_3512_pins,
.num_pins = ARRAY_SIZE(tvc_clk_3512_pins),
.value = TVC_CLK_PAD_ENABLE,
},
/*
* The construction is done such that it is possible to use a serial
* flash together with a NAND or parallel (NOR) flash, but it is not
* possible to use NAND and parallel flash together. To use serial
* flash with one of the two others, the muxbits need to be flipped
* around before any access.
*/
{
.name = "nflashgrp",
.pins = nflash_3512_pins,
.num_pins = ARRAY_SIZE(nflash_3512_pins),
/* Conflict with IDE, parallel and serial flash */
.mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "pflashgrp",
.pins = pflash_3512_pins,
.num_pins = ARRAY_SIZE(pflash_3512_pins),
/* Conflict with IDE, NAND and serial flash */
.mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "sflashgrp",
.pins = sflash_3512_pins,
.num_pins = ARRAY_SIZE(sflash_3512_pins),
/* Conflict with IDE, NAND and parallel flash */
.mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio0agrp",
.pins = gpio0a_3512_pins,
.num_pins = ARRAY_SIZE(gpio0a_3512_pins),
/* Conflict with TVC CLK */
.mask = TVC_CLK_PAD_ENABLE,
},
{
.name = "gpio0bgrp",
.pins = gpio0b_3512_pins,
.num_pins = ARRAY_SIZE(gpio0b_3512_pins),
/* Conflict with TVC and ICE */
.mask = TVC_PADS_ENABLE,
},
{
.name = "gpio0cgrp",
.pins = gpio0c_3512_pins,
.num_pins = ARRAY_SIZE(gpio0c_3512_pins),
/* Conflict with ICE */
},
{
.name = "gpio0dgrp",
.pins = gpio0d_3512_pins,
.num_pins = ARRAY_SIZE(gpio0d_3512_pins),
/* Conflict with UART RX/TX */
},
{
.name = "gpio0egrp",
.pins = gpio0e_3512_pins,
.num_pins = ARRAY_SIZE(gpio0e_3512_pins),
/* Conflict with LPC, UART modem pins, SSP */
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "gpio0fgrp",
.pins = gpio0f_3512_pins,
.num_pins = ARRAY_SIZE(gpio0f_3512_pins),
/* Conflict with LCD */
.mask = LCD_PADS_ENABLE,
},
{
.name = "gpio0ggrp",
.pins = gpio0g_3512_pins,
.num_pins = ARRAY_SIZE(gpio0g_3512_pins),
/* Conflict with NAND flash */
.value = NAND_PADS_DISABLE,
},
{
.name = "gpio0hgrp",
.pins = gpio0h_3512_pins,
.num_pins = ARRAY_SIZE(gpio0h_3512_pins),
/* Conflict with parallel flash */
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio0igrp",
.pins = gpio0i_3512_pins,
.num_pins = ARRAY_SIZE(gpio0i_3512_pins),
/* Conflict with serial flash */
.value = SFLASH_PADS_DISABLE,
},
{
.name = "gpio0jgrp",
.pins = gpio0j_3512_pins,
.num_pins = ARRAY_SIZE(gpio0j_3512_pins),
/* Conflict with all flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0kgrp",
.pins = gpio0k_3512_pins,
.num_pins = ARRAY_SIZE(gpio0k_3512_pins),
/* Conflict with all flash and LCD */
.mask = LCD_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0lgrp",
.pins = gpio0l_3512_pins,
.num_pins = ARRAY_SIZE(gpio0l_3512_pins),
/* Conflict with parallel flash */
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio0mgrp",
.pins = gpio0m_3512_pins,
.num_pins = ARRAY_SIZE(gpio0m_3512_pins),
/* Conflict with parallel and NAND flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
},
{
.name = "gpio1agrp",
.pins = gpio1a_3512_pins,
.num_pins = ARRAY_SIZE(gpio1a_3512_pins),
/* Conflict with IDE and parallel flash */
.mask = IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio1bgrp",
.pins = gpio1b_3512_pins,
.num_pins = ARRAY_SIZE(gpio1b_3512_pins),
/* Conflict with IDE only */
.mask = IDE_PADS_ENABLE,
},
{
.name = "gpio1cgrp",
.pins = gpio1c_3512_pins,
.num_pins = ARRAY_SIZE(gpio1c_3512_pins),
/* Conflict with IDE, parallel and NAND flash */
.mask = IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio1dgrp",
.pins = gpio1d_3512_pins,
.num_pins = ARRAY_SIZE(gpio1d_3512_pins),
/* Conflict with LCD and TVC */
.mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
},
{
.name = "gpio2agrp",
.pins = gpio2a_3512_pins,
.num_pins = ARRAY_SIZE(gpio2a_3512_pins),
.mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
/* Conflict with GMII GMAC1 and extended parallel flash */
},
{
.name = "gpio2bgrp",
.pins = gpio2b_3512_pins,
.num_pins = ARRAY_SIZE(gpio2b_3512_pins),
/* Conflict with GMII GMAC1, extended parallel flash and LCD */
.mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
},
{
.name = "gpio2cgrp",
.pins = gpio2c_3512_pins,
.num_pins = ARRAY_SIZE(gpio2c_3512_pins),
/* Conflict with PCI */
.mask = PCI_PADS_ENABLE,
},
};
/* Pin names for the pinmux subsystem, 3516 variant */
static const struct pinctrl_pin_desc gemini_3516_pins[] = {
/* Row A */
PINCTRL_PIN(0, "A1 AVCC3IOHA"),
PINCTRL_PIN(1, "A2 DRAM CK N"),
PINCTRL_PIN(2, "A3 DRAM CK"),
PINCTRL_PIN(3, "A4 DRAM DQM1"),
PINCTRL_PIN(4, "A5 DRAM DQ9"),
PINCTRL_PIN(5, "A6 DRAM DQ13"),
PINCTRL_PIN(6, "A7 DRAM DQ1"),
PINCTRL_PIN(7, "A8 DRAM DQ2"),
PINCTRL_PIN(8, "A9 DRAM DQ4"),
PINCTRL_PIN(9, "A10 DRAM VREF"),
PINCTRL_PIN(10, "A11 DRAM DQ24"),
PINCTRL_PIN(11, "A12 DRAM DQ28"),
PINCTRL_PIN(12, "A13 DRAM DQ30"),
PINCTRL_PIN(13, "A14 DRAM DQ18"),
PINCTRL_PIN(14, "A15 DRAM DQ21"),
PINCTRL_PIN(15, "A16 DRAM CAS_N"),
PINCTRL_PIN(16, "A17 DRAM BA1"),
PINCTRL_PIN(17, "A18 PCI INTA N"),
PINCTRL_PIN(18, "A19 PCI INTB N"),
PINCTRL_PIN(19, "A20 PCI INTC N"),
/* Row B */
PINCTRL_PIN(20, "B1 PWR EN"),
PINCTRL_PIN(21, "B2 GND"),
PINCTRL_PIN(22, "B3 RTC CLKO"),
PINCTRL_PIN(23, "B4 DRAM A5"),
PINCTRL_PIN(24, "B5 DRAM A6"),
PINCTRL_PIN(25, "B6 DRAM DQS1"),
PINCTRL_PIN(26, "B7 DRAM DQ11"),
PINCTRL_PIN(27, "B8 DRAM DQ0"),
PINCTRL_PIN(28, "B9 DRAM DQS0"),
PINCTRL_PIN(29, "B10 DRAM DQ7"),
PINCTRL_PIN(30, "B11 DRAM DQS3"),
PINCTRL_PIN(31, "B12 DRAM DQ27"),
PINCTRL_PIN(32, "B13 DRAM DQ31"),
PINCTRL_PIN(33, "B14 DRAM DQ20"),
PINCTRL_PIN(34, "B15 DRAM DQS2"),
PINCTRL_PIN(35, "B16 DRAM WE N"),
PINCTRL_PIN(36, "B17 DRAM A10"),
PINCTRL_PIN(37, "B18 DRAM A2"),
PINCTRL_PIN(38, "B19 GND"),
PINCTRL_PIN(39, "B20 PCI GNT0 N"),
/* Row C */
PINCTRL_PIN(40, "C1 AGNDIOHA"),
PINCTRL_PIN(41, "C2 XTALI"),
PINCTRL_PIN(42, "C3 GND"),
PINCTRL_PIN(43, "C4 RTC CLKI"),
PINCTRL_PIN(44, "C5 DRAM A12"),
PINCTRL_PIN(45, "C6 DRAM A11"),
PINCTRL_PIN(46, "C7 DRAM DQ8"),
PINCTRL_PIN(47, "C8 DRAM DQ10"),
PINCTRL_PIN(48, "C9 DRAM DQ3"),
PINCTRL_PIN(49, "C10 DRAM DQ6"),
PINCTRL_PIN(50, "C11 DRAM DQM0"),
PINCTRL_PIN(51, "C12 DRAM DQ26"),
PINCTRL_PIN(52, "C13 DRAM DQ16"),
PINCTRL_PIN(53, "C14 DRAM DQ22"),
PINCTRL_PIN(54, "C15 DRAM DQM2"),
PINCTRL_PIN(55, "C16 DRAM BA0"),
PINCTRL_PIN(56, "C17 DRAM A3"),
PINCTRL_PIN(57, "C18 GND"),
PINCTRL_PIN(58, "C19 PCI GNT1 N"),
PINCTRL_PIN(59, "C20 PCI REQ2 N"),
/* Row D */
PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
PINCTRL_PIN(61, "D2 AVCCKHA"),
PINCTRL_PIN(62, "D3 XTALO"),
PINCTRL_PIN(63, "D4 GND"),
PINCTRL_PIN(64, "D5 CIR RXD"),
PINCTRL_PIN(65, "D6 DRAM A7"),
PINCTRL_PIN(66, "D7 DRAM A4"),
PINCTRL_PIN(67, "D8 DRAM A8"),
PINCTRL_PIN(68, "D9 DRAM CKE"),
PINCTRL_PIN(69, "D10 DRAM DQ14"),
PINCTRL_PIN(70, "D11 DRAM DQ5"),
PINCTRL_PIN(71, "D12 DRAM DQ25"),
PINCTRL_PIN(72, "D13 DRAM DQ17"),
PINCTRL_PIN(73, "D14 DRAM DQ23"),
PINCTRL_PIN(74, "D15 DRAM RAS N"),
PINCTRL_PIN(75, "D16 DRAM A1"),
PINCTRL_PIN(76, "D17 GND"),
PINCTRL_PIN(77, "D18 EXT RESET N"),
PINCTRL_PIN(78, "D19 PCI REQ1 N"),
PINCTRL_PIN(79, "D20 PCI REQ3 N"),
/* Row E */
PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
PINCTRL_PIN(81, "E2 VREF CTRL"),
PINCTRL_PIN(82, "E3 CIR RST N"),
PINCTRL_PIN(83, "E4 PWR BTN"),
PINCTRL_PIN(84, "E5 GND"),
PINCTRL_PIN(85, "E6 CIR TXD"),
PINCTRL_PIN(86, "E7 VCCK CTRL"),
PINCTRL_PIN(87, "E8 DRAM A9"),
PINCTRL_PIN(88, "E9 DRAM DQ12"),
PINCTRL_PIN(89, "E10 DRAM DQ15"),
PINCTRL_PIN(90, "E11 DRAM DQM3"),
PINCTRL_PIN(91, "E12 DRAM DQ29"),
PINCTRL_PIN(92, "E13 DRAM DQ19"),
PINCTRL_PIN(93, "E14 DRAM A13"),
PINCTRL_PIN(94, "E15 DRAM A0"),
PINCTRL_PIN(95, "E16 GND"),
PINCTRL_PIN(96, "E17 PCI INTD N"),
PINCTRL_PIN(97, "E18 PCI GNT3 N"),
PINCTRL_PIN(98, "E19 PCI AD29"),
PINCTRL_PIN(99, "E20 PCI AD28"),
/* Row F */
PINCTRL_PIN(100, "F1 AVCCKHB"),
PINCTRL_PIN(101, "F2 AVCCK P"),
PINCTRL_PIN(102, "F3 EBG"),
PINCTRL_PIN(103, "F4 REXT"),
PINCTRL_PIN(104, "F5 AVCC3IOHB"),
PINCTRL_PIN(105, "F6 GND"),
PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
PINCTRL_PIN(109, "F10 V1"),
PINCTRL_PIN(110, "F11 V1"),
PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
PINCTRL_PIN(114, "F15 GND"),
PINCTRL_PIN(115, "F16 PCI CLK"),
PINCTRL_PIN(116, "F17 PCI GNT2 N"),
PINCTRL_PIN(117, "F18 PCI AD31"),
PINCTRL_PIN(118, "F19 PCI AD26"),
PINCTRL_PIN(119, "F20 PCI CBE3 N"),
/* Row G */
PINCTRL_PIN(120, "G1 SATA0 RXDP"),
PINCTRL_PIN(121, "G2 SATA0 RXDN"),
PINCTRL_PIN(122, "G3 AGNDK 0"),
PINCTRL_PIN(123, "G4 AVCCK S"),
PINCTRL_PIN(124, "G5 AVCC3 S"),
PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
PINCTRL_PIN(126, "G7 GND"),
PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
PINCTRL_PIN(128, "G9 V1"),
PINCTRL_PIN(129, "G10 V1"),
PINCTRL_PIN(130, "G11 V1"),
PINCTRL_PIN(131, "G12 V1"),
PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
PINCTRL_PIN(133, "G14 GND"),
PINCTRL_PIN(134, "G15 VCC3IOHA"),
PINCTRL_PIN(135, "G16 PCI REQ0 N"),
PINCTRL_PIN(136, "G17 PCI AD30"),
PINCTRL_PIN(137, "G18 PCI AD24"),
PINCTRL_PIN(138, "G19 PCI AD23"),
PINCTRL_PIN(139, "G20 PCI AD21"),
/* Row H */
PINCTRL_PIN(140, "H1 SATA0 TXDP"),
PINCTRL_PIN(141, "H2 SATA0 TXDN"),
PINCTRL_PIN(142, "H3 AGNDK 1"),
PINCTRL_PIN(143, "H4 AVCCK 0"),
PINCTRL_PIN(144, "H5 TEST CLKOUT"),
PINCTRL_PIN(145, "H6 AGND"),
PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
PINCTRL_PIN(147, "H8 GND"),
PINCTRL_PIN(148, "H9 GND"),
PINCTRL_PIN(149, "H10 GDN"),
PINCTRL_PIN(150, "H11 GND"),
PINCTRL_PIN(151, "H12 GND"),
PINCTRL_PIN(152, "H13 GND"),
PINCTRL_PIN(153, "H14 VCC3IOHA"),
PINCTRL_PIN(154, "H15 VCC3IOHA"),
PINCTRL_PIN(155, "H16 PCI AD27"),
PINCTRL_PIN(156, "H17 PCI AD25"),
PINCTRL_PIN(157, "H18 PCI AD22"),
PINCTRL_PIN(158, "H19 PCI AD18"),
PINCTRL_PIN(159, "H20 PCI AD17"),
/* Row J (for some reason I is skipped) */
PINCTRL_PIN(160, "J1 SATA1 TXDP"),
PINCTRL_PIN(161, "J2 SATA1 TXDN"),
PINCTRL_PIN(162, "J3 AGNDK 2"),
PINCTRL_PIN(163, "J4 AVCCK 1"),
PINCTRL_PIN(164, "J5 AGND"),
PINCTRL_PIN(165, "J6 AGND"),
PINCTRL_PIN(166, "J7 V1"),
PINCTRL_PIN(167, "J8 GND"),
PINCTRL_PIN(168, "J9 GND"),
PINCTRL_PIN(169, "J10 GND"),
PINCTRL_PIN(170, "J11 GND"),
PINCTRL_PIN(171, "J12 GND"),
PINCTRL_PIN(172, "J13 GND"),
PINCTRL_PIN(173, "J14 V1"),
PINCTRL_PIN(174, "J15 VCC3IOHA"),
PINCTRL_PIN(175, "J16 PCI AD19"),
PINCTRL_PIN(176, "J17 PCI AD20"),
PINCTRL_PIN(177, "J18 PCI AD16"),
PINCTRL_PIN(178, "J19 PCI CBE2 N"),
PINCTRL_PIN(179, "J20 PCI FRAME N"),
/* Row K */
PINCTRL_PIN(180, "K1 SATA1 RXDP"),
PINCTRL_PIN(181, "K2 SATA1 RXDN"),
PINCTRL_PIN(182, "K3 AGNDK 3"),
PINCTRL_PIN(183, "K4 AVCCK 2"),
PINCTRL_PIN(184, "K5 AGND"),
PINCTRL_PIN(185, "K6 V1"),
PINCTRL_PIN(186, "K7 V1"),
PINCTRL_PIN(187, "K8 GND"),
PINCTRL_PIN(188, "K9 GND"),
PINCTRL_PIN(189, "K10 GND"),
PINCTRL_PIN(190, "K11 GND"),
PINCTRL_PIN(191, "K12 GND"),
PINCTRL_PIN(192, "K13 GND"),
PINCTRL_PIN(193, "K14 V1"),
PINCTRL_PIN(194, "K15 V1"),
PINCTRL_PIN(195, "K16 PCI TRDY N"),
PINCTRL_PIN(196, "K17 PCI IRDY N"),
PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
PINCTRL_PIN(198, "K19 PCI STOP N"),
PINCTRL_PIN(199, "K20 PCI PAR"),
/* Row L */
PINCTRL_PIN(200, "L1 IDE CS0 N"),
PINCTRL_PIN(201, "L2 IDE DA0"),
PINCTRL_PIN(202, "L3 AVCCK 3"),
PINCTRL_PIN(203, "L4 AGND"),
PINCTRL_PIN(204, "L5 IDE DIOR N"),
PINCTRL_PIN(205, "L6 V1"),
PINCTRL_PIN(206, "L7 V1"),
PINCTRL_PIN(207, "L8 GND"),
PINCTRL_PIN(208, "L9 GND"),
PINCTRL_PIN(209, "L10 GND"),
PINCTRL_PIN(210, "L11 GND"),
PINCTRL_PIN(211, "L12 GND"),
PINCTRL_PIN(212, "L13 GND"),
PINCTRL_PIN(213, "L14 V1"),
PINCTRL_PIN(214, "L15 V1"),
PINCTRL_PIN(215, "L16 PCI AD12"),
PINCTRL_PIN(216, "L17 PCI AD13"),
PINCTRL_PIN(217, "L18 PCI AD14"),
PINCTRL_PIN(218, "L19 PCI AD15"),
PINCTRL_PIN(219, "L20 PCI CBE1 N"),
/* Row M */
PINCTRL_PIN(220, "M1 IDE DA1"),
PINCTRL_PIN(221, "M2 IDE CS1 N"),
PINCTRL_PIN(222, "M3 IDE DA2"),
PINCTRL_PIN(223, "M4 IDE DMACK N"),
PINCTRL_PIN(224, "M5 IDE DD1"),
PINCTRL_PIN(225, "M6 VCC3IOHA"),
PINCTRL_PIN(226, "M7 V1"),
PINCTRL_PIN(227, "M8 GND"),
PINCTRL_PIN(228, "M9 GND"),
PINCTRL_PIN(229, "M10 GND"),
PINCTRL_PIN(230, "M11 GND"),
PINCTRL_PIN(231, "M12 GND"),
PINCTRL_PIN(232, "M13 GND"),
PINCTRL_PIN(233, "M14 V1"),
PINCTRL_PIN(234, "M15 VCC3IOHA"),
PINCTRL_PIN(235, "M16 PCI AD7"),
PINCTRL_PIN(236, "M17 PCI AD6"),
PINCTRL_PIN(237, "M18 PCI AD9"),
PINCTRL_PIN(238, "M19 PCI AD10"),
PINCTRL_PIN(239, "M20 PCI AD11"),
/* Row N */
PINCTRL_PIN(240, "N1 IDE IORDY"),
PINCTRL_PIN(241, "N2 IDE INTRQ"),
PINCTRL_PIN(242, "N3 IDE DIOW N"),
PINCTRL_PIN(243, "N4 IDE DD15"),
PINCTRL_PIN(244, "N5 IDE DMARQ"),
PINCTRL_PIN(245, "N6 VCC3IOHA"),
PINCTRL_PIN(246, "N7 VCC3IOHA"),
PINCTRL_PIN(247, "N8 GND"),
PINCTRL_PIN(248, "N9 GND"),
PINCTRL_PIN(249, "N10 GND"),
PINCTRL_PIN(250, "N11 GND"),
PINCTRL_PIN(251, "N12 GND"),
PINCTRL_PIN(252, "N13 GND"),
PINCTRL_PIN(253, "N14 VCC3IOHA"),
PINCTRL_PIN(254, "N15 VCC3IOHA"),
PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
PINCTRL_PIN(256, "N17 PCI AD0"),
PINCTRL_PIN(257, "N18 PCI AD4"),
PINCTRL_PIN(258, "N19 PCI CBE0 N"),
PINCTRL_PIN(259, "N20 PCI AD8"),
/* Row P (for some reason O is skipped) */
PINCTRL_PIN(260, "P1 IDE DD0"),
PINCTRL_PIN(261, "P2 IDE DD14"),
PINCTRL_PIN(262, "P3 IDE DD2"),
PINCTRL_PIN(263, "P4 IDE DD4"),
PINCTRL_PIN(264, "P5 IDE DD3"),
PINCTRL_PIN(265, "P6 VCC3IOHA"),
PINCTRL_PIN(266, "P7 GND"),
PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
PINCTRL_PIN(268, "P9 V1"),
PINCTRL_PIN(269, "P10 V1"),
PINCTRL_PIN(270, "P11 V1"),
PINCTRL_PIN(271, "P12 V1"),
PINCTRL_PIN(272, "P13 VCC3IOHA"),
PINCTRL_PIN(273, "P14 GND"),
PINCTRL_PIN(274, "P15 VCC3IOHA"),
PINCTRL_PIN(275, "P16 GPIO0 30"),
PINCTRL_PIN(276, "P17 GPIO0 28"),
PINCTRL_PIN(277, "P18 PCI AD1"),
PINCTRL_PIN(278, "P19 PCI AD3"),
PINCTRL_PIN(279, "P20 PCI AD5"),
/* Row R (for some reason Q is skipped) */
PINCTRL_PIN(280, "R1 IDE DD13"),
PINCTRL_PIN(281, "R2 IDE DD12"),
PINCTRL_PIN(282, "R3 IDE DD10"),
PINCTRL_PIN(283, "R4 IDE DD6"),
PINCTRL_PIN(284, "R5 ICE0 IDI"),
PINCTRL_PIN(285, "R6 GND"),
PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
PINCTRL_PIN(289, "R10 V1"),
PINCTRL_PIN(290, "R11 V1"),
PINCTRL_PIN(291, "R12 VCC3IOHA"),
PINCTRL_PIN(292, "R13 VCC3IOHA"),
PINCTRL_PIN(293, "R14 VCC3IOHA"),
PINCTRL_PIN(294, "R15 GND"),
PINCTRL_PIN(295, "R16 GPIO0 23"),
PINCTRL_PIN(296, "R17 GPIO0 21"),
PINCTRL_PIN(297, "R18 GPIO0 26"),
PINCTRL_PIN(298, "R19 GPIO0 31"),
PINCTRL_PIN(299, "R20 PCI AD2"),
/* Row T (for some reason S is skipped) */
PINCTRL_PIN(300, "T1 IDE DD11"),
PINCTRL_PIN(301, "T2 IDE DD5"),
PINCTRL_PIN(302, "T3 IDE DD8"),
PINCTRL_PIN(303, "T4 ICE0 IDO"),
PINCTRL_PIN(304, "T5 GND"),
PINCTRL_PIN(305, "T6 USB GNDA U20"),
PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
PINCTRL_PIN(311, "T12 GPIO1 29"),
PINCTRL_PIN(312, "T13 GPIO0 3"),
PINCTRL_PIN(313, "T14 GPIO0 9"),
PINCTRL_PIN(314, "T15 GPIO0 16"),
PINCTRL_PIN(315, "T16 GND"),
PINCTRL_PIN(316, "T17 GPIO0 14"),
PINCTRL_PIN(317, "T18 GPIO0 19"),
PINCTRL_PIN(318, "T19 GPIO0 27"),
PINCTRL_PIN(319, "T20 GPIO0 29"),
/* Row U */
PINCTRL_PIN(320, "U1 IDE DD9"),
PINCTRL_PIN(321, "U2 IDE DD7"),
PINCTRL_PIN(322, "U3 ICE0 ICK"),
PINCTRL_PIN(323, "U4 GND"),
PINCTRL_PIN(324, "U5 USB XSCO"),
PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
PINCTRL_PIN(327, "U8 GMAC0 TXC"),
PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
PINCTRL_PIN(330, "U11 GMAC1 CRS"),
PINCTRL_PIN(331, "U12 EXT CLK"),
PINCTRL_PIN(332, "U13 DEV DEF"),
PINCTRL_PIN(333, "U14 GPIO0 0"),
PINCTRL_PIN(334, "U15 GPIO0 4"),
PINCTRL_PIN(335, "U16 GPIO0 10"),
PINCTRL_PIN(336, "U17 GND"),
PINCTRL_PIN(337, "U18 GPIO0 17"),
PINCTRL_PIN(338, "U19 GPIO0 22"),
PINCTRL_PIN(339, "U20 GPIO0 25"),
/* Row V */
PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
PINCTRL_PIN(342, "V3 GND"),
PINCTRL_PIN(343, "V4 ICE0 IRST N"),
PINCTRL_PIN(344, "V5 USB XSCI"),
PINCTRL_PIN(345, "V6 GMAC0 COL"),
PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
PINCTRL_PIN(349, "V10 GMAC1 COL"),
PINCTRL_PIN(350, "V11 GMAC1 TXC"),
PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
PINCTRL_PIN(352, "V13 MODE SEL1"),
PINCTRL_PIN(353, "V14 GPIO1 28"),
PINCTRL_PIN(354, "V15 GPIO0 1"),
PINCTRL_PIN(355, "V16 GPIO0 8"),
PINCTRL_PIN(356, "V17 GPIO0 11"),
PINCTRL_PIN(357, "V18 GND"),
PINCTRL_PIN(358, "V19 GPIO0 18"),
PINCTRL_PIN(359, "V20 GPIO0 24"),
/* Row W */
PINCTRL_PIN(360, "W1 IDE RESET N"),
PINCTRL_PIN(361, "W2 GND"),
PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
PINCTRL_PIN(363, "W4 USB0 DP"),
PINCTRL_PIN(364, "W5 USB VCCA U20"),
PINCTRL_PIN(365, "W6 USB1 DP"),
PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
PINCTRL_PIN(368, "W9 GMAC0 CRS"),
PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
PINCTRL_PIN(372, "W13 MODE SEL0"),
PINCTRL_PIN(373, "W14 MODE SEL3"),
PINCTRL_PIN(374, "W15 GPIO1 31"),
PINCTRL_PIN(375, "W16 GPIO0 5"),
PINCTRL_PIN(376, "W17 GPIO0 7"),
PINCTRL_PIN(377, "W18 GPIO0 12"),
PINCTRL_PIN(378, "W19 GND"),
PINCTRL_PIN(379, "W20 GPIO0 20"),
/* Row Y */
PINCTRL_PIN(380, "Y1 ICE0 IMS"),
PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
PINCTRL_PIN(382, "Y3 USB0 DM"),
PINCTRL_PIN(383, "Y4 USB RREF"),
PINCTRL_PIN(384, "Y5 USB1 DM"),
PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
PINCTRL_PIN(388, "Y9 REF CLK"),
PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
PINCTRL_PIN(392, "Y13 M30 CLK"),
PINCTRL_PIN(393, "Y14 MODE SEL2"),
PINCTRL_PIN(394, "Y15 GPIO1 30"),
PINCTRL_PIN(395, "Y16 GPIO0 2"),
PINCTRL_PIN(396, "Y17 GPIO0 6"),
PINCTRL_PIN(397, "Y18 SYS RESET N"),
PINCTRL_PIN(398, "Y19 GPIO0 13"),
PINCTRL_PIN(399, "Y20 GPIO0 15"),
};
/* Digital ground */
static const unsigned int gnd_3516_pins[] = {
21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
361, 378
};
static const unsigned int dram_3516_pins[] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
87, 88, 89, 90, 91, 92, 93, 94
};
static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
static const unsigned int system_3516_pins[] = {
332, 392, 372, 373, 393, 352, 331, 388, 397, 77
};
static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
static const unsigned int ide_3516_pins[] = {
200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
};
static const unsigned int sata_3516_pins[] = {
100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
144, 160, 161, 162, 163, 180, 181, 182, 183, 202
};
static const unsigned int usb_3516_pins[] = {
305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
};
/* GMII, ethernet pins */
static const unsigned int gmii_gmac0_3516_pins[] = {
306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
};
static const unsigned int gmii_gmac1_3516_pins[] = {
308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
};
static const unsigned int pci_3516_pins[] = {
17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
};
/*
* Apparently the LPC interface is using the PCICLK for the clocking so
* PCI needs to be active at the same time.
*/
static const unsigned int lpc_3516_pins[] = {
355, /* LPC_LAD[0] */
356, /* LPC_SERIRQ */
377, /* LPC_LAD[2] */
398, /* LPC_LFRAME# */
316, /* LPC_LAD[3] */
399, /* LPC_LAD[1] */
};
/* Character LCD */
static const unsigned int lcd_3516_pins[] = {
391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
};
static const unsigned int ssp_3516_pins[] = {
355, /* SSP_97RST# SSP AC97 Reset, active low */
356, /* SSP_FSC */
377, /* SSP_ECLK */
398, /* SSP_TXD */
316, /* SSP_RXD */
399, /* SSP_SCLK */
};
static const unsigned int uart_rxtx_3516_pins[] = {
313, /* UART_SIN serial input, RX */
335, /* UART_SOUT serial output, TX */
};
static const unsigned int uart_modem_3516_pins[] = {
355, /* UART_NDCD DCD carrier detect */
356, /* UART_NDTR DTR data terminal ready */
377, /* UART_NDSR DSR data set ready */
398, /* UART_NRTS RTS request to send */
316, /* UART_NCTS CTS clear to send */
399, /* UART_NRI RI ring indicator */
};
static const unsigned int tvc_3516_pins[] = {
353, /* TVC_DATA[0] */
311, /* TVC_DATA[1] */
394, /* TVC_DATA[2] */
374, /* TVC_DATA[3] */
354, /* TVC_DATA[4] */
395, /* TVC_DATA[5] */
312, /* TVC_DATA[6] */
334, /* TVC_DATA[7] */
};
static const unsigned int tvc_clk_3516_pins[] = {
333, /* TVC_CLK */
};
/* NAND flash pins */
static const unsigned int nflash_3516_pins[] = {
243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
302, 321, 337, 358, 295, 359, 339, 275, 298
};
/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
static const unsigned int pflash_3516_pins[] = {
221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
276, 319, 275, 298
};
/*
* The parallel flash can be set up in a 26-bit address bus mode exposing
* A[0-15] (A[15] takes the place of ALE), but it has the
* side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
* used at the same time.
*/
static const unsigned int pflash_3516_pins_extended[] = {
221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
276, 319, 275, 298,
/* The extra pins */
349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
333
};
/* Serial flash pins CE0, CE1, DI, DO, CK */
static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
/* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 };
/* The GPIO0B (5-7) pins overlap with ICE */
static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
/* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
/* The GPIO0D (9,10) pins overlap with UART RX/TX */
static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
/* The GPIO0E (16) pins overlap with LCD */
static const unsigned int gpio0e_3516_pins[] = { 314 };
/* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
/* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
/* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
/* The GPIO0I (23) pins overlap with all flash */
static const unsigned int gpio0i_3516_pins[] = { 295 };
/* The GPIO0J (24,25) pins overlap with all flash and LCD */
static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
/* The GPIO0K (30,31) pins overlap with NAND flash */
static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
/* The GPIO0L (0) pins overlap with TVC_CLK */
static const unsigned int gpio0l_3516_pins[] = { 333 };
/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
/* The GPIO1B (5-10,27) pins overlap with just IDE */
static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
static const unsigned int gpio1c_3516_pins[] = {
243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
302, 321
};
/* The GPIO1D (28-31) pins overlap with TVC */
static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
/* The GPIO2C (8-31) pins overlap with PCI */
static const unsigned int gpio2c_3516_pins[] = {
259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
157, 138, 137, 156, 118, 155, 99, 98, 136, 117
};
/* Groups for the 3516 SoC/package */
static const struct gemini_pin_group gemini_3516_pin_groups[] = {
{
.name = "gndgrp",
.pins = gnd_3516_pins,
.num_pins = ARRAY_SIZE(gnd_3516_pins),
},
{
.name = "dramgrp",
.pins = dram_3516_pins,
.num_pins = ARRAY_SIZE(dram_3516_pins),
.mask = DRAM_PADS_POWERDOWN,
},
{
.name = "rtcgrp",
.pins = rtc_3516_pins,
.num_pins = ARRAY_SIZE(rtc_3516_pins),
},
{
.name = "powergrp",
.pins = power_3516_pins,
.num_pins = ARRAY_SIZE(power_3516_pins),
},
{
.name = "cirgrp",
.pins = cir_3516_pins,
.num_pins = ARRAY_SIZE(cir_3516_pins),
},
{
.name = "systemgrp",
.pins = system_3516_pins,
.num_pins = ARRAY_SIZE(system_3516_pins),
},
{
.name = "vcontrolgrp",
.pins = vcontrol_3516_pins,
.num_pins = ARRAY_SIZE(vcontrol_3516_pins),
},
{
.name = "icegrp",
.pins = ice_3516_pins,
.num_pins = ARRAY_SIZE(ice_3516_pins),
/* Conflict with some GPIO groups */
},
{
.name = "idegrp",
.pins = ide_3516_pins,
.num_pins = ARRAY_SIZE(ide_3516_pins),
/* Conflict with all flash usage */
.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
.driving_mask = GENMASK(21, 20),
},
{
.name = "satagrp",
.pins = sata_3516_pins,
.num_pins = ARRAY_SIZE(sata_3516_pins),
},
{
.name = "usbgrp",
.pins = usb_3516_pins,
.num_pins = ARRAY_SIZE(usb_3516_pins),
},
{
.name = "gmii_gmac0_grp",
.pins = gmii_gmac0_3516_pins,
.num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
.mask = GEMINI_GMAC_IOSEL_MASK,
.driving_mask = GENMASK(17, 16),
},
{
.name = "gmii_gmac1_grp",
.pins = gmii_gmac1_3516_pins,
.num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
/* Bring out RGMII on the GMAC1 pins */
.mask = GEMINI_GMAC_IOSEL_MASK,
.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
.driving_mask = GENMASK(19, 18),
},
{
.name = "pcigrp",
.pins = pci_3516_pins,
.num_pins = ARRAY_SIZE(pci_3516_pins),
/* Conflict only with GPIO2 */
.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
.driving_mask = GENMASK(23, 22),
},
{
.name = "lpcgrp",
.pins = lpc_3516_pins,
.num_pins = ARRAY_SIZE(lpc_3516_pins),
/* Conflict with SSP */
.mask = SSP_PADS_ENABLE,
.value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
},
{
.name = "lcdgrp",
.pins = lcd_3516_pins,
.num_pins = ARRAY_SIZE(lcd_3516_pins),
.mask = TVC_PADS_ENABLE,
.value = LCD_PADS_ENABLE,
},
{
.name = "sspgrp",
.pins = ssp_3516_pins,
.num_pins = ARRAY_SIZE(ssp_3516_pins),
/* Conflict with LPC */
.mask = LPC_PADS_ENABLE,
.value = SSP_PADS_ENABLE,
},
{
.name = "uartrxtxgrp",
.pins = uart_rxtx_3516_pins,
.num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
/* No conflicts except GPIO */
},
{
.name = "uartmodemgrp",
.pins = uart_modem_3516_pins,
.num_pins = ARRAY_SIZE(uart_modem_3516_pins),
/*
* Conflict with LPC and SSP,
* so when those are both disabled, modem UART can thrive.
*/
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "tvcgrp",
.pins = tvc_3516_pins,
.num_pins = ARRAY_SIZE(tvc_3516_pins),
/* Conflict with character LCD */
.mask = LCD_PADS_ENABLE,
.value = TVC_PADS_ENABLE,
},
{
.name = "tvcclkgrp",
.pins = tvc_clk_3516_pins,
.num_pins = ARRAY_SIZE(tvc_clk_3516_pins),
.value = TVC_CLK_PAD_ENABLE,
},
/*
* The construction is done such that it is possible to use a serial
* flash together with a NAND or parallel (NOR) flash, but it is not
* possible to use NAND and parallel flash together. To use serial
* flash with one of the two others, the muxbits need to be flipped
* around before any access.
*/
{
.name = "nflashgrp",
.pins = nflash_3516_pins,
.num_pins = ARRAY_SIZE(nflash_3516_pins),
/* Conflict with IDE, parallel and serial flash */
.mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "pflashgrp",
.pins = pflash_3516_pins,
.num_pins = ARRAY_SIZE(pflash_3516_pins),
/* Conflict with IDE, NAND and serial flash */
.mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "sflashgrp",
.pins = sflash_3516_pins,
.num_pins = ARRAY_SIZE(sflash_3516_pins),
/* Conflict with IDE, NAND and parallel flash */
.mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio0agrp",
.pins = gpio0a_3516_pins,
.num_pins = ARRAY_SIZE(gpio0a_3516_pins),
/* Conflict with TVC and ICE */
.mask = TVC_PADS_ENABLE,
},
{
.name = "gpio0bgrp",
.pins = gpio0b_3516_pins,
.num_pins = ARRAY_SIZE(gpio0b_3516_pins),
/* Conflict with ICE */
},
{
.name = "gpio0cgrp",
.pins = gpio0c_3516_pins,
.num_pins = ARRAY_SIZE(gpio0c_3516_pins),
/* Conflict with LPC, UART and SSP */
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "gpio0dgrp",
.pins = gpio0d_3516_pins,
.num_pins = ARRAY_SIZE(gpio0d_3516_pins),
/* Conflict with UART */
},
{
.name = "gpio0egrp",
.pins = gpio0e_3516_pins,
.num_pins = ARRAY_SIZE(gpio0e_3516_pins),
/* Conflict with LCD */
.mask = LCD_PADS_ENABLE,
},
{
.name = "gpio0fgrp",
.pins = gpio0f_3516_pins,
.num_pins = ARRAY_SIZE(gpio0f_3516_pins),
/* Conflict with NAND flash */
.value = NAND_PADS_DISABLE,
},
{
.name = "gpio0ggrp",
.pins = gpio0g_3516_pins,
.num_pins = ARRAY_SIZE(gpio0g_3516_pins),
/* Conflict with parallel flash */
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio0hgrp",
.pins = gpio0h_3516_pins,
.num_pins = ARRAY_SIZE(gpio0h_3516_pins),
/* Conflict with serial flash */
.value = SFLASH_PADS_DISABLE,
},
{
.name = "gpio0igrp",
.pins = gpio0i_3516_pins,
.num_pins = ARRAY_SIZE(gpio0i_3516_pins),
/* Conflict with all flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0jgrp",
.pins = gpio0j_3516_pins,
.num_pins = ARRAY_SIZE(gpio0j_3516_pins),
/* Conflict with all flash and LCD */
.mask = LCD_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0kgrp",
.pins = gpio0k_3516_pins,
.num_pins = ARRAY_SIZE(gpio0k_3516_pins),
/* Conflict with parallel and NAND flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
},
{
.name = "gpio0lgrp",
.pins = gpio0l_3516_pins,
.num_pins = ARRAY_SIZE(gpio0l_3516_pins),
/* Conflict with TVE CLK */
.mask = TVC_CLK_PAD_ENABLE,
},
{
.name = "gpio1agrp",
.pins = gpio1a_3516_pins,
.num_pins = ARRAY_SIZE(gpio1a_3516_pins),
/* Conflict with IDE and parallel flash */
.mask = IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio1bgrp",
.pins = gpio1b_3516_pins,
.num_pins = ARRAY_SIZE(gpio1b_3516_pins),
/* Conflict with IDE only */
.mask = IDE_PADS_ENABLE,
},
{
.name = "gpio1cgrp",
.pins = gpio1c_3516_pins,
.num_pins = ARRAY_SIZE(gpio1c_3516_pins),
/* Conflict with IDE, parallel and NAND flash */
.mask = IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio1dgrp",
.pins = gpio1d_3516_pins,
.num_pins = ARRAY_SIZE(gpio1d_3516_pins),
/* Conflict with TVC */
.mask = TVC_PADS_ENABLE,
},
{
.name = "gpio2agrp",
.pins = gpio2a_3516_pins,
.num_pins = ARRAY_SIZE(gpio2a_3516_pins),
.mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
/* Conflict with GMII GMAC1 and extended parallel flash */
},
{
.name = "gpio2bgrp",
.pins = gpio2b_3516_pins,
.num_pins = ARRAY_SIZE(gpio2b_3516_pins),
/* Conflict with GMII GMAC1, extended parallel flash and LCD */
.mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
},
{
.name = "gpio2cgrp",
.pins = gpio2c_3516_pins,
.num_pins = ARRAY_SIZE(gpio2c_3516_pins),
/* Conflict with PCI */
.mask = PCI_PADS_ENABLE,
},
};
static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
if (pmx->is_3512)
return ARRAY_SIZE(gemini_3512_pin_groups);
if (pmx->is_3516)
return ARRAY_SIZE(gemini_3516_pin_groups);
return 0;
}
static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
if (pmx->is_3512)
return gemini_3512_pin_groups[selector].name;
if (pmx->is_3516)
return gemini_3516_pin_groups[selector].name;
return NULL;
}
static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
/* The special case with the 3516 flash pin */
if (pmx->flash_pin &&
pmx->is_3512 &&
!strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
*pins = pflash_3512_pins_extended;
*num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
return 0;
}
if (pmx->flash_pin &&
pmx->is_3516 &&
!strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
*pins = pflash_3516_pins_extended;
*num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
return 0;
}
if (pmx->is_3512) {
*pins = gemini_3512_pin_groups[selector].pins;
*num_pins = gemini_3512_pin_groups[selector].num_pins;
}
if (pmx->is_3516) {
*pins = gemini_3516_pin_groups[selector].pins;
*num_pins = gemini_3516_pin_groups[selector].num_pins;
}
return 0;
}
static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
seq_printf(s, " " DRIVER_NAME);
}
static const struct pinctrl_ops gemini_pctrl_ops = {
.get_groups_count = gemini_get_groups_count,
.get_group_name = gemini_get_group_name,
.get_group_pins = gemini_get_group_pins,
.pin_dbg_show = gemini_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
/**
* struct gemini_pmx_func - describes Gemini pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
*/
struct gemini_pmx_func {
const char *name;
const char * const *groups;
const unsigned int num_groups;
};
static const char * const dramgrps[] = { "dramgrp" };
static const char * const rtcgrps[] = { "rtcgrp" };
static const char * const powergrps[] = { "powergrp" };
static const char * const cirgrps[] = { "cirgrp" };
static const char * const systemgrps[] = { "systemgrp" };
static const char * const vcontrolgrps[] = { "vcontrolgrp" };
static const char * const icegrps[] = { "icegrp" };
static const char * const idegrps[] = { "idegrp" };
static const char * const satagrps[] = { "satagrp" };
static const char * const usbgrps[] = { "usbgrp" };
static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
static const char * const pcigrps[] = { "pcigrp" };
static const char * const lpcgrps[] = { "lpcgrp" };
static const char * const lcdgrps[] = { "lcdgrp" };
static const char * const sspgrps[] = { "sspgrp" };
static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
static const char * const tvcgrps[] = { "tvcgrp" };
static const char * const nflashgrps[] = { "nflashgrp" };
static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
static const char * const sflashgrps[] = { "sflashgrp" };
static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
"gpio0dgrp", "gpio0egrp", "gpio0fgrp",
"gpio0ggrp", "gpio0hgrp", "gpio0igrp",
"gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
"gpio0mgrp" };
static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
"gpio1dgrp" };
static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
static const struct gemini_pmx_func gemini_pmx_functions[] = {
{
.name = "dram",
.groups = dramgrps,
.num_groups = ARRAY_SIZE(idegrps),
},
{
.name = "rtc",
.groups = rtcgrps,
.num_groups = ARRAY_SIZE(rtcgrps),
},
{
.name = "power",
.groups = powergrps,
.num_groups = ARRAY_SIZE(powergrps),
},
{
/* This function is strictly unavailable on 3512 */
.name = "cir",
.groups = cirgrps,
.num_groups = ARRAY_SIZE(cirgrps),
},
{
.name = "system",
.groups = systemgrps,
.num_groups = ARRAY_SIZE(systemgrps),
},
{
.name = "vcontrol",
.groups = vcontrolgrps,
.num_groups = ARRAY_SIZE(vcontrolgrps),
},
{
.name = "ice",
.groups = icegrps,
.num_groups = ARRAY_SIZE(icegrps),
},
{
.name = "ide",
.groups = idegrps,
.num_groups = ARRAY_SIZE(idegrps),
},
{
.name = "sata",
.groups = satagrps,
.num_groups = ARRAY_SIZE(satagrps),
},
{
.name = "usb",
.groups = usbgrps,
.num_groups = ARRAY_SIZE(usbgrps),
},
{
.name = "gmii",
.groups = gmiigrps,
.num_groups = ARRAY_SIZE(gmiigrps),
},
{
.name = "pci",
.groups = pcigrps,
.num_groups = ARRAY_SIZE(pcigrps),
},
{
.name = "lpc",
.groups = lpcgrps,
.num_groups = ARRAY_SIZE(lpcgrps),
},
{
.name = "lcd",
.groups = lcdgrps,
.num_groups = ARRAY_SIZE(lcdgrps),
},
{
.name = "ssp",
.groups = sspgrps,
.num_groups = ARRAY_SIZE(sspgrps),
},
{
.name = "uart",
.groups = uartgrps,
.num_groups = ARRAY_SIZE(uartgrps),
},
{
.name = "tvc",
.groups = tvcgrps,
.num_groups = ARRAY_SIZE(tvcgrps),
},
{
.name = "nflash",
.groups = nflashgrps,
.num_groups = ARRAY_SIZE(nflashgrps),
},
{
.name = "pflash",
.groups = pflashgrps,
.num_groups = ARRAY_SIZE(pflashgrps),
},
{
.name = "sflash",
.groups = sflashgrps,
.num_groups = ARRAY_SIZE(sflashgrps),
},
{
.name = "gpio0",
.groups = gpio0grps,
.num_groups = ARRAY_SIZE(gpio0grps),
},
{
.name = "gpio1",
.groups = gpio1grps,
.num_groups = ARRAY_SIZE(gpio1grps),
},
{
.name = "gpio2",
.groups = gpio2grps,
.num_groups = ARRAY_SIZE(gpio2grps),
},
};
static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned int group)
{
struct gemini_pmx *pmx;
const struct gemini_pmx_func *func;
const struct gemini_pin_group *grp;
u32 before, after, expected;
unsigned long tmp;
int i;
pmx = pinctrl_dev_get_drvdata(pctldev);
func = &gemini_pmx_functions[selector];
if (pmx->is_3512)
grp = &gemini_3512_pin_groups[group];
else if (pmx->is_3516)
grp = &gemini_3516_pin_groups[group];
else {
dev_err(pmx->dev, "invalid SoC type\n");
return -ENODEV;
}
dev_dbg(pmx->dev,
"ACTIVATE function \"%s\" with group \"%s\"\n",
func->name, grp->name);
regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL,
grp->mask | grp->value,
grp->value);
regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
/* Which bits changed */
before &= PADS_MASK;
after &= PADS_MASK;
expected = before &= ~grp->mask;
expected |= grp->value;
expected &= PADS_MASK;
/* Print changed states */
tmp = grp->mask;
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
bool enabled = !(i > 3);
/* Did not go low though it should */
if (after & BIT(i)) {
dev_err(pmx->dev,
"pin group %s could not be %s: "
"probably a hardware limitation\n",
gemini_padgroups[i],
enabled ? "enabled" : "disabled");
dev_err(pmx->dev,
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
before, after, expected);
} else {
dev_dbg(pmx->dev,
"padgroup %s %s\n",
gemini_padgroups[i],
enabled ? "enabled" : "disabled");
}
}
tmp = grp->value;
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
bool enabled = (i > 3);
/* Did not go high though it should */
if (!(after & BIT(i))) {
dev_err(pmx->dev,
"pin group %s could not be %s: "
"probably a hardware limitation\n",
gemini_padgroups[i],
enabled ? "enabled" : "disabled");
dev_err(pmx->dev,
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
before, after, expected);
} else {
dev_dbg(pmx->dev,
"padgroup %s %s\n",
gemini_padgroups[i],
enabled ? "enabled" : "disabled");
}
}
return 0;
}
static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(gemini_pmx_functions);
}
static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return gemini_pmx_functions[selector].name;
}
static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = gemini_pmx_functions[selector].groups;
*num_groups = gemini_pmx_functions[selector].num_groups;
return 0;
}
static const struct pinmux_ops gemini_pmx_ops = {
.get_functions_count = gemini_pmx_get_funcs_count,
.get_function_name = gemini_pmx_get_func_name,
.get_function_groups = gemini_pmx_get_groups,
.set_mux = gemini_pmx_set_mux,
};
#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
.pin = _n, \
.reg = _r, \
.mask = GENMASK(_hb, _lb) \
}
static const struct gemini_pin_conf gemini_confs_3512[] = {
GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
};
static const struct gemini_pin_conf gemini_confs_3516[] = {
GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
};
static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
unsigned int pin)
{
const struct gemini_pin_conf *retconf;
int i;
for (i = 0; i < pmx->nconfs; i++) {
retconf = &pmx->confs[i];
if (retconf->pin == pin)
return retconf;
}
return NULL;
}
static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
const struct gemini_pin_conf *conf;
u32 val;
switch (param) {
case PIN_CONFIG_SKEW_DELAY:
conf = gemini_get_pin_conf(pmx, pin);
if (!conf)
return -ENOTSUPP;
regmap_read(pmx->map, conf->reg, &val);
val &= conf->mask;
val >>= (ffs(conf->mask) - 1);
*config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct gemini_pin_conf *conf;
enum pin_config_param param;
u32 arg;
int ret = 0;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_SKEW_DELAY:
if (arg > 0xf)
return -EINVAL;
conf = gemini_get_pin_conf(pmx, pin);
if (!conf) {
dev_err(pmx->dev,
"invalid pin for skew delay %d\n", pin);
return -ENOTSUPP;
}
arg <<= (ffs(conf->mask) - 1);
dev_dbg(pmx->dev,
"set pin %d to skew delay mask %08x, val %08x\n",
pin, conf->mask, arg);
regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
break;
default:
dev_err(pmx->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
}
return ret;
}
static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long *configs,
unsigned num_configs)
{
struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct gemini_pin_group *grp = NULL;
enum pin_config_param param;
u32 arg;
u32 val;
int i;
if (pmx->is_3512)
grp = &gemini_3512_pin_groups[selector];
if (pmx->is_3516)
grp = &gemini_3516_pin_groups[selector];
/* First figure out if this group supports configs */
if (!grp->driving_mask) {
dev_err(pmx->dev, "pin config group \"%s\" does "
"not support drive strength setting\n",
grp->name);
return -EINVAL;
}
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case 4:
val = 0;
break;
case 8:
val = 1;
break;
case 12:
val = 2;
break;
case 16:
val = 3;
break;
default:
dev_err(pmx->dev,
"invalid drive strength %d mA\n",
arg);
return -ENOTSUPP;
}
val <<= (ffs(grp->driving_mask) - 1);
regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
grp->driving_mask,
val);
dev_dbg(pmx->dev,
"set group %s to %d mA drive strength mask %08x val %08x\n",
grp->name, arg, grp->driving_mask, val);
break;
default:
dev_err(pmx->dev, "invalid config param %04x\n", param);
return -ENOTSUPP;
}
}
return 0;
}
static const struct pinconf_ops gemini_pinconf_ops = {
.pin_config_get = gemini_pinconf_get,
.pin_config_set = gemini_pinconf_set,
.pin_config_group_set = gemini_pinconf_group_set,
.is_generic = true,
};
static struct pinctrl_desc gemini_pmx_desc = {
.name = DRIVER_NAME,
.pctlops = &gemini_pctrl_ops,
.pmxops = &gemini_pmx_ops,
.confops = &gemini_pinconf_ops,
.owner = THIS_MODULE,
};
static int gemini_pmx_probe(struct platform_device *pdev)
{
struct gemini_pmx *pmx;
struct regmap *map;
struct device *dev = &pdev->dev;
struct device *parent;
unsigned long tmp;
u32 val;
int ret;
int i;
/* Create state holders etc for this driver */
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
pmx->dev = &pdev->dev;
parent = dev->parent;
if (!parent) {
dev_err(dev, "no parent to pin controller\n");
return -ENODEV;
}
map = syscon_node_to_regmap(parent->of_node);
if (IS_ERR(map)) {
dev_err(dev, "no syscon regmap\n");
return PTR_ERR(map);
}
pmx->map = map;
/* Check that regmap works at first call, then no more */
ret = regmap_read(map, GLOBAL_WORD_ID, &val);
if (ret) {
dev_err(dev, "cannot access regmap\n");
return ret;
}
val >>= 8;
val &= 0xffff;
if (val == 0x3512) {
pmx->is_3512 = true;
pmx->confs = gemini_confs_3512;
pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
gemini_pmx_desc.pins = gemini_3512_pins;
gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
dev_info(dev, "detected 3512 chip variant\n");
} else if (val == 0x3516) {
pmx->is_3516 = true;
pmx->confs = gemini_confs_3516;
pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
gemini_pmx_desc.pins = gemini_3516_pins;
gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
dev_info(dev, "detected 3516 chip variant\n");
} else {
dev_err(dev, "unknown chip ID: %04x\n", val);
return -ENODEV;
}
ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
/* Mask off relevant pads */
val &= PADS_MASK;
/* Invert the meaning of the DRAM+flash pads */
val ^= 0x0f;
/* Print initial state */
tmp = val;
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i],
(val & BIT(i)) ? "enabled" : "disabled");
}
/* Check if flash pin is set */
regmap_read(map, GLOBAL_STATUS, &val);
pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(dev, "could not register pinmux driver\n");
return PTR_ERR(pmx->pctl);
}
dev_info(dev, "initialized Gemini pin control driver\n");
return 0;
}
static const struct of_device_id gemini_pinctrl_match[] = {
{ .compatible = "cortina,gemini-pinctrl" },
{},
};
static struct platform_driver gemini_pmx_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = gemini_pinctrl_match,
},
.probe = gemini_pmx_probe,
};
static int __init gemini_pmx_init(void)
{
return platform_driver_register(&gemini_pmx_driver);
}
arch_initcall(gemini_pmx_init);
|
linux-master
|
drivers/pinctrl/pinctrl-gemini.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/pinctrl/pinctrl-lantiq.c
* based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
*
* Copyright (C) 2012 John Crispin <[email protected]>
*/
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "pinctrl-lantiq.h"
static int ltq_get_group_count(struct pinctrl_dev *pctrldev)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
return info->num_grps;
}
static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev,
unsigned selector)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_grps)
return NULL;
return info->grps[selector].name;
}
static int ltq_get_group_pins(struct pinctrl_dev *pctrldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_grps)
return -EINVAL;
*pins = info->grps[selector].pins;
*num_pins = info->grps[selector].npins;
return 0;
}
static void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
kfree(map[i].data.configs.configs);
kfree(map);
}
static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
static void ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
struct property *pins = of_find_property(np, "lantiq,pins", NULL);
struct property *groups = of_find_property(np, "lantiq,groups", NULL);
unsigned long configs[3];
unsigned num_configs = 0;
struct property *prop;
const char *group, *pin;
const char *function;
int ret, i;
if (!pins && !groups) {
dev_err(pctldev->dev, "%pOFn defines neither pins nor groups\n",
np);
return;
}
if (pins && groups) {
dev_err(pctldev->dev, "%pOFn defines both pins and groups\n",
np);
return;
}
ret = of_property_read_string(np, "lantiq,function", &function);
if (groups && !ret) {
of_property_for_each_string(np, "lantiq,groups", prop, group) {
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->name = function;
(*map)->data.mux.group = group;
(*map)->data.mux.function = function;
(*map)++;
}
}
for (i = 0; i < info->num_params; i++) {
u32 val;
int ret = of_property_read_u32(np,
info->params[i].property, &val);
if (!ret)
configs[num_configs++] =
LTQ_PINCONF_PACK(info->params[i].param,
val);
}
if (!num_configs)
return;
of_property_for_each_string(np, "lantiq,pins", prop, pin) {
(*map)->data.configs.configs = kmemdup(configs,
num_configs * sizeof(unsigned long),
GFP_KERNEL);
(*map)->type = PIN_MAP_TYPE_CONFIGS_PIN;
(*map)->name = pin;
(*map)->data.configs.group_or_pin = pin;
(*map)->data.configs.num_configs = num_configs;
(*map)++;
}
of_property_for_each_string(np, "lantiq,groups", prop, group) {
(*map)->data.configs.configs = kmemdup(configs,
num_configs * sizeof(unsigned long),
GFP_KERNEL);
(*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
(*map)->name = group;
(*map)->data.configs.group_or_pin = group;
(*map)->data.configs.num_configs = num_configs;
(*map)++;
}
}
static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
{
int ret;
ret = of_property_count_strings(np, "lantiq,groups");
if (ret < 0)
ret = of_property_count_strings(np, "lantiq,pins");
return ret;
}
static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned *num_maps)
{
struct pinctrl_map *tmp;
struct device_node *np;
int max_maps = 0;
for_each_child_of_node(np_config, np)
max_maps += ltq_pinctrl_dt_subnode_size(np);
*map = kzalloc(array3_size(max_maps, sizeof(struct pinctrl_map), 2),
GFP_KERNEL);
if (!*map)
return -ENOMEM;
tmp = *map;
for_each_child_of_node(np_config, np)
ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
*num_maps = ((int)(tmp - *map));
return 0;
}
static const struct pinctrl_ops ltq_pctrl_ops = {
.get_groups_count = ltq_get_group_count,
.get_group_name = ltq_get_group_name,
.get_group_pins = ltq_get_group_pins,
.pin_dbg_show = ltq_pinctrl_pin_dbg_show,
.dt_node_to_map = ltq_pinctrl_dt_node_to_map,
.dt_free_map = ltq_pinctrl_dt_free_map,
};
static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
return info->num_funcs;
}
static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev,
unsigned selector)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
if (selector >= info->num_funcs)
return NULL;
return info->funcs[selector].name;
}
static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev,
unsigned func,
const char * const **groups,
unsigned * const num_groups)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
*groups = info->funcs[func].groups;
*num_groups = info->funcs[func].num_groups;
return 0;
}
/* Return function number. If failure, return negative value. */
static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux)
{
int i;
for (i = 0; i < LTQ_MAX_MUX; i++) {
if (mfp->func[i] == mux)
break;
}
if (i >= LTQ_MAX_MUX)
return -EINVAL;
return i;
}
/* don't assume .mfp is linearly mapped. find the mfp with the correct .pin */
static int match_mfp(const struct ltq_pinmux_info *info, int pin)
{
int i;
for (i = 0; i < info->num_mfp; i++) {
if (info->mfp[i].pin == pin)
return i;
}
return -1;
}
/* check whether current pin configuration is valid. Negative for failure */
static int match_group_mux(const struct ltq_pin_group *grp,
const struct ltq_pinmux_info *info,
unsigned mux)
{
int i, pin, ret = 0;
for (i = 0; i < grp->npins; i++) {
pin = match_mfp(info, grp->pins[i]);
if (pin < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n",
grp->pins[i]);
return -EINVAL;
}
ret = match_mux(&info->mfp[pin], mux);
if (ret < 0) {
dev_err(info->dev, "Can't find mux %d on pin%d\n",
mux, pin);
break;
}
}
return ret;
}
static int ltq_pmx_set(struct pinctrl_dev *pctrldev,
unsigned func,
unsigned group)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
const struct ltq_pin_group *pin_grp = &info->grps[group];
int i, pin, pin_func, ret;
if (!pin_grp->npins ||
(match_group_mux(pin_grp, info, pin_grp->mux) < 0)) {
dev_err(info->dev, "Failed to set the pin group: %s\n",
info->grps[group].name);
return -EINVAL;
}
for (i = 0; i < pin_grp->npins; i++) {
pin = match_mfp(info, pin_grp->pins[i]);
if (pin < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n",
pin_grp->pins[i]);
return -EINVAL;
}
pin_func = match_mux(&info->mfp[pin], pin_grp->mux);
ret = info->apply_mux(pctrldev, pin, pin_func);
if (ret) {
dev_err(info->dev,
"failed to apply mux %d for pin %d\n",
pin_func, pin);
return ret;
}
}
return 0;
}
static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int mfp = match_mfp(info, pin);
int pin_func;
if (mfp < 0) {
dev_err(info->dev, "could not find mfp for pin %d\n", pin);
return -EINVAL;
}
pin_func = match_mux(&info->mfp[mfp], 0);
if (pin_func < 0) {
dev_err(info->dev, "No GPIO function on pin%d\n", mfp);
return -EINVAL;
}
return info->apply_mux(pctrldev, mfp, pin_func);
}
static const struct pinmux_ops ltq_pmx_ops = {
.get_functions_count = ltq_pmx_func_count,
.get_function_name = ltq_pmx_func_name,
.get_function_groups = ltq_pmx_get_groups,
.set_mux = ltq_pmx_set,
.gpio_request_enable = ltq_pmx_gpio_request_enable,
};
/*
* allow different socs to register with the generic part of the lanti
* pinctrl code
*/
int ltq_pinctrl_register(struct platform_device *pdev,
struct ltq_pinmux_info *info)
{
struct pinctrl_desc *desc;
if (!info)
return -EINVAL;
desc = info->desc;
desc->pctlops = <q_pctrl_ops;
desc->pmxops = <q_pmx_ops;
info->dev = &pdev->dev;
info->pctrl = devm_pinctrl_register(&pdev->dev, desc, info);
if (IS_ERR(info->pctrl)) {
dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n");
return PTR_ERR(info->pctrl);
}
platform_set_drvdata(pdev, info);
return 0;
}
|
linux-master
|
drivers/pinctrl/pinctrl-lantiq.c
|
/*
* Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
*
* Copyright (C) 2015 Joachim Eastwood <[email protected]>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
/* LPC18XX SCU analog function registers */
#define LPC18XX_SCU_REG_ENAIO0 0xc88
#define LPC18XX_SCU_REG_ENAIO1 0xc8c
#define LPC18XX_SCU_REG_ENAIO2 0xc90
#define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
/* LPC18XX SCU pin register definitions */
#define LPC18XX_SCU_PIN_MODE_MASK 0x7
#define LPC18XX_SCU_PIN_EPD BIT(3)
#define LPC18XX_SCU_PIN_EPUN BIT(4)
#define LPC18XX_SCU_PIN_EHS BIT(5)
#define LPC18XX_SCU_PIN_EZI BIT(6)
#define LPC18XX_SCU_PIN_ZIF BIT(7)
#define LPC18XX_SCU_PIN_EHD_MASK 0x300
#define LPC18XX_SCU_PIN_EHD_POS 8
#define LPC18XX_SCU_USB1_EPD BIT(2)
#define LPC18XX_SCU_USB1_EPWR BIT(4)
#define LPC18XX_SCU_I2C0_EFP BIT(0)
#define LPC18XX_SCU_I2C0_EHD BIT(2)
#define LPC18XX_SCU_I2C0_EZI BIT(3)
#define LPC18XX_SCU_I2C0_ZIF BIT(7)
#define LPC18XX_SCU_I2C0_SCL_SHIFT 0
#define LPC18XX_SCU_I2C0_SDA_SHIFT 8
#define LPC18XX_SCU_FUNC_PER_PIN 8
/* LPC18XX SCU pin interrupt select registers */
#define LPC18XX_SCU_PINTSEL0 0xe00
#define LPC18XX_SCU_PINTSEL1 0xe04
#define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
#define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
#define LPC18XX_SCU_IRQ_PER_PINTSEL 4
#define LPC18XX_GPIO_PINS_PER_PORT 32
#define LPC18XX_GPIO_PIN_INT_MAX 8
#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
/* LPC18xx pin types */
enum {
TYPE_ND, /* Normal-drive */
TYPE_HD, /* High-drive */
TYPE_HS, /* High-speed */
TYPE_I2C0,
TYPE_USB1,
};
/* LPC18xx pin functions */
enum {
FUNC_R, /* Reserved */
FUNC_ADC,
FUNC_ADCTRIG,
FUNC_CAN0,
FUNC_CAN1,
FUNC_CGU_OUT,
FUNC_CLKIN,
FUNC_CLKOUT,
FUNC_CTIN,
FUNC_CTOUT,
FUNC_DAC,
FUNC_EMC,
FUNC_EMC_ALT,
FUNC_ENET,
FUNC_ENET_ALT,
FUNC_GPIO,
FUNC_I2C0,
FUNC_I2C1,
FUNC_I2S0_RX_MCLK,
FUNC_I2S0_RX_SCK,
FUNC_I2S0_RX_SDA,
FUNC_I2S0_RX_WS,
FUNC_I2S0_TX_MCLK,
FUNC_I2S0_TX_SCK,
FUNC_I2S0_TX_SDA,
FUNC_I2S0_TX_WS,
FUNC_I2S1,
FUNC_LCD,
FUNC_LCD_ALT,
FUNC_MCTRL,
FUNC_NMI,
FUNC_QEI,
FUNC_SDMMC,
FUNC_SGPIO,
FUNC_SPI,
FUNC_SPIFI,
FUNC_SSP0,
FUNC_SSP0_ALT,
FUNC_SSP1,
FUNC_TIMER0,
FUNC_TIMER1,
FUNC_TIMER2,
FUNC_TIMER3,
FUNC_TRACE,
FUNC_UART0,
FUNC_UART1,
FUNC_UART2,
FUNC_UART3,
FUNC_USB0,
FUNC_USB1,
FUNC_MAX
};
static const char *const lpc18xx_function_names[] = {
[FUNC_R] = "reserved",
[FUNC_ADC] = "adc",
[FUNC_ADCTRIG] = "adctrig",
[FUNC_CAN0] = "can0",
[FUNC_CAN1] = "can1",
[FUNC_CGU_OUT] = "cgu_out",
[FUNC_CLKIN] = "clkin",
[FUNC_CLKOUT] = "clkout",
[FUNC_CTIN] = "ctin",
[FUNC_CTOUT] = "ctout",
[FUNC_DAC] = "dac",
[FUNC_EMC] = "emc",
[FUNC_EMC_ALT] = "emc_alt",
[FUNC_ENET] = "enet",
[FUNC_ENET_ALT] = "enet_alt",
[FUNC_GPIO] = "gpio",
[FUNC_I2C0] = "i2c0",
[FUNC_I2C1] = "i2c1",
[FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
[FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
[FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
[FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
[FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
[FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
[FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
[FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
[FUNC_I2S1] = "i2s1",
[FUNC_LCD] = "lcd",
[FUNC_LCD_ALT] = "lcd_alt",
[FUNC_MCTRL] = "mctrl",
[FUNC_NMI] = "nmi",
[FUNC_QEI] = "qei",
[FUNC_SDMMC] = "sdmmc",
[FUNC_SGPIO] = "sgpio",
[FUNC_SPI] = "spi",
[FUNC_SPIFI] = "spifi",
[FUNC_SSP0] = "ssp0",
[FUNC_SSP0_ALT] = "ssp0_alt",
[FUNC_SSP1] = "ssp1",
[FUNC_TIMER0] = "timer0",
[FUNC_TIMER1] = "timer1",
[FUNC_TIMER2] = "timer2",
[FUNC_TIMER3] = "timer3",
[FUNC_TRACE] = "trace",
[FUNC_UART0] = "uart0",
[FUNC_UART1] = "uart1",
[FUNC_UART2] = "uart2",
[FUNC_UART3] = "uart3",
[FUNC_USB0] = "usb0",
[FUNC_USB1] = "usb1",
};
struct lpc18xx_pmx_func {
const char **groups;
unsigned ngroups;
};
struct lpc18xx_scu_data {
struct pinctrl_dev *pctl;
void __iomem *base;
struct clk *clk;
struct lpc18xx_pmx_func func[FUNC_MAX];
};
struct lpc18xx_pin_caps {
unsigned int offset;
unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
unsigned char analog;
unsigned char type;
};
/* Analog pins are required to have both bias and input disabled */
#define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
/* Macros to maniupluate analog member in lpc18xx_pin_caps */
#define LPC18XX_ANALOG_PIN BIT(7)
#define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
#define LPC18XX_ANALOG_BIT_MASK 0x1f
#define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
#define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
#define DAC LPC18XX_ANALOG_PIN
#define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
.offset = 0x##port * 32 * 4 + pin * 4, \
.functions = { \
FUNC_##f0, FUNC_##f1, FUNC_##f2, \
FUNC_##f3, FUNC_##f4, FUNC_##f5, \
FUNC_##f6, FUNC_##f7, \
}, \
.analog = a, \
.type = TYPE_##t, \
}
#define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
.offset = off, \
.functions = { \
FUNC_##f0, FUNC_##f1, FUNC_##f2, \
FUNC_##f3, FUNC_##f4, FUNC_##f5, \
FUNC_##f6, FUNC_##f7, \
}, \
.analog = a, \
.type = TYPE_##t, \
}
/* Pinmuxing table taken from data sheet */
/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
/* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
#define LPC18XX_PIN_P(port, pin) { \
.number = 0x##port * 32 + pin, \
.name = "p"#port"_"#pin, \
.drv_data = &lpc18xx_pin_p##port##_##pin \
}
/* Pin numbers for special pins */
enum {
PIN_CLK0 = 600,
PIN_CLK1,
PIN_CLK2,
PIN_CLK3,
PIN_USB1_DM,
PIN_USB1_DP,
PIN_I2C0_SCL,
PIN_I2C0_SDA,
};
#define LPC18XX_PIN(pname, n) { \
.number = n, \
.name = #pname, \
.drv_data = &lpc18xx_pin_##pname \
}
static const struct pinctrl_pin_desc lpc18xx_pins[] = {
LPC18XX_PIN_P(0,0),
LPC18XX_PIN_P(0,1),
LPC18XX_PIN_P(1,0),
LPC18XX_PIN_P(1,1),
LPC18XX_PIN_P(1,2),
LPC18XX_PIN_P(1,3),
LPC18XX_PIN_P(1,4),
LPC18XX_PIN_P(1,5),
LPC18XX_PIN_P(1,6),
LPC18XX_PIN_P(1,7),
LPC18XX_PIN_P(1,8),
LPC18XX_PIN_P(1,9),
LPC18XX_PIN_P(1,10),
LPC18XX_PIN_P(1,11),
LPC18XX_PIN_P(1,12),
LPC18XX_PIN_P(1,13),
LPC18XX_PIN_P(1,14),
LPC18XX_PIN_P(1,15),
LPC18XX_PIN_P(1,16),
LPC18XX_PIN_P(1,17),
LPC18XX_PIN_P(1,18),
LPC18XX_PIN_P(1,19),
LPC18XX_PIN_P(1,20),
LPC18XX_PIN_P(2,0),
LPC18XX_PIN_P(2,1),
LPC18XX_PIN_P(2,2),
LPC18XX_PIN_P(2,3),
LPC18XX_PIN_P(2,4),
LPC18XX_PIN_P(2,5),
LPC18XX_PIN_P(2,6),
LPC18XX_PIN_P(2,7),
LPC18XX_PIN_P(2,8),
LPC18XX_PIN_P(2,9),
LPC18XX_PIN_P(2,10),
LPC18XX_PIN_P(2,11),
LPC18XX_PIN_P(2,12),
LPC18XX_PIN_P(2,13),
LPC18XX_PIN_P(3,0),
LPC18XX_PIN_P(3,1),
LPC18XX_PIN_P(3,2),
LPC18XX_PIN_P(3,3),
LPC18XX_PIN_P(3,4),
LPC18XX_PIN_P(3,5),
LPC18XX_PIN_P(3,6),
LPC18XX_PIN_P(3,7),
LPC18XX_PIN_P(3,8),
LPC18XX_PIN_P(4,0),
LPC18XX_PIN_P(4,1),
LPC18XX_PIN_P(4,2),
LPC18XX_PIN_P(4,3),
LPC18XX_PIN_P(4,4),
LPC18XX_PIN_P(4,5),
LPC18XX_PIN_P(4,6),
LPC18XX_PIN_P(4,7),
LPC18XX_PIN_P(4,8),
LPC18XX_PIN_P(4,9),
LPC18XX_PIN_P(4,10),
LPC18XX_PIN_P(5,0),
LPC18XX_PIN_P(5,1),
LPC18XX_PIN_P(5,2),
LPC18XX_PIN_P(5,3),
LPC18XX_PIN_P(5,4),
LPC18XX_PIN_P(5,5),
LPC18XX_PIN_P(5,6),
LPC18XX_PIN_P(5,7),
LPC18XX_PIN_P(6,0),
LPC18XX_PIN_P(6,1),
LPC18XX_PIN_P(6,2),
LPC18XX_PIN_P(6,3),
LPC18XX_PIN_P(6,4),
LPC18XX_PIN_P(6,5),
LPC18XX_PIN_P(6,6),
LPC18XX_PIN_P(6,7),
LPC18XX_PIN_P(6,8),
LPC18XX_PIN_P(6,9),
LPC18XX_PIN_P(6,10),
LPC18XX_PIN_P(6,11),
LPC18XX_PIN_P(6,12),
LPC18XX_PIN_P(7,0),
LPC18XX_PIN_P(7,1),
LPC18XX_PIN_P(7,2),
LPC18XX_PIN_P(7,3),
LPC18XX_PIN_P(7,4),
LPC18XX_PIN_P(7,5),
LPC18XX_PIN_P(7,6),
LPC18XX_PIN_P(7,7),
LPC18XX_PIN_P(8,0),
LPC18XX_PIN_P(8,1),
LPC18XX_PIN_P(8,2),
LPC18XX_PIN_P(8,3),
LPC18XX_PIN_P(8,4),
LPC18XX_PIN_P(8,5),
LPC18XX_PIN_P(8,6),
LPC18XX_PIN_P(8,7),
LPC18XX_PIN_P(8,8),
LPC18XX_PIN_P(9,0),
LPC18XX_PIN_P(9,1),
LPC18XX_PIN_P(9,2),
LPC18XX_PIN_P(9,3),
LPC18XX_PIN_P(9,4),
LPC18XX_PIN_P(9,5),
LPC18XX_PIN_P(9,6),
LPC18XX_PIN_P(a,0),
LPC18XX_PIN_P(a,1),
LPC18XX_PIN_P(a,2),
LPC18XX_PIN_P(a,3),
LPC18XX_PIN_P(a,4),
LPC18XX_PIN_P(b,0),
LPC18XX_PIN_P(b,1),
LPC18XX_PIN_P(b,2),
LPC18XX_PIN_P(b,3),
LPC18XX_PIN_P(b,4),
LPC18XX_PIN_P(b,5),
LPC18XX_PIN_P(b,6),
LPC18XX_PIN_P(c,0),
LPC18XX_PIN_P(c,1),
LPC18XX_PIN_P(c,2),
LPC18XX_PIN_P(c,3),
LPC18XX_PIN_P(c,4),
LPC18XX_PIN_P(c,5),
LPC18XX_PIN_P(c,6),
LPC18XX_PIN_P(c,7),
LPC18XX_PIN_P(c,8),
LPC18XX_PIN_P(c,9),
LPC18XX_PIN_P(c,10),
LPC18XX_PIN_P(c,11),
LPC18XX_PIN_P(c,12),
LPC18XX_PIN_P(c,13),
LPC18XX_PIN_P(c,14),
LPC18XX_PIN_P(d,0),
LPC18XX_PIN_P(d,1),
LPC18XX_PIN_P(d,2),
LPC18XX_PIN_P(d,3),
LPC18XX_PIN_P(d,4),
LPC18XX_PIN_P(d,5),
LPC18XX_PIN_P(d,6),
LPC18XX_PIN_P(d,7),
LPC18XX_PIN_P(d,8),
LPC18XX_PIN_P(d,9),
LPC18XX_PIN_P(d,10),
LPC18XX_PIN_P(d,11),
LPC18XX_PIN_P(d,12),
LPC18XX_PIN_P(d,13),
LPC18XX_PIN_P(d,14),
LPC18XX_PIN_P(d,15),
LPC18XX_PIN_P(d,16),
LPC18XX_PIN_P(e,0),
LPC18XX_PIN_P(e,1),
LPC18XX_PIN_P(e,2),
LPC18XX_PIN_P(e,3),
LPC18XX_PIN_P(e,4),
LPC18XX_PIN_P(e,5),
LPC18XX_PIN_P(e,6),
LPC18XX_PIN_P(e,7),
LPC18XX_PIN_P(e,8),
LPC18XX_PIN_P(e,9),
LPC18XX_PIN_P(e,10),
LPC18XX_PIN_P(e,11),
LPC18XX_PIN_P(e,12),
LPC18XX_PIN_P(e,13),
LPC18XX_PIN_P(e,14),
LPC18XX_PIN_P(e,15),
LPC18XX_PIN_P(f,0),
LPC18XX_PIN_P(f,1),
LPC18XX_PIN_P(f,2),
LPC18XX_PIN_P(f,3),
LPC18XX_PIN_P(f,4),
LPC18XX_PIN_P(f,5),
LPC18XX_PIN_P(f,6),
LPC18XX_PIN_P(f,7),
LPC18XX_PIN_P(f,8),
LPC18XX_PIN_P(f,9),
LPC18XX_PIN_P(f,10),
LPC18XX_PIN_P(f,11),
LPC18XX_PIN(clk0, PIN_CLK0),
LPC18XX_PIN(clk1, PIN_CLK1),
LPC18XX_PIN(clk2, PIN_CLK2),
LPC18XX_PIN(clk3, PIN_CLK3),
LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
};
/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params lpc18xx_params[] = {
{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
};
#endif
static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
{
switch (param) {
case PIN_CONFIG_MODE_LOW_POWER:
if (reg & LPC18XX_SCU_USB1_EPWR)
*arg = 0;
else
*arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
if (reg & LPC18XX_SCU_USB1_EPD)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (reg & LPC18XX_SCU_USB1_EPD)
*arg = 1;
else
return -EINVAL;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
unsigned pin)
{
u8 shift;
if (pin == PIN_I2C0_SCL)
shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
else
shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
*arg = 1;
else
return -EINVAL;
break;
case PIN_CONFIG_SLEW_RATE:
if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
*arg = 1;
else
*arg = 0;
break;
case PIN_CONFIG_INPUT_SCHMITT:
if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
*arg = 3;
else
*arg = 50;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
return -EINVAL;
else
*arg = 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
{
struct pinctrl_gpio_range *range;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range)
return -EINVAL;
return pin - range->pin_base + range->base;
}
static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
{
u32 reg_val;
int i;
reg_val = readl(addr);
for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
return 0;
reg_val >>= BITS_PER_BYTE;
*arg += 1;
}
return -EINVAL;
}
static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
{
unsigned int gpio_port, gpio_pin;
gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
}
static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
int *arg, unsigned pin)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
int gpio, ret;
u32 val;
gpio = lpc18xx_pin_to_gpio(pctldev, pin);
if (gpio < 0)
return -ENOTSUPP;
val = lpc18xx_gpio_to_pintsel_val(gpio);
/*
* Check if this pin has been enabled as a interrupt in any of the two
* PINTSEL registers. *arg indicates which interrupt number (0-7).
*/
*arg = 0;
ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
if (ret == 0)
return ret;
return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
}
static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
int *arg, u32 reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
;
else
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (reg & LPC18XX_SCU_PIN_EPUN)
return -EINVAL;
else
*arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (reg & LPC18XX_SCU_PIN_EPD)
*arg = 1;
else
return -EINVAL;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (reg & LPC18XX_SCU_PIN_EZI)
*arg = 1;
else
return -EINVAL;
break;
case PIN_CONFIG_SLEW_RATE:
if (pin_cap->type == TYPE_HD)
return -ENOTSUPP;
if (reg & LPC18XX_SCU_PIN_EHS)
*arg = 1;
else
*arg = 0;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (reg & LPC18XX_SCU_PIN_ZIF)
return -EINVAL;
else
*arg = 1;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (pin_cap->type != TYPE_HD)
return -ENOTSUPP;
*arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
switch (*arg) {
case 3: *arg += 5;
fallthrough;
case 2: *arg += 5;
fallthrough;
case 1: *arg += 3;
fallthrough;
case 0: *arg += 4;
}
break;
case PIN_CONFIG_GPIO_PIN_INT:
return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
default:
return -ENOTSUPP;
}
return 0;
}
static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
{
int i;
for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
if (lpc18xx_pins[i].number == pin)
return lpc18xx_pins[i].drv_data;
}
return NULL;
}
static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
struct lpc18xx_pin_caps *pin_cap;
int ret, arg = 0;
u32 reg;
pin_cap = lpc18xx_get_pin_caps(pin);
if (!pin_cap)
return -EINVAL;
reg = readl(scu->base + pin_cap->offset);
if (pin_cap->type == TYPE_I2C0)
ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
else
ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
if (ret < 0)
return ret;
*config = pinconf_to_config_packed(param, (u16)arg);
return 0;
}
static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
enum pin_config_param param,
u32 param_val, u32 *reg)
{
switch (param) {
case PIN_CONFIG_MODE_LOW_POWER:
if (param_val)
*reg &= ~LPC18XX_SCU_USB1_EPWR;
else
*reg |= LPC18XX_SCU_USB1_EPWR;
break;
case PIN_CONFIG_BIAS_DISABLE:
*reg &= ~LPC18XX_SCU_USB1_EPD;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*reg |= LPC18XX_SCU_USB1_EPD;
break;
default:
dev_err(pctldev->dev, "Property not supported\n");
return -ENOTSUPP;
}
return 0;
}
static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
enum pin_config_param param,
u32 param_val, u32 *reg,
unsigned pin)
{
u8 shift;
if (pin == PIN_I2C0_SCL)
shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
else
shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
if (param_val)
*reg |= (LPC18XX_SCU_I2C0_EZI << shift);
else
*reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
break;
case PIN_CONFIG_SLEW_RATE:
if (param_val)
*reg |= (LPC18XX_SCU_I2C0_EHD << shift);
else
*reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
break;
case PIN_CONFIG_INPUT_SCHMITT:
if (param_val == 3)
*reg |= (LPC18XX_SCU_I2C0_EFP << shift);
else if (param_val == 50)
*reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
else
return -ENOTSUPP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (param_val)
*reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
else
*reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
break;
default:
dev_err(pctldev->dev, "Property not supported\n");
return -ENOTSUPP;
}
return 0;
}
static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
u32 param_val, unsigned pin)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
int gpio;
if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
return -EINVAL;
gpio = lpc18xx_pin_to_gpio(pctldev, pin);
if (gpio < 0)
return -ENOTSUPP;
val = lpc18xx_gpio_to_pintsel_val(gpio);
reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
reg_val = readl(scu->base + reg_offset);
reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
writel(reg_val, scu->base + reg_offset);
return 0;
}
static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
u32 param_val, u32 *reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
*reg &= ~LPC18XX_SCU_PIN_EPD;
*reg |= LPC18XX_SCU_PIN_EPUN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*reg &= ~LPC18XX_SCU_PIN_EPUN;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*reg |= LPC18XX_SCU_PIN_EPD;
break;
case PIN_CONFIG_INPUT_ENABLE:
if (param_val)
*reg |= LPC18XX_SCU_PIN_EZI;
else
*reg &= ~LPC18XX_SCU_PIN_EZI;
break;
case PIN_CONFIG_SLEW_RATE:
if (pin_cap->type == TYPE_HD) {
dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
return -ENOTSUPP;
}
if (param_val == 0)
*reg &= ~LPC18XX_SCU_PIN_EHS;
else
*reg |= LPC18XX_SCU_PIN_EHS;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (param_val)
*reg &= ~LPC18XX_SCU_PIN_ZIF;
else
*reg |= LPC18XX_SCU_PIN_ZIF;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
if (pin_cap->type != TYPE_HD) {
dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
return -ENOTSUPP;
}
*reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
switch (param_val) {
case 20: param_val -= 5;
fallthrough;
case 14: param_val -= 5;
fallthrough;
case 8: param_val -= 3;
fallthrough;
case 4: param_val -= 4;
break;
default:
dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
return -ENOTSUPP;
}
*reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
break;
case PIN_CONFIG_GPIO_PIN_INT:
return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
default:
dev_err(pctldev->dev, "Property not supported\n");
return -ENOTSUPP;
}
return 0;
}
static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
struct lpc18xx_pin_caps *pin_cap;
enum pin_config_param param;
u32 param_val;
u32 reg;
int ret;
int i;
pin_cap = lpc18xx_get_pin_caps(pin);
if (!pin_cap)
return -EINVAL;
reg = readl(scu->base + pin_cap->offset);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
if (pin_cap->type == TYPE_I2C0)
ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin);
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®);
else
ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap);
if (ret)
return ret;
}
writel(reg, scu->base + pin_cap->offset);
return 0;
}
static const struct pinconf_ops lpc18xx_pconf_ops = {
.is_generic = true,
.pin_config_get = lpc18xx_pconf_get,
.pin_config_set = lpc18xx_pconf_set,
};
static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(lpc18xx_function_names);
}
static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
return lpc18xx_function_names[function];
}
static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char *const **groups,
unsigned *const num_groups)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
*groups = scu->func[function].groups;
*num_groups = scu->func[function].ngroups;
return 0;
}
static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
int func;
u32 reg;
/* Dedicated USB1 and I2C0 pins doesn't support muxing */
if (pin->type == TYPE_USB1) {
if (function == FUNC_USB1)
return 0;
goto fail;
}
if (pin->type == TYPE_I2C0) {
if (function == FUNC_I2C0)
return 0;
goto fail;
}
if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
u32 offset;
writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
offset = LPC18XX_SCU_REG_ENAIO0;
else
offset = LPC18XX_SCU_REG_ENAIO1;
reg = readl(scu->base + offset);
reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
writel(reg, scu->base + offset);
return 0;
}
if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
return 0;
}
for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
if (function == pin->functions[func])
break;
}
if (func >= LPC18XX_SCU_FUNC_PER_PIN)
goto fail;
reg = readl(scu->base + pin->offset);
reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
writel(reg | func, scu->base + pin->offset);
return 0;
fail:
dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
lpc18xx_function_names[function]);
return -EINVAL;
}
static const struct pinmux_ops lpc18xx_pmx_ops = {
.get_functions_count = lpc18xx_pmx_get_funcs_count,
.get_function_name = lpc18xx_pmx_get_func_name,
.get_function_groups = lpc18xx_pmx_get_func_groups,
.set_mux = lpc18xx_pmx_set,
};
static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(lpc18xx_pins);
}
static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return lpc18xx_pins[group].name;
}
static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
*pins = &lpc18xx_pins[group].number;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops lpc18xx_pctl_ops = {
.get_groups_count = lpc18xx_pctl_get_groups_count,
.get_group_name = lpc18xx_pctl_get_group_name,
.get_group_pins = lpc18xx_pctl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static struct pinctrl_desc lpc18xx_scu_desc = {
.name = "lpc18xx/43xx-scu",
.pins = lpc18xx_pins,
.npins = ARRAY_SIZE(lpc18xx_pins),
.pctlops = &lpc18xx_pctl_ops,
.pmxops = &lpc18xx_pmx_ops,
.confops = &lpc18xx_pconf_ops,
.num_custom_params = ARRAY_SIZE(lpc18xx_params),
.custom_params = lpc18xx_params,
#ifdef CONFIG_DEBUG_FS
.custom_conf_items = lpc18xx_conf_items,
#endif
.owner = THIS_MODULE,
};
static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
{
struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
int i;
if (function == FUNC_DAC && p->analog == DAC)
return true;
if (function == FUNC_ADC && p->analog)
return true;
if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
return true;
if (function == FUNC_USB1 && p->type == TYPE_USB1)
return true;
for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
if (function == p->functions[i])
return true;
}
return false;
}
static int lpc18xx_create_group_func_map(struct device *dev,
struct lpc18xx_scu_data *scu)
{
u16 pins[ARRAY_SIZE(lpc18xx_pins)];
int func, ngroups, i;
for (func = 0; func < FUNC_MAX; func++) {
for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
if (lpc18xx_valid_pin_function(i, func))
pins[ngroups++] = i;
}
scu->func[func].ngroups = ngroups;
scu->func[func].groups = devm_kcalloc(dev,
ngroups, sizeof(char *),
GFP_KERNEL);
if (!scu->func[func].groups)
return -ENOMEM;
for (i = 0; i < ngroups; i++)
scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
}
return 0;
}
static int lpc18xx_scu_probe(struct platform_device *pdev)
{
struct lpc18xx_scu_data *scu;
int ret;
scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
if (!scu)
return -ENOMEM;
scu->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(scu->base))
return PTR_ERR(scu->base);
scu->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(scu->clk)) {
dev_err(&pdev->dev, "Input clock not found.\n");
return PTR_ERR(scu->clk);
}
ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
if (ret) {
dev_err(&pdev->dev, "Unable to create group func map.\n");
return ret;
}
ret = clk_prepare_enable(scu->clk);
if (ret) {
dev_err(&pdev->dev, "Unable to enable clock.\n");
return ret;
}
platform_set_drvdata(pdev, scu);
scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
if (IS_ERR(scu->pctl)) {
dev_err(&pdev->dev, "Could not register pinctrl driver\n");
clk_disable_unprepare(scu->clk);
return PTR_ERR(scu->pctl);
}
return 0;
}
static const struct of_device_id lpc18xx_scu_match[] = {
{ .compatible = "nxp,lpc1850-scu" },
{},
};
static struct platform_driver lpc18xx_scu_driver = {
.probe = lpc18xx_scu_probe,
.driver = {
.name = "lpc18xx-scu",
.of_match_table = lpc18xx_scu_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver(lpc18xx_scu_driver);
|
linux-master
|
drivers/pinctrl/pinctrl-lpc18xx.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Pinctrl driver for Rockchip RK805/RK806 PMIC
*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
* Author: Joseph Chen <[email protected]>
* Author: Xu Shengfei <[email protected]>
*
* Based on the pinctrl-as3722 driver
*/
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/rk808.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
struct rk805_pin_function {
const char *name;
const char *const *groups;
unsigned int ngroups;
int mux_option;
};
struct rk805_pin_group {
const char *name;
const unsigned int pins[1];
unsigned int npins;
};
/*
* @reg: gpio setting register;
* @fun_reg: functions select register;
* @fun_mask: functions select mask value, when set is gpio;
* @dir_mask: input or output mask value, when set is output, otherwise input;
* @val_mask: gpio set value, when set is level high, otherwise low;
*
* Different PMIC has different pin features, belowing 3 mask members are not
* all necessary for every PMIC. For example, RK805 has 2 pins that can be used
* as output only GPIOs, so func_mask and dir_mask are not needed. RK816 has 1
* pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all
* necessary.
*/
struct rk805_pin_config {
u8 reg;
u8 fun_reg;
u8 fun_msk;
u8 dir_msk;
u8 val_msk;
};
struct rk805_pctrl_info {
struct rk808 *rk808;
struct device *dev;
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct pinctrl_desc pinctrl_desc;
const struct rk805_pin_function *functions;
unsigned int num_functions;
const struct rk805_pin_group *groups;
int num_pin_groups;
const struct pinctrl_pin_desc *pins;
unsigned int num_pins;
const struct rk805_pin_config *pin_cfg;
};
enum rk805_pinmux_option {
RK805_PINMUX_GPIO,
};
enum rk806_pinmux_option {
RK806_PINMUX_FUN0 = 0,
RK806_PINMUX_FUN1,
RK806_PINMUX_FUN2,
RK806_PINMUX_FUN3,
RK806_PINMUX_FUN4,
RK806_PINMUX_FUN5,
};
enum {
RK805_GPIO0,
RK805_GPIO1,
};
enum {
RK806_GPIO_DVS1,
RK806_GPIO_DVS2,
RK806_GPIO_DVS3
};
static const char *const rk805_gpio_groups[] = {
"gpio0",
"gpio1",
};
static const char *const rk806_gpio_groups[] = {
"gpio_pwrctrl1",
"gpio_pwrctrl2",
"gpio_pwrctrl3",
};
/* RK805: 2 output only GPIOs */
static const struct pinctrl_pin_desc rk805_pins_desc[] = {
PINCTRL_PIN(RK805_GPIO0, "gpio0"),
PINCTRL_PIN(RK805_GPIO1, "gpio1"),
};
/* RK806 */
static const struct pinctrl_pin_desc rk806_pins_desc[] = {
PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"),
PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"),
PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
};
static const struct rk805_pin_function rk805_pin_functions[] = {
{
.name = "gpio",
.groups = rk805_gpio_groups,
.ngroups = ARRAY_SIZE(rk805_gpio_groups),
.mux_option = RK805_PINMUX_GPIO,
},
};
static const struct rk805_pin_function rk806_pin_functions[] = {
{
.name = "pin_fun0",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN0,
},
{
.name = "pin_fun1",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN1,
},
{
.name = "pin_fun2",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN2,
},
{
.name = "pin_fun3",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN3,
},
{
.name = "pin_fun4",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN4,
},
{
.name = "pin_fun5",
.groups = rk806_gpio_groups,
.ngroups = ARRAY_SIZE(rk806_gpio_groups),
.mux_option = RK806_PINMUX_FUN5,
},
};
static const struct rk805_pin_group rk805_pin_groups[] = {
{
.name = "gpio0",
.pins = { RK805_GPIO0 },
.npins = 1,
},
{
.name = "gpio1",
.pins = { RK805_GPIO1 },
.npins = 1,
},
};
static const struct rk805_pin_group rk806_pin_groups[] = {
{
.name = "gpio_pwrctrl1",
.pins = { RK806_GPIO_DVS1 },
.npins = 1,
},
{
.name = "gpio_pwrctrl2",
.pins = { RK806_GPIO_DVS2 },
.npins = 1,
},
{
.name = "gpio_pwrctrl3",
.pins = { RK806_GPIO_DVS3 },
.npins = 1,
}
};
#define RK805_GPIO0_VAL_MSK BIT(0)
#define RK805_GPIO1_VAL_MSK BIT(1)
static const struct rk805_pin_config rk805_gpio_cfgs[] = {
{
.reg = RK805_OUT_REG,
.val_msk = RK805_GPIO0_VAL_MSK,
},
{
.reg = RK805_OUT_REG,
.val_msk = RK805_GPIO1_VAL_MSK,
},
};
#define RK806_PWRCTRL1_DR BIT(0)
#define RK806_PWRCTRL2_DR BIT(1)
#define RK806_PWRCTRL3_DR BIT(2)
#define RK806_PWRCTRL1_DATA BIT(4)
#define RK806_PWRCTRL2_DATA BIT(5)
#define RK806_PWRCTRL3_DATA BIT(6)
#define RK806_PWRCTRL1_FUN GENMASK(2, 0)
#define RK806_PWRCTRL2_FUN GENMASK(6, 4)
#define RK806_PWRCTRL3_FUN GENMASK(2, 0)
static struct rk805_pin_config rk806_gpio_cfgs[] = {
{
.fun_reg = RK806_SLEEP_CONFIG0,
.fun_msk = RK806_PWRCTRL1_FUN,
.reg = RK806_SLEEP_GPIO,
.val_msk = RK806_PWRCTRL1_DATA,
.dir_msk = RK806_PWRCTRL1_DR,
},
{
.fun_reg = RK806_SLEEP_CONFIG0,
.fun_msk = RK806_PWRCTRL2_FUN,
.reg = RK806_SLEEP_GPIO,
.val_msk = RK806_PWRCTRL2_DATA,
.dir_msk = RK806_PWRCTRL2_DR,
},
{
.fun_reg = RK806_SLEEP_CONFIG1,
.fun_msk = RK806_PWRCTRL3_FUN,
.reg = RK806_SLEEP_GPIO,
.val_msk = RK806_PWRCTRL3_DATA,
.dir_msk = RK806_PWRCTRL3_DR,
}
};
/* generic gpio chip */
static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
int ret, val;
ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val);
if (ret) {
dev_err(pci->dev, "get gpio%d value failed\n", offset);
return ret;
}
return !!(val & pci->pin_cfg[offset].val_msk);
}
static void rk805_gpio_set(struct gpio_chip *chip,
unsigned int offset,
int value)
{
struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
int ret;
ret = regmap_update_bits(pci->rk808->regmap,
pci->pin_cfg[offset].reg,
pci->pin_cfg[offset].val_msk,
value ? pci->pin_cfg[offset].val_msk : 0);
if (ret)
dev_err(pci->dev, "set gpio%d value %d failed\n",
offset, value);
}
static int rk805_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int rk805_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
rk805_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
unsigned int val;
int ret;
/* default output*/
if (!pci->pin_cfg[offset].dir_msk)
return GPIO_LINE_DIRECTION_OUT;
ret = regmap_read(pci->rk808->regmap,
pci->pin_cfg[offset].reg,
&val);
if (ret) {
dev_err(pci->dev, "get gpio%d direction failed\n", offset);
return ret;
}
if (val & pci->pin_cfg[offset].dir_msk)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static const struct gpio_chip rk805_gpio_chip = {
.label = "rk805-gpio",
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = rk805_gpio_get_direction,
.get = rk805_gpio_get,
.set = rk805_gpio_set,
.direction_input = rk805_gpio_direction_input,
.direction_output = rk805_gpio_direction_output,
.can_sleep = true,
.base = -1,
.owner = THIS_MODULE,
};
/* generic pinctrl */
static int rk805_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->num_pin_groups;
}
static const char *rk805_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->groups[group].name;
}
static int rk805_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
*pins = pci->groups[group].pins;
*num_pins = pci->groups[group].npins;
return 0;
}
static const struct pinctrl_ops rk805_pinctrl_ops = {
.get_groups_count = rk805_pinctrl_get_groups_count,
.get_group_name = rk805_pinctrl_get_group_name,
.get_group_pins = rk805_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int rk805_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->num_functions;
}
static const char *rk805_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
return pci->functions[function].name;
}
static int rk805_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char *const **groups,
unsigned int *const num_groups)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
*groups = pci->functions[function].groups;
*num_groups = pci->functions[function].ngroups;
return 0;
}
static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int offset,
int mux)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
int ret;
if (!pci->pin_cfg[offset].fun_msk)
return 0;
mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
ret = regmap_update_bits(pci->rk808->regmap,
pci->pin_cfg[offset].fun_reg,
pci->pin_cfg[offset].fun_msk, mux);
if (ret)
dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
return 0;
}
static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
int mux = pci->functions[function].mux_option;
int offset = group;
return _rk805_pinctrl_set_mux(pctldev, offset, mux);
}
static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
switch (pci->rk808->variant) {
case RK805_ID:
return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
case RK806_ID:
return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
}
return -ENOTSUPP;
}
static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
int ret;
/* set direction */
if (!pci->pin_cfg[offset].dir_msk)
return 0;
ret = regmap_update_bits(pci->rk808->regmap,
pci->pin_cfg[offset].reg,
pci->pin_cfg[offset].dir_msk,
input ? 0 : pci->pin_cfg[offset].dir_msk);
if (ret) {
dev_err(pci->dev, "set gpio%d direction failed\n", offset);
return ret;
}
return ret;
}
static const struct pinmux_ops rk805_pinmux_ops = {
.get_functions_count = rk805_pinctrl_get_funcs_count,
.get_function_name = rk805_pinctrl_get_func_name,
.get_function_groups = rk805_pinctrl_get_func_groups,
.set_mux = rk805_pinctrl_set_mux,
.gpio_request_enable = rk805_pinctrl_gpio_request_enable,
.gpio_set_direction = rk805_pmx_gpio_set_direction,
};
static int rk805_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 arg = 0;
switch (param) {
case PIN_CONFIG_OUTPUT:
case PIN_CONFIG_INPUT_ENABLE:
arg = rk805_gpio_get(&pci->gpio_chip, pin);
break;
default:
dev_err(pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, (u16)arg);
return 0;
}
static int rk805_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 i, arg = 0;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_OUTPUT:
rk805_gpio_set(&pci->gpio_chip, pin, arg);
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
case PIN_CONFIG_INPUT_ENABLE:
if (pci->rk808->variant != RK805_ID && arg) {
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true);
break;
}
fallthrough;
default:
dev_err(pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
}
return 0;
}
static const struct pinconf_ops rk805_pinconf_ops = {
.pin_config_get = rk805_pinconf_get,
.pin_config_set = rk805_pinconf_set,
};
static const struct pinctrl_desc rk805_pinctrl_desc = {
.name = "rk805-pinctrl",
.pctlops = &rk805_pinctrl_ops,
.pmxops = &rk805_pinmux_ops,
.confops = &rk805_pinconf_ops,
.owner = THIS_MODULE,
};
static int rk805_pinctrl_probe(struct platform_device *pdev)
{
struct rk805_pctrl_info *pci;
int ret;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
if (!pci)
return -ENOMEM;
pci->dev = &pdev->dev;
pci->rk808 = dev_get_drvdata(pdev->dev.parent);
pci->pinctrl_desc = rk805_pinctrl_desc;
pci->gpio_chip = rk805_gpio_chip;
pci->gpio_chip.parent = &pdev->dev;
platform_set_drvdata(pdev, pci);
switch (pci->rk808->variant) {
case RK805_ID:
pci->pins = rk805_pins_desc;
pci->num_pins = ARRAY_SIZE(rk805_pins_desc);
pci->functions = rk805_pin_functions;
pci->num_functions = ARRAY_SIZE(rk805_pin_functions);
pci->groups = rk805_pin_groups;
pci->num_pin_groups = ARRAY_SIZE(rk805_pin_groups);
pci->pinctrl_desc.pins = rk805_pins_desc;
pci->pinctrl_desc.npins = ARRAY_SIZE(rk805_pins_desc);
pci->pin_cfg = rk805_gpio_cfgs;
pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
break;
case RK806_ID:
pci->pins = rk806_pins_desc;
pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
pci->functions = rk806_pin_functions;
pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
pci->groups = rk806_pin_groups;
pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
pci->pinctrl_desc.pins = rk806_pins_desc;
pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
pci->pin_cfg = rk806_gpio_cfgs;
pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
break;
default:
dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
pci->rk808->variant);
return -EINVAL;
}
/* Add gpio chip */
ret = devm_gpiochip_add_data(&pdev->dev, &pci->gpio_chip, pci);
if (ret < 0) {
dev_err(&pdev->dev, "Couldn't add gpiochip\n");
return ret;
}
/* Add pinctrl */
pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
if (IS_ERR(pci->pctl)) {
dev_err(&pdev->dev, "Couldn't add pinctrl\n");
return PTR_ERR(pci->pctl);
}
/* Add pin range */
ret = gpiochip_add_pin_range(&pci->gpio_chip, dev_name(&pdev->dev),
0, 0, pci->gpio_chip.ngpio);
if (ret < 0) {
dev_err(&pdev->dev, "Couldn't add gpiochip pin range\n");
return ret;
}
return 0;
}
static struct platform_driver rk805_pinctrl_driver = {
.probe = rk805_pinctrl_probe,
.driver = {
.name = "rk805-pinctrl",
},
};
module_platform_driver(rk805_pinctrl_driver);
MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
MODULE_AUTHOR("Xu Shengfei <[email protected]>");
MODULE_AUTHOR("Joseph Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-rk805.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device tree integration for the pin control subsystem
*
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
#include "core.h"
#include "devicetree.h"
/**
* struct pinctrl_dt_map - mapping table chunk parsed from device tree
* @node: list node for struct pinctrl's @dt_maps field
* @pctldev: the pin controller that allocated this struct, and will free it
* @map: the mapping table entries
* @num_maps: number of mapping table entries
*/
struct pinctrl_dt_map {
struct list_head node;
struct pinctrl_dev *pctldev;
struct pinctrl_map *map;
unsigned num_maps;
};
static void dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; ++i) {
kfree_const(map[i].dev_name);
map[i].dev_name = NULL;
}
if (pctldev) {
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
if (ops->dt_free_map)
ops->dt_free_map(pctldev, map, num_maps);
} else {
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
kfree(map);
}
}
void pinctrl_dt_free_maps(struct pinctrl *p)
{
struct pinctrl_dt_map *dt_map, *n1;
list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
pinctrl_unregister_mappings(dt_map->map);
list_del(&dt_map->node);
dt_free_map(dt_map->pctldev, dt_map->map,
dt_map->num_maps);
kfree(dt_map);
}
of_node_put(p->dev->of_node);
}
static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
struct pinctrl_dt_map *dt_map;
/* Initialize common mapping table entry fields */
for (i = 0; i < num_maps; i++) {
const char *devname;
devname = kstrdup_const(dev_name(p->dev), GFP_KERNEL);
if (!devname)
goto err_free_map;
map[i].dev_name = devname;
map[i].name = statename;
if (pctldev)
map[i].ctrl_dev_name = dev_name(pctldev->dev);
}
/* Remember the converted mapping table entries */
dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
if (!dt_map)
goto err_free_map;
dt_map->pctldev = pctldev;
dt_map->map = map;
dt_map->num_maps = num_maps;
list_add_tail(&dt_map->node, &p->dt_maps);
return pinctrl_register_mappings(map, num_maps);
err_free_map:
dt_free_map(pctldev, map, num_maps);
return -ENOMEM;
}
struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
{
return get_pinctrl_dev_from_of_node(np);
}
EXPORT_SYMBOL_GPL(of_pinctrl_get);
static int dt_to_map_one_config(struct pinctrl *p,
struct pinctrl_dev *hog_pctldev,
const char *statename,
struct device_node *np_config)
{
struct pinctrl_dev *pctldev = NULL;
struct device_node *np_pctldev;
const struct pinctrl_ops *ops;
int ret;
struct pinctrl_map *map;
unsigned num_maps;
bool allow_default = false;
/* Find the pin controller containing np_config */
np_pctldev = of_node_get(np_config);
for (;;) {
if (!allow_default)
allow_default = of_property_read_bool(np_pctldev,
"pinctrl-use-default");
np_pctldev = of_get_next_parent(np_pctldev);
if (!np_pctldev || of_node_is_root(np_pctldev)) {
of_node_put(np_pctldev);
ret = -ENODEV;
/* keep deferring if modules are enabled */
if (IS_ENABLED(CONFIG_MODULES) && !allow_default && ret < 0)
ret = -EPROBE_DEFER;
return ret;
}
/* If we're creating a hog we can use the passed pctldev */
if (hog_pctldev && (np_pctldev == p->dev->of_node)) {
pctldev = hog_pctldev;
break;
}
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
if (pctldev)
break;
/* Do not defer probing of hogs (circular loop) */
if (np_pctldev == p->dev->of_node) {
of_node_put(np_pctldev);
return -ENODEV;
}
}
of_node_put(np_pctldev);
/*
* Call pinctrl driver to parse device tree node, and
* generate mapping table entries
*/
ops = pctldev->desc->pctlops;
if (!ops->dt_node_to_map) {
dev_err(p->dev, "pctldev %s doesn't support DT\n",
dev_name(pctldev->dev));
return -ENODEV;
}
ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
if (ret < 0)
return ret;
else if (num_maps == 0) {
/*
* If we have no valid maps (maybe caused by empty pinctrl node
* or typing error) ther is no need remember this, so just
* return.
*/
dev_info(p->dev,
"there is not valid maps for state %s\n", statename);
return 0;
}
/* Stash the mapping table chunk away for later use */
return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
}
static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
{
struct pinctrl_map *map;
map = kzalloc(sizeof(*map), GFP_KERNEL);
if (!map)
return -ENOMEM;
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
map->type = PIN_MAP_TYPE_DUMMY_STATE;
return dt_remember_or_free_map(p, statename, NULL, map, 1);
}
int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
{
struct device_node *np = p->dev->of_node;
int state, ret;
char *propname;
struct property *prop;
const char *statename;
const __be32 *list;
int size, config;
phandle phandle;
struct device_node *np_config;
/* CONFIG_OF enabled, p->dev not instantiated from DT */
if (!np) {
if (of_have_populated_dt())
dev_dbg(p->dev,
"no of_node; not parsing pinctrl DT\n");
return 0;
}
/* We may store pointers to property names within the node */
of_node_get(np);
/* For each defined state ID */
for (state = 0; ; state++) {
/* Retrieve the pinctrl-* property */
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
if (!propname)
return -ENOMEM;
prop = of_find_property(np, propname, &size);
kfree(propname);
if (!prop) {
if (state == 0) {
of_node_put(np);
return -ENODEV;
}
break;
}
list = prop->value;
size /= sizeof(*list);
/* Determine whether pinctrl-names property names the state */
ret = of_property_read_string_index(np, "pinctrl-names",
state, &statename);
/*
* If not, statename is just the integer state ID. But rather
* than dynamically allocate it and have to free it later,
* just point part way into the property name for the string.
*/
if (ret < 0)
statename = prop->name + strlen("pinctrl-");
/* For every referenced pin configuration node in it */
for (config = 0; config < size; config++) {
phandle = be32_to_cpup(list++);
/* Look up the pin configuration node */
np_config = of_find_node_by_phandle(phandle);
if (!np_config) {
dev_err(p->dev,
"prop %s index %i invalid phandle\n",
prop->name, config);
ret = -EINVAL;
goto err;
}
/* Parse the node */
ret = dt_to_map_one_config(p, pctldev, statename,
np_config);
of_node_put(np_config);
if (ret < 0)
goto err;
}
/* No entries in DT? Generate a dummy state table entry */
if (!size) {
ret = dt_remember_dummy_state(p, statename);
if (ret < 0)
goto err;
}
}
return 0;
err:
pinctrl_dt_free_maps(p);
return ret;
}
/*
* For pinctrl binding, typically #pinctrl-cells is for the pin controller
* device, so either parent or grandparent. See pinctrl-bindings.txt.
*/
static int pinctrl_find_cells_size(const struct device_node *np)
{
const char *cells_name = "#pinctrl-cells";
int cells_size, error;
error = of_property_read_u32(np->parent, cells_name, &cells_size);
if (error) {
error = of_property_read_u32(np->parent->parent,
cells_name, &cells_size);
if (error)
return -ENOENT;
}
return cells_size;
}
/**
* pinctrl_get_list_and_count - Gets the list and it's cell size and number
* @np: pointer to device node with the property
* @list_name: property that contains the list
* @list: pointer for the list found
* @cells_size: pointer for the cell size found
* @nr_elements: pointer for the number of elements found
*
* Typically np is a single pinctrl entry containing the list.
*/
static int pinctrl_get_list_and_count(const struct device_node *np,
const char *list_name,
const __be32 **list,
int *cells_size,
int *nr_elements)
{
int size;
*cells_size = 0;
*nr_elements = 0;
*list = of_get_property(np, list_name, &size);
if (!*list)
return -ENOENT;
*cells_size = pinctrl_find_cells_size(np);
if (*cells_size < 0)
return -ENOENT;
/* First element is always the index within the pinctrl device */
*nr_elements = (size / sizeof(**list)) / (*cells_size + 1);
return 0;
}
/**
* pinctrl_count_index_with_args - Count number of elements in a pinctrl entry
* @np: pointer to device node with the property
* @list_name: property that contains the list
*
* Counts the number of elements in a pinctrl array consisting of an index
* within the controller and a number of u32 entries specified for each
* entry. Note that device_node is always for the parent pin controller device.
*/
int pinctrl_count_index_with_args(const struct device_node *np,
const char *list_name)
{
const __be32 *list;
int size, nr_cells, error;
error = pinctrl_get_list_and_count(np, list_name, &list,
&nr_cells, &size);
if (error)
return error;
return size;
}
EXPORT_SYMBOL_GPL(pinctrl_count_index_with_args);
/**
* pinctrl_copy_args - Populates of_phandle_args based on index
* @np: pointer to device node with the property
* @list: pointer to a list with the elements
* @index: entry within the list of elements
* @nr_cells: number of cells in the list
* @nr_elem: number of elements for each entry in the list
* @out_args: returned values
*
* Populates the of_phandle_args based on the index in the list.
*/
static int pinctrl_copy_args(const struct device_node *np,
const __be32 *list,
int index, int nr_cells, int nr_elem,
struct of_phandle_args *out_args)
{
int i;
memset(out_args, 0, sizeof(*out_args));
out_args->np = (struct device_node *)np;
out_args->args_count = nr_cells + 1;
if (index >= nr_elem)
return -EINVAL;
list += index * (nr_cells + 1);
for (i = 0; i < nr_cells + 1; i++)
out_args->args[i] = be32_to_cpup(list++);
return 0;
}
/**
* pinctrl_parse_index_with_args - Find a node pointed by index in a list
* @np: pointer to device node with the property
* @list_name: property that contains the list
* @index: index within the list
* @out_args: entries in the list pointed by index
*
* Finds the selected element in a pinctrl array consisting of an index
* within the controller and a number of u32 entries specified for each
* entry. Note that device_node is always for the parent pin controller device.
*/
int pinctrl_parse_index_with_args(const struct device_node *np,
const char *list_name, int index,
struct of_phandle_args *out_args)
{
const __be32 *list;
int nr_elem, nr_cells, error;
error = pinctrl_get_list_and_count(np, list_name, &list,
&nr_cells, &nr_elem);
if (error || !nr_cells)
return error;
error = pinctrl_copy_args(np, list, index, nr_cells, nr_elem,
out_args);
if (error)
return error;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_parse_index_with_args);
|
linux-master
|
drivers/pinctrl/devicetree.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for the pin config portions of the pin control subsystem
*
* Copyright (C) 2011 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <[email protected]>
*/
#define pr_fmt(fmt) "pinconfig core: " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include "core.h"
#include "pinconf.h"
int pinconf_check_ops(struct pinctrl_dev *pctldev)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
/* We have to be able to config the pins in SOME way */
if (!ops->pin_config_set && !ops->pin_config_group_set) {
dev_err(pctldev->dev,
"pinconf has to be able to set a pins config\n");
return -EINVAL;
}
return 0;
}
int pinconf_validate_map(const struct pinctrl_map *map, int i)
{
if (!map->data.configs.group_or_pin) {
pr_err("failed to register map %s (%d): no group/pin given\n",
map->name, i);
return -EINVAL;
}
if (!map->data.configs.num_configs ||
!map->data.configs.configs) {
pr_err("failed to register map %s (%d): no configs given\n",
map->name, i);
return -EINVAL;
}
return 0;
}
int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
if (!ops || !ops->pin_config_get) {
dev_dbg(pctldev->dev,
"cannot get pin configuration, .pin_config_get missing in driver\n");
return -ENOTSUPP;
}
return ops->pin_config_get(pctldev, pin, config);
}
int pin_config_group_get(const char *dev_name, const char *pin_group,
unsigned long *config)
{
struct pinctrl_dev *pctldev;
const struct pinconf_ops *ops;
int selector, ret;
pctldev = get_pinctrl_dev_from_devname(dev_name);
if (!pctldev) {
ret = -EINVAL;
return ret;
}
mutex_lock(&pctldev->mutex);
ops = pctldev->desc->confops;
if (!ops || !ops->pin_config_group_get) {
dev_dbg(pctldev->dev,
"cannot get configuration for pin group, missing group config get function in driver\n");
ret = -ENOTSUPP;
goto unlock;
}
selector = pinctrl_get_group_selector(pctldev, pin_group);
if (selector < 0) {
ret = selector;
goto unlock;
}
ret = ops->pin_config_group_get(pctldev, selector, config);
unlock:
mutex_unlock(&pctldev->mutex);
return ret;
}
int pinconf_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
int pin;
switch (setting->type) {
case PIN_MAP_TYPE_CONFIGS_PIN:
pin = pin_get_from_name(pctldev,
map->data.configs.group_or_pin);
if (pin < 0) {
dev_err(pctldev->dev, "could not map pin config for \"%s\"",
map->data.configs.group_or_pin);
return pin;
}
setting->data.configs.group_or_pin = pin;
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
pin = pinctrl_get_group_selector(pctldev,
map->data.configs.group_or_pin);
if (pin < 0) {
dev_err(pctldev->dev, "could not map group config for \"%s\"",
map->data.configs.group_or_pin);
return pin;
}
setting->data.configs.group_or_pin = pin;
break;
default:
return -EINVAL;
}
setting->data.configs.num_configs = map->data.configs.num_configs;
setting->data.configs.configs = map->data.configs.configs;
return 0;
}
void pinconf_free_setting(const struct pinctrl_setting *setting)
{
}
int pinconf_apply_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinconf_ops *ops = pctldev->desc->confops;
int ret;
if (!ops) {
dev_err(pctldev->dev, "missing confops\n");
return -EINVAL;
}
switch (setting->type) {
case PIN_MAP_TYPE_CONFIGS_PIN:
if (!ops->pin_config_set) {
dev_err(pctldev->dev, "missing pin_config_set op\n");
return -EINVAL;
}
ret = ops->pin_config_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs,
setting->data.configs.num_configs);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_set op failed for pin %d\n",
setting->data.configs.group_or_pin);
return ret;
}
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
if (!ops->pin_config_group_set) {
dev_err(pctldev->dev,
"missing pin_config_group_set op\n");
return -EINVAL;
}
ret = ops->pin_config_group_set(pctldev,
setting->data.configs.group_or_pin,
setting->data.configs.configs,
setting->data.configs.num_configs);
if (ret < 0) {
dev_err(pctldev->dev,
"pin_config_group_set op failed for group %d\n",
setting->data.configs.group_or_pin);
return ret;
}
break;
default:
return -EINVAL;
}
return 0;
}
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, size_t nconfigs)
{
const struct pinconf_ops *ops;
ops = pctldev->desc->confops;
if (!ops || !ops->pin_config_set)
return -ENOTSUPP;
return ops->pin_config_set(pctldev, pin, configs, nconfigs);
}
#ifdef CONFIG_DEBUG_FS
static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev,
unsigned long *configs, unsigned num_configs)
{
const struct pinconf_ops *confops;
int i;
if (pctldev)
confops = pctldev->desc->confops;
else
confops = NULL;
for (i = 0; i < num_configs; i++) {
seq_puts(s, "config ");
if (confops && confops->pin_config_config_dbg_show)
confops->pin_config_config_dbg_show(pctldev, s,
configs[i]);
else
seq_printf(s, "%08lx", configs[i]);
seq_putc(s, '\n');
}
}
void pinconf_show_map(struct seq_file *s, const struct pinctrl_map *map)
{
struct pinctrl_dev *pctldev;
pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
switch (map->type) {
case PIN_MAP_TYPE_CONFIGS_PIN:
seq_puts(s, "pin ");
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
seq_puts(s, "group ");
break;
default:
break;
}
seq_printf(s, "%s\n", map->data.configs.group_or_pin);
pinconf_show_config(s, pctldev, map->data.configs.configs,
map->data.configs.num_configs);
}
void pinconf_show_setting(struct seq_file *s,
const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
struct pin_desc *desc;
switch (setting->type) {
case PIN_MAP_TYPE_CONFIGS_PIN:
desc = pin_desc_get(setting->pctldev,
setting->data.configs.group_or_pin);
seq_printf(s, "pin %s (%d)", desc->name,
setting->data.configs.group_or_pin);
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
seq_printf(s, "group %s (%d)",
pctlops->get_group_name(pctldev,
setting->data.configs.group_or_pin),
setting->data.configs.group_or_pin);
break;
default:
break;
}
/*
* FIXME: We should really get the pin controller to dump the config
* values, so they can be decoded to something meaningful.
*/
pinconf_show_config(s, pctldev, setting->data.configs.configs,
setting->data.configs.num_configs);
}
static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
struct seq_file *s, int pin)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
/* no-op when not using generic pin config */
pinconf_generic_dump_pins(pctldev, s, NULL, pin);
if (ops && ops->pin_config_dbg_show)
ops->pin_config_dbg_show(pctldev, s, pin);
}
static int pinconf_pins_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
unsigned i, pin;
seq_puts(s, "Pin config settings per pin\n");
seq_puts(s, "Format: pin (name): configs\n");
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Skip if we cannot search the pin */
if (!desc)
continue;
seq_printf(s, "pin %d (%s): ", pin, desc->name);
pinconf_dump_pin(pctldev, s, pin);
seq_putc(s, '\n');
}
mutex_unlock(&pctldev->mutex);
return 0;
}
static void pinconf_dump_group(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned selector,
const char *gname)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
/* no-op when not using generic pin config */
pinconf_generic_dump_pins(pctldev, s, gname, 0);
if (ops && ops->pin_config_group_dbg_show)
ops->pin_config_group_dbg_show(pctldev, s, selector);
}
static int pinconf_groups_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
unsigned ngroups = pctlops->get_groups_count(pctldev);
unsigned selector = 0;
seq_puts(s, "Pin config settings per pin group\n");
seq_puts(s, "Format: group (name): configs\n");
while (selector < ngroups) {
const char *gname = pctlops->get_group_name(pctldev, selector);
seq_printf(s, "%u (%s): ", selector, gname);
pinconf_dump_group(pctldev, s, selector, gname);
seq_putc(s, '\n');
selector++;
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinconf_pins);
DEFINE_SHOW_ATTRIBUTE(pinconf_groups);
void pinconf_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinconf-pins", 0444,
devroot, pctldev, &pinconf_pins_fops);
debugfs_create_file("pinconf-groups", 0444,
devroot, pctldev, &pinconf_groups_fops);
}
#endif
|
linux-master
|
drivers/pinctrl/pinconf.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for the generic pin config portions of the pin control subsystem
*
* Copyright (C) 2011 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <[email protected]>
*/
#define pr_fmt(fmt) "generic pinconfig core: " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/of.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
"input bias pull to pin specific state", "ohms", true),
PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
};
static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
struct seq_file *s, const char *gname,
unsigned pin,
const struct pin_config_item *items,
int nitems, int *print_sep)
{
int i;
for (i = 0; i < nitems; i++) {
unsigned long config;
int ret;
/* We want to check out this parameter */
config = pinconf_to_config_packed(items[i].param, 0);
if (gname)
ret = pin_config_group_get(dev_name(pctldev->dev),
gname, &config);
else
ret = pin_config_get_for_pin(pctldev, pin, &config);
/* These are legal errors */
if (ret == -EINVAL || ret == -ENOTSUPP)
continue;
if (ret) {
seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
continue;
}
/* comma between multiple configs */
if (*print_sep)
seq_puts(s, ", ");
*print_sep = 1;
seq_puts(s, items[i].display);
/* Print unit if available */
if (items[i].has_arg) {
seq_printf(s, " (%u",
pinconf_to_config_argument(config));
if (items[i].format)
seq_printf(s, " %s)", items[i].format);
else
seq_puts(s, ")");
}
}
}
/**
* pinconf_generic_dump_pins - Print information about pin or group of pins
* @pctldev: Pincontrol device
* @s: File to print to
* @gname: Group name specifying pins
* @pin: Pin number specyfying pin
*
* Print the pinconf configuration for the requested pin(s) to @s. Pins can be
* specified either by pin using @pin or by group using @gname. Only one needs
* to be specified the other can be NULL/0.
*/
void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s,
const char *gname, unsigned pin)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
int print_sep = 0;
if (!ops->is_generic)
return;
/* generic parameters */
pinconf_generic_dump_one(pctldev, s, gname, pin, conf_items,
ARRAY_SIZE(conf_items), &print_sep);
/* driver-specific parameters */
if (pctldev->desc->num_custom_params &&
pctldev->desc->custom_conf_items)
pinconf_generic_dump_one(pctldev, s, gname, pin,
pctldev->desc->custom_conf_items,
pctldev->desc->num_custom_params,
&print_sep);
}
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned long config)
{
int i;
for (i = 0; i < ARRAY_SIZE(conf_items); i++) {
if (pinconf_to_config_param(config) != conf_items[i].param)
continue;
seq_printf(s, "%s: 0x%x", conf_items[i].display,
pinconf_to_config_argument(config));
}
if (!pctldev->desc->num_custom_params ||
!pctldev->desc->custom_conf_items)
return;
for (i = 0; i < pctldev->desc->num_custom_params; i++) {
if (pinconf_to_config_param(config) !=
pctldev->desc->custom_conf_items[i].param)
continue;
seq_printf(s, "%s: 0x%x",
pctldev->desc->custom_conf_items[i].display,
pinconf_to_config_argument(config));
}
}
EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
#endif
#ifdef CONFIG_OF
static const struct pinconf_generic_params dt_params[] = {
{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
{ "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
{ "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
{ "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 },
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ "low-power-disable", PIN_CONFIG_MODE_LOW_POWER, 0 },
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
{ "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
};
/**
* parse_dt_cfg() - Parse DT pinconf parameters
* @np: DT node
* @params: Array of describing generic parameters
* @count: Number of entries in @params
* @cfg: Array of parsed config options
* @ncfg: Number of entries in @cfg
*
* Parse the config options described in @params from @np and puts the result
* in @cfg. @cfg does not need to be empty, entries are added beginning at
* @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
* needs to have enough memory allocated to hold all possible entries.
*/
static void parse_dt_cfg(struct device_node *np,
const struct pinconf_generic_params *params,
unsigned int count, unsigned long *cfg,
unsigned int *ncfg)
{
int i;
for (i = 0; i < count; i++) {
u32 val;
int ret;
const struct pinconf_generic_params *par = ¶ms[i];
ret = of_property_read_u32(np, par->property, &val);
/* property not found */
if (ret == -EINVAL)
continue;
/* use default value, when no value is specified */
if (ret)
val = par->default_value;
pr_debug("found %s with value %u\n", par->property, val);
cfg[*ncfg] = pinconf_to_config_packed(par->param, val);
(*ncfg)++;
}
}
/**
* pinconf_generic_parse_dt_config()
* parse the config properties into generic pinconfig values.
* @np: node containing the pinconfig properties
* @pctldev: pincontrol device
* @configs: array with nconfigs entries containing the generic pinconf values
* must be freed when no longer necessary.
* @nconfigs: number of configurations
*/
int pinconf_generic_parse_dt_config(struct device_node *np,
struct pinctrl_dev *pctldev,
unsigned long **configs,
unsigned int *nconfigs)
{
unsigned long *cfg;
unsigned int max_cfg, ncfg = 0;
int ret;
if (!np)
return -EINVAL;
/* allocate a temporary array big enough to hold one of each option */
max_cfg = ARRAY_SIZE(dt_params);
if (pctldev)
max_cfg += pctldev->desc->num_custom_params;
cfg = kcalloc(max_cfg, sizeof(*cfg), GFP_KERNEL);
if (!cfg)
return -ENOMEM;
parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
if (pctldev && pctldev->desc->num_custom_params &&
pctldev->desc->custom_params)
parse_dt_cfg(np, pctldev->desc->custom_params,
pctldev->desc->num_custom_params, cfg, &ncfg);
ret = 0;
/* no configs found at all */
if (ncfg == 0) {
*configs = NULL;
*nconfigs = 0;
goto out;
}
/*
* Now limit the number of configs to the real number of
* found properties.
*/
*configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
if (!*configs) {
ret = -ENOMEM;
goto out;
}
*nconfigs = ncfg;
out:
kfree(cfg);
return ret;
}
EXPORT_SYMBOL_GPL(pinconf_generic_parse_dt_config);
int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np, struct pinctrl_map **map,
unsigned *reserved_maps, unsigned *num_maps,
enum pinctrl_map_type type)
{
int ret;
const char *function;
struct device *dev = pctldev->dev;
unsigned long *configs = NULL;
unsigned num_configs = 0;
unsigned reserve, strings_count;
struct property *prop;
const char *group;
const char *subnode_target_type = "pins";
ret = of_property_count_strings(np, "pins");
if (ret < 0) {
ret = of_property_count_strings(np, "groups");
if (ret < 0)
/* skip this node; may contain config child nodes */
return 0;
if (type == PIN_MAP_TYPE_INVALID)
type = PIN_MAP_TYPE_CONFIGS_GROUP;
subnode_target_type = "groups";
} else {
if (type == PIN_MAP_TYPE_INVALID)
type = PIN_MAP_TYPE_CONFIGS_PIN;
}
strings_count = ret;
ret = of_property_read_string(np, "function", &function);
if (ret < 0) {
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev, "%pOF: could not parse property function\n",
np);
function = NULL;
}
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(dev, "%pOF: could not parse node property\n", np);
return ret;
}
reserve = 0;
if (function != NULL)
reserve++;
if (num_configs)
reserve++;
reserve *= strings_count;
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, subnode_target_type, prop, group) {
if (function) {
ret = pinctrl_utils_add_map_mux(pctldev, map,
reserved_maps, num_maps, group,
function);
if (ret < 0)
goto exit;
}
if (num_configs) {
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group, configs,
num_configs, type);
if (ret < 0)
goto exit;
}
}
ret = 0;
exit:
kfree(configs);
return ret;
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_subnode_to_map);
int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config, struct pinctrl_map **map,
unsigned *num_maps, enum pinctrl_map_type type)
{
unsigned reserved_maps;
struct device_node *np;
int ret;
reserved_maps = 0;
*map = NULL;
*num_maps = 0;
ret = pinconf_generic_dt_subnode_to_map(pctldev, np_config, map,
&reserved_maps, num_maps, type);
if (ret < 0)
goto exit;
for_each_available_child_of_node(np_config, np) {
ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps, type);
if (ret < 0) {
of_node_put(np);
goto exit;
}
}
return 0;
exit:
pinctrl_utils_free_map(pctldev, *map, *num_maps);
return ret;
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map);
void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned num_maps)
{
pinctrl_utils_free_map(pctldev, map, num_maps);
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_free_map);
#endif
|
linux-master
|
drivers/pinctrl/pinconf-generic.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* ams AS3722 pin control and GPIO driver.
*
* Copyright (c) 2013, NVIDIA Corporation.
*
* Author: Laxman Dewangan <[email protected]>
*/
#include <linux/delay.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mfd/as3722.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#define AS3722_PIN_GPIO0 0
#define AS3722_PIN_GPIO1 1
#define AS3722_PIN_GPIO2 2
#define AS3722_PIN_GPIO3 3
#define AS3722_PIN_GPIO4 4
#define AS3722_PIN_GPIO5 5
#define AS3722_PIN_GPIO6 6
#define AS3722_PIN_GPIO7 7
#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
#define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
#define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
struct as3722_pin_function {
const char *name;
const char * const *groups;
unsigned ngroups;
int mux_option;
};
struct as3722_gpio_pin_control {
unsigned mode_prop;
int io_function;
};
struct as3722_pingroup {
const char *name;
const unsigned pins[1];
unsigned npins;
};
struct as3722_pctrl_info {
struct device *dev;
struct pinctrl_dev *pctl;
struct as3722 *as3722;
struct gpio_chip gpio_chip;
int pins_current_opt[AS3722_PIN_NUM];
const struct as3722_pin_function *functions;
unsigned num_functions;
const struct as3722_pingroup *pin_groups;
int num_pin_groups;
const struct pinctrl_pin_desc *pins;
unsigned num_pins;
struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
};
static const struct pinctrl_pin_desc as3722_pins_desc[] = {
PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
};
static const char * const gpio_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
};
enum as3722_pinmux_option {
AS3722_PINMUX_GPIO = 0,
AS3722_PINMUX_INTERRUPT_OUT = 1,
AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
AS3722_PINMUX_GPIO_INTERRUPT = 3,
AS3722_PINMUX_PWM_INPUT = 4,
AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
AS3722_PINMUX_OC_PG_SD0 = 6,
AS3722_PINMUX_PG_OUT = 7,
AS3722_PINMUX_CLK32K_OUT = 8,
AS3722_PINMUX_WATCHDOG_INPUT = 9,
AS3722_PINMUX_SOFT_RESET_IN = 11,
AS3722_PINMUX_PWM_OUTPUT = 12,
AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
AS3722_PINMUX_OC_PG_SD6 = 14,
};
#define FUNCTION_GROUP(fname, mux) \
{ \
.name = #fname, \
.groups = gpio_groups, \
.ngroups = ARRAY_SIZE(gpio_groups), \
.mux_option = AS3722_PINMUX_##mux, \
}
static const struct as3722_pin_function as3722_pin_function[] = {
FUNCTION_GROUP(gpio, GPIO),
FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
FUNCTION_GROUP(powergood-out, PG_OUT),
FUNCTION_GROUP(pwm-in, PWM_INPUT),
FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
};
#define AS3722_PINGROUP(pg_name, pin_id) \
{ \
.name = #pg_name, \
.pins = {AS3722_PIN_##pin_id}, \
.npins = 1, \
}
static const struct as3722_pingroup as3722_pingroups[] = {
AS3722_PINGROUP(gpio0, GPIO0),
AS3722_PINGROUP(gpio1, GPIO1),
AS3722_PINGROUP(gpio2, GPIO2),
AS3722_PINGROUP(gpio3, GPIO3),
AS3722_PINGROUP(gpio4, GPIO4),
AS3722_PINGROUP(gpio5, GPIO5),
AS3722_PINGROUP(gpio6, GPIO6),
AS3722_PINGROUP(gpio7, GPIO7),
};
static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
return as_pci->num_pin_groups;
}
static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
return as_pci->pin_groups[group].name;
}
static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins, unsigned *num_pins)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
*pins = as_pci->pin_groups[group].pins;
*num_pins = as_pci->pin_groups[group].npins;
return 0;
}
static const struct pinctrl_ops as3722_pinctrl_ops = {
.get_groups_count = as3722_pinctrl_get_groups_count,
.get_group_name = as3722_pinctrl_get_group_name,
.get_group_pins = as3722_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
return as_pci->num_functions;
}
static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned function)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
return as_pci->functions[function].name;
}
static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function, const char * const **groups,
unsigned * const num_groups)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
*groups = as_pci->functions[function].groups;
*num_groups = as_pci->functions[function].ngroups;
return 0;
}
static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
int ret;
dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
__func__, group, function, val);
ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
AS3722_GPIO_IOSF_MASK, val);
if (ret < 0) {
dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
group, ret);
return ret;
}
as_pci->gpio_control[group].io_function = function;
switch (val) {
case AS3722_GPIO_IOSF_SD0_OUT:
case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
case AS3722_GPIO_IOSF_Q32K_OUT:
case AS3722_GPIO_IOSF_PWM_OUT:
case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
if (ret < 0) {
dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
group, ret);
return ret;
}
as_pci->gpio_control[group].mode_prop =
AS3722_GPIO_MODE_OUTPUT_VDDH;
break;
default:
break;
}
return ret;
}
static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
{
if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
return -EINVAL;
if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
}
if (input) {
if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
return AS3722_GPIO_MODE_INPUT_PULL_UP;
else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
return AS3722_GPIO_MODE_INPUT;
}
if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
return AS3722_GPIO_MODE_OUTPUT_VDDL;
return AS3722_GPIO_MODE_OUTPUT_VDDH;
}
static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
if (as_pci->gpio_control[offset].io_function)
return -EBUSY;
return 0;
}
static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
struct as3722 *as3722 = as_pci->as3722;
int mode;
mode = as3722_pinctrl_gpio_get_mode(
as_pci->gpio_control[offset].mode_prop, input);
if (mode < 0) {
dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
(input) ? "Input" : "Output", offset);
return mode;
}
return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
AS3722_GPIO_MODE_MASK, mode);
}
static const struct pinmux_ops as3722_pinmux_ops = {
.get_functions_count = as3722_pinctrl_get_funcs_count,
.get_function_name = as3722_pinctrl_get_func_name,
.get_function_groups = as3722_pinctrl_get_func_groups,
.set_mux = as3722_pinctrl_set,
.gpio_request_enable = as3722_pinctrl_gpio_request_enable,
.gpio_set_direction = as3722_pinctrl_gpio_set_direction,
};
static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
int arg = 0;
u16 prop;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
prop = AS3722_GPIO_MODE_PULL_UP |
AS3722_GPIO_MODE_PULL_DOWN;
if (!(as_pci->gpio_control[pin].mode_prop & prop))
arg = 1;
prop = 0;
break;
case PIN_CONFIG_BIAS_PULL_UP:
prop = AS3722_GPIO_MODE_PULL_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
prop = AS3722_GPIO_MODE_PULL_DOWN;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
prop = AS3722_GPIO_MODE_OPEN_DRAIN;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
prop = AS3722_GPIO_MODE_HIGH_IMPED;
break;
default:
dev_err(as_pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
if (as_pci->gpio_control[pin].mode_prop & prop)
arg = 1;
*config = pinconf_to_config_packed(param, (u16)arg);
return 0;
}
static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
int mode_prop;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
mode_prop = as_pci->gpio_control[pin].mode_prop;
switch (param) {
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
break;
case PIN_CONFIG_BIAS_DISABLE:
mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
AS3722_GPIO_MODE_PULL_DOWN);
break;
case PIN_CONFIG_BIAS_PULL_UP:
mode_prop |= AS3722_GPIO_MODE_PULL_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
break;
default:
dev_err(as_pci->dev, "Properties not supported\n");
return -ENOTSUPP;
}
as_pci->gpio_control[pin].mode_prop = mode_prop;
}
return 0;
}
static const struct pinconf_ops as3722_pinconf_ops = {
.pin_config_get = as3722_pinconf_get,
.pin_config_set = as3722_pinconf_set,
};
static struct pinctrl_desc as3722_pinctrl_desc = {
.pctlops = &as3722_pinctrl_ops,
.pmxops = &as3722_pinmux_ops,
.confops = &as3722_pinconf_ops,
.owner = THIS_MODULE,
};
static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
struct as3722 *as3722 = as_pci->as3722;
int ret;
u32 reg;
u32 control;
u32 val;
int mode;
int invert_enable;
ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
if (ret < 0) {
dev_err(as_pci->dev,
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
return ret;
}
invert_enable = !!(control & AS3722_GPIO_INV);
mode = control & AS3722_GPIO_MODE_MASK;
switch (mode) {
case AS3722_GPIO_MODE_INPUT:
case AS3722_GPIO_MODE_INPUT_PULL_UP:
case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
reg = AS3722_GPIO_SIGNAL_IN_REG;
break;
case AS3722_GPIO_MODE_OUTPUT_VDDH:
case AS3722_GPIO_MODE_OUTPUT_VDDL:
reg = AS3722_GPIO_SIGNAL_OUT_REG;
break;
default:
return -EINVAL;
}
ret = as3722_read(as3722, reg, &val);
if (ret < 0) {
dev_err(as_pci->dev,
"GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
return ret;
}
val = !!(val & AS3722_GPIOn_SIGNAL(offset));
return (invert_enable) ? !val : val;
}
static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
int value)
{
struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
struct as3722 *as3722 = as_pci->as3722;
int en_invert;
u32 val;
int ret;
ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
if (ret < 0) {
dev_err(as_pci->dev,
"GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
return;
}
en_invert = !!(val & AS3722_GPIO_INV);
if (value)
val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
else
val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
AS3722_GPIOn_SIGNAL(offset), val);
if (ret < 0)
dev_err(as_pci->dev,
"GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
}
static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int as3722_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
as3722_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
return as3722_irq_get_virq(as_pci->as3722, offset);
}
static const struct gpio_chip as3722_gpio_chip = {
.label = "as3722-gpio",
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get = as3722_gpio_get,
.set = as3722_gpio_set,
.direction_input = as3722_gpio_direction_input,
.direction_output = as3722_gpio_direction_output,
.to_irq = as3722_gpio_to_irq,
.can_sleep = true,
.ngpio = AS3722_PIN_NUM,
.base = -1,
};
static int as3722_pinctrl_probe(struct platform_device *pdev)
{
struct as3722_pctrl_info *as_pci;
int ret;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
if (!as_pci)
return -ENOMEM;
as_pci->dev = &pdev->dev;
as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
platform_set_drvdata(pdev, as_pci);
as_pci->pins = as3722_pins_desc;
as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
as_pci->functions = as3722_pin_function;
as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
as_pci->pin_groups = as3722_pingroups;
as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
as3722_pinctrl_desc.name = dev_name(&pdev->dev);
as3722_pinctrl_desc.pins = as3722_pins_desc;
as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
as_pci);
if (IS_ERR(as_pci->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(as_pci->pctl);
}
as_pci->gpio_chip = as3722_gpio_chip;
as_pci->gpio_chip.parent = &pdev->dev;
ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
if (ret < 0) {
dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
return ret;
}
ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
0, 0, AS3722_PIN_NUM);
if (ret < 0) {
dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
goto fail_range_add;
}
return 0;
fail_range_add:
gpiochip_remove(&as_pci->gpio_chip);
return ret;
}
static int as3722_pinctrl_remove(struct platform_device *pdev)
{
struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
gpiochip_remove(&as_pci->gpio_chip);
return 0;
}
static const struct of_device_id as3722_pinctrl_of_match[] = {
{ .compatible = "ams,as3722-pinctrl", },
{ },
};
MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
static struct platform_driver as3722_pinctrl_driver = {
.driver = {
.name = "as3722-pinctrl",
.of_match_table = as3722_pinctrl_of_match,
},
.probe = as3722_pinctrl_probe,
.remove = as3722_pinctrl_remove,
};
module_platform_driver(as3722_pinctrl_driver);
MODULE_ALIAS("platform:as3722-pinctrl");
MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
MODULE_AUTHOR("Laxman Dewangan<[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-as3722.c
|
// SPDX-License-Identifier: GPL-2.0-only
/* MCP23S08 SPI/I2C GPIO driver */
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-mcp23s08.h"
/* Registers are all 8 bits wide.
*
* The mcp23s17 has twice as many bits, and can be configured to work
* with either 16 bit registers or with two adjacent 8 bit banks.
*/
#define MCP_IODIR 0x00 /* init/reset: all ones */
#define MCP_IPOL 0x01
#define MCP_GPINTEN 0x02
#define MCP_DEFVAL 0x03
#define MCP_INTCON 0x04
#define MCP_IOCON 0x05
# define IOCON_MIRROR (1 << 6)
# define IOCON_SEQOP (1 << 5)
# define IOCON_HAEN (1 << 3)
# define IOCON_ODR (1 << 2)
# define IOCON_INTPOL (1 << 1)
# define IOCON_INTCC (1)
#define MCP_GPPU 0x06
#define MCP_INTF 0x07
#define MCP_INTCAP 0x08
#define MCP_GPIO 0x09
#define MCP_OLAT 0x0a
static const struct reg_default mcp23x08_defaults[] = {
{.reg = MCP_IODIR, .def = 0xff},
{.reg = MCP_IPOL, .def = 0x00},
{.reg = MCP_GPINTEN, .def = 0x00},
{.reg = MCP_DEFVAL, .def = 0x00},
{.reg = MCP_INTCON, .def = 0x00},
{.reg = MCP_IOCON, .def = 0x00},
{.reg = MCP_GPPU, .def = 0x00},
{.reg = MCP_OLAT, .def = 0x00},
};
static const struct regmap_range mcp23x08_volatile_range = {
.range_min = MCP_INTF,
.range_max = MCP_GPIO,
};
static const struct regmap_access_table mcp23x08_volatile_table = {
.yes_ranges = &mcp23x08_volatile_range,
.n_yes_ranges = 1,
};
static const struct regmap_range mcp23x08_precious_range = {
.range_min = MCP_GPIO,
.range_max = MCP_GPIO,
};
static const struct regmap_access_table mcp23x08_precious_table = {
.yes_ranges = &mcp23x08_precious_range,
.n_yes_ranges = 1,
};
const struct regmap_config mcp23x08_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_stride = 1,
.volatile_table = &mcp23x08_volatile_table,
.precious_table = &mcp23x08_precious_table,
.reg_defaults = mcp23x08_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
.cache_type = REGCACHE_FLAT,
.max_register = MCP_OLAT,
};
EXPORT_SYMBOL_GPL(mcp23x08_regmap);
static const struct reg_default mcp23x17_defaults[] = {
{.reg = MCP_IODIR << 1, .def = 0xffff},
{.reg = MCP_IPOL << 1, .def = 0x0000},
{.reg = MCP_GPINTEN << 1, .def = 0x0000},
{.reg = MCP_DEFVAL << 1, .def = 0x0000},
{.reg = MCP_INTCON << 1, .def = 0x0000},
{.reg = MCP_IOCON << 1, .def = 0x0000},
{.reg = MCP_GPPU << 1, .def = 0x0000},
{.reg = MCP_OLAT << 1, .def = 0x0000},
};
static const struct regmap_range mcp23x17_volatile_range = {
.range_min = MCP_INTF << 1,
.range_max = MCP_GPIO << 1,
};
static const struct regmap_access_table mcp23x17_volatile_table = {
.yes_ranges = &mcp23x17_volatile_range,
.n_yes_ranges = 1,
};
static const struct regmap_range mcp23x17_precious_range = {
.range_min = MCP_INTCAP << 1,
.range_max = MCP_GPIO << 1,
};
static const struct regmap_access_table mcp23x17_precious_table = {
.yes_ranges = &mcp23x17_precious_range,
.n_yes_ranges = 1,
};
const struct regmap_config mcp23x17_regmap = {
.reg_bits = 8,
.val_bits = 16,
.reg_stride = 2,
.max_register = MCP_OLAT << 1,
.volatile_table = &mcp23x17_volatile_table,
.precious_table = &mcp23x17_precious_table,
.reg_defaults = mcp23x17_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
.cache_type = REGCACHE_FLAT,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
EXPORT_SYMBOL_GPL(mcp23x17_regmap);
static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
{
return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
}
static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
{
return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
}
static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
unsigned int mask, unsigned int val)
{
return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
mask, val);
}
static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
unsigned int pin, bool enabled)
{
u16 mask = BIT(pin);
return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
}
static const struct pinctrl_pin_desc mcp23x08_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
};
static const struct pinctrl_pin_desc mcp23x17_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
};
static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return 0;
}
static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return NULL;
}
static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
return -ENOTSUPP;
}
static const struct pinctrl_ops mcp_pinctrl_ops = {
.get_groups_count = mcp_pinctrl_get_groups_count,
.get_group_name = mcp_pinctrl_get_group_name,
.get_group_pins = mcp_pinctrl_get_group_pins,
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
#endif
};
static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int data, status;
int ret;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
ret = mcp_read(mcp, MCP_GPPU, &data);
if (ret < 0)
return ret;
status = (data & BIT(pin)) ? 1 : 0;
break;
default:
return -ENOTSUPP;
}
*config = 0;
return status ? 0 : -EINVAL;
}
static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 arg;
int ret = 0;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
break;
default:
dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
}
return ret;
}
static const struct pinconf_ops mcp_pinconf_ops = {
.pin_config_get = mcp_pinconf_get,
.pin_config_set = mcp_pinconf_set,
.is_generic = true,
};
/*----------------------------------------------------------------------*/
static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
int status;
mutex_lock(&mcp->lock);
status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
mutex_unlock(&mcp->lock);
return status;
}
static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
int status, ret;
mutex_lock(&mcp->lock);
/* REVISIT reading this clears any IRQ ... */
ret = mcp_read(mcp, MCP_GPIO, &status);
if (ret < 0)
status = 0;
else {
mcp->cached_gpio = status;
status = !!(status & (1 << offset));
}
mutex_unlock(&mcp->lock);
return status;
}
static int mcp23s08_get_multiple(struct gpio_chip *chip,
unsigned long *mask, unsigned long *bits)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
unsigned int status;
int ret;
mutex_lock(&mcp->lock);
/* REVISIT reading this clears any IRQ ... */
ret = mcp_read(mcp, MCP_GPIO, &status);
if (ret < 0)
status = 0;
else {
mcp->cached_gpio = status;
*bits = status;
}
mutex_unlock(&mcp->lock);
return ret;
}
static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
{
return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
}
static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
unsigned mask = BIT(offset);
mutex_lock(&mcp->lock);
__mcp23s08_set(mcp, mask, !!value);
mutex_unlock(&mcp->lock);
}
static void mcp23s08_set_multiple(struct gpio_chip *chip,
unsigned long *mask, unsigned long *bits)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
mutex_lock(&mcp->lock);
mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
mutex_unlock(&mcp->lock);
}
static int
mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
{
struct mcp23s08 *mcp = gpiochip_get_data(chip);
unsigned mask = BIT(offset);
int status;
mutex_lock(&mcp->lock);
status = __mcp23s08_set(mcp, mask, value);
if (status == 0) {
status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
}
mutex_unlock(&mcp->lock);
return status;
}
/*----------------------------------------------------------------------*/
static irqreturn_t mcp23s08_irq(int irq, void *data)
{
struct mcp23s08 *mcp = data;
int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
unsigned int child_irq;
bool intf_set, intcap_changed, gpio_bit_changed,
defval_changed, gpio_set;
mutex_lock(&mcp->lock);
if (mcp_read(mcp, MCP_INTF, &intf))
goto unlock;
if (intf == 0) {
/* There is no interrupt pending */
goto unlock;
}
if (mcp_read(mcp, MCP_INTCAP, &intcap))
goto unlock;
if (mcp_read(mcp, MCP_INTCON, &intcon))
goto unlock;
if (mcp_read(mcp, MCP_DEFVAL, &defval))
goto unlock;
/* This clears the interrupt(configurable on S18) */
if (mcp_read(mcp, MCP_GPIO, &gpio))
goto unlock;
gpio_orig = mcp->cached_gpio;
mcp->cached_gpio = gpio;
mutex_unlock(&mcp->lock);
dev_dbg(mcp->chip.parent,
"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
intcap, intf, gpio_orig, gpio);
for (i = 0; i < mcp->chip.ngpio; i++) {
/* We must check all of the inputs on the chip,
* otherwise we may not notice a change on >=2 pins.
*
* On at least the mcp23s17, INTCAP is only updated
* one byte at a time(INTCAPA and INTCAPB are
* not written to at the same time - only on a per-bank
* basis).
*
* INTF only contains the single bit that caused the
* interrupt per-bank. On the mcp23s17, there is
* INTFA and INTFB. If two pins are changed on the A
* side at the same time, INTF will only have one bit
* set. If one pin on the A side and one pin on the B
* side are changed at the same time, INTF will have
* two bits set. Thus, INTF can't be the only check
* to see if the input has changed.
*/
intf_set = intf & BIT(i);
if (i < 8 && intf_set)
intcap_mask = 0x00FF;
else if (i >= 8 && intf_set)
intcap_mask = 0xFF00;
else
intcap_mask = 0x00;
intcap_changed = (intcap_mask &
(intcap & BIT(i))) !=
(intcap_mask & (BIT(i) & gpio_orig));
gpio_set = BIT(i) & gpio;
gpio_bit_changed = (BIT(i) & gpio_orig) !=
(BIT(i) & gpio);
defval_changed = (BIT(i) & intcon) &&
((BIT(i) & gpio) !=
(BIT(i) & defval));
if (((gpio_bit_changed || intcap_changed) &&
(BIT(i) & mcp->irq_rise) && gpio_set) ||
((gpio_bit_changed || intcap_changed) &&
(BIT(i) & mcp->irq_fall) && !gpio_set) ||
defval_changed) {
child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
handle_nested_irq(child_irq);
}
}
return IRQ_HANDLED;
unlock:
mutex_unlock(&mcp->lock);
return IRQ_HANDLED;
}
static void mcp23s08_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
unsigned int pos = irqd_to_hwirq(data);
mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
gpiochip_disable_irq(gc, pos);
}
static void mcp23s08_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
unsigned int pos = irqd_to_hwirq(data);
gpiochip_enable_irq(gc, pos);
mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
}
static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
unsigned int pos = irqd_to_hwirq(data);
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
mcp_set_bit(mcp, MCP_INTCON, pos, false);
mcp->irq_rise |= BIT(pos);
mcp->irq_fall |= BIT(pos);
} else if (type & IRQ_TYPE_EDGE_RISING) {
mcp_set_bit(mcp, MCP_INTCON, pos, false);
mcp->irq_rise |= BIT(pos);
mcp->irq_fall &= ~BIT(pos);
} else if (type & IRQ_TYPE_EDGE_FALLING) {
mcp_set_bit(mcp, MCP_INTCON, pos, false);
mcp->irq_rise &= ~BIT(pos);
mcp->irq_fall |= BIT(pos);
} else if (type & IRQ_TYPE_LEVEL_HIGH) {
mcp_set_bit(mcp, MCP_INTCON, pos, true);
mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
} else if (type & IRQ_TYPE_LEVEL_LOW) {
mcp_set_bit(mcp, MCP_INTCON, pos, true);
mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
} else
return -EINVAL;
return 0;
}
static void mcp23s08_irq_bus_lock(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
mutex_lock(&mcp->lock);
regcache_cache_only(mcp->regmap, true);
}
static void mcp23s08_irq_bus_unlock(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
regcache_cache_only(mcp->regmap, false);
regcache_sync(mcp->regmap);
mutex_unlock(&mcp->lock);
}
static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
{
struct gpio_chip *chip = &mcp->chip;
int err;
unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
if (mcp->irq_active_high)
irqflags |= IRQF_TRIGGER_HIGH;
else
irqflags |= IRQF_TRIGGER_LOW;
err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
mcp23s08_irq,
irqflags, dev_name(chip->parent), mcp);
if (err != 0) {
dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
mcp->irq, err);
return err;
}
return 0;
}
static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mcp23s08 *mcp = gpiochip_get_data(gc);
seq_printf(p, dev_name(mcp->dev));
}
static const struct irq_chip mcp23s08_irq_chip = {
.irq_mask = mcp23s08_irq_mask,
.irq_unmask = mcp23s08_irq_unmask,
.irq_set_type = mcp23s08_irq_set_type,
.irq_bus_lock = mcp23s08_irq_bus_lock,
.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
.irq_print_chip = mcp23s08_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/*----------------------------------------------------------------------*/
int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
unsigned int addr, unsigned int type, unsigned int base)
{
int status, ret;
bool mirror = false;
bool open_drain = false;
mutex_init(&mcp->lock);
mcp->dev = dev;
mcp->addr = addr;
mcp->irq_active_high = false;
mcp->chip.direction_input = mcp23s08_direction_input;
mcp->chip.get = mcp23s08_get;
mcp->chip.get_multiple = mcp23s08_get_multiple;
mcp->chip.direction_output = mcp23s08_direction_output;
mcp->chip.set = mcp23s08_set;
mcp->chip.set_multiple = mcp23s08_set_multiple;
mcp->chip.base = base;
mcp->chip.can_sleep = true;
mcp->chip.parent = dev;
mcp->chip.owner = THIS_MODULE;
mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
* and MCP_IOCON.HAEN = 1, so we work with all chips.
*/
ret = mcp_read(mcp, MCP_IOCON, &status);
if (ret < 0)
return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
mcp->irq_controller =
device_property_read_bool(dev, "interrupt-controller");
if (mcp->irq && mcp->irq_controller) {
mcp->irq_active_high =
device_property_read_bool(dev,
"microchip,irq-active-high");
mirror = device_property_read_bool(dev, "microchip,irq-mirror");
open_drain = device_property_read_bool(dev, "drive-open-drain");
}
if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
mcp->irq_active_high || open_drain) {
/* mcp23s17 has IOCON twice, make sure they are in sync */
status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
status |= IOCON_HAEN | (IOCON_HAEN << 8);
if (mcp->irq_active_high)
status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
else
status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
if (mirror)
status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
if (open_drain)
status |= IOCON_ODR | (IOCON_ODR << 8);
if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
status |= IOCON_INTCC | (IOCON_INTCC << 8);
ret = mcp_write(mcp, MCP_IOCON, status);
if (ret < 0)
return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
}
if (mcp->irq && mcp->irq_controller) {
struct gpio_irq_chip *girq = &mcp->chip.irq;
gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
}
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
if (ret < 0)
return dev_err_probe(dev, ret, "can't add GPIO chip\n");
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
mcp->pinctrl_desc.npins = mcp->chip.ngpio;
if (mcp->pinctrl_desc.npins == 8)
mcp->pinctrl_desc.pins = mcp23x08_pins;
else if (mcp->pinctrl_desc.npins == 16)
mcp->pinctrl_desc.pins = mcp23x17_pins;
mcp->pinctrl_desc.owner = THIS_MODULE;
mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
if (IS_ERR(mcp->pctldev))
return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
if (mcp->irq) {
ret = mcp23s08_irq_setup(mcp);
if (ret)
return dev_err_probe(dev, ret, "can't setup IRQ\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-mcp23s08.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pistachio SoC pinctrl driver
*
* Copyright (C) 2014 Imagination Technologies Ltd.
* Copyright (C) 2014 Google, Inc.
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/mod_devicetable.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include "pinctrl-utils.h"
#define PADS_SCHMITT_EN0 0x000
#define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
#define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
#define PADS_PU_PD0 0x040
#define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
#define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
#define PADS_PU_PD_MASK 0x3
#define PADS_PU_PD_HIGHZ 0x0
#define PADS_PU_PD_UP 0x1
#define PADS_PU_PD_DOWN 0x2
#define PADS_PU_PD_BUS 0x3
#define PADS_FUNCTION_SELECT0 0x0c0
#define PADS_FUNCTION_SELECT1 0x0c4
#define PADS_FUNCTION_SELECT2 0x0c8
#define PADS_SCENARIO_SELECT 0x0f8
#define PADS_SLEW_RATE0 0x100
#define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
#define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
#define PADS_DRIVE_STRENGTH0 0x120
#define PADS_DRIVE_STRENGTH_REG(pin) \
(PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
#define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
#define PADS_DRIVE_STRENGTH_MASK 0x3
#define PADS_DRIVE_STRENGTH_2MA 0x0
#define PADS_DRIVE_STRENGTH_4MA 0x1
#define PADS_DRIVE_STRENGTH_8MA 0x2
#define PADS_DRIVE_STRENGTH_12MA 0x3
#define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
#define GPIO_BIT_EN 0x00
#define GPIO_OUTPUT_EN 0x04
#define GPIO_OUTPUT 0x08
#define GPIO_INPUT 0x0c
#define GPIO_INPUT_POLARITY 0x10
#define GPIO_INTERRUPT_TYPE 0x14
#define GPIO_INTERRUPT_TYPE_LEVEL 0x0
#define GPIO_INTERRUPT_TYPE_EDGE 0x1
#define GPIO_INTERRUPT_EDGE 0x18
#define GPIO_INTERRUPT_EDGE_SINGLE 0x0
#define GPIO_INTERRUPT_EDGE_DUAL 0x1
#define GPIO_INTERRUPT_EN 0x1c
#define GPIO_INTERRUPT_STATUS 0x20
struct pistachio_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
const int *scenarios;
unsigned int nscenarios;
unsigned int scenario_reg;
unsigned int scenario_shift;
unsigned int scenario_mask;
};
struct pistachio_pin_group {
const char *name;
unsigned int pin;
int mux_option[3];
int mux_reg;
int mux_shift;
int mux_mask;
};
struct pistachio_gpio_bank {
struct pistachio_pinctrl *pctl;
void __iomem *base;
int instance;
unsigned int pin_base;
unsigned int npins;
struct gpio_chip gpio_chip;
};
struct pistachio_pinctrl {
struct device *dev;
void __iomem *base;
struct pinctrl_dev *pctldev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
const struct pistachio_function *functions;
unsigned int nfunctions;
const struct pistachio_pin_group *groups;
unsigned int ngroups;
struct pistachio_gpio_bank *gpio_banks;
unsigned int nbanks;
};
#define PISTACHIO_PIN_MFIO(p) (p)
#define PISTACHIO_PIN_TCK 90
#define PISTACHIO_PIN_TRSTN 91
#define PISTACHIO_PIN_TDI 92
#define PISTACHIO_PIN_TMS 93
#define PISTACHIO_PIN_TDO 94
#define PISTACHIO_PIN_JTAG_COMPLY 95
#define PISTACHIO_PIN_SAFE_MODE 96
#define PISTACHIO_PIN_POR_DISABLE 97
#define PISTACHIO_PIN_RESETN 98
#define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
static const struct pinctrl_pin_desc pistachio_pins[] = {
MFIO_PIN_DESC(0),
MFIO_PIN_DESC(1),
MFIO_PIN_DESC(2),
MFIO_PIN_DESC(3),
MFIO_PIN_DESC(4),
MFIO_PIN_DESC(5),
MFIO_PIN_DESC(6),
MFIO_PIN_DESC(7),
MFIO_PIN_DESC(8),
MFIO_PIN_DESC(9),
MFIO_PIN_DESC(10),
MFIO_PIN_DESC(11),
MFIO_PIN_DESC(12),
MFIO_PIN_DESC(13),
MFIO_PIN_DESC(14),
MFIO_PIN_DESC(15),
MFIO_PIN_DESC(16),
MFIO_PIN_DESC(17),
MFIO_PIN_DESC(18),
MFIO_PIN_DESC(19),
MFIO_PIN_DESC(20),
MFIO_PIN_DESC(21),
MFIO_PIN_DESC(22),
MFIO_PIN_DESC(23),
MFIO_PIN_DESC(24),
MFIO_PIN_DESC(25),
MFIO_PIN_DESC(26),
MFIO_PIN_DESC(27),
MFIO_PIN_DESC(28),
MFIO_PIN_DESC(29),
MFIO_PIN_DESC(30),
MFIO_PIN_DESC(31),
MFIO_PIN_DESC(32),
MFIO_PIN_DESC(33),
MFIO_PIN_DESC(34),
MFIO_PIN_DESC(35),
MFIO_PIN_DESC(36),
MFIO_PIN_DESC(37),
MFIO_PIN_DESC(38),
MFIO_PIN_DESC(39),
MFIO_PIN_DESC(40),
MFIO_PIN_DESC(41),
MFIO_PIN_DESC(42),
MFIO_PIN_DESC(43),
MFIO_PIN_DESC(44),
MFIO_PIN_DESC(45),
MFIO_PIN_DESC(46),
MFIO_PIN_DESC(47),
MFIO_PIN_DESC(48),
MFIO_PIN_DESC(49),
MFIO_PIN_DESC(50),
MFIO_PIN_DESC(51),
MFIO_PIN_DESC(52),
MFIO_PIN_DESC(53),
MFIO_PIN_DESC(54),
MFIO_PIN_DESC(55),
MFIO_PIN_DESC(56),
MFIO_PIN_DESC(57),
MFIO_PIN_DESC(58),
MFIO_PIN_DESC(59),
MFIO_PIN_DESC(60),
MFIO_PIN_DESC(61),
MFIO_PIN_DESC(62),
MFIO_PIN_DESC(63),
MFIO_PIN_DESC(64),
MFIO_PIN_DESC(65),
MFIO_PIN_DESC(66),
MFIO_PIN_DESC(67),
MFIO_PIN_DESC(68),
MFIO_PIN_DESC(69),
MFIO_PIN_DESC(70),
MFIO_PIN_DESC(71),
MFIO_PIN_DESC(72),
MFIO_PIN_DESC(73),
MFIO_PIN_DESC(74),
MFIO_PIN_DESC(75),
MFIO_PIN_DESC(76),
MFIO_PIN_DESC(77),
MFIO_PIN_DESC(78),
MFIO_PIN_DESC(79),
MFIO_PIN_DESC(80),
MFIO_PIN_DESC(81),
MFIO_PIN_DESC(82),
MFIO_PIN_DESC(83),
MFIO_PIN_DESC(84),
MFIO_PIN_DESC(85),
MFIO_PIN_DESC(86),
MFIO_PIN_DESC(87),
MFIO_PIN_DESC(88),
MFIO_PIN_DESC(89),
PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
};
static const char * const pistachio_spim0_groups[] = {
"mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
"mfio30", "mfio55", "mfio56", "mfio57",
};
static const char * const pistachio_spim1_groups[] = {
"mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
"mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
};
static const char * const pistachio_spis_groups[] = {
"mfio11", "mfio12", "mfio13", "mfio14",
};
static const char *const pistachio_sdhost_groups[] = {
"mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
"mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
"mfio27",
};
static const char * const pistachio_i2c0_groups[] = {
"mfio28", "mfio29",
};
static const char * const pistachio_i2c1_groups[] = {
"mfio30", "mfio31",
};
static const char * const pistachio_i2c2_groups[] = {
"mfio32", "mfio33",
};
static const char * const pistachio_i2c3_groups[] = {
"mfio34", "mfio35",
};
static const char * const pistachio_audio_clk_in_groups[] = {
"mfio36",
};
static const char * const pistachio_i2s_out_groups[] = {
"mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
"mfio42", "mfio43", "mfio44",
};
static const char * const pistachio_debug_raw_cca_ind_groups[] = {
"mfio37",
};
static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
"mfio38",
};
static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
"mfio39",
};
static const char * const pistachio_debug_agc_done_0_groups[] = {
"mfio40",
};
static const char * const pistachio_debug_agc_done_1_groups[] = {
"mfio41",
};
static const char * const pistachio_debug_ed_cca_ind_groups[] = {
"mfio42",
};
static const char * const pistachio_debug_s2l_done_groups[] = {
"mfio43",
};
static const char * const pistachio_i2s_dac_clk_groups[] = {
"mfio45",
};
static const char * const pistachio_audio_sync_groups[] = {
"mfio45",
};
static const char * const pistachio_audio_trigger_groups[] = {
"mfio46",
};
static const char * const pistachio_i2s_in_groups[] = {
"mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
"mfio53", "mfio54",
};
static const char * const pistachio_uart0_groups[] = {
"mfio55", "mfio56", "mfio57", "mfio58",
};
static const char * const pistachio_uart1_groups[] = {
"mfio59", "mfio60", "mfio1", "mfio2",
};
static const char * const pistachio_spdif_out_groups[] = {
"mfio61",
};
static const char * const pistachio_spdif_in_groups[] = {
"mfio62", "mfio54",
};
static const int pistachio_spdif_in_scenarios[] = {
PISTACHIO_PIN_MFIO(62),
PISTACHIO_PIN_MFIO(54),
};
static const char * const pistachio_eth_groups[] = {
"mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
"mfio69", "mfio70", "mfio71",
};
static const char * const pistachio_ir_groups[] = {
"mfio72",
};
static const char * const pistachio_pwmpdm_groups[] = {
"mfio73", "mfio74", "mfio75", "mfio76",
};
static const char * const pistachio_mips_trace_clk_groups[] = {
"mfio15", "mfio63", "mfio73",
};
static const char * const pistachio_mips_trace_dint_groups[] = {
"mfio16", "mfio64", "mfio74",
};
static const int pistachio_mips_trace_dint_scenarios[] = {
PISTACHIO_PIN_MFIO(16),
PISTACHIO_PIN_MFIO(64),
PISTACHIO_PIN_MFIO(74),
};
static const char * const pistachio_mips_trace_trigout_groups[] = {
"mfio17", "mfio65", "mfio75",
};
static const char * const pistachio_mips_trace_trigin_groups[] = {
"mfio18", "mfio66", "mfio76",
};
static const int pistachio_mips_trace_trigin_scenarios[] = {
PISTACHIO_PIN_MFIO(18),
PISTACHIO_PIN_MFIO(66),
PISTACHIO_PIN_MFIO(76),
};
static const char * const pistachio_mips_trace_dm_groups[] = {
"mfio19", "mfio67", "mfio77",
};
static const char * const pistachio_mips_probe_n_groups[] = {
"mfio20", "mfio68", "mfio78",
};
static const int pistachio_mips_probe_n_scenarios[] = {
PISTACHIO_PIN_MFIO(20),
PISTACHIO_PIN_MFIO(68),
PISTACHIO_PIN_MFIO(78),
};
static const char * const pistachio_mips_trace_data_groups[] = {
"mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
"mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
"mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
"mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
};
static const char * const pistachio_sram_debug_groups[] = {
"mfio73", "mfio74",
};
static const char * const pistachio_rom_debug_groups[] = {
"mfio75", "mfio76",
};
static const char * const pistachio_rpu_debug_groups[] = {
"mfio77", "mfio78",
};
static const char * const pistachio_mips_debug_groups[] = {
"mfio79", "mfio80",
};
static const char * const pistachio_eth_debug_groups[] = {
"mfio81", "mfio82",
};
static const char * const pistachio_usb_debug_groups[] = {
"mfio83", "mfio84",
};
static const char * const pistachio_sdhost_debug_groups[] = {
"mfio85", "mfio86",
};
static const char * const pistachio_socif_debug_groups[] = {
"mfio87", "mfio88",
};
static const char * const pistachio_mdc_debug_groups[] = {
"mfio77", "mfio78",
};
static const char * const pistachio_ddr_debug_groups[] = {
"mfio79", "mfio80",
};
static const char * const pistachio_dreq0_groups[] = {
"mfio81",
};
static const char * const pistachio_dreq1_groups[] = {
"mfio82",
};
static const char * const pistachio_dreq2_groups[] = {
"mfio87",
};
static const char * const pistachio_dreq3_groups[] = {
"mfio88",
};
static const char * const pistachio_dreq4_groups[] = {
"mfio89",
};
static const char * const pistachio_dreq5_groups[] = {
"mfio89",
};
static const char * const pistachio_mips_pll_lock_groups[] = {
"mfio83",
};
static const char * const pistachio_audio_pll_lock_groups[] = {
"mfio84",
};
static const char * const pistachio_rpu_v_pll_lock_groups[] = {
"mfio85",
};
static const char * const pistachio_rpu_l_pll_lock_groups[] = {
"mfio86",
};
static const char * const pistachio_sys_pll_lock_groups[] = {
"mfio87",
};
static const char * const pistachio_wifi_pll_lock_groups[] = {
"mfio88",
};
static const char * const pistachio_bt_pll_lock_groups[] = {
"mfio89",
};
#define FUNCTION(_name) \
{ \
.name = #_name, \
.groups = pistachio_##_name##_groups, \
.ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
}
#define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \
{ \
.name = #_name, \
.groups = pistachio_##_name##_groups, \
.ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
.scenarios = pistachio_##_name##_scenarios, \
.nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
.scenario_reg = _reg, \
.scenario_shift = _shift, \
.scenario_mask = _mask, \
}
enum pistachio_mux_option {
PISTACHIO_FUNCTION_NONE = -1,
PISTACHIO_FUNCTION_SPIM0,
PISTACHIO_FUNCTION_SPIM1,
PISTACHIO_FUNCTION_SPIS,
PISTACHIO_FUNCTION_SDHOST,
PISTACHIO_FUNCTION_I2C0,
PISTACHIO_FUNCTION_I2C1,
PISTACHIO_FUNCTION_I2C2,
PISTACHIO_FUNCTION_I2C3,
PISTACHIO_FUNCTION_AUDIO_CLK_IN,
PISTACHIO_FUNCTION_I2S_OUT,
PISTACHIO_FUNCTION_I2S_DAC_CLK,
PISTACHIO_FUNCTION_AUDIO_SYNC,
PISTACHIO_FUNCTION_AUDIO_TRIGGER,
PISTACHIO_FUNCTION_I2S_IN,
PISTACHIO_FUNCTION_UART0,
PISTACHIO_FUNCTION_UART1,
PISTACHIO_FUNCTION_SPDIF_OUT,
PISTACHIO_FUNCTION_SPDIF_IN,
PISTACHIO_FUNCTION_ETH,
PISTACHIO_FUNCTION_IR,
PISTACHIO_FUNCTION_PWMPDM,
PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
PISTACHIO_FUNCTION_MIPS_TRACE_DM,
PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
PISTACHIO_FUNCTION_SRAM_DEBUG,
PISTACHIO_FUNCTION_ROM_DEBUG,
PISTACHIO_FUNCTION_RPU_DEBUG,
PISTACHIO_FUNCTION_MIPS_DEBUG,
PISTACHIO_FUNCTION_ETH_DEBUG,
PISTACHIO_FUNCTION_USB_DEBUG,
PISTACHIO_FUNCTION_SDHOST_DEBUG,
PISTACHIO_FUNCTION_SOCIF_DEBUG,
PISTACHIO_FUNCTION_MDC_DEBUG,
PISTACHIO_FUNCTION_DDR_DEBUG,
PISTACHIO_FUNCTION_DREQ0,
PISTACHIO_FUNCTION_DREQ1,
PISTACHIO_FUNCTION_DREQ2,
PISTACHIO_FUNCTION_DREQ3,
PISTACHIO_FUNCTION_DREQ4,
PISTACHIO_FUNCTION_DREQ5,
PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
PISTACHIO_FUNCTION_SYS_PLL_LOCK,
PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
PISTACHIO_FUNCTION_BT_PLL_LOCK,
PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
};
static const struct pistachio_function pistachio_functions[] = {
FUNCTION(spim0),
FUNCTION(spim1),
FUNCTION(spis),
FUNCTION(sdhost),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
FUNCTION(i2c3),
FUNCTION(audio_clk_in),
FUNCTION(i2s_out),
FUNCTION(i2s_dac_clk),
FUNCTION(audio_sync),
FUNCTION(audio_trigger),
FUNCTION(i2s_in),
FUNCTION(uart0),
FUNCTION(uart1),
FUNCTION(spdif_out),
FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
FUNCTION(eth),
FUNCTION(ir),
FUNCTION(pwmpdm),
FUNCTION(mips_trace_clk),
FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
FUNCTION(mips_trace_trigout),
FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
FUNCTION(mips_trace_dm),
FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
FUNCTION(mips_trace_data),
FUNCTION(sram_debug),
FUNCTION(rom_debug),
FUNCTION(rpu_debug),
FUNCTION(mips_debug),
FUNCTION(eth_debug),
FUNCTION(usb_debug),
FUNCTION(sdhost_debug),
FUNCTION(socif_debug),
FUNCTION(mdc_debug),
FUNCTION(ddr_debug),
FUNCTION(dreq0),
FUNCTION(dreq1),
FUNCTION(dreq2),
FUNCTION(dreq3),
FUNCTION(dreq4),
FUNCTION(dreq5),
FUNCTION(mips_pll_lock),
FUNCTION(audio_pll_lock),
FUNCTION(rpu_v_pll_lock),
FUNCTION(rpu_l_pll_lock),
FUNCTION(sys_pll_lock),
FUNCTION(wifi_pll_lock),
FUNCTION(bt_pll_lock),
FUNCTION(debug_raw_cca_ind),
FUNCTION(debug_ed_sec20_cca_ind),
FUNCTION(debug_ed_sec40_cca_ind),
FUNCTION(debug_agc_done_0),
FUNCTION(debug_agc_done_1),
FUNCTION(debug_ed_cca_ind),
FUNCTION(debug_s2l_done),
};
#define PIN_GROUP(_pin, _name) \
{ \
.name = #_name, \
.pin = PISTACHIO_PIN_##_pin, \
.mux_option = { \
PISTACHIO_FUNCTION_NONE, \
PISTACHIO_FUNCTION_NONE, \
PISTACHIO_FUNCTION_NONE, \
}, \
.mux_reg = -1, \
.mux_shift = -1, \
.mux_mask = -1, \
}
#define MFIO_PIN_GROUP(_pin, _func) \
{ \
.name = "mfio" #_pin, \
.pin = PISTACHIO_PIN_MFIO(_pin), \
.mux_option = { \
PISTACHIO_FUNCTION_##_func, \
PISTACHIO_FUNCTION_NONE, \
PISTACHIO_FUNCTION_NONE, \
}, \
.mux_reg = -1, \
.mux_shift = -1, \
.mux_mask = -1, \
}
#define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \
{ \
.name = "mfio" #_pin, \
.pin = PISTACHIO_PIN_MFIO(_pin), \
.mux_option = { \
PISTACHIO_FUNCTION_##_f0, \
PISTACHIO_FUNCTION_##_f1, \
PISTACHIO_FUNCTION_##_f2, \
}, \
.mux_reg = _reg, \
.mux_shift = _shift, \
.mux_mask = _mask, \
}
static const struct pistachio_pin_group pistachio_groups[] = {
MFIO_PIN_GROUP(0, SPIM1),
MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
PADS_FUNCTION_SELECT0, 0, 0x3),
MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
PADS_FUNCTION_SELECT0, 2, 0x3),
MFIO_PIN_GROUP(3, SPIM1),
MFIO_PIN_GROUP(4, SPIM1),
MFIO_PIN_GROUP(5, SPIM1),
MFIO_PIN_GROUP(6, SPIM1),
MFIO_PIN_GROUP(7, SPIM1),
MFIO_PIN_GROUP(8, SPIM0),
MFIO_PIN_GROUP(9, SPIM0),
MFIO_PIN_GROUP(10, SPIM0),
MFIO_PIN_GROUP(11, SPIS),
MFIO_PIN_GROUP(12, SPIS),
MFIO_PIN_GROUP(13, SPIS),
MFIO_PIN_GROUP(14, SPIS),
MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 4, 0x3),
MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 6, 0x3),
MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 8, 0x3),
MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 10, 0x3),
MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 12, 0x3),
MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 14, 0x3),
MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 16, 0x3),
MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT0, 18, 0x3),
MFIO_PIN_GROUP(23, SDHOST),
MFIO_PIN_GROUP(24, SDHOST),
MFIO_PIN_GROUP(25, SDHOST),
MFIO_PIN_GROUP(26, SDHOST),
MFIO_PIN_GROUP(27, SDHOST),
MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
PADS_FUNCTION_SELECT0, 20, 0x1),
MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
PADS_FUNCTION_SELECT0, 21, 0x1),
MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
PADS_FUNCTION_SELECT0, 22, 0x1),
MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
PADS_FUNCTION_SELECT0, 23, 0x1),
MFIO_PIN_GROUP(32, I2C2),
MFIO_PIN_GROUP(33, I2C2),
MFIO_PIN_GROUP(34, I2C3),
MFIO_PIN_GROUP(35, I2C3),
MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
PADS_FUNCTION_SELECT0, 24, 0x1),
MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
PADS_FUNCTION_SELECT0, 25, 0x1),
MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
PADS_FUNCTION_SELECT0, 26, 0x1),
MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
PADS_FUNCTION_SELECT0, 27, 0x1),
MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
PADS_FUNCTION_SELECT0, 28, 0x1),
MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
PADS_FUNCTION_SELECT0, 29, 0x1),
MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
PADS_FUNCTION_SELECT0, 30, 0x1),
MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
PADS_FUNCTION_SELECT0, 31, 0x1),
MFIO_PIN_GROUP(44, I2S_OUT),
MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
PADS_FUNCTION_SELECT1, 0, 0x1),
MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
MFIO_PIN_GROUP(47, I2S_IN),
MFIO_PIN_GROUP(48, I2S_IN),
MFIO_PIN_GROUP(49, I2S_IN),
MFIO_PIN_GROUP(50, I2S_IN),
MFIO_PIN_GROUP(51, I2S_IN),
MFIO_PIN_GROUP(52, I2S_IN),
MFIO_PIN_GROUP(53, I2S_IN),
MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
PADS_FUNCTION_SELECT1, 1, 0x3),
MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
PADS_FUNCTION_SELECT1, 3, 0x3),
MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
PADS_FUNCTION_SELECT1, 5, 0x3),
MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
PADS_FUNCTION_SELECT1, 7, 0x3),
MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
PADS_FUNCTION_SELECT1, 9, 0x1),
MFIO_PIN_GROUP(59, UART1),
MFIO_PIN_GROUP(60, UART1),
MFIO_PIN_GROUP(61, SPDIF_OUT),
MFIO_PIN_GROUP(62, SPDIF_IN),
MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 10, 0x3),
MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 12, 0x3),
MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 14, 0x3),
MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 16, 0x3),
MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 18, 0x3),
MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 20, 0x3),
MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 22, 0x3),
MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
PADS_FUNCTION_SELECT1, 24, 0x3),
MFIO_PIN_GROUP(71, ETH),
MFIO_PIN_GROUP(72, IR),
MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
PADS_FUNCTION_SELECT1, 26, 0x3),
MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
PADS_FUNCTION_SELECT1, 28, 0x3),
MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
PADS_FUNCTION_SELECT1, 30, 0x3),
MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
PADS_FUNCTION_SELECT2, 0, 0x3),
MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
PADS_FUNCTION_SELECT2, 2, 0x3),
MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
PADS_FUNCTION_SELECT2, 4, 0x3),
MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
PADS_FUNCTION_SELECT2, 6, 0x3),
MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
PADS_FUNCTION_SELECT2, 8, 0x3),
MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
PADS_FUNCTION_SELECT2, 10, 0x3),
MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
PADS_FUNCTION_SELECT2, 12, 0x3),
MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
PADS_FUNCTION_SELECT2, 14, 0x3),
MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
PADS_FUNCTION_SELECT2, 16, 0x3),
MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
PADS_FUNCTION_SELECT2, 18, 0x3),
MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
PADS_FUNCTION_SELECT2, 20, 0x3),
MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,
PADS_FUNCTION_SELECT2, 22, 0x3),
MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,
PADS_FUNCTION_SELECT2, 24, 0x3),
MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,
PADS_FUNCTION_SELECT2, 26, 0x3),
PIN_GROUP(TCK, "tck"),
PIN_GROUP(TRSTN, "trstn"),
PIN_GROUP(TDI, "tdi"),
PIN_GROUP(TMS, "tms"),
PIN_GROUP(TDO, "tdo"),
PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
PIN_GROUP(SAFE_MODE, "safe_mode"),
PIN_GROUP(POR_DISABLE, "por_disable"),
PIN_GROUP(RESETN, "resetn"),
};
static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
{
return readl(pctl->base + reg);
}
static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
{
writel(val, pctl->base + reg);
}
static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
{
return gpiochip_get_data(irq_data_get_irq_chip_data(d));
}
static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
{
return readl(bank->base + reg);
}
static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
u32 reg)
{
writel(val, bank->base + reg);
}
static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
u32 reg, unsigned int bit, u32 val)
{
/*
* For most of the GPIO registers, bit 16 + X must be set in order to
* write bit X.
*/
gpio_writel(bank, (0x10000 | val) << bit, reg);
}
static inline void gpio_enable(struct pistachio_gpio_bank *bank,
unsigned offset)
{
gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
}
static inline void gpio_disable(struct pistachio_gpio_bank *bank,
unsigned offset)
{
gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
}
static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = &pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops pistachio_pinctrl_ops = {
.get_groups_count = pistachio_pinctrl_get_groups_count,
.get_group_name = pistachio_pinctrl_get_group_name,
.get_group_pins = pistachio_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->nfunctions;
}
static const char *
pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->functions[func].name;
}
static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned func,
const char * const **groups,
unsigned * const num_groups)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->functions[func].groups;
*num_groups = pctl->functions[func].ngroups;
return 0;
}
static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
unsigned func, unsigned group)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct pistachio_pin_group *pg = &pctl->groups[group];
const struct pistachio_function *pf = &pctl->functions[func];
struct pinctrl_gpio_range *range;
unsigned int i;
u32 val;
if (pg->mux_reg > 0) {
for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
if (pg->mux_option[i] == func)
break;
}
if (i == ARRAY_SIZE(pg->mux_option)) {
dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
group, func);
return -EINVAL;
}
val = pctl_readl(pctl, pg->mux_reg);
val &= ~(pg->mux_mask << pg->mux_shift);
val |= i << pg->mux_shift;
pctl_writel(pctl, val, pg->mux_reg);
if (pf->scenarios) {
for (i = 0; i < pf->nscenarios; i++) {
if (pf->scenarios[i] == group)
break;
}
if (WARN_ON(i == pf->nscenarios))
return -EINVAL;
val = pctl_readl(pctl, pf->scenario_reg);
val &= ~(pf->scenario_mask << pf->scenario_shift);
val |= i << pf->scenario_shift;
pctl_writel(pctl, val, pf->scenario_reg);
}
}
range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
if (range)
gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);
return 0;
}
static const struct pinmux_ops pistachio_pinmux_ops = {
.get_functions_count = pistachio_pinmux_get_functions_count,
.get_function_name = pistachio_pinmux_get_function_name,
.get_function_groups = pistachio_pinmux_get_function_groups,
.set_mux = pistachio_pinmux_enable,
};
static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
u32 val, arg;
switch (param) {
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
PADS_PU_PD_SHIFT(pin);
arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
break;
case PIN_CONFIG_BIAS_PULL_UP:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
PADS_PU_PD_SHIFT(pin);
arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
PADS_PU_PD_SHIFT(pin);
arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
PADS_PU_PD_SHIFT(pin);
arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
break;
case PIN_CONFIG_SLEW_RATE:
val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
arg = !!(val & PADS_SLEW_RATE_BIT(pin));
break;
case PIN_CONFIG_DRIVE_STRENGTH:
val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
PADS_DRIVE_STRENGTH_SHIFT(pin);
switch (val & PADS_DRIVE_STRENGTH_MASK) {
case PADS_DRIVE_STRENGTH_2MA:
arg = 2;
break;
case PADS_DRIVE_STRENGTH_4MA:
arg = 4;
break;
case PADS_DRIVE_STRENGTH_8MA:
arg = 8;
break;
case PADS_DRIVE_STRENGTH_12MA:
default:
arg = 12;
break;
}
break;
default:
dev_dbg(pctl->dev, "Property %u not supported\n", param);
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
u32 drv, val, arg;
unsigned int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
if (arg)
val |= PADS_SCHMITT_EN_BIT(pin);
else
val &= ~PADS_SCHMITT_EN_BIT(pin);
pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
break;
case PIN_CONFIG_BIAS_PULL_UP:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
break;
case PIN_CONFIG_SLEW_RATE:
val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
if (arg)
val |= PADS_SLEW_RATE_BIT(pin);
else
val &= ~PADS_SLEW_RATE_BIT(pin);
pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
break;
case PIN_CONFIG_DRIVE_STRENGTH:
val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
val &= ~(PADS_DRIVE_STRENGTH_MASK <<
PADS_DRIVE_STRENGTH_SHIFT(pin));
switch (arg) {
case 2:
drv = PADS_DRIVE_STRENGTH_2MA;
break;
case 4:
drv = PADS_DRIVE_STRENGTH_4MA;
break;
case 8:
drv = PADS_DRIVE_STRENGTH_8MA;
break;
case 12:
drv = PADS_DRIVE_STRENGTH_12MA;
break;
default:
dev_err(pctl->dev,
"Drive strength %umA not supported\n",
arg);
return -EINVAL;
}
val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
break;
default:
dev_err(pctl->dev, "Property %u not supported\n",
param);
return -ENOTSUPP;
}
}
return 0;
}
static const struct pinconf_ops pistachio_pinconf_ops = {
.pin_config_get = pistachio_pinconf_get,
.pin_config_set = pistachio_pinconf_set,
.is_generic = true,
};
static struct pinctrl_desc pistachio_pinctrl_desc = {
.name = "pistachio-pinctrl",
.pctlops = &pistachio_pinctrl_ops,
.pmxops = &pistachio_pinmux_ops,
.confops = &pistachio_pinconf_ops,
};
static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
u32 reg;
if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
reg = GPIO_OUTPUT;
else
reg = GPIO_INPUT;
return !!(gpio_readl(bank, reg) & BIT(offset));
}
static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
int value)
{
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
}
static int pistachio_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
gpio_enable(bank, offset);
return 0;
}
static int pistachio_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
pistachio_gpio_set(chip, offset, value);
gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
gpio_enable(bank, offset);
return 0;
}
static void pistachio_gpio_irq_ack(struct irq_data *data)
{
struct pistachio_gpio_bank *bank = irqd_to_bank(data);
gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
}
static void pistachio_gpio_irq_mask(struct irq_data *data)
{
struct pistachio_gpio_bank *bank = irqd_to_bank(data);
gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
}
static void pistachio_gpio_irq_unmask(struct irq_data *data)
{
struct pistachio_gpio_bank *bank = irqd_to_bank(data);
gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
}
static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
pistachio_gpio_direction_input(chip, data->hwirq);
pistachio_gpio_irq_unmask(data);
return 0;
}
static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct pistachio_gpio_bank *bank = irqd_to_bank(data);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
GPIO_INTERRUPT_TYPE_EDGE);
gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
GPIO_INTERRUPT_EDGE_SINGLE);
break;
case IRQ_TYPE_EDGE_FALLING:
gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
GPIO_INTERRUPT_TYPE_EDGE);
gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
GPIO_INTERRUPT_EDGE_SINGLE);
break;
case IRQ_TYPE_EDGE_BOTH:
gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
GPIO_INTERRUPT_TYPE_EDGE);
gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
GPIO_INTERRUPT_EDGE_DUAL);
break;
case IRQ_TYPE_LEVEL_HIGH:
gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
GPIO_INTERRUPT_TYPE_LEVEL);
break;
case IRQ_TYPE_LEVEL_LOW:
gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
GPIO_INTERRUPT_TYPE_LEVEL);
break;
default:
return -EINVAL;
}
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);
return 0;
}
static void pistachio_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned int pin;
chained_irq_enter(chip, desc);
pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
gpio_readl(bank, GPIO_INTERRUPT_EN);
for_each_set_bit(pin, &pending, 16)
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}
#define GPIO_BANK(_bank, _pin_base, _npins) \
{ \
.instance = (_bank), \
.pin_base = _pin_base, \
.npins = _npins, \
.gpio_chip = { \
.label = "GPIO" #_bank, \
.request = gpiochip_generic_request, \
.free = gpiochip_generic_free, \
.get_direction = pistachio_gpio_get_direction, \
.direction_input = pistachio_gpio_direction_input, \
.direction_output = pistachio_gpio_direction_output, \
.get = pistachio_gpio_get, \
.set = pistachio_gpio_set, \
.base = _pin_base, \
.ngpio = _npins, \
}, \
}
static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
};
static void pistachio_gpio_irq_print_chip(struct irq_data *data,
struct seq_file *p)
{
struct pistachio_gpio_bank *bank = irqd_to_bank(data);
seq_printf(p, "GPIO%d", bank->instance);
}
static const struct irq_chip pistachio_gpio_irq_chip = {
.irq_startup = pistachio_gpio_irq_startup,
.irq_ack = pistachio_gpio_irq_ack,
.irq_mask = pistachio_gpio_irq_mask,
.irq_unmask = pistachio_gpio_irq_unmask,
.irq_set_type = pistachio_gpio_irq_set_type,
.irq_print_chip = pistachio_gpio_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
{
struct pistachio_gpio_bank *bank;
unsigned int i;
int irq, ret = 0;
for (i = 0; i < pctl->nbanks; i++) {
char child_name[sizeof("gpioXX")];
struct fwnode_handle *child;
struct gpio_irq_chip *girq;
snprintf(child_name, sizeof(child_name), "gpio%d", i);
child = device_get_named_child_node(pctl->dev, child_name);
if (!child) {
dev_err(pctl->dev, "No node for bank %u\n", i);
ret = -ENODEV;
goto err;
}
if (!fwnode_property_present(child, "gpio-controller")) {
fwnode_handle_put(child);
dev_err(pctl->dev,
"No gpio-controller property for bank %u\n", i);
ret = -ENODEV;
goto err;
}
ret = fwnode_irq_get(child, 0);
if (ret < 0) {
fwnode_handle_put(child);
dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);
goto err;
}
if (!ret) {
fwnode_handle_put(child);
dev_err(pctl->dev, "No IRQ for bank %u\n", i);
ret = -EINVAL;
goto err;
}
irq = ret;
bank = &pctl->gpio_banks[i];
bank->pctl = pctl;
bank->base = pctl->base + GPIO_BANK_BASE(i);
bank->gpio_chip.parent = pctl->dev;
bank->gpio_chip.fwnode = child;
girq = &bank->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &pistachio_gpio_irq_chip);
girq->parent_handler = pistachio_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(pctl->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents) {
ret = -ENOMEM;
goto err;
}
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
ret = gpiochip_add_data(&bank->gpio_chip, bank);
if (ret < 0) {
dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
i, ret);
goto err;
}
ret = gpiochip_add_pin_range(&bank->gpio_chip,
dev_name(pctl->dev), 0,
bank->pin_base, bank->npins);
if (ret < 0) {
dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
i, ret);
gpiochip_remove(&bank->gpio_chip);
goto err;
}
}
return 0;
err:
for (; i > 0; i--) {
bank = &pctl->gpio_banks[i - 1];
gpiochip_remove(&bank->gpio_chip);
}
return ret;
}
static const struct of_device_id pistachio_pinctrl_of_match[] = {
{ .compatible = "img,pistachio-system-pinctrl", },
{ },
};
static int pistachio_pinctrl_probe(struct platform_device *pdev)
{
struct pistachio_pinctrl *pctl;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, pctl);
pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctl->base))
return PTR_ERR(pctl->base);
pctl->pins = pistachio_pins;
pctl->npins = ARRAY_SIZE(pistachio_pins);
pctl->functions = pistachio_functions;
pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
pctl->groups = pistachio_groups;
pctl->ngroups = ARRAY_SIZE(pistachio_groups);
pctl->gpio_banks = pistachio_gpio_banks;
pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
pistachio_pinctrl_desc.pins = pctl->pins;
pistachio_pinctrl_desc.npins = pctl->npins;
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
pctl);
if (IS_ERR(pctl->pctldev)) {
dev_err(&pdev->dev, "Failed to register pinctrl device\n");
return PTR_ERR(pctl->pctldev);
}
return pistachio_gpio_register(pctl);
}
static struct platform_driver pistachio_pinctrl_driver = {
.driver = {
.name = "pistachio-pinctrl",
.of_match_table = pistachio_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = pistachio_pinctrl_probe,
};
static int __init pistachio_pinctrl_register(void)
{
return platform_driver_register(&pistachio_pinctrl_driver);
}
arch_initcall(pistachio_pinctrl_register);
|
linux-master
|
drivers/pinctrl/pinctrl-pistachio.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/pinctrl/pinmux-falcon.c
* based on linux/drivers/pinctrl/pinmux-pxa910.c
*
* Copyright (C) 2012 Thomas Langer <[email protected]>
* Copyright (C) 2012 John Crispin <[email protected]>
*/
#include <linux/err.h>
#include <linux/export.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "pinctrl-lantiq.h"
#include <lantiq_soc.h>
/* Multiplexer Control Register */
#define LTQ_PADC_MUX(x) (x * 0x4)
/* Pull Up Enable Register */
#define LTQ_PADC_PUEN 0x80
/* Pull Down Enable Register */
#define LTQ_PADC_PDEN 0x84
/* Slew Rate Control Register */
#define LTQ_PADC_SRC 0x88
/* Drive Current Control Register */
#define LTQ_PADC_DCC 0x8C
/* Pad Control Availability Register */
#define LTQ_PADC_AVAIL 0xF0
#define pad_r32(p, reg) ltq_r32(p + reg)
#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
#define pad_w32_mask(c, clear, set, reg) \
pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
#define PORTS 5
#define PINS 32
#define PORT(x) (x / PINS)
#define PORT_PIN(x) (x % PINS)
#define MFP_FALCON(a, f0, f1, f2, f3) \
{ \
.name = #a, \
.pin = a, \
.func = { \
FALCON_MUX_##f0, \
FALCON_MUX_##f1, \
FALCON_MUX_##f2, \
FALCON_MUX_##f3, \
}, \
}
#define GRP_MUX(a, m, p) \
{ \
.name = a, \
.mux = FALCON_MUX_##m, \
.pins = p, \
.npins = ARRAY_SIZE(p), \
}
enum falcon_mux {
FALCON_MUX_GPIO = 0,
FALCON_MUX_RST,
FALCON_MUX_NTR,
FALCON_MUX_PPS,
FALCON_MUX_MDIO,
FALCON_MUX_LED,
FALCON_MUX_SPI,
FALCON_MUX_ASC,
FALCON_MUX_I2C,
FALCON_MUX_HOSTIF,
FALCON_MUX_SLIC,
FALCON_MUX_JTAG,
FALCON_MUX_PCM,
FALCON_MUX_MII,
FALCON_MUX_PHY,
FALCON_MUX_NONE = 0xffff,
};
static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
static int pad_count[PORTS];
static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
{
int base = bank * PINS;
int i;
for (i = 0; i < len; i++) {
d[i].number = base + i;
d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
}
pad_count[bank] = len;
}
static struct ltq_mfp_pin falcon_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
};
static const unsigned pins_por[] = {GPIO0};
static const unsigned pins_ntr[] = {GPIO4};
static const unsigned pins_ntr8k[] = {GPIO5};
static const unsigned pins_pps[] = {GPIO5};
static const unsigned pins_hrst[] = {GPIO6};
static const unsigned pins_mdio[] = {GPIO7, GPIO8};
static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
GPIO12, GPIO13, GPIO14};
static const unsigned pins_asc0[] = {GPIO32, GPIO33};
static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
static const unsigned pins_spi_cs0[] = {GPIO37};
static const unsigned pins_spi_cs1[] = {GPIO38};
static const unsigned pins_i2c[] = {GPIO39, GPIO40};
static const unsigned pins_jtag[] = {GPIO41};
static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
static const unsigned pins_pcm[] = {GPIO44, GPIO45};
static const unsigned pins_asc1[] = {GPIO44, GPIO45};
static struct ltq_pin_group falcon_grps[] = {
GRP_MUX("por", RST, pins_por),
GRP_MUX("ntr", NTR, pins_ntr),
GRP_MUX("ntr8k", NTR, pins_ntr8k),
GRP_MUX("pps", PPS, pins_pps),
GRP_MUX("hrst", RST, pins_hrst),
GRP_MUX("mdio", MDIO, pins_mdio),
GRP_MUX("bootled", LED, pins_bled),
GRP_MUX("asc0", ASC, pins_asc0),
GRP_MUX("spi", SPI, pins_spi),
GRP_MUX("spi cs0", SPI, pins_spi_cs0),
GRP_MUX("spi cs1", SPI, pins_spi_cs1),
GRP_MUX("i2c", I2C, pins_i2c),
GRP_MUX("jtag", JTAG, pins_jtag),
GRP_MUX("slic", SLIC, pins_slic),
GRP_MUX("pcm", PCM, pins_pcm),
GRP_MUX("asc1", ASC, pins_asc1),
};
static const char * const ltq_rst_grps[] = {"por", "hrst"};
static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
static const char * const ltq_mdio_grps[] = {"mdio"};
static const char * const ltq_bled_grps[] = {"bootled"};
static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
static const char * const ltq_i2c_grps[] = {"i2c"};
static const char * const ltq_jtag_grps[] = {"jtag"};
static const char * const ltq_slic_grps[] = {"slic"};
static const char * const ltq_pcm_grps[] = {"pcm"};
static struct ltq_pmx_func falcon_funcs[] = {
{"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
{"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
{"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
{"led", ARRAY_AND_SIZE(ltq_bled_grps)},
{"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
{"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
{"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
{"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
{"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
{"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
};
/* --------- pinconf related code --------- */
static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
unsigned group, unsigned long *config)
{
return -ENOTSUPP;
}
static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
return -ENOTSUPP;
}
static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
unsigned pin, unsigned long *config)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
void __iomem *mem = info->membase[PORT(pin)];
switch (param) {
case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
*config = LTQ_PINCONF_PACK(param,
!!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
break;
case LTQ_PINCONF_PARAM_SLEW_RATE:
*config = LTQ_PINCONF_PACK(param,
!!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
break;
case LTQ_PINCONF_PARAM_PULL:
if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
*config = LTQ_PINCONF_PACK(param, 1);
else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
*config = LTQ_PINCONF_PACK(param, 2);
else
*config = LTQ_PINCONF_PACK(param, 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
enum ltq_pinconf_param param;
int arg;
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
void __iomem *mem = info->membase[PORT(pin)];
u32 reg;
int i;
for (i = 0; i < num_configs; i++) {
param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
switch (param) {
case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
reg = LTQ_PADC_DCC;
break;
case LTQ_PINCONF_PARAM_SLEW_RATE:
reg = LTQ_PADC_SRC;
break;
case LTQ_PINCONF_PARAM_PULL:
if (arg == 1)
reg = LTQ_PADC_PDEN;
else
reg = LTQ_PADC_PUEN;
break;
default:
pr_err("%s: Invalid config param %04x\n",
pinctrl_dev_get_name(pctrldev), param);
return -ENOTSUPP;
}
pad_w32(mem, BIT(PORT_PIN(pin)), reg);
if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
return -ENOTSUPP;
} /* for each config */
return 0;
}
static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
struct seq_file *s, unsigned offset)
{
unsigned long config;
struct pin_desc *desc;
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int port = PORT(offset);
seq_printf(s, " (port %d) mux %d -- ", port,
pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
if (!falcon_pinconf_get(pctrldev, offset, &config))
seq_printf(s, "pull %d ",
(int)LTQ_PINCONF_UNPACK_ARG(config));
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
if (!falcon_pinconf_get(pctrldev, offset, &config))
seq_printf(s, "drive-current %d ",
(int)LTQ_PINCONF_UNPACK_ARG(config));
config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
if (!falcon_pinconf_get(pctrldev, offset, &config))
seq_printf(s, "slew-rate %d ",
(int)LTQ_PINCONF_UNPACK_ARG(config));
desc = pin_desc_get(pctrldev, offset);
if (desc) {
if (desc->gpio_owner)
seq_printf(s, " owner: %s", desc->gpio_owner);
} else {
seq_printf(s, " not registered");
}
}
static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
struct seq_file *s, unsigned selector)
{
}
static const struct pinconf_ops falcon_pinconf_ops = {
.pin_config_get = falcon_pinconf_get,
.pin_config_set = falcon_pinconf_set,
.pin_config_group_get = falcon_pinconf_group_get,
.pin_config_group_set = falcon_pinconf_group_set,
.pin_config_dbg_show = falcon_pinconf_dbg_show,
.pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
};
static struct pinctrl_desc falcon_pctrl_desc = {
.owner = THIS_MODULE,
.pins = falcon_pads,
.confops = &falcon_pinconf_ops,
};
static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
int mfp, int mux)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int port = PORT(info->mfp[mfp].pin);
if ((port >= PORTS) || (!info->membase[port]))
return -ENODEV;
pad_w32(info->membase[port], mux,
LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
return 0;
}
static const struct ltq_cfg_param falcon_cfg_params[] = {
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
{"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
{"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
};
static struct ltq_pinmux_info falcon_info = {
.desc = &falcon_pctrl_desc,
.apply_mux = falcon_mux_apply,
.params = falcon_cfg_params,
.num_params = ARRAY_SIZE(falcon_cfg_params),
};
/* --------- register the pinctrl layer --------- */
int pinctrl_falcon_get_range_size(int id)
{
u32 avail;
if ((id >= PORTS) || (!falcon_info.membase[id]))
return -EINVAL;
avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
return fls(avail);
}
void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
{
pinctrl_add_gpio_range(falcon_info.pctrl, range);
}
static int pinctrl_falcon_probe(struct platform_device *pdev)
{
struct device_node *np;
int pad_count = 0;
int ret = 0;
/* load and remap the pad resources of the different banks */
for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
struct resource res;
struct platform_device *ppdev;
u32 avail;
int pins;
if (!of_device_is_available(np))
continue;
if (!bank || *bank >= PORTS)
continue;
if (of_address_to_resource(np, 0, &res))
continue;
ppdev = of_find_device_by_node(np);
if (!ppdev) {
dev_err(&pdev->dev, "failed to find pad pdev\n");
continue;
}
falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
put_device(&ppdev->dev);
if (IS_ERR(falcon_info.clk[*bank])) {
dev_err(&ppdev->dev, "failed to get clock\n");
of_node_put(np);
return PTR_ERR(falcon_info.clk[*bank]);
}
falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
&res);
if (IS_ERR(falcon_info.membase[*bank])) {
of_node_put(np);
return PTR_ERR(falcon_info.membase[*bank]);
}
avail = pad_r32(falcon_info.membase[*bank],
LTQ_PADC_AVAIL);
pins = fls(avail);
lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
pad_count += pins;
clk_enable(falcon_info.clk[*bank]);
dev_dbg(&pdev->dev, "found %s with %d pads\n",
res.name, pins);
}
dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
falcon_pctrl_desc.name = dev_name(&pdev->dev);
falcon_pctrl_desc.npins = pad_count;
falcon_info.mfp = falcon_mfp;
falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
falcon_info.grps = falcon_grps;
falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
falcon_info.funcs = falcon_funcs;
falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
ret = ltq_pinctrl_register(pdev, &falcon_info);
if (!ret)
dev_info(&pdev->dev, "Init done\n");
return ret;
}
static const struct of_device_id falcon_match[] = {
{ .compatible = "lantiq,pinctrl-falcon" },
{},
};
MODULE_DEVICE_TABLE(of, falcon_match);
static struct platform_driver pinctrl_falcon_driver = {
.probe = pinctrl_falcon_probe,
.driver = {
.name = "pinctrl-falcon",
.of_match_table = falcon_match,
},
};
int __init pinctrl_falcon_init(void)
{
return platform_driver_register(&pinctrl_falcon_driver);
}
core_initcall_sync(pinctrl_falcon_init);
|
linux-master
|
drivers/pinctrl/pinctrl-falcon.c
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Microsemi SoCs pinctrl driver
*
* Author: <[email protected]>
* License: Dual MIT/GPL
* Copyright (c) 2017 Microsemi Corporation
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mfd/ocelot.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#define ocelot_clrsetbits(addr, clear, set) \
writel((readl(addr) & ~(clear)) | (set), (addr))
enum {
PINCONF_BIAS,
PINCONF_SCHMITT,
PINCONF_DRIVE_STRENGTH,
};
/* GPIO standard registers */
#define OCELOT_GPIO_OUT_SET 0x0
#define OCELOT_GPIO_OUT_CLR 0x4
#define OCELOT_GPIO_OUT 0x8
#define OCELOT_GPIO_IN 0xc
#define OCELOT_GPIO_OE 0x10
#define OCELOT_GPIO_INTR 0x14
#define OCELOT_GPIO_INTR_ENA 0x18
#define OCELOT_GPIO_INTR_IDENT 0x1c
#define OCELOT_GPIO_ALT0 0x20
#define OCELOT_GPIO_ALT1 0x24
#define OCELOT_GPIO_SD_MAP 0x28
#define OCELOT_FUNC_PER_PIN 4
enum {
FUNC_CAN0_a,
FUNC_CAN0_b,
FUNC_CAN1,
FUNC_CLKMON,
FUNC_NONE,
FUNC_FC0_a,
FUNC_FC0_b,
FUNC_FC0_c,
FUNC_FC1_a,
FUNC_FC1_b,
FUNC_FC1_c,
FUNC_FC2_a,
FUNC_FC2_b,
FUNC_FC3_a,
FUNC_FC3_b,
FUNC_FC3_c,
FUNC_FC4_a,
FUNC_FC4_b,
FUNC_FC4_c,
FUNC_FC_SHRD0,
FUNC_FC_SHRD1,
FUNC_FC_SHRD2,
FUNC_FC_SHRD3,
FUNC_FC_SHRD4,
FUNC_FC_SHRD5,
FUNC_FC_SHRD6,
FUNC_FC_SHRD7,
FUNC_FC_SHRD8,
FUNC_FC_SHRD9,
FUNC_FC_SHRD10,
FUNC_FC_SHRD11,
FUNC_FC_SHRD12,
FUNC_FC_SHRD13,
FUNC_FC_SHRD14,
FUNC_FC_SHRD15,
FUNC_FC_SHRD16,
FUNC_FC_SHRD17,
FUNC_FC_SHRD18,
FUNC_FC_SHRD19,
FUNC_FC_SHRD20,
FUNC_GPIO,
FUNC_IB_TRG_a,
FUNC_IB_TRG_b,
FUNC_IB_TRG_c,
FUNC_IRQ0,
FUNC_IRQ_IN_a,
FUNC_IRQ_IN_b,
FUNC_IRQ_IN_c,
FUNC_IRQ0_IN,
FUNC_IRQ_OUT_a,
FUNC_IRQ_OUT_b,
FUNC_IRQ_OUT_c,
FUNC_IRQ0_OUT,
FUNC_IRQ1,
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
FUNC_EXT_IRQ,
FUNC_MIIM,
FUNC_MIIM_a,
FUNC_MIIM_b,
FUNC_MIIM_c,
FUNC_MIIM_Sa,
FUNC_MIIM_Sb,
FUNC_OB_TRG,
FUNC_OB_TRG_a,
FUNC_OB_TRG_b,
FUNC_PHY_LED,
FUNC_PCI_WAKE,
FUNC_MD,
FUNC_PTP0,
FUNC_PTP1,
FUNC_PTP2,
FUNC_PTP3,
FUNC_PTPSYNC_0,
FUNC_PTPSYNC_1,
FUNC_PTPSYNC_2,
FUNC_PTPSYNC_3,
FUNC_PTPSYNC_4,
FUNC_PTPSYNC_5,
FUNC_PTPSYNC_6,
FUNC_PTPSYNC_7,
FUNC_PWM,
FUNC_PWM_a,
FUNC_PWM_b,
FUNC_QSPI1,
FUNC_QSPI2,
FUNC_R,
FUNC_RECO_a,
FUNC_RECO_b,
FUNC_RECO_CLK,
FUNC_SD,
FUNC_SFP,
FUNC_SFP_SD,
FUNC_SG0,
FUNC_SG1,
FUNC_SG2,
FUNC_SGPIO_a,
FUNC_SGPIO_b,
FUNC_SI,
FUNC_SI2,
FUNC_TACHO,
FUNC_TACHO_a,
FUNC_TACHO_b,
FUNC_TWI,
FUNC_TWI2,
FUNC_TWI3,
FUNC_TWI_SCL_M,
FUNC_TWI_SLC_GATE,
FUNC_TWI_SLC_GATE_AD,
FUNC_UART,
FUNC_UART2,
FUNC_UART3,
FUNC_USB_H_a,
FUNC_USB_H_b,
FUNC_USB_H_c,
FUNC_USB_S_a,
FUNC_USB_S_b,
FUNC_USB_S_c,
FUNC_PLL_STAT,
FUNC_EMMC,
FUNC_EMMC_SD,
FUNC_REF_CLK,
FUNC_RCVRD_CLK,
FUNC_MAX
};
static const char *const ocelot_function_names[] = {
[FUNC_CAN0_a] = "can0_a",
[FUNC_CAN0_b] = "can0_b",
[FUNC_CAN1] = "can1",
[FUNC_CLKMON] = "clkmon",
[FUNC_NONE] = "none",
[FUNC_FC0_a] = "fc0_a",
[FUNC_FC0_b] = "fc0_b",
[FUNC_FC0_c] = "fc0_c",
[FUNC_FC1_a] = "fc1_a",
[FUNC_FC1_b] = "fc1_b",
[FUNC_FC1_c] = "fc1_c",
[FUNC_FC2_a] = "fc2_a",
[FUNC_FC2_b] = "fc2_b",
[FUNC_FC3_a] = "fc3_a",
[FUNC_FC3_b] = "fc3_b",
[FUNC_FC3_c] = "fc3_c",
[FUNC_FC4_a] = "fc4_a",
[FUNC_FC4_b] = "fc4_b",
[FUNC_FC4_c] = "fc4_c",
[FUNC_FC_SHRD0] = "fc_shrd0",
[FUNC_FC_SHRD1] = "fc_shrd1",
[FUNC_FC_SHRD2] = "fc_shrd2",
[FUNC_FC_SHRD3] = "fc_shrd3",
[FUNC_FC_SHRD4] = "fc_shrd4",
[FUNC_FC_SHRD5] = "fc_shrd5",
[FUNC_FC_SHRD6] = "fc_shrd6",
[FUNC_FC_SHRD7] = "fc_shrd7",
[FUNC_FC_SHRD8] = "fc_shrd8",
[FUNC_FC_SHRD9] = "fc_shrd9",
[FUNC_FC_SHRD10] = "fc_shrd10",
[FUNC_FC_SHRD11] = "fc_shrd11",
[FUNC_FC_SHRD12] = "fc_shrd12",
[FUNC_FC_SHRD13] = "fc_shrd13",
[FUNC_FC_SHRD14] = "fc_shrd14",
[FUNC_FC_SHRD15] = "fc_shrd15",
[FUNC_FC_SHRD16] = "fc_shrd16",
[FUNC_FC_SHRD17] = "fc_shrd17",
[FUNC_FC_SHRD18] = "fc_shrd18",
[FUNC_FC_SHRD19] = "fc_shrd19",
[FUNC_FC_SHRD20] = "fc_shrd20",
[FUNC_GPIO] = "gpio",
[FUNC_IB_TRG_a] = "ib_trig_a",
[FUNC_IB_TRG_b] = "ib_trig_b",
[FUNC_IB_TRG_c] = "ib_trig_c",
[FUNC_IRQ0] = "irq0",
[FUNC_IRQ_IN_a] = "irq_in_a",
[FUNC_IRQ_IN_b] = "irq_in_b",
[FUNC_IRQ_IN_c] = "irq_in_c",
[FUNC_IRQ0_IN] = "irq0_in",
[FUNC_IRQ_OUT_a] = "irq_out_a",
[FUNC_IRQ_OUT_b] = "irq_out_b",
[FUNC_IRQ_OUT_c] = "irq_out_c",
[FUNC_IRQ0_OUT] = "irq0_out",
[FUNC_IRQ1] = "irq1",
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
[FUNC_EXT_IRQ] = "ext_irq",
[FUNC_MIIM] = "miim",
[FUNC_MIIM_a] = "miim_a",
[FUNC_MIIM_b] = "miim_b",
[FUNC_MIIM_c] = "miim_c",
[FUNC_MIIM_Sa] = "miim_slave_a",
[FUNC_MIIM_Sb] = "miim_slave_b",
[FUNC_PHY_LED] = "phy_led",
[FUNC_PCI_WAKE] = "pci_wake",
[FUNC_MD] = "md",
[FUNC_OB_TRG] = "ob_trig",
[FUNC_OB_TRG_a] = "ob_trig_a",
[FUNC_OB_TRG_b] = "ob_trig_b",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
[FUNC_PTP2] = "ptp2",
[FUNC_PTP3] = "ptp3",
[FUNC_PTPSYNC_0] = "ptpsync_0",
[FUNC_PTPSYNC_1] = "ptpsync_1",
[FUNC_PTPSYNC_2] = "ptpsync_2",
[FUNC_PTPSYNC_3] = "ptpsync_3",
[FUNC_PTPSYNC_4] = "ptpsync_4",
[FUNC_PTPSYNC_5] = "ptpsync_5",
[FUNC_PTPSYNC_6] = "ptpsync_6",
[FUNC_PTPSYNC_7] = "ptpsync_7",
[FUNC_PWM] = "pwm",
[FUNC_PWM_a] = "pwm_a",
[FUNC_PWM_b] = "pwm_b",
[FUNC_QSPI1] = "qspi1",
[FUNC_QSPI2] = "qspi2",
[FUNC_R] = "reserved",
[FUNC_RECO_a] = "reco_a",
[FUNC_RECO_b] = "reco_b",
[FUNC_RECO_CLK] = "reco_clk",
[FUNC_SD] = "sd",
[FUNC_SFP] = "sfp",
[FUNC_SFP_SD] = "sfp_sd",
[FUNC_SG0] = "sg0",
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
[FUNC_SGPIO_a] = "sgpio_a",
[FUNC_SGPIO_b] = "sgpio_b",
[FUNC_SI] = "si",
[FUNC_SI2] = "si2",
[FUNC_TACHO] = "tacho",
[FUNC_TACHO_a] = "tacho_a",
[FUNC_TACHO_b] = "tacho_b",
[FUNC_TWI] = "twi",
[FUNC_TWI2] = "twi2",
[FUNC_TWI3] = "twi3",
[FUNC_TWI_SCL_M] = "twi_scl_m",
[FUNC_TWI_SLC_GATE] = "twi_slc_gate",
[FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad",
[FUNC_USB_H_a] = "usb_host_a",
[FUNC_USB_H_b] = "usb_host_b",
[FUNC_USB_H_c] = "usb_host_c",
[FUNC_USB_S_a] = "usb_slave_a",
[FUNC_USB_S_b] = "usb_slave_b",
[FUNC_USB_S_c] = "usb_slave_c",
[FUNC_UART] = "uart",
[FUNC_UART2] = "uart2",
[FUNC_UART3] = "uart3",
[FUNC_PLL_STAT] = "pll_stat",
[FUNC_EMMC] = "emmc",
[FUNC_EMMC_SD] = "emmc_sd",
[FUNC_REF_CLK] = "ref_clk",
[FUNC_RCVRD_CLK] = "rcvrd_clk",
};
struct ocelot_pmx_func {
const char **groups;
unsigned int ngroups;
};
struct ocelot_pin_caps {
unsigned int pin;
unsigned char functions[OCELOT_FUNC_PER_PIN];
unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */
};
struct ocelot_pincfg_data {
u8 pd_bit;
u8 pu_bit;
u8 drive_bits;
u8 schmitt_bit;
};
struct ocelot_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct regmap *map;
struct regmap *pincfg;
struct pinctrl_desc *desc;
const struct ocelot_pincfg_data *pincfg_data;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
struct workqueue_struct *wq;
};
struct ocelot_match_data {
struct pinctrl_desc desc;
struct ocelot_pincfg_data pincfg_data;
};
struct ocelot_irq_work {
struct work_struct irq_work;
struct irq_desc *irq_desc;
};
#define LUTON_P(p, f0, f1) \
static struct ocelot_pin_caps luton_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \
}, \
}
LUTON_P(0, SG0, NONE);
LUTON_P(1, SG0, NONE);
LUTON_P(2, SG0, NONE);
LUTON_P(3, SG0, NONE);
LUTON_P(4, TACHO, NONE);
LUTON_P(5, TWI, PHY_LED);
LUTON_P(6, TWI, PHY_LED);
LUTON_P(7, NONE, PHY_LED);
LUTON_P(8, EXT_IRQ, PHY_LED);
LUTON_P(9, EXT_IRQ, PHY_LED);
LUTON_P(10, SFP, PHY_LED);
LUTON_P(11, SFP, PHY_LED);
LUTON_P(12, SFP, PHY_LED);
LUTON_P(13, SFP, PHY_LED);
LUTON_P(14, SI, PHY_LED);
LUTON_P(15, SI, PHY_LED);
LUTON_P(16, SI, PHY_LED);
LUTON_P(17, SFP, PHY_LED);
LUTON_P(18, SFP, PHY_LED);
LUTON_P(19, SFP, PHY_LED);
LUTON_P(20, SFP, PHY_LED);
LUTON_P(21, SFP, PHY_LED);
LUTON_P(22, SFP, PHY_LED);
LUTON_P(23, SFP, PHY_LED);
LUTON_P(24, SFP, PHY_LED);
LUTON_P(25, SFP, PHY_LED);
LUTON_P(26, SFP, PHY_LED);
LUTON_P(27, SFP, PHY_LED);
LUTON_P(28, SFP, PHY_LED);
LUTON_P(29, PWM, NONE);
LUTON_P(30, UART, NONE);
LUTON_P(31, UART, NONE);
#define LUTON_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &luton_pin_##n \
}
static const struct pinctrl_pin_desc luton_pins[] = {
LUTON_PIN(0),
LUTON_PIN(1),
LUTON_PIN(2),
LUTON_PIN(3),
LUTON_PIN(4),
LUTON_PIN(5),
LUTON_PIN(6),
LUTON_PIN(7),
LUTON_PIN(8),
LUTON_PIN(9),
LUTON_PIN(10),
LUTON_PIN(11),
LUTON_PIN(12),
LUTON_PIN(13),
LUTON_PIN(14),
LUTON_PIN(15),
LUTON_PIN(16),
LUTON_PIN(17),
LUTON_PIN(18),
LUTON_PIN(19),
LUTON_PIN(20),
LUTON_PIN(21),
LUTON_PIN(22),
LUTON_PIN(23),
LUTON_PIN(24),
LUTON_PIN(25),
LUTON_PIN(26),
LUTON_PIN(27),
LUTON_PIN(28),
LUTON_PIN(29),
LUTON_PIN(30),
LUTON_PIN(31),
};
#define SERVAL_P(p, f0, f1, f2) \
static struct ocelot_pin_caps serval_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
}, \
}
SERVAL_P(0, SG0, NONE, NONE);
SERVAL_P(1, SG0, NONE, NONE);
SERVAL_P(2, SG0, NONE, NONE);
SERVAL_P(3, SG0, NONE, NONE);
SERVAL_P(4, TACHO, NONE, NONE);
SERVAL_P(5, PWM, NONE, NONE);
SERVAL_P(6, TWI, NONE, NONE);
SERVAL_P(7, TWI, NONE, NONE);
SERVAL_P(8, SI, NONE, NONE);
SERVAL_P(9, SI, MD, NONE);
SERVAL_P(10, SI, MD, NONE);
SERVAL_P(11, SFP, MD, TWI_SCL_M);
SERVAL_P(12, SFP, MD, TWI_SCL_M);
SERVAL_P(13, SFP, UART2, TWI_SCL_M);
SERVAL_P(14, SFP, UART2, TWI_SCL_M);
SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
SERVAL_P(18, SFP, NONE, TWI_SCL_M);
SERVAL_P(19, SFP, NONE, TWI_SCL_M);
SERVAL_P(20, SFP, NONE, TWI_SCL_M);
SERVAL_P(21, SFP, NONE, TWI_SCL_M);
SERVAL_P(22, NONE, NONE, NONE);
SERVAL_P(23, NONE, NONE, NONE);
SERVAL_P(24, NONE, NONE, NONE);
SERVAL_P(25, NONE, NONE, NONE);
SERVAL_P(26, UART, NONE, NONE);
SERVAL_P(27, UART, NONE, NONE);
SERVAL_P(28, IRQ0, NONE, NONE);
SERVAL_P(29, IRQ1, NONE, NONE);
SERVAL_P(30, PTP0, NONE, NONE);
SERVAL_P(31, PTP0, NONE, NONE);
#define SERVAL_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &serval_pin_##n \
}
static const struct pinctrl_pin_desc serval_pins[] = {
SERVAL_PIN(0),
SERVAL_PIN(1),
SERVAL_PIN(2),
SERVAL_PIN(3),
SERVAL_PIN(4),
SERVAL_PIN(5),
SERVAL_PIN(6),
SERVAL_PIN(7),
SERVAL_PIN(8),
SERVAL_PIN(9),
SERVAL_PIN(10),
SERVAL_PIN(11),
SERVAL_PIN(12),
SERVAL_PIN(13),
SERVAL_PIN(14),
SERVAL_PIN(15),
SERVAL_PIN(16),
SERVAL_PIN(17),
SERVAL_PIN(18),
SERVAL_PIN(19),
SERVAL_PIN(20),
SERVAL_PIN(21),
SERVAL_PIN(22),
SERVAL_PIN(23),
SERVAL_PIN(24),
SERVAL_PIN(25),
SERVAL_PIN(26),
SERVAL_PIN(27),
SERVAL_PIN(28),
SERVAL_PIN(29),
SERVAL_PIN(30),
SERVAL_PIN(31),
};
#define OCELOT_P(p, f0, f1, f2) \
static struct ocelot_pin_caps ocelot_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
}, \
}
OCELOT_P(0, SG0, NONE, NONE);
OCELOT_P(1, SG0, NONE, NONE);
OCELOT_P(2, SG0, NONE, NONE);
OCELOT_P(3, SG0, NONE, NONE);
OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
OCELOT_P(6, UART, TWI_SCL_M, NONE);
OCELOT_P(7, UART, TWI_SCL_M, NONE);
OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
OCELOT_P(12, UART2, TWI_SCL_M, SFP);
OCELOT_P(13, UART2, TWI_SCL_M, SFP);
OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
OCELOT_P(16, TWI, NONE, SI);
OCELOT_P(17, TWI, TWI_SCL_M, SI);
OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
#define OCELOT_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &ocelot_pin_##n \
}
static const struct pinctrl_pin_desc ocelot_pins[] = {
OCELOT_PIN(0),
OCELOT_PIN(1),
OCELOT_PIN(2),
OCELOT_PIN(3),
OCELOT_PIN(4),
OCELOT_PIN(5),
OCELOT_PIN(6),
OCELOT_PIN(7),
OCELOT_PIN(8),
OCELOT_PIN(9),
OCELOT_PIN(10),
OCELOT_PIN(11),
OCELOT_PIN(12),
OCELOT_PIN(13),
OCELOT_PIN(14),
OCELOT_PIN(15),
OCELOT_PIN(16),
OCELOT_PIN(17),
OCELOT_PIN(18),
OCELOT_PIN(19),
OCELOT_PIN(20),
OCELOT_PIN(21),
};
#define JAGUAR2_P(p, f0, f1) \
static struct ocelot_pin_caps jaguar2_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
}, \
}
JAGUAR2_P(0, SG0, NONE);
JAGUAR2_P(1, SG0, NONE);
JAGUAR2_P(2, SG0, NONE);
JAGUAR2_P(3, SG0, NONE);
JAGUAR2_P(4, SG1, NONE);
JAGUAR2_P(5, SG1, NONE);
JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
JAGUAR2_P(8, PTP0, NONE);
JAGUAR2_P(9, PTP1, NONE);
JAGUAR2_P(10, UART, NONE);
JAGUAR2_P(11, UART, NONE);
JAGUAR2_P(12, SG1, NONE);
JAGUAR2_P(13, SG1, NONE);
JAGUAR2_P(14, TWI, TWI_SCL_M);
JAGUAR2_P(15, TWI, NONE);
JAGUAR2_P(16, SI, TWI_SCL_M);
JAGUAR2_P(17, SI, TWI_SCL_M);
JAGUAR2_P(18, SI, TWI_SCL_M);
JAGUAR2_P(19, PCI_WAKE, NONE);
JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
JAGUAR2_P(22, TACHO, NONE);
JAGUAR2_P(23, PWM, NONE);
JAGUAR2_P(24, UART2, NONE);
JAGUAR2_P(25, UART2, SI);
JAGUAR2_P(26, PTP2, SI);
JAGUAR2_P(27, PTP3, SI);
JAGUAR2_P(28, TWI2, SI);
JAGUAR2_P(29, TWI2, SI);
JAGUAR2_P(30, SG2, SI);
JAGUAR2_P(31, SG2, SI);
JAGUAR2_P(32, SG2, SI);
JAGUAR2_P(33, SG2, SI);
JAGUAR2_P(34, NONE, TWI_SCL_M);
JAGUAR2_P(35, NONE, TWI_SCL_M);
JAGUAR2_P(36, NONE, TWI_SCL_M);
JAGUAR2_P(37, NONE, TWI_SCL_M);
JAGUAR2_P(38, NONE, TWI_SCL_M);
JAGUAR2_P(39, NONE, TWI_SCL_M);
JAGUAR2_P(40, NONE, TWI_SCL_M);
JAGUAR2_P(41, NONE, TWI_SCL_M);
JAGUAR2_P(42, NONE, TWI_SCL_M);
JAGUAR2_P(43, NONE, TWI_SCL_M);
JAGUAR2_P(44, NONE, SFP);
JAGUAR2_P(45, NONE, SFP);
JAGUAR2_P(46, NONE, SFP);
JAGUAR2_P(47, NONE, SFP);
JAGUAR2_P(48, SFP, NONE);
JAGUAR2_P(49, SFP, SI);
JAGUAR2_P(50, SFP, SI);
JAGUAR2_P(51, SFP, SI);
JAGUAR2_P(52, SFP, NONE);
JAGUAR2_P(53, SFP, NONE);
JAGUAR2_P(54, SFP, NONE);
JAGUAR2_P(55, SFP, NONE);
JAGUAR2_P(56, MIIM, SFP);
JAGUAR2_P(57, MIIM, SFP);
JAGUAR2_P(58, MIIM, SFP);
JAGUAR2_P(59, MIIM, SFP);
JAGUAR2_P(60, NONE, NONE);
JAGUAR2_P(61, NONE, NONE);
JAGUAR2_P(62, NONE, NONE);
JAGUAR2_P(63, NONE, NONE);
#define JAGUAR2_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &jaguar2_pin_##n \
}
static const struct pinctrl_pin_desc jaguar2_pins[] = {
JAGUAR2_PIN(0),
JAGUAR2_PIN(1),
JAGUAR2_PIN(2),
JAGUAR2_PIN(3),
JAGUAR2_PIN(4),
JAGUAR2_PIN(5),
JAGUAR2_PIN(6),
JAGUAR2_PIN(7),
JAGUAR2_PIN(8),
JAGUAR2_PIN(9),
JAGUAR2_PIN(10),
JAGUAR2_PIN(11),
JAGUAR2_PIN(12),
JAGUAR2_PIN(13),
JAGUAR2_PIN(14),
JAGUAR2_PIN(15),
JAGUAR2_PIN(16),
JAGUAR2_PIN(17),
JAGUAR2_PIN(18),
JAGUAR2_PIN(19),
JAGUAR2_PIN(20),
JAGUAR2_PIN(21),
JAGUAR2_PIN(22),
JAGUAR2_PIN(23),
JAGUAR2_PIN(24),
JAGUAR2_PIN(25),
JAGUAR2_PIN(26),
JAGUAR2_PIN(27),
JAGUAR2_PIN(28),
JAGUAR2_PIN(29),
JAGUAR2_PIN(30),
JAGUAR2_PIN(31),
JAGUAR2_PIN(32),
JAGUAR2_PIN(33),
JAGUAR2_PIN(34),
JAGUAR2_PIN(35),
JAGUAR2_PIN(36),
JAGUAR2_PIN(37),
JAGUAR2_PIN(38),
JAGUAR2_PIN(39),
JAGUAR2_PIN(40),
JAGUAR2_PIN(41),
JAGUAR2_PIN(42),
JAGUAR2_PIN(43),
JAGUAR2_PIN(44),
JAGUAR2_PIN(45),
JAGUAR2_PIN(46),
JAGUAR2_PIN(47),
JAGUAR2_PIN(48),
JAGUAR2_PIN(49),
JAGUAR2_PIN(50),
JAGUAR2_PIN(51),
JAGUAR2_PIN(52),
JAGUAR2_PIN(53),
JAGUAR2_PIN(54),
JAGUAR2_PIN(55),
JAGUAR2_PIN(56),
JAGUAR2_PIN(57),
JAGUAR2_PIN(58),
JAGUAR2_PIN(59),
JAGUAR2_PIN(60),
JAGUAR2_PIN(61),
JAGUAR2_PIN(62),
JAGUAR2_PIN(63),
};
#define SERVALT_P(p, f0, f1, f2) \
static struct ocelot_pin_caps servalt_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
}, \
}
SERVALT_P(0, SG0, NONE, NONE);
SERVALT_P(1, SG0, NONE, NONE);
SERVALT_P(2, SG0, NONE, NONE);
SERVALT_P(3, SG0, NONE, NONE);
SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
SERVALT_P(6, UART, NONE, NONE);
SERVALT_P(7, UART, NONE, NONE);
SERVALT_P(8, SI, SFP, TWI_SCL_M);
SERVALT_P(9, PCI_WAKE, SFP, SI);
SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
SERVALT_P(16, TACHO, SFP, SI);
SERVALT_P(17, PWM, NONE, TWI_SCL_M);
SERVALT_P(18, PTP2, SFP, SI);
SERVALT_P(19, PTP3, SFP, SI);
SERVALT_P(20, UART2, SFP, SI);
SERVALT_P(21, UART2, NONE, NONE);
SERVALT_P(22, MIIM, SFP, TWI2);
SERVALT_P(23, MIIM, SFP, TWI2);
SERVALT_P(24, TWI, NONE, NONE);
SERVALT_P(25, TWI, SFP, TWI_SCL_M);
SERVALT_P(26, TWI_SCL_M, SFP, SI);
SERVALT_P(27, TWI_SCL_M, SFP, SI);
SERVALT_P(28, TWI_SCL_M, SFP, SI);
SERVALT_P(29, TWI_SCL_M, NONE, NONE);
SERVALT_P(30, TWI_SCL_M, NONE, NONE);
SERVALT_P(31, TWI_SCL_M, NONE, NONE);
SERVALT_P(32, TWI_SCL_M, NONE, NONE);
SERVALT_P(33, RCVRD_CLK, NONE, NONE);
SERVALT_P(34, RCVRD_CLK, NONE, NONE);
SERVALT_P(35, RCVRD_CLK, NONE, NONE);
SERVALT_P(36, RCVRD_CLK, NONE, NONE);
#define SERVALT_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &servalt_pin_##n \
}
static const struct pinctrl_pin_desc servalt_pins[] = {
SERVALT_PIN(0),
SERVALT_PIN(1),
SERVALT_PIN(2),
SERVALT_PIN(3),
SERVALT_PIN(4),
SERVALT_PIN(5),
SERVALT_PIN(6),
SERVALT_PIN(7),
SERVALT_PIN(8),
SERVALT_PIN(9),
SERVALT_PIN(10),
SERVALT_PIN(11),
SERVALT_PIN(12),
SERVALT_PIN(13),
SERVALT_PIN(14),
SERVALT_PIN(15),
SERVALT_PIN(16),
SERVALT_PIN(17),
SERVALT_PIN(18),
SERVALT_PIN(19),
SERVALT_PIN(20),
SERVALT_PIN(21),
SERVALT_PIN(22),
SERVALT_PIN(23),
SERVALT_PIN(24),
SERVALT_PIN(25),
SERVALT_PIN(26),
SERVALT_PIN(27),
SERVALT_PIN(28),
SERVALT_PIN(29),
SERVALT_PIN(30),
SERVALT_PIN(31),
SERVALT_PIN(32),
SERVALT_PIN(33),
SERVALT_PIN(34),
SERVALT_PIN(35),
SERVALT_PIN(36),
};
#define SPARX5_P(p, f0, f1, f2) \
static struct ocelot_pin_caps sparx5_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
}, \
}
SPARX5_P(0, SG0, PLL_STAT, NONE);
SPARX5_P(1, SG0, NONE, NONE);
SPARX5_P(2, SG0, NONE, NONE);
SPARX5_P(3, SG0, NONE, NONE);
SPARX5_P(4, SG1, NONE, NONE);
SPARX5_P(5, SG1, NONE, NONE);
SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
SPARX5_P(8, PTP0, NONE, SFP);
SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
SPARX5_P(10, UART, NONE, NONE);
SPARX5_P(11, UART, NONE, NONE);
SPARX5_P(12, SG1, NONE, NONE);
SPARX5_P(13, SG1, NONE, NONE);
SPARX5_P(14, TWI, TWI_SCL_M, NONE);
SPARX5_P(15, TWI, NONE, NONE);
SPARX5_P(16, SI, TWI_SCL_M, SFP);
SPARX5_P(17, SI, TWI_SCL_M, SFP);
SPARX5_P(18, SI, TWI_SCL_M, SFP);
SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
SPARX5_P(23, PWM, UART3, TWI_SCL_M);
SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
SPARX5_P(25, PTP3, SI, TWI_SCL_M);
SPARX5_P(26, UART2, SI, TWI_SCL_M);
SPARX5_P(27, UART2, SI, TWI_SCL_M);
SPARX5_P(28, TWI2, SI, SFP);
SPARX5_P(29, TWI2, SI, SFP);
SPARX5_P(30, SG2, SI, PWM);
SPARX5_P(31, SG2, SI, TWI_SCL_M);
SPARX5_P(32, SG2, SI, TWI_SCL_M);
SPARX5_P(33, SG2, SI, SFP);
SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
SPARX5_P(37, SFP, NONE, EMMC);
SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
SPARX5_P(44, SI, SFP, EMMC);
SPARX5_P(45, SI, SFP, EMMC);
SPARX5_P(46, NONE, SFP, EMMC);
SPARX5_P(47, NONE, SFP, EMMC);
SPARX5_P(48, TWI3, SI, SFP);
SPARX5_P(49, TWI3, NONE, SFP);
SPARX5_P(50, SFP, NONE, TWI_SCL_M);
SPARX5_P(51, SFP, SI, TWI_SCL_M);
SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
SPARX5_P(55, SFP, PTP3, PCI_WAKE);
SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
SPARX5_P(59, MIIM, SFP, NONE);
SPARX5_P(60, RECO_CLK, NONE, NONE);
SPARX5_P(61, RECO_CLK, NONE, NONE);
SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
SPARX5_P(63, RECO_CLK, NONE, NONE);
#define SPARX5_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &sparx5_pin_##n \
}
static const struct pinctrl_pin_desc sparx5_pins[] = {
SPARX5_PIN(0),
SPARX5_PIN(1),
SPARX5_PIN(2),
SPARX5_PIN(3),
SPARX5_PIN(4),
SPARX5_PIN(5),
SPARX5_PIN(6),
SPARX5_PIN(7),
SPARX5_PIN(8),
SPARX5_PIN(9),
SPARX5_PIN(10),
SPARX5_PIN(11),
SPARX5_PIN(12),
SPARX5_PIN(13),
SPARX5_PIN(14),
SPARX5_PIN(15),
SPARX5_PIN(16),
SPARX5_PIN(17),
SPARX5_PIN(18),
SPARX5_PIN(19),
SPARX5_PIN(20),
SPARX5_PIN(21),
SPARX5_PIN(22),
SPARX5_PIN(23),
SPARX5_PIN(24),
SPARX5_PIN(25),
SPARX5_PIN(26),
SPARX5_PIN(27),
SPARX5_PIN(28),
SPARX5_PIN(29),
SPARX5_PIN(30),
SPARX5_PIN(31),
SPARX5_PIN(32),
SPARX5_PIN(33),
SPARX5_PIN(34),
SPARX5_PIN(35),
SPARX5_PIN(36),
SPARX5_PIN(37),
SPARX5_PIN(38),
SPARX5_PIN(39),
SPARX5_PIN(40),
SPARX5_PIN(41),
SPARX5_PIN(42),
SPARX5_PIN(43),
SPARX5_PIN(44),
SPARX5_PIN(45),
SPARX5_PIN(46),
SPARX5_PIN(47),
SPARX5_PIN(48),
SPARX5_PIN(49),
SPARX5_PIN(50),
SPARX5_PIN(51),
SPARX5_PIN(52),
SPARX5_PIN(53),
SPARX5_PIN(54),
SPARX5_PIN(55),
SPARX5_PIN(56),
SPARX5_PIN(57),
SPARX5_PIN(58),
SPARX5_PIN(59),
SPARX5_PIN(60),
SPARX5_PIN(61),
SPARX5_PIN(62),
SPARX5_PIN(63),
};
#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
static struct ocelot_pin_caps lan966x_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_##f0, FUNC_##f1, FUNC_##f2, \
FUNC_##f3 \
}, \
.a_functions = { \
FUNC_##f4, FUNC_##f5, FUNC_##f6, \
FUNC_##f7 \
}, \
}
/* Pinmuxing table taken from data sheet */
/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);
LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);
LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);
LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);
LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);
LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);
LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);
LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);
LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);
LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);
LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);
LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);
LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);
LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);
LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);
LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);
LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);
LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);
LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);
LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);
LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);
LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);
LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);
LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);
#define LAN966X_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &lan966x_pin_##n \
}
static const struct pinctrl_pin_desc lan966x_pins[] = {
LAN966X_PIN(0),
LAN966X_PIN(1),
LAN966X_PIN(2),
LAN966X_PIN(3),
LAN966X_PIN(4),
LAN966X_PIN(5),
LAN966X_PIN(6),
LAN966X_PIN(7),
LAN966X_PIN(8),
LAN966X_PIN(9),
LAN966X_PIN(10),
LAN966X_PIN(11),
LAN966X_PIN(12),
LAN966X_PIN(13),
LAN966X_PIN(14),
LAN966X_PIN(15),
LAN966X_PIN(16),
LAN966X_PIN(17),
LAN966X_PIN(18),
LAN966X_PIN(19),
LAN966X_PIN(20),
LAN966X_PIN(21),
LAN966X_PIN(22),
LAN966X_PIN(23),
LAN966X_PIN(24),
LAN966X_PIN(25),
LAN966X_PIN(26),
LAN966X_PIN(27),
LAN966X_PIN(28),
LAN966X_PIN(29),
LAN966X_PIN(30),
LAN966X_PIN(31),
LAN966X_PIN(32),
LAN966X_PIN(33),
LAN966X_PIN(34),
LAN966X_PIN(35),
LAN966X_PIN(36),
LAN966X_PIN(37),
LAN966X_PIN(38),
LAN966X_PIN(39),
LAN966X_PIN(40),
LAN966X_PIN(41),
LAN966X_PIN(42),
LAN966X_PIN(43),
LAN966X_PIN(44),
LAN966X_PIN(45),
LAN966X_PIN(46),
LAN966X_PIN(47),
LAN966X_PIN(48),
LAN966X_PIN(49),
LAN966X_PIN(50),
LAN966X_PIN(51),
LAN966X_PIN(52),
LAN966X_PIN(53),
LAN966X_PIN(54),
LAN966X_PIN(55),
LAN966X_PIN(56),
LAN966X_PIN(57),
LAN966X_PIN(58),
LAN966X_PIN(59),
LAN966X_PIN(60),
LAN966X_PIN(61),
LAN966X_PIN(62),
LAN966X_PIN(63),
LAN966X_PIN(64),
LAN966X_PIN(65),
LAN966X_PIN(66),
LAN966X_PIN(67),
LAN966X_PIN(68),
LAN966X_PIN(69),
LAN966X_PIN(70),
LAN966X_PIN(71),
LAN966X_PIN(72),
LAN966X_PIN(73),
LAN966X_PIN(74),
LAN966X_PIN(75),
LAN966X_PIN(76),
LAN966X_PIN(77),
};
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_function_names);
}
static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return ocelot_function_names[function];
}
static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char *const **groups,
unsigned *const num_groups)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*groups = info->func[function].groups;
*num_groups = info->func[function].ngroups;
return 0;
}
static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
unsigned int pin, unsigned int function)
{
struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
int i;
for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
if (function == p->functions[i])
return i;
if (function == p->a_functions[i])
return i + OCELOT_FUNC_PER_PIN;
}
return -1;
}
#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
unsigned int p = pin->pin % 32;
int f;
f = ocelot_pin_function_idx(info, group, selector);
if (f < 0)
return -EINVAL;
/*
* f is encoded on two bits.
* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
* ALT[1]
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
* Note: ALT0/ALT1 are organized specially for 64 gpio targets
*/
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
BIT(p), (f >> 1) << p);
return 0;
}
static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
unsigned int p = pin->pin % 32;
int f;
f = ocelot_pin_function_idx(info, group, selector);
if (f < 0)
return -EINVAL;
/*
* f is encoded on three bits.
* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
* ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
* This is racy because three registers can't be updated at the same time
* but it doesn't matter much for now.
* Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
*/
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
BIT(p), (f >> 1) << p);
regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
BIT(p), (f >> 2) << p);
return 0;
}
#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = pin % 32;
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
input ? 0 : BIT(p));
return 0;
}
static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = offset % 32;
regmap_update_bits(info->map, REG_ALT(0, info, offset),
BIT(p), 0);
regmap_update_bits(info->map, REG_ALT(1, info, offset),
BIT(p), 0);
return 0;
}
static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = offset % 32;
regmap_update_bits(info->map, REG_ALT(0, info, offset),
BIT(p), 0);
regmap_update_bits(info->map, REG_ALT(1, info, offset),
BIT(p), 0);
regmap_update_bits(info->map, REG_ALT(2, info, offset),
BIT(p), 0);
return 0;
}
static const struct pinmux_ops ocelot_pmx_ops = {
.get_functions_count = ocelot_get_functions_count,
.get_function_name = ocelot_get_function_name,
.get_function_groups = ocelot_get_function_groups,
.set_mux = ocelot_pinmux_set_mux,
.gpio_set_direction = ocelot_gpio_set_direction,
.gpio_request_enable = ocelot_gpio_request_enable,
};
static const struct pinmux_ops lan966x_pmx_ops = {
.get_functions_count = ocelot_get_functions_count,
.get_function_name = ocelot_get_function_name,
.get_function_groups = ocelot_get_function_groups,
.set_mux = lan966x_pinmux_set_mux,
.gpio_set_direction = ocelot_gpio_set_direction,
.gpio_request_enable = lan966x_gpio_request_enable,
};
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->npins;
}
static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->pins[group].name;
}
static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*pins = &info->desc->pins[group].number;
*num_pins = 1;
return 0;
}
static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
unsigned int pin,
unsigned int reg,
int *val)
{
int ret = -EOPNOTSUPP;
if (info->pincfg) {
const struct ocelot_pincfg_data *opd = info->pincfg_data;
u32 regcfg;
ret = regmap_read(info->pincfg,
pin * regmap_get_reg_stride(info->pincfg),
®cfg);
if (ret)
return ret;
ret = 0;
switch (reg) {
case PINCONF_BIAS:
*val = regcfg & (opd->pd_bit | opd->pu_bit);
break;
case PINCONF_SCHMITT:
*val = regcfg & opd->schmitt_bit;
break;
case PINCONF_DRIVE_STRENGTH:
*val = regcfg & opd->drive_bits;
break;
default:
ret = -EOPNOTSUPP;
break;
}
}
return ret;
}
static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
u32 clrbits, u32 setbits)
{
u32 val;
int ret;
ret = regmap_read(info->pincfg,
regaddr * regmap_get_reg_stride(info->pincfg),
&val);
if (ret)
return ret;
val &= ~clrbits;
val |= setbits;
ret = regmap_write(info->pincfg,
regaddr * regmap_get_reg_stride(info->pincfg),
val);
return ret;
}
static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
unsigned int pin,
unsigned int reg,
int val)
{
int ret = -EOPNOTSUPP;
if (info->pincfg) {
const struct ocelot_pincfg_data *opd = info->pincfg_data;
ret = 0;
switch (reg) {
case PINCONF_BIAS:
ret = ocelot_pincfg_clrsetbits(info, pin,
opd->pd_bit | opd->pu_bit,
val);
break;
case PINCONF_SCHMITT:
ret = ocelot_pincfg_clrsetbits(info, pin,
opd->schmitt_bit,
val);
break;
case PINCONF_DRIVE_STRENGTH:
if (val <= 3)
ret = ocelot_pincfg_clrsetbits(info, pin,
opd->drive_bits,
val);
else
ret = -EINVAL;
break;
default:
ret = -EOPNOTSUPP;
break;
}
}
return ret;
}
static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, err;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
if (err)
return err;
if (param == PIN_CONFIG_BIAS_DISABLE)
val = (val == 0);
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
val = !!(val & info->pincfg_data->pd_bit);
else /* PIN_CONFIG_BIAS_PULL_UP */
val = !!(val & info->pincfg_data->pu_bit);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!info->pincfg_data->schmitt_bit)
return -EOPNOTSUPP;
err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
if (err)
return err;
val = !!(val & info->pincfg_data->schmitt_bit);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
&val);
if (err)
return err;
break;
case PIN_CONFIG_OUTPUT:
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
&val);
if (err)
return err;
val = !!(val & BIT(pin % 32));
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
&val);
if (err)
return err;
val = val & BIT(pin % 32);
if (param == PIN_CONFIG_OUTPUT_ENABLE)
val = !!val;
else
val = !val;
break;
default:
return -EOPNOTSUPP;
}
*config = pinconf_to_config_packed(param, val);
return 0;
}
static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct ocelot_pincfg_data *opd = info->pincfg_data;
u32 param, arg, p;
int cfg, err = 0;
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
(param == PIN_CONFIG_BIAS_PULL_UP) ?
opd->pu_bit : opd->pd_bit;
err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!opd->schmitt_bit)
return -EOPNOTSUPP;
arg = arg ? opd->schmitt_bit : 0;
err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
err = ocelot_hw_set_value(info, pin,
PINCONF_DRIVE_STRENGTH,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT:
p = pin % 32;
if (arg)
regmap_write(info->map,
REG(OCELOT_GPIO_OUT_SET, info,
pin),
BIT(p));
else
regmap_write(info->map,
REG(OCELOT_GPIO_OUT_CLR, info,
pin),
BIT(p));
regmap_update_bits(info->map,
REG(OCELOT_GPIO_OE, info, pin),
BIT(p),
param == PIN_CONFIG_INPUT_ENABLE ?
0 : BIT(p));
break;
default:
err = -EOPNOTSUPP;
}
}
err:
return err;
}
static const struct pinconf_ops ocelot_confops = {
.is_generic = true,
.pin_config_get = ocelot_pinconf_get,
.pin_config_set = ocelot_pinconf_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static const struct pinctrl_ops ocelot_pctl_ops = {
.get_groups_count = ocelot_pctl_get_groups_count,
.get_group_name = ocelot_pctl_get_group_name,
.get_group_pins = ocelot_pctl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
};
static struct ocelot_match_data luton_desc = {
.desc = {
.name = "luton-pinctrl",
.pins = luton_pins,
.npins = ARRAY_SIZE(luton_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
},
};
static struct ocelot_match_data serval_desc = {
.desc = {
.name = "serval-pinctrl",
.pins = serval_pins,
.npins = ARRAY_SIZE(serval_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
},
};
static struct ocelot_match_data ocelot_desc = {
.desc = {
.name = "ocelot-pinctrl",
.pins = ocelot_pins,
.npins = ARRAY_SIZE(ocelot_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
},
};
static struct ocelot_match_data jaguar2_desc = {
.desc = {
.name = "jaguar2-pinctrl",
.pins = jaguar2_pins,
.npins = ARRAY_SIZE(jaguar2_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
},
};
static struct ocelot_match_data servalt_desc = {
.desc = {
.name = "servalt-pinctrl",
.pins = servalt_pins,
.npins = ARRAY_SIZE(servalt_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
},
};
static struct ocelot_match_data sparx5_desc = {
.desc = {
.name = "sparx5-pinctrl",
.pins = sparx5_pins,
.npins = ARRAY_SIZE(sparx5_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.confops = &ocelot_confops,
.owner = THIS_MODULE,
},
.pincfg_data = {
.pd_bit = BIT(4),
.pu_bit = BIT(3),
.drive_bits = GENMASK(1, 0),
.schmitt_bit = BIT(2),
},
};
static struct ocelot_match_data lan966x_desc = {
.desc = {
.name = "lan966x-pinctrl",
.pins = lan966x_pins,
.npins = ARRAY_SIZE(lan966x_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &lan966x_pmx_ops,
.confops = &ocelot_confops,
.owner = THIS_MODULE,
},
.pincfg_data = {
.pd_bit = BIT(3),
.pu_bit = BIT(2),
.drive_bits = GENMASK(1, 0),
},
};
static int ocelot_create_group_func_map(struct device *dev,
struct ocelot_pinctrl *info)
{
int f, npins, i;
u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (f = 0; f < FUNC_MAX; f++) {
for (npins = 0, i = 0; i < info->desc->npins; i++) {
if (ocelot_pin_function_idx(info, i, f) >= 0)
pins[npins++] = i;
}
if (!npins)
continue;
info->func[f].ngroups = npins;
info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
GFP_KERNEL);
if (!info->func[f].groups) {
kfree(pins);
return -ENOMEM;
}
for (i = 0; i < npins; i++)
info->func[f].groups[i] =
info->desc->pins[pins[i]].name;
}
kfree(pins);
return 0;
}
static int ocelot_pinctrl_register(struct platform_device *pdev,
struct ocelot_pinctrl *info)
{
int ret;
ret = ocelot_create_group_func_map(&pdev->dev, info);
if (ret) {
dev_err(&pdev->dev, "Unable to create group func map.\n");
return ret;
}
info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
if (IS_ERR(info->pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(info->pctl);
}
return 0;
}
static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
return !!(val & BIT(offset % 32));
}
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
if (value)
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
BIT(offset % 32));
else
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
BIT(offset % 32));
}
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
if (val & BIT(offset % 32))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int ocelot_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int ocelot_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int pin = BIT(offset % 32);
if (value)
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
pin);
else
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
pin);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static const struct gpio_chip ocelot_gpiolib_chip = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.set = ocelot_gpio_set,
.get = ocelot_gpio_get,
.get_direction = ocelot_gpio_get_direction,
.direction_input = ocelot_gpio_direction_input,
.direction_output = ocelot_gpio_direction_output,
.owner = THIS_MODULE,
};
static void ocelot_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
BIT(gpio % 32), 0);
gpiochip_disable_irq(chip, gpio);
}
static void ocelot_irq_work(struct work_struct *work)
{
struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work);
struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc);
struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc);
struct irq_data *data = irq_desc_get_irq_data(w->irq_desc);
unsigned int gpio = irqd_to_hwirq(data);
local_irq_disable();
chained_irq_enter(parent_chip, w->irq_desc);
generic_handle_domain_irq(chip->irq.domain, gpio);
chained_irq_exit(parent_chip, w->irq_desc);
local_irq_enable();
kfree(w);
}
static void ocelot_irq_unmask_level(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
struct irq_desc *desc = irq_data_to_desc(data);
unsigned int gpio = irqd_to_hwirq(data);
unsigned int bit = BIT(gpio % 32);
bool ack = false, active = false;
u8 trigger_level;
int val;
trigger_level = irqd_get_trigger_type(data);
/* Check if the interrupt line is still active. */
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
(val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
active = true;
/*
* Check if the interrupt controller has seen any changes in the
* interrupt line.
*/
regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val);
if (val & bit)
ack = true;
/* Try to clear any rising edges */
if (!active && ack)
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
bit, bit);
/* Enable the interrupt now */
gpiochip_enable_irq(chip, gpio);
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
bit, bit);
/*
* In case the interrupt line is still active then it means that
* there happen another interrupt while the line was active.
* So we missed that one, so we need to kick the interrupt again
* handler.
*/
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
(val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
active = true;
if (active) {
struct ocelot_irq_work *work;
work = kmalloc(sizeof(*work), GFP_ATOMIC);
if (!work)
return;
work->irq_desc = desc;
INIT_WORK(&work->irq_work, ocelot_irq_work);
queue_work(info->wq, &work->irq_work);
}
}
static void ocelot_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
gpiochip_enable_irq(chip, gpio);
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
BIT(gpio % 32), BIT(gpio % 32));
}
static void ocelot_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
BIT(gpio % 32), BIT(gpio % 32));
}
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
static struct irq_chip ocelot_level_irqchip = {
.name = "gpio",
.irq_mask = ocelot_irq_mask,
.irq_ack = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask_level,
.flags = IRQCHIP_IMMUTABLE,
.irq_set_type = ocelot_irq_set_type,
GPIOCHIP_IRQ_RESOURCE_HELPERS
};
static struct irq_chip ocelot_irqchip = {
.name = "gpio",
.irq_mask = ocelot_irq_mask,
.irq_ack = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask,
.irq_set_type = ocelot_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS
};
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
{
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip,
handle_level_irq, NULL);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
handle_edge_irq, NULL);
return 0;
}
static void ocelot_irq_handler(struct irq_desc *desc)
{
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
unsigned int reg = 0, irq, i;
unsigned long irqs;
for (i = 0; i < info->stride; i++) {
regmap_read(info->map, id_reg + 4 * i, ®);
if (!reg)
continue;
chained_irq_enter(parent_chip, desc);
irqs = reg;
for_each_set_bit(irq, &irqs,
min(32U, info->desc->npins - 32 * i))
generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
chained_irq_exit(parent_chip, desc);
}
}
static int ocelot_gpiochip_register(struct platform_device *pdev,
struct ocelot_pinctrl *info)
{
struct gpio_chip *gc;
struct gpio_irq_chip *girq;
int irq;
info->gpio_chip = ocelot_gpiolib_chip;
gc = &info->gpio_chip;
gc->ngpio = info->desc->npins;
gc->parent = &pdev->dev;
gc->base = -1;
gc->label = "ocelot-gpio";
irq = platform_get_irq_optional(pdev, 0);
if (irq > 0) {
girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &ocelot_irqchip);
girq->parent_handler = ocelot_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_edge_irq;
}
return devm_gpiochip_add_data(&pdev->dev, gc, info);
}
static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
{ .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
{ .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
{ .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
{},
};
MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,
const struct ocelot_pinctrl *info)
{
void __iomem *base;
const struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = info->desc->npins * 4,
.name = "pincfg",
};
base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(base)) {
dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
return NULL;
}
return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
}
static void ocelot_destroy_workqueue(void *data)
{
destroy_workqueue(data);
}
static int ocelot_pinctrl_probe(struct platform_device *pdev)
{
const struct ocelot_match_data *data;
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;
struct reset_control *reset;
struct regmap *pincfg;
int ret;
struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
data = device_get_match_data(dev);
if (!data)
return -EINVAL;
info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc),
GFP_KERNEL);
if (!info->desc)
return -ENOMEM;
info->wq = alloc_ordered_workqueue("ocelot_ordered", 0);
if (!info->wq)
return -ENOMEM;
ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue,
info->wq);
if (ret)
return ret;
info->pincfg_data = &data->pincfg_data;
reset = devm_reset_control_get_optional_shared(dev, "switch");
if (IS_ERR(reset))
return dev_err_probe(dev, PTR_ERR(reset),
"Failed to get reset\n");
reset_control_reset(reset);
info->stride = 1 + (info->desc->npins - 1) / 32;
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config);
if (IS_ERR(info->map))
return dev_err_probe(dev, PTR_ERR(info->map),
"Failed to create regmap\n");
dev_set_drvdata(dev, info);
info->dev = dev;
/* Pinconf registers */
if (info->desc->confops) {
pincfg = ocelot_pinctrl_create_pincfg(pdev, info);
if (IS_ERR(pincfg))
dev_dbg(dev, "Failed to create pincfg regmap\n");
else
info->pincfg = pincfg;
}
ret = ocelot_pinctrl_register(pdev, info);
if (ret)
return ret;
ret = ocelot_gpiochip_register(pdev, info);
if (ret)
return ret;
dev_info(dev, "driver registered\n");
return 0;
}
static struct platform_driver ocelot_pinctrl_driver = {
.driver = {
.name = "pinctrl-ocelot",
.of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = ocelot_pinctrl_probe,
};
module_platform_driver(ocelot_pinctrl_driver);
MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
MODULE_LICENSE("Dual MIT/GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-ocelot.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Bitmain BM1880 SoC Pinctrl driver
*
* Copyright (c) 2019 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
#define BM1880_REG_MUX 0x20
/**
* struct bm1880_pinctrl - driver data
* @base: Pinctrl base address
* @pctrldev: Pinctrl device
* @groups: Pingroups
* @ngroups: Number of @groups
* @funcs: Pinmux functions
* @nfuncs: Number of @funcs
* @pinconf: Pinconf data
*/
struct bm1880_pinctrl {
void __iomem *base;
struct pinctrl_dev *pctrldev;
const struct bm1880_pctrl_group *groups;
unsigned int ngroups;
const struct bm1880_pinmux_function *funcs;
unsigned int nfuncs;
const struct bm1880_pinconf_data *pinconf;
};
/**
* struct bm1880_pctrl_group - pinctrl group
* @name: Name of the group
* @pins: Array of pins belonging to this group
* @npins: Number of @pins
*/
struct bm1880_pctrl_group {
const char *name;
const unsigned int *pins;
const unsigned int npins;
};
/**
* struct bm1880_pinmux_function - a pinmux function
* @name: Name of the pinmux function.
* @groups: List of pingroups for this function.
* @ngroups: Number of entries in @groups.
* @mux_val: Selector for this function
* @mux: Offset of function specific mux
* @mux_shift: Shift for function specific selector
*/
struct bm1880_pinmux_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
u32 mux_val;
u32 mux;
u8 mux_shift;
};
/**
* struct bm1880_pinconf_data - pinconf data
* @drv_bits: Drive strength bit width
*/
struct bm1880_pinconf_data {
u32 drv_bits;
};
static const struct pinctrl_pin_desc bm1880_pins[] = {
PINCTRL_PIN(0, "MIO0"),
PINCTRL_PIN(1, "MIO1"),
PINCTRL_PIN(2, "MIO2"),
PINCTRL_PIN(3, "MIO3"),
PINCTRL_PIN(4, "MIO4"),
PINCTRL_PIN(5, "MIO5"),
PINCTRL_PIN(6, "MIO6"),
PINCTRL_PIN(7, "MIO7"),
PINCTRL_PIN(8, "MIO8"),
PINCTRL_PIN(9, "MIO9"),
PINCTRL_PIN(10, "MIO10"),
PINCTRL_PIN(11, "MIO11"),
PINCTRL_PIN(12, "MIO12"),
PINCTRL_PIN(13, "MIO13"),
PINCTRL_PIN(14, "MIO14"),
PINCTRL_PIN(15, "MIO15"),
PINCTRL_PIN(16, "MIO16"),
PINCTRL_PIN(17, "MIO17"),
PINCTRL_PIN(18, "MIO18"),
PINCTRL_PIN(19, "MIO19"),
PINCTRL_PIN(20, "MIO20"),
PINCTRL_PIN(21, "MIO21"),
PINCTRL_PIN(22, "MIO22"),
PINCTRL_PIN(23, "MIO23"),
PINCTRL_PIN(24, "MIO24"),
PINCTRL_PIN(25, "MIO25"),
PINCTRL_PIN(26, "MIO26"),
PINCTRL_PIN(27, "MIO27"),
PINCTRL_PIN(28, "MIO28"),
PINCTRL_PIN(29, "MIO29"),
PINCTRL_PIN(30, "MIO30"),
PINCTRL_PIN(31, "MIO31"),
PINCTRL_PIN(32, "MIO32"),
PINCTRL_PIN(33, "MIO33"),
PINCTRL_PIN(34, "MIO34"),
PINCTRL_PIN(35, "MIO35"),
PINCTRL_PIN(36, "MIO36"),
PINCTRL_PIN(37, "MIO37"),
PINCTRL_PIN(38, "MIO38"),
PINCTRL_PIN(39, "MIO39"),
PINCTRL_PIN(40, "MIO40"),
PINCTRL_PIN(41, "MIO41"),
PINCTRL_PIN(42, "MIO42"),
PINCTRL_PIN(43, "MIO43"),
PINCTRL_PIN(44, "MIO44"),
PINCTRL_PIN(45, "MIO45"),
PINCTRL_PIN(46, "MIO46"),
PINCTRL_PIN(47, "MIO47"),
PINCTRL_PIN(48, "MIO48"),
PINCTRL_PIN(49, "MIO49"),
PINCTRL_PIN(50, "MIO50"),
PINCTRL_PIN(51, "MIO51"),
PINCTRL_PIN(52, "MIO52"),
PINCTRL_PIN(53, "MIO53"),
PINCTRL_PIN(54, "MIO54"),
PINCTRL_PIN(55, "MIO55"),
PINCTRL_PIN(56, "MIO56"),
PINCTRL_PIN(57, "MIO57"),
PINCTRL_PIN(58, "MIO58"),
PINCTRL_PIN(59, "MIO59"),
PINCTRL_PIN(60, "MIO60"),
PINCTRL_PIN(61, "MIO61"),
PINCTRL_PIN(62, "MIO62"),
PINCTRL_PIN(63, "MIO63"),
PINCTRL_PIN(64, "MIO64"),
PINCTRL_PIN(65, "MIO65"),
PINCTRL_PIN(66, "MIO66"),
PINCTRL_PIN(67, "MIO67"),
PINCTRL_PIN(68, "MIO68"),
PINCTRL_PIN(69, "MIO69"),
PINCTRL_PIN(70, "MIO70"),
PINCTRL_PIN(71, "MIO71"),
PINCTRL_PIN(72, "MIO72"),
PINCTRL_PIN(73, "MIO73"),
PINCTRL_PIN(74, "MIO74"),
PINCTRL_PIN(75, "MIO75"),
PINCTRL_PIN(76, "MIO76"),
PINCTRL_PIN(77, "MIO77"),
PINCTRL_PIN(78, "MIO78"),
PINCTRL_PIN(79, "MIO79"),
PINCTRL_PIN(80, "MIO80"),
PINCTRL_PIN(81, "MIO81"),
PINCTRL_PIN(82, "MIO82"),
PINCTRL_PIN(83, "MIO83"),
PINCTRL_PIN(84, "MIO84"),
PINCTRL_PIN(85, "MIO85"),
PINCTRL_PIN(86, "MIO86"),
PINCTRL_PIN(87, "MIO87"),
PINCTRL_PIN(88, "MIO88"),
PINCTRL_PIN(89, "MIO89"),
PINCTRL_PIN(90, "MIO90"),
PINCTRL_PIN(91, "MIO91"),
PINCTRL_PIN(92, "MIO92"),
PINCTRL_PIN(93, "MIO93"),
PINCTRL_PIN(94, "MIO94"),
PINCTRL_PIN(95, "MIO95"),
PINCTRL_PIN(96, "MIO96"),
PINCTRL_PIN(97, "MIO97"),
PINCTRL_PIN(98, "MIO98"),
PINCTRL_PIN(99, "MIO99"),
PINCTRL_PIN(100, "MIO100"),
PINCTRL_PIN(101, "MIO101"),
PINCTRL_PIN(102, "MIO102"),
PINCTRL_PIN(103, "MIO103"),
PINCTRL_PIN(104, "MIO104"),
PINCTRL_PIN(105, "MIO105"),
PINCTRL_PIN(106, "MIO106"),
PINCTRL_PIN(107, "MIO107"),
PINCTRL_PIN(108, "MIO108"),
PINCTRL_PIN(109, "MIO109"),
PINCTRL_PIN(110, "MIO110"),
PINCTRL_PIN(111, "MIO111"),
};
enum bm1880_pinmux_functions {
F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
F_max
};
static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16 };
static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
25, 26 };
static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42 };
static const unsigned int pwm0_pins[] = { 29 };
static const unsigned int pwm1_pins[] = { 30 };
static const unsigned int pwm2_pins[] = { 34 };
static const unsigned int pwm3_pins[] = { 35 };
static const unsigned int pwm4_pins[] = { 43 };
static const unsigned int pwm5_pins[] = { 44 };
static const unsigned int pwm6_pins[] = { 45 };
static const unsigned int pwm7_pins[] = { 46 };
static const unsigned int pwm8_pins[] = { 47 };
static const unsigned int pwm9_pins[] = { 48 };
static const unsigned int pwm10_pins[] = { 49 };
static const unsigned int pwm11_pins[] = { 50 };
static const unsigned int pwm12_pins[] = { 51 };
static const unsigned int pwm13_pins[] = { 52 };
static const unsigned int pwm14_pins[] = { 53 };
static const unsigned int pwm15_pins[] = { 54 };
static const unsigned int pwm16_pins[] = { 55 };
static const unsigned int pwm17_pins[] = { 56 };
static const unsigned int pwm18_pins[] = { 57 };
static const unsigned int pwm19_pins[] = { 58 };
static const unsigned int pwm20_pins[] = { 59 };
static const unsigned int pwm21_pins[] = { 60 };
static const unsigned int pwm22_pins[] = { 61 };
static const unsigned int pwm23_pins[] = { 62 };
static const unsigned int pwm24_pins[] = { 97 };
static const unsigned int pwm25_pins[] = { 98 };
static const unsigned int pwm26_pins[] = { 99 };
static const unsigned int pwm27_pins[] = { 100 };
static const unsigned int pwm28_pins[] = { 101 };
static const unsigned int pwm29_pins[] = { 102 };
static const unsigned int pwm30_pins[] = { 103 };
static const unsigned int pwm31_pins[] = { 104 };
static const unsigned int pwm32_pins[] = { 105 };
static const unsigned int pwm33_pins[] = { 106 };
static const unsigned int pwm34_pins[] = { 107 };
static const unsigned int pwm35_pins[] = { 108 };
static const unsigned int pwm36_pins[] = { 109 };
static const unsigned int pwm37_pins[] = { 110 };
static const unsigned int i2c0_pins[] = { 63, 64 };
static const unsigned int i2c1_pins[] = { 65, 66 };
static const unsigned int i2c2_pins[] = { 67, 68 };
static const unsigned int i2c3_pins[] = { 69, 70 };
static const unsigned int i2c4_pins[] = { 71, 72 };
static const unsigned int uart0_pins[] = { 73, 74 };
static const unsigned int uart1_pins[] = { 75, 76 };
static const unsigned int uart2_pins[] = { 77, 78 };
static const unsigned int uart3_pins[] = { 79, 80 };
static const unsigned int uart4_pins[] = { 81, 82 };
static const unsigned int uart5_pins[] = { 83, 84 };
static const unsigned int uart6_pins[] = { 85, 86 };
static const unsigned int uart7_pins[] = { 87, 88 };
static const unsigned int uart8_pins[] = { 89, 90 };
static const unsigned int uart9_pins[] = { 91, 92 };
static const unsigned int uart10_pins[] = { 93, 94 };
static const unsigned int uart11_pins[] = { 95, 96 };
static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
static const unsigned int gpio0_pins[] = { 97 };
static const unsigned int gpio1_pins[] = { 98 };
static const unsigned int gpio2_pins[] = { 99 };
static const unsigned int gpio3_pins[] = { 100 };
static const unsigned int gpio4_pins[] = { 101 };
static const unsigned int gpio5_pins[] = { 102 };
static const unsigned int gpio6_pins[] = { 103 };
static const unsigned int gpio7_pins[] = { 104 };
static const unsigned int gpio8_pins[] = { 105 };
static const unsigned int gpio9_pins[] = { 106 };
static const unsigned int gpio10_pins[] = { 107 };
static const unsigned int gpio11_pins[] = { 108 };
static const unsigned int gpio12_pins[] = { 109 };
static const unsigned int gpio13_pins[] = { 110 };
static const unsigned int gpio14_pins[] = { 43 };
static const unsigned int gpio15_pins[] = { 44 };
static const unsigned int gpio16_pins[] = { 45 };
static const unsigned int gpio17_pins[] = { 46 };
static const unsigned int gpio18_pins[] = { 47 };
static const unsigned int gpio19_pins[] = { 48 };
static const unsigned int gpio20_pins[] = { 49 };
static const unsigned int gpio21_pins[] = { 50 };
static const unsigned int gpio22_pins[] = { 51 };
static const unsigned int gpio23_pins[] = { 52 };
static const unsigned int gpio24_pins[] = { 53 };
static const unsigned int gpio25_pins[] = { 54 };
static const unsigned int gpio26_pins[] = { 55 };
static const unsigned int gpio27_pins[] = { 56 };
static const unsigned int gpio28_pins[] = { 57 };
static const unsigned int gpio29_pins[] = { 58 };
static const unsigned int gpio30_pins[] = { 59 };
static const unsigned int gpio31_pins[] = { 60 };
static const unsigned int gpio32_pins[] = { 61 };
static const unsigned int gpio33_pins[] = { 62 };
static const unsigned int gpio34_pins[] = { 63 };
static const unsigned int gpio35_pins[] = { 64 };
static const unsigned int gpio36_pins[] = { 65 };
static const unsigned int gpio37_pins[] = { 66 };
static const unsigned int gpio38_pins[] = { 67 };
static const unsigned int gpio39_pins[] = { 68 };
static const unsigned int gpio40_pins[] = { 69 };
static const unsigned int gpio41_pins[] = { 70 };
static const unsigned int gpio42_pins[] = { 71 };
static const unsigned int gpio43_pins[] = { 72 };
static const unsigned int gpio44_pins[] = { 73 };
static const unsigned int gpio45_pins[] = { 74 };
static const unsigned int gpio46_pins[] = { 75 };
static const unsigned int gpio47_pins[] = { 76 };
static const unsigned int gpio48_pins[] = { 77 };
static const unsigned int gpio49_pins[] = { 78 };
static const unsigned int gpio50_pins[] = { 79 };
static const unsigned int gpio51_pins[] = { 80 };
static const unsigned int gpio52_pins[] = { 81 };
static const unsigned int gpio53_pins[] = { 82 };
static const unsigned int gpio54_pins[] = { 83 };
static const unsigned int gpio55_pins[] = { 84 };
static const unsigned int gpio56_pins[] = { 85 };
static const unsigned int gpio57_pins[] = { 86 };
static const unsigned int gpio58_pins[] = { 87 };
static const unsigned int gpio59_pins[] = { 88 };
static const unsigned int gpio60_pins[] = { 89 };
static const unsigned int gpio61_pins[] = { 90 };
static const unsigned int gpio62_pins[] = { 91 };
static const unsigned int gpio63_pins[] = { 92 };
static const unsigned int gpio64_pins[] = { 93 };
static const unsigned int gpio65_pins[] = { 94 };
static const unsigned int gpio66_pins[] = { 95 };
static const unsigned int gpio67_pins[] = { 96 };
static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58 };
static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
static const unsigned int i2s0_mclkin_pins[] = { 97 };
static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
static const unsigned int i2s1_mclkin_pins[] = { 98 };
static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
#define BM1880_PINCTRL_GRP(nm) \
{ \
.name = #nm "_grp", \
.pins = nm ## _pins, \
.npins = ARRAY_SIZE(nm ## _pins), \
}
static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
BM1880_PINCTRL_GRP(nand),
BM1880_PINCTRL_GRP(spi),
BM1880_PINCTRL_GRP(emmc),
BM1880_PINCTRL_GRP(sdio),
BM1880_PINCTRL_GRP(eth0),
BM1880_PINCTRL_GRP(pwm0),
BM1880_PINCTRL_GRP(pwm1),
BM1880_PINCTRL_GRP(pwm2),
BM1880_PINCTRL_GRP(pwm3),
BM1880_PINCTRL_GRP(pwm4),
BM1880_PINCTRL_GRP(pwm5),
BM1880_PINCTRL_GRP(pwm6),
BM1880_PINCTRL_GRP(pwm7),
BM1880_PINCTRL_GRP(pwm8),
BM1880_PINCTRL_GRP(pwm9),
BM1880_PINCTRL_GRP(pwm10),
BM1880_PINCTRL_GRP(pwm11),
BM1880_PINCTRL_GRP(pwm12),
BM1880_PINCTRL_GRP(pwm13),
BM1880_PINCTRL_GRP(pwm14),
BM1880_PINCTRL_GRP(pwm15),
BM1880_PINCTRL_GRP(pwm16),
BM1880_PINCTRL_GRP(pwm17),
BM1880_PINCTRL_GRP(pwm18),
BM1880_PINCTRL_GRP(pwm19),
BM1880_PINCTRL_GRP(pwm20),
BM1880_PINCTRL_GRP(pwm21),
BM1880_PINCTRL_GRP(pwm22),
BM1880_PINCTRL_GRP(pwm23),
BM1880_PINCTRL_GRP(pwm24),
BM1880_PINCTRL_GRP(pwm25),
BM1880_PINCTRL_GRP(pwm26),
BM1880_PINCTRL_GRP(pwm27),
BM1880_PINCTRL_GRP(pwm28),
BM1880_PINCTRL_GRP(pwm29),
BM1880_PINCTRL_GRP(pwm30),
BM1880_PINCTRL_GRP(pwm31),
BM1880_PINCTRL_GRP(pwm32),
BM1880_PINCTRL_GRP(pwm33),
BM1880_PINCTRL_GRP(pwm34),
BM1880_PINCTRL_GRP(pwm35),
BM1880_PINCTRL_GRP(pwm36),
BM1880_PINCTRL_GRP(pwm37),
BM1880_PINCTRL_GRP(i2c0),
BM1880_PINCTRL_GRP(i2c1),
BM1880_PINCTRL_GRP(i2c2),
BM1880_PINCTRL_GRP(i2c3),
BM1880_PINCTRL_GRP(i2c4),
BM1880_PINCTRL_GRP(uart0),
BM1880_PINCTRL_GRP(uart1),
BM1880_PINCTRL_GRP(uart2),
BM1880_PINCTRL_GRP(uart3),
BM1880_PINCTRL_GRP(uart4),
BM1880_PINCTRL_GRP(uart5),
BM1880_PINCTRL_GRP(uart6),
BM1880_PINCTRL_GRP(uart7),
BM1880_PINCTRL_GRP(uart8),
BM1880_PINCTRL_GRP(uart9),
BM1880_PINCTRL_GRP(uart10),
BM1880_PINCTRL_GRP(uart11),
BM1880_PINCTRL_GRP(uart12),
BM1880_PINCTRL_GRP(uart13),
BM1880_PINCTRL_GRP(uart14),
BM1880_PINCTRL_GRP(uart15),
BM1880_PINCTRL_GRP(gpio0),
BM1880_PINCTRL_GRP(gpio1),
BM1880_PINCTRL_GRP(gpio2),
BM1880_PINCTRL_GRP(gpio3),
BM1880_PINCTRL_GRP(gpio4),
BM1880_PINCTRL_GRP(gpio5),
BM1880_PINCTRL_GRP(gpio6),
BM1880_PINCTRL_GRP(gpio7),
BM1880_PINCTRL_GRP(gpio8),
BM1880_PINCTRL_GRP(gpio9),
BM1880_PINCTRL_GRP(gpio10),
BM1880_PINCTRL_GRP(gpio11),
BM1880_PINCTRL_GRP(gpio12),
BM1880_PINCTRL_GRP(gpio13),
BM1880_PINCTRL_GRP(gpio14),
BM1880_PINCTRL_GRP(gpio15),
BM1880_PINCTRL_GRP(gpio16),
BM1880_PINCTRL_GRP(gpio17),
BM1880_PINCTRL_GRP(gpio18),
BM1880_PINCTRL_GRP(gpio19),
BM1880_PINCTRL_GRP(gpio20),
BM1880_PINCTRL_GRP(gpio21),
BM1880_PINCTRL_GRP(gpio22),
BM1880_PINCTRL_GRP(gpio23),
BM1880_PINCTRL_GRP(gpio24),
BM1880_PINCTRL_GRP(gpio25),
BM1880_PINCTRL_GRP(gpio26),
BM1880_PINCTRL_GRP(gpio27),
BM1880_PINCTRL_GRP(gpio28),
BM1880_PINCTRL_GRP(gpio29),
BM1880_PINCTRL_GRP(gpio30),
BM1880_PINCTRL_GRP(gpio31),
BM1880_PINCTRL_GRP(gpio32),
BM1880_PINCTRL_GRP(gpio33),
BM1880_PINCTRL_GRP(gpio34),
BM1880_PINCTRL_GRP(gpio35),
BM1880_PINCTRL_GRP(gpio36),
BM1880_PINCTRL_GRP(gpio37),
BM1880_PINCTRL_GRP(gpio38),
BM1880_PINCTRL_GRP(gpio39),
BM1880_PINCTRL_GRP(gpio40),
BM1880_PINCTRL_GRP(gpio41),
BM1880_PINCTRL_GRP(gpio42),
BM1880_PINCTRL_GRP(gpio43),
BM1880_PINCTRL_GRP(gpio44),
BM1880_PINCTRL_GRP(gpio45),
BM1880_PINCTRL_GRP(gpio46),
BM1880_PINCTRL_GRP(gpio47),
BM1880_PINCTRL_GRP(gpio48),
BM1880_PINCTRL_GRP(gpio49),
BM1880_PINCTRL_GRP(gpio50),
BM1880_PINCTRL_GRP(gpio51),
BM1880_PINCTRL_GRP(gpio52),
BM1880_PINCTRL_GRP(gpio53),
BM1880_PINCTRL_GRP(gpio54),
BM1880_PINCTRL_GRP(gpio55),
BM1880_PINCTRL_GRP(gpio56),
BM1880_PINCTRL_GRP(gpio57),
BM1880_PINCTRL_GRP(gpio58),
BM1880_PINCTRL_GRP(gpio59),
BM1880_PINCTRL_GRP(gpio60),
BM1880_PINCTRL_GRP(gpio61),
BM1880_PINCTRL_GRP(gpio62),
BM1880_PINCTRL_GRP(gpio63),
BM1880_PINCTRL_GRP(gpio64),
BM1880_PINCTRL_GRP(gpio65),
BM1880_PINCTRL_GRP(gpio66),
BM1880_PINCTRL_GRP(gpio67),
BM1880_PINCTRL_GRP(eth1),
BM1880_PINCTRL_GRP(i2s0),
BM1880_PINCTRL_GRP(i2s0_mclkin),
BM1880_PINCTRL_GRP(i2s1),
BM1880_PINCTRL_GRP(i2s1_mclkin),
BM1880_PINCTRL_GRP(spi0),
};
static const char * const nand_group[] = { "nand_grp" };
static const char * const spi_group[] = { "spi_grp" };
static const char * const emmc_group[] = { "emmc_grp" };
static const char * const sdio_group[] = { "sdio_grp" };
static const char * const eth0_group[] = { "eth0_grp" };
static const char * const pwm0_group[] = { "pwm0_grp" };
static const char * const pwm1_group[] = { "pwm1_grp" };
static const char * const pwm2_group[] = { "pwm2_grp" };
static const char * const pwm3_group[] = { "pwm3_grp" };
static const char * const pwm4_group[] = { "pwm4_grp" };
static const char * const pwm5_group[] = { "pwm5_grp" };
static const char * const pwm6_group[] = { "pwm6_grp" };
static const char * const pwm7_group[] = { "pwm7_grp" };
static const char * const pwm8_group[] = { "pwm8_grp" };
static const char * const pwm9_group[] = { "pwm9_grp" };
static const char * const pwm10_group[] = { "pwm10_grp" };
static const char * const pwm11_group[] = { "pwm11_grp" };
static const char * const pwm12_group[] = { "pwm12_grp" };
static const char * const pwm13_group[] = { "pwm13_grp" };
static const char * const pwm14_group[] = { "pwm14_grp" };
static const char * const pwm15_group[] = { "pwm15_grp" };
static const char * const pwm16_group[] = { "pwm16_grp" };
static const char * const pwm17_group[] = { "pwm17_grp" };
static const char * const pwm18_group[] = { "pwm18_grp" };
static const char * const pwm19_group[] = { "pwm19_grp" };
static const char * const pwm20_group[] = { "pwm20_grp" };
static const char * const pwm21_group[] = { "pwm21_grp" };
static const char * const pwm22_group[] = { "pwm22_grp" };
static const char * const pwm23_group[] = { "pwm23_grp" };
static const char * const pwm24_group[] = { "pwm24_grp" };
static const char * const pwm25_group[] = { "pwm25_grp" };
static const char * const pwm26_group[] = { "pwm26_grp" };
static const char * const pwm27_group[] = { "pwm27_grp" };
static const char * const pwm28_group[] = { "pwm28_grp" };
static const char * const pwm29_group[] = { "pwm29_grp" };
static const char * const pwm30_group[] = { "pwm30_grp" };
static const char * const pwm31_group[] = { "pwm31_grp" };
static const char * const pwm32_group[] = { "pwm32_grp" };
static const char * const pwm33_group[] = { "pwm33_grp" };
static const char * const pwm34_group[] = { "pwm34_grp" };
static const char * const pwm35_group[] = { "pwm35_grp" };
static const char * const pwm36_group[] = { "pwm36_grp" };
static const char * const pwm37_group[] = { "pwm37_grp" };
static const char * const i2c0_group[] = { "i2c0_grp" };
static const char * const i2c1_group[] = { "i2c1_grp" };
static const char * const i2c2_group[] = { "i2c2_grp" };
static const char * const i2c3_group[] = { "i2c3_grp" };
static const char * const i2c4_group[] = { "i2c4_grp" };
static const char * const uart0_group[] = { "uart0_grp" };
static const char * const uart1_group[] = { "uart1_grp" };
static const char * const uart2_group[] = { "uart2_grp" };
static const char * const uart3_group[] = { "uart3_grp" };
static const char * const uart4_group[] = { "uart4_grp" };
static const char * const uart5_group[] = { "uart5_grp" };
static const char * const uart6_group[] = { "uart6_grp" };
static const char * const uart7_group[] = { "uart7_grp" };
static const char * const uart8_group[] = { "uart8_grp" };
static const char * const uart9_group[] = { "uart9_grp" };
static const char * const uart10_group[] = { "uart10_grp" };
static const char * const uart11_group[] = { "uart11_grp" };
static const char * const uart12_group[] = { "uart12_grp" };
static const char * const uart13_group[] = { "uart13_grp" };
static const char * const uart14_group[] = { "uart14_grp" };
static const char * const uart15_group[] = { "uart15_grp" };
static const char * const gpio0_group[] = { "gpio0_grp" };
static const char * const gpio1_group[] = { "gpio1_grp" };
static const char * const gpio2_group[] = { "gpio2_grp" };
static const char * const gpio3_group[] = { "gpio3_grp" };
static const char * const gpio4_group[] = { "gpio4_grp" };
static const char * const gpio5_group[] = { "gpio5_grp" };
static const char * const gpio6_group[] = { "gpio6_grp" };
static const char * const gpio7_group[] = { "gpio7_grp" };
static const char * const gpio8_group[] = { "gpio8_grp" };
static const char * const gpio9_group[] = { "gpio9_grp" };
static const char * const gpio10_group[] = { "gpio10_grp" };
static const char * const gpio11_group[] = { "gpio11_grp" };
static const char * const gpio12_group[] = { "gpio12_grp" };
static const char * const gpio13_group[] = { "gpio13_grp" };
static const char * const gpio14_group[] = { "gpio14_grp" };
static const char * const gpio15_group[] = { "gpio15_grp" };
static const char * const gpio16_group[] = { "gpio16_grp" };
static const char * const gpio17_group[] = { "gpio17_grp" };
static const char * const gpio18_group[] = { "gpio18_grp" };
static const char * const gpio19_group[] = { "gpio19_grp" };
static const char * const gpio20_group[] = { "gpio20_grp" };
static const char * const gpio21_group[] = { "gpio21_grp" };
static const char * const gpio22_group[] = { "gpio22_grp" };
static const char * const gpio23_group[] = { "gpio23_grp" };
static const char * const gpio24_group[] = { "gpio24_grp" };
static const char * const gpio25_group[] = { "gpio25_grp" };
static const char * const gpio26_group[] = { "gpio26_grp" };
static const char * const gpio27_group[] = { "gpio27_grp" };
static const char * const gpio28_group[] = { "gpio28_grp" };
static const char * const gpio29_group[] = { "gpio29_grp" };
static const char * const gpio30_group[] = { "gpio30_grp" };
static const char * const gpio31_group[] = { "gpio31_grp" };
static const char * const gpio32_group[] = { "gpio32_grp" };
static const char * const gpio33_group[] = { "gpio33_grp" };
static const char * const gpio34_group[] = { "gpio34_grp" };
static const char * const gpio35_group[] = { "gpio35_grp" };
static const char * const gpio36_group[] = { "gpio36_grp" };
static const char * const gpio37_group[] = { "gpio37_grp" };
static const char * const gpio38_group[] = { "gpio38_grp" };
static const char * const gpio39_group[] = { "gpio39_grp" };
static const char * const gpio40_group[] = { "gpio40_grp" };
static const char * const gpio41_group[] = { "gpio41_grp" };
static const char * const gpio42_group[] = { "gpio42_grp" };
static const char * const gpio43_group[] = { "gpio43_grp" };
static const char * const gpio44_group[] = { "gpio44_grp" };
static const char * const gpio45_group[] = { "gpio45_grp" };
static const char * const gpio46_group[] = { "gpio46_grp" };
static const char * const gpio47_group[] = { "gpio47_grp" };
static const char * const gpio48_group[] = { "gpio48_grp" };
static const char * const gpio49_group[] = { "gpio49_grp" };
static const char * const gpio50_group[] = { "gpio50_grp" };
static const char * const gpio51_group[] = { "gpio51_grp" };
static const char * const gpio52_group[] = { "gpio52_grp" };
static const char * const gpio53_group[] = { "gpio53_grp" };
static const char * const gpio54_group[] = { "gpio54_grp" };
static const char * const gpio55_group[] = { "gpio55_grp" };
static const char * const gpio56_group[] = { "gpio56_grp" };
static const char * const gpio57_group[] = { "gpio57_grp" };
static const char * const gpio58_group[] = { "gpio58_grp" };
static const char * const gpio59_group[] = { "gpio59_grp" };
static const char * const gpio60_group[] = { "gpio60_grp" };
static const char * const gpio61_group[] = { "gpio61_grp" };
static const char * const gpio62_group[] = { "gpio62_grp" };
static const char * const gpio63_group[] = { "gpio63_grp" };
static const char * const gpio64_group[] = { "gpio64_grp" };
static const char * const gpio65_group[] = { "gpio65_grp" };
static const char * const gpio66_group[] = { "gpio66_grp" };
static const char * const gpio67_group[] = { "gpio67_grp" };
static const char * const eth1_group[] = { "eth1_grp" };
static const char * const i2s0_group[] = { "i2s0_grp" };
static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
static const char * const i2s1_group[] = { "i2s1_grp" };
static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
static const char * const spi0_group[] = { "spi0_grp" };
#define BM1880_PINMUX_FUNCTION(fname, mval) \
[F_##fname] = { \
.name = #fname, \
.groups = fname##_group, \
.ngroups = ARRAY_SIZE(fname##_group), \
.mux_val = mval, \
}
static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
BM1880_PINMUX_FUNCTION(nand, 2),
BM1880_PINMUX_FUNCTION(spi, 0),
BM1880_PINMUX_FUNCTION(emmc, 1),
BM1880_PINMUX_FUNCTION(sdio, 0),
BM1880_PINMUX_FUNCTION(eth0, 0),
BM1880_PINMUX_FUNCTION(pwm0, 2),
BM1880_PINMUX_FUNCTION(pwm1, 2),
BM1880_PINMUX_FUNCTION(pwm2, 2),
BM1880_PINMUX_FUNCTION(pwm3, 2),
BM1880_PINMUX_FUNCTION(pwm4, 2),
BM1880_PINMUX_FUNCTION(pwm5, 2),
BM1880_PINMUX_FUNCTION(pwm6, 2),
BM1880_PINMUX_FUNCTION(pwm7, 2),
BM1880_PINMUX_FUNCTION(pwm8, 2),
BM1880_PINMUX_FUNCTION(pwm9, 2),
BM1880_PINMUX_FUNCTION(pwm10, 2),
BM1880_PINMUX_FUNCTION(pwm11, 2),
BM1880_PINMUX_FUNCTION(pwm12, 2),
BM1880_PINMUX_FUNCTION(pwm13, 2),
BM1880_PINMUX_FUNCTION(pwm14, 2),
BM1880_PINMUX_FUNCTION(pwm15, 2),
BM1880_PINMUX_FUNCTION(pwm16, 2),
BM1880_PINMUX_FUNCTION(pwm17, 2),
BM1880_PINMUX_FUNCTION(pwm18, 2),
BM1880_PINMUX_FUNCTION(pwm19, 2),
BM1880_PINMUX_FUNCTION(pwm20, 2),
BM1880_PINMUX_FUNCTION(pwm21, 2),
BM1880_PINMUX_FUNCTION(pwm22, 2),
BM1880_PINMUX_FUNCTION(pwm23, 2),
BM1880_PINMUX_FUNCTION(pwm24, 2),
BM1880_PINMUX_FUNCTION(pwm25, 2),
BM1880_PINMUX_FUNCTION(pwm26, 2),
BM1880_PINMUX_FUNCTION(pwm27, 2),
BM1880_PINMUX_FUNCTION(pwm28, 2),
BM1880_PINMUX_FUNCTION(pwm29, 2),
BM1880_PINMUX_FUNCTION(pwm30, 2),
BM1880_PINMUX_FUNCTION(pwm31, 2),
BM1880_PINMUX_FUNCTION(pwm32, 2),
BM1880_PINMUX_FUNCTION(pwm33, 2),
BM1880_PINMUX_FUNCTION(pwm34, 2),
BM1880_PINMUX_FUNCTION(pwm35, 2),
BM1880_PINMUX_FUNCTION(pwm36, 2),
BM1880_PINMUX_FUNCTION(pwm37, 2),
BM1880_PINMUX_FUNCTION(i2c0, 1),
BM1880_PINMUX_FUNCTION(i2c1, 1),
BM1880_PINMUX_FUNCTION(i2c2, 1),
BM1880_PINMUX_FUNCTION(i2c3, 1),
BM1880_PINMUX_FUNCTION(i2c4, 1),
BM1880_PINMUX_FUNCTION(uart0, 3),
BM1880_PINMUX_FUNCTION(uart1, 3),
BM1880_PINMUX_FUNCTION(uart2, 3),
BM1880_PINMUX_FUNCTION(uart3, 3),
BM1880_PINMUX_FUNCTION(uart4, 1),
BM1880_PINMUX_FUNCTION(uart5, 1),
BM1880_PINMUX_FUNCTION(uart6, 1),
BM1880_PINMUX_FUNCTION(uart7, 1),
BM1880_PINMUX_FUNCTION(uart8, 1),
BM1880_PINMUX_FUNCTION(uart9, 1),
BM1880_PINMUX_FUNCTION(uart10, 1),
BM1880_PINMUX_FUNCTION(uart11, 1),
BM1880_PINMUX_FUNCTION(uart12, 3),
BM1880_PINMUX_FUNCTION(uart13, 3),
BM1880_PINMUX_FUNCTION(uart14, 3),
BM1880_PINMUX_FUNCTION(uart15, 3),
BM1880_PINMUX_FUNCTION(gpio0, 0),
BM1880_PINMUX_FUNCTION(gpio1, 0),
BM1880_PINMUX_FUNCTION(gpio2, 0),
BM1880_PINMUX_FUNCTION(gpio3, 0),
BM1880_PINMUX_FUNCTION(gpio4, 0),
BM1880_PINMUX_FUNCTION(gpio5, 0),
BM1880_PINMUX_FUNCTION(gpio6, 0),
BM1880_PINMUX_FUNCTION(gpio7, 0),
BM1880_PINMUX_FUNCTION(gpio8, 0),
BM1880_PINMUX_FUNCTION(gpio9, 0),
BM1880_PINMUX_FUNCTION(gpio10, 0),
BM1880_PINMUX_FUNCTION(gpio11, 0),
BM1880_PINMUX_FUNCTION(gpio12, 1),
BM1880_PINMUX_FUNCTION(gpio13, 1),
BM1880_PINMUX_FUNCTION(gpio14, 0),
BM1880_PINMUX_FUNCTION(gpio15, 0),
BM1880_PINMUX_FUNCTION(gpio16, 0),
BM1880_PINMUX_FUNCTION(gpio17, 0),
BM1880_PINMUX_FUNCTION(gpio18, 0),
BM1880_PINMUX_FUNCTION(gpio19, 0),
BM1880_PINMUX_FUNCTION(gpio20, 0),
BM1880_PINMUX_FUNCTION(gpio21, 0),
BM1880_PINMUX_FUNCTION(gpio22, 0),
BM1880_PINMUX_FUNCTION(gpio23, 0),
BM1880_PINMUX_FUNCTION(gpio24, 0),
BM1880_PINMUX_FUNCTION(gpio25, 0),
BM1880_PINMUX_FUNCTION(gpio26, 0),
BM1880_PINMUX_FUNCTION(gpio27, 0),
BM1880_PINMUX_FUNCTION(gpio28, 0),
BM1880_PINMUX_FUNCTION(gpio29, 0),
BM1880_PINMUX_FUNCTION(gpio30, 0),
BM1880_PINMUX_FUNCTION(gpio31, 0),
BM1880_PINMUX_FUNCTION(gpio32, 0),
BM1880_PINMUX_FUNCTION(gpio33, 0),
BM1880_PINMUX_FUNCTION(gpio34, 0),
BM1880_PINMUX_FUNCTION(gpio35, 0),
BM1880_PINMUX_FUNCTION(gpio36, 0),
BM1880_PINMUX_FUNCTION(gpio37, 0),
BM1880_PINMUX_FUNCTION(gpio38, 0),
BM1880_PINMUX_FUNCTION(gpio39, 0),
BM1880_PINMUX_FUNCTION(gpio40, 0),
BM1880_PINMUX_FUNCTION(gpio41, 0),
BM1880_PINMUX_FUNCTION(gpio42, 0),
BM1880_PINMUX_FUNCTION(gpio43, 0),
BM1880_PINMUX_FUNCTION(gpio44, 0),
BM1880_PINMUX_FUNCTION(gpio45, 0),
BM1880_PINMUX_FUNCTION(gpio46, 0),
BM1880_PINMUX_FUNCTION(gpio47, 0),
BM1880_PINMUX_FUNCTION(gpio48, 0),
BM1880_PINMUX_FUNCTION(gpio49, 0),
BM1880_PINMUX_FUNCTION(gpio50, 0),
BM1880_PINMUX_FUNCTION(gpio51, 0),
BM1880_PINMUX_FUNCTION(gpio52, 0),
BM1880_PINMUX_FUNCTION(gpio53, 0),
BM1880_PINMUX_FUNCTION(gpio54, 0),
BM1880_PINMUX_FUNCTION(gpio55, 0),
BM1880_PINMUX_FUNCTION(gpio56, 0),
BM1880_PINMUX_FUNCTION(gpio57, 0),
BM1880_PINMUX_FUNCTION(gpio58, 0),
BM1880_PINMUX_FUNCTION(gpio59, 0),
BM1880_PINMUX_FUNCTION(gpio60, 0),
BM1880_PINMUX_FUNCTION(gpio61, 0),
BM1880_PINMUX_FUNCTION(gpio62, 0),
BM1880_PINMUX_FUNCTION(gpio63, 0),
BM1880_PINMUX_FUNCTION(gpio64, 0),
BM1880_PINMUX_FUNCTION(gpio65, 0),
BM1880_PINMUX_FUNCTION(gpio66, 0),
BM1880_PINMUX_FUNCTION(gpio67, 0),
BM1880_PINMUX_FUNCTION(eth1, 1),
BM1880_PINMUX_FUNCTION(i2s0, 2),
BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1),
BM1880_PINMUX_FUNCTION(i2s1, 2),
BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1),
BM1880_PINMUX_FUNCTION(spi0, 1),
};
#define BM1880_PINCONF_DAT(_width) \
{ \
.drv_bits = _width, \
}
static const struct bm1880_pinconf_data bm1880_pinconf[] = {
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x03),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
BM1880_PINCONF_DAT(0x02),
};
static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->ngroups;
}
static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->groups[selector].name;
}
static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->groups[selector].pins;
*num_pins = pctrl->groups[selector].npins;
return 0;
}
static const struct pinctrl_ops bm1880_pctrl_ops = {
.get_groups_count = bm1880_pctrl_get_groups_count,
.get_group_name = bm1880_pctrl_get_group_name,
.get_group_pins = bm1880_pctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
/* pinmux */
static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->nfuncs;
}
static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->funcs[selector].name;
}
static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->funcs[selector].groups;
*num_groups = pctrl->funcs[selector].ngroups;
return 0;
}
static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
int i;
for (i = 0; i < pgrp->npins; i++) {
unsigned int pin = pgrp->pins[i];
u32 offset = (pin >> 1) << 2;
u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
offset);
regval &= ~(0x03 << mux_offset);
regval |= func->mux_val << mux_offset;
writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
}
return 0;
}
#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx)
#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0)
#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1)
#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2)
#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6)
#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9)
#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10)
static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
u32 *regval, u32 bit_offset)
{
u32 _regval;
_regval = *regval;
/*
* There are two sets of drive strength bit width exposed by the
* SoC at 4mA step, hence we need to handle them separately.
*/
if (width == 0x03) {
switch (mA) {
case 4:
_regval &= ~(width << bit_offset);
_regval |= (0 << bit_offset);
break;
case 8:
_regval &= ~(width << bit_offset);
_regval |= (1 << bit_offset);
break;
case 12:
_regval &= ~(width << bit_offset);
_regval |= (2 << bit_offset);
break;
case 16:
_regval &= ~(width << bit_offset);
_regval |= (3 << bit_offset);
break;
case 20:
_regval &= ~(width << bit_offset);
_regval |= (4 << bit_offset);
break;
case 24:
_regval &= ~(width << bit_offset);
_regval |= (5 << bit_offset);
break;
case 28:
_regval &= ~(width << bit_offset);
_regval |= (6 << bit_offset);
break;
case 32:
_regval &= ~(width << bit_offset);
_regval |= (7 << bit_offset);
break;
default:
return -EINVAL;
}
} else {
switch (mA) {
case 4:
_regval &= ~(width << bit_offset);
_regval |= (0 << bit_offset);
break;
case 8:
_regval &= ~(width << bit_offset);
_regval |= (1 << bit_offset);
break;
case 12:
_regval &= ~(width << bit_offset);
_regval |= (2 << bit_offset);
break;
case 16:
_regval &= ~(width << bit_offset);
_regval |= (3 << bit_offset);
break;
default:
return -EINVAL;
}
}
*regval = _regval;
return 0;
}
static int bm1880_pinconf_drv_get(u32 width, u32 drv)
{
int ret = -ENOTSUPP;
/*
* There are two sets of drive strength bit width exposed by the
* SoC at 4mA step, hence we need to handle them separately.
*/
if (width == 0x03) {
switch (drv) {
case 0:
ret = 4;
break;
case 1:
ret = 8;
break;
case 2:
ret = 12;
break;
case 3:
ret = 16;
break;
case 4:
ret = 20;
break;
case 5:
ret = 24;
break;
case 6:
ret = 28;
break;
case 7:
ret = 32;
break;
default:
break;
}
} else {
switch (drv) {
case 0:
ret = 4;
break;
case 1:
ret = 8;
break;
case 2:
ret = 12;
break;
case 3:
ret = 16;
break;
default:
break;
}
}
return ret;
}
static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *config)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
unsigned int arg = 0;
u32 regval, offset, bit_offset;
int ret;
offset = (pin >> 1) << 2;
regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
bit_offset = BM1880_PINCONF_PULLUP(pin);
arg = !!(regval & BIT(bit_offset));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bit_offset = BM1880_PINCONF_PULLDOWN(pin);
arg = !!(regval & BIT(bit_offset));
break;
case PIN_CONFIG_BIAS_DISABLE:
bit_offset = BM1880_PINCONF_PULLCTRL(pin);
arg = !!(regval & BIT(bit_offset));
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
bit_offset = BM1880_PINCONF_SCHMITT(pin);
arg = !!(regval & BIT(bit_offset));
break;
case PIN_CONFIG_SLEW_RATE:
bit_offset = BM1880_PINCONF_SLEW(pin);
arg = !!(regval & BIT(bit_offset));
break;
case PIN_CONFIG_DRIVE_STRENGTH:
bit_offset = BM1880_PINCONF_DRV(pin);
ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
!!(regval & BIT(bit_offset)));
if (ret < 0)
return ret;
arg = ret;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *configs,
unsigned int num_configs)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
u32 regval, offset, bit_offset;
int i, ret;
offset = (pin >> 1) << 2;
regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
bit_offset = BM1880_PINCONF_PULLUP(pin);
regval |= BIT(bit_offset);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bit_offset = BM1880_PINCONF_PULLDOWN(pin);
regval |= BIT(bit_offset);
break;
case PIN_CONFIG_BIAS_DISABLE:
bit_offset = BM1880_PINCONF_PULLCTRL(pin);
regval |= BIT(bit_offset);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
bit_offset = BM1880_PINCONF_SCHMITT(pin);
if (arg)
regval |= BIT(bit_offset);
else
regval &= ~BIT(bit_offset);
break;
case PIN_CONFIG_SLEW_RATE:
bit_offset = BM1880_PINCONF_SLEW(pin);
if (arg)
regval |= BIT(bit_offset);
else
regval &= ~BIT(bit_offset);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
bit_offset = BM1880_PINCONF_DRV(pin);
ret = bm1880_pinconf_drv_set(arg,
pctrl->pinconf[pin].drv_bits,
®val, bit_offset);
if (ret < 0)
return ret;
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter '%u'\n",
param);
continue;
}
writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset);
}
return 0;
}
static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector];
for (i = 0; i < pgrp->npins; i++) {
ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops bm1880_pinconf_ops = {
.is_generic = true,
.pin_config_get = bm1880_pinconf_cfg_get,
.pin_config_set = bm1880_pinconf_cfg_set,
.pin_config_group_set = bm1880_pinconf_group_set,
};
static const struct pinmux_ops bm1880_pinmux_ops = {
.get_functions_count = bm1880_pmux_get_functions_count,
.get_function_name = bm1880_pmux_get_function_name,
.get_function_groups = bm1880_pmux_get_function_groups,
.set_mux = bm1880_pinmux_set_mux,
};
static struct pinctrl_desc bm1880_desc = {
.name = "bm1880_pinctrl",
.pins = bm1880_pins,
.npins = ARRAY_SIZE(bm1880_pins),
.pctlops = &bm1880_pctrl_ops,
.pmxops = &bm1880_pinmux_ops,
.confops = &bm1880_pinconf_ops,
.owner = THIS_MODULE,
};
static int bm1880_pinctrl_probe(struct platform_device *pdev)
{
struct bm1880_pinctrl *pctrl;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);
pctrl->groups = bm1880_pctrl_groups;
pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
pctrl->funcs = bm1880_pmux_functions;
pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
pctrl->pinconf = bm1880_pinconf;
pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
pctrl);
if (IS_ERR(pctrl->pctrldev))
return PTR_ERR(pctrl->pctrldev);
platform_set_drvdata(pdev, pctrl);
dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
return 0;
}
static const struct of_device_id bm1880_pinctrl_of_match[] = {
{ .compatible = "bitmain,bm1880-pinctrl" },
{ }
};
static struct platform_driver bm1880_pinctrl_driver = {
.driver = {
.name = "pinctrl-bm1880",
.of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
},
.probe = bm1880_pinctrl_probe,
};
static int __init bm1880_pinctrl_init(void)
{
return platform_driver_register(&bm1880_pinctrl_driver);
}
arch_initcall(bm1880_pinctrl_init);
|
linux-master
|
drivers/pinctrl/pinctrl-bm1880.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for the pin control subsystem
*
* Copyright (C) 2011-2012 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
* Based on bits of regulator core, gpio core and clk core
*
* Author: Linus Walleij <[email protected]>
*
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
*/
#define pr_fmt(fmt) "pinctrl core: " fmt
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/devinfo.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#ifdef CONFIG_GPIOLIB
#include "../gpio/gpiolib.h"
#endif
#include "core.h"
#include "devicetree.h"
#include "pinconf.h"
#include "pinmux.h"
static bool pinctrl_dummy_state;
/* Mutex taken to protect pinctrl_list */
static DEFINE_MUTEX(pinctrl_list_mutex);
/* Mutex taken to protect pinctrl_maps */
DEFINE_MUTEX(pinctrl_maps_mutex);
/* Mutex taken to protect pinctrldev_list */
static DEFINE_MUTEX(pinctrldev_list_mutex);
/* Global list of pin control devices (struct pinctrl_dev) */
static LIST_HEAD(pinctrldev_list);
/* List of pin controller handles (struct pinctrl) */
static LIST_HEAD(pinctrl_list);
/* List of pinctrl maps (struct pinctrl_maps) */
LIST_HEAD(pinctrl_maps);
/**
* pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
*
* Usually this function is called by platforms without pinctrl driver support
* but run with some shared drivers using pinctrl APIs.
* After calling this function, the pinctrl core will return successfully
* with creating a dummy state for the driver to keep going smoothly.
*/
void pinctrl_provide_dummies(void)
{
pinctrl_dummy_state = true;
}
const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
{
/* We're not allowed to register devices without name */
return pctldev->desc->name;
}
EXPORT_SYMBOL_GPL(pinctrl_dev_get_name);
const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev)
{
return dev_name(pctldev->dev);
}
EXPORT_SYMBOL_GPL(pinctrl_dev_get_devname);
void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev)
{
return pctldev->driver_data;
}
EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata);
/**
* get_pinctrl_dev_from_devname() - look up pin controller device
* @devname: the name of a device instance, as returned by dev_name()
*
* Looks up a pin control device matching a certain device name or pure device
* pointer, the pure device pointer will take precedence.
*/
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname)
{
struct pinctrl_dev *pctldev;
if (!devname)
return NULL;
mutex_lock(&pinctrldev_list_mutex);
list_for_each_entry(pctldev, &pinctrldev_list, node) {
if (!strcmp(dev_name(pctldev->dev), devname)) {
/* Matched on device name */
mutex_unlock(&pinctrldev_list_mutex);
return pctldev;
}
}
mutex_unlock(&pinctrldev_list_mutex);
return NULL;
}
struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np)
{
struct pinctrl_dev *pctldev;
mutex_lock(&pinctrldev_list_mutex);
list_for_each_entry(pctldev, &pinctrldev_list, node)
if (device_match_of_node(pctldev->dev, np)) {
mutex_unlock(&pinctrldev_list_mutex);
return pctldev;
}
mutex_unlock(&pinctrldev_list_mutex);
return NULL;
}
/**
* pin_get_from_name() - look up a pin number from a name
* @pctldev: the pin control device to lookup the pin on
* @name: the name of the pin to look up
*/
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
{
unsigned i, pin;
/* The pin number can be retrived from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Pin space may be sparse */
if (desc && !strcmp(name, desc->name))
return pin;
}
return -EINVAL;
}
/**
* pin_get_name() - look up a pin name from a pin id
* @pctldev: the pin control device to lookup the pin on
* @pin: pin number/id to look up
*/
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
{
const struct pin_desc *desc;
desc = pin_desc_get(pctldev, pin);
if (!desc) {
dev_err(pctldev->dev, "failed to get pin(%d) name\n",
pin);
return NULL;
}
return desc->name;
}
EXPORT_SYMBOL_GPL(pin_get_name);
/* Deletes a range of pin descriptors */
static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
const struct pinctrl_pin_desc *pins,
unsigned num_pins)
{
int i;
for (i = 0; i < num_pins; i++) {
struct pin_desc *pindesc;
pindesc = radix_tree_lookup(&pctldev->pin_desc_tree,
pins[i].number);
if (pindesc) {
radix_tree_delete(&pctldev->pin_desc_tree,
pins[i].number);
if (pindesc->dynamic_name)
kfree(pindesc->name);
}
kfree(pindesc);
}
}
static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
const struct pinctrl_pin_desc *pin)
{
struct pin_desc *pindesc;
int error;
pindesc = pin_desc_get(pctldev, pin->number);
if (pindesc) {
dev_err(pctldev->dev, "pin %d already registered\n",
pin->number);
return -EINVAL;
}
pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL);
if (!pindesc)
return -ENOMEM;
/* Set owner */
pindesc->pctldev = pctldev;
/* Copy basic pin info */
if (pin->name) {
pindesc->name = pin->name;
} else {
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number);
if (!pindesc->name) {
error = -ENOMEM;
goto failed;
}
pindesc->dynamic_name = true;
}
pindesc->drv_data = pin->drv_data;
error = radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc);
if (error)
goto failed;
pr_debug("registered pin %d (%s) on %s\n",
pin->number, pindesc->name, pctldev->desc->name);
return 0;
failed:
kfree(pindesc);
return error;
}
static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
const struct pinctrl_pin_desc *pins,
unsigned num_descs)
{
unsigned i;
int ret = 0;
for (i = 0; i < num_descs; i++) {
ret = pinctrl_register_one_pin(pctldev, &pins[i]);
if (ret)
return ret;
}
return 0;
}
/**
* gpio_to_pin() - GPIO range GPIO number to pin number translation
* @range: GPIO range used for the translation
* @gpio: gpio pin to translate to a pin number
*
* Finds the pin number for a given GPIO using the specified GPIO range
* as a base for translation. The distinction between linear GPIO ranges
* and pin list based GPIO ranges is managed correctly by this function.
*
* This function assumes the gpio is part of the specified GPIO range, use
* only after making sure this is the case (e.g. by calling it on the
* result of successful pinctrl_get_device_gpio_range calls)!
*/
static inline int gpio_to_pin(struct pinctrl_gpio_range *range,
unsigned int gpio)
{
unsigned int offset = gpio - range->base;
if (range->pins)
return range->pins[offset];
else
return range->pin_base + offset;
}
/**
* pinctrl_match_gpio_range() - check if a certain GPIO pin is in range
* @pctldev: pin controller device to check
* @gpio: gpio pin to check taken from the global GPIO pin space
*
* Tries to match a GPIO pin number to the ranges handled by a certain pin
* controller, return the range or NULL
*/
static struct pinctrl_gpio_range *
pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
{
struct pinctrl_gpio_range *range;
mutex_lock(&pctldev->mutex);
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
if (gpio >= range->base &&
gpio < range->base + range->npins) {
mutex_unlock(&pctldev->mutex);
return range;
}
}
mutex_unlock(&pctldev->mutex);
return NULL;
}
/**
* pinctrl_ready_for_gpio_range() - check if other GPIO pins of
* the same GPIO chip are in range
* @gpio: gpio pin to check taken from the global GPIO pin space
*
* This function is complement of pinctrl_match_gpio_range(). If the return
* value of pinctrl_match_gpio_range() is NULL, this function could be used
* to check whether pinctrl device is ready or not. Maybe some GPIO pins
* of the same GPIO chip don't have back-end pinctrl interface.
* If the return value is true, it means that pinctrl device is ready & the
* certain GPIO pin doesn't have back-end pinctrl device. If the return value
* is false, it means that pinctrl device may not be ready.
*/
#ifdef CONFIG_GPIOLIB
static bool pinctrl_ready_for_gpio_range(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range = NULL;
/*
* FIXME: "gpio" here is a number in the global GPIO numberspace.
* get rid of this from the ranges eventually and get the GPIO
* descriptor from the gpio_chip.
*/
struct gpio_chip *chip = gpiod_to_chip(gpio_to_desc(gpio));
if (WARN(!chip, "no gpio_chip for gpio%i?", gpio))
return false;
mutex_lock(&pinctrldev_list_mutex);
/* Loop over the pin controllers */
list_for_each_entry(pctldev, &pinctrldev_list, node) {
/* Loop over the ranges */
mutex_lock(&pctldev->mutex);
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if any gpio range overlapped with gpio chip */
if (range->base + range->npins - 1 < chip->base ||
range->base > chip->base + chip->ngpio - 1)
continue;
mutex_unlock(&pctldev->mutex);
mutex_unlock(&pinctrldev_list_mutex);
return true;
}
mutex_unlock(&pctldev->mutex);
}
mutex_unlock(&pinctrldev_list_mutex);
return false;
}
#else
static bool pinctrl_ready_for_gpio_range(unsigned gpio) { return true; }
#endif
/**
* pinctrl_get_device_gpio_range() - find device for GPIO range
* @gpio: the pin to locate the pin controller for
* @outdev: the pin control device if found
* @outrange: the GPIO range if found
*
* Find the pin controller handling a certain GPIO pin from the pinspace of
* the GPIO subsystem, return the device and the matching GPIO range. Returns
* -EPROBE_DEFER if the GPIO range could not be found in any device since it
* may still have not been registered.
*/
static int pinctrl_get_device_gpio_range(unsigned gpio,
struct pinctrl_dev **outdev,
struct pinctrl_gpio_range **outrange)
{
struct pinctrl_dev *pctldev;
mutex_lock(&pinctrldev_list_mutex);
/* Loop over the pin controllers */
list_for_each_entry(pctldev, &pinctrldev_list, node) {
struct pinctrl_gpio_range *range;
range = pinctrl_match_gpio_range(pctldev, gpio);
if (range) {
*outdev = pctldev;
*outrange = range;
mutex_unlock(&pinctrldev_list_mutex);
return 0;
}
}
mutex_unlock(&pinctrldev_list_mutex);
return -EPROBE_DEFER;
}
/**
* pinctrl_add_gpio_range() - register a GPIO range for a controller
* @pctldev: pin controller device to add the range to
* @range: the GPIO range to add
*
* This adds a range of GPIOs to be handled by a certain pin controller. Call
* this to register handled ranges after registering your pin controller.
*/
void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range)
{
mutex_lock(&pctldev->mutex);
list_add_tail(&range->node, &pctldev->gpio_ranges);
mutex_unlock(&pctldev->mutex);
}
EXPORT_SYMBOL_GPL(pinctrl_add_gpio_range);
void pinctrl_add_gpio_ranges(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *ranges,
unsigned nranges)
{
int i;
for (i = 0; i < nranges; i++)
pinctrl_add_gpio_range(pctldev, &ranges[i]);
}
EXPORT_SYMBOL_GPL(pinctrl_add_gpio_ranges);
struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
struct pinctrl_gpio_range *range)
{
struct pinctrl_dev *pctldev;
pctldev = get_pinctrl_dev_from_devname(devname);
/*
* If we can't find this device, let's assume that is because
* it has not probed yet, so the driver trying to register this
* range need to defer probing.
*/
if (!pctldev) {
return ERR_PTR(-EPROBE_DEFER);
}
pinctrl_add_gpio_range(pctldev, range);
return pctldev;
}
EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
const unsigned **pins, unsigned *num_pins)
{
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
int gs;
if (!pctlops->get_group_pins)
return -EINVAL;
gs = pinctrl_get_group_selector(pctldev, pin_group);
if (gs < 0)
return gs;
return pctlops->get_group_pins(pctldev, gs, pins, num_pins);
}
EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
unsigned int pin)
{
struct pinctrl_gpio_range *range;
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
if (range->pins) {
int a;
for (a = 0; a < range->npins; a++) {
if (range->pins[a] == pin)
return range;
}
} else if (pin >= range->pin_base &&
pin < range->pin_base + range->npins)
return range;
}
return NULL;
}
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin_nolock);
/**
* pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
* @pctldev: the pin controller device to look in
* @pin: a controller-local number to find the range for
*/
struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
unsigned int pin)
{
struct pinctrl_gpio_range *range;
mutex_lock(&pctldev->mutex);
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
mutex_unlock(&pctldev->mutex);
return range;
}
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);
/**
* pinctrl_remove_gpio_range() - remove a range of GPIOs from a pin controller
* @pctldev: pin controller device to remove the range from
* @range: the GPIO range to remove
*/
void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range)
{
mutex_lock(&pctldev->mutex);
list_del(&range->node);
mutex_unlock(&pctldev->mutex);
}
EXPORT_SYMBOL_GPL(pinctrl_remove_gpio_range);
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
/**
* pinctrl_generic_get_group_count() - returns the number of pin groups
* @pctldev: pin controller device
*/
int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev)
{
return pctldev->num_groups;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_count);
/**
* pinctrl_generic_get_group_name() - returns the name of a pin group
* @pctldev: pin controller device
* @selector: group number
*/
const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct group_desc *group;
group = radix_tree_lookup(&pctldev->pin_group_tree,
selector);
if (!group)
return NULL;
return group->name;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_name);
/**
* pinctrl_generic_get_group_pins() - gets the pin group pins
* @pctldev: pin controller device
* @selector: group number
* @pins: pins in the group
* @num_pins: number of pins in the group
*/
int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct group_desc *group;
group = radix_tree_lookup(&pctldev->pin_group_tree,
selector);
if (!group) {
dev_err(pctldev->dev, "%s could not find pingroup%i\n",
__func__, selector);
return -EINVAL;
}
*pins = group->pins;
*num_pins = group->num_pins;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_pins);
/**
* pinctrl_generic_get_group() - returns a pin group based on the number
* @pctldev: pin controller device
* @selector: group number
*/
struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct group_desc *group;
group = radix_tree_lookup(&pctldev->pin_group_tree,
selector);
if (!group)
return NULL;
return group;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group);
static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev,
const char *function)
{
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
int ngroups = ops->get_groups_count(pctldev);
int selector = 0;
/* See if this pctldev has this group */
while (selector < ngroups) {
const char *gname = ops->get_group_name(pctldev, selector);
if (gname && !strcmp(function, gname))
return selector;
selector++;
}
return -EINVAL;
}
/**
* pinctrl_generic_add_group() - adds a new pin group
* @pctldev: pin controller device
* @name: name of the pin group
* @pins: pins in the pin group
* @num_pins: number of pins in the pin group
* @data: pin controller driver specific data
*
* Note that the caller must take care of locking.
*/
int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
int *pins, int num_pins, void *data)
{
struct group_desc *group;
int selector, error;
if (!name)
return -EINVAL;
selector = pinctrl_generic_group_name_to_selector(pctldev, name);
if (selector >= 0)
return selector;
selector = pctldev->num_groups;
group = devm_kzalloc(pctldev->dev, sizeof(*group), GFP_KERNEL);
if (!group)
return -ENOMEM;
group->name = name;
group->pins = pins;
group->num_pins = num_pins;
group->data = data;
error = radix_tree_insert(&pctldev->pin_group_tree, selector, group);
if (error)
return error;
pctldev->num_groups++;
return selector;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_add_group);
/**
* pinctrl_generic_remove_group() - removes a numbered pin group
* @pctldev: pin controller device
* @selector: group number
*
* Note that the caller must take care of locking.
*/
int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct group_desc *group;
group = radix_tree_lookup(&pctldev->pin_group_tree,
selector);
if (!group)
return -ENOENT;
radix_tree_delete(&pctldev->pin_group_tree, selector);
devm_kfree(pctldev->dev, group);
pctldev->num_groups--;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group);
/**
* pinctrl_generic_free_groups() - removes all pin groups
* @pctldev: pin controller device
*
* Note that the caller must take care of locking. The pinctrl groups
* are allocated with devm_kzalloc() so no need to free them here.
*/
static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
{
struct radix_tree_iter iter;
void __rcu **slot;
radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0)
radix_tree_delete(&pctldev->pin_group_tree, iter.index);
pctldev->num_groups = 0;
}
#else
static inline void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
{
}
#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */
/**
* pinctrl_get_group_selector() - returns the group selector for a group
* @pctldev: the pin controller handling the group
* @pin_group: the pin group to look up
*/
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
const char *pin_group)
{
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
unsigned ngroups = pctlops->get_groups_count(pctldev);
unsigned group_selector = 0;
while (group_selector < ngroups) {
const char *gname = pctlops->get_group_name(pctldev,
group_selector);
if (gname && !strcmp(gname, pin_group)) {
dev_dbg(pctldev->dev,
"found group selector %u for %s\n",
group_selector,
pin_group);
return group_selector;
}
group_selector++;
}
dev_err(pctldev->dev, "does not have pin group %s\n",
pin_group);
return -EINVAL;
}
bool pinctrl_gpio_can_use_line(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
bool result;
int pin;
/*
* Try to obtain GPIO range, if it fails
* we're probably dealing with GPIO driver
* without a backing pin controller - bail out.
*/
if (pinctrl_get_device_gpio_range(gpio, &pctldev, &range))
return true;
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
result = pinmux_can_be_used_for_gpio(pctldev, pin);
mutex_unlock(&pctldev->mutex);
return result;
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_can_use_line);
/**
* pinctrl_gpio_request() - request a single pin to be used as GPIO
* @gpio: the GPIO pin number from the GPIO subsystem number space
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_request() semantics, platforms and individual drivers
* shall *NOT* request GPIO pins to be muxed in.
*/
int pinctrl_gpio_request(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
int ret;
int pin;
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret) {
if (pinctrl_ready_for_gpio_range(gpio))
ret = 0;
return ret;
}
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
ret = pinmux_request_gpio(pctldev, range, pin, gpio);
mutex_unlock(&pctldev->mutex);
return ret;
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_request);
/**
* pinctrl_gpio_free() - free control on a single pin, currently used as GPIO
* @gpio: the GPIO pin number from the GPIO subsystem number space
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_free() semantics, platforms and individual drivers
* shall *NOT* request GPIO pins to be muxed out.
*/
void pinctrl_gpio_free(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
int ret;
int pin;
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret) {
return;
}
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
pinmux_free_gpio(pctldev, pin, range);
mutex_unlock(&pctldev->mutex);
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_free);
static int pinctrl_gpio_direction(unsigned gpio, bool input)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
int ret;
int pin;
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret) {
return ret;
}
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
ret = pinmux_gpio_direction(pctldev, range, pin, input);
mutex_unlock(&pctldev->mutex);
return ret;
}
/**
* pinctrl_gpio_direction_input() - request a GPIO pin to go into input mode
* @gpio: the GPIO pin number from the GPIO subsystem number space
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_direction_input() semantics, platforms and individual
* drivers shall *NOT* touch pin control GPIO calls.
*/
int pinctrl_gpio_direction_input(unsigned gpio)
{
return pinctrl_gpio_direction(gpio, true);
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_direction_input);
/**
* pinctrl_gpio_direction_output() - request a GPIO pin to go into output mode
* @gpio: the GPIO pin number from the GPIO subsystem number space
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers,
* as part of their gpio_direction_output() semantics, platforms and individual
* drivers shall *NOT* touch pin control GPIO calls.
*/
int pinctrl_gpio_direction_output(unsigned gpio)
{
return pinctrl_gpio_direction(gpio, false);
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_direction_output);
/**
* pinctrl_gpio_set_config() - Apply config to given GPIO pin
* @gpio: the GPIO pin number from the GPIO subsystem number space
* @config: the configuration to apply to the GPIO
*
* This function should *ONLY* be used from gpiolib-based GPIO drivers, if
* they need to call the underlying pin controller to change GPIO config
* (for example set debounce time).
*/
int pinctrl_gpio_set_config(unsigned gpio, unsigned long config)
{
unsigned long configs[] = { config };
struct pinctrl_gpio_range *range;
struct pinctrl_dev *pctldev;
int ret, pin;
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret)
return ret;
mutex_lock(&pctldev->mutex);
pin = gpio_to_pin(range, gpio);
ret = pinconf_set_config(pctldev, pin, configs, ARRAY_SIZE(configs));
mutex_unlock(&pctldev->mutex);
return ret;
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_set_config);
static struct pinctrl_state *find_state(struct pinctrl *p,
const char *name)
{
struct pinctrl_state *state;
list_for_each_entry(state, &p->states, node)
if (!strcmp(state->name, name))
return state;
return NULL;
}
static struct pinctrl_state *create_state(struct pinctrl *p,
const char *name)
{
struct pinctrl_state *state;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return ERR_PTR(-ENOMEM);
state->name = name;
INIT_LIST_HEAD(&state->settings);
list_add_tail(&state->node, &p->states);
return state;
}
static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev,
const struct pinctrl_map *map)
{
struct pinctrl_state *state;
struct pinctrl_setting *setting;
int ret;
state = find_state(p, map->name);
if (!state)
state = create_state(p, map->name);
if (IS_ERR(state))
return PTR_ERR(state);
if (map->type == PIN_MAP_TYPE_DUMMY_STATE)
return 0;
setting = kzalloc(sizeof(*setting), GFP_KERNEL);
if (!setting)
return -ENOMEM;
setting->type = map->type;
if (pctldev)
setting->pctldev = pctldev;
else
setting->pctldev =
get_pinctrl_dev_from_devname(map->ctrl_dev_name);
if (!setting->pctldev) {
kfree(setting);
/* Do not defer probing of hogs (circular loop) */
if (!strcmp(map->ctrl_dev_name, map->dev_name))
return -ENODEV;
/*
* OK let us guess that the driver is not there yet, and
* let's defer obtaining this pinctrl handle to later...
*/
dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
map->ctrl_dev_name);
return -EPROBE_DEFER;
}
setting->dev_name = map->dev_name;
switch (map->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = pinmux_map_to_setting(map, setting);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = pinconf_map_to_setting(map, setting);
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0) {
kfree(setting);
return ret;
}
list_add_tail(&setting->node, &state->settings);
return 0;
}
static struct pinctrl *find_pinctrl(struct device *dev)
{
struct pinctrl *p;
mutex_lock(&pinctrl_list_mutex);
list_for_each_entry(p, &pinctrl_list, node)
if (p->dev == dev) {
mutex_unlock(&pinctrl_list_mutex);
return p;
}
mutex_unlock(&pinctrl_list_mutex);
return NULL;
}
static void pinctrl_free(struct pinctrl *p, bool inlist);
static struct pinctrl *create_pinctrl(struct device *dev,
struct pinctrl_dev *pctldev)
{
struct pinctrl *p;
const char *devname;
struct pinctrl_maps *maps_node;
const struct pinctrl_map *map;
int ret;
/*
* create the state cookie holder struct pinctrl for each
* mapping, this is what consumers will get when requesting
* a pin control handle with pinctrl_get()
*/
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return ERR_PTR(-ENOMEM);
p->dev = dev;
INIT_LIST_HEAD(&p->states);
INIT_LIST_HEAD(&p->dt_maps);
ret = pinctrl_dt_to_map(p, pctldev);
if (ret < 0) {
kfree(p);
return ERR_PTR(ret);
}
devname = dev_name(dev);
mutex_lock(&pinctrl_maps_mutex);
/* Iterate over the pin control maps to locate the right ones */
for_each_pin_map(maps_node, map) {
/* Map must be for this device */
if (strcmp(map->dev_name, devname))
continue;
/*
* If pctldev is not null, we are claiming hog for it,
* that means, setting that is served by pctldev by itself.
*
* Thus we must skip map that is for this device but is served
* by other device.
*/
if (pctldev &&
strcmp(dev_name(pctldev->dev), map->ctrl_dev_name))
continue;
ret = add_setting(p, pctldev, map);
/*
* At this point the adding of a setting may:
*
* - Defer, if the pinctrl device is not yet available
* - Fail, if the pinctrl device is not yet available,
* AND the setting is a hog. We cannot defer that, since
* the hog will kick in immediately after the device
* is registered.
*
* If the error returned was not -EPROBE_DEFER then we
* accumulate the errors to see if we end up with
* an -EPROBE_DEFER later, as that is the worst case.
*/
if (ret == -EPROBE_DEFER) {
pinctrl_free(p, false);
mutex_unlock(&pinctrl_maps_mutex);
return ERR_PTR(ret);
}
}
mutex_unlock(&pinctrl_maps_mutex);
if (ret < 0) {
/* If some other error than deferral occurred, return here */
pinctrl_free(p, false);
return ERR_PTR(ret);
}
kref_init(&p->users);
/* Add the pinctrl handle to the global list */
mutex_lock(&pinctrl_list_mutex);
list_add_tail(&p->node, &pinctrl_list);
mutex_unlock(&pinctrl_list_mutex);
return p;
}
/**
* pinctrl_get() - retrieves the pinctrl handle for a device
* @dev: the device to obtain the handle for
*/
struct pinctrl *pinctrl_get(struct device *dev)
{
struct pinctrl *p;
if (WARN_ON(!dev))
return ERR_PTR(-EINVAL);
/*
* See if somebody else (such as the device core) has already
* obtained a handle to the pinctrl for this device. In that case,
* return another pointer to it.
*/
p = find_pinctrl(dev);
if (p) {
dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
kref_get(&p->users);
return p;
}
return create_pinctrl(dev, NULL);
}
EXPORT_SYMBOL_GPL(pinctrl_get);
static void pinctrl_free_setting(bool disable_setting,
struct pinctrl_setting *setting)
{
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
if (disable_setting)
pinmux_disable_setting(setting);
pinmux_free_setting(setting);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
pinconf_free_setting(setting);
break;
default:
break;
}
}
static void pinctrl_free(struct pinctrl *p, bool inlist)
{
struct pinctrl_state *state, *n1;
struct pinctrl_setting *setting, *n2;
mutex_lock(&pinctrl_list_mutex);
list_for_each_entry_safe(state, n1, &p->states, node) {
list_for_each_entry_safe(setting, n2, &state->settings, node) {
pinctrl_free_setting(state == p->state, setting);
list_del(&setting->node);
kfree(setting);
}
list_del(&state->node);
kfree(state);
}
pinctrl_dt_free_maps(p);
if (inlist)
list_del(&p->node);
kfree(p);
mutex_unlock(&pinctrl_list_mutex);
}
/**
* pinctrl_release() - release the pinctrl handle
* @kref: the kref in the pinctrl being released
*/
static void pinctrl_release(struct kref *kref)
{
struct pinctrl *p = container_of(kref, struct pinctrl, users);
pinctrl_free(p, true);
}
/**
* pinctrl_put() - decrease use count on a previously claimed pinctrl handle
* @p: the pinctrl handle to release
*/
void pinctrl_put(struct pinctrl *p)
{
kref_put(&p->users, pinctrl_release);
}
EXPORT_SYMBOL_GPL(pinctrl_put);
/**
* pinctrl_lookup_state() - retrieves a state handle from a pinctrl handle
* @p: the pinctrl handle to retrieve the state from
* @name: the state name to retrieve
*/
struct pinctrl_state *pinctrl_lookup_state(struct pinctrl *p,
const char *name)
{
struct pinctrl_state *state;
state = find_state(p, name);
if (!state) {
if (pinctrl_dummy_state) {
/* create dummy state */
dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
name);
state = create_state(p, name);
} else
state = ERR_PTR(-ENODEV);
}
return state;
}
EXPORT_SYMBOL_GPL(pinctrl_lookup_state);
static void pinctrl_link_add(struct pinctrl_dev *pctldev,
struct device *consumer)
{
if (pctldev->desc->link_consumers)
device_link_add(consumer, pctldev->dev,
DL_FLAG_PM_RUNTIME |
DL_FLAG_AUTOREMOVE_CONSUMER);
}
/**
* pinctrl_commit_state() - select/activate/program a pinctrl state to HW
* @p: the pinctrl handle for the device that requests configuration
* @state: the state handle to select/activate/program
*/
static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
{
struct pinctrl_setting *setting, *setting2;
struct pinctrl_state *old_state = p->state;
int ret;
if (p->state) {
/*
* For each pinmux setting in the old state, forget SW's record
* of mux owner for that pingroup. Any pingroups which are
* still owned by the new state will be re-acquired by the call
* to pinmux_enable_setting() in the loop below.
*/
list_for_each_entry(setting, &p->state->settings, node) {
if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
continue;
pinmux_disable_setting(setting);
}
}
p->state = NULL;
/* Apply all the settings for the new state - pinmux first */
list_for_each_entry(setting, &state->settings, node) {
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = pinmux_enable_setting(setting);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = 0;
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0)
goto unapply_new_state;
/* Do not link hogs (circular dependency) */
if (p != setting->pctldev->p)
pinctrl_link_add(setting->pctldev, p->dev);
}
/* Apply all the settings for the new state - pinconf after */
list_for_each_entry(setting, &state->settings, node) {
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = 0;
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = pinconf_apply_setting(setting);
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0) {
goto unapply_new_state;
}
/* Do not link hogs (circular dependency) */
if (p != setting->pctldev->p)
pinctrl_link_add(setting->pctldev, p->dev);
}
p->state = state;
return 0;
unapply_new_state:
dev_err(p->dev, "Error applying setting, reverse things back\n");
list_for_each_entry(setting2, &state->settings, node) {
if (&setting2->node == &setting->node)
break;
/*
* All we can do here is pinmux_disable_setting.
* That means that some pins are muxed differently now
* than they were before applying the setting (We can't
* "unmux a pin"!), but it's not a big deal since the pins
* are free to be muxed by another apply_setting.
*/
if (setting2->type == PIN_MAP_TYPE_MUX_GROUP)
pinmux_disable_setting(setting2);
}
/* There's no infinite recursive loop here because p->state is NULL */
if (old_state)
pinctrl_select_state(p, old_state);
return ret;
}
/**
* pinctrl_select_state() - select/activate/program a pinctrl state to HW
* @p: the pinctrl handle for the device that requests configuration
* @state: the state handle to select/activate/program
*/
int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
{
if (p->state == state)
return 0;
return pinctrl_commit_state(p, state);
}
EXPORT_SYMBOL_GPL(pinctrl_select_state);
static void devm_pinctrl_release(struct device *dev, void *res)
{
pinctrl_put(*(struct pinctrl **)res);
}
/**
* devm_pinctrl_get() - Resource managed pinctrl_get()
* @dev: the device to obtain the handle for
*
* If there is a need to explicitly destroy the returned struct pinctrl,
* devm_pinctrl_put() should be used, rather than plain pinctrl_put().
*/
struct pinctrl *devm_pinctrl_get(struct device *dev)
{
struct pinctrl **ptr, *p;
ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
p = pinctrl_get(dev);
if (!IS_ERR(p)) {
*ptr = p;
devres_add(dev, ptr);
} else {
devres_free(ptr);
}
return p;
}
EXPORT_SYMBOL_GPL(devm_pinctrl_get);
static int devm_pinctrl_match(struct device *dev, void *res, void *data)
{
struct pinctrl **p = res;
return *p == data;
}
/**
* devm_pinctrl_put() - Resource managed pinctrl_put()
* @p: the pinctrl handle to release
*
* Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
* this function will not need to be called and the resource management
* code will ensure that the resource is freed.
*/
void devm_pinctrl_put(struct pinctrl *p)
{
WARN_ON(devres_release(p->dev, devm_pinctrl_release,
devm_pinctrl_match, p));
}
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
/**
* pinctrl_register_mappings() - register a set of pin controller mappings
* @maps: the pincontrol mappings table to register. Note the pinctrl-core
* keeps a reference to the passed in maps, so they should _not_ be
* marked with __initdata.
* @num_maps: the number of maps in the mapping table
*/
int pinctrl_register_mappings(const struct pinctrl_map *maps,
unsigned num_maps)
{
int i, ret;
struct pinctrl_maps *maps_node;
pr_debug("add %u pinctrl maps\n", num_maps);
/* First sanity check the new mapping */
for (i = 0; i < num_maps; i++) {
if (!maps[i].dev_name) {
pr_err("failed to register map %s (%d): no device given\n",
maps[i].name, i);
return -EINVAL;
}
if (!maps[i].name) {
pr_err("failed to register map %d: no map name given\n",
i);
return -EINVAL;
}
if (maps[i].type != PIN_MAP_TYPE_DUMMY_STATE &&
!maps[i].ctrl_dev_name) {
pr_err("failed to register map %s (%d): no pin control device given\n",
maps[i].name, i);
return -EINVAL;
}
switch (maps[i].type) {
case PIN_MAP_TYPE_DUMMY_STATE:
break;
case PIN_MAP_TYPE_MUX_GROUP:
ret = pinmux_validate_map(&maps[i], i);
if (ret < 0)
return ret;
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = pinconf_validate_map(&maps[i], i);
if (ret < 0)
return ret;
break;
default:
pr_err("failed to register map %s (%d): invalid type given\n",
maps[i].name, i);
return -EINVAL;
}
}
maps_node = kzalloc(sizeof(*maps_node), GFP_KERNEL);
if (!maps_node)
return -ENOMEM;
maps_node->maps = maps;
maps_node->num_maps = num_maps;
mutex_lock(&pinctrl_maps_mutex);
list_add_tail(&maps_node->node, &pinctrl_maps);
mutex_unlock(&pinctrl_maps_mutex);
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
/**
* pinctrl_unregister_mappings() - unregister a set of pin controller mappings
* @map: the pincontrol mappings table passed to pinctrl_register_mappings()
* when registering the mappings.
*/
void pinctrl_unregister_mappings(const struct pinctrl_map *map)
{
struct pinctrl_maps *maps_node;
mutex_lock(&pinctrl_maps_mutex);
list_for_each_entry(maps_node, &pinctrl_maps, node) {
if (maps_node->maps == map) {
list_del(&maps_node->node);
kfree(maps_node);
mutex_unlock(&pinctrl_maps_mutex);
return;
}
}
mutex_unlock(&pinctrl_maps_mutex);
}
EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings);
/**
* pinctrl_force_sleep() - turn a given controller device into sleep state
* @pctldev: pin controller device
*/
int pinctrl_force_sleep(struct pinctrl_dev *pctldev)
{
if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_sleep))
return pinctrl_commit_state(pctldev->p, pctldev->hog_sleep);
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_force_sleep);
/**
* pinctrl_force_default() - turn a given controller device into default state
* @pctldev: pin controller device
*/
int pinctrl_force_default(struct pinctrl_dev *pctldev)
{
if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_default))
return pinctrl_commit_state(pctldev->p, pctldev->hog_default);
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_force_default);
/**
* pinctrl_init_done() - tell pinctrl probe is done
*
* We'll use this time to switch the pins from "init" to "default" unless the
* driver selected some other state.
*
* @dev: device to that's done probing
*/
int pinctrl_init_done(struct device *dev)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (!pins)
return 0;
if (IS_ERR(pins->init_state))
return 0; /* No such state */
if (pins->p->state != pins->init_state)
return 0; /* Not at init anyway */
if (IS_ERR(pins->default_state))
return 0; /* No default state */
ret = pinctrl_select_state(pins->p, pins->default_state);
if (ret)
dev_err(dev, "failed to activate default pinctrl state\n");
return ret;
}
static int pinctrl_select_bound_state(struct device *dev,
struct pinctrl_state *state)
{
struct dev_pin_info *pins = dev->pins;
int ret;
if (IS_ERR(state))
return 0; /* No such state */
ret = pinctrl_select_state(pins->p, state);
if (ret)
dev_err(dev, "failed to activate pinctrl state %s\n",
state->name);
return ret;
}
/**
* pinctrl_select_default_state() - select default pinctrl state
* @dev: device to select default state for
*/
int pinctrl_select_default_state(struct device *dev)
{
if (!dev->pins)
return 0;
return pinctrl_select_bound_state(dev, dev->pins->default_state);
}
EXPORT_SYMBOL_GPL(pinctrl_select_default_state);
#ifdef CONFIG_PM
/**
* pinctrl_pm_select_default_state() - select default pinctrl state for PM
* @dev: device to select default state for
*/
int pinctrl_pm_select_default_state(struct device *dev)
{
return pinctrl_select_default_state(dev);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state);
/**
* pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM
* @dev: device to select sleep state for
*/
int pinctrl_pm_select_sleep_state(struct device *dev)
{
if (!dev->pins)
return 0;
return pinctrl_select_bound_state(dev, dev->pins->sleep_state);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_sleep_state);
/**
* pinctrl_pm_select_idle_state() - select idle pinctrl state for PM
* @dev: device to select idle state for
*/
int pinctrl_pm_select_idle_state(struct device *dev)
{
if (!dev->pins)
return 0;
return pinctrl_select_bound_state(dev, dev->pins->idle_state);
}
EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state);
#endif
#ifdef CONFIG_DEBUG_FS
static int pinctrl_pins_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
unsigned i, pin;
#ifdef CONFIG_GPIOLIB
struct pinctrl_gpio_range *range;
struct gpio_chip *chip;
int gpio_num;
#endif
seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Pin space may be sparse */
if (!desc)
continue;
seq_printf(s, "pin %d (%s) ", pin, desc->name);
#ifdef CONFIG_GPIOLIB
gpio_num = -1;
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
if ((pin >= range->pin_base) &&
(pin < (range->pin_base + range->npins))) {
gpio_num = range->base + (pin - range->pin_base);
break;
}
}
if (gpio_num >= 0)
/*
* FIXME: gpio_num comes from the global GPIO numberspace.
* we need to get rid of the range->base eventually and
* get the descriptor directly from the gpio_chip.
*/
chip = gpiod_to_chip(gpio_to_desc(gpio_num));
else
chip = NULL;
if (chip)
seq_printf(s, "%u:%s ", gpio_num - chip->gpiodev->base, chip->label);
else
seq_puts(s, "0:? ");
#endif
/* Driver-specific info per pin */
if (ops->pin_dbg_show)
ops->pin_dbg_show(pctldev, s, pin);
seq_puts(s, "\n");
}
mutex_unlock(&pctldev->mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_pins);
static int pinctrl_groups_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
unsigned ngroups, selector = 0;
mutex_lock(&pctldev->mutex);
ngroups = ops->get_groups_count(pctldev);
seq_puts(s, "registered pin groups:\n");
while (selector < ngroups) {
const unsigned *pins = NULL;
unsigned num_pins = 0;
const char *gname = ops->get_group_name(pctldev, selector);
const char *pname;
int ret = 0;
int i;
if (ops->get_group_pins)
ret = ops->get_group_pins(pctldev, selector,
&pins, &num_pins);
if (ret)
seq_printf(s, "%s [ERROR GETTING PINS]\n",
gname);
else {
seq_printf(s, "group: %s\n", gname);
for (i = 0; i < num_pins; i++) {
pname = pin_get_name(pctldev, pins[i]);
if (WARN_ON(!pname)) {
mutex_unlock(&pctldev->mutex);
return -EINVAL;
}
seq_printf(s, "pin %d (%s)\n", pins[i], pname);
}
seq_puts(s, "\n");
}
selector++;
}
mutex_unlock(&pctldev->mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_groups);
static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
struct pinctrl_gpio_range *range;
seq_puts(s, "GPIO ranges handled:\n");
mutex_lock(&pctldev->mutex);
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
if (range->pins) {
int a;
seq_printf(s, "%u: %s GPIOS [%u - %u] PINS {",
range->id, range->name,
range->base, (range->base + range->npins - 1));
for (a = 0; a < range->npins - 1; a++)
seq_printf(s, "%u, ", range->pins[a]);
seq_printf(s, "%u}\n", range->pins[a]);
}
else
seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n",
range->id, range->name,
range->base, (range->base + range->npins - 1),
range->pin_base,
(range->pin_base + range->npins - 1));
}
mutex_unlock(&pctldev->mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_gpioranges);
static int pinctrl_devices_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev;
seq_puts(s, "name [pinmux] [pinconf]\n");
mutex_lock(&pinctrldev_list_mutex);
list_for_each_entry(pctldev, &pinctrldev_list, node) {
seq_printf(s, "%s ", pctldev->desc->name);
if (pctldev->desc->pmxops)
seq_puts(s, "yes ");
else
seq_puts(s, "no ");
if (pctldev->desc->confops)
seq_puts(s, "yes");
else
seq_puts(s, "no");
seq_puts(s, "\n");
}
mutex_unlock(&pinctrldev_list_mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_devices);
static inline const char *map_type(enum pinctrl_map_type type)
{
static const char * const names[] = {
"INVALID",
"DUMMY_STATE",
"MUX_GROUP",
"CONFIGS_PIN",
"CONFIGS_GROUP",
};
if (type >= ARRAY_SIZE(names))
return "UNKNOWN";
return names[type];
}
static int pinctrl_maps_show(struct seq_file *s, void *what)
{
struct pinctrl_maps *maps_node;
const struct pinctrl_map *map;
seq_puts(s, "Pinctrl maps:\n");
mutex_lock(&pinctrl_maps_mutex);
for_each_pin_map(maps_node, map) {
seq_printf(s, "device %s\nstate %s\ntype %s (%d)\n",
map->dev_name, map->name, map_type(map->type),
map->type);
if (map->type != PIN_MAP_TYPE_DUMMY_STATE)
seq_printf(s, "controlling device %s\n",
map->ctrl_dev_name);
switch (map->type) {
case PIN_MAP_TYPE_MUX_GROUP:
pinmux_show_map(s, map);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
pinconf_show_map(s, map);
break;
default:
break;
}
seq_putc(s, '\n');
}
mutex_unlock(&pinctrl_maps_mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_maps);
static int pinctrl_show(struct seq_file *s, void *what)
{
struct pinctrl *p;
struct pinctrl_state *state;
struct pinctrl_setting *setting;
seq_puts(s, "Requested pin control handlers their pinmux maps:\n");
mutex_lock(&pinctrl_list_mutex);
list_for_each_entry(p, &pinctrl_list, node) {
seq_printf(s, "device: %s current state: %s\n",
dev_name(p->dev),
p->state ? p->state->name : "none");
list_for_each_entry(state, &p->states, node) {
seq_printf(s, " state: %s\n", state->name);
list_for_each_entry(setting, &state->settings, node) {
struct pinctrl_dev *pctldev = setting->pctldev;
seq_printf(s, " type: %s controller %s ",
map_type(setting->type),
pinctrl_dev_get_name(pctldev));
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
pinmux_show_setting(s, setting);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
pinconf_show_setting(s, setting);
break;
default:
break;
}
}
}
}
mutex_unlock(&pinctrl_list_mutex);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl);
static struct dentry *debugfs_root;
static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
{
struct dentry *device_root;
const char *debugfs_name;
if (pctldev->desc->name &&
strcmp(dev_name(pctldev->dev), pctldev->desc->name)) {
debugfs_name = devm_kasprintf(pctldev->dev, GFP_KERNEL,
"%s-%s", dev_name(pctldev->dev),
pctldev->desc->name);
if (!debugfs_name) {
pr_warn("failed to determine debugfs dir name for %s\n",
dev_name(pctldev->dev));
return;
}
} else {
debugfs_name = dev_name(pctldev->dev);
}
device_root = debugfs_create_dir(debugfs_name, debugfs_root);
pctldev->device_root = device_root;
if (IS_ERR(device_root) || !device_root) {
pr_warn("failed to create debugfs directory for %s\n",
dev_name(pctldev->dev));
return;
}
debugfs_create_file("pins", 0444,
device_root, pctldev, &pinctrl_pins_fops);
debugfs_create_file("pingroups", 0444,
device_root, pctldev, &pinctrl_groups_fops);
debugfs_create_file("gpio-ranges", 0444,
device_root, pctldev, &pinctrl_gpioranges_fops);
if (pctldev->desc->pmxops)
pinmux_init_device_debugfs(device_root, pctldev);
if (pctldev->desc->confops)
pinconf_init_device_debugfs(device_root, pctldev);
}
static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev)
{
debugfs_remove_recursive(pctldev->device_root);
}
static void pinctrl_init_debugfs(void)
{
debugfs_root = debugfs_create_dir("pinctrl", NULL);
if (IS_ERR(debugfs_root) || !debugfs_root) {
pr_warn("failed to create debugfs directory\n");
debugfs_root = NULL;
return;
}
debugfs_create_file("pinctrl-devices", 0444,
debugfs_root, NULL, &pinctrl_devices_fops);
debugfs_create_file("pinctrl-maps", 0444,
debugfs_root, NULL, &pinctrl_maps_fops);
debugfs_create_file("pinctrl-handles", 0444,
debugfs_root, NULL, &pinctrl_fops);
}
#else /* CONFIG_DEBUG_FS */
static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
{
}
static void pinctrl_init_debugfs(void)
{
}
static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev)
{
}
#endif
static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
{
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
if (!ops ||
!ops->get_groups_count ||
!ops->get_group_name)
return -EINVAL;
return 0;
}
/**
* pinctrl_init_controller() - init a pin controller device
* @pctldesc: descriptor for this pin controller
* @dev: parent device for this pin controller
* @driver_data: private pin controller data for this pin controller
*/
static struct pinctrl_dev *
pinctrl_init_controller(struct pinctrl_desc *pctldesc, struct device *dev,
void *driver_data)
{
struct pinctrl_dev *pctldev;
int ret;
if (!pctldesc)
return ERR_PTR(-EINVAL);
if (!pctldesc->name)
return ERR_PTR(-EINVAL);
pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL);
if (!pctldev)
return ERR_PTR(-ENOMEM);
/* Initialize pin control device struct */
pctldev->owner = pctldesc->owner;
pctldev->desc = pctldesc;
pctldev->driver_data = driver_data;
INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL);
#ifdef CONFIG_GENERIC_PINCTRL_GROUPS
INIT_RADIX_TREE(&pctldev->pin_group_tree, GFP_KERNEL);
#endif
#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS
INIT_RADIX_TREE(&pctldev->pin_function_tree, GFP_KERNEL);
#endif
INIT_LIST_HEAD(&pctldev->gpio_ranges);
INIT_LIST_HEAD(&pctldev->node);
pctldev->dev = dev;
mutex_init(&pctldev->mutex);
/* check core ops for sanity */
ret = pinctrl_check_ops(pctldev);
if (ret) {
dev_err(dev, "pinctrl ops lacks necessary functions\n");
goto out_err;
}
/* If we're implementing pinmuxing, check the ops for sanity */
if (pctldesc->pmxops) {
ret = pinmux_check_ops(pctldev);
if (ret)
goto out_err;
}
/* If we're implementing pinconfig, check the ops for sanity */
if (pctldesc->confops) {
ret = pinconf_check_ops(pctldev);
if (ret)
goto out_err;
}
/* Register all the pins */
dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
if (ret) {
dev_err(dev, "error during pin registration\n");
pinctrl_free_pindescs(pctldev, pctldesc->pins,
pctldesc->npins);
goto out_err;
}
return pctldev;
out_err:
mutex_destroy(&pctldev->mutex);
kfree(pctldev);
return ERR_PTR(ret);
}
static int pinctrl_claim_hogs(struct pinctrl_dev *pctldev)
{
pctldev->p = create_pinctrl(pctldev->dev, pctldev);
if (PTR_ERR(pctldev->p) == -ENODEV) {
dev_dbg(pctldev->dev, "no hogs found\n");
return 0;
}
if (IS_ERR(pctldev->p)) {
dev_err(pctldev->dev, "error claiming hogs: %li\n",
PTR_ERR(pctldev->p));
return PTR_ERR(pctldev->p);
}
pctldev->hog_default =
pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT);
if (IS_ERR(pctldev->hog_default)) {
dev_dbg(pctldev->dev,
"failed to lookup the default state\n");
} else {
if (pinctrl_select_state(pctldev->p,
pctldev->hog_default))
dev_err(pctldev->dev,
"failed to select default state\n");
}
pctldev->hog_sleep =
pinctrl_lookup_state(pctldev->p,
PINCTRL_STATE_SLEEP);
if (IS_ERR(pctldev->hog_sleep))
dev_dbg(pctldev->dev,
"failed to lookup the sleep state\n");
return 0;
}
int pinctrl_enable(struct pinctrl_dev *pctldev)
{
int error;
error = pinctrl_claim_hogs(pctldev);
if (error) {
dev_err(pctldev->dev, "could not claim hogs: %i\n",
error);
pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
pctldev->desc->npins);
mutex_destroy(&pctldev->mutex);
kfree(pctldev);
return error;
}
mutex_lock(&pinctrldev_list_mutex);
list_add_tail(&pctldev->node, &pinctrldev_list);
mutex_unlock(&pinctrldev_list_mutex);
pinctrl_init_device_debugfs(pctldev);
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_enable);
/**
* pinctrl_register() - register a pin controller device
* @pctldesc: descriptor for this pin controller
* @dev: parent device for this pin controller
* @driver_data: private pin controller data for this pin controller
*
* Note that pinctrl_register() is known to have problems as the pin
* controller driver functions are called before the driver has a
* struct pinctrl_dev handle. To avoid issues later on, please use the
* new pinctrl_register_and_init() below instead.
*/
struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
struct device *dev, void *driver_data)
{
struct pinctrl_dev *pctldev;
int error;
pctldev = pinctrl_init_controller(pctldesc, dev, driver_data);
if (IS_ERR(pctldev))
return pctldev;
error = pinctrl_enable(pctldev);
if (error)
return ERR_PTR(error);
return pctldev;
}
EXPORT_SYMBOL_GPL(pinctrl_register);
/**
* pinctrl_register_and_init() - register and init pin controller device
* @pctldesc: descriptor for this pin controller
* @dev: parent device for this pin controller
* @driver_data: private pin controller data for this pin controller
* @pctldev: pin controller device
*
* Note that pinctrl_enable() still needs to be manually called after
* this once the driver is ready.
*/
int pinctrl_register_and_init(struct pinctrl_desc *pctldesc,
struct device *dev, void *driver_data,
struct pinctrl_dev **pctldev)
{
struct pinctrl_dev *p;
p = pinctrl_init_controller(pctldesc, dev, driver_data);
if (IS_ERR(p))
return PTR_ERR(p);
/*
* We have pinctrl_start() call functions in the pin controller
* driver with create_pinctrl() for at least dt_node_to_map(). So
* let's make sure pctldev is properly initialized for the
* pin controller driver before we do anything.
*/
*pctldev = p;
return 0;
}
EXPORT_SYMBOL_GPL(pinctrl_register_and_init);
/**
* pinctrl_unregister() - unregister pinmux
* @pctldev: pin controller to unregister
*
* Called by pinmux drivers to unregister a pinmux.
*/
void pinctrl_unregister(struct pinctrl_dev *pctldev)
{
struct pinctrl_gpio_range *range, *n;
if (!pctldev)
return;
mutex_lock(&pctldev->mutex);
pinctrl_remove_device_debugfs(pctldev);
mutex_unlock(&pctldev->mutex);
if (!IS_ERR_OR_NULL(pctldev->p))
pinctrl_put(pctldev->p);
mutex_lock(&pinctrldev_list_mutex);
mutex_lock(&pctldev->mutex);
/* TODO: check that no pinmuxes are still active? */
list_del(&pctldev->node);
pinmux_generic_free_functions(pctldev);
pinctrl_generic_free_groups(pctldev);
/* Destroy descriptor tree */
pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
pctldev->desc->npins);
/* remove gpio ranges map */
list_for_each_entry_safe(range, n, &pctldev->gpio_ranges, node)
list_del(&range->node);
mutex_unlock(&pctldev->mutex);
mutex_destroy(&pctldev->mutex);
kfree(pctldev);
mutex_unlock(&pinctrldev_list_mutex);
}
EXPORT_SYMBOL_GPL(pinctrl_unregister);
static void devm_pinctrl_dev_release(struct device *dev, void *res)
{
struct pinctrl_dev *pctldev = *(struct pinctrl_dev **)res;
pinctrl_unregister(pctldev);
}
static int devm_pinctrl_dev_match(struct device *dev, void *res, void *data)
{
struct pctldev **r = res;
if (WARN_ON(!r || !*r))
return 0;
return *r == data;
}
/**
* devm_pinctrl_register() - Resource managed version of pinctrl_register().
* @dev: parent device for this pin controller
* @pctldesc: descriptor for this pin controller
* @driver_data: private pin controller data for this pin controller
*
* Returns an error pointer if pincontrol register failed. Otherwise
* it returns valid pinctrl handle.
*
* The pinctrl device will be automatically released when the device is unbound.
*/
struct pinctrl_dev *devm_pinctrl_register(struct device *dev,
struct pinctrl_desc *pctldesc,
void *driver_data)
{
struct pinctrl_dev **ptr, *pctldev;
ptr = devres_alloc(devm_pinctrl_dev_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
pctldev = pinctrl_register(pctldesc, dev, driver_data);
if (IS_ERR(pctldev)) {
devres_free(ptr);
return pctldev;
}
*ptr = pctldev;
devres_add(dev, ptr);
return pctldev;
}
EXPORT_SYMBOL_GPL(devm_pinctrl_register);
/**
* devm_pinctrl_register_and_init() - Resource managed pinctrl register and init
* @dev: parent device for this pin controller
* @pctldesc: descriptor for this pin controller
* @driver_data: private pin controller data for this pin controller
* @pctldev: pin controller device
*
* Returns zero on success or an error number on failure.
*
* The pinctrl device will be automatically released when the device is unbound.
*/
int devm_pinctrl_register_and_init(struct device *dev,
struct pinctrl_desc *pctldesc,
void *driver_data,
struct pinctrl_dev **pctldev)
{
struct pinctrl_dev **ptr;
int error;
ptr = devres_alloc(devm_pinctrl_dev_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return -ENOMEM;
error = pinctrl_register_and_init(pctldesc, dev, driver_data, pctldev);
if (error) {
devres_free(ptr);
return error;
}
*ptr = *pctldev;
devres_add(dev, ptr);
return 0;
}
EXPORT_SYMBOL_GPL(devm_pinctrl_register_and_init);
/**
* devm_pinctrl_unregister() - Resource managed version of pinctrl_unregister().
* @dev: device for which resource was allocated
* @pctldev: the pinctrl device to unregister.
*/
void devm_pinctrl_unregister(struct device *dev, struct pinctrl_dev *pctldev)
{
WARN_ON(devres_release(dev, devm_pinctrl_dev_release,
devm_pinctrl_dev_match, pctldev));
}
EXPORT_SYMBOL_GPL(devm_pinctrl_unregister);
static int __init pinctrl_init(void)
{
pr_info("initialized pinctrl subsystem\n");
pinctrl_init_debugfs();
return 0;
}
/* init early since many drivers really need to initialized pinmux early */
core_initcall(pinctrl_init);
|
linux-master
|
drivers/pinctrl/core.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2020 Sean Anderson <[email protected]>
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <dt-bindings/pinctrl/k210-fpioa.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
/*
* The K210 only implements 8 drive levels, even though
* there is register space for 16
*/
#define K210_PC_DRIVE_MASK GENMASK(11, 8)
#define K210_PC_DRIVE_SHIFT 8
#define K210_PC_DRIVE_0 (0 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_1 (1 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_2 (2 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_3 (3 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_4 (4 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_5 (5 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_6 (6 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_7 (7 << K210_PC_DRIVE_SHIFT)
#define K210_PC_DRIVE_MAX 7
#define K210_PC_MODE_MASK GENMASK(23, 12)
/*
* output enabled == PC_OE & (PC_OE_INV ^ FUNCTION_OE)
* where FUNCTION_OE is a physical signal from the function.
*/
#define K210_PC_OE BIT(12) /* Output Enable */
#define K210_PC_OE_INV BIT(13) /* INVert Output Enable */
#define K210_PC_DO_OE BIT(14) /* set Data Out to Output Enable sig */
#define K210_PC_DO_INV BIT(15) /* INVert final Data Output */
#define K210_PC_PU BIT(16) /* Pull Up */
#define K210_PC_PD BIT(17) /* Pull Down */
/* Strong pull up not implemented on K210 */
#define K210_PC_SL BIT(19) /* reduce SLew rate */
/* Same semantics as OE above */
#define K210_PC_IE BIT(20) /* Input Enable */
#define K210_PC_IE_INV BIT(21) /* INVert Input Enable */
#define K210_PC_DI_INV BIT(22) /* INVert Data Input */
#define K210_PC_ST BIT(23) /* Schmitt Trigger */
#define K210_PC_DI BIT(31) /* raw Data Input */
#define K210_PC_BIAS_MASK (K210_PC_PU & K210_PC_PD)
#define K210_PC_MODE_IN (K210_PC_IE | K210_PC_ST)
#define K210_PC_MODE_OUT (K210_PC_DRIVE_7 | K210_PC_OE)
#define K210_PC_MODE_I2C (K210_PC_MODE_IN | K210_PC_SL | \
K210_PC_OE | K210_PC_PU)
#define K210_PC_MODE_SCCB (K210_PC_MODE_I2C | \
K210_PC_OE_INV | K210_PC_IE_INV)
#define K210_PC_MODE_SPI (K210_PC_MODE_IN | K210_PC_IE_INV | \
K210_PC_MODE_OUT | K210_PC_OE_INV)
#define K210_PC_MODE_GPIO (K210_PC_MODE_IN | K210_PC_MODE_OUT)
#define K210_PG_FUNC GENMASK(7, 0)
#define K210_PG_DO BIT(8)
#define K210_PG_PIN GENMASK(22, 16)
/*
* struct k210_fpioa: Kendryte K210 FPIOA memory mapped registers
* @pins: 48 32-bits IO pin registers
* @tie_en: 256 (one per function) input tie enable bits
* @tie_val: 256 (one per function) input tie value bits
*/
struct k210_fpioa {
u32 pins[48];
u32 tie_en[8];
u32 tie_val[8];
};
struct k210_fpioa_data {
struct device *dev;
struct pinctrl_dev *pctl;
struct k210_fpioa __iomem *fpioa;
struct regmap *sysctl_map;
u32 power_offset;
struct clk *clk;
struct clk *pclk;
};
#define K210_PIN_NAME(i) ("IO_" #i)
#define K210_PIN(i) [(i)] = PINCTRL_PIN((i), K210_PIN_NAME(i))
static const struct pinctrl_pin_desc k210_pins[] = {
K210_PIN(0), K210_PIN(1), K210_PIN(2),
K210_PIN(3), K210_PIN(4), K210_PIN(5),
K210_PIN(6), K210_PIN(7), K210_PIN(8),
K210_PIN(9), K210_PIN(10), K210_PIN(11),
K210_PIN(12), K210_PIN(13), K210_PIN(14),
K210_PIN(15), K210_PIN(16), K210_PIN(17),
K210_PIN(18), K210_PIN(19), K210_PIN(20),
K210_PIN(21), K210_PIN(22), K210_PIN(23),
K210_PIN(24), K210_PIN(25), K210_PIN(26),
K210_PIN(27), K210_PIN(28), K210_PIN(29),
K210_PIN(30), K210_PIN(31), K210_PIN(32),
K210_PIN(33), K210_PIN(34), K210_PIN(35),
K210_PIN(36), K210_PIN(37), K210_PIN(38),
K210_PIN(39), K210_PIN(40), K210_PIN(41),
K210_PIN(42), K210_PIN(43), K210_PIN(44),
K210_PIN(45), K210_PIN(46), K210_PIN(47)
};
#define K210_NPINS ARRAY_SIZE(k210_pins)
/*
* Pin groups: each of the 48 programmable pins is a group.
* To this are added 8 power domain groups, which for the purposes of
* the pin subsystem, contain no pins. The power domain groups only exist
* to set the power level. The id should never be used (since there are
* no pins 48-55).
*/
static const char *const k210_group_names[] = {
/* The first 48 groups are for pins, one each */
K210_PIN_NAME(0), K210_PIN_NAME(1), K210_PIN_NAME(2),
K210_PIN_NAME(3), K210_PIN_NAME(4), K210_PIN_NAME(5),
K210_PIN_NAME(6), K210_PIN_NAME(7), K210_PIN_NAME(8),
K210_PIN_NAME(9), K210_PIN_NAME(10), K210_PIN_NAME(11),
K210_PIN_NAME(12), K210_PIN_NAME(13), K210_PIN_NAME(14),
K210_PIN_NAME(15), K210_PIN_NAME(16), K210_PIN_NAME(17),
K210_PIN_NAME(18), K210_PIN_NAME(19), K210_PIN_NAME(20),
K210_PIN_NAME(21), K210_PIN_NAME(22), K210_PIN_NAME(23),
K210_PIN_NAME(24), K210_PIN_NAME(25), K210_PIN_NAME(26),
K210_PIN_NAME(27), K210_PIN_NAME(28), K210_PIN_NAME(29),
K210_PIN_NAME(30), K210_PIN_NAME(31), K210_PIN_NAME(32),
K210_PIN_NAME(33), K210_PIN_NAME(34), K210_PIN_NAME(35),
K210_PIN_NAME(36), K210_PIN_NAME(37), K210_PIN_NAME(38),
K210_PIN_NAME(39), K210_PIN_NAME(40), K210_PIN_NAME(41),
K210_PIN_NAME(42), K210_PIN_NAME(43), K210_PIN_NAME(44),
K210_PIN_NAME(45), K210_PIN_NAME(46), K210_PIN_NAME(47),
[48] = "A0", [49] = "A1", [50] = "A2",
[51] = "B3", [52] = "B4", [53] = "B5",
[54] = "C6", [55] = "C7"
};
#define K210_NGROUPS ARRAY_SIZE(k210_group_names)
enum k210_pinctrl_mode_id {
K210_PC_DEFAULT_DISABLED,
K210_PC_DEFAULT_IN,
K210_PC_DEFAULT_IN_TIE,
K210_PC_DEFAULT_OUT,
K210_PC_DEFAULT_I2C,
K210_PC_DEFAULT_SCCB,
K210_PC_DEFAULT_SPI,
K210_PC_DEFAULT_GPIO,
K210_PC_DEFAULT_INT13,
};
#define K210_PC_DEFAULT(mode) \
[K210_PC_DEFAULT_##mode] = K210_PC_MODE_##mode
static const u32 k210_pinconf_mode_id_to_mode[] = {
[K210_PC_DEFAULT_DISABLED] = 0,
K210_PC_DEFAULT(IN),
[K210_PC_DEFAULT_IN_TIE] = K210_PC_MODE_IN,
K210_PC_DEFAULT(OUT),
K210_PC_DEFAULT(I2C),
K210_PC_DEFAULT(SCCB),
K210_PC_DEFAULT(SPI),
K210_PC_DEFAULT(GPIO),
[K210_PC_DEFAULT_INT13] = K210_PC_MODE_IN | K210_PC_PU,
};
#undef DEFAULT
/*
* Pin functions configuration information.
*/
struct k210_pcf_info {
char name[15];
u8 mode_id;
};
#define K210_FUNC(id, mode) \
[K210_PCF_##id] = { \
.name = #id, \
.mode_id = K210_PC_DEFAULT_##mode \
}
static const struct k210_pcf_info k210_pcf_infos[] = {
K210_FUNC(JTAG_TCLK, IN),
K210_FUNC(JTAG_TDI, IN),
K210_FUNC(JTAG_TMS, IN),
K210_FUNC(JTAG_TDO, OUT),
K210_FUNC(SPI0_D0, SPI),
K210_FUNC(SPI0_D1, SPI),
K210_FUNC(SPI0_D2, SPI),
K210_FUNC(SPI0_D3, SPI),
K210_FUNC(SPI0_D4, SPI),
K210_FUNC(SPI0_D5, SPI),
K210_FUNC(SPI0_D6, SPI),
K210_FUNC(SPI0_D7, SPI),
K210_FUNC(SPI0_SS0, OUT),
K210_FUNC(SPI0_SS1, OUT),
K210_FUNC(SPI0_SS2, OUT),
K210_FUNC(SPI0_SS3, OUT),
K210_FUNC(SPI0_ARB, IN_TIE),
K210_FUNC(SPI0_SCLK, OUT),
K210_FUNC(UARTHS_RX, IN),
K210_FUNC(UARTHS_TX, OUT),
K210_FUNC(RESV6, IN),
K210_FUNC(RESV7, IN),
K210_FUNC(CLK_SPI1, OUT),
K210_FUNC(CLK_I2C1, OUT),
K210_FUNC(GPIOHS0, GPIO),
K210_FUNC(GPIOHS1, GPIO),
K210_FUNC(GPIOHS2, GPIO),
K210_FUNC(GPIOHS3, GPIO),
K210_FUNC(GPIOHS4, GPIO),
K210_FUNC(GPIOHS5, GPIO),
K210_FUNC(GPIOHS6, GPIO),
K210_FUNC(GPIOHS7, GPIO),
K210_FUNC(GPIOHS8, GPIO),
K210_FUNC(GPIOHS9, GPIO),
K210_FUNC(GPIOHS10, GPIO),
K210_FUNC(GPIOHS11, GPIO),
K210_FUNC(GPIOHS12, GPIO),
K210_FUNC(GPIOHS13, GPIO),
K210_FUNC(GPIOHS14, GPIO),
K210_FUNC(GPIOHS15, GPIO),
K210_FUNC(GPIOHS16, GPIO),
K210_FUNC(GPIOHS17, GPIO),
K210_FUNC(GPIOHS18, GPIO),
K210_FUNC(GPIOHS19, GPIO),
K210_FUNC(GPIOHS20, GPIO),
K210_FUNC(GPIOHS21, GPIO),
K210_FUNC(GPIOHS22, GPIO),
K210_FUNC(GPIOHS23, GPIO),
K210_FUNC(GPIOHS24, GPIO),
K210_FUNC(GPIOHS25, GPIO),
K210_FUNC(GPIOHS26, GPIO),
K210_FUNC(GPIOHS27, GPIO),
K210_FUNC(GPIOHS28, GPIO),
K210_FUNC(GPIOHS29, GPIO),
K210_FUNC(GPIOHS30, GPIO),
K210_FUNC(GPIOHS31, GPIO),
K210_FUNC(GPIO0, GPIO),
K210_FUNC(GPIO1, GPIO),
K210_FUNC(GPIO2, GPIO),
K210_FUNC(GPIO3, GPIO),
K210_FUNC(GPIO4, GPIO),
K210_FUNC(GPIO5, GPIO),
K210_FUNC(GPIO6, GPIO),
K210_FUNC(GPIO7, GPIO),
K210_FUNC(UART1_RX, IN),
K210_FUNC(UART1_TX, OUT),
K210_FUNC(UART2_RX, IN),
K210_FUNC(UART2_TX, OUT),
K210_FUNC(UART3_RX, IN),
K210_FUNC(UART3_TX, OUT),
K210_FUNC(SPI1_D0, SPI),
K210_FUNC(SPI1_D1, SPI),
K210_FUNC(SPI1_D2, SPI),
K210_FUNC(SPI1_D3, SPI),
K210_FUNC(SPI1_D4, SPI),
K210_FUNC(SPI1_D5, SPI),
K210_FUNC(SPI1_D6, SPI),
K210_FUNC(SPI1_D7, SPI),
K210_FUNC(SPI1_SS0, OUT),
K210_FUNC(SPI1_SS1, OUT),
K210_FUNC(SPI1_SS2, OUT),
K210_FUNC(SPI1_SS3, OUT),
K210_FUNC(SPI1_ARB, IN_TIE),
K210_FUNC(SPI1_SCLK, OUT),
K210_FUNC(SPI2_D0, SPI),
K210_FUNC(SPI2_SS, IN),
K210_FUNC(SPI2_SCLK, IN),
K210_FUNC(I2S0_MCLK, OUT),
K210_FUNC(I2S0_SCLK, OUT),
K210_FUNC(I2S0_WS, OUT),
K210_FUNC(I2S0_IN_D0, IN),
K210_FUNC(I2S0_IN_D1, IN),
K210_FUNC(I2S0_IN_D2, IN),
K210_FUNC(I2S0_IN_D3, IN),
K210_FUNC(I2S0_OUT_D0, OUT),
K210_FUNC(I2S0_OUT_D1, OUT),
K210_FUNC(I2S0_OUT_D2, OUT),
K210_FUNC(I2S0_OUT_D3, OUT),
K210_FUNC(I2S1_MCLK, OUT),
K210_FUNC(I2S1_SCLK, OUT),
K210_FUNC(I2S1_WS, OUT),
K210_FUNC(I2S1_IN_D0, IN),
K210_FUNC(I2S1_IN_D1, IN),
K210_FUNC(I2S1_IN_D2, IN),
K210_FUNC(I2S1_IN_D3, IN),
K210_FUNC(I2S1_OUT_D0, OUT),
K210_FUNC(I2S1_OUT_D1, OUT),
K210_FUNC(I2S1_OUT_D2, OUT),
K210_FUNC(I2S1_OUT_D3, OUT),
K210_FUNC(I2S2_MCLK, OUT),
K210_FUNC(I2S2_SCLK, OUT),
K210_FUNC(I2S2_WS, OUT),
K210_FUNC(I2S2_IN_D0, IN),
K210_FUNC(I2S2_IN_D1, IN),
K210_FUNC(I2S2_IN_D2, IN),
K210_FUNC(I2S2_IN_D3, IN),
K210_FUNC(I2S2_OUT_D0, OUT),
K210_FUNC(I2S2_OUT_D1, OUT),
K210_FUNC(I2S2_OUT_D2, OUT),
K210_FUNC(I2S2_OUT_D3, OUT),
K210_FUNC(RESV0, DISABLED),
K210_FUNC(RESV1, DISABLED),
K210_FUNC(RESV2, DISABLED),
K210_FUNC(RESV3, DISABLED),
K210_FUNC(RESV4, DISABLED),
K210_FUNC(RESV5, DISABLED),
K210_FUNC(I2C0_SCLK, I2C),
K210_FUNC(I2C0_SDA, I2C),
K210_FUNC(I2C1_SCLK, I2C),
K210_FUNC(I2C1_SDA, I2C),
K210_FUNC(I2C2_SCLK, I2C),
K210_FUNC(I2C2_SDA, I2C),
K210_FUNC(DVP_XCLK, OUT),
K210_FUNC(DVP_RST, OUT),
K210_FUNC(DVP_PWDN, OUT),
K210_FUNC(DVP_VSYNC, IN),
K210_FUNC(DVP_HSYNC, IN),
K210_FUNC(DVP_PCLK, IN),
K210_FUNC(DVP_D0, IN),
K210_FUNC(DVP_D1, IN),
K210_FUNC(DVP_D2, IN),
K210_FUNC(DVP_D3, IN),
K210_FUNC(DVP_D4, IN),
K210_FUNC(DVP_D5, IN),
K210_FUNC(DVP_D6, IN),
K210_FUNC(DVP_D7, IN),
K210_FUNC(SCCB_SCLK, SCCB),
K210_FUNC(SCCB_SDA, SCCB),
K210_FUNC(UART1_CTS, IN),
K210_FUNC(UART1_DSR, IN),
K210_FUNC(UART1_DCD, IN),
K210_FUNC(UART1_RI, IN),
K210_FUNC(UART1_SIR_IN, IN),
K210_FUNC(UART1_DTR, OUT),
K210_FUNC(UART1_RTS, OUT),
K210_FUNC(UART1_OUT2, OUT),
K210_FUNC(UART1_OUT1, OUT),
K210_FUNC(UART1_SIR_OUT, OUT),
K210_FUNC(UART1_BAUD, OUT),
K210_FUNC(UART1_RE, OUT),
K210_FUNC(UART1_DE, OUT),
K210_FUNC(UART1_RS485_EN, OUT),
K210_FUNC(UART2_CTS, IN),
K210_FUNC(UART2_DSR, IN),
K210_FUNC(UART2_DCD, IN),
K210_FUNC(UART2_RI, IN),
K210_FUNC(UART2_SIR_IN, IN),
K210_FUNC(UART2_DTR, OUT),
K210_FUNC(UART2_RTS, OUT),
K210_FUNC(UART2_OUT2, OUT),
K210_FUNC(UART2_OUT1, OUT),
K210_FUNC(UART2_SIR_OUT, OUT),
K210_FUNC(UART2_BAUD, OUT),
K210_FUNC(UART2_RE, OUT),
K210_FUNC(UART2_DE, OUT),
K210_FUNC(UART2_RS485_EN, OUT),
K210_FUNC(UART3_CTS, IN),
K210_FUNC(UART3_DSR, IN),
K210_FUNC(UART3_DCD, IN),
K210_FUNC(UART3_RI, IN),
K210_FUNC(UART3_SIR_IN, IN),
K210_FUNC(UART3_DTR, OUT),
K210_FUNC(UART3_RTS, OUT),
K210_FUNC(UART3_OUT2, OUT),
K210_FUNC(UART3_OUT1, OUT),
K210_FUNC(UART3_SIR_OUT, OUT),
K210_FUNC(UART3_BAUD, OUT),
K210_FUNC(UART3_RE, OUT),
K210_FUNC(UART3_DE, OUT),
K210_FUNC(UART3_RS485_EN, OUT),
K210_FUNC(TIMER0_TOGGLE1, OUT),
K210_FUNC(TIMER0_TOGGLE2, OUT),
K210_FUNC(TIMER0_TOGGLE3, OUT),
K210_FUNC(TIMER0_TOGGLE4, OUT),
K210_FUNC(TIMER1_TOGGLE1, OUT),
K210_FUNC(TIMER1_TOGGLE2, OUT),
K210_FUNC(TIMER1_TOGGLE3, OUT),
K210_FUNC(TIMER1_TOGGLE4, OUT),
K210_FUNC(TIMER2_TOGGLE1, OUT),
K210_FUNC(TIMER2_TOGGLE2, OUT),
K210_FUNC(TIMER2_TOGGLE3, OUT),
K210_FUNC(TIMER2_TOGGLE4, OUT),
K210_FUNC(CLK_SPI2, OUT),
K210_FUNC(CLK_I2C2, OUT),
K210_FUNC(INTERNAL0, OUT),
K210_FUNC(INTERNAL1, OUT),
K210_FUNC(INTERNAL2, OUT),
K210_FUNC(INTERNAL3, OUT),
K210_FUNC(INTERNAL4, OUT),
K210_FUNC(INTERNAL5, OUT),
K210_FUNC(INTERNAL6, OUT),
K210_FUNC(INTERNAL7, OUT),
K210_FUNC(INTERNAL8, OUT),
K210_FUNC(INTERNAL9, IN),
K210_FUNC(INTERNAL10, IN),
K210_FUNC(INTERNAL11, IN),
K210_FUNC(INTERNAL12, IN),
K210_FUNC(INTERNAL13, INT13),
K210_FUNC(INTERNAL14, I2C),
K210_FUNC(INTERNAL15, IN),
K210_FUNC(INTERNAL16, IN),
K210_FUNC(INTERNAL17, IN),
K210_FUNC(CONSTANT, DISABLED),
K210_FUNC(INTERNAL18, IN),
K210_FUNC(DEBUG0, OUT),
K210_FUNC(DEBUG1, OUT),
K210_FUNC(DEBUG2, OUT),
K210_FUNC(DEBUG3, OUT),
K210_FUNC(DEBUG4, OUT),
K210_FUNC(DEBUG5, OUT),
K210_FUNC(DEBUG6, OUT),
K210_FUNC(DEBUG7, OUT),
K210_FUNC(DEBUG8, OUT),
K210_FUNC(DEBUG9, OUT),
K210_FUNC(DEBUG10, OUT),
K210_FUNC(DEBUG11, OUT),
K210_FUNC(DEBUG12, OUT),
K210_FUNC(DEBUG13, OUT),
K210_FUNC(DEBUG14, OUT),
K210_FUNC(DEBUG15, OUT),
K210_FUNC(DEBUG16, OUT),
K210_FUNC(DEBUG17, OUT),
K210_FUNC(DEBUG18, OUT),
K210_FUNC(DEBUG19, OUT),
K210_FUNC(DEBUG20, OUT),
K210_FUNC(DEBUG21, OUT),
K210_FUNC(DEBUG22, OUT),
K210_FUNC(DEBUG23, OUT),
K210_FUNC(DEBUG24, OUT),
K210_FUNC(DEBUG25, OUT),
K210_FUNC(DEBUG26, OUT),
K210_FUNC(DEBUG27, OUT),
K210_FUNC(DEBUG28, OUT),
K210_FUNC(DEBUG29, OUT),
K210_FUNC(DEBUG30, OUT),
K210_FUNC(DEBUG31, OUT),
};
#define PIN_CONFIG_OUTPUT_INVERT (PIN_CONFIG_END + 1)
#define PIN_CONFIG_INPUT_INVERT (PIN_CONFIG_END + 2)
static const struct pinconf_generic_params k210_pinconf_custom_params[] = {
{ "output-polarity-invert", PIN_CONFIG_OUTPUT_INVERT, 1 },
{ "input-polarity-invert", PIN_CONFIG_INPUT_INVERT, 1 },
};
/*
* Max drive strength in uA.
*/
static const int k210_pinconf_drive_strength[] = {
[0] = 11200,
[1] = 16800,
[2] = 22300,
[3] = 27800,
[4] = 33300,
[5] = 38700,
[6] = 44100,
[7] = 49500,
};
static int k210_pinconf_get_drive(unsigned int max_strength_ua)
{
int i;
for (i = K210_PC_DRIVE_MAX; i >= 0; i--) {
if (k210_pinconf_drive_strength[i] <= max_strength_ua)
return i;
}
return -EINVAL;
}
static void k210_pinmux_set_pin_function(struct pinctrl_dev *pctldev,
u32 pin, u32 func)
{
struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct k210_pcf_info *info = &k210_pcf_infos[func];
u32 mode = k210_pinconf_mode_id_to_mode[info->mode_id];
u32 val = func | mode;
dev_dbg(pdata->dev, "set pin %u function %s (%u) -> 0x%08x\n",
pin, info->name, func, val);
writel(val, &pdata->fpioa->pins[pin]);
}
static int k210_pinconf_set_param(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned int param, unsigned int arg)
{
struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev);
u32 val = readl(&pdata->fpioa->pins[pin]);
int drive;
dev_dbg(pdata->dev, "set pin %u param %u, arg 0x%x\n",
pin, param, arg);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
val &= ~K210_PC_BIAS_MASK;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!arg)
return -EINVAL;
val |= K210_PC_PD;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (!arg)
return -EINVAL;
val |= K210_PC_PU;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg *= 1000;
fallthrough;
case PIN_CONFIG_DRIVE_STRENGTH_UA:
drive = k210_pinconf_get_drive(arg);
if (drive < 0)
return drive;
val &= ~K210_PC_DRIVE_MASK;
val |= FIELD_PREP(K210_PC_DRIVE_MASK, drive);
break;
case PIN_CONFIG_INPUT_ENABLE:
if (arg)
val |= K210_PC_IE;
else
val &= ~K210_PC_IE;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (arg)
val |= K210_PC_ST;
else
val &= ~K210_PC_ST;
break;
case PIN_CONFIG_OUTPUT:
k210_pinmux_set_pin_function(pctldev, pin, K210_PCF_CONSTANT);
val = readl(&pdata->fpioa->pins[pin]);
val |= K210_PC_MODE_OUT;
if (!arg)
val |= K210_PC_DO_INV;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
if (arg)
val |= K210_PC_OE;
else
val &= ~K210_PC_OE;
break;
case PIN_CONFIG_SLEW_RATE:
if (arg)
val |= K210_PC_SL;
else
val &= ~K210_PC_SL;
break;
case PIN_CONFIG_OUTPUT_INVERT:
if (arg)
val |= K210_PC_DO_INV;
else
val &= ~K210_PC_DO_INV;
break;
case PIN_CONFIG_INPUT_INVERT:
if (arg)
val |= K210_PC_DI_INV;
else
val &= ~K210_PC_DI_INV;
break;
default:
return -EINVAL;
}
writel(val, &pdata->fpioa->pins[pin]);
return 0;
}
static int k210_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
unsigned int param, arg;
int i, ret;
if (WARN_ON(pin >= K210_NPINS))
return -EINVAL;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
ret = k210_pinconf_set_param(pctldev, pin, param, arg);
if (ret)
return ret;
}
return 0;
}
static void k210_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int pin)
{
struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev);
seq_printf(s, "%#x", readl(&pdata->fpioa->pins[pin]));
}
static int k210_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned long *configs,
unsigned int num_configs)
{
struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev);
unsigned int param, arg;
u32 bit;
int i;
/* Pins should be configured with pinmux, not groups*/
if (selector < K210_NPINS)
return -EINVAL;
/* Otherwise it's a power domain */
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
if (param != PIN_CONFIG_POWER_SOURCE)
return -EINVAL;
arg = pinconf_to_config_argument(configs[i]);
bit = BIT(selector - K210_NPINS);
regmap_update_bits(pdata->sysctl_map,
pdata->power_offset,
bit, arg ? bit : 0);
}
return 0;
}
static void k210_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int selector)
{
struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev);
int ret;
u32 val;
if (selector < K210_NPINS)
return k210_pinconf_dbg_show(pctldev, s, selector);
ret = regmap_read(pdata->sysctl_map, pdata->power_offset, &val);
if (ret) {
dev_err(pdata->dev, "Failed to read power reg\n");
return;
}
seq_printf(s, "%s: %s V", k210_group_names[selector],
val & BIT(selector - K210_NPINS) ? "1.8" : "3.3");
}
static const struct pinconf_ops k210_pinconf_ops = {
.is_generic = true,
.pin_config_set = k210_pinconf_set,
.pin_config_group_set = k210_pinconf_group_set,
.pin_config_dbg_show = k210_pinconf_dbg_show,
.pin_config_group_dbg_show = k210_pinconf_group_dbg_show,
};
static int k210_pinmux_get_function_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(k210_pcf_infos);
}
static const char *k210_pinmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return k210_pcf_infos[selector].name;
}
static int k210_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
/* Any function can be mapped to any pin */
*groups = k210_group_names;
*num_groups = K210_NPINS;
return 0;
}
static int k210_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
/* Can't mux power domains */
if (group >= K210_NPINS)
return -EINVAL;
k210_pinmux_set_pin_function(pctldev, group, function);
return 0;
}
static const struct pinmux_ops k210_pinmux_ops = {
.get_functions_count = k210_pinmux_get_function_count,
.get_function_name = k210_pinmux_get_function_name,
.get_function_groups = k210_pinmux_get_function_groups,
.set_mux = k210_pinmux_set_mux,
.strict = true,
};
static int k210_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return K210_NGROUPS;
}
static const char *k210_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return k210_group_names[group];
}
static int k210_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *npins)
{
if (group >= K210_NPINS) {
*pins = NULL;
*npins = 0;
return 0;
}
*pins = &k210_pins[group].number;
*npins = 1;
return 0;
}
static void k210_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static int k210_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
struct property *prop;
const __be32 *p;
int ret, pinmux_groups;
u32 pinmux_group;
unsigned long *configs = NULL;
unsigned int num_configs = 0;
unsigned int reserve = 0;
ret = of_property_count_strings(np, "groups");
if (!ret)
return pinconf_generic_dt_subnode_to_map(pctldev, np, map,
reserved_maps, num_maps,
PIN_MAP_TYPE_CONFIGS_GROUP);
pinmux_groups = of_property_count_u32_elems(np, "pinmux");
if (pinmux_groups <= 0) {
/* Ignore this node */
return 0;
}
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(pctldev->dev, "%pOF: could not parse node property\n",
np);
return ret;
}
reserve = pinmux_groups * (1 + num_configs);
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (ret < 0)
goto exit;
of_property_for_each_u32(np, "pinmux", prop, p, pinmux_group) {
const char *group_name, *func_name;
u32 pin = FIELD_GET(K210_PG_PIN, pinmux_group);
u32 func = FIELD_GET(K210_PG_FUNC, pinmux_group);
if (pin >= K210_NPINS) {
ret = -EINVAL;
goto exit;
}
group_name = k210_group_names[pin];
func_name = k210_pcf_infos[func].name;
dev_dbg(pctldev->dev, "Pinmux %s: pin %u func %s\n",
np->name, pin, func_name);
ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps,
num_maps, group_name,
func_name);
if (ret < 0) {
dev_err(pctldev->dev, "%pOF add mux map failed %d\n",
np, ret);
goto exit;
}
if (num_configs) {
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group_name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_PIN);
if (ret < 0) {
dev_err(pctldev->dev,
"%pOF add configs map failed %d\n",
np, ret);
goto exit;
}
}
}
ret = 0;
exit:
kfree(configs);
return ret;
}
static int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned int *num_maps)
{
unsigned int reserved_maps;
struct device_node *np;
int ret;
reserved_maps = 0;
*map = NULL;
*num_maps = 0;
ret = k210_pinctrl_dt_subnode_to_map(pctldev, np_config, map,
&reserved_maps, num_maps);
if (ret < 0)
goto err;
for_each_available_child_of_node(np_config, np) {
ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
of_node_put(np);
goto err;
}
}
return 0;
err:
pinctrl_utils_free_map(pctldev, *map, *num_maps);
return ret;
}
static const struct pinctrl_ops k210_pinctrl_ops = {
.get_groups_count = k210_pinctrl_get_groups_count,
.get_group_name = k210_pinctrl_get_group_name,
.get_group_pins = k210_pinctrl_get_group_pins,
.pin_dbg_show = k210_pinctrl_pin_dbg_show,
.dt_node_to_map = k210_pinctrl_dt_node_to_map,
.dt_free_map = pinconf_generic_dt_free_map,
};
static struct pinctrl_desc k210_pinctrl_desc = {
.name = "k210-pinctrl",
.pins = k210_pins,
.npins = K210_NPINS,
.pctlops = &k210_pinctrl_ops,
.pmxops = &k210_pinmux_ops,
.confops = &k210_pinconf_ops,
.custom_params = k210_pinconf_custom_params,
.num_custom_params = ARRAY_SIZE(k210_pinconf_custom_params),
};
static void k210_fpioa_init_ties(struct k210_fpioa_data *pdata)
{
struct k210_fpioa __iomem *fpioa = pdata->fpioa;
u32 val;
int i, j;
dev_dbg(pdata->dev, "Init pin ties\n");
/* Init pin functions input ties */
for (i = 0; i < ARRAY_SIZE(fpioa->tie_en); i++) {
val = 0;
for (j = 0; j < 32; j++) {
if (k210_pcf_infos[i * 32 + j].mode_id ==
K210_PC_DEFAULT_IN_TIE) {
dev_dbg(pdata->dev,
"tie_en function %d (%s)\n",
i * 32 + j,
k210_pcf_infos[i * 32 + j].name);
val |= BIT(j);
}
}
/* Set value before enable */
writel(val, &fpioa->tie_val[i]);
writel(val, &fpioa->tie_en[i]);
}
}
static int k210_fpioa_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct k210_fpioa_data *pdata;
int ret;
dev_info(dev, "K210 FPIOA pin controller\n");
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
pdata->fpioa = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->fpioa))
return PTR_ERR(pdata->fpioa);
pdata->clk = devm_clk_get(dev, "ref");
if (IS_ERR(pdata->clk))
return PTR_ERR(pdata->clk);
ret = clk_prepare_enable(pdata->clk);
if (ret)
return ret;
pdata->pclk = devm_clk_get_optional(dev, "pclk");
if (!IS_ERR(pdata->pclk)) {
ret = clk_prepare_enable(pdata->pclk);
if (ret)
goto disable_clk;
}
pdata->sysctl_map =
syscon_regmap_lookup_by_phandle_args(np,
"canaan,k210-sysctl-power",
1, &pdata->power_offset);
if (IS_ERR(pdata->sysctl_map)) {
ret = PTR_ERR(pdata->sysctl_map);
goto disable_pclk;
}
k210_fpioa_init_ties(pdata);
pdata->pctl = pinctrl_register(&k210_pinctrl_desc, dev, (void *)pdata);
if (IS_ERR(pdata->pctl)) {
ret = PTR_ERR(pdata->pctl);
goto disable_pclk;
}
return 0;
disable_pclk:
clk_disable_unprepare(pdata->pclk);
disable_clk:
clk_disable_unprepare(pdata->clk);
return ret;
}
static const struct of_device_id k210_fpioa_dt_ids[] = {
{ .compatible = "canaan,k210-fpioa" },
{ /* sentinel */ },
};
static struct platform_driver k210_fpioa_driver = {
.probe = k210_fpioa_probe,
.driver = {
.name = "k210-fpioa",
.of_match_table = k210_fpioa_dt_ids,
},
};
builtin_platform_driver(k210_fpioa_driver);
|
linux-master
|
drivers/pinctrl/pinctrl-k210.c
|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2019 Intel Corporation */
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#include "pinctrl-equilibrium.h"
#define PIN_NAME_FMT "io-%d"
#define PIN_NAME_LEN 10
#define PAD_REG_OFF 0x100
static void eqbr_gpio_disable_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
unsigned long flags;
raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
gpiochip_disable_irq(gc, offset);
}
static void eqbr_gpio_enable_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
unsigned long flags;
gc->direction_input(gc, offset);
gpiochip_enable_irq(gc, offset);
raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
}
static void eqbr_gpio_ack_irq(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
unsigned long flags;
raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
}
static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
{
eqbr_gpio_disable_irq(d);
eqbr_gpio_ack_irq(d);
}
static inline void eqbr_cfg_bit(void __iomem *addr,
unsigned int offset, unsigned int set)
{
if (set)
writel(readl(addr) | BIT(offset), addr);
else
writel(readl(addr) & ~BIT(offset), addr);
}
static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
struct eqbr_gpio_ctrl *gctrl,
unsigned int offset)
{
unsigned long flags;
raw_spin_lock_irqsave(&gctrl->lock, flags);
eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
return 0;
}
static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
unsigned int offset = irqd_to_hwirq(d);
struct gpio_irq_type it;
memset(&it, 0, sizeof(it));
if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
return 0;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
it.trig_type = GPIO_EDGE_TRIG;
it.edge_type = GPIO_SINGLE_EDGE;
it.logic_type = GPIO_POSITIVE_TRIG;
break;
case IRQ_TYPE_EDGE_FALLING:
it.trig_type = GPIO_EDGE_TRIG;
it.edge_type = GPIO_SINGLE_EDGE;
it.logic_type = GPIO_NEGATIVE_TRIG;
break;
case IRQ_TYPE_EDGE_BOTH:
it.trig_type = GPIO_EDGE_TRIG;
it.edge_type = GPIO_BOTH_EDGE;
it.logic_type = GPIO_POSITIVE_TRIG;
break;
case IRQ_TYPE_LEVEL_HIGH:
it.trig_type = GPIO_LEVEL_TRIG;
it.edge_type = GPIO_SINGLE_EDGE;
it.logic_type = GPIO_POSITIVE_TRIG;
break;
case IRQ_TYPE_LEVEL_LOW:
it.trig_type = GPIO_LEVEL_TRIG;
it.edge_type = GPIO_SINGLE_EDGE;
it.logic_type = GPIO_NEGATIVE_TRIG;
break;
default:
return -EINVAL;
}
eqbr_irq_type_cfg(&it, gctrl, offset);
if (it.trig_type == GPIO_EDGE_TRIG)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
return 0;
}
static void eqbr_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
struct irq_chip *ic = irq_desc_get_chip(desc);
unsigned long pins, offset;
chained_irq_enter(ic, desc);
pins = readl(gctrl->membase + GPIO_IRNCR);
for_each_set_bit(offset, &pins, gc->ngpio)
generic_handle_domain_irq(gc->irq.domain, offset);
chained_irq_exit(ic, desc);
}
static const struct irq_chip eqbr_irq_chip = {
.name = "gpio_irq",
.irq_mask = eqbr_gpio_disable_irq,
.irq_unmask = eqbr_gpio_enable_irq,
.irq_ack = eqbr_gpio_ack_irq,
.irq_mask_ack = eqbr_gpio_mask_ack_irq,
.irq_set_type = eqbr_gpio_set_irq_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
{
struct gpio_irq_chip *girq;
struct gpio_chip *gc;
gc = &gctrl->chip;
gc->label = gctrl->name;
gc->fwnode = gctrl->fwnode;
if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {
dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
gctrl->name);
return 0;
}
girq = &gctrl->chip.irq;
gpio_irq_chip_set_chip(girq, &eqbr_irq_chip);
girq->parent_handler = eqbr_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->parents[0] = gctrl->virq;
return 0;
}
static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
{
struct device *dev = drvdata->dev;
struct eqbr_gpio_ctrl *gctrl;
struct device_node *np;
struct resource res;
int i, ret;
for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
gctrl = drvdata->gpio_ctrls + i;
np = to_of_node(gctrl->fwnode);
gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
if (!gctrl->name)
return -ENOMEM;
if (of_address_to_resource(np, 0, &res)) {
dev_err(dev, "Failed to get GPIO register address\n");
return -ENXIO;
}
gctrl->membase = devm_ioremap_resource(dev, &res);
if (IS_ERR(gctrl->membase))
return PTR_ERR(gctrl->membase);
gctrl->virq = irq_of_parse_and_map(np, 0);
if (!gctrl->virq) {
dev_err(dev, "%s: failed to parse and map irq\n",
gctrl->name);
return -ENXIO;
}
raw_spin_lock_init(&gctrl->lock);
ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
gctrl->membase + GPIO_IN,
gctrl->membase + GPIO_OUTSET,
gctrl->membase + GPIO_OUTCLR,
gctrl->membase + GPIO_DIR,
NULL, 0);
if (ret) {
dev_err(dev, "unable to init generic GPIO\n");
return ret;
}
ret = gpiochip_setup(dev, gctrl);
if (ret)
return ret;
ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
if (ret)
return ret;
}
return 0;
}
static inline struct eqbr_pin_bank
*find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
{
struct eqbr_pin_bank *bank;
int i;
for (i = 0; i < pctl->nr_banks; i++) {
bank = &pctl->pin_banks[i];
if (pin >= bank->pin_base &&
(pin - bank->pin_base) < bank->nr_pins)
return bank;
}
return NULL;
}
static const struct pinctrl_ops eqbr_pctl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
unsigned int pmx, unsigned int pin)
{
struct eqbr_pin_bank *bank;
unsigned long flags;
unsigned int offset;
void __iomem *mem;
bank = find_pinbank_via_pin(pctl, pin);
if (!bank) {
dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
return -ENODEV;
}
mem = bank->membase;
offset = pin - bank->pin_base;
if (!(bank->aval_pinmap & BIT(offset))) {
dev_err(pctl->dev,
"PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
pin, bank->pin_base, bank->aval_pinmap);
return -ENODEV;
}
raw_spin_lock_irqsave(&pctl->lock, flags);
writel(pmx, mem + (offset * 4));
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
}
static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
unsigned int *pinmux;
int i;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
pinmux = grp->data;
for (i = 0; i < grp->num_pins; i++)
eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
return 0;
}
static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
}
static const struct pinmux_ops eqbr_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = eqbr_pinmux_set_mux,
.gpio_request_enable = eqbr_pinmux_gpio_request,
.strict = true,
};
static int get_drv_cur(void __iomem *mem, unsigned int offset)
{
unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
unsigned int pin_offset = offset % DRV_CUR_PINS;
return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
}
static struct eqbr_gpio_ctrl
*get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl,
struct eqbr_pin_bank *bank)
{
int i;
for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
if (pctl->gpio_ctrls[i].bank == bank)
return &pctl->gpio_ctrls[i];
}
return NULL;
}
static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
struct eqbr_gpio_ctrl *gctrl;
struct eqbr_pin_bank *bank;
unsigned long flags;
unsigned int offset;
void __iomem *mem;
u32 val;
bank = find_pinbank_via_pin(pctl, pin);
if (!bank) {
dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
return -ENODEV;
}
mem = bank->membase;
offset = pin - bank->pin_base;
if (!(bank->aval_pinmap & BIT(offset))) {
dev_err(pctl->dev,
"PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
pin, bank->pin_base, bank->aval_pinmap);
return -ENODEV;
}
raw_spin_lock_irqsave(&pctl->lock, flags);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
val = !!(readl(mem + REG_PUEN) & BIT(offset));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
val = !!(readl(mem + REG_PDEN) & BIT(offset));
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
val = !!(readl(mem + REG_OD) & BIT(offset));
break;
case PIN_CONFIG_DRIVE_STRENGTH:
val = get_drv_cur(mem, offset);
break;
case PIN_CONFIG_SLEW_RATE:
val = !!(readl(mem + REG_SRC) & BIT(offset));
break;
case PIN_CONFIG_OUTPUT_ENABLE:
gctrl = get_gpio_ctrls_via_bank(pctl, bank);
if (!gctrl) {
dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
bank->pin_base, pin);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return -ENODEV;
}
val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
break;
default:
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return -ENOTSUPP;
}
raw_spin_unlock_irqrestore(&pctl->lock, flags);
*config = pinconf_to_config_packed(param, val);
;
return 0;
}
static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
struct eqbr_gpio_ctrl *gctrl;
enum pin_config_param param;
struct eqbr_pin_bank *bank;
unsigned int val, offset;
struct gpio_chip *gc;
unsigned long flags;
void __iomem *mem;
u32 regval, mask;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
val = pinconf_to_config_argument(configs[i]);
bank = find_pinbank_via_pin(pctl, pin);
if (!bank) {
dev_err(pctl->dev,
"Couldn't find pin bank for pin %u\n", pin);
return -ENODEV;
}
mem = bank->membase;
offset = pin - bank->pin_base;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
mem += REG_PUEN;
mask = BIT(offset);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
mem += REG_PDEN;
mask = BIT(offset);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
mem += REG_OD;
mask = BIT(offset);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
mem += REG_DRCC(offset / DRV_CUR_PINS);
offset = (offset % DRV_CUR_PINS) * 2;
mask = GENMASK(1, 0) << offset;
break;
case PIN_CONFIG_SLEW_RATE:
mem += REG_SRC;
mask = BIT(offset);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
gctrl = get_gpio_ctrls_via_bank(pctl, bank);
if (!gctrl) {
dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
bank->pin_base, pin);
return -ENODEV;
}
gc = &gctrl->chip;
gc->direction_output(gc, offset, 0);
continue;
default:
return -ENOTSUPP;
}
raw_spin_lock_irqsave(&pctl->lock, flags);
regval = readl(mem);
regval = (regval & ~mask) | ((val << offset) & mask);
writel(regval, mem);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
}
return 0;
}
static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *config)
{
unsigned int i, npins, old = 0;
const unsigned int *pins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (eqbr_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
if (i && old != *config)
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops eqbr_pinconf_ops = {
.is_generic = true,
.pin_config_get = eqbr_pinconf_get,
.pin_config_set = eqbr_pinconf_set,
.pin_config_group_get = eqbr_pinconf_group_get,
.pin_config_group_set = eqbr_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
unsigned int nr_funcs, unsigned int *idx)
{
int i;
if (!funcs)
return false;
for (i = 0; i < nr_funcs; i++) {
if (funcs[i].name && !strcmp(funcs[i].name, name)) {
*idx = i;
return true;
}
}
return false;
}
static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
unsigned int *nr_funcs, funcs_util_ops op)
{
struct device_node *node = dev->of_node;
struct device_node *np;
struct property *prop;
const char *fn_name;
unsigned int fid;
int i, j;
i = 0;
for_each_child_of_node(node, np) {
prop = of_find_property(np, "groups", NULL);
if (!prop)
continue;
if (of_property_read_string(np, "function", &fn_name)) {
/* some groups may not have function, it's OK */
dev_dbg(dev, "Group %s: not function binded!\n",
(char *)prop->value);
continue;
}
switch (op) {
case OP_COUNT_NR_FUNCS:
if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
*nr_funcs = *nr_funcs + 1;
break;
case OP_ADD_FUNCS:
if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
funcs[i].name = fn_name;
break;
case OP_COUNT_NR_FUNC_GRPS:
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
funcs[fid].nr_groups++;
break;
case OP_ADD_FUNC_GRPS:
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
for (j = 0; j < funcs[fid].nr_groups; j++)
if (!funcs[fid].groups[j])
break;
funcs[fid].groups[j] = prop->value;
}
break;
default:
of_node_put(np);
return -EINVAL;
}
i++;
}
return 0;
}
static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
{
struct device *dev = drvdata->dev;
struct eqbr_pmx_func *funcs = NULL;
unsigned int nr_funcs = 0;
int i, ret;
ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
if (ret)
return ret;
funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
if (!funcs)
return -ENOMEM;
ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
if (ret)
return ret;
ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
if (ret)
return ret;
for (i = 0; i < nr_funcs; i++) {
if (!funcs[i].nr_groups)
continue;
funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
sizeof(*(funcs[i].groups)),
GFP_KERNEL);
if (!funcs[i].groups)
return -ENOMEM;
}
ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
if (ret)
return ret;
for (i = 0; i < nr_funcs; i++) {
/* Ignore the same function with multiple groups */
if (funcs[i].name == NULL)
continue;
ret = pinmux_generic_add_function(drvdata->pctl_dev,
funcs[i].name,
funcs[i].groups,
funcs[i].nr_groups,
drvdata);
if (ret < 0) {
dev_err(dev, "Failed to register function %s\n",
funcs[i].name);
return ret;
}
}
return 0;
}
static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
{
struct device *dev = drvdata->dev;
struct device_node *node = dev->of_node;
unsigned int *pinmux, pin_id, pinmux_id;
struct group_desc group;
struct device_node *np;
struct property *prop;
int j, err;
for_each_child_of_node(node, np) {
prop = of_find_property(np, "groups", NULL);
if (!prop)
continue;
group.num_pins = of_property_count_u32_elems(np, "pins");
if (group.num_pins < 0) {
dev_err(dev, "No pins in the group: %s\n", prop->name);
of_node_put(np);
return -EINVAL;
}
group.name = prop->value;
group.pins = devm_kcalloc(dev, group.num_pins,
sizeof(*(group.pins)), GFP_KERNEL);
if (!group.pins) {
of_node_put(np);
return -ENOMEM;
}
pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
GFP_KERNEL);
if (!pinmux) {
of_node_put(np);
return -ENOMEM;
}
for (j = 0; j < group.num_pins; j++) {
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
dev_err(dev, "Group %s: Read intel pins id failed\n",
group.name);
of_node_put(np);
return -EINVAL;
}
if (pin_id >= drvdata->pctl_desc.npins) {
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
group.name, j, pin_id);
of_node_put(np);
return -EINVAL;
}
group.pins[j] = pin_id;
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
group.name);
of_node_put(np);
return -EINVAL;
}
pinmux[j] = pinmux_id;
}
err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
group.pins, group.num_pins,
pinmux);
if (err < 0) {
dev_err(dev, "Failed to register group %s\n", group.name);
of_node_put(np);
return err;
}
memset(&group, 0, sizeof(group));
pinmux = NULL;
}
return 0;
}
static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
{
struct pinctrl_desc *pctl_desc;
struct pinctrl_pin_desc *pdesc;
struct device *dev;
unsigned int nr_pins;
char *pin_names;
int i, ret;
dev = drvdata->dev;
pctl_desc = &drvdata->pctl_desc;
pctl_desc->name = "eqbr-pinctrl";
pctl_desc->owner = THIS_MODULE;
pctl_desc->pctlops = &eqbr_pctl_ops;
pctl_desc->pmxops = &eqbr_pinmux_ops;
pctl_desc->confops = &eqbr_pinconf_ops;
raw_spin_lock_init(&drvdata->lock);
for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
nr_pins += drvdata->pin_banks[i].nr_pins;
pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
if (!pdesc)
return -ENOMEM;
pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
if (!pin_names)
return -ENOMEM;
for (i = 0; i < nr_pins; i++) {
sprintf(pin_names, PIN_NAME_FMT, i);
pdesc[i].number = i;
pdesc[i].name = pin_names;
pin_names += PIN_NAME_LEN;
}
pctl_desc->pins = pdesc;
pctl_desc->npins = nr_pins;
dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
&drvdata->pctl_dev);
if (ret)
return ret;
ret = eqbr_build_groups(drvdata);
if (ret) {
dev_err(dev, "Failed to build groups\n");
return ret;
}
ret = eqbr_build_functions(drvdata);
if (ret) {
dev_err(dev, "Failed to build functions\n");
return ret;
}
return pinctrl_enable(drvdata->pctl_dev);
}
static int pinbank_init(struct device_node *np,
struct eqbr_pinctrl_drv_data *drvdata,
struct eqbr_pin_bank *bank, unsigned int id)
{
struct device *dev = drvdata->dev;
struct of_phandle_args spec;
int ret;
bank->membase = drvdata->membase + id * PAD_REG_OFF;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
if (ret) {
dev_err(dev, "gpio-range not available!\n");
return ret;
}
bank->pin_base = spec.args[1];
bank->nr_pins = spec.args[2];
bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
bank->id = id;
dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
id, bank->membase, bank->pin_base,
bank->nr_pins, bank->aval_pinmap);
return ret;
}
static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
{
struct device *dev = drvdata->dev;
struct device_node *np_gpio;
struct eqbr_gpio_ctrl *gctrls;
struct eqbr_pin_bank *banks;
int i, nr_gpio;
/* Count gpio bank number */
nr_gpio = 0;
for_each_node_by_name(np_gpio, "gpio") {
if (of_device_is_available(np_gpio))
nr_gpio++;
}
if (!nr_gpio) {
dev_err(dev, "NO pin bank available!\n");
return -ENODEV;
}
/* Count pin bank number and gpio controller number */
banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
if (!banks)
return -ENOMEM;
gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
if (!gctrls)
return -ENOMEM;
dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
/* Initialize Pin bank */
i = 0;
for_each_node_by_name(np_gpio, "gpio") {
if (!of_device_is_available(np_gpio))
continue;
pinbank_init(np_gpio, drvdata, banks + i, i);
gctrls[i].fwnode = of_fwnode_handle(np_gpio);
gctrls[i].bank = banks + i;
i++;
}
drvdata->pin_banks = banks;
drvdata->nr_banks = nr_gpio;
drvdata->gpio_ctrls = gctrls;
drvdata->nr_gpio_ctrls = nr_gpio;
return 0;
}
static int eqbr_pinctrl_probe(struct platform_device *pdev)
{
struct eqbr_pinctrl_drv_data *drvdata;
struct device *dev = &pdev->dev;
int ret;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
drvdata->dev = dev;
drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(drvdata->membase))
return PTR_ERR(drvdata->membase);
ret = pinbank_probe(drvdata);
if (ret)
return ret;
ret = pinctrl_reg(drvdata);
if (ret)
return ret;
ret = gpiolib_reg(drvdata);
if (ret)
return ret;
platform_set_drvdata(pdev, drvdata);
return 0;
}
static const struct of_device_id eqbr_pinctrl_dt_match[] = {
{ .compatible = "intel,lgm-io" },
{}
};
MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match);
static struct platform_driver eqbr_pinctrl_driver = {
.probe = eqbr_pinctrl_probe,
.driver = {
.name = "eqbr-pinctrl",
.of_match_table = eqbr_pinctrl_dt_match,
},
};
module_platform_driver(eqbr_pinctrl_driver);
MODULE_AUTHOR("Zhu Yixin <[email protected]>, Rahul Tanwar <[email protected]>");
MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-equilibrium.c
|
// SPDX-License-Identifier: GPL-2.0-only
/* MCP23S08 I2C GPIO driver */
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "pinctrl-mcp23s08.h"
static int mcp230xx_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device *dev = &client->dev;
unsigned int type = id->driver_data;
struct mcp23s08 *mcp;
int ret;
mcp = devm_kzalloc(dev, sizeof(*mcp), GFP_KERNEL);
if (!mcp)
return -ENOMEM;
switch (type) {
case MCP_TYPE_008:
mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap);
mcp->reg_shift = 0;
mcp->chip.ngpio = 8;
mcp->chip.label = "mcp23008";
break;
case MCP_TYPE_017:
mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap);
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = "mcp23017";
break;
case MCP_TYPE_018:
mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap);
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = "mcp23018";
break;
default:
dev_err(dev, "invalid device type (%d)\n", type);
return -EINVAL;
}
if (IS_ERR(mcp->regmap))
return PTR_ERR(mcp->regmap);
mcp->irq = client->irq;
mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
ret = mcp23s08_probe_one(mcp, dev, client->addr, type, -1);
if (ret)
return ret;
i2c_set_clientdata(client, mcp);
return 0;
}
static const struct i2c_device_id mcp230xx_id[] = {
{ "mcp23008", MCP_TYPE_008 },
{ "mcp23017", MCP_TYPE_017 },
{ "mcp23018", MCP_TYPE_018 },
{ }
};
MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
static const struct of_device_id mcp23s08_i2c_of_match[] = {
{
.compatible = "microchip,mcp23008",
.data = (void *) MCP_TYPE_008,
},
{
.compatible = "microchip,mcp23017",
.data = (void *) MCP_TYPE_017,
},
{
.compatible = "microchip,mcp23018",
.data = (void *) MCP_TYPE_018,
},
/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
{
.compatible = "mcp,mcp23008",
.data = (void *) MCP_TYPE_008,
},
{
.compatible = "mcp,mcp23017",
.data = (void *) MCP_TYPE_017,
},
{ }
};
MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
static struct i2c_driver mcp230xx_driver = {
.driver = {
.name = "mcp230xx",
.of_match_table = mcp23s08_i2c_of_match,
},
.probe = mcp230xx_probe,
.id_table = mcp230xx_id,
};
static int __init mcp23s08_i2c_init(void)
{
return i2c_add_driver(&mcp230xx_driver);
}
/*
* Register after I²C postcore initcall and before
* subsys initcalls that may rely on these GPIOs.
*/
subsys_initcall(mcp23s08_i2c_init);
static void mcp23s08_i2c_exit(void)
{
i2c_del_driver(&mcp230xx_driver);
}
module_exit(mcp23s08_i2c_exit);
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-mcp23s08_i2c.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl driver for Rockchip SoCs
*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*
* With some ideas taken from pinctrl-samsung:
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2012 Linaro Ltd
* https://www.linaro.org
*
* and pinctrl-at91:
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/string_helpers.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-rockchip.h"
/*
* Generate a bitmask for setting a value (v) with a write mask bit in hiword
* register 31:16 area.
*/
#define WRITE_MASK_VAL(h, l, v) \
(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
/*
* Encode variants of iomux registers into a type variable
*/
#define IOMUX_GPIO_ONLY BIT(0)
#define IOMUX_WIDTH_4BIT BIT(1)
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
#define IOMUX_L_SOURCE_PMU BIT(6)
#define PIN_BANK(id, pins, label) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
}, \
}
#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = type0, .offset = -1 }, \
{ .drv_type = type1, .offset = -1 }, \
{ .drv_type = type2, .offset = -1 }, \
{ .drv_type = type3, .offset = -1 }, \
}, \
}
#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
iom2, iom3, pull0, pull1, \
pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
drv2, drv3, pull0, pull1, \
pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = -1 }, \
{ .drv_type = drv1, .offset = -1 }, \
{ .drv_type = drv2, .offset = -1 }, \
{ .drv_type = drv3, .offset = -1 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
iom3, offset0, offset1, offset2, \
offset3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
}
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
offset2, offset3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = offset0 }, \
{ .drv_type = drv1, .offset = offset1 }, \
{ .drv_type = drv2, .offset = offset2 }, \
{ .drv_type = drv3, .offset = offset3 }, \
}, \
}
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
offset2, offset3, pull0, \
pull1, pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = offset0 }, \
{ .drv_type = drv1, .offset = offset1 }, \
{ .drv_type = drv2, .offset = offset2 }, \
{ .drv_type = drv3, .offset = offset3 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
{ \
.bank_num = ID, \
.pin = PIN, \
.func = FUNC, \
.route_offset = REG, \
.route_val = VAL, \
.route_location = FLAG, \
}
#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
static struct regmap_config rockchip_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static inline const struct rockchip_pin_group *pinctrl_name_to_group(
const struct rockchip_pinctrl *info,
const char *name)
{
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name))
return &info->groups[i];
}
return NULL;
}
/*
* given a pin number that is local to a pin controller, find out the pin bank
* and the register base of the pin bank.
*/
static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
unsigned pin)
{
struct rockchip_pin_bank *b = info->ctrl->pin_banks;
while (pin >= (b->pin_base + b->nr_pins))
b++;
return b;
}
static struct rockchip_pin_bank *bank_num_to_bank(
struct rockchip_pinctrl *info,
unsigned num)
{
struct rockchip_pin_bank *b = info->ctrl->pin_banks;
int i;
for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
if (b->bank_num == num)
return b;
}
return ERR_PTR(-EINVAL);
}
/*
* Pinctrl_ops handling
*/
static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->ngroups;
}
static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->groups[selector].name;
}
static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector, const unsigned **pins,
unsigned *npins)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*npins = info->groups[selector].npins;
return 0;
}
static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct rockchip_pin_group *grp;
struct device *dev = info->dev;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num = 1;
int i;
/*
* first find the group of this node and check if we need to create
* config maps for pins
*/
grp = pinctrl_name_to_group(info, np->name);
if (!grp) {
dev_err(dev, "unable to find group for node %pOFn\n", np);
return -EINVAL;
}
map_num += grp->npins;
new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
kfree(new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = 0; i < grp->npins; i++) {
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[i].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i]);
new_map[i].data.configs.configs = grp->data[i].configs;
new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
}
dev_dbg(dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
kfree(map);
}
static const struct pinctrl_ops rockchip_pctrl_ops = {
.get_groups_count = rockchip_get_groups_count,
.get_group_name = rockchip_get_group_name,
.get_group_pins = rockchip_get_group_pins,
.dt_node_to_map = rockchip_dt_node_to_map,
.dt_free_map = rockchip_dt_free_map,
};
/*
* Hardware access
*/
static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
{
.num = 1,
.pin = 0,
.reg = 0x418,
.bit = 0,
.mask = 0x3
}, {
.num = 1,
.pin = 1,
.reg = 0x418,
.bit = 2,
.mask = 0x3
}, {
.num = 1,
.pin = 2,
.reg = 0x418,
.bit = 4,
.mask = 0x3
}, {
.num = 1,
.pin = 3,
.reg = 0x418,
.bit = 6,
.mask = 0x3
}, {
.num = 1,
.pin = 4,
.reg = 0x418,
.bit = 8,
.mask = 0x3
}, {
.num = 1,
.pin = 5,
.reg = 0x418,
.bit = 10,
.mask = 0x3
}, {
.num = 1,
.pin = 6,
.reg = 0x418,
.bit = 12,
.mask = 0x3
}, {
.num = 1,
.pin = 7,
.reg = 0x418,
.bit = 14,
.mask = 0x3
}, {
.num = 1,
.pin = 8,
.reg = 0x41c,
.bit = 0,
.mask = 0x3
}, {
.num = 1,
.pin = 9,
.reg = 0x41c,
.bit = 2,
.mask = 0x3
},
};
static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
{
.num = 0,
.pin = 20,
.reg = 0x10000,
.bit = 0,
.mask = 0xf
},
{
.num = 0,
.pin = 21,
.reg = 0x10000,
.bit = 4,
.mask = 0xf
},
{
.num = 0,
.pin = 22,
.reg = 0x10000,
.bit = 8,
.mask = 0xf
},
{
.num = 0,
.pin = 23,
.reg = 0x10000,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
.pin = 20,
.reg = 0xe8,
.bit = 0,
.mask = 0x7
}, {
.num = 2,
.pin = 21,
.reg = 0xe8,
.bit = 4,
.mask = 0x7
}, {
.num = 2,
.pin = 22,
.reg = 0xe8,
.bit = 8,
.mask = 0x7
}, {
.num = 2,
.pin = 23,
.reg = 0xe8,
.bit = 12,
.mask = 0x7
}, {
.num = 2,
.pin = 24,
.reg = 0xd4,
.bit = 12,
.mask = 0x7
},
};
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
{
/* gpio1b6_sel */
.num = 1,
.pin = 14,
.reg = 0x28,
.bit = 12,
.mask = 0xf
}, {
/* gpio1b7_sel */
.num = 1,
.pin = 15,
.reg = 0x2c,
.bit = 0,
.mask = 0x3
}, {
/* gpio1c2_sel */
.num = 1,
.pin = 18,
.reg = 0x30,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c3_sel */
.num = 1,
.pin = 19,
.reg = 0x30,
.bit = 8,
.mask = 0xf
}, {
/* gpio1c4_sel */
.num = 1,
.pin = 20,
.reg = 0x30,
.bit = 12,
.mask = 0xf
}, {
/* gpio1c5_sel */
.num = 1,
.pin = 21,
.reg = 0x34,
.bit = 0,
.mask = 0xf
}, {
/* gpio1c6_sel */
.num = 1,
.pin = 22,
.reg = 0x34,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c7_sel */
.num = 1,
.pin = 23,
.reg = 0x34,
.bit = 8,
.mask = 0xf
}, {
/* gpio2a2_sel */
.num = 2,
.pin = 2,
.reg = 0x40,
.bit = 4,
.mask = 0x3
}, {
/* gpio2a3_sel */
.num = 2,
.pin = 3,
.reg = 0x40,
.bit = 6,
.mask = 0x3
}, {
/* gpio2c0_sel */
.num = 2,
.pin = 16,
.reg = 0x50,
.bit = 0,
.mask = 0x3
}, {
/* gpio3b2_sel */
.num = 3,
.pin = 10,
.reg = 0x68,
.bit = 4,
.mask = 0x3
}, {
/* gpio3b3_sel */
.num = 3,
.pin = 11,
.reg = 0x68,
.bit = 6,
.mask = 0x3
}, {
/* gpio3b4_sel */
.num = 3,
.pin = 12,
.reg = 0x68,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b5_sel */
.num = 3,
.pin = 13,
.reg = 0x68,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
.pin = 12,
.reg = 0x24,
.bit = 8,
.mask = 0x3
}, {
.num = 2,
.pin = 15,
.reg = 0x28,
.bit = 0,
.mask = 0x7
}, {
.num = 2,
.pin = 23,
.reg = 0x30,
.bit = 14,
.mask = 0x3
},
};
static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
for (i = 0; i < ctrl->niomux_recalced; i++) {
data = &ctrl->iomux_recalced[i];
if (data->num == bank->bank_num &&
data->pin == pin)
break;
}
if (i >= ctrl->niomux_recalced)
return;
*reg = data->reg;
*mask = data->mask;
*bit = data->bit;
}
static struct rockchip_mux_route_data px30_mux_route_data[] = {
RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
};
static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
};
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
};
static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
};
static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
};
static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
};
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
};
static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
};
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *loc, u32 *reg, u32 *value)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_route_data *data;
int i;
for (i = 0; i < ctrl->niomux_routes; i++) {
data = &ctrl->iomux_routes[i];
if ((data->bank_num == bank->bank_num) &&
(data->pin == pin) && (data->func == mux))
break;
}
if (i >= ctrl->niomux_routes)
return false;
*loc = data->route_location;
*reg = data->route_offset;
*value = data->route_val;
return true;
}
static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
unsigned int val;
int reg, ret, mask, mux_type;
u8 bit;
if (iomux_num > 3)
return -EINVAL;
if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
dev_err(info->dev, "pin %d is unrouted\n", pin);
return -EINVAL;
}
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
if (mux_type & IOMUX_WIDTH_4BIT) {
if ((pin % 8) >= 4)
reg += 0x4;
bit = (pin % 4) * 4;
mask = 0xf;
} else if (mux_type & IOMUX_WIDTH_3BIT) {
if ((pin % 8) >= 5)
reg += 0x4;
bit = (pin % 8 % 5) * 3;
mask = 0x7;
} else {
bit = (pin % 8) * 2;
mask = 0x3;
}
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
u32 reg0 = 0;
reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
ret = regmap_read(regmap, reg0, &val);
if (ret)
return ret;
if (!(val & BIT(8)))
return ((val >> bit) & mask);
reg = reg + 0x8000; /* BUS_IOC_BASE */
regmap = info->regmap_base;
}
} else if (bank->bank_num > 0) {
reg += 0x8000; /* BUS_IOC_BASE */
}
}
ret = regmap_read(regmap, reg, &val);
if (ret)
return ret;
return ((val >> bit) & mask);
}
static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct device *dev = info->dev;
int iomux_num = (pin / 8);
if (iomux_num > 3)
return -EINVAL;
if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
dev_err(dev, "pin %d is unrouted\n", pin);
return -EINVAL;
}
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
if (mux != RK_FUNC_GPIO) {
dev_err(dev, "pin %d only supports a gpio mux\n", pin);
return -ENOTSUPP;
}
}
return 0;
}
/*
* Set a new mux function for a pin.
*
* The register is divided into the upper and lower 16 bit. When changing
* a value, the previous register value is not read and changed. Instead
* it seems the changed bits are marked in the upper 16 bit, while the
* changed value gets set in the same offset in the lower 16 bit.
* All pin settings seem to be 2 bit wide in both the upper and lower
* parts.
* @bank: pin bank to change
* @pin: pin to change
* @mux: new mux function to set
*/
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, rmask, route_location, route_reg, route_val;
ret = rockchip_verify_mux(bank, pin, mux);
if (ret < 0)
return ret;
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return 0;
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
regmap = info->regmap_pmu;
else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
else
regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
if (mux_type & IOMUX_WIDTH_4BIT) {
if ((pin % 8) >= 4)
reg += 0x4;
bit = (pin % 4) * 4;
mask = 0xf;
} else if (mux_type & IOMUX_WIDTH_3BIT) {
if ((pin % 8) >= 5)
reg += 0x4;
bit = (pin % 8 % 5) * 3;
mask = 0x7;
} else {
bit = (pin % 8) * 2;
mask = 0x3;
}
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
if (mux < 8) {
reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
} else {
u32 reg0 = 0;
reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= 8 << bit;
ret = regmap_update_bits(regmap, reg0, rmask, data);
reg0 = reg + 0x8000; /* BUS_IOC_BASE */
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= mux << bit;
regmap = info->regmap_base;
ret |= regmap_update_bits(regmap, reg0, rmask, data);
}
} else {
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
}
return ret;
} else if (bank->bank_num > 0) {
reg += 0x8000; /* BUS_IOC_BASE */
}
}
if (mux > mask)
return -EINVAL;
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_location,
&route_reg, &route_val)) {
struct regmap *route_regmap = regmap;
/* handle special locations */
switch (route_location) {
case ROCKCHIP_ROUTE_PMU:
route_regmap = info->regmap_pmu;
break;
case ROCKCHIP_ROUTE_GRF:
route_regmap = info->regmap_base;
break;
}
ret = regmap_write(route_regmap, route_reg, route_val);
if (ret)
return ret;
}
}
data = (mask << (bit + 16));
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
return ret;
}
#define PX30_PULL_PMU_OFFSET 0x10
#define PX30_PULL_GRF_OFFSET 0x60
#define PX30_PULL_BITS_PER_PIN 2
#define PX30_PULL_PINS_PER_REG 8
#define PX30_PULL_BANK_STRIDE 16
static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = PX30_PULL_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = PX30_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
}
*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % PX30_PULL_PINS_PER_REG);
*bit *= PX30_PULL_BITS_PER_PIN;
return 0;
}
#define PX30_DRV_PMU_OFFSET 0x20
#define PX30_DRV_GRF_OFFSET 0xf0
#define PX30_DRV_BITS_PER_PIN 2
#define PX30_DRV_PINS_PER_REG 8
#define PX30_DRV_BANK_STRIDE 16
static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = PX30_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = PX30_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
}
*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % PX30_DRV_PINS_PER_REG);
*bit *= PX30_DRV_BITS_PER_PIN;
return 0;
}
#define PX30_SCHMITT_PMU_OFFSET 0x38
#define PX30_SCHMITT_GRF_OFFSET 0xc0
#define PX30_SCHMITT_PINS_PER_PMU_REG 16
#define PX30_SCHMITT_BANK_STRIDE 16
#define PX30_SCHMITT_PINS_PER_GRF_REG 8
static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = PX30_SCHMITT_PMU_OFFSET;
pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = PX30_SCHMITT_GRF_OFFSET;
pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RV1108_PULL_PMU_OFFSET 0x10
#define RV1108_PULL_OFFSET 0x110
#define RV1108_PULL_PINS_PER_REG 8
#define RV1108_PULL_BITS_PER_PIN 2
#define RV1108_PULL_BANK_STRIDE 16
static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RV1108_PULL_PMU_OFFSET;
} else {
*reg = RV1108_PULL_OFFSET;
*regmap = info->regmap_base;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
*bit *= RV1108_PULL_BITS_PER_PIN;
return 0;
}
#define RV1108_DRV_PMU_OFFSET 0x20
#define RV1108_DRV_GRF_OFFSET 0x210
#define RV1108_DRV_BITS_PER_PIN 2
#define RV1108_DRV_PINS_PER_REG 8
#define RV1108_DRV_BANK_STRIDE 16
static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RV1108_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RV1108_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1108_DRV_PINS_PER_REG;
*bit *= RV1108_DRV_BITS_PER_PIN;
return 0;
}
#define RV1108_SCHMITT_PMU_OFFSET 0x30
#define RV1108_SCHMITT_GRF_OFFSET 0x388
#define RV1108_SCHMITT_BANK_STRIDE 8
#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RV1108_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = RV1108_SCHMITT_GRF_OFFSET;
pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RV1126_PULL_PMU_OFFSET 0x40
#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
#define RV1126_PULL_PINS_PER_REG 8
#define RV1126_PULL_BITS_PER_PIN 2
#define RV1126_PULL_BANK_STRIDE 16
#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
*bit = pin_num % RV1126_PULL_PINS_PER_REG;
*bit *= RV1126_PULL_BITS_PER_PIN;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_PULL_PMU_OFFSET;
} else {
*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
*regmap = info->regmap_base;
*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
*bit *= RV1126_PULL_BITS_PER_PIN;
return 0;
}
#define RV1126_DRV_PMU_OFFSET 0x20
#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
#define RV1126_DRV_BITS_PER_PIN 4
#define RV1126_DRV_PINS_PER_REG 4
#define RV1126_DRV_BANK_STRIDE 32
static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
*reg -= 0x4;
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1126_DRV_PINS_PER_REG;
*bit *= RV1126_DRV_BITS_PER_PIN;
return 0;
}
#define RV1126_SCHMITT_PMU_OFFSET 0x60
#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
#define RV1126_SCHMITT_BANK_STRIDE 16
#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
if (RV1126_GPIO_C4_D7(pin_num)) {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
return 0;
}
*regmap = info->regmap_pmu;
*reg = RV1126_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3308_SCHMITT_GRF_OFFSET;
*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
return 0;
}
#define RK2928_PULL_OFFSET 0x118
#define RK2928_PULL_PINS_PER_REG 16
#define RK2928_PULL_BANK_STRIDE 8
static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK2928_PULL_OFFSET;
*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
*reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
return 0;
};
#define RK3128_PULL_OFFSET 0x118
static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
return 0;
}
#define RK3188_PULL_OFFSET 0x164
#define RK3188_PULL_BITS_PER_PIN 2
#define RK3188_PULL_PINS_PER_REG 8
#define RK3188_PULL_BANK_STRIDE 16
#define RK3188_PULL_PMU_OFFSET 0x64
static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 12 pins of the first bank are located elsewhere */
if (bank->bank_num == 0 && pin_num < 12) {
*regmap = info->regmap_pmu ? info->regmap_pmu
: bank->regmap_pull;
*reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_pull ? info->regmap_pull
: info->regmap_base;
*reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
/* correct the offset, as it is the 2nd pull register */
*reg -= 4;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
/*
* The bits in these registers have an inverse ordering
* with the lowest pin being in bits 15:14 and the highest
* pin in bits 1:0
*/
*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3288_PULL_OFFSET 0x140
static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3188_PULL_PMU_OFFSET;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3288_DRV_PMU_OFFSET 0x70
#define RK3288_DRV_GRF_OFFSET 0x1c0
#define RK3288_DRV_BITS_PER_PIN 2
#define RK3288_DRV_PINS_PER_REG 8
#define RK3288_DRV_BANK_STRIDE 16
static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3288_DRV_PMU_OFFSET;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3288_DRV_PINS_PER_REG;
*bit *= RK3288_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3228_PULL_OFFSET 0x100
static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
return 0;
}
#define RK3228_DRV_GRF_OFFSET 0x200
static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
return 0;
}
#define RK3308_PULL_OFFSET 0xa0
static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3308_PULL_OFFSET;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
return 0;
}
#define RK3308_DRV_GRF_OFFSET 0x100
static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3308_DRV_GRF_OFFSET;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
return 0;
}
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3288_DRV_PINS_PER_REG;
*bit *= RK3288_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
*bit *= RK3288_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The bank0:16 and bank1:32 pins are located in PMU */
if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
return 0;
}
static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int drv_num = (pin_num / 8);
/* The bank0:16 and bank1:32 pins are located in PMU */
if ((bank->bank_num == 0) || (bank->bank_num == 1))
*regmap = info->regmap_pmu;
else
*regmap = info->regmap_base;
*reg = bank->drv[drv_num].offset;
if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
(bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
*bit = (pin_num % 8) * 3;
else
*bit = (pin_num % 8) * 2;
return 0;
}
#define RK3568_PULL_PMU_OFFSET 0x20
#define RK3568_PULL_GRF_OFFSET 0x80
#define RK3568_PULL_BITS_PER_PIN 2
#define RK3568_PULL_PINS_PER_REG 8
#define RK3568_PULL_BANK_STRIDE 0x10
static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3568_PULL_PMU_OFFSET;
*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3568_PULL_PINS_PER_REG;
*bit *= RK3568_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3568_PULL_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
*bit *= RK3568_PULL_BITS_PER_PIN;
}
return 0;
}
#define RK3568_DRV_PMU_OFFSET 0x70
#define RK3568_DRV_GRF_OFFSET 0x200
#define RK3568_DRV_BITS_PER_PIN 8
#define RK3568_DRV_PINS_PER_REG 2
#define RK3568_DRV_BANK_STRIDE 0x40
static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The first 32 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3568_DRV_PMU_OFFSET;
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3568_DRV_PINS_PER_REG;
*bit *= RK3568_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3568_DRV_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
*bit *= RK3568_DRV_BITS_PER_PIN;
}
return 0;
}
#define RK3588_PMU1_IOC_REG (0x0000)
#define RK3588_PMU2_IOC_REG (0x4000)
#define RK3588_BUS_IOC_REG (0x8000)
#define RK3588_VCCIO1_4_IOC_REG (0x9000)
#define RK3588_VCCIO3_5_IOC_REG (0xA000)
#define RK3588_VCCIO2_IOC_REG (0xB000)
#define RK3588_VCCIO6_IOC_REG (0xC000)
#define RK3588_EMMC_IOC_REG (0xD000)
static const u32 rk3588_ds_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
{RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
{RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
{RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
{RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
{RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
{RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
{RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
{RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
{RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
{RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
{RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
{RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
{RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
{RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
{RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
{RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
{RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
{RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
{RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
};
static const u32 rk3588_p_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
};
static const u32 rk3588_smt_regs[][2] = {
{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
};
#define RK3588_PULL_BITS_PER_PIN 2
#define RK3588_PULL_PINS_PER_REG 8
static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_p_regs[i][0]) {
*reg = rk3588_p_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_PULL_PINS_PER_REG;
*bit *= RK3588_PULL_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
#define RK3588_DRV_BITS_PER_PIN 4
#define RK3588_DRV_PINS_PER_REG 4
static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_ds_regs[i][0]) {
*reg = rk3588_ds_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_DRV_PINS_PER_REG;
*bit *= RK3588_DRV_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
#define RK3588_SMT_BITS_PER_PIN 1
#define RK3588_SMT_PINS_PER_REG 8
static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
u8 bank_num = bank->bank_num;
u32 pin = bank_num * 32 + pin_num;
int i;
for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
if (pin >= rk3588_smt_regs[i][0]) {
*reg = rk3588_smt_regs[i][1];
*regmap = info->regmap_base;
*bit = pin_num % RK3588_SMT_PINS_PER_REG;
*bit *= RK3588_SMT_BITS_PER_PIN;
return 0;
}
}
return -EINVAL;
}
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
{ 2, 4, 8, 12, -1, -1, -1, -1 },
{ 3, 6, 9, 12, -1, -1, -1, -1 },
{ 5, 10, 15, 20, -1, -1, -1, -1 },
{ 4, 6, 8, 10, 12, 14, 16, 18 },
{ 4, 7, 10, 13, 16, 19, 22, 26 }
};
static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
struct regmap *regmap;
int reg, ret;
u32 data, temp, rmask_bits;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = RK3399_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is
* spread over 2 registers
*/
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
ret = regmap_read(regmap, reg + 0x4, &temp);
if (ret)
return ret;
/*
* the bit data[15] contains bit 0 of the value
* while temp[1:0] contains bits 2 and 1
*/
data >>= 15;
temp &= 0x3;
temp <<= 1;
data |= temp;
return rockchip_perpin_drv_list[drv_type][data];
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
return -EINVAL;
}
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
data &= (1 << rmask_bits) - 1;
return rockchip_perpin_drv_list[drv_type][data];
}
static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask, rmask_bits, temp;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
bank->bank_num, pin_num, strength);
ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
if (ctrl->type == RK3588) {
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RK3568) {
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
}
if (ctrl->type == RV1126) {
rmask_bits = RV1126_DRV_BITS_PER_PIN;
ret = strength;
goto config;
}
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
ret = i;
break;
} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
ret = rockchip_perpin_drv_list[drv_type][i];
break;
}
}
if (ret < 0) {
dev_err(dev, "unsupported driver strength %d\n", strength);
return ret;
}
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = RK3399_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is spread
* over 2 registers, the bit data[15] contains bit 0
* of the value while temp[1:0] contains bits 2 and 1
*/
data = (ret & 0x1) << 15;
temp = (ret >> 0x1) & 0x3;
rmask = BIT(15) | BIT(31);
data |= BIT(31);
ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret)
return ret;
rmask = 0x3 | (0x3 << 16);
temp |= (0x3 << 16);
reg += 0x4;
ret = regmap_update_bits(regmap, reg, rmask, temp);
return ret;
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
return -EINVAL;
}
config:
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
data |= (ret << bit);
ret = regmap_update_bits(regmap, reg, rmask, data);
return ret;
}
static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
{
PIN_CONFIG_BIAS_DISABLE,
PIN_CONFIG_BIAS_PULL_UP,
PIN_CONFIG_BIAS_PULL_DOWN,
PIN_CONFIG_BIAS_BUS_HOLD
},
{
PIN_CONFIG_BIAS_DISABLE,
PIN_CONFIG_BIAS_PULL_DOWN,
PIN_CONFIG_BIAS_DISABLE,
PIN_CONFIG_BIAS_PULL_UP
},
};
static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
struct regmap *regmap;
int reg, ret, pull_type;
u8 bit;
u32 data;
/* rk3066b does support any pulls */
if (ctrl->type == RK3066B)
return PIN_CONFIG_BIAS_DISABLE;
ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
switch (ctrl->type) {
case RK2928:
case RK3128:
return !(data & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
case PX30:
case RV1108:
case RK3188:
case RK3288:
case RK3308:
case RK3368:
case RK3399:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
/*
* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
* where that pull up value becomes 3.
*/
if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
if (data == 3)
data = 1;
}
return rockchip_pull_list[pull_type][data];
default:
dev_err(dev, "unsupported pinctrl type\n");
return -EINVAL;
};
}
static int rockchip_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
u32 data, rmask;
dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
/* rk3066b does support any pulls */
if (ctrl->type == RK3066B)
return pull ? -EINVAL : 0;
ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
switch (ctrl->type) {
case RK2928:
case RK3128:
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
ret = regmap_write(regmap, reg, data);
break;
case PX30:
case RV1108:
case RV1126:
case RK3188:
case RK3288:
case RK3308:
case RK3368:
case RK3399:
case RK3568:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) {
if (rockchip_pull_list[pull_type][i] == pull) {
ret = i;
break;
}
}
/*
* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
* where that pull up value becomes 3.
*/
if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
if (ret == 1)
ret = 3;
}
if (ret < 0) {
dev_err(dev, "unsupported pull setting %d\n", pull);
return ret;
}
/* enable the write to the equivalent lower bits */
data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
rmask = data | (data >> 16);
data |= (ret << bit);
ret = regmap_update_bits(regmap, reg, rmask, data);
break;
default:
dev_err(dev, "unsupported pinctrl type\n");
return -EINVAL;
}
return ret;
}
#define RK3328_SCHMITT_BITS_PER_PIN 1
#define RK3328_SCHMITT_PINS_PER_REG 16
#define RK3328_SCHMITT_BANK_STRIDE 8
#define RK3328_SCHMITT_GRF_OFFSET 0x380
static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3328_SCHMITT_GRF_OFFSET;
*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
*reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
*bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
return 0;
}
#define RK3568_SCHMITT_BITS_PER_PIN 2
#define RK3568_SCHMITT_PINS_PER_REG 8
#define RK3568_SCHMITT_BANK_STRIDE 0x10
#define RK3568_SCHMITT_GRF_OFFSET 0xc0
#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK3568_SCHMITT_PMUGRF_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RK3568_SCHMITT_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
*bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
*bit *= RK3568_SCHMITT_BITS_PER_PIN;
return 0;
}
static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data;
ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
switch (ctrl->type) {
case RK3568:
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
default:
break;
}
return data & 0x1;
}
static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
int pin_num, int enable)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct device *dev = info->dev;
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data, rmask;
dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
bank->bank_num, pin_num, enable);
ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
if (ret)
return ret;
/* enable the write to the equivalent lower bits */
switch (ctrl->type) {
case RK3568:
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
rmask = data | (data >> 16);
data |= ((enable ? 0x2 : 0x1) << bit);
break;
default:
data = BIT(bit + 16) | (enable << bit);
rmask = BIT(bit + 16) | BIT(bit);
break;
}
return regmap_update_bits(regmap, reg, rmask, data);
}
/*
* Pinmux_ops handling
*/
static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->nfunctions;
}
static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->functions[selector].name;
}
static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned selector, const char * const **groups,
unsigned * const num_groups)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*groups = info->functions[selector].groups;
*num_groups = info->functions[selector].ngroups;
return 0;
}
static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins = info->groups[group].pins;
const struct rockchip_pin_config *data = info->groups[group].data;
struct device *dev = info->dev;
struct rockchip_pin_bank *bank;
int cnt, ret = 0;
dev_dbg(dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
/*
* for each pin in the pin group selected, program the corresponding
* pin function number in the config register.
*/
for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
bank = pin_to_bank(info, pins[cnt]);
ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
data[cnt].func);
if (ret)
break;
}
if (ret) {
/* revert the already done pin settings */
for (cnt--; cnt >= 0; cnt--)
rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
return ret;
}
return 0;
}
static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset,
bool input)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct rockchip_pin_bank *bank;
bank = pin_to_bank(info, offset);
return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
}
static const struct pinmux_ops rockchip_pmx_ops = {
.get_functions_count = rockchip_pmx_get_funcs_count,
.get_function_name = rockchip_pmx_get_func_name,
.get_function_groups = rockchip_pmx_get_groups,
.set_mux = rockchip_pmx_set,
.gpio_set_direction = rockchip_pmx_gpio_set_direction,
};
/*
* Pinconf_ops handling
*/
static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
{
switch (ctrl->type) {
case RK2928:
case RK3128:
return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
pull == PIN_CONFIG_BIAS_DISABLE);
case RK3066B:
return pull ? false : true;
case PX30:
case RV1108:
case RV1126:
case RK3188:
case RK3288:
case RK3308:
case RK3368:
case RK3399:
case RK3568:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
return false;
}
static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
unsigned int pin, u32 param, u32 arg)
{
struct rockchip_pin_deferred *cfg;
cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
if (!cfg)
return -ENOMEM;
cfg->pin = pin;
cfg->param = param;
cfg->arg = arg;
list_add_tail(&cfg->head, &bank->deferred_pins);
return 0;
}
/* set the pin config settings for a specified pin */
static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned num_configs)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
struct gpio_chip *gpio = &bank->gpio_chip;
enum pin_config_param param;
u32 arg;
int i;
int rc;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
/*
* Check for gpio driver not being probed yet.
* The lock makes sure that either gpio-probe has completed
* or the gpio driver hasn't probed yet.
*/
mutex_lock(&bank->deferred_lock);
if (!gpio || !gpio->direction_output) {
rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
arg);
mutex_unlock(&bank->deferred_lock);
if (rc)
return rc;
break;
}
mutex_unlock(&bank->deferred_lock);
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
rc = rockchip_set_pull(bank, pin - bank->pin_base,
param);
if (rc)
return rc;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_BUS_HOLD:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
return -ENOTSUPP;
if (!arg)
return -EINVAL;
rc = rockchip_set_pull(bank, pin - bank->pin_base,
param);
if (rc)
return rc;
break;
case PIN_CONFIG_OUTPUT:
rc = rockchip_set_mux(bank, pin - bank->pin_base,
RK_FUNC_GPIO);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
rc = gpio->direction_output(gpio, pin - bank->pin_base,
arg);
if (rc)
return rc;
break;
case PIN_CONFIG_INPUT_ENABLE:
rc = rockchip_set_mux(bank, pin - bank->pin_base,
RK_FUNC_GPIO);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
rc = gpio->direction_input(gpio, pin - bank->pin_base);
if (rc)
return rc;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* rk3288 is the first with per-pin drive-strength */
if (!info->ctrl->drv_calc_reg)
return -ENOTSUPP;
rc = rockchip_set_drive_perpin(bank,
pin - bank->pin_base, arg);
if (rc < 0)
return rc;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!info->ctrl->schmitt_calc_reg)
return -ENOTSUPP;
rc = rockchip_set_schmitt(bank,
pin - bank->pin_base, arg);
if (rc < 0)
return rc;
break;
default:
return -ENOTSUPP;
break;
}
} /* for each config */
return 0;
}
/* get the pin config settings for a specified pin */
static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
struct gpio_chip *gpio = &bank->gpio_chip;
enum pin_config_param param = pinconf_to_config_param(*config);
u16 arg;
int rc;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
return -EINVAL;
arg = 0;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_BUS_HOLD:
if (!rockchip_pinconf_pull_valid(info->ctrl, param))
return -ENOTSUPP;
if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_OUTPUT:
rc = rockchip_get_mux(bank, pin - bank->pin_base);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
if (!gpio || !gpio->get) {
arg = 0;
break;
}
rc = gpio->get(gpio, pin - bank->pin_base);
if (rc < 0)
return rc;
arg = rc ? 1 : 0;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
/* rk3288 is the first with per-pin drive-strength */
if (!info->ctrl->drv_calc_reg)
return -ENOTSUPP;
rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
if (rc < 0)
return rc;
arg = rc;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!info->ctrl->schmitt_calc_reg)
return -ENOTSUPP;
rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
if (rc < 0)
return rc;
arg = rc;
break;
default:
return -ENOTSUPP;
break;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static const struct pinconf_ops rockchip_pinconf_ops = {
.pin_config_get = rockchip_pinconf_get,
.pin_config_set = rockchip_pinconf_set,
.is_generic = true,
};
static const struct of_device_id rockchip_bank_match[] = {
{ .compatible = "rockchip,gpio-bank" },
{ .compatible = "rockchip,rk3188-gpio-bank0" },
{},
};
static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
struct device_node *np)
{
struct device_node *child;
for_each_child_of_node(np, child) {
if (of_match_node(rockchip_bank_match, child))
continue;
info->nfunctions++;
info->ngroups += of_get_child_count(child);
}
}
static int rockchip_pinctrl_parse_groups(struct device_node *np,
struct rockchip_pin_group *grp,
struct rockchip_pinctrl *info,
u32 index)
{
struct device *dev = info->dev;
struct rockchip_pin_bank *bank;
int size;
const __be32 *list;
int num;
int i, j;
int ret;
dev_dbg(dev, "group(%d): %pOFn\n", index, np);
/* Initialise group */
grp->name = np->name;
/*
* the binding format is rockchip,pins = <bank pin mux CONFIG>,
* do sanity check and calculate pins number
*/
list = of_get_property(np, "rockchip,pins", &size);
/* we do not check return since it's safe node passed down */
size /= sizeof(*list);
if (!size || size % 4)
return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
grp->npins = size / 4;
grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
if (!grp->pins || !grp->data)
return -ENOMEM;
for (i = 0, j = 0; i < size; i += 4, j++) {
const __be32 *phandle;
struct device_node *np_config;
num = be32_to_cpu(*list++);
bank = bank_num_to_bank(info, num);
if (IS_ERR(bank))
return PTR_ERR(bank);
grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
grp->data[j].func = be32_to_cpu(*list++);
phandle = list++;
if (!phandle)
return -EINVAL;
np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
ret = pinconf_generic_parse_dt_config(np_config, NULL,
&grp->data[j].configs, &grp->data[j].nconfigs);
of_node_put(np_config);
if (ret)
return ret;
}
return 0;
}
static int rockchip_pinctrl_parse_functions(struct device_node *np,
struct rockchip_pinctrl *info,
u32 index)
{
struct device *dev = info->dev;
struct device_node *child;
struct rockchip_pmx_func *func;
struct rockchip_pin_group *grp;
int ret;
static u32 grp_index;
u32 i = 0;
dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
func = &info->functions[index];
/* Initialise function */
func->name = np->name;
func->ngroups = of_get_child_count(np);
if (func->ngroups <= 0)
return 0;
func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;
}
static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *child;
int ret;
int i;
rockchip_pinctrl_child_count(info, np);
dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
dev_dbg(dev, "ngroups = %d\n", info->ngroups);
info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
if (!info->functions)
return -ENOMEM;
info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
if (!info->groups)
return -ENOMEM;
i = 0;
for_each_child_of_node(np, child) {
if (of_match_node(rockchip_bank_match, child))
continue;
ret = rockchip_pinctrl_parse_functions(child, info, i++);
if (ret) {
dev_err(dev, "failed to parse function\n");
of_node_put(child);
return ret;
}
}
return 0;
}
static int rockchip_pinctrl_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
struct pinctrl_desc *ctrldesc = &info->pctl;
struct pinctrl_pin_desc *pindesc, *pdesc;
struct rockchip_pin_bank *pin_bank;
struct device *dev = &pdev->dev;
char **pin_names;
int pin, bank, ret;
int k;
ctrldesc->name = "rockchip-pinctrl";
ctrldesc->owner = THIS_MODULE;
ctrldesc->pctlops = &rockchip_pctrl_ops;
ctrldesc->pmxops = &rockchip_pmx_ops;
ctrldesc->confops = &rockchip_pinconf_ops;
pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
if (!pindesc)
return -ENOMEM;
ctrldesc->pins = pindesc;
ctrldesc->npins = info->ctrl->nr_pins;
pdesc = pindesc;
for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
pin_bank = &info->ctrl->pin_banks[bank];
pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
if (IS_ERR(pin_names))
return PTR_ERR(pin_names);
for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
pdesc->number = k;
pdesc->name = pin_names[pin];
pdesc++;
}
INIT_LIST_HEAD(&pin_bank->deferred_pins);
mutex_init(&pin_bank->deferred_lock);
}
ret = rockchip_pinctrl_parse_dt(pdev, info);
if (ret)
return ret;
info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
if (IS_ERR(info->pctl_dev))
return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
return 0;
}
static const struct of_device_id rockchip_pinctrl_dt_match[];
/* retrieve the soc specific data */
static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pinctrl *d,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
const struct of_device_id *match;
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
grf_offs = ctrl->grf_mux_offset;
pmu_offs = ctrl->pmu_mux_offset;
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
raw_spin_lock_init(&bank->slock);
bank->drvdata = d;
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
struct rockchip_iomux *iom = &bank->iomux[j];
struct rockchip_drv *drv = &bank->drv[j];
int inc;
if (bank_pins >= bank->nr_pins)
break;
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
if ((iom->type & IOMUX_SOURCE_PMU) ||
(iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
(iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
/* preset drv offset value, set new start value */
if (drv->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
drv_pmu_offs = drv->offset;
else
drv_grf_offs = drv->offset;
} else { /* set current drv offset */
drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
drv_pmu_offs : drv_grf_offs;
}
dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
i, j, iom->offset, drv->offset);
/*
* Increase offset according to iomux width.
* 4bit iomux'es are spread over two registers.
*/
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_WIDTH_2BIT)) ? 8 : 4;
if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
/*
* Increase offset according to drv width.
* 3bit drive-strenth'es are spread over two registers.
*/
if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
(drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
inc = 8;
else
inc = 4;
if (iom->type & IOMUX_SOURCE_PMU)
drv_pmu_offs += inc;
else
drv_grf_offs += inc;
bank_pins += 8;
}
/* calculate the per-bank recalced_mask */
for (j = 0; j < ctrl->niomux_recalced; j++) {
int pin = 0;
if (ctrl->iomux_recalced[j].num == bank->bank_num) {
pin = ctrl->iomux_recalced[j].pin;
bank->recalced_mask |= BIT(pin);
}
}
/* calculate the per-bank route_mask */
for (j = 0; j < ctrl->niomux_routes; j++) {
int pin = 0;
if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
pin = ctrl->iomux_routes[j].pin;
bank->route_mask |= BIT(pin);
}
}
}
return ctrl;
}
#define RK3288_GRF_GPIO6C_IOMUX 0x64
#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
static u32 rk3288_grf_gpio6c_iomux;
static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
int ret = pinctrl_force_sleep(info->pctl_dev);
if (ret)
return ret;
/*
* RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
* the setting here, and restore it at resume.
*/
if (info->ctrl->type == RK3288) {
ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
&rk3288_grf_gpio6c_iomux);
if (ret) {
pinctrl_force_default(info->pctl_dev);
return ret;
}
}
return 0;
}
static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
{
struct rockchip_pinctrl *info = dev_get_drvdata(dev);
int ret;
if (info->ctrl->type == RK3288) {
ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
rk3288_grf_gpio6c_iomux |
GPIO6C6_SEL_WRITE_ENABLE);
if (ret)
return ret;
}
return pinctrl_force_default(info->pctl_dev);
}
static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
rockchip_pinctrl_resume);
static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *node;
struct rockchip_pin_ctrl *ctrl;
struct resource *res;
void __iomem *base;
int ret;
if (!dev->of_node)
return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->dev = dev;
ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
if (!ctrl)
return dev_err_probe(dev, -EINVAL, "driver data not available\n");
info->ctrl = ctrl;
node = of_parse_phandle(np, "rockchip,grf", 0);
if (node) {
info->regmap_base = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(info->regmap_base))
return PTR_ERR(info->regmap_base);
} else {
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
rockchip_regmap_config.max_register = resource_size(res) - 4;
rockchip_regmap_config.name = "rockchip,pinctrl";
info->regmap_base =
devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
/* to check for the old dt-bindings */
info->reg_size = resource_size(res);
/* Honor the old binding, with pull registers as 2nd resource */
if (ctrl->type == RK3188 && info->reg_size < 0x200) {
base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
if (IS_ERR(base))
return PTR_ERR(base);
rockchip_regmap_config.max_register = resource_size(res) - 4;
rockchip_regmap_config.name = "rockchip,pinctrl-pull";
info->regmap_pull =
devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
}
}
/* try to find the optional reference to the pmu syscon */
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (node) {
info->regmap_pmu = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(info->regmap_pmu))
return PTR_ERR(info->regmap_pmu);
}
ret = rockchip_pinctrl_register(pdev, info);
if (ret)
return ret;
platform_set_drvdata(pdev, info);
ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
if (ret)
return dev_err_probe(dev, ret, "failed to register gpio device\n");
return 0;
}
static int rockchip_pinctrl_remove(struct platform_device *pdev)
{
struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
struct rockchip_pin_bank *bank;
struct rockchip_pin_deferred *cfg;
int i;
of_platform_depopulate(&pdev->dev);
for (i = 0; i < info->ctrl->nr_banks; i++) {
bank = &info->ctrl->pin_banks[i];
mutex_lock(&bank->deferred_lock);
while (!list_empty(&bank->deferred_pins)) {
cfg = list_first_entry(&bank->deferred_pins,
struct rockchip_pin_deferred, head);
list_del(&cfg->head);
kfree(cfg);
}
mutex_unlock(&bank->deferred_lock);
}
return 0;
}
static struct rockchip_pin_bank px30_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT
),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT
),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT
),
};
static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
.label = "PX30-GPIO",
.type = PX30,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.iomux_routes = px30_mux_route_data,
.niomux_routes = ARRAY_SIZE(px30_mux_route_data),
.pull_calc_reg = px30_calc_pull_reg_and_bit,
.drv_calc_reg = px30_calc_drv_reg_and_bit,
.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
.label = "RV1108-GPIO",
.type = RV1108,
.grf_mux_offset = 0x10,
.pmu_mux_offset = 0x0,
.iomux_recalced = rv1108_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1126_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x10010, 0x10018, 0x10020, 0x10028),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
IOMUX_WIDTH_4BIT, 0, 0, 0),
};
static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
.pin_banks = rv1126_pin_banks,
.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
.label = "RV1126-GPIO",
.type = RV1126,
.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
.pmu_mux_offset = 0x0,
.iomux_routes = rv1126_mux_route_data,
.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
.iomux_recalced = rv1126_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
.label = "RK2928-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
};
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.label = "RK3036-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
PIN_BANK(4, 32, "gpio4"),
PIN_BANK(6, 16, "gpio6"),
};
static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
.label = "RK3066a-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3066b_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
.label = "RK3066b-GPIO",
.type = RK3066B,
.grf_mux_offset = 0x60,
};
static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
.iomux_recalced = rk3128_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
.iomux_routes = rk3128_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
.iomux_routes = rk3188_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.iomux_routes = rk3228_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_UNROUTED
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED,
IOMUX_UNROUTED,
0
),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0,
0
),
PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
0,
0,
IOMUX_UNROUTED
),
PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
0,
IOMUX_WIDTH_4BIT,
IOMUX_UNROUTED
),
PIN_BANK(8, 16, "gpio8"),
};
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.label = "RK3288-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x84,
.iomux_routes = rk3288_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
.pull_calc_reg = rk3288_calc_pull_reg_and_bit,
.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3308_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT),
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT,
IOMUX_WIDTH_2BIT),
};
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
.label = "RK3308-GPIO",
.type = RK3308,
.grf_mux_offset = 0x0,
.iomux_recalced = rk3308_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
.iomux_routes = rk3308_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3328_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
IOMUX_WIDTH_3BIT,
IOMUX_WIDTH_3BIT,
0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_3BIT,
IOMUX_WIDTH_3BIT,
0,
0),
};
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.iomux_recalced = rk3328_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
.iomux_routes = rk3328_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU
),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.pull_calc_reg = rk3368_calc_pull_reg_and_bit,
.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3399_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_DEFAULT,
DRV_TYPE_IO_DEFAULT,
0x80,
0x88,
-1,
-1,
PULL_TYPE_IO_1V8_ONLY,
PULL_TYPE_IO_1V8_ONLY,
PULL_TYPE_IO_DEFAULT,
PULL_TYPE_IO_DEFAULT
),
PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
0xa0,
0xa8,
0xb0,
0xb8
),
PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_ONLY,
PULL_TYPE_IO_DEFAULT,
PULL_TYPE_IO_DEFAULT,
PULL_TYPE_IO_1V8_ONLY,
PULL_TYPE_IO_1V8_ONLY
),
PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_1V8_OR_3V0
),
PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_3V0_AUTO,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0
),
};
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
.pmu_mux_offset = 0x0,
.grf_drv_offset = 0xe100,
.pmu_drv_offset = 0x80,
.iomux_routes = rk3399_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
.pull_calc_reg = rk3399_calc_pull_reg_and_bit,
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3568_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
};
static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
.pin_banks = rk3568_pin_banks,
.nr_banks = ARRAY_SIZE(rk3568_pin_banks),
.label = "RK3568-GPIO",
.type = RK3568,
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.grf_drv_offset = 0x0200,
.pmu_drv_offset = 0x0070,
.iomux_routes = rk3568_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
.pull_calc_reg = rk3568_calc_pull_reg_and_bit,
.drv_calc_reg = rk3568_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3588_pin_banks[] = {
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
};
static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
.pin_banks = rk3588_pin_banks,
.nr_banks = ARRAY_SIZE(rk3588_pin_banks),
.label = "RK3588-GPIO",
.type = RK3588,
.pull_calc_reg = rk3588_calc_pull_reg_and_bit,
.drv_calc_reg = rk3588_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,px30-pinctrl",
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",
.data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
.data = &rk3036_pin_ctrl },
{ .compatible = "rockchip,rk3066a-pinctrl",
.data = &rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
.data = &rk3066b_pin_ctrl },
{ .compatible = "rockchip,rk3128-pinctrl",
.data = (void *)&rk3128_pin_ctrl },
{ .compatible = "rockchip,rk3188-pinctrl",
.data = &rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3228-pinctrl",
.data = &rk3228_pin_ctrl },
{ .compatible = "rockchip,rk3288-pinctrl",
.data = &rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3308-pinctrl",
.data = &rk3308_pin_ctrl },
{ .compatible = "rockchip,rk3328-pinctrl",
.data = &rk3328_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
.data = &rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
.data = &rk3399_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
.data = &rk3588_pin_ctrl },
{},
};
static struct platform_driver rockchip_pinctrl_driver = {
.probe = rockchip_pinctrl_probe,
.remove = rockchip_pinctrl_remove,
.driver = {
.name = "rockchip-pinctrl",
.pm = &rockchip_pinctrl_dev_pm_ops,
.of_match_table = rockchip_pinctrl_dt_match,
},
};
static int __init rockchip_pinctrl_drv_register(void)
{
return platform_driver_register(&rockchip_pinctrl_driver);
}
postcore_initcall(rockchip_pinctrl_drv_register);
static void __exit rockchip_pinctrl_drv_unregister(void)
{
platform_driver_unregister(&rockchip_pinctrl_driver);
}
module_exit(rockchip_pinctrl_drv_unregister);
MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pinctrl-rockchip");
MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
|
linux-master
|
drivers/pinctrl/pinctrl-rockchip.c
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Author: zhanghongchen <[email protected]>
* Yinbo Zhu <[email protected]>
* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/seq_file.h>
#include "core.h"
#include "pinctrl-utils.h"
#define PMX_GROUP(name, offset, bitv) \
{ \
.grp = PINCTRL_PINGROUP((#name), (name ## _pins), \
ARRAY_SIZE((name ## _pins))), \
.reg = offset, \
.bit = bitv, \
}
#define SPECIFIC_GROUP(group) \
static const char * const group##_groups[] = { \
#group \
}
#define FUNCTION(fn) \
{ \
.name = #fn, \
.groups = fn ## _groups, \
.num_groups = ARRAY_SIZE(fn ## _groups), \
}
struct loongson2_pinctrl {
struct device *dev;
struct pinctrl_dev *pcdev;
struct pinctrl_desc desc;
struct device_node *of_node;
spinlock_t lock;
void __iomem *reg_base;
};
struct loongson2_pmx_group {
struct pingroup grp;
unsigned int reg;
unsigned int bit;
};
struct loongson2_pmx_func {
const char *name;
const char * const *groups;
unsigned int num_groups;
};
#define LOONGSON2_PIN(x) PINCTRL_PIN(x, "gpio"#x)
static const struct pinctrl_pin_desc loongson2_pctrl_pins[] = {
LOONGSON2_PIN(0), LOONGSON2_PIN(1), LOONGSON2_PIN(2), LOONGSON2_PIN(3),
LOONGSON2_PIN(4), LOONGSON2_PIN(5), LOONGSON2_PIN(6), LOONGSON2_PIN(7),
LOONGSON2_PIN(8), LOONGSON2_PIN(9), LOONGSON2_PIN(10), LOONGSON2_PIN(11),
LOONGSON2_PIN(12), LOONGSON2_PIN(13), LOONGSON2_PIN(14),
LOONGSON2_PIN(16), LOONGSON2_PIN(17), LOONGSON2_PIN(18), LOONGSON2_PIN(19),
LOONGSON2_PIN(20), LOONGSON2_PIN(21), LOONGSON2_PIN(22), LOONGSON2_PIN(23),
LOONGSON2_PIN(24), LOONGSON2_PIN(25), LOONGSON2_PIN(26), LOONGSON2_PIN(27),
LOONGSON2_PIN(28), LOONGSON2_PIN(29), LOONGSON2_PIN(30),
LOONGSON2_PIN(32), LOONGSON2_PIN(33), LOONGSON2_PIN(34), LOONGSON2_PIN(35),
LOONGSON2_PIN(36), LOONGSON2_PIN(37), LOONGSON2_PIN(38), LOONGSON2_PIN(39),
LOONGSON2_PIN(40), LOONGSON2_PIN(41),
LOONGSON2_PIN(44), LOONGSON2_PIN(45), LOONGSON2_PIN(46), LOONGSON2_PIN(47),
LOONGSON2_PIN(48), LOONGSON2_PIN(49), LOONGSON2_PIN(50), LOONGSON2_PIN(51),
LOONGSON2_PIN(52), LOONGSON2_PIN(53), LOONGSON2_PIN(54), LOONGSON2_PIN(55),
LOONGSON2_PIN(56), LOONGSON2_PIN(57), LOONGSON2_PIN(58), LOONGSON2_PIN(59),
LOONGSON2_PIN(60), LOONGSON2_PIN(61), LOONGSON2_PIN(62), LOONGSON2_PIN(63),
};
static const unsigned int gpio_pins[] = {0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30,
32, 33, 34, 35, 36, 37, 38, 39,
40, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 46, 55,
56, 57, 58, 59, 60, 61, 62, 63};
static const unsigned int sdio_pins[] = {36, 37, 38, 39, 40, 41};
static const unsigned int can1_pins[] = {34, 35};
static const unsigned int can0_pins[] = {32, 33};
static const unsigned int pwm3_pins[] = {23};
static const unsigned int pwm2_pins[] = {22};
static const unsigned int pwm1_pins[] = {21};
static const unsigned int pwm0_pins[] = {20};
static const unsigned int i2c1_pins[] = {18, 19};
static const unsigned int i2c0_pins[] = {16, 17};
static const unsigned int nand_pins[] = {44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58, 59, 60,
61, 62, 63};
static const unsigned int sata_led_pins[] = {14};
static const unsigned int i2s_pins[] = {24, 25, 26, 27, 28};
static const unsigned int hda_pins[] = {24, 25, 26, 27, 28, 29, 30};
static struct loongson2_pmx_group loongson2_pmx_groups[] = {
PMX_GROUP(gpio, 0x0, 64),
PMX_GROUP(sdio, 0x0, 20),
PMX_GROUP(can1, 0x0, 17),
PMX_GROUP(can0, 0x0, 16),
PMX_GROUP(pwm3, 0x0, 15),
PMX_GROUP(pwm2, 0x0, 14),
PMX_GROUP(pwm1, 0x0, 13),
PMX_GROUP(pwm0, 0x0, 12),
PMX_GROUP(i2c1, 0x0, 11),
PMX_GROUP(i2c0, 0x0, 10),
PMX_GROUP(nand, 0x0, 9),
PMX_GROUP(sata_led, 0x0, 8),
PMX_GROUP(i2s, 0x0, 6),
PMX_GROUP(hda, 0x0, 4),
};
SPECIFIC_GROUP(sdio);
SPECIFIC_GROUP(can1);
SPECIFIC_GROUP(can0);
SPECIFIC_GROUP(pwm3);
SPECIFIC_GROUP(pwm2);
SPECIFIC_GROUP(pwm1);
SPECIFIC_GROUP(pwm0);
SPECIFIC_GROUP(i2c1);
SPECIFIC_GROUP(i2c0);
SPECIFIC_GROUP(nand);
SPECIFIC_GROUP(sata_led);
SPECIFIC_GROUP(i2s);
SPECIFIC_GROUP(hda);
static const char * const gpio_groups[] = {
"sdio",
"can1", "can0",
"pwm3", "pwm2", "pwm1", "pwm0",
"i2c1", "i2c0",
"nand",
"sata_led",
"i2s",
"hda",
};
static const struct loongson2_pmx_func loongson2_pmx_functions[] = {
FUNCTION(gpio),
FUNCTION(sdio),
FUNCTION(can1),
FUNCTION(can0),
FUNCTION(pwm3),
FUNCTION(pwm2),
FUNCTION(pwm1),
FUNCTION(pwm0),
FUNCTION(i2c1),
FUNCTION(i2c0),
FUNCTION(nand),
FUNCTION(sata_led),
FUNCTION(i2s),
FUNCTION(hda),
};
static int loongson2_get_groups_count(struct pinctrl_dev *pcdev)
{
return ARRAY_SIZE(loongson2_pmx_groups);
}
static const char *loongson2_get_group_name(struct pinctrl_dev *pcdev,
unsigned int selector)
{
return loongson2_pmx_groups[selector].grp.name;
}
static int loongson2_get_group_pins(struct pinctrl_dev *pcdev, unsigned int selector,
const unsigned int **pins, unsigned int *num_pins)
{
*pins = loongson2_pmx_groups[selector].grp.pins;
*num_pins = loongson2_pmx_groups[selector].grp.npins;
return 0;
}
static void loongson2_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
unsigned int offset)
{
seq_printf(s, " %s", dev_name(pcdev->dev));
}
static const struct pinctrl_ops loongson2_pctrl_ops = {
.get_groups_count = loongson2_get_groups_count,
.get_group_name = loongson2_get_group_name,
.get_group_pins = loongson2_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
.pin_dbg_show = loongson2_pin_dbg_show,
};
static int loongson2_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned int func_num,
unsigned int group_num)
{
struct loongson2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pcdev);
void __iomem *reg = pctrl->reg_base +
loongson2_pmx_groups[group_num].reg;
unsigned int mux_bit = loongson2_pmx_groups[group_num].bit;
unsigned int val;
unsigned long flags;
spin_lock_irqsave(&pctrl->lock, flags);
val = readl(reg);
if (func_num == 0)
val &= ~BIT(mux_bit);
else
val |= BIT(mux_bit);
writel(val, reg);
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int loongson2_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
{
return ARRAY_SIZE(loongson2_pmx_functions);
}
static const char *loongson2_pmx_get_func_name(struct pinctrl_dev *pcdev,
unsigned int selector)
{
return loongson2_pmx_functions[selector].name;
}
static int loongson2_pmx_get_groups(struct pinctrl_dev *pcdev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = loongson2_pmx_functions[selector].groups;
*num_groups = loongson2_pmx_functions[selector].num_groups;
return 0;
}
static const struct pinmux_ops loongson2_pmx_ops = {
.set_mux = loongson2_pmx_set_mux,
.get_functions_count = loongson2_pmx_get_funcs_count,
.get_function_name = loongson2_pmx_get_func_name,
.get_function_groups = loongson2_pmx_get_groups,
};
static int loongson2_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct loongson2_pinctrl *pctrl;
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->reg_base))
return PTR_ERR(pctrl->reg_base);
spin_lock_init(&pctrl->lock);
pctrl->dev = dev;
pctrl->desc.name = "pinctrl-loongson2";
pctrl->desc.owner = THIS_MODULE;
pctrl->desc.pctlops = &loongson2_pctrl_ops;
pctrl->desc.pmxops = &loongson2_pmx_ops;
pctrl->desc.pins = loongson2_pctrl_pins;
pctrl->desc.npins = ARRAY_SIZE(loongson2_pctrl_pins);
pctrl->pcdev = devm_pinctrl_register(pctrl->dev, &pctrl->desc, pctrl);
if (IS_ERR(pctrl->pcdev))
return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->pcdev),
"can't register pinctrl device");
return 0;
}
static const struct of_device_id loongson2_pinctrl_dt_match[] = {
{
.compatible = "loongson,ls2k-pinctrl",
},
{ }
};
static struct platform_driver loongson2_pinctrl_driver = {
.probe = loongson2_pinctrl_probe,
.driver = {
.name = "loongson2-pinctrl",
.of_match_table = loongson2_pinctrl_dt_match,
},
};
static int __init loongson2_pinctrl_init(void)
{
return platform_driver_register(&loongson2_pinctrl_driver);
}
arch_initcall(loongson2_pinctrl_init);
static void __exit loongson2_pinctrl_exit(void)
{
platform_driver_unregister(&loongson2_pinctrl_driver);
}
module_exit(loongson2_pinctrl_exit);
MODULE_DESCRIPTION("Loongson2 Pinctrl driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-loongson2.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
*
* Copyright (C) 2019 STMicroelectronics
* Author(s): Amelie Delaunay <[email protected]>.
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/stmfx.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
/* GPIOs expander */
/* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
#define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */
/* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
#define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */
/* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
#define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */
/* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
#define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */
/* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
#define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */
/* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
#define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */
/* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
#define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */
/* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
#define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */
/* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
#define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */
/* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
#define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */
/* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
#define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */
#define NR_GPIO_REGS 3
#define NR_GPIOS_PER_REG 8
#define get_reg(offset) ((offset) / NR_GPIOS_PER_REG)
#define get_shift(offset) ((offset) % NR_GPIOS_PER_REG)
#define get_mask(offset) (BIT(get_shift(offset)))
/*
* STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
* Pins availability is managed thanks to gpio-ranges property.
*/
static const struct pinctrl_pin_desc stmfx_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "agpio0"),
PINCTRL_PIN(17, "agpio1"),
PINCTRL_PIN(18, "agpio2"),
PINCTRL_PIN(19, "agpio3"),
PINCTRL_PIN(20, "agpio4"),
PINCTRL_PIN(21, "agpio5"),
PINCTRL_PIN(22, "agpio6"),
PINCTRL_PIN(23, "agpio7"),
};
struct stmfx_pinctrl {
struct device *dev;
struct stmfx *stmfx;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
struct gpio_chip gpio_chip;
struct mutex lock; /* IRQ bus lock */
unsigned long gpio_valid_mask;
/* Cache of IRQ_GPI_* registers for bus_lock */
u8 irq_gpi_src[NR_GPIO_REGS];
u8 irq_gpi_type[NR_GPIO_REGS];
u8 irq_gpi_evt[NR_GPIO_REGS];
u8 irq_toggle_edge[NR_GPIO_REGS];
#ifdef CONFIG_PM
/* Backup of GPIO_* registers for suspend/resume */
u8 bkp_gpio_state[NR_GPIO_REGS];
u8 bkp_gpio_dir[NR_GPIO_REGS];
u8 bkp_gpio_type[NR_GPIO_REGS];
u8 bkp_gpio_pupd[NR_GPIO_REGS];
#endif
};
static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
u32 mask = get_mask(offset);
u32 value;
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &value);
return ret ? ret : !!(value & mask);
}
static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
u32 mask = get_mask(offset);
regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
mask, mask);
}
static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
u32 val;
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &val);
/*
* On stmfx, gpio pins direction is (0)input, (1)output.
*/
if (ret)
return ret;
if (val & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
}
static int stmfx_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
stmfx_gpio_set(gc, offset, value);
return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
}
static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
unsigned int offset)
{
u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
u32 pupd, mask = get_mask(offset);
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &pupd);
if (ret)
return ret;
return !!(pupd & mask);
}
static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
unsigned int offset, u32 pupd)
{
u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
u32 mask = get_mask(offset);
return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
}
static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
unsigned int offset)
{
u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
u32 type, mask = get_mask(offset);
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &type);
if (ret)
return ret;
return !!(type & mask);
}
static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
unsigned int offset, u32 type)
{
u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
u32 mask = get_mask(offset);
return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
}
static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
struct pinctrl_gpio_range *range;
u32 arg = 0;
int ret, dir, type, pupd;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range)
return -EINVAL;
dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
if (dir < 0)
return dir;
/*
* Currently the gpiolib IN is 1 and OUT is 0 but let's not count
* on it just to be on the safe side also in the future :)
*/
dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
type = stmfx_pinconf_get_type(pctl, pin);
if (type < 0)
return type;
pupd = stmfx_pinconf_get_pupd(pctl, pin);
if (pupd < 0)
return pupd;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if ((!dir && (!type || !pupd)) || (dir && !type))
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (dir && type && !pupd)
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (type && pupd)
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if ((!dir && type) || (dir && !type))
arg = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if ((!dir && !type) || (dir && type))
arg = 1;
break;
case PIN_CONFIG_OUTPUT:
if (dir)
return -EINVAL;
ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
if (ret < 0)
return ret;
arg = ret;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_gpio_range *range;
enum pin_config_param param;
u32 arg;
int i, ret;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range) {
dev_err(pctldev->dev, "pin %d is not available\n", pin);
return -EINVAL;
}
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_DRIVE_PUSH_PULL:
ret = stmfx_pinconf_set_type(pctl, pin, 0);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
break;
case PIN_CONFIG_OUTPUT:
ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
pin, arg);
if (ret)
return ret;
break;
default:
return -ENOTSUPP;
}
}
return 0;
}
static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset)
{
struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_gpio_range *range;
int dir, type, pupd, val;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
if (!range)
return;
dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
if (dir < 0)
return;
type = stmfx_pinconf_get_type(pctl, offset);
if (type < 0)
return;
pupd = stmfx_pinconf_get_pupd(pctl, offset);
if (pupd < 0)
return;
val = stmfx_gpio_get(&pctl->gpio_chip, offset);
if (val < 0)
return;
if (dir == GPIO_LINE_DIRECTION_OUT) {
seq_printf(s, "output %s ", val ? "high" : "low");
if (type)
seq_printf(s, "open drain %s internal pull-up ",
pupd ? "with" : "without");
else
seq_puts(s, "push pull no pull ");
} else {
seq_printf(s, "input %s ", val ? "high" : "low");
if (type)
seq_printf(s, "with internal pull-%s ",
pupd ? "up" : "down");
else
seq_printf(s, "%s ", pupd ? "floating" : "analog");
}
}
static const struct pinconf_ops stmfx_pinconf_ops = {
.pin_config_get = stmfx_pinconf_get,
.pin_config_set = stmfx_pinconf_set,
.pin_config_dbg_show = stmfx_pinconf_dbg_show,
};
static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return 0;
}
static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return NULL;
}
static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
return -ENOTSUPP;
}
static const struct pinctrl_ops stmfx_pinctrl_ops = {
.get_groups_count = stmfx_pinctrl_get_groups_count,
.get_group_name = stmfx_pinctrl_get_group_name,
.get_group_pins = stmfx_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static void stmfx_pinctrl_irq_mask(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
u32 reg = get_reg(data->hwirq);
u32 mask = get_mask(data->hwirq);
pctl->irq_gpi_src[reg] &= ~mask;
gpiochip_disable_irq(gpio_chip, irqd_to_hwirq(data));
}
static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
u32 reg = get_reg(data->hwirq);
u32 mask = get_mask(data->hwirq);
gpiochip_enable_irq(gpio_chip, irqd_to_hwirq(data));
pctl->irq_gpi_src[reg] |= mask;
}
static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
u32 reg = get_reg(data->hwirq);
u32 mask = get_mask(data->hwirq);
if (type == IRQ_TYPE_NONE)
return -EINVAL;
if (type & IRQ_TYPE_EDGE_BOTH) {
pctl->irq_gpi_evt[reg] |= mask;
irq_set_handler_locked(data, handle_edge_irq);
} else {
pctl->irq_gpi_evt[reg] &= ~mask;
irq_set_handler_locked(data, handle_level_irq);
}
if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
pctl->irq_gpi_type[reg] |= mask;
else
pctl->irq_gpi_type[reg] &= ~mask;
/*
* In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
* GPIO value to set the right edge trigger. But in atomic context
* here we can't access registers over I2C. That's why (type &
* IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
*/
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
pctl->irq_toggle_edge[reg] |= mask;
else
pctl->irq_toggle_edge[reg] &= mask;
return 0;
}
static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
mutex_lock(&pctl->lock);
}
static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
u32 reg = get_reg(data->hwirq);
u32 mask = get_mask(data->hwirq);
/*
* In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
* (this couldn't be done in .irq_set_type because of atomic context)
* to set the right irq trigger type.
*/
if (pctl->irq_toggle_edge[reg] & mask) {
if (stmfx_gpio_get(gpio_chip, data->hwirq))
pctl->irq_gpi_type[reg] &= ~mask;
else
pctl->irq_gpi_type[reg] |= mask;
}
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
pctl->irq_gpi_evt, NR_GPIO_REGS);
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
pctl->irq_gpi_type, NR_GPIO_REGS);
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
pctl->irq_gpi_src, NR_GPIO_REGS);
mutex_unlock(&pctl->lock);
}
static int stmfx_gpio_irq_request_resources(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
int ret;
ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
if (ret)
return ret;
return gpiochip_reqres_irq(gpio_chip, data->hwirq);
}
static void stmfx_gpio_irq_release_resources(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
return gpiochip_relres_irq(gpio_chip, data->hwirq);
}
static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
unsigned int offset)
{
u32 reg = get_reg(offset);
u32 mask = get_mask(offset);
int val;
if (!(pctl->irq_toggle_edge[reg] & mask))
return;
val = stmfx_gpio_get(&pctl->gpio_chip, offset);
if (val < 0)
return;
if (val) {
pctl->irq_gpi_type[reg] &= mask;
regmap_write_bits(pctl->stmfx->map,
STMFX_REG_IRQ_GPI_TYPE + reg,
mask, 0);
} else {
pctl->irq_gpi_type[reg] |= mask;
regmap_write_bits(pctl->stmfx->map,
STMFX_REG_IRQ_GPI_TYPE + reg,
mask, mask);
}
}
static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
{
struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
struct gpio_chip *gc = &pctl->gpio_chip;
u8 pending[NR_GPIO_REGS];
u8 src[NR_GPIO_REGS] = {0, 0, 0};
unsigned long n, status;
int i, ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
&pending, NR_GPIO_REGS);
if (ret)
return IRQ_NONE;
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
src, NR_GPIO_REGS);
BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
status |= (unsigned long)pending[i] << (i * 8);
for_each_set_bit(n, &status, gc->ngpio) {
handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
stmfx_pinctrl_irq_toggle_trigger(pctl, n);
}
regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
pctl->irq_gpi_src, NR_GPIO_REGS);
return IRQ_HANDLED;
}
static void stmfx_pinctrl_irq_print_chip(struct irq_data *d, struct seq_file *p)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(d);
struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
seq_printf(p, dev_name(pctl->dev));
}
static const struct irq_chip stmfx_pinctrl_irq_chip = {
.irq_mask = stmfx_pinctrl_irq_mask,
.irq_unmask = stmfx_pinctrl_irq_unmask,
.irq_set_type = stmfx_pinctrl_irq_set_type,
.irq_bus_lock = stmfx_pinctrl_irq_bus_lock,
.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock,
.irq_request_resources = stmfx_gpio_irq_request_resources,
.irq_release_resources = stmfx_gpio_irq_release_resources,
.irq_print_chip = stmfx_pinctrl_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
};
static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
{
struct pinctrl_gpio_range *gpio_range;
struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
u32 func = STMFX_FUNC_GPIO;
pctl->gpio_valid_mask = GENMASK(15, 0);
gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
if (gpio_range) {
func |= STMFX_FUNC_ALTGPIO_LOW;
pctl->gpio_valid_mask |= GENMASK(19, 16);
}
gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
if (gpio_range) {
func |= STMFX_FUNC_ALTGPIO_HIGH;
pctl->gpio_valid_mask |= GENMASK(23, 20);
}
return stmfx_function_enable(pctl->stmfx, func);
}
static int stmfx_pinctrl_probe(struct platform_device *pdev)
{
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
struct device_node *np = pdev->dev.of_node;
struct stmfx_pinctrl *pctl;
struct gpio_irq_chip *girq;
int irq, ret;
pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
pctl->dev = &pdev->dev;
pctl->stmfx = stmfx;
if (!of_property_present(np, "gpio-ranges")) {
dev_err(pctl->dev, "missing required gpio-ranges property\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
mutex_init(&pctl->lock);
/* Register pin controller */
pctl->pctl_desc.name = "stmfx-pinctrl";
pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
pctl->pctl_desc.confops = &stmfx_pinconf_ops;
pctl->pctl_desc.pins = stmfx_pins;
pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
pctl->pctl_desc.owner = THIS_MODULE;
pctl->pctl_desc.link_consumers = true;
ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
pctl, &pctl->pctl_dev);
if (ret) {
dev_err(pctl->dev, "pinctrl registration failed\n");
return ret;
}
ret = pinctrl_enable(pctl->pctl_dev);
if (ret) {
dev_err(pctl->dev, "pinctrl enable failed\n");
return ret;
}
/* Register gpio controller */
pctl->gpio_chip.label = "stmfx-gpio";
pctl->gpio_chip.parent = pctl->dev;
pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
pctl->gpio_chip.get = stmfx_gpio_get;
pctl->gpio_chip.set = stmfx_gpio_set;
pctl->gpio_chip.set_config = gpiochip_generic_config;
pctl->gpio_chip.base = -1;
pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
pctl->gpio_chip.can_sleep = true;
girq = &pctl->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &stmfx_pinctrl_irq_chip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->threaded = true;
ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
if (ret) {
dev_err(pctl->dev, "gpio_chip registration failed\n");
return ret;
}
ret = stmfx_pinctrl_gpio_function_enable(pctl);
if (ret)
return ret;
ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
stmfx_pinctrl_irq_thread_fn,
IRQF_ONESHOT,
dev_name(pctl->dev), pctl);
if (ret) {
dev_err(pctl->dev, "cannot request irq%d\n", irq);
return ret;
}
dev_info(pctl->dev,
"%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
return 0;
}
static int stmfx_pinctrl_remove(struct platform_device *pdev)
{
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
return stmfx_function_disable(stmfx,
STMFX_FUNC_GPIO |
STMFX_FUNC_ALTGPIO_LOW |
STMFX_FUNC_ALTGPIO_HIGH);
}
#ifdef CONFIG_PM_SLEEP
static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
{
int ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
&pctl->bkp_gpio_state, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
&pctl->bkp_gpio_dir, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
&pctl->bkp_gpio_type, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
&pctl->bkp_gpio_pupd, NR_GPIO_REGS);
if (ret)
return ret;
return 0;
}
static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
{
int ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
pctl->bkp_gpio_dir, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
pctl->bkp_gpio_type, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
pctl->bkp_gpio_pupd, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
pctl->bkp_gpio_state, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
pctl->irq_gpi_evt, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
pctl->irq_gpi_type, NR_GPIO_REGS);
if (ret)
return ret;
ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
pctl->irq_gpi_src, NR_GPIO_REGS);
if (ret)
return ret;
return 0;
}
static int stmfx_pinctrl_suspend(struct device *dev)
{
struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
int ret;
ret = stmfx_pinctrl_backup_regs(pctl);
if (ret) {
dev_err(pctl->dev, "registers backup failure\n");
return ret;
}
return 0;
}
static int stmfx_pinctrl_resume(struct device *dev)
{
struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
int ret;
ret = stmfx_pinctrl_restore_regs(pctl);
if (ret) {
dev_err(pctl->dev, "registers restoration failure\n");
return ret;
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
static const struct of_device_id stmfx_pinctrl_of_match[] = {
{ .compatible = "st,stmfx-0300-pinctrl", },
{},
};
MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
static struct platform_driver stmfx_pinctrl_driver = {
.driver = {
.name = "stmfx-pinctrl",
.of_match_table = stmfx_pinctrl_of_match,
.pm = &stmfx_pinctrl_dev_pm_ops,
},
.probe = stmfx_pinctrl_probe,
.remove = stmfx_pinctrl_remove,
};
module_platform_driver(stmfx_pinctrl_driver);
MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-stmfx.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* at91 pinctrl driver based on at91 pinmux core
*
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-at91.h"
#include "core.h"
#define MAX_GPIO_BANKS 5
#define MAX_NB_GPIO_PER_BANK 32
struct at91_pinctrl_mux_ops;
/**
* struct at91_gpio_chip: at91 gpio chip
* @chip: gpio chip
* @range: gpio range
* @next: bank sharing same clock
* @pioc_hwirq: PIO bank interrupt identifier on AIC
* @pioc_virq: PIO bank Linux virtual interrupt
* @regbase: PIO bank virtual address
* @clock: associated clock
* @ops: at91 pinctrl mux ops
* @wakeups: wakeup interrupts
* @backups: interrupts disabled in suspend
* @id: gpio chip identifier
*/
struct at91_gpio_chip {
struct gpio_chip chip;
struct pinctrl_gpio_range range;
struct at91_gpio_chip *next;
int pioc_hwirq;
int pioc_virq;
void __iomem *regbase;
struct clk *clock;
const struct at91_pinctrl_mux_ops *ops;
u32 wakeups;
u32 backups;
u32 id;
};
static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
static int gpio_banks;
#define PULL_UP (1 << 0)
#define MULTI_DRIVE (1 << 1)
#define DEGLITCH (1 << 2)
#define PULL_DOWN (1 << 3)
#define DIS_SCHMIT (1 << 4)
#define DRIVE_STRENGTH_SHIFT 5
#define DRIVE_STRENGTH_MASK 0x3
#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
#define OUTPUT (1 << 7)
#define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
#define SLEWRATE_SHIFT 9
#define SLEWRATE_MASK 0x1
#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
/*
* These defines will translated the dt binding settings to our internal
* settings. They are not necessarily the same value as the register setting.
* The actual drive strength current of low, medium and high must be looked up
* from the corresponding device datasheet. This value is different for pins
* that are even in the same banks. It is also dependent on VCC.
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
enum drive_strength_bit {
DRIVE_STRENGTH_BIT_DEF,
DRIVE_STRENGTH_BIT_LOW,
DRIVE_STRENGTH_BIT_MED,
DRIVE_STRENGTH_BIT_HI,
};
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT)
enum slewrate_bit {
SLEWRATE_BIT_ENA,
SLEWRATE_BIT_DIS,
};
#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
* @groups: corresponding pin groups
* @ngroups: the number of groups
*/
struct at91_pmx_func {
const char *name;
const char **groups;
unsigned ngroups;
};
enum at91_mux {
AT91_MUX_GPIO = 0,
AT91_MUX_PERIPH_A = 1,
AT91_MUX_PERIPH_B = 2,
AT91_MUX_PERIPH_C = 3,
AT91_MUX_PERIPH_D = 4,
};
/**
* struct at91_pmx_pin - describes an At91 pin mux
* @bank: the bank of the pin
* @pin: the pin number in the @bank
* @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
* @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
*/
struct at91_pmx_pin {
uint32_t bank;
uint32_t pin;
enum at91_mux mux;
unsigned long conf;
};
/**
* struct at91_pin_group - describes an At91 pin group
* @name: the name of this specific pin group
* @pins_conf: the mux mode for each pin in this group. The size of this
* array is the same as pins.
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @npins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
*/
struct at91_pin_group {
const char *name;
struct at91_pmx_pin *pins_conf;
unsigned int *pins;
unsigned npins;
};
/**
* struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
* on new IP with support for periph C and D the way to mux in
* periph A and B has changed
* So provide the right call back
* if not present means the IP does not support it
* @get_periph: return the periph mode configured
* @mux_A_periph: mux as periph A
* @mux_B_periph: mux as periph B
* @mux_C_periph: mux as periph C
* @mux_D_periph: mux as periph D
* @get_deglitch: get deglitch status
* @set_deglitch: enable/disable deglitch
* @get_debounce: get debounce status
* @set_debounce: enable/disable debounce
* @get_pulldown: get pulldown status
* @set_pulldown: enable/disable pulldown
* @get_schmitt_trig: get schmitt trigger status
* @disable_schmitt_trig: disable schmitt trigger
* @get_drivestrength: get driver strength
* @set_drivestrength: set driver strength
* @get_slewrate: get slew rate
* @set_slewrate: set slew rate
* @irq_type: return irq type
*/
struct at91_pinctrl_mux_ops {
enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
void (*mux_A_periph)(void __iomem *pio, unsigned mask);
void (*mux_B_periph)(void __iomem *pio, unsigned mask);
void (*mux_C_periph)(void __iomem *pio, unsigned mask);
void (*mux_D_periph)(void __iomem *pio, unsigned mask);
bool (*get_deglitch)(void __iomem *pio, unsigned pin);
void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
bool (*get_pulldown)(void __iomem *pio, unsigned pin);
void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
void (*set_drivestrength)(void __iomem *pio, unsigned pin,
u32 strength);
unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
static int gpio_irq_type(struct irq_data *d, unsigned type);
static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
struct at91_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
int nactive_banks;
uint32_t *mux_mask;
int nmux;
struct at91_pmx_func *functions;
int nfunctions;
struct at91_pin_group *groups;
int ngroups;
const struct at91_pinctrl_mux_ops *ops;
};
static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
const struct at91_pinctrl *info,
const char *name)
{
const struct at91_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (strcmp(info->groups[i].name, name))
continue;
grp = &info->groups[i];
dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
break;
}
return grp;
}
static int at91_get_groups_count(struct pinctrl_dev *pctldev)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->ngroups;
}
static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->groups[selector].name;
}
static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *npins)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*npins = info->groups[selector].npins;
return 0;
}
static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, "%s", dev_name(pctldev->dev));
}
static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map, unsigned *num_maps)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct at91_pin_group *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num = 1;
int i;
/*
* first find the group of this node and check if we need to create
* config maps for pins
*/
grp = at91_pinctrl_find_group_by_name(info, np->name);
if (!grp) {
dev_err(info->dev, "unable to find group for node %pOFn\n",
np);
return -EINVAL;
}
map_num += grp->npins;
new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
GFP_KERNEL);
if (!new_map)
return -ENOMEM;
*map = new_map;
*num_maps = map_num;
/* create mux map */
parent = of_get_parent(np);
if (!parent) {
devm_kfree(pctldev->dev, new_map);
return -EINVAL;
}
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map */
new_map++;
for (i = 0; i < grp->npins; i++) {
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[i].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i]);
new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
new_map[i].data.configs.num_configs = 1;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
return 0;
}
static void at91_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
}
static const struct pinctrl_ops at91_pctrl_ops = {
.get_groups_count = at91_get_groups_count,
.get_group_name = at91_get_group_name,
.get_group_pins = at91_get_group_pins,
.pin_dbg_show = at91_pin_dbg_show,
.dt_node_to_map = at91_dt_node_to_map,
.dt_free_map = at91_dt_free_map,
};
static void __iomem *pin_to_controller(struct at91_pinctrl *info,
unsigned int bank)
{
if (!gpio_chips[bank])
return NULL;
return gpio_chips[bank]->regbase;
}
static inline int pin_to_bank(unsigned pin)
{
return pin /= MAX_NB_GPIO_PER_BANK;
}
static unsigned pin_to_mask(unsigned int pin)
{
return 1 << pin;
}
static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
{
/* return the shift value for a pin for "two bit" per pin registers,
* i.e. drive strength */
return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
}
static unsigned sama5d3_get_drive_register(unsigned int pin)
{
/* drive strength is split between two registers
* with two bits per pin */
return (pin >= MAX_NB_GPIO_PER_BANK/2)
? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
}
static unsigned at91sam9x5_get_drive_register(unsigned int pin)
{
/* drive strength is split between two registers
* with two bits per pin */
return (pin >= MAX_NB_GPIO_PER_BANK/2)
? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
}
static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_IDR);
}
static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
{
return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
}
static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
{
if (on)
writel_relaxed(mask, pio + PIO_PPDDR);
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
{
*val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
}
static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
bool is_on, bool val)
{
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
}
static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
}
static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
{
writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
}
static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_ASR);
}
static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_BSR);
}
static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
pio + PIO_ABCDSR1);
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
pio + PIO_ABCDSR2);
}
static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
pio + PIO_ABCDSR1);
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
pio + PIO_ABCDSR2);
}
static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}
static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
{
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
}
static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
{
unsigned select;
if (readl_relaxed(pio + PIO_PSR) & mask)
return AT91_MUX_GPIO;
select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
return select + 1;
}
static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
{
unsigned select;
if (readl_relaxed(pio + PIO_PSR) & mask)
return AT91_MUX_GPIO;
select = readl_relaxed(pio + PIO_ABSR) & mask;
return select + 1;
}
static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
}
static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
}
static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
{
if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
return false;
}
static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
{
if (is_on)
writel_relaxed(mask, pio + PIO_IFSCDR);
at91_mux_set_deglitch(pio, mask, is_on);
}
static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
{
*div = readl_relaxed(pio + PIO_SCDR);
return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
}
static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
bool is_on, u32 div)
{
if (is_on) {
writel_relaxed(mask, pio + PIO_IFSCER);
writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
writel_relaxed(mask, pio + PIO_IFER);
} else
writel_relaxed(mask, pio + PIO_IFSCDR);
}
static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
{
return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
}
static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
{
if (is_on)
writel_relaxed(mask, pio + PIO_PUDR);
writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
}
static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
{
writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
}
static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
{
return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
}
static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
{
unsigned tmp = readl_relaxed(reg);
tmp = tmp >> two_bit_pin_value_shift_amount(pin);
return tmp & DRIVE_STRENGTH_MASK;
}
static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
unsigned pin)
{
unsigned tmp = read_drive_strength(pio +
sama5d3_get_drive_register(pin), pin);
/* SAMA5 strength is 1:1 with our defines,
* except 0 is equivalent to low per datasheet */
if (!tmp)
tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
return tmp;
}
static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
unsigned pin)
{
unsigned tmp = read_drive_strength(pio +
at91sam9x5_get_drive_register(pin), pin);
/* strength is inverse in SAM9x5s hardware with the pinctrl defines
* hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
return tmp;
}
static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
unsigned pin)
{
unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
if (tmp & BIT(pin))
return DRIVE_STRENGTH_BIT_HI;
return DRIVE_STRENGTH_BIT_LOW;
}
static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
{
unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
if ((tmp & BIT(pin)))
return SLEWRATE_BIT_ENA;
return SLEWRATE_BIT_DIS;
}
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = readl_relaxed(reg);
unsigned shift = two_bit_pin_value_shift_amount(pin);
tmp &= ~(DRIVE_STRENGTH_MASK << shift);
tmp |= strength << shift;
writel_relaxed(tmp, reg);
}
static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
u32 setting)
{
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is 1 to 1 with setting for SAMA5 */
set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
}
static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
u32 setting)
{
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
setting);
}
static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
u32 setting)
{
unsigned int tmp;
if (setting <= DRIVE_STRENGTH_BIT_DEF ||
setting == DRIVE_STRENGTH_BIT_MED ||
setting > DRIVE_STRENGTH_BIT_HI)
return;
tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
/* Strength is 0: low, 1: hi */
if (setting == DRIVE_STRENGTH_BIT_LOW)
tmp &= ~BIT(pin);
else
tmp |= BIT(pin);
writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
}
static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
u32 setting)
{
unsigned int tmp;
if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
return;
tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
if (setting == SLEWRATE_BIT_DIS)
tmp &= ~BIT(pin);
else
tmp |= BIT(pin);
writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
}
static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
.mux_B_periph = at91_mux_set_B_periph,
.get_deglitch = at91_mux_get_deglitch,
.set_deglitch = at91_mux_set_deglitch,
.irq_type = gpio_irq_type,
};
static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.get_deglitch = at91_mux_pio3_get_deglitch,
.set_deglitch = at91_mux_pio3_set_deglitch,
.get_debounce = at91_mux_pio3_get_debounce,
.set_debounce = at91_mux_pio3_set_debounce,
.get_pulldown = at91_mux_pio3_get_pulldown,
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
.irq_type = alt_gpio_irq_type,
};
static const struct at91_pinctrl_mux_ops sam9x60_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.get_deglitch = at91_mux_pio3_get_deglitch,
.set_deglitch = at91_mux_pio3_set_deglitch,
.get_debounce = at91_mux_pio3_get_debounce,
.set_debounce = at91_mux_pio3_set_debounce,
.get_pulldown = at91_mux_pio3_get_pulldown,
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
.get_slewrate = at91_mux_sam9x60_get_slewrate,
.set_slewrate = at91_mux_sam9x60_set_slewrate,
.irq_type = alt_gpio_irq_type,
};
static const struct at91_pinctrl_mux_ops sama5d3_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.get_deglitch = at91_mux_pio3_get_deglitch,
.set_deglitch = at91_mux_pio3_set_deglitch,
.get_debounce = at91_mux_pio3_get_debounce,
.set_debounce = at91_mux_pio3_set_debounce,
.get_pulldown = at91_mux_pio3_get_pulldown,
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
.irq_type = alt_gpio_irq_type,
};
static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
{
if (pin->mux) {
dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
} else {
dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
pin->bank + 'A', pin->pin, pin->conf);
}
}
static int pin_check_config(struct at91_pinctrl *info, const char *name,
int index, const struct at91_pmx_pin *pin)
{
int mux;
/* check if it's a valid config */
if (pin->bank >= gpio_banks) {
dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
name, index, pin->bank, gpio_banks);
return -EINVAL;
}
if (!gpio_chips[pin->bank]) {
dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
name, index, pin->bank);
return -ENXIO;
}
if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
return -EINVAL;
}
if (!pin->mux)
return 0;
mux = pin->mux - 1;
if (mux >= info->nmux) {
dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
name, index, mux, info->nmux);
return -EINVAL;
}
if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
name, index, mux, pin->bank + 'A', pin->pin);
return -EINVAL;
}
return 0;
}
static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_PDR);
}
static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
{
writel_relaxed(mask, pio + PIO_PER);
writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
}
static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
const struct at91_pmx_pin *pin;
uint32_t npins = info->groups[group].npins;
int i, ret;
unsigned mask;
void __iomem *pio;
dev_dbg(info->dev, "enable function %s group %s\n",
info->functions[selector].name, info->groups[group].name);
/* first check that all the pins of the group are valid with a valid
* parameter */
for (i = 0; i < npins; i++) {
pin = &pins_conf[i];
ret = pin_check_config(info, info->groups[group].name, i, pin);
if (ret)
return ret;
}
for (i = 0; i < npins; i++) {
pin = &pins_conf[i];
at91_pin_dbg(info->dev, pin);
pio = pin_to_controller(info, pin->bank);
if (!pio)
continue;
mask = pin_to_mask(pin->pin);
at91_mux_disable_interrupt(pio, mask);
switch (pin->mux) {
case AT91_MUX_GPIO:
at91_mux_gpio_enable(pio, mask, 1);
break;
case AT91_MUX_PERIPH_A:
info->ops->mux_A_periph(pio, mask);
break;
case AT91_MUX_PERIPH_B:
info->ops->mux_B_periph(pio, mask);
break;
case AT91_MUX_PERIPH_C:
if (!info->ops->mux_C_periph)
return -EINVAL;
info->ops->mux_C_periph(pio, mask);
break;
case AT91_MUX_PERIPH_D:
if (!info->ops->mux_D_periph)
return -EINVAL;
info->ops->mux_D_periph(pio, mask);
break;
}
if (pin->mux)
at91_mux_gpio_disable(pio, mask);
}
return 0;
}
static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->nfunctions;
}
static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->functions[selector].name;
}
static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*groups = info->functions[selector].groups;
*num_groups = info->functions[selector].ngroups;
return 0;
}
static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
struct at91_gpio_chip *at91_chip;
struct gpio_chip *chip;
unsigned mask;
if (!range) {
dev_err(npct->dev, "invalid range\n");
return -EINVAL;
}
if (!range->gc) {
dev_err(npct->dev, "missing GPIO chip in range\n");
return -EINVAL;
}
chip = range->gc;
at91_chip = gpiochip_get_data(chip);
dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
mask = 1 << (offset - chip->base);
dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
offset, 'A' + range->id, offset - chip->base, mask);
writel_relaxed(mask, at91_chip->regbase + PIO_PER);
return 0;
}
static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
/* Set the pin to some default state, GPIO is usually default */
}
static const struct pinmux_ops at91_pmx_ops = {
.get_functions_count = at91_pmx_get_funcs_count,
.get_function_name = at91_pmx_get_func_name,
.get_function_groups = at91_pmx_get_groups,
.set_mux = at91_pmx_set,
.gpio_request_enable = at91_gpio_request_enable,
.gpio_disable_free = at91_gpio_disable_free,
};
static int at91_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
void __iomem *pio;
unsigned pin;
int div;
bool out;
*config = 0;
dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
pio = pin_to_controller(info, pin_to_bank(pin_id));
if (!pio)
return -EINVAL;
pin = pin_id % MAX_NB_GPIO_PER_BANK;
if (at91_mux_get_multidrive(pio, pin))
*config |= MULTI_DRIVE;
if (at91_mux_get_pullup(pio, pin))
*config |= PULL_UP;
if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
*config |= DEGLITCH;
if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
*config |= PULL_DOWN;
if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
*config |= DIS_SCHMIT;
if (info->ops->get_drivestrength)
*config |= (info->ops->get_drivestrength(pio, pin)
<< DRIVE_STRENGTH_SHIFT);
if (info->ops->get_slewrate)
*config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
if (at91_mux_get_output(pio, pin, &out))
*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
return 0;
}
static int at91_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned mask;
void __iomem *pio;
int i;
unsigned long config;
unsigned pin;
for (i = 0; i < num_configs; i++) {
config = configs[i];
dev_dbg(info->dev,
"%s:%d, pin_id=%d, config=0x%lx",
__func__, __LINE__, pin_id, config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
if (!pio)
return -EINVAL;
pin = pin_id % MAX_NB_GPIO_PER_BANK;
mask = pin_to_mask(pin);
if (config & PULL_UP && config & PULL_DOWN)
return -EINVAL;
at91_mux_set_output(pio, mask, config & OUTPUT,
(config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
at91_mux_set_pullup(pio, mask, config & PULL_UP);
at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
if (info->ops->set_deglitch)
info->ops->set_deglitch(pio, mask, config & DEGLITCH);
if (info->ops->set_debounce)
info->ops->set_debounce(pio, mask, config & DEBOUNCE,
(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
if (info->ops->set_pulldown)
info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
info->ops->disable_schmitt_trig(pio, mask);
if (info->ops->set_drivestrength)
info->ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH)
>> DRIVE_STRENGTH_SHIFT);
if (info->ops->set_slewrate)
info->ops->set_slewrate(pio, pin,
(config & SLEWRATE) >> SLEWRATE_SHIFT);
} /* for each config */
return 0;
}
#define DBG_SHOW_FLAG(flag) do { \
if (config & flag) { \
if (num_conf) \
seq_puts(s, "|"); \
seq_puts(s, #flag); \
num_conf++; \
} \
} while (0)
#define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
if ((config & mask) == flag) { \
if (num_conf) \
seq_puts(s, "|"); \
seq_puts(s, #name); \
num_conf++; \
} \
} while (0)
static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
unsigned long config;
int val, num_conf = 0;
at91_pinconf_get(pctldev, pin_id, &config);
DBG_SHOW_FLAG(MULTI_DRIVE);
DBG_SHOW_FLAG(PULL_UP);
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
DRIVE_STRENGTH_LOW);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
DRIVE_STRENGTH_MED);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(SLEWRATE);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
seq_printf(s, "(%d)", val);
}
return;
}
static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned group)
{
}
static const struct pinconf_ops at91_pinconf_ops = {
.pin_config_get = at91_pinconf_get,
.pin_config_set = at91_pinconf_set,
.pin_config_dbg_show = at91_pinconf_dbg_show,
.pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
};
static struct pinctrl_desc at91_pinctrl_desc = {
.pctlops = &at91_pctrl_ops,
.pmxops = &at91_pmx_ops,
.confops = &at91_pinconf_ops,
.owner = THIS_MODULE,
};
static const char *gpio_compat = "atmel,at91rm9200-gpio";
static void at91_pinctrl_child_count(struct at91_pinctrl *info,
struct device_node *np)
{
struct device_node *child;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat)) {
if (of_device_is_available(child))
info->nactive_banks++;
} else {
info->nfunctions++;
info->ngroups += of_get_child_count(child);
}
}
}
static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
struct device_node *np)
{
int ret = 0;
int size;
const __be32 *list;
list = of_get_property(np, "atmel,mux-mask", &size);
if (!list) {
dev_err(info->dev, "can not read the mux-mask of %d\n", size);
return -EINVAL;
}
size /= sizeof(*list);
if (!size || size % gpio_banks) {
dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
return -EINVAL;
}
info->nmux = size / gpio_banks;
info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
GFP_KERNEL);
if (!info->mux_mask)
return -ENOMEM;
ret = of_property_read_u32_array(np, "atmel,mux-mask",
info->mux_mask, size);
if (ret)
dev_err(info->dev, "can not read the mux-mask of %d\n", size);
return ret;
}
static int at91_pinctrl_parse_groups(struct device_node *np,
struct at91_pin_group *grp,
struct at91_pinctrl *info, u32 index)
{
struct at91_pmx_pin *pin;
int size;
const __be32 *list;
int i, j;
dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
/* Initialise group */
grp->name = np->name;
/*
* the binding format is atmel,pins = <bank pin mux CONFIG ...>,
* do sanity check and calculate pins number
*/
list = of_get_property(np, "atmel,pins", &size);
/* we do not check return since it's safe node passed down */
size /= sizeof(*list);
if (!size || size % 4) {
dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
return -EINVAL;
}
grp->npins = size / 4;
pin = grp->pins_conf = devm_kcalloc(info->dev,
grp->npins,
sizeof(struct at91_pmx_pin),
GFP_KERNEL);
grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
GFP_KERNEL);
if (!grp->pins_conf || !grp->pins)
return -ENOMEM;
for (i = 0, j = 0; i < size; i += 4, j++) {
pin->bank = be32_to_cpu(*list++);
pin->pin = be32_to_cpu(*list++);
grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
pin->mux = be32_to_cpu(*list++);
pin->conf = be32_to_cpu(*list++);
at91_pin_dbg(info->dev, pin);
pin++;
}
return 0;
}
static int at91_pinctrl_parse_functions(struct device_node *np,
struct at91_pinctrl *info, u32 index)
{
struct device_node *child;
struct at91_pmx_func *func;
struct at91_pin_group *grp;
int ret;
static u32 grp_index;
u32 i = 0;
dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
func = &info->functions[index];
/* Initialise function */
func->name = np->name;
func->ngroups = of_get_child_count(np);
if (func->ngroups == 0) {
dev_err(info->dev, "no groups defined\n");
return -EINVAL;
}
func->groups = devm_kcalloc(info->dev,
func->ngroups, sizeof(char *), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = at91_pinctrl_parse_groups(child, grp, info, i++);
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;
}
static const struct of_device_id at91_pinctrl_of_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
{ .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
{ /* sentinel */ }
};
static int at91_pinctrl_probe_dt(struct platform_device *pdev,
struct at91_pinctrl *info)
{
struct device *dev = &pdev->dev;
int ret = 0;
int i, j, ngpio_chips_enabled = 0;
uint32_t *tmp;
struct device_node *np = dev->of_node;
struct device_node *child;
if (!np)
return -ENODEV;
info->dev = dev;
info->ops = of_device_get_match_data(dev);
at91_pinctrl_child_count(info, np);
/*
* We need all the GPIO drivers to probe FIRST, or we will not be able
* to obtain references to the struct gpio_chip * for them, and we
* need this to proceed.
*/
for (i = 0; i < MAX_GPIO_BANKS; i++)
if (gpio_chips[i])
ngpio_chips_enabled++;
if (ngpio_chips_enabled < info->nactive_banks)
return -EPROBE_DEFER;
ret = at91_pinctrl_mux_mask(info, np);
if (ret)
return ret;
dev_dbg(dev, "nmux = %d\n", info->nmux);
dev_dbg(dev, "mux-mask\n");
tmp = info->mux_mask;
for (i = 0; i < gpio_banks; i++) {
for (j = 0; j < info->nmux; j++, tmp++) {
dev_dbg(dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
}
}
dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
dev_dbg(dev, "ngroups = %d\n", info->ngroups);
info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions),
GFP_KERNEL);
if (!info->functions)
return -ENOMEM;
info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups),
GFP_KERNEL);
if (!info->groups)
return -ENOMEM;
dev_dbg(dev, "nbanks = %d\n", gpio_banks);
dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
dev_dbg(dev, "ngroups = %d\n", info->ngroups);
i = 0;
for_each_child_of_node(np, child) {
if (of_device_is_compatible(child, gpio_compat))
continue;
ret = at91_pinctrl_parse_functions(child, info, i++);
if (ret) {
of_node_put(child);
return dev_err_probe(dev, ret, "failed to parse function\n");
}
}
return 0;
}
static int at91_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct at91_pinctrl *info;
struct pinctrl_pin_desc *pdesc;
int ret, i, j, k;
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
ret = at91_pinctrl_probe_dt(pdev, info);
if (ret)
return ret;
at91_pinctrl_desc.name = dev_name(dev);
at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
at91_pinctrl_desc.pins = pdesc =
devm_kcalloc(dev, at91_pinctrl_desc.npins, sizeof(*pdesc), GFP_KERNEL);
if (!at91_pinctrl_desc.pins)
return -ENOMEM;
for (i = 0, k = 0; i < gpio_banks; i++) {
char **names;
names = devm_kasprintf_strarray(dev, "pio", MAX_NB_GPIO_PER_BANK);
if (IS_ERR(names))
return PTR_ERR(names);
for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
char *name = names[j];
strreplace(name, '-', i + 'A');
pdesc->number = k;
pdesc->name = name;
pdesc++;
}
}
platform_set_drvdata(pdev, info);
info->pctl = devm_pinctrl_register(dev, &at91_pinctrl_desc, info);
if (IS_ERR(info->pctl))
return dev_err_probe(dev, PTR_ERR(info->pctl), "could not register AT91 pinctrl driver\n");
/* We will handle a range of GPIO pins */
for (i = 0; i < gpio_banks; i++)
if (gpio_chips[i])
pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
dev_info(dev, "initialized AT91 pinctrl driver\n");
return 0;
}
static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
u32 osr;
osr = readl_relaxed(pio + PIO_OSR);
if (osr & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
writel_relaxed(mask, pio + PIO_ODR);
return 0;
}
static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
u32 pdsr;
pdsr = readl_relaxed(pio + PIO_PDSR);
return (pdsr & mask) != 0;
}
static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
int val)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
}
static void at91_gpio_set_multiple(struct gpio_chip *chip,
unsigned long *mask, unsigned long *bits)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
writel_relaxed(set_mask, pio + PIO_SODR);
writel_relaxed(clear_mask, pio + PIO_CODR);
}
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int val)
{
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << offset;
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
writel_relaxed(mask, pio + PIO_OER);
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
enum at91_mux mode;
int i;
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
void __iomem *pio = at91_gpio->regbase;
const char *gpio_label;
for_each_requested_gpio(chip, i, gpio_label) {
unsigned mask = pin_to_mask(i);
mode = at91_gpio->ops->get_periph(pio, mask);
seq_printf(s, "[%s] GPIO%s%d: ",
gpio_label, chip->label, i);
if (mode == AT91_MUX_GPIO) {
seq_printf(s, "[gpio] ");
seq_printf(s, "%s ",
readl_relaxed(pio + PIO_OSR) & mask ?
"output" : "input");
seq_printf(s, "%s\n",
readl_relaxed(pio + PIO_PDSR) & mask ?
"set" : "clear");
} else {
seq_printf(s, "[periph %c]\n",
mode + 'A' - 1);
}
}
}
#else
#define at91_gpio_dbg_show NULL
#endif
static int gpio_irq_request_resources(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
return gpiochip_lock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
}
static void gpio_irq_release_resources(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
gpiochip_unlock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
}
/* Several AIC controller irqs are dispatched through this GPIO handler.
* To use any AT91_PIN_* as an externally triggered IRQ, first call
* at91_set_gpio_input() then maybe enable its glitch filter.
* Then just request_irq() with the pin ID; it works like any ARM IRQ
* handler.
* First implementation always triggers on rising and falling edges
* whereas the newer PIO3 can be additionally configured to trigger on
* level, edge with any polarity.
*
* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
* configuring them with at91_set_a_periph() or at91_set_b_periph().
* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
*/
static void gpio_irq_mask(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << d->hwirq;
unsigned gpio = irqd_to_hwirq(d);
gpiochip_disable_irq(&at91_gpio->chip, gpio);
if (pio)
writel_relaxed(mask, pio + PIO_IDR);
}
static void gpio_irq_unmask(struct irq_data *d)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << d->hwirq;
unsigned gpio = irqd_to_hwirq(d);
gpiochip_enable_irq(&at91_gpio->chip, gpio);
if (pio)
writel_relaxed(mask, pio + PIO_IER);
}
static int gpio_irq_type(struct irq_data *d, unsigned type)
{
switch (type) {
case IRQ_TYPE_NONE:
case IRQ_TYPE_EDGE_BOTH:
return 0;
default:
return -EINVAL;
}
}
/* Alternate irq type for PIO3 support */
static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
void __iomem *pio = at91_gpio->regbase;
unsigned mask = 1 << d->hwirq;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
irq_set_handler_locked(d, handle_simple_irq);
writel_relaxed(mask, pio + PIO_ESR);
writel_relaxed(mask, pio + PIO_REHLSR);
break;
case IRQ_TYPE_EDGE_FALLING:
irq_set_handler_locked(d, handle_simple_irq);
writel_relaxed(mask, pio + PIO_ESR);
writel_relaxed(mask, pio + PIO_FELLSR);
break;
case IRQ_TYPE_LEVEL_LOW:
irq_set_handler_locked(d, handle_level_irq);
writel_relaxed(mask, pio + PIO_LSR);
writel_relaxed(mask, pio + PIO_FELLSR);
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_set_handler_locked(d, handle_level_irq);
writel_relaxed(mask, pio + PIO_LSR);
writel_relaxed(mask, pio + PIO_REHLSR);
break;
case IRQ_TYPE_EDGE_BOTH:
/*
* disable additional interrupt modes:
* fall back to default behavior
*/
irq_set_handler_locked(d, handle_simple_irq);
writel_relaxed(mask, pio + PIO_AIMDR);
return 0;
case IRQ_TYPE_NONE:
default:
pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
return -EINVAL;
}
/* enable additional interrupt modes */
writel_relaxed(mask, pio + PIO_AIMER);
return 0;
}
static void gpio_irq_ack(struct irq_data *d)
{
/* the interrupt is already cleared before by reading ISR */
}
static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
{
struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
unsigned mask = 1 << d->hwirq;
if (state)
at91_gpio->wakeups |= mask;
else
at91_gpio->wakeups &= ~mask;
irq_set_irq_wake(at91_gpio->pioc_virq, state);
return 0;
}
static int at91_gpio_suspend(struct device *dev)
{
struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
void __iomem *pio = at91_chip->regbase;
at91_chip->backups = readl_relaxed(pio + PIO_IMR);
writel_relaxed(at91_chip->backups, pio + PIO_IDR);
writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
if (!at91_chip->wakeups)
clk_disable_unprepare(at91_chip->clock);
else
dev_dbg(dev, "GPIO-%c may wake for %08x\n",
'A' + at91_chip->id, at91_chip->wakeups);
return 0;
}
static int at91_gpio_resume(struct device *dev)
{
struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
void __iomem *pio = at91_chip->regbase;
if (!at91_chip->wakeups)
clk_prepare_enable(at91_chip->clock);
writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
writel_relaxed(at91_chip->backups, pio + PIO_IER);
return 0;
}
static void gpio_irq_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
void __iomem *pio = at91_gpio->regbase;
unsigned long isr;
int n;
chained_irq_enter(chip, desc);
for (;;) {
/* Reading ISR acks pending (edge triggered) GPIO interrupts.
* When there are none pending, we're finished unless we need
* to process multiple banks (like ID_PIOCDE on sam9263).
*/
isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
if (!isr) {
if (!at91_gpio->next)
break;
at91_gpio = at91_gpio->next;
pio = at91_gpio->regbase;
gpio_chip = &at91_gpio->chip;
continue;
}
for_each_set_bit(n, &isr, BITS_PER_LONG)
generic_handle_domain_irq(gpio_chip->irq.domain, n);
}
chained_irq_exit(chip, desc);
/* now it may re-trigger */
}
static int at91_gpio_of_irq_setup(struct platform_device *pdev,
struct at91_gpio_chip *at91_gpio)
{
struct device *dev = &pdev->dev;
struct gpio_chip *gpiochip_prev = NULL;
struct at91_gpio_chip *prev = NULL;
struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
struct irq_chip *gpio_irqchip;
struct gpio_irq_chip *girq;
int i;
gpio_irqchip = devm_kzalloc(dev, sizeof(*gpio_irqchip), GFP_KERNEL);
if (!gpio_irqchip)
return -ENOMEM;
at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
gpio_irqchip->name = "GPIO";
gpio_irqchip->irq_request_resources = gpio_irq_request_resources;
gpio_irqchip->irq_release_resources = gpio_irq_release_resources;
gpio_irqchip->irq_ack = gpio_irq_ack;
gpio_irqchip->irq_disable = gpio_irq_mask;
gpio_irqchip->irq_mask = gpio_irq_mask;
gpio_irqchip->irq_unmask = gpio_irq_unmask;
gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
gpio_irqchip->flags = IRQCHIP_IMMUTABLE;
/* Disable irqs of this PIO controller */
writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
/*
* Let the generic code handle this edge IRQ, the chained
* handler will perform the actual work of handling the parent
* interrupt.
*/
girq = &at91_gpio->chip.irq;
gpio_irq_chip_set_chip(girq, gpio_irqchip);
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_edge_irq;
/*
* The top level handler handles one bank of GPIOs, except
* on some SoC it can handle up to three...
* We only set up the handler for the first of the list.
*/
gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
if (!gpiochip_prev) {
girq->parent_handler = gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = at91_gpio->pioc_virq;
return 0;
}
prev = gpiochip_get_data(gpiochip_prev);
/* we can only have 2 banks before */
for (i = 0; i < 2; i++) {
if (prev->next) {
prev = prev->next;
} else {
prev->next = at91_gpio;
return 0;
}
}
return -EINVAL;
}
/* This structure is replicated for each GPIO block allocated at probe time */
static const struct gpio_chip at91_gpio_template = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = at91_gpio_get_direction,
.direction_input = at91_gpio_direction_input,
.get = at91_gpio_get,
.direction_output = at91_gpio_direction_output,
.set = at91_gpio_set,
.set_multiple = at91_gpio_set_multiple,
.dbg_show = at91_gpio_dbg_show,
.can_sleep = false,
.ngpio = MAX_NB_GPIO_PER_BANK,
};
static const struct of_device_id at91_gpio_of_match[] = {
{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
{ .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
{ /* sentinel */ }
};
static int at91_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct at91_gpio_chip *at91_chip = NULL;
struct gpio_chip *chip;
struct pinctrl_gpio_range *range;
int ret = 0;
int irq, i;
int alias_idx = of_alias_get_id(np, "gpio");
uint32_t ngpio;
char **names;
BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
if (gpio_chips[alias_idx])
return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
at91_chip = devm_kzalloc(dev, sizeof(*at91_chip), GFP_KERNEL);
if (!at91_chip)
return -ENOMEM;
at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(at91_chip->regbase))
return PTR_ERR(at91_chip->regbase);
at91_chip->ops = of_device_get_match_data(dev);
at91_chip->pioc_virq = irq;
at91_chip->clock = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(at91_chip->clock))
return dev_err_probe(dev, PTR_ERR(at91_chip->clock), "failed to get clock, ignoring.\n");
at91_chip->chip = at91_gpio_template;
at91_chip->id = alias_idx;
chip = &at91_chip->chip;
chip->label = dev_name(dev);
chip->parent = dev;
chip->owner = THIS_MODULE;
chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
if (ngpio >= MAX_NB_GPIO_PER_BANK)
dev_err(dev, "at91_gpio.%d, gpio-nb >= %d failback to %d\n",
alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
else
chip->ngpio = ngpio;
}
names = devm_kasprintf_strarray(dev, "pio", chip->ngpio);
if (IS_ERR(names))
return PTR_ERR(names);
for (i = 0; i < chip->ngpio; i++)
strreplace(names[i], '-', alias_idx + 'A');
chip->names = (const char *const *)names;
range = &at91_chip->range;
range->name = chip->label;
range->id = alias_idx;
range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
range->npins = chip->ngpio;
range->gc = chip;
ret = at91_gpio_of_irq_setup(pdev, at91_chip);
if (ret)
return ret;
ret = gpiochip_add_data(chip, at91_chip);
if (ret)
return ret;
gpio_chips[alias_idx] = at91_chip;
platform_set_drvdata(pdev, at91_chip);
gpio_banks = max(gpio_banks, alias_idx + 1);
dev_info(dev, "at address %p\n", at91_chip->regbase);
return 0;
}
static DEFINE_NOIRQ_DEV_PM_OPS(at91_gpio_pm_ops, at91_gpio_suspend, at91_gpio_resume);
static struct platform_driver at91_gpio_driver = {
.driver = {
.name = "gpio-at91",
.of_match_table = at91_gpio_of_match,
.pm = pm_sleep_ptr(&at91_gpio_pm_ops),
},
.probe = at91_gpio_probe,
};
static struct platform_driver at91_pinctrl_driver = {
.driver = {
.name = "pinctrl-at91",
.of_match_table = at91_pinctrl_of_match,
},
.probe = at91_pinctrl_probe,
};
static struct platform_driver * const drivers[] = {
&at91_gpio_driver,
&at91_pinctrl_driver,
};
static int __init at91_pinctrl_init(void)
{
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
arch_initcall(at91_pinctrl_init);
|
linux-master
|
drivers/pinctrl/pinctrl-at91.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* MAX77620 pin control driver.
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Chaitanya Bandi <[email protected]>
* Laxman Dewangan <[email protected]>
*/
#include <linux/mfd/max77620.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#define MAX77620_PIN_NUM 8
enum max77620_pin_ppdrv {
MAX77620_PIN_UNCONFIG_DRV,
MAX77620_PIN_OD_DRV,
MAX77620_PIN_PP_DRV,
};
#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
struct max77620_pin_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
int mux_option;
};
static const struct pinconf_generic_params max77620_cfg_params[] = {
{
.property = "maxim,active-fps-source",
.param = MAX77620_ACTIVE_FPS_SOURCE,
}, {
.property = "maxim,active-fps-power-up-slot",
.param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
}, {
.property = "maxim,active-fps-power-down-slot",
.param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
}, {
.property = "maxim,suspend-fps-source",
.param = MAX77620_SUSPEND_FPS_SOURCE,
}, {
.property = "maxim,suspend-fps-power-up-slot",
.param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
}, {
.property = "maxim,suspend-fps-power-down-slot",
.param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
},
};
enum max77620_alternate_pinmux_option {
MAX77620_PINMUX_GPIO = 0,
MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
MAX77620_PINMUX_32K_OUT1 = 3,
MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
MAX77620_PINMUX_REFERENCE_OUT = 6,
};
struct max77620_pingroup {
const char *name;
const unsigned int pins[1];
unsigned int npins;
enum max77620_alternate_pinmux_option alt_option;
};
struct max77620_pin_info {
enum max77620_pin_ppdrv drv_type;
int pull_config;
};
struct max77620_fps_config {
int active_fps_src;
int active_power_up_slots;
int active_power_down_slots;
int suspend_fps_src;
int suspend_power_up_slots;
int suspend_power_down_slots;
};
struct max77620_pctrl_info {
struct device *dev;
struct pinctrl_dev *pctl;
struct regmap *rmap;
int pins_current_opt[MAX77620_GPIO_NR];
const struct max77620_pin_function *functions;
unsigned int num_functions;
const struct max77620_pingroup *pin_groups;
int num_pin_groups;
const struct pinctrl_pin_desc *pins;
unsigned int num_pins;
struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
};
static const struct pinctrl_pin_desc max77620_pins_desc[] = {
PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
};
static const char * const gpio_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
};
#define FUNCTION_GROUP(fname, mux) \
{ \
.name = fname, \
.groups = gpio_groups, \
.ngroups = ARRAY_SIZE(gpio_groups), \
.mux_option = MAX77620_PINMUX_##mux, \
}
static const struct max77620_pin_function max77620_pin_function[] = {
FUNCTION_GROUP("gpio", GPIO),
FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
FUNCTION_GROUP("32k-out1", 32K_OUT1),
FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
FUNCTION_GROUP("reference-out", REFERENCE_OUT),
};
#define MAX77620_PINGROUP(pg_name, pin_id, option) \
{ \
.name = #pg_name, \
.pins = {MAX77620_##pin_id}, \
.npins = 1, \
.alt_option = MAX77620_PINMUX_##option, \
}
static const struct max77620_pingroup max77620_pingroups[] = {
MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
};
static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
return mpci->num_pin_groups;
}
static const char *max77620_pinctrl_get_group_name(
struct pinctrl_dev *pctldev, unsigned int group)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
return mpci->pin_groups[group].name;
}
static int max77620_pinctrl_get_group_pins(
struct pinctrl_dev *pctldev, unsigned int group,
const unsigned int **pins, unsigned int *num_pins)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
*pins = mpci->pin_groups[group].pins;
*num_pins = mpci->pin_groups[group].npins;
return 0;
}
static const struct pinctrl_ops max77620_pinctrl_ops = {
.get_groups_count = max77620_pinctrl_get_groups_count,
.get_group_name = max77620_pinctrl_get_group_name,
.get_group_pins = max77620_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
return mpci->num_functions;
}
static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
return mpci->functions[function].name;
}
static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
*groups = mpci->functions[function].groups;
*num_groups = mpci->functions[function].ngroups;
return 0;
}
static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
u8 val;
int ret;
if (function == MAX77620_PINMUX_GPIO) {
val = 0;
} else if (function == mpci->pin_groups[group].alt_option) {
val = 1 << group;
} else {
dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
group, function);
return -EINVAL;
}
ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
BIT(group), val);
if (ret < 0)
dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
return ret;
}
static const struct pinmux_ops max77620_pinmux_ops = {
.get_functions_count = max77620_pinctrl_get_funcs_count,
.get_function_name = max77620_pinctrl_get_func_name,
.get_function_groups = max77620_pinctrl_get_func_groups,
.set_mux = max77620_pinctrl_enable,
};
static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = mpci->dev;
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int val;
int arg = 0;
int ret;
switch (param) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
arg = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
if (ret < 0) {
dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
return ret;
}
if (val & BIT(pin))
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
if (ret < 0) {
dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
return ret;
}
if (val & BIT(pin))
arg = 1;
break;
default:
dev_err(dev, "Properties not supported\n");
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, (u16)arg);
return 0;
}
static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
int addr, int *fps)
{
unsigned int val;
int ret;
ret = regmap_read(mpci->rmap, addr, &val);
if (ret < 0) {
dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
return ret;
}
*fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
return 0;
}
static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
int pin, int param)
{
struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
int addr, ret;
int param_val;
int mask, shift;
if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
return 0;
addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
switch (param) {
case MAX77620_ACTIVE_FPS_SOURCE:
case MAX77620_SUSPEND_FPS_SOURCE:
mask = MAX77620_FPS_SRC_MASK;
shift = MAX77620_FPS_SRC_SHIFT;
param_val = fps_config->active_fps_src;
if (param == MAX77620_SUSPEND_FPS_SOURCE)
param_val = fps_config->suspend_fps_src;
break;
case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
mask = MAX77620_FPS_PU_PERIOD_MASK;
shift = MAX77620_FPS_PU_PERIOD_SHIFT;
param_val = fps_config->active_power_up_slots;
if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
param_val = fps_config->suspend_power_up_slots;
break;
case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
mask = MAX77620_FPS_PD_PERIOD_MASK;
shift = MAX77620_FPS_PD_PERIOD_SHIFT;
param_val = fps_config->active_power_down_slots;
if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
param_val = fps_config->suspend_power_down_slots;
break;
default:
dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
param, pin);
return -EINVAL;
}
if (param_val < 0)
return 0;
ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
if (ret < 0)
dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
return ret;
}
static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = mpci->dev;
struct max77620_fps_config *fps_config;
int param;
u32 param_val;
unsigned int val;
unsigned int pu_val;
unsigned int pd_val;
int addr, ret;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
val = param_val ? 0 : 1;
ret = regmap_update_bits(mpci->rmap,
MAX77620_REG_GPIO0 + pin,
MAX77620_CNFG_GPIO_DRV_MASK,
val);
if (ret)
goto report_update_failure;
mpci->pin_info[pin].drv_type = val ?
MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
val = param_val ? 1 : 0;
ret = regmap_update_bits(mpci->rmap,
MAX77620_REG_GPIO0 + pin,
MAX77620_CNFG_GPIO_DRV_MASK,
val);
if (ret)
goto report_update_failure;
mpci->pin_info[pin].drv_type = val ?
MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
break;
case MAX77620_ACTIVE_FPS_SOURCE:
case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
return -EINVAL;
fps_config = &mpci->fps_config[pin];
if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
(param_val == MAX77620_FPS_SRC_DEF)) {
addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
ret = max77620_get_default_fps(
mpci, addr,
&fps_config->active_fps_src);
if (ret < 0)
return ret;
break;
}
if (param == MAX77620_ACTIVE_FPS_SOURCE)
fps_config->active_fps_src = param_val;
else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
fps_config->active_power_up_slots = param_val;
else
fps_config->active_power_down_slots = param_val;
ret = max77620_set_fps_param(mpci, pin, param);
if (ret < 0)
return ret;
break;
case MAX77620_SUSPEND_FPS_SOURCE:
case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
return -EINVAL;
fps_config = &mpci->fps_config[pin];
if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
(param_val == MAX77620_FPS_SRC_DEF)) {
addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
ret = max77620_get_default_fps(
mpci, addr,
&fps_config->suspend_fps_src);
if (ret < 0)
return ret;
break;
}
if (param == MAX77620_SUSPEND_FPS_SOURCE)
fps_config->suspend_fps_src = param_val;
else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
fps_config->suspend_power_up_slots = param_val;
else
fps_config->suspend_power_down_slots =
param_val;
break;
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
BIT(pin) : 0;
pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
BIT(pin) : 0;
ret = regmap_update_bits(mpci->rmap,
MAX77620_REG_PUE_GPIO,
BIT(pin), pu_val);
if (ret < 0) {
dev_err(dev, "PUE_GPIO update failed: %d\n",
ret);
return ret;
}
ret = regmap_update_bits(mpci->rmap,
MAX77620_REG_PDE_GPIO,
BIT(pin), pd_val);
if (ret < 0) {
dev_err(dev, "PDE_GPIO update failed: %d\n",
ret);
return ret;
}
break;
default:
dev_err(dev, "Properties not supported\n");
return -ENOTSUPP;
}
}
return 0;
report_update_failure:
dev_err(dev, "Reg 0x%02x update failed %d\n",
MAX77620_REG_GPIO0 + pin, ret);
return ret;
}
static const struct pinconf_ops max77620_pinconf_ops = {
.pin_config_get = max77620_pinconf_get,
.pin_config_set = max77620_pinconf_set,
};
static struct pinctrl_desc max77620_pinctrl_desc = {
.pctlops = &max77620_pinctrl_ops,
.pmxops = &max77620_pinmux_ops,
.confops = &max77620_pinconf_ops,
};
static int max77620_pinctrl_probe(struct platform_device *pdev)
{
struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
struct max77620_pctrl_info *mpci;
int i;
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
if (!mpci)
return -ENOMEM;
mpci->dev = &pdev->dev;
mpci->rmap = max77620->rmap;
mpci->pins = max77620_pins_desc;
mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
mpci->functions = max77620_pin_function;
mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
mpci->pin_groups = max77620_pingroups;
mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
platform_set_drvdata(pdev, mpci);
max77620_pinctrl_desc.name = dev_name(&pdev->dev);
max77620_pinctrl_desc.pins = max77620_pins_desc;
max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
max77620_pinctrl_desc.num_custom_params =
ARRAY_SIZE(max77620_cfg_params);
max77620_pinctrl_desc.custom_params = max77620_cfg_params;
for (i = 0; i < MAX77620_PIN_NUM; ++i) {
mpci->fps_config[i].active_fps_src = -1;
mpci->fps_config[i].active_power_up_slots = -1;
mpci->fps_config[i].active_power_down_slots = -1;
mpci->fps_config[i].suspend_fps_src = -1;
mpci->fps_config[i].suspend_power_up_slots = -1;
mpci->fps_config[i].suspend_power_down_slots = -1;
}
mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
mpci);
if (IS_ERR(mpci->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(mpci->pctl);
}
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max77620_suspend_fps_param[] = {
MAX77620_SUSPEND_FPS_SOURCE,
MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
};
static int max77620_active_fps_param[] = {
MAX77620_ACTIVE_FPS_SOURCE,
MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
};
static int max77620_pinctrl_suspend(struct device *dev)
{
struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
int pin, p;
for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
continue;
for (p = 0; p < 3; ++p)
max77620_set_fps_param(
mpci, pin, max77620_suspend_fps_param[p]);
}
return 0;
};
static int max77620_pinctrl_resume(struct device *dev)
{
struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
int pin, p;
for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
continue;
for (p = 0; p < 3; ++p)
max77620_set_fps_param(
mpci, pin, max77620_active_fps_param[p]);
}
return 0;
}
#endif
static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(
max77620_pinctrl_suspend, max77620_pinctrl_resume)
};
static const struct platform_device_id max77620_pinctrl_devtype[] = {
{ .name = "max77620-pinctrl", },
{ .name = "max20024-pinctrl", },
{},
};
MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
static struct platform_driver max77620_pinctrl_driver = {
.driver = {
.name = "max77620-pinctrl",
.pm = &max77620_pinctrl_pm_ops,
},
.probe = max77620_pinctrl_probe,
.id_table = max77620_pinctrl_devtype,
};
module_platform_driver(max77620_pinctrl_driver);
MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
MODULE_AUTHOR("Chaitanya Bandi<[email protected]>");
MODULE_AUTHOR("Laxman Dewangan<[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-max77620.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* PIC32 pinctrl driver
*
* Joshua Henderson, <[email protected]>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/mach-pic32/pic32.h>
#include "pinctrl-utils.h"
#include "pinctrl-pic32.h"
#define PINS_PER_BANK 16
#define PIC32_CNCON_EDGE 11
#define PIC32_CNCON_ON 15
#define PIN_CONFIG_MICROCHIP_DIGITAL (PIN_CONFIG_END + 1)
#define PIN_CONFIG_MICROCHIP_ANALOG (PIN_CONFIG_END + 2)
static const struct pinconf_generic_params pic32_mpp_bindings[] = {
{"microchip,digital", PIN_CONFIG_MICROCHIP_DIGITAL, 0},
{"microchip,analog", PIN_CONFIG_MICROCHIP_ANALOG, 0},
};
#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
struct pic32_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
struct pic32_pin_group {
const char *name;
unsigned int pin;
struct pic32_desc_function *functions;
};
struct pic32_desc_function {
const char *name;
u32 muxreg;
u32 muxval;
};
struct pic32_gpio_bank {
void __iomem *reg_base;
int instance;
struct gpio_chip gpio_chip;
struct clk *clk;
};
struct pic32_pinctrl {
void __iomem *reg_base;
struct device *dev;
struct pinctrl_dev *pctldev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
const struct pic32_function *functions;
unsigned int nfunctions;
const struct pic32_pin_group *groups;
unsigned int ngroups;
struct pic32_gpio_bank *gpio_banks;
unsigned int nbanks;
struct clk *clk;
};
static const struct pinctrl_pin_desc pic32_pins[] = {
PINCTRL_PIN(0, "A0"),
PINCTRL_PIN(1, "A1"),
PINCTRL_PIN(2, "A2"),
PINCTRL_PIN(3, "A3"),
PINCTRL_PIN(4, "A4"),
PINCTRL_PIN(5, "A5"),
PINCTRL_PIN(6, "A6"),
PINCTRL_PIN(7, "A7"),
PINCTRL_PIN(8, "A8"),
PINCTRL_PIN(9, "A9"),
PINCTRL_PIN(10, "A10"),
PINCTRL_PIN(11, "A11"),
PINCTRL_PIN(12, "A12"),
PINCTRL_PIN(13, "A13"),
PINCTRL_PIN(14, "A14"),
PINCTRL_PIN(15, "A15"),
PINCTRL_PIN(16, "B0"),
PINCTRL_PIN(17, "B1"),
PINCTRL_PIN(18, "B2"),
PINCTRL_PIN(19, "B3"),
PINCTRL_PIN(20, "B4"),
PINCTRL_PIN(21, "B5"),
PINCTRL_PIN(22, "B6"),
PINCTRL_PIN(23, "B7"),
PINCTRL_PIN(24, "B8"),
PINCTRL_PIN(25, "B9"),
PINCTRL_PIN(26, "B10"),
PINCTRL_PIN(27, "B11"),
PINCTRL_PIN(28, "B12"),
PINCTRL_PIN(29, "B13"),
PINCTRL_PIN(30, "B14"),
PINCTRL_PIN(31, "B15"),
PINCTRL_PIN(33, "C1"),
PINCTRL_PIN(34, "C2"),
PINCTRL_PIN(35, "C3"),
PINCTRL_PIN(36, "C4"),
PINCTRL_PIN(44, "C12"),
PINCTRL_PIN(45, "C13"),
PINCTRL_PIN(46, "C14"),
PINCTRL_PIN(47, "C15"),
PINCTRL_PIN(48, "D0"),
PINCTRL_PIN(49, "D1"),
PINCTRL_PIN(50, "D2"),
PINCTRL_PIN(51, "D3"),
PINCTRL_PIN(52, "D4"),
PINCTRL_PIN(53, "D5"),
PINCTRL_PIN(54, "D6"),
PINCTRL_PIN(55, "D7"),
PINCTRL_PIN(57, "D9"),
PINCTRL_PIN(58, "D10"),
PINCTRL_PIN(59, "D11"),
PINCTRL_PIN(60, "D12"),
PINCTRL_PIN(61, "D13"),
PINCTRL_PIN(62, "D14"),
PINCTRL_PIN(63, "D15"),
PINCTRL_PIN(64, "E0"),
PINCTRL_PIN(65, "E1"),
PINCTRL_PIN(66, "E2"),
PINCTRL_PIN(67, "E3"),
PINCTRL_PIN(68, "E4"),
PINCTRL_PIN(69, "E5"),
PINCTRL_PIN(70, "E6"),
PINCTRL_PIN(71, "E7"),
PINCTRL_PIN(72, "E8"),
PINCTRL_PIN(73, "E9"),
PINCTRL_PIN(80, "F0"),
PINCTRL_PIN(81, "F1"),
PINCTRL_PIN(82, "F2"),
PINCTRL_PIN(83, "F3"),
PINCTRL_PIN(84, "F4"),
PINCTRL_PIN(85, "F5"),
PINCTRL_PIN(88, "F8"),
PINCTRL_PIN(92, "F12"),
PINCTRL_PIN(93, "F13"),
PINCTRL_PIN(96, "G0"),
PINCTRL_PIN(97, "G1"),
PINCTRL_PIN(102, "G6"),
PINCTRL_PIN(103, "G7"),
PINCTRL_PIN(104, "G8"),
PINCTRL_PIN(105, "G9"),
PINCTRL_PIN(108, "G12"),
PINCTRL_PIN(109, "G13"),
PINCTRL_PIN(110, "G14"),
PINCTRL_PIN(111, "G15"),
PINCTRL_PIN(112, "H0"),
PINCTRL_PIN(113, "H1"),
PINCTRL_PIN(114, "H2"),
PINCTRL_PIN(115, "H3"),
PINCTRL_PIN(116, "H4"),
PINCTRL_PIN(117, "H5"),
PINCTRL_PIN(118, "H6"),
PINCTRL_PIN(119, "H7"),
PINCTRL_PIN(120, "H8"),
PINCTRL_PIN(121, "H9"),
PINCTRL_PIN(122, "H10"),
PINCTRL_PIN(123, "H11"),
PINCTRL_PIN(124, "H12"),
PINCTRL_PIN(125, "H13"),
PINCTRL_PIN(126, "H14"),
PINCTRL_PIN(127, "H15"),
PINCTRL_PIN(128, "J0"),
PINCTRL_PIN(129, "J1"),
PINCTRL_PIN(130, "J2"),
PINCTRL_PIN(131, "J3"),
PINCTRL_PIN(132, "J4"),
PINCTRL_PIN(133, "J5"),
PINCTRL_PIN(134, "J6"),
PINCTRL_PIN(135, "J7"),
PINCTRL_PIN(136, "J8"),
PINCTRL_PIN(137, "J9"),
PINCTRL_PIN(138, "J10"),
PINCTRL_PIN(139, "J11"),
PINCTRL_PIN(140, "J12"),
PINCTRL_PIN(141, "J13"),
PINCTRL_PIN(142, "J14"),
PINCTRL_PIN(143, "J15"),
PINCTRL_PIN(144, "K0"),
PINCTRL_PIN(145, "K1"),
PINCTRL_PIN(146, "K2"),
PINCTRL_PIN(147, "K3"),
PINCTRL_PIN(148, "K4"),
PINCTRL_PIN(149, "K5"),
PINCTRL_PIN(150, "K6"),
PINCTRL_PIN(151, "K7"),
};
static const char * const pic32_input0_group[] = {
"D2", "G8", "F4", "F1", "B9", "B10", "C14", "B5",
"C1", "D14", "G1", "A14", "D6",
};
static const char * const pic32_input1_group[] = {
"D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
"B3", "C4", "G0", "A15", "D7",
};
static const char * const pic32_input2_group[] = {
"D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
"F12", "D12", "F8", "C3", "E9",
};
static const char * const pic32_input3_group[] = {
"G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
"F2", "C2", "E8",
};
static const char * const pic32_output0_group[] = {
"D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
"B5", "C1", "D14", "G1", "A14", "D6",
};
static const char * const pic32_output0_1_group[] = {
"D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14",
"B5", "C1", "D14", "G1", "A14", "D6",
"D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
"B3", "C4", "D15", "G0", "A15", "D7",
};
static const char *const pic32_output1_group[] = {
"D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
"B3", "C4", "D15", "G0", "A15", "D7",
};
static const char *const pic32_output1_3_group[] = {
"D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13",
"B3", "C4", "D15", "G0", "A15", "D7",
"G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
"C2", "E8", "F2",
};
static const char * const pic32_output2_group[] = {
"D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
"F12", "D12", "F8", "C3", "E9",
};
static const char * const pic32_output2_3_group[] = {
"D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
"F12", "D12", "F8", "C3", "E9",
"G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
"C2", "E8", "F2",
};
static const char * const pic32_output3_group[] = {
"G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13",
"C2", "E8", "F2",
};
#define FUNCTION(_name, _gr) \
{ \
.name = #_name, \
.groups = pic32_##_gr##_group, \
.ngroups = ARRAY_SIZE(pic32_##_gr##_group), \
}
static const struct pic32_function pic32_functions[] = {
FUNCTION(INT3, input0),
FUNCTION(T2CK, input0),
FUNCTION(T6CK, input0),
FUNCTION(IC3, input0),
FUNCTION(IC7, input0),
FUNCTION(U1RX, input0),
FUNCTION(U2CTS, input0),
FUNCTION(U5RX, input0),
FUNCTION(U6CTS, input0),
FUNCTION(SDI1, input0),
FUNCTION(SDI3, input0),
FUNCTION(SDI5, input0),
FUNCTION(SS6IN, input0),
FUNCTION(REFCLKI1, input0),
FUNCTION(INT4, input1),
FUNCTION(T5CK, input1),
FUNCTION(T7CK, input1),
FUNCTION(IC4, input1),
FUNCTION(IC8, input1),
FUNCTION(U3RX, input1),
FUNCTION(U4CTS, input1),
FUNCTION(SDI2, input1),
FUNCTION(SDI4, input1),
FUNCTION(C1RX, input1),
FUNCTION(REFCLKI4, input1),
FUNCTION(INT2, input2),
FUNCTION(T3CK, input2),
FUNCTION(T8CK, input2),
FUNCTION(IC2, input2),
FUNCTION(IC5, input2),
FUNCTION(IC9, input2),
FUNCTION(U1CTS, input2),
FUNCTION(U2RX, input2),
FUNCTION(U5CTS, input2),
FUNCTION(SS1IN, input2),
FUNCTION(SS3IN, input2),
FUNCTION(SS4IN, input2),
FUNCTION(SS5IN, input2),
FUNCTION(C2RX, input2),
FUNCTION(INT1, input3),
FUNCTION(T4CK, input3),
FUNCTION(T9CK, input3),
FUNCTION(IC1, input3),
FUNCTION(IC6, input3),
FUNCTION(U3CTS, input3),
FUNCTION(U4RX, input3),
FUNCTION(U6RX, input3),
FUNCTION(SS2IN, input3),
FUNCTION(SDI6, input3),
FUNCTION(OCFA, input3),
FUNCTION(REFCLKI3, input3),
FUNCTION(U3TX, output0),
FUNCTION(U4RTS, output0),
FUNCTION(SDO1, output0_1),
FUNCTION(SDO2, output0_1),
FUNCTION(SDO3, output0_1),
FUNCTION(SDO5, output0_1),
FUNCTION(SS6OUT, output0),
FUNCTION(OC3, output0),
FUNCTION(OC6, output0),
FUNCTION(REFCLKO4, output0),
FUNCTION(C2OUT, output0),
FUNCTION(C1TX, output0),
FUNCTION(U1TX, output1),
FUNCTION(U2RTS, output1),
FUNCTION(U5TX, output1),
FUNCTION(U6RTS, output1),
FUNCTION(SDO4, output1_3),
FUNCTION(OC4, output1),
FUNCTION(OC7, output1),
FUNCTION(REFCLKO1, output1),
FUNCTION(U3RTS, output2),
FUNCTION(U4TX, output2),
FUNCTION(U6TX, output2_3),
FUNCTION(SS1OUT, output2),
FUNCTION(SS3OUT, output2),
FUNCTION(SS4OUT, output2),
FUNCTION(SS5OUT, output2),
FUNCTION(SDO6, output2_3),
FUNCTION(OC5, output2),
FUNCTION(OC8, output2),
FUNCTION(C1OUT, output2),
FUNCTION(REFCLKO3, output2),
FUNCTION(U1RTS, output3),
FUNCTION(U2TX, output3),
FUNCTION(U5RTS, output3),
FUNCTION(SS2OUT, output3),
FUNCTION(OC2, output3),
FUNCTION(OC1, output3),
FUNCTION(OC9, output3),
FUNCTION(C2TX, output3),
};
#define PIC32_PINCTRL_GROUP(_pin, _name, ...) \
{ \
.name = #_name, \
.pin = _pin, \
.functions = (struct pic32_desc_function[]){ \
__VA_ARGS__, { } }, \
}
#define PIC32_PINCTRL_FUNCTION(_name, _muxreg, _muxval) \
{ \
.name = #_name, \
.muxreg = _muxreg, \
.muxval = _muxval, \
}
static const struct pic32_pin_group pic32_groups[] = {
PIC32_PINCTRL_GROUP(14, A14,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 13),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 13),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 13),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 13),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 13),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 13),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 13),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 13),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 13),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 13),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 13),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 13),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 13),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 13),
PIC32_PINCTRL_FUNCTION(U3TX, RPA14R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPA14R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPA14R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPA14R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPA14R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPA14R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPA14R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPA14R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPA14R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPA14R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPA14R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPA14R, 15)),
PIC32_PINCTRL_GROUP(15, A15,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 13),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 13),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 13),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 13),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 13),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 13),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 13),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 13),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 13),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 13),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 13),
PIC32_PINCTRL_FUNCTION(U1TX, RPA15R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPA15R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPA15R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPA15R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPA15R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPA15R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPA15R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPA15R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPA15R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPA15R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPA15R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPA15R, 15)),
PIC32_PINCTRL_GROUP(16, B0,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 5),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 5),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 5),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 5),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 5),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 5),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 5),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 5),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 5),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 5),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 5),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 5),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 5),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 5),
PIC32_PINCTRL_FUNCTION(U3RTS, RPB0R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPB0R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPB0R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPB0R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPB0R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPB0R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPB0R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPB0R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPB0R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPB0R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPB0R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB0R, 15)),
PIC32_PINCTRL_GROUP(17, B1,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 5),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 5),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 5),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 5),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 5),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 5),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 5),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 5),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 5),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 5),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 5),
PIC32_PINCTRL_FUNCTION(U1TX, RPB1R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPB1R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPB1R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPB1R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPB1R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPB1R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPB1R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPB1R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPB1R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPB1R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPB1R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB1R, 15)),
PIC32_PINCTRL_GROUP(18, B2,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 7),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 7),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 7),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 7),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 7),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 7),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 7),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 7),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 7),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 7),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 7),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 7),
PIC32_PINCTRL_FUNCTION(U1RTS, RPB2R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPB2R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPB2R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPB2R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPB2R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPB2R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPB2R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPB2R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPB2R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPB2R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPB2R, 15)),
PIC32_PINCTRL_GROUP(19, B3,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 8),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 8),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 8),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 8),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 8),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 8),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 8),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 8),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 8),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 8),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 8),
PIC32_PINCTRL_FUNCTION(U1TX, RPB3R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPB3R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPB3R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPB3R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPB3R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPB3R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPB3R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPB3R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPB3R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPB3R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPB3R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB3R, 15)),
PIC32_PINCTRL_GROUP(21, B5,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 8),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 8),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 8),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 8),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 8),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 8),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 8),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 8),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 8),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 8),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 8),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 8),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 8),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 8),
PIC32_PINCTRL_FUNCTION(U3TX, RPB5R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPB5R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPB5R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPB5R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPB5R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPB5R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPB5R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPB5R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPB5R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB5R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPB5R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPB5R, 15)),
PIC32_PINCTRL_GROUP(22, B6,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 4),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 4),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 4),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 4),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 4),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 4),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 4),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 4),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 4),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 4),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 4),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 4),
PIC32_PINCTRL_FUNCTION(U1RTS, RPB6R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPB6R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPB6R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPB6R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPB6R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPB6R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPB6R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPB6R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPB6R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPB6R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPB6R, 15)),
PIC32_PINCTRL_GROUP(23, B7,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 7),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 7),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 7),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 7),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 7),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 7),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 7),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 7),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 7),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 7),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 7),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 7),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 7),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 7),
PIC32_PINCTRL_FUNCTION(U3RTS, RPB7R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPB7R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPB7R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPB7R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPB7R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPB7R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPB7R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPB7R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPB7R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPB7R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPB7R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB7R, 15)),
PIC32_PINCTRL_GROUP(24, B8,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 2),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 2),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 2),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 2),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 2),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 2),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 2),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 2),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 2),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 2),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 2),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 2),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 2),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 2),
PIC32_PINCTRL_FUNCTION(U3RTS, RPB8R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPB8R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPB8R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPB8R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPB8R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPB8R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPB8R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPB8R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPB8R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPB8R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPB8R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB8R, 15)),
PIC32_PINCTRL_GROUP(25, B9,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 5),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 5),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 5),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 5),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 5),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 5),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 5),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 5),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 5),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 5),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 5),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 5),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 5),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 5),
PIC32_PINCTRL_FUNCTION(U3TX, RPB9R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPB9R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPB9R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPB9R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPB9R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPB9R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPB9R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPB9R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPB9R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB9R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPB9R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPB9R, 15)),
PIC32_PINCTRL_GROUP(26, B10,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 6),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 6),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 6),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 6),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 6),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 6),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 6),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 6),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 6),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 6),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 6),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 6),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 6),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 6),
PIC32_PINCTRL_FUNCTION(U3TX, RPB10R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPB10R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPB10R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPB10R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPB10R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPB10R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPB10R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPB10R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPB10R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB10R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPB10R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPB10R, 15)),
PIC32_PINCTRL_GROUP(30, B14,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 2),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 2),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 2),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 2),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 2),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 2),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 2),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 2),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 2),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 2),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 2),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 2),
PIC32_PINCTRL_FUNCTION(U1RTS, RPB14R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPB14R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPB14R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPB14R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPB14R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPB14R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPB14R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPB14R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPB14R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPB14R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPB14R, 15)),
PIC32_PINCTRL_GROUP(31, B15,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 3),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 3),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 3),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 3),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 3),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 3),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 3),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 3),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 3),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 3),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 3),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 3),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 3),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 3),
PIC32_PINCTRL_FUNCTION(U3RTS, RPB15R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPB15R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPB15R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPB15R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPB15R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPB15R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPB15R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPB15R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPB15R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPB15R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPB15R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB15R, 15)),
PIC32_PINCTRL_GROUP(33, C1,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 10),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 10),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 10),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 10),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 10),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 10),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 10),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 10),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 10),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 10),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 10),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 10),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 10),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 10),
PIC32_PINCTRL_FUNCTION(U3TX, RPC1R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPC1R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPC1R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPC1R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPC1R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPC1R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPC1R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPC1R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPC1R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC1R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPC1R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPC1R, 15)),
PIC32_PINCTRL_GROUP(34, C2,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 12),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 12),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 12),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 12),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 12),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 12),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 12),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 12),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 12),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 12),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 12),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 12),
PIC32_PINCTRL_FUNCTION(U1RTS, RPC2R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPC2R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPC2R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPC2R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPC2R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPC2R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPC2R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPC2R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPC2R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPC2R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPC2R, 15)),
PIC32_PINCTRL_GROUP(35, C3,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 12),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 12),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 12),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 12),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 12),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 12),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 12),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 12),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 12),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 12),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 12),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 12),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 12),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 12),
PIC32_PINCTRL_FUNCTION(U3RTS, RPC3R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPC3R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPC3R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPC3R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPC3R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPC3R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPC3R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPC3R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPC3R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPC3R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPC3R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPC3R, 15)),
PIC32_PINCTRL_GROUP(36, C4,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 10),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 10),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 10),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 10),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 10),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 10),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 10),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 10),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 10),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 10),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 10),
PIC32_PINCTRL_FUNCTION(U1TX, RPC4R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPC4R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPC4R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPC4R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPC4R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPC4R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPC4R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPC4R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPC4R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPC4R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPC4R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC4R, 15)),
PIC32_PINCTRL_GROUP(45, C13,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 7),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 7),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 7),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 7),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 7),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 7),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 7),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 7),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 7),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 7),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 7),
PIC32_PINCTRL_FUNCTION(U1TX, RPC13R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPC13R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPC13R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPC13R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPC13R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPC13R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPC13R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPC13R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPC13R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPC13R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPC13R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC13R, 15)),
PIC32_PINCTRL_GROUP(46, C14,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 7),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 7),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 7),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 7),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 7),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 7),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 7),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 7),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 7),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 7),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 7),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 7),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 7),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 7),
PIC32_PINCTRL_FUNCTION(U3TX, RPC14R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPC14R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPC14R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPC14R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPC14R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPC14R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPC14R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPC14R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPC14R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC14R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPC14R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPC14R, 15)),
PIC32_PINCTRL_GROUP(48, D0,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 3),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 3),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 3),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 3),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 3),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 3),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 3),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 3),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 3),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 3),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 3),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 3),
PIC32_PINCTRL_FUNCTION(U1RTS, RPD0R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPD0R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPD0R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPD0R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPD0R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPD0R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPD0R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPD0R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPD0R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPD0R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPD0R, 15)),
PIC32_PINCTRL_GROUP(50, D2,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 0),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 0),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 0),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 0),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 0),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 0),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 0),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 0),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 0),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 0),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 0),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 0),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 0),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 0),
PIC32_PINCTRL_FUNCTION(U3TX, RPD2R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPD2R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPD2R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD2R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD2R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPD2R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPD2R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPD2R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPD2R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD2R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPD2R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPD2R, 15)),
PIC32_PINCTRL_GROUP(51, D3,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 0),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 0),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 0),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 0),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 0),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 0),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 0),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 0),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 0),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 0),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 0),
PIC32_PINCTRL_FUNCTION(U1TX, RPD3R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPD3R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPD3R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPD3R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPD3R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD3R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD3R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPD3R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPD3R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPD3R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPD3R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD3R, 15)),
PIC32_PINCTRL_GROUP(52, D4,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 4),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 4),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 4),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 4),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 4),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 4),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 4),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 4),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 4),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 4),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 4),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 4),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 4),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 4),
PIC32_PINCTRL_FUNCTION(U3RTS, RPD4R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPD4R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPD4R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPD4R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPD4R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPD4R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPD4R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPD4R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPD4R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPD4R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPD4R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD4R, 15)),
PIC32_PINCTRL_GROUP(53, D5,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 6),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 6),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 6),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 6),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 6),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 6),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 6),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 6),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 6),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 6),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 6),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 6),
PIC32_PINCTRL_FUNCTION(U1RTS, RPD5R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPD5R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPD5R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPD5R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPD5R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPD5R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPD5R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPD5R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPD5R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPD5R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPD5R, 15)),
PIC32_PINCTRL_GROUP(54, D6,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 14),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 14),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 14),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 14),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 14),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 14),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 14),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 14),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 14),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 14),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 14),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 14),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 14),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 14),
PIC32_PINCTRL_FUNCTION(U3TX, RPD6R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPD6R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPD6R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD6R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD6R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPD6R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPD6R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPD6R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPD6R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD6R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPD6R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPD6R, 15)),
PIC32_PINCTRL_GROUP(55, D7,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 14),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 14),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 14),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 14),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 14),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 14),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 14),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 14),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 14),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 14),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 14),
PIC32_PINCTRL_FUNCTION(U1TX, RPD7R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPD7R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPD7R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPD7R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPD7R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD7R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD7R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPD7R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPD7R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPD7R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPD7R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD7R, 15)),
PIC32_PINCTRL_GROUP(57, D9,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 0),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 0),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 0),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 0),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 0),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 0),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 0),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 0),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 0),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 0),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 0),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 0),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 0),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 0),
PIC32_PINCTRL_FUNCTION(U3RTS, RPD9R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPD9R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPD9R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPD9R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPD9R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPD9R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPD9R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPD9R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPD9R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPD9R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPD9R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD9R, 15)),
PIC32_PINCTRL_GROUP(58, D10,
PIC32_PINCTRL_FUNCTION(U3TX, RPD10R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPD10R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPD10R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD10R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD10R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPD10R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPD10R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPD10R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPD10R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD10R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPD10R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPD10R, 15)),
PIC32_PINCTRL_GROUP(59, D11,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 3),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 3),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 3),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 3),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 3),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 3),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 3),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 3),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 3),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 3),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 3),
PIC32_PINCTRL_FUNCTION(U1TX, RPD11R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPD11R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPD11R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPD11R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPD11R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD11R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD11R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPD11R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPD11R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPD11R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPD11R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD11R, 15)),
PIC32_PINCTRL_GROUP(60, D12,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 10),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 10),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 10),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 10),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 10),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 10),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 10),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 10),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 10),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 10),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 10),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 10),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 10),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 10),
PIC32_PINCTRL_FUNCTION(U3RTS, RPD12R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPD12R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPD12R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPD12R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPD12R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPD12R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPD12R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPD12R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPD12R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPD12R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPD12R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD12R, 15)),
PIC32_PINCTRL_GROUP(62, D14,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 11),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 11),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 11),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 11),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 11),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 11),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 11),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 11),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 11),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 11),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 11),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 11),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 11),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 11),
PIC32_PINCTRL_FUNCTION(U3TX, RPD14R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPD14R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPD14R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD14R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD14R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPD14R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPD14R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPD14R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPD14R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD14R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPD14R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPD14R, 15)),
PIC32_PINCTRL_GROUP(63, D15,
PIC32_PINCTRL_FUNCTION(U1TX, RPD15R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPD15R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPD15R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPD15R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPD15R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPD15R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPD15R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPD15R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPD15R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPD15R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPD15R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD15R, 15)),
PIC32_PINCTRL_GROUP(67, E3,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 6),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 6),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 6),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 6),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 6),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 6),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 6),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 6),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 6),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 6),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 6),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 6),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 6),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 6),
PIC32_PINCTRL_FUNCTION(U3RTS, RPE3R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPE3R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPE3R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPE3R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPE3R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPE3R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPE3R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPE3R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPE3R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPE3R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPE3R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE3R, 15)),
PIC32_PINCTRL_GROUP(69, E5,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 6),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 6),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 6),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 6),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 6),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 6),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 6),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 6),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 6),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 6),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 6),
PIC32_PINCTRL_FUNCTION(U1TX, RPE5R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPE5R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPE5R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPE5R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPE5R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPE5R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPE5R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPE5R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPE5R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPE5R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPE5R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPE5R, 15)),
PIC32_PINCTRL_GROUP(72, E8,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 13),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 13),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 13),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 13),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 13),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 13),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 13),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 13),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 13),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 13),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 13),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 13),
PIC32_PINCTRL_FUNCTION(U1RTS, RPE8R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPE8R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPE8R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPE8R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPE8R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPE8R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPE8R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPE8R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPE8R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPE8R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPE8R, 15)),
PIC32_PINCTRL_GROUP(73, E9,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 13),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 13),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 13),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 13),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 13),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 13),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 13),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 13),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 13),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 13),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 13),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 13),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 13),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 13),
PIC32_PINCTRL_FUNCTION(U3RTS, RPE9R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPE9R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPE9R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPE9R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPE9R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPE9R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPE9R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPE9R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPE9R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPE9R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPE9R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE9R, 15)),
PIC32_PINCTRL_GROUP(80, F0,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 4),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 4),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 4),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 4),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 4),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 4),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 4),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 4),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 4),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 4),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 4),
PIC32_PINCTRL_FUNCTION(U1TX, RPF0R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPF0R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPF0R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPF0R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPF0R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPF0R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPF0R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPF0R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPF0R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPF0R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPF0R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF0R, 15)),
PIC32_PINCTRL_GROUP(81, F1,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 4),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 4),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 4),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 4),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 4),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 4),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 4),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 4),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 4),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 4),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 4),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 4),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 4),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 4),
PIC32_PINCTRL_FUNCTION(U3TX, RPF1R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPF1R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPF1R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPF1R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPF1R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPF1R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPF1R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPF1R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPF1R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF1R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPF1R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPF1R, 15)),
PIC32_PINCTRL_GROUP(82, F2,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 11),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 11),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 11),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 11),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 11),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 11),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 11),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 11),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 11),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 11),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 11),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 11),
PIC32_PINCTRL_FUNCTION(U1RTS, RPF2R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPF2R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPF2R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPF2R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPF2R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPF2R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPF2R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPF2R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPF2R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPF2R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPF2R, 15)),
PIC32_PINCTRL_GROUP(83, F3,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 8),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 8),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 8),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 8),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 8),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 8),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 8),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 8),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 8),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 8),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 8),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 8),
PIC32_PINCTRL_FUNCTION(U1RTS, RPF3R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPF3R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPF3R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPF3R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPF3R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPF3R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPF3R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPF3R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPF3R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPF3R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPF3R, 15)),
PIC32_PINCTRL_GROUP(84, F4,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 2),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 2),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 2),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 2),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 2),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 2),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 2),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 2),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 2),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 2),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 2),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 2),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 2),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 2),
PIC32_PINCTRL_FUNCTION(U3TX, RPF4R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPF4R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPF4R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPF4R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPF4R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPF4R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPF4R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPF4R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPF4R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF4R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPF4R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPF4R, 15)),
PIC32_PINCTRL_GROUP(85, F5,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 2),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 2),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 2),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 2),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 2),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 2),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 2),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 2),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 2),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 2),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 2),
PIC32_PINCTRL_FUNCTION(U1TX, RPF5R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPF5R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPF5R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPF5R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPF5R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPF5R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPF5R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPF5R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPF5R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPF5R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPF5R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF5R, 15)),
PIC32_PINCTRL_GROUP(88, F8,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 11),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 11),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 11),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 11),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 11),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 11),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 11),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 11),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 11),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 11),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 11),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 11),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 11),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 11),
PIC32_PINCTRL_FUNCTION(U3RTS, RPF8R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPF8R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPF8R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPF8R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPF8R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPF8R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPF8R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPF8R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPF8R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPF8R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPF8R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF8R, 15)),
PIC32_PINCTRL_GROUP(92, F12,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 9),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 9),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 9),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 9),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 9),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 9),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 9),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 9),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 9),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 9),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 9),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 9),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 9),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 9),
PIC32_PINCTRL_FUNCTION(U3RTS, RPF12R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPF12R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPF12R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPF12R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPF12R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPF12R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPF12R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPF12R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPF12R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPF12R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPF12R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF12R, 15)),
PIC32_PINCTRL_GROUP(93, F13,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 9),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 9),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 9),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 9),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 9),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 9),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 9),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 9),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 9),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 9),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 9),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 9),
PIC32_PINCTRL_FUNCTION(U1RTS, RPF13R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPF13R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPF13R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPF13R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPF13R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPF13R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPF13R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPF13R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPF13R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPF13R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPF13R, 15)),
PIC32_PINCTRL_GROUP(96, G0,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 12),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 12),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 12),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 12),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 12),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 12),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 12),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 12),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 12),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 12),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 12),
PIC32_PINCTRL_FUNCTION(U1TX, RPG0R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPG0R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPG0R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPG0R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPG0R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPG0R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPG0R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPG0R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPG0R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPG0R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPG0R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG0R, 15)),
PIC32_PINCTRL_GROUP(97, G1,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 12),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 12),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 12),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 12),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 12),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 12),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 12),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 12),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 12),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 12),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 12),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 12),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 12),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 12),
PIC32_PINCTRL_FUNCTION(U3TX, RPG1R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPG1R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPG1R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPG1R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPG1R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPG1R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPG1R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPG1R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPG1R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG1R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPG1R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPG1R, 15)),
PIC32_PINCTRL_GROUP(102, G6,
PIC32_PINCTRL_FUNCTION(INT2, INT2R, 1),
PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 1),
PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 1),
PIC32_PINCTRL_FUNCTION(IC2, IC2R, 1),
PIC32_PINCTRL_FUNCTION(IC5, IC5R, 1),
PIC32_PINCTRL_FUNCTION(IC9, IC9R, 1),
PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 1),
PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 1),
PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 1),
PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 1),
PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 1),
PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 1),
PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 1),
PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 1),
PIC32_PINCTRL_FUNCTION(U3RTS, RPG6R, 1),
PIC32_PINCTRL_FUNCTION(U4TX, RPG6R, 2),
PIC32_PINCTRL_FUNCTION(U6TX, RPG6R, 4),
PIC32_PINCTRL_FUNCTION(SS1OUT, RPG6R, 5),
PIC32_PINCTRL_FUNCTION(SS3OUT, RPG6R, 7),
PIC32_PINCTRL_FUNCTION(SS4OUT, RPG6R, 8),
PIC32_PINCTRL_FUNCTION(SS5OUT, RPG6R, 9),
PIC32_PINCTRL_FUNCTION(SDO6, RPG6R, 10),
PIC32_PINCTRL_FUNCTION(OC5, RPG6R, 11),
PIC32_PINCTRL_FUNCTION(OC8, RPG6R, 12),
PIC32_PINCTRL_FUNCTION(C1OUT, RPG6R, 14),
PIC32_PINCTRL_FUNCTION(REFCLKO3, RPG6R, 15)),
PIC32_PINCTRL_GROUP(103, G7,
PIC32_PINCTRL_FUNCTION(INT4, INT4R, 1),
PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 1),
PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 1),
PIC32_PINCTRL_FUNCTION(IC4, IC4R, 1),
PIC32_PINCTRL_FUNCTION(IC8, IC8R, 1),
PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 1),
PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 1),
PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 1),
PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 1),
PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 1),
PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 1),
PIC32_PINCTRL_FUNCTION(U1TX, RPG7R, 1),
PIC32_PINCTRL_FUNCTION(U2RTS, RPG7R, 2),
PIC32_PINCTRL_FUNCTION(U5TX, RPG7R, 3),
PIC32_PINCTRL_FUNCTION(U6RTS, RPG7R, 4),
PIC32_PINCTRL_FUNCTION(SDO1, RPG7R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPG7R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPG7R, 7),
PIC32_PINCTRL_FUNCTION(SDO4, RPG7R, 8),
PIC32_PINCTRL_FUNCTION(SDO5, RPG7R, 9),
PIC32_PINCTRL_FUNCTION(OC4, RPG7R, 11),
PIC32_PINCTRL_FUNCTION(OC7, RPG7R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG7R, 15)),
PIC32_PINCTRL_GROUP(104, G8,
PIC32_PINCTRL_FUNCTION(INT3, INT3R, 1),
PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 1),
PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 1),
PIC32_PINCTRL_FUNCTION(IC3, IC3R, 1),
PIC32_PINCTRL_FUNCTION(IC7, IC7R, 1),
PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 1),
PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 1),
PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 1),
PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 1),
PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 1),
PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 1),
PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 1),
PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 1),
PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 1),
PIC32_PINCTRL_FUNCTION(U3TX, RPG8R, 1),
PIC32_PINCTRL_FUNCTION(U4RTS, RPG8R, 2),
PIC32_PINCTRL_FUNCTION(SDO1, RPG8R, 5),
PIC32_PINCTRL_FUNCTION(SDO2, RPG8R, 6),
PIC32_PINCTRL_FUNCTION(SDO3, RPG8R, 7),
PIC32_PINCTRL_FUNCTION(SDO5, RPG8R, 9),
PIC32_PINCTRL_FUNCTION(SS6OUT, RPG8R, 10),
PIC32_PINCTRL_FUNCTION(OC3, RPG8R, 11),
PIC32_PINCTRL_FUNCTION(OC6, RPG8R, 12),
PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG8R, 13),
PIC32_PINCTRL_FUNCTION(C2OUT, RPG8R, 14),
PIC32_PINCTRL_FUNCTION(C1TX, RPG8R, 15)),
PIC32_PINCTRL_GROUP(105, G9,
PIC32_PINCTRL_FUNCTION(INT1, INT1R, 1),
PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 1),
PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 1),
PIC32_PINCTRL_FUNCTION(IC1, IC1R, 1),
PIC32_PINCTRL_FUNCTION(IC6, IC6R, 1),
PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 1),
PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 1),
PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 1),
PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 1),
PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 1),
PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 1),
PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 1),
PIC32_PINCTRL_FUNCTION(U1RTS, RPG9R, 1),
PIC32_PINCTRL_FUNCTION(U2TX, RPG9R, 2),
PIC32_PINCTRL_FUNCTION(U5RTS, RPG9R, 3),
PIC32_PINCTRL_FUNCTION(U6TX, RPG9R, 4),
PIC32_PINCTRL_FUNCTION(SS2OUT, RPG9R, 6),
PIC32_PINCTRL_FUNCTION(SDO4, RPG9R, 8),
PIC32_PINCTRL_FUNCTION(SDO6, RPG9R, 10),
PIC32_PINCTRL_FUNCTION(OC2, RPG9R, 11),
PIC32_PINCTRL_FUNCTION(OC1, RPG9R, 12),
PIC32_PINCTRL_FUNCTION(OC9, RPG9R, 13),
PIC32_PINCTRL_FUNCTION(C2TX, RPG9R, 15)),
};
static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d)
{
return gpiochip_get_data(irq_data_get_irq_chip_data(d));
}
static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
unsigned pin)
{
return &pctl->gpio_banks[pin / PINS_PER_BANK];
}
static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = &pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops pic32_pinctrl_ops = {
.get_groups_count = pic32_pinctrl_get_groups_count,
.get_group_name = pic32_pinctrl_get_group_name,
.get_group_pins = pic32_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->nfunctions;
}
static const char *
pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->functions[func].name;
}
static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned func,
const char * const **groups,
unsigned * const num_groups)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->functions[func].groups;
*num_groups = pctl->functions[func].ngroups;
return 0;
}
static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
unsigned func, unsigned group)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct pic32_pin_group *pg = &pctl->groups[group];
const struct pic32_function *pf = &pctl->functions[func];
const char *fname = pf->name;
struct pic32_desc_function *functions = pg->functions;
while (functions->name) {
if (!strcmp(functions->name, fname)) {
dev_dbg(pctl->dev,
"setting function %s reg 0x%x = %d\n",
fname, functions->muxreg, functions->muxval);
writel(functions->muxval, pctl->reg_base + functions->muxreg);
return 0;
}
functions++;
}
dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
return -EINVAL;
}
static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);
u32 mask = BIT(offset - bank->gpio_chip.base);
dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n",
offset, bank->gpio_chip.base, mask);
writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
return 0;
}
static int pic32_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
u32 mask = BIT(offset);
writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));
return 0;
}
static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));
}
static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset,
int value)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
u32 mask = BIT(offset);
if (value)
writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
else
writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));
}
static int pic32_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
u32 mask = BIT(offset);
pic32_gpio_set(chip, offset, value);
writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG));
return 0;
}
static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct gpio_chip *chip = range->gc;
if (input)
pic32_gpio_direction_input(chip, offset);
else
pic32_gpio_direction_output(chip, offset, 0);
return 0;
}
static const struct pinmux_ops pic32_pinmux_ops = {
.get_functions_count = pic32_pinmux_get_functions_count,
.get_function_name = pic32_pinmux_get_function_name,
.get_function_groups = pic32_pinmux_get_function_groups,
.set_mux = pic32_pinmux_enable,
.gpio_request_enable = pic32_gpio_request_enable,
.gpio_set_direction = pic32_gpio_set_direction,
};
static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned param = pinconf_to_config_param(*config);
u32 mask = BIT(pin - bank->gpio_chip.base);
u32 arg;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
arg = !!(readl(bank->reg_base + CNPU_REG) & mask);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = !!(readl(bank->reg_base + CNPD_REG) & mask);
break;
case PIN_CONFIG_MICROCHIP_DIGITAL:
arg = !(readl(bank->reg_base + ANSEL_REG) & mask);
break;
case PIN_CONFIG_MICROCHIP_ANALOG:
arg = !!(readl(bank->reg_base + ANSEL_REG) & mask);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
arg = !!(readl(bank->reg_base + ODCU_REG) & mask);
break;
case PIN_CONFIG_INPUT_ENABLE:
arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
break;
case PIN_CONFIG_OUTPUT:
arg = !(readl(bank->reg_base + TRIS_REG) & mask);
break;
default:
dev_err(pctl->dev, "Property %u not supported\n", param);
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned param;
u32 arg;
unsigned int i;
u32 offset = pin - bank->gpio_chip.base;
u32 mask = BIT(offset);
dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
pin, bank->gpio_chip.base, mask);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
dev_dbg(pctl->dev, " pullup\n");
writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
dev_dbg(pctl->dev, " pulldown\n");
writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));
break;
case PIN_CONFIG_MICROCHIP_DIGITAL:
dev_dbg(pctl->dev, " digital\n");
writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
break;
case PIN_CONFIG_MICROCHIP_ANALOG:
dev_dbg(pctl->dev, " analog\n");
writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
dev_dbg(pctl->dev, " opendrain\n");
writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));
break;
case PIN_CONFIG_INPUT_ENABLE:
pic32_gpio_direction_input(&bank->gpio_chip, offset);
break;
case PIN_CONFIG_OUTPUT:
pic32_gpio_direction_output(&bank->gpio_chip,
offset, arg);
break;
default:
dev_err(pctl->dev, "Property %u not supported\n",
param);
return -ENOTSUPP;
}
}
return 0;
}
static const struct pinconf_ops pic32_pinconf_ops = {
.pin_config_get = pic32_pinconf_get,
.pin_config_set = pic32_pinconf_set,
.is_generic = true,
};
static struct pinctrl_desc pic32_pinctrl_desc = {
.name = "pic32-pinctrl",
.pctlops = &pic32_pinctrl_ops,
.pmxops = &pic32_pinmux_ops,
.confops = &pic32_pinconf_ops,
.owner = THIS_MODULE,
};
static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
if (readl(bank->reg_base + TRIS_REG) & BIT(offset))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static void pic32_gpio_irq_ack(struct irq_data *data)
{
struct pic32_gpio_bank *bank = irqd_to_bank(data);
writel(0, bank->reg_base + CNF_REG);
}
static void pic32_gpio_irq_mask(struct irq_data *data)
{
struct pic32_gpio_bank *bank = irqd_to_bank(data);
writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG));
gpiochip_disable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
}
static void pic32_gpio_irq_unmask(struct irq_data *data)
{
struct pic32_gpio_bank *bank = irqd_to_bank(data);
gpiochip_enable_irq(&bank->gpio_chip, irqd_to_hwirq(data));
writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));
}
static unsigned int pic32_gpio_irq_startup(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
pic32_gpio_direction_input(chip, data->hwirq);
pic32_gpio_irq_unmask(data);
return 0;
}
static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct pic32_gpio_bank *bank = irqd_to_bank(data);
u32 mask = irqd_to_hwirq(data);
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
/* enable RISE */
writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
/* disable FALL */
writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG));
/* enable EDGE */
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
break;
case IRQ_TYPE_EDGE_FALLING:
/* disable RISE */
writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG));
/* enable FALL */
writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
/* enable EDGE */
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
break;
case IRQ_TYPE_EDGE_BOTH:
/* enable RISE */
writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
/* enable FALL */
writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
/* enable EDGE */
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
break;
default:
return -EINVAL;
}
irq_set_handler_locked(data, handle_edge_irq);
return 0;
}
static u32 pic32_gpio_get_pending(struct gpio_chip *gc, unsigned long status)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
u32 pending = 0;
u32 cnen_rise, cnne_fall;
u32 pin;
cnen_rise = readl(bank->reg_base + CNEN_REG);
cnne_fall = readl(bank->reg_base + CNNE_REG);
for_each_set_bit(pin, &status, BITS_PER_LONG) {
u32 mask = BIT(pin);
if ((mask & cnen_rise) || (mask && cnne_fall))
pending |= mask;
}
return pending;
}
static void pic32_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct pic32_gpio_bank *bank = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned int pin;
u32 stat;
chained_irq_enter(chip, desc);
stat = readl(bank->reg_base + CNF_REG);
pending = pic32_gpio_get_pending(gc, stat);
for_each_set_bit(pin, &pending, BITS_PER_LONG)
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}
#define GPIO_BANK(_bank, _npins) \
{ \
.gpio_chip = { \
.label = "GPIO" #_bank, \
.request = gpiochip_generic_request, \
.free = gpiochip_generic_free, \
.get_direction = pic32_gpio_get_direction, \
.direction_input = pic32_gpio_direction_input, \
.direction_output = pic32_gpio_direction_output, \
.get = pic32_gpio_get, \
.set = pic32_gpio_set, \
.ngpio = _npins, \
.base = GPIO_BANK_START(_bank), \
.owner = THIS_MODULE, \
.can_sleep = 0, \
}, \
.instance = (_bank), \
}
static struct pic32_gpio_bank pic32_gpio_banks[] = {
GPIO_BANK(0, PINS_PER_BANK),
GPIO_BANK(1, PINS_PER_BANK),
GPIO_BANK(2, PINS_PER_BANK),
GPIO_BANK(3, PINS_PER_BANK),
GPIO_BANK(4, PINS_PER_BANK),
GPIO_BANK(5, PINS_PER_BANK),
GPIO_BANK(6, PINS_PER_BANK),
GPIO_BANK(7, PINS_PER_BANK),
GPIO_BANK(8, PINS_PER_BANK),
GPIO_BANK(9, PINS_PER_BANK),
};
static void pic32_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct pic32_gpio_bank *bank = irqd_to_bank(data);
seq_printf(p, "GPIO%d", bank->instance);
}
static const struct irq_chip pic32_gpio_irq_chip = {
.irq_startup = pic32_gpio_irq_startup,
.irq_ack = pic32_gpio_irq_ack,
.irq_mask = pic32_gpio_irq_mask,
.irq_unmask = pic32_gpio_irq_unmask,
.irq_set_type = pic32_gpio_irq_set_type,
.irq_print_chip = pic32_gpio_irq_print_chip,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int pic32_pinctrl_probe(struct platform_device *pdev)
{
struct pic32_pinctrl *pctl;
int ret;
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, pctl);
pctl->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctl->reg_base))
return PTR_ERR(pctl->reg_base);
pctl->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pctl->clk)) {
ret = PTR_ERR(pctl->clk);
dev_err(&pdev->dev, "clk get failed\n");
return ret;
}
ret = clk_prepare_enable(pctl->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
return ret;
}
pctl->pins = pic32_pins;
pctl->npins = ARRAY_SIZE(pic32_pins);
pctl->functions = pic32_functions;
pctl->nfunctions = ARRAY_SIZE(pic32_functions);
pctl->groups = pic32_groups;
pctl->ngroups = ARRAY_SIZE(pic32_groups);
pctl->gpio_banks = pic32_gpio_banks;
pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks);
pic32_pinctrl_desc.pins = pctl->pins;
pic32_pinctrl_desc.npins = pctl->npins;
pic32_pinctrl_desc.custom_params = pic32_mpp_bindings;
pic32_pinctrl_desc.num_custom_params = ARRAY_SIZE(pic32_mpp_bindings);
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pic32_pinctrl_desc,
pctl);
if (IS_ERR(pctl->pctldev)) {
dev_err(&pdev->dev, "Failed to register pinctrl device\n");
return PTR_ERR(pctl->pctldev);
}
return 0;
}
static int pic32_gpio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct pic32_gpio_bank *bank;
u32 id;
int irq, ret;
struct gpio_irq_chip *girq;
if (of_property_read_u32(np, "microchip,gpio-bank", &id)) {
dev_err(&pdev->dev, "microchip,gpio-bank property not found\n");
return -EINVAL;
}
if (id >= ARRAY_SIZE(pic32_gpio_banks)) {
dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n");
return -EINVAL;
}
bank = &pic32_gpio_banks[id];
bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(bank->reg_base))
return PTR_ERR(bank->reg_base);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
bank->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(bank->clk)) {
ret = PTR_ERR(bank->clk);
dev_err(&pdev->dev, "clk get failed\n");
return ret;
}
ret = clk_prepare_enable(bank->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
return ret;
}
bank->gpio_chip.parent = &pdev->dev;
girq = &bank->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &pic32_gpio_irq_chip);
girq->parent_handler = pic32_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
girq->parents[0] = irq;
ret = gpiochip_add_data(&bank->gpio_chip, bank);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
id, ret);
return ret;
}
return 0;
}
static const struct of_device_id pic32_pinctrl_of_match[] = {
{ .compatible = "microchip,pic32mzda-pinctrl", },
{ },
};
static struct platform_driver pic32_pinctrl_driver = {
.driver = {
.name = "pic32-pinctrl",
.of_match_table = pic32_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = pic32_pinctrl_probe,
};
static const struct of_device_id pic32_gpio_of_match[] = {
{ .compatible = "microchip,pic32mzda-gpio", },
{ },
};
static struct platform_driver pic32_gpio_driver = {
.driver = {
.name = "pic32-gpio",
.of_match_table = pic32_gpio_of_match,
.suppress_bind_attrs = true,
},
.probe = pic32_gpio_probe,
};
static int __init pic32_gpio_register(void)
{
return platform_driver_register(&pic32_gpio_driver);
}
arch_initcall(pic32_gpio_register);
static int __init pic32_pinctrl_register(void)
{
return platform_driver_register(&pic32_pinctrl_driver);
}
arch_initcall(pic32_pinctrl_register);
|
linux-master
|
drivers/pinctrl/pinctrl-pic32.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Abilis Systems TB10x pin control driver
*
* Copyright (C) Abilis Systems 2012
*
* Author: Christian Ruppert <[email protected]>
*/
#include <linux/stringify.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "pinctrl-utils.h"
#define TB10X_PORT1 (0)
#define TB10X_PORT2 (16)
#define TB10X_PORT3 (32)
#define TB10X_PORT4 (48)
#define TB10X_PORT5 (128)
#define TB10X_PORT6 (64)
#define TB10X_PORT7 (80)
#define TB10X_PORT8 (96)
#define TB10X_PORT9 (112)
#define TB10X_GPIOS (256)
#define PCFG_PORT_BITWIDTH (2)
#define PCFG_PORT_MASK(PORT) \
(((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
static const struct pinctrl_pin_desc tb10x_pins[] = {
/* Port 1 */
PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"),
PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"),
PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"),
PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"),
PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"),
PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"),
PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"),
PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"),
PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"),
PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"),
PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
/* Port 2 */
PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"),
PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"),
PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"),
PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"),
PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"),
PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"),
PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"),
PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"),
PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"),
PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"),
PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"),
/* Port 3 */
PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"),
PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"),
PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"),
PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"),
PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"),
PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"),
PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"),
PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"),
PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"),
PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"),
PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"),
/* Port 4 */
PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"),
PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"),
PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"),
PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"),
PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"),
PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"),
PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"),
PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"),
PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"),
PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"),
PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"),
/* Port 5 */
PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"),
PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"),
PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"),
PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"),
PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"),
PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"),
PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"),
PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"),
PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"),
PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
/* Port 6 */
PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"),
PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"),
PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"),
PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"),
PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"),
PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"),
PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"),
PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"),
PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"),
/* Port 7 */
PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"),
PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"),
PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"),
PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"),
PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"),
PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"),
PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"),
/* Port 8 */
PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"),
PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"),
PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"),
PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
/* Port 9 */
PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"),
PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"),
PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"),
PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"),
/* Unmuxed GPIOs */
PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"),
PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"),
PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"),
PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"),
PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"),
PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"),
PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"),
PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"),
PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"),
PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"),
PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"),
PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"),
PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"),
PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"),
PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"),
PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"),
PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"),
PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"),
PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"),
PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"),
PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"),
PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"),
PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"),
PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"),
#define MAX_PIN (TB10X_GPIOS + 24)
PINCTRL_PIN(MAX_PIN, "GPION4"),
};
/* Port 1 */
static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
TB10X_PORT1 + 2, TB10X_PORT1 + 3};
static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5,
TB10X_PORT1 + 6};
static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8,
TB10X_PORT1 + 9, TB10X_PORT1 + 10};
static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
TB10X_PORT1 + 2, TB10X_PORT1 + 3,
TB10X_PORT1 + 4, TB10X_PORT1 + 5,
TB10X_PORT1 + 6, TB10X_PORT1 + 7,
TB10X_PORT1 + 8, TB10X_PORT1 + 9,
TB10X_PORT1 + 10};
/* Port 2 */
static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
TB10X_PORT2 + 2, TB10X_PORT2 + 3};
static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5,
TB10X_PORT2 + 6};
static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8,
TB10X_PORT2 + 9, TB10X_PORT2 + 10};
static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
TB10X_PORT2 + 2, TB10X_PORT2 + 3,
TB10X_PORT2 + 4, TB10X_PORT2 + 5,
TB10X_PORT2 + 6, TB10X_PORT2 + 7,
TB10X_PORT2 + 8, TB10X_PORT2 + 9,
TB10X_PORT2 + 10};
/* Port 3 */
static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
TB10X_PORT3 + 2, TB10X_PORT3 + 3};
static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5,
TB10X_PORT3 + 6};
static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8,
TB10X_PORT3 + 9, TB10X_PORT3 + 10};
static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
TB10X_PORT3 + 2, TB10X_PORT3 + 3,
TB10X_PORT3 + 4, TB10X_PORT3 + 5,
TB10X_PORT3 + 6, TB10X_PORT3 + 7,
TB10X_PORT3 + 8, TB10X_PORT3 + 9,
TB10X_PORT3 + 10};
/* Port 4 */
static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
TB10X_PORT4 + 2, TB10X_PORT4 + 3};
static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5,
TB10X_PORT4 + 6};
static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8,
TB10X_PORT4 + 9, TB10X_PORT4 + 10};
static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
TB10X_PORT4 + 2, TB10X_PORT4 + 3,
TB10X_PORT4 + 4, TB10X_PORT4 + 5,
TB10X_PORT4 + 6, TB10X_PORT4 + 7,
TB10X_PORT4 + 8, TB10X_PORT4 + 9,
TB10X_PORT4 + 10};
/* Port 6 */
static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
TB10X_PORT6 + 2, TB10X_PORT6 + 3,
TB10X_PORT6 + 4, TB10X_PORT6 + 5,
TB10X_PORT6 + 6, TB10X_PORT6 + 7,
TB10X_PORT6 + 8, TB10X_PORT6 + 9};
static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
TB10X_PORT6 + 2};
static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4,
TB10X_PORT6 + 5};
static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7,
TB10X_PORT6 + 8};
static const unsigned mos3_pins[] = { TB10X_PORT6 + 9};
/* Port 7 */
static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
TB10X_PORT7 + 2, TB10X_PORT7 + 3};
static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
TB10X_PORT7 + 6, TB10X_PORT7 + 7};
static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
TB10X_PORT7 + 2, TB10X_PORT7 + 3};
static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
TB10X_PORT7 + 6, TB10X_PORT7 + 7};
/* Port 8 */
static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
TB10X_PORT8 + 2, TB10X_PORT8 + 3};
static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
TB10X_PORT8 + 2, TB10X_PORT8 + 3};
/* Port 9 */
static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
TB10X_PORT9 + 2, TB10X_PORT9 + 3,
TB10X_PORT9 + 4};
static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
TB10X_PORT9 + 2, TB10X_PORT9 + 3,
TB10X_PORT9 + 4};
/* Port 5 */
static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
TB10X_PORT5 + 2, TB10X_PORT5 + 3,
TB10X_PORT5 + 4, TB10X_PORT5 + 5,
TB10X_PORT5 + 6, TB10X_PORT5 + 7,
TB10X_PORT5 + 8, TB10X_PORT5 + 9,
TB10X_PORT5 + 10, TB10X_PORT5 + 11,
TB10X_PORT5 + 12, TB10X_PORT5 + 13,
TB10X_PORT5 + 14, TB10X_PORT5 + 15,
TB10X_PORT5 + 16, TB10X_PORT5 + 17,
TB10X_PORT5 + 18, TB10X_PORT5 + 19,
TB10X_PORT5 + 20, TB10X_PORT5 + 21,
TB10X_PORT5 + 22, TB10X_PORT5 + 23,
TB10X_PORT5 + 24, TB10X_PORT5 + 25,
TB10X_PORT5 + 26, TB10X_PORT5 + 27,
TB10X_PORT5 + 28, TB10X_PORT5 + 29,
TB10X_PORT5 + 30, TB10X_PORT5 + 31};
static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33,
TB10X_PORT5 + 34, TB10X_PORT5 + 35,
TB10X_PORT5 + 36, TB10X_PORT5 + 37,
TB10X_PORT5 + 38, TB10X_PORT5 + 39,
TB10X_PORT5 + 40, TB10X_PORT5 + 41,
TB10X_PORT5 + 42, TB10X_PORT5 + 43,
TB10X_PORT5 + 44, TB10X_PORT5 + 45,
TB10X_PORT5 + 46, TB10X_PORT5 + 47,
TB10X_PORT5 + 48, TB10X_PORT5 + 49,
TB10X_PORT5 + 50, TB10X_PORT5 + 51,
TB10X_PORT5 + 52, TB10X_PORT5 + 53};
static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
TB10X_PORT5 + 2, TB10X_PORT5 + 3,
TB10X_PORT5 + 4, TB10X_PORT5 + 5,
TB10X_PORT5 + 6, TB10X_PORT5 + 7,
TB10X_PORT5 + 8, TB10X_PORT5 + 9,
TB10X_PORT5 + 10, TB10X_PORT5 + 11,
TB10X_PORT5 + 12, TB10X_PORT5 + 13,
TB10X_PORT5 + 14, TB10X_PORT5 + 15,
TB10X_PORT5 + 16, TB10X_PORT5 + 17,
TB10X_PORT5 + 18, TB10X_PORT5 + 19,
TB10X_PORT5 + 20, TB10X_PORT5 + 21,
TB10X_PORT5 + 22, TB10X_PORT5 + 23,
TB10X_PORT5 + 24, TB10X_PORT5 + 25,
TB10X_PORT5 + 26, TB10X_PORT5 + 27,
TB10X_PORT5 + 28, TB10X_PORT5 + 29,
TB10X_PORT5 + 30, TB10X_PORT5 + 31,
TB10X_PORT5 + 32, TB10X_PORT5 + 33,
TB10X_PORT5 + 34, TB10X_PORT5 + 35,
TB10X_PORT5 + 36, TB10X_PORT5 + 37,
TB10X_PORT5 + 38, TB10X_PORT5 + 39,
TB10X_PORT5 + 40, TB10X_PORT5 + 41,
TB10X_PORT5 + 42, TB10X_PORT5 + 43,
TB10X_PORT5 + 44, TB10X_PORT5 + 45,
TB10X_PORT5 + 46, TB10X_PORT5 + 47,
TB10X_PORT5 + 48, TB10X_PORT5 + 49,
TB10X_PORT5 + 50, TB10X_PORT5 + 51,
TB10X_PORT5 + 52, TB10X_PORT5 + 53};
static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
TB10X_PORT5 + 11, TB10X_PORT5 + 12,
TB10X_PORT5 + 22, TB10X_PORT5 + 23,
TB10X_PORT5 + 33, TB10X_PORT5 + 35,
TB10X_PORT5 + 36, TB10X_PORT5 + 37,
TB10X_PORT5 + 38, TB10X_PORT5 + 39,
TB10X_PORT5 + 40, TB10X_PORT5 + 41,
TB10X_PORT5 + 42, TB10X_PORT5 + 43,
TB10X_PORT5 + 45, TB10X_PORT5 + 46,
TB10X_PORT5 + 47, TB10X_PORT5 + 48,
TB10X_PORT5 + 49, TB10X_PORT5 + 50,
TB10X_PORT5 + 51, TB10X_PORT5 + 52,
TB10X_PORT5 + 53};
static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35,
TB10X_PORT5 + 36, TB10X_PORT5 + 37,
TB10X_PORT5 + 38, TB10X_PORT5 + 39,
TB10X_PORT5 + 40};
static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26,
TB10X_PORT5 + 27, TB10X_PORT5 + 28,
TB10X_PORT5 + 29, TB10X_PORT5 + 30,
TB10X_PORT5 + 44};
/* Unmuxed GPIOs */
static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1};
static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3};
static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5};
static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7};
static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9,
TB10X_GPIOS + 10, TB10X_GPIOS + 11,
TB10X_GPIOS + 12, TB10X_GPIOS + 13,
TB10X_GPIOS + 14, TB10X_GPIOS + 15,
TB10X_GPIOS + 16, TB10X_GPIOS + 17,
TB10X_GPIOS + 18, TB10X_GPIOS + 19};
struct tb10x_pinfuncgrp {
const char *name;
const unsigned int *pins;
const unsigned int pincnt;
const int port;
const unsigned int mode;
const int isgpio;
};
#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
.name = __stringify(NAME), \
.pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \
.port = (PORT), .mode = (MODE), \
.isgpio = (ISGPIO), \
}
static const struct tb10x_pinfuncgrp tb10x_pingroups[] = {
DEFPINFUNCGRP(mis0, 0, 0, 0),
DEFPINFUNCGRP(gpioa, 0, 0, 1),
DEFPINFUNCGRP(mis1, 0, 0, 0),
DEFPINFUNCGRP(mip1, 0, 1, 0),
DEFPINFUNCGRP(mis2, 1, 0, 0),
DEFPINFUNCGRP(gpioc, 1, 0, 1),
DEFPINFUNCGRP(mis3, 1, 0, 0),
DEFPINFUNCGRP(mip3, 1, 1, 0),
DEFPINFUNCGRP(mis4, 2, 0, 0),
DEFPINFUNCGRP(gpioe, 2, 0, 1),
DEFPINFUNCGRP(mis5, 2, 0, 0),
DEFPINFUNCGRP(mip5, 2, 1, 0),
DEFPINFUNCGRP(mis6, 3, 0, 0),
DEFPINFUNCGRP(gpiog, 3, 0, 1),
DEFPINFUNCGRP(mis7, 3, 0, 0),
DEFPINFUNCGRP(mip7, 3, 1, 0),
DEFPINFUNCGRP(gpioj, 4, 0, 1),
DEFPINFUNCGRP(gpiok, 4, 0, 1),
DEFPINFUNCGRP(ciplus, 4, 1, 0),
DEFPINFUNCGRP(mcard, 4, 2, 0),
DEFPINFUNCGRP(stc0, 4, 3, 0),
DEFPINFUNCGRP(stc1, 4, 3, 0),
DEFPINFUNCGRP(mop, 5, 0, 0),
DEFPINFUNCGRP(mos0, 5, 1, 0),
DEFPINFUNCGRP(mos1, 5, 1, 0),
DEFPINFUNCGRP(mos2, 5, 1, 0),
DEFPINFUNCGRP(mos3, 5, 1, 0),
DEFPINFUNCGRP(uart0, 6, 0, 0),
DEFPINFUNCGRP(uart1, 6, 0, 0),
DEFPINFUNCGRP(gpiol, 6, 1, 1),
DEFPINFUNCGRP(gpiom, 6, 1, 1),
DEFPINFUNCGRP(spi3, 7, 0, 0),
DEFPINFUNCGRP(jtag, 7, 1, 0),
DEFPINFUNCGRP(spi1, 8, 0, 0),
DEFPINFUNCGRP(gpion, 8, 1, 1),
DEFPINFUNCGRP(gpiob, -1, 0, 1),
DEFPINFUNCGRP(gpiod, -1, 0, 1),
DEFPINFUNCGRP(gpiof, -1, 0, 1),
DEFPINFUNCGRP(gpioh, -1, 0, 1),
DEFPINFUNCGRP(gpioi, -1, 0, 1),
};
#undef DEFPINFUNCGRP
struct tb10x_of_pinfunc {
const char *name;
const char *group;
};
#define TB10X_PORTS (9)
/**
* struct tb10x_port - state of an I/O port
* @mode: Node this port is currently in.
* @count: Number of enabled functions which require this port to be
* configured in @mode.
*/
struct tb10x_port {
unsigned int mode;
unsigned int count;
};
/**
* struct tb10x_pinctrl - TB10x pin controller internal state
* @pctl: pointer to the pinctrl_dev structure of this pin controller.
* @base: register set base address.
* @pingroups: pointer to an array of the pin groups this driver manages.
* @pinfuncgrpcnt: number of pingroups in @pingroups.
* @pinfuncnt: number of pin functions in @pinfuncs.
* @mutex: mutex for exclusive access to a pin controller's state.
* @ports: current state of each port.
* @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
* @pinfuncs: flexible array of pin functions this driver manages.
*/
struct tb10x_pinctrl {
struct pinctrl_dev *pctl;
void *base;
const struct tb10x_pinfuncgrp *pingroups;
unsigned int pinfuncgrpcnt;
unsigned int pinfuncnt;
struct mutex mutex;
struct tb10x_port ports[TB10X_PORTS];
DECLARE_BITMAP(gpios, MAX_PIN + 1);
struct tb10x_of_pinfunc pinfuncs[];
};
static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
unsigned int port, unsigned int mode)
{
u32 pcfg;
if (state->ports[port].count)
return;
state->ports[port].mode = mode;
pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port));
pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port);
iowrite32(pcfg, state->base);
}
static inline unsigned int tb10x_pinctrl_get_config(
struct tb10x_pinctrl *state,
unsigned int port)
{
return (ioread32(state->base) & PCFG_PORT_MASK(port))
>> (PCFG_PORT_BITWIDTH * port);
}
static int tb10x_get_groups_count(struct pinctrl_dev *pctl)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
return state->pinfuncgrpcnt;
}
static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
return state->pingroups[n].name;
}
static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n,
unsigned const **pins,
unsigned * const num_pins)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
*pins = state->pingroups[n].pins;
*num_pins = state->pingroups[n].pincnt;
return 0;
}
static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
const char *string;
unsigned reserved_maps = 0;
int ret = 0;
if (of_property_read_string(np_config, "abilis,function", &string)) {
pr_err("%pOF: No abilis,function property in device tree.\n",
np_config);
return -EINVAL;
}
*map = NULL;
*num_maps = 0;
ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps,
num_maps, 1);
if (ret)
goto out;
ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps,
num_maps, string, np_config->name);
out:
return ret;
}
static const struct pinctrl_ops tb10x_pinctrl_ops = {
.get_groups_count = tb10x_get_groups_count,
.get_group_name = tb10x_get_group_name,
.get_group_pins = tb10x_get_group_pins,
.dt_node_to_map = tb10x_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int tb10x_get_functions_count(struct pinctrl_dev *pctl)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
return state->pinfuncnt;
}
static const char *tb10x_get_function_name(struct pinctrl_dev *pctl,
unsigned n)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
return state->pinfuncs[n].name;
}
static int tb10x_get_function_groups(struct pinctrl_dev *pctl,
unsigned n, const char * const **groups,
unsigned * const num_groups)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
*groups = &state->pinfuncs[n].group;
*num_groups = 1;
return 0;
}
static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
int muxport = -1;
int muxmode = -1;
int i;
mutex_lock(&state->mutex);
/*
* Figure out to which port the requested GPIO belongs and how to
* configure that port.
* This loop also checks for pin conflicts between GPIOs and other
* functions.
*/
for (i = 0; i < state->pinfuncgrpcnt; i++) {
const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
unsigned int mode = pfg->mode;
int j, port = pfg->port;
/*
* Skip pin groups which are always mapped and don't need
* to be configured.
*/
if (port < 0)
continue;
for (j = 0; j < pfg->pincnt; j++) {
if (pin == pfg->pins[j]) {
if (pfg->isgpio) {
/*
* Remember the GPIO-only setting of
* the port this pin belongs to.
*/
muxport = port;
muxmode = mode;
} else if (state->ports[port].count
&& (state->ports[port].mode == mode)) {
/*
* Error: The requested pin is already
* used for something else.
*/
mutex_unlock(&state->mutex);
return -EBUSY;
}
break;
}
}
}
/*
* If we haven't returned an error at this point, the GPIO pin is not
* used by another function and the GPIO request can be granted:
* Register pin as being used as GPIO so we don't allocate it to
* another function later.
*/
set_bit(pin, state->gpios);
/*
* Potential conflicts between GPIOs and pin functions were caught
* earlier in this function and tb10x_pinctrl_set_config will do the
* Right Thing, either configure the port in GPIO only mode or leave
* another mode compatible with this GPIO request untouched.
*/
if (muxport >= 0)
tb10x_pinctrl_set_config(state, muxport, muxmode);
mutex_unlock(&state->mutex);
return 0;
}
static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
struct pinctrl_gpio_range *range,
unsigned pin)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
mutex_lock(&state->mutex);
clear_bit(pin, state->gpios);
mutex_unlock(&state->mutex);
}
static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
unsigned func_selector, unsigned group_selector)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
int i;
if (grp->port < 0)
return 0;
mutex_lock(&state->mutex);
/*
* Check if the requested function is compatible with previously
* requested functions.
*/
if (state->ports[grp->port].count
&& (state->ports[grp->port].mode != grp->mode)) {
mutex_unlock(&state->mutex);
return -EBUSY;
}
/*
* Check if the requested function is compatible with previously
* requested GPIOs.
*/
for (i = 0; i < grp->pincnt; i++)
if (test_bit(grp->pins[i], state->gpios)) {
mutex_unlock(&state->mutex);
return -EBUSY;
}
tb10x_pinctrl_set_config(state, grp->port, grp->mode);
state->ports[grp->port].count++;
mutex_unlock(&state->mutex);
return 0;
}
static const struct pinmux_ops tb10x_pinmux_ops = {
.get_functions_count = tb10x_get_functions_count,
.get_function_name = tb10x_get_function_name,
.get_function_groups = tb10x_get_function_groups,
.gpio_request_enable = tb10x_gpio_request_enable,
.gpio_disable_free = tb10x_gpio_disable_free,
.set_mux = tb10x_pctl_set_mux,
};
static struct pinctrl_desc tb10x_pindesc = {
.name = "TB10x",
.pins = tb10x_pins,
.npins = ARRAY_SIZE(tb10x_pins),
.owner = THIS_MODULE,
.pctlops = &tb10x_pinctrl_ops,
.pmxops = &tb10x_pinmux_ops,
};
static int tb10x_pinctrl_probe(struct platform_device *pdev)
{
int ret = -EINVAL;
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
struct device_node *child;
struct tb10x_pinctrl *state;
int i;
if (!of_node) {
dev_err(dev, "No device tree node found.\n");
return -EINVAL;
}
state = devm_kzalloc(dev, struct_size(state, pinfuncs,
of_get_child_count(of_node)),
GFP_KERNEL);
if (!state)
return -ENOMEM;
platform_set_drvdata(pdev, state);
mutex_init(&state->mutex);
state->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(state->base)) {
ret = PTR_ERR(state->base);
goto fail;
}
state->pingroups = tb10x_pingroups;
state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups);
for (i = 0; i < TB10X_PORTS; i++)
state->ports[i].mode = tb10x_pinctrl_get_config(state, i);
for_each_child_of_node(of_node, child) {
const char *name;
if (!of_property_read_string(child, "abilis,function",
&name)) {
state->pinfuncs[state->pinfuncnt].name = child->name;
state->pinfuncs[state->pinfuncnt].group = name;
state->pinfuncnt++;
}
}
state->pctl = devm_pinctrl_register(dev, &tb10x_pindesc, state);
if (IS_ERR(state->pctl)) {
dev_err(dev, "could not register TB10x pin driver\n");
ret = PTR_ERR(state->pctl);
goto fail;
}
return 0;
fail:
mutex_destroy(&state->mutex);
return ret;
}
static int tb10x_pinctrl_remove(struct platform_device *pdev)
{
struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
mutex_destroy(&state->mutex);
return 0;
}
static const struct of_device_id tb10x_pinctrl_dt_ids[] = {
{ .compatible = "abilis,tb10x-iomux" },
{ }
};
MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
static struct platform_driver tb10x_pinctrl_pdrv = {
.probe = tb10x_pinctrl_probe,
.remove = tb10x_pinctrl_remove,
.driver = {
.name = "tb10x_pinctrl",
.of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
}
};
module_platform_driver(tb10x_pinctrl_pdrv);
MODULE_AUTHOR("Christian Ruppert <[email protected]>");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-tb10x.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/pinctrl/pinmux-xway.c
* based on linux/drivers/pinctrl/pinmux-pxa910.c
*
* Copyright (C) 2012 John Crispin <[email protected]>
* Copyright (C) 2015 Martin Schiller <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include "pinctrl-lantiq.h"
#include <lantiq_soc.h>
/* we have up to 4 banks of 16 bit each */
#define PINS 16
#define PORT3 3
#define PORT(x) (x / PINS)
#define PORT_PIN(x) (x % PINS)
/* we have 2 mux bits that can be set for each pin */
#define MUX_ALT0 0x1
#define MUX_ALT1 0x2
/*
* each bank has this offset apart from the 4th bank that is mixed into the
* other 3 ranges
*/
#define REG_OFF 0x30
/* these are the offsets to our registers */
#define GPIO_BASE(p) (REG_OFF * PORT(p))
#define GPIO_OUT(p) GPIO_BASE(p)
#define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
#define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
/* the 4th port needs special offsets for some registers */
#define GPIO3_OD (GPIO_BASE(0) + 0x24)
#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
/* macros to help us access the registers */
#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
#define MFP_XWAY(a, f0, f1, f2, f3) \
{ \
.name = #a, \
.pin = a, \
.func = { \
XWAY_MUX_##f0, \
XWAY_MUX_##f1, \
XWAY_MUX_##f2, \
XWAY_MUX_##f3, \
}, \
}
#define GRP_MUX(a, m, p) \
{ .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
#define FUNC_MUX(f, m) \
{ .func = f, .mux = XWAY_MUX_##m, }
enum xway_mux {
XWAY_MUX_GPIO = 0,
XWAY_MUX_SPI,
XWAY_MUX_ASC,
XWAY_MUX_USIF,
XWAY_MUX_PCI,
XWAY_MUX_CBUS,
XWAY_MUX_CGU,
XWAY_MUX_EBU,
XWAY_MUX_EBU2,
XWAY_MUX_JTAG,
XWAY_MUX_MCD,
XWAY_MUX_EXIN,
XWAY_MUX_TDM,
XWAY_MUX_STP,
XWAY_MUX_SIN,
XWAY_MUX_GPT,
XWAY_MUX_NMI,
XWAY_MUX_MDIO,
XWAY_MUX_MII,
XWAY_MUX_EPHY,
XWAY_MUX_DFE,
XWAY_MUX_SDIO,
XWAY_MUX_GPHY,
XWAY_MUX_SSI,
XWAY_MUX_WIFI,
XWAY_MUX_NONE = 0xffff,
};
/* --------- ase related code --------- */
#define ASE_MAX_PIN 32
static const struct ltq_mfp_pin ase_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2),
MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO),
MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO),
MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
};
static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
static const unsigned ase_pins_exin0[] = {GPIO6};
static const unsigned ase_pins_exin1[] = {GPIO29};
static const unsigned ase_pins_exin2[] = {GPIO0};
static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
static const unsigned ase_pins_ephy_led0[] = {GPIO2};
static const unsigned ase_pins_ephy_led1[] = {GPIO3};
static const unsigned ase_pins_ephy_led2[] = {GPIO4};
static const unsigned ase_pins_dfe_led0[] = {GPIO1};
static const unsigned ase_pins_dfe_led1[] = {GPIO2};
static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
static const unsigned ase_pins_spi_di[] = {GPIO8};
static const unsigned ase_pins_spi_do[] = {GPIO9};
static const unsigned ase_pins_spi_clk[] = {GPIO10};
static const unsigned ase_pins_spi_cs1[] = {GPIO7};
static const unsigned ase_pins_spi_cs2[] = {GPIO15};
static const unsigned ase_pins_spi_cs3[] = {GPIO14};
static const unsigned ase_pins_gpt1[] = {GPIO5};
static const unsigned ase_pins_gpt2[] = {GPIO4};
static const unsigned ase_pins_gpt3[] = {GPIO25};
static const unsigned ase_pins_clkout0[] = {GPIO23};
static const unsigned ase_pins_clkout1[] = {GPIO22};
static const unsigned ase_pins_clkout2[] = {GPIO14};
static const struct ltq_pin_group ase_grps[] = {
GRP_MUX("exin0", EXIN, ase_pins_exin0),
GRP_MUX("exin1", EXIN, ase_pins_exin1),
GRP_MUX("exin2", EXIN, ase_pins_exin2),
GRP_MUX("jtag", JTAG, ase_pins_jtag),
GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
GRP_MUX("spi_di", SPI, ase_pins_spi_di),
GRP_MUX("spi_do", SPI, ase_pins_spi_do),
GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
GRP_MUX("asc", ASC, ase_pins_asc),
GRP_MUX("stp", STP, ase_pins_stp),
GRP_MUX("gpt1", GPT, ase_pins_gpt1),
GRP_MUX("gpt2", GPT, ase_pins_gpt2),
GRP_MUX("gpt3", GPT, ase_pins_gpt3),
GRP_MUX("clkout0", CGU, ase_pins_clkout0),
GRP_MUX("clkout1", CGU, ase_pins_clkout1),
GRP_MUX("clkout2", CGU, ase_pins_clkout2),
GRP_MUX("mdio", MDIO, ase_pins_mdio),
GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
};
static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
"clkout2"};
static const char * const ase_mdio_grps[] = {"mdio"};
static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
"ephy led2"};
static const char * const ase_asc_grps[] = {"asc"};
static const char * const ase_jtag_grps[] = {"jtag"};
static const char * const ase_stp_grps[] = {"stp"};
static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
"spi_di", "spi_do",
"spi_clk", "spi_cs1",
"spi_cs2", "spi_cs3"};
static const struct ltq_pmx_func ase_funcs[] = {
{"spi", ARRAY_AND_SIZE(ase_spi_grps)},
{"asc", ARRAY_AND_SIZE(ase_asc_grps)},
{"cgu", ARRAY_AND_SIZE(ase_cgu_grps)},
{"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
{"exin", ARRAY_AND_SIZE(ase_exin_grps)},
{"stp", ARRAY_AND_SIZE(ase_stp_grps)},
{"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
{"mdio", ARRAY_AND_SIZE(ase_mdio_grps)},
{"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
{"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
};
/* --------- danube related code --------- */
#define DANUBE_MAX_PIN 32
static const struct ltq_mfp_pin danube_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, MII),
MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII),
MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
MFP_XWAY(GPIO5, GPIO, STP, MII, DFE),
MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
MFP_XWAY(GPIO7, GPIO, CGU, CBUS, MII),
MFP_XWAY(GPIO8, GPIO, CGU, NMI, MII),
MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
MFP_XWAY(GPIO14, GPIO, CGU, CBUS, MII),
MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
MFP_XWAY(GPIO19, GPIO, PCI, SDIO, MII),
MFP_XWAY(GPIO20, GPIO, JTAG, SDIO, MII),
MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
MFP_XWAY(GPIO29, GPIO, PCI, CBUS, MII),
MFP_XWAY(GPIO30, GPIO, PCI, CBUS, MII),
MFP_XWAY(GPIO31, GPIO, EBU, PCI, MII),
};
static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
static const unsigned danube_pins_exin0[] = {GPIO0};
static const unsigned danube_pins_exin1[] = {GPIO1};
static const unsigned danube_pins_exin2[] = {GPIO2};
static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
static const unsigned danube_pins_nmi[] = {GPIO8};
static const unsigned danube_pins_dfe_led0[] = {GPIO4};
static const unsigned danube_pins_dfe_led1[] = {GPIO5};
static const unsigned danube_pins_ebu_a24[] = {GPIO13};
static const unsigned danube_pins_ebu_clk[] = {GPIO21};
static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
static const unsigned danube_pins_ebu_a23[] = {GPIO24};
static const unsigned danube_pins_ebu_wait[] = {GPIO26};
static const unsigned danube_pins_ebu_a25[] = {GPIO31};
static const unsigned danube_pins_nand_ale[] = {GPIO13};
static const unsigned danube_pins_nand_cs1[] = {GPIO23};
static const unsigned danube_pins_nand_cle[] = {GPIO24};
static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
static const unsigned danube_pins_spi_di[] = {GPIO16};
static const unsigned danube_pins_spi_do[] = {GPIO17};
static const unsigned danube_pins_spi_clk[] = {GPIO18};
static const unsigned danube_pins_spi_cs1[] = {GPIO15};
static const unsigned danube_pins_spi_cs2[] = {GPIO21};
static const unsigned danube_pins_spi_cs3[] = {GPIO13};
static const unsigned danube_pins_spi_cs4[] = {GPIO10};
static const unsigned danube_pins_spi_cs5[] = {GPIO9};
static const unsigned danube_pins_spi_cs6[] = {GPIO11};
static const unsigned danube_pins_gpt1[] = {GPIO28};
static const unsigned danube_pins_gpt2[] = {GPIO21};
static const unsigned danube_pins_gpt3[] = {GPIO6};
static const unsigned danube_pins_clkout0[] = {GPIO8};
static const unsigned danube_pins_clkout1[] = {GPIO7};
static const unsigned danube_pins_clkout2[] = {GPIO3};
static const unsigned danube_pins_clkout3[] = {GPIO2};
static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
static const unsigned danube_pins_pci_req1[] = {GPIO29};
static const unsigned danube_pins_pci_req2[] = {GPIO31};
static const unsigned danube_pins_pci_req3[] = {GPIO3};
static const struct ltq_pin_group danube_grps[] = {
GRP_MUX("exin0", EXIN, danube_pins_exin0),
GRP_MUX("exin1", EXIN, danube_pins_exin1),
GRP_MUX("exin2", EXIN, danube_pins_exin2),
GRP_MUX("jtag", JTAG, danube_pins_jtag),
GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
GRP_MUX("spi_di", SPI, danube_pins_spi_di),
GRP_MUX("spi_do", SPI, danube_pins_spi_do),
GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
GRP_MUX("asc0", ASC, danube_pins_asc0),
GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
GRP_MUX("stp", STP, danube_pins_stp),
GRP_MUX("nmi", NMI, danube_pins_nmi),
GRP_MUX("gpt1", GPT, danube_pins_gpt1),
GRP_MUX("gpt2", GPT, danube_pins_gpt2),
GRP_MUX("gpt3", GPT, danube_pins_gpt3),
GRP_MUX("clkout0", CGU, danube_pins_clkout0),
GRP_MUX("clkout1", CGU, danube_pins_clkout1),
GRP_MUX("clkout2", CGU, danube_pins_clkout2),
GRP_MUX("clkout3", CGU, danube_pins_clkout3),
GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
GRP_MUX("req1", PCI, danube_pins_pci_req1),
GRP_MUX("req2", PCI, danube_pins_pci_req2),
GRP_MUX("req3", PCI, danube_pins_pci_req3),
GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
};
static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
"gnt3", "req1",
"req2", "req3"};
static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
"spi_di", "spi_do",
"spi_clk", "spi_cs1",
"spi_cs2", "spi_cs3",
"spi_cs4", "spi_cs5",
"spi_cs6"};
static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
"clkout2", "clkout3"};
static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
"ebu a25", "ebu cs1",
"ebu wait", "ebu clk",
"nand ale", "nand cs1",
"nand cle"};
static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
static const char * const danube_jtag_grps[] = {"jtag"};
static const char * const danube_stp_grps[] = {"stp"};
static const char * const danube_nmi_grps[] = {"nmi"};
static const struct ltq_pmx_func danube_funcs[] = {
{"spi", ARRAY_AND_SIZE(danube_spi_grps)},
{"asc", ARRAY_AND_SIZE(danube_asc_grps)},
{"cgu", ARRAY_AND_SIZE(danube_cgu_grps)},
{"jtag", ARRAY_AND_SIZE(danube_jtag_grps)},
{"exin", ARRAY_AND_SIZE(danube_exin_grps)},
{"stp", ARRAY_AND_SIZE(danube_stp_grps)},
{"gpt", ARRAY_AND_SIZE(danube_gpt_grps)},
{"nmi", ARRAY_AND_SIZE(danube_nmi_grps)},
{"pci", ARRAY_AND_SIZE(danube_pci_grps)},
{"ebu", ARRAY_AND_SIZE(danube_ebu_grps)},
{"dfe", ARRAY_AND_SIZE(danube_dfe_grps)},
};
/* --------- xrx100 related code --------- */
#define XRX100_MAX_PIN 56
static const struct ltq_mfp_pin xrx100_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
MFP_XWAY(GPIO5, GPIO, STP, NONE, DFE),
MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
MFP_XWAY(GPIO7, GPIO, CGU, CBUS, NONE),
MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
MFP_XWAY(GPIO14, GPIO, CGU, NONE, NONE),
MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
MFP_XWAY(GPIO28, GPIO, GPT, NONE, SDIO),
MFP_XWAY(GPIO29, GPIO, PCI, CBUS, NONE),
MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
MFP_XWAY(GPIO36, GPIO, SIN, SSI, NONE),
MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
MFP_XWAY(GPIO39, GPIO, NONE, EXIN, NONE),
MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO44, GPIO, MII, SIN, NONE),
MFP_XWAY(GPIO45, GPIO, MII, NONE, SIN),
MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
MFP_XWAY(GPIO47, GPIO, MII, NONE, SIN),
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
};
static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
static const unsigned xrx100_pins_exin0[] = {GPIO0};
static const unsigned xrx100_pins_exin1[] = {GPIO1};
static const unsigned xrx100_pins_exin2[] = {GPIO2};
static const unsigned xrx100_pins_exin3[] = {GPIO39};
static const unsigned xrx100_pins_exin4[] = {GPIO10};
static const unsigned xrx100_pins_exin5[] = {GPIO9};
static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
static const unsigned xrx100_pins_nmi[] = {GPIO8};
static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
static const unsigned xrx100_pins_spi_di[] = {GPIO16};
static const unsigned xrx100_pins_spi_do[] = {GPIO17};
static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
static const unsigned xrx100_pins_gpt1[] = {GPIO28};
static const unsigned xrx100_pins_gpt2[] = {GPIO21};
static const unsigned xrx100_pins_gpt3[] = {GPIO6};
static const unsigned xrx100_pins_clkout0[] = {GPIO8};
static const unsigned xrx100_pins_clkout1[] = {GPIO7};
static const unsigned xrx100_pins_clkout2[] = {GPIO3};
static const unsigned xrx100_pins_clkout3[] = {GPIO2};
static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
static const struct ltq_pin_group xrx100_grps[] = {
GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
GRP_MUX("asc0", ASC, xrx100_pins_asc0),
GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
GRP_MUX("stp", STP, xrx100_pins_stp),
GRP_MUX("nmi", NMI, xrx100_pins_nmi),
GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
};
static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
"gnt3", "gnt4",
"req1", "req2",
"req3", "req4"};
static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
"spi_clk", "spi_cs1",
"spi_cs2", "spi_cs3",
"spi_cs4", "spi_cs5",
"spi_cs6"};
static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
"clkout2", "clkout3"};
static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
"ebu a25", "ebu cs1",
"ebu wait", "ebu clk",
"nand ale", "nand cs1",
"nand cle", "nand rdy",
"nand rd"};
static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
"exin3", "exin4", "exin5"};
static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
static const char * const xrx100_stp_grps[] = {"stp"};
static const char * const xrx100_nmi_grps[] = {"nmi"};
static const char * const xrx100_mdio_grps[] = {"mdio"};
static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
static const struct ltq_pmx_func xrx100_funcs[] = {
{"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
{"asc", ARRAY_AND_SIZE(xrx100_asc_grps)},
{"cgu", ARRAY_AND_SIZE(xrx100_cgu_grps)},
{"exin", ARRAY_AND_SIZE(xrx100_exin_grps)},
{"stp", ARRAY_AND_SIZE(xrx100_stp_grps)},
{"gpt", ARRAY_AND_SIZE(xrx100_gpt_grps)},
{"nmi", ARRAY_AND_SIZE(xrx100_nmi_grps)},
{"pci", ARRAY_AND_SIZE(xrx100_pci_grps)},
{"ebu", ARRAY_AND_SIZE(xrx100_ebu_grps)},
{"mdio", ARRAY_AND_SIZE(xrx100_mdio_grps)},
{"dfe", ARRAY_AND_SIZE(xrx100_dfe_grps)},
};
/* --------- xrx200 related code --------- */
#define XRX200_MAX_PIN 50
static const struct ltq_mfp_pin xrx200_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
MFP_XWAY(GPIO4, GPIO, STP, DFE, USIF),
MFP_XWAY(GPIO5, GPIO, STP, GPHY, DFE),
MFP_XWAY(GPIO6, GPIO, STP, GPT, USIF),
MFP_XWAY(GPIO7, GPIO, CGU, CBUS, GPHY),
MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
MFP_XWAY(GPIO12, GPIO, USIF, CBUS, MCD),
MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
MFP_XWAY(GPIO14, GPIO, CGU, CBUS, USIF),
MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
MFP_XWAY(GPIO25, GPIO, TDM, SDIO, USIF),
MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
MFP_XWAY(GPIO27, GPIO, TDM, SDIO, USIF),
MFP_XWAY(GPIO28, GPIO, GPT, PCI, SDIO),
MFP_XWAY(GPIO29, GPIO, PCI, CBUS, EXIN),
MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
MFP_XWAY(GPIO36, GPIO, SIN, SSI, EXIN),
MFP_XWAY(GPIO37, GPIO, USIF, NONE, PCI),
MFP_XWAY(GPIO38, GPIO, PCI, USIF, NONE),
MFP_XWAY(GPIO39, GPIO, USIF, EXIN, NONE),
MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
MFP_XWAY(GPIO45, GPIO, MII, GPHY, SIN),
MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
};
static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
static const unsigned xrx200_pins_exin0[] = {GPIO0};
static const unsigned xrx200_pins_exin1[] = {GPIO1};
static const unsigned xrx200_pins_exin2[] = {GPIO2};
static const unsigned xrx200_pins_exin3[] = {GPIO39};
static const unsigned xrx200_pins_exin4[] = {GPIO10};
static const unsigned xrx200_pins_exin5[] = {GPIO9};
static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
static const unsigned xrx200_pins_nmi[] = {GPIO8};
static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
static const unsigned xrx200_pins_spi_di[] = {GPIO16};
static const unsigned xrx200_pins_spi_do[] = {GPIO17};
static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
static const unsigned xrx200_pins_gpt1[] = {GPIO28};
static const unsigned xrx200_pins_gpt2[] = {GPIO21};
static const unsigned xrx200_pins_gpt3[] = {GPIO6};
static const unsigned xrx200_pins_clkout0[] = {GPIO8};
static const unsigned xrx200_pins_clkout1[] = {GPIO7};
static const unsigned xrx200_pins_clkout2[] = {GPIO3};
static const unsigned xrx200_pins_clkout3[] = {GPIO2};
static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
static const struct ltq_pin_group xrx200_grps[] = {
GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
GRP_MUX("stp", STP, xrx200_pins_stp),
GRP_MUX("nmi", NMI, xrx200_pins_nmi),
GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
};
static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
"gnt3", "gnt4",
"req1", "req2",
"req3", "req4"};
static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
"spi_clk", "spi_cs1",
"spi_cs2", "spi_cs3",
"spi_cs4", "spi_cs5",
"spi_cs6"};
static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
"clkout2", "clkout3"};
static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
"ebu a25", "ebu cs1",
"ebu wait", "ebu clk",
"nand ale", "nand cs1",
"nand cle", "nand rdy",
"nand rd"};
static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
"exin3", "exin4", "exin5"};
static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
"usif uart_rts", "usif uart_cts",
"usif uart_dtr", "usif uart_dsr",
"usif uart_dcd", "usif uart_ri",
"usif spi_di", "usif spi_do",
"usif spi_clk", "usif spi_cs0",
"usif spi_cs1", "usif spi_cs2"};
static const char * const xrx200_stp_grps[] = {"stp"};
static const char * const xrx200_nmi_grps[] = {"nmi"};
static const char * const xrx200_mdio_grps[] = {"mdio"};
static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
"gphy0 led2", "gphy1 led0",
"gphy1 led1", "gphy1 led2"};
static const struct ltq_pmx_func xrx200_funcs[] = {
{"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
{"usif", ARRAY_AND_SIZE(xrx200_usif_grps)},
{"cgu", ARRAY_AND_SIZE(xrx200_cgu_grps)},
{"exin", ARRAY_AND_SIZE(xrx200_exin_grps)},
{"stp", ARRAY_AND_SIZE(xrx200_stp_grps)},
{"gpt", ARRAY_AND_SIZE(xrx200_gpt_grps)},
{"nmi", ARRAY_AND_SIZE(xrx200_nmi_grps)},
{"pci", ARRAY_AND_SIZE(xrx200_pci_grps)},
{"ebu", ARRAY_AND_SIZE(xrx200_ebu_grps)},
{"mdio", ARRAY_AND_SIZE(xrx200_mdio_grps)},
{"dfe", ARRAY_AND_SIZE(xrx200_dfe_grps)},
{"gphy", ARRAY_AND_SIZE(xrx200_gphy_grps)},
};
/* --------- xrx300 related code --------- */
#define XRX300_MAX_PIN 64
static const struct ltq_mfp_pin xrx300_mfp[] = {
/* pin f0 f1 f2 f3 */
MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE),
MFP_XWAY(GPIO1, GPIO, NONE, EXIN, NONE),
MFP_XWAY(GPIO2, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO3, GPIO, CGU, NONE, NONE),
MFP_XWAY(GPIO4, GPIO, STP, DFE, NONE),
MFP_XWAY(GPIO5, GPIO, STP, EPHY, DFE),
MFP_XWAY(GPIO6, GPIO, STP, NONE, NONE),
MFP_XWAY(GPIO7, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO8, GPIO, CGU, GPHY, EPHY),
MFP_XWAY(GPIO9, GPIO, WIFI, NONE, EXIN),
MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
MFP_XWAY(GPIO12, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO13, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO14, GPIO, CGU, USIF, EPHY),
MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
MFP_XWAY(GPIO19, GPIO, USIF, NONE, EPHY),
MFP_XWAY(GPIO20, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO21, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO22, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO23, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO24, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO25, GPIO, TDM, NONE, NONE),
MFP_XWAY(GPIO26, GPIO, TDM, NONE, NONE),
MFP_XWAY(GPIO27, GPIO, TDM, NONE, NONE),
MFP_XWAY(GPIO28, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO29, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO30, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO31, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO32, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO33, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO34, GPIO, NONE, SSI, NONE),
MFP_XWAY(GPIO35, GPIO, NONE, SSI, NONE),
MFP_XWAY(GPIO36, GPIO, NONE, SSI, NONE),
MFP_XWAY(GPIO37, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO38, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO39, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO40, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO41, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
MFP_XWAY(GPIO44, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO45, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO46, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO47, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO50, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO51, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO52, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO53, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO54, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO55, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO56, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO57, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO58, GPIO, EBU, TDM, NONE),
MFP_XWAY(GPIO59, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO60, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO61, GPIO, EBU, NONE, NONE),
MFP_XWAY(GPIO62, NONE, NONE, NONE, NONE),
MFP_XWAY(GPIO63, NONE, NONE, NONE, NONE),
};
static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
static const unsigned xrx300_pins_exin0[] = {GPIO0};
static const unsigned xrx300_pins_exin1[] = {GPIO1};
static const unsigned xrx300_pins_exin2[] = {GPIO16};
/* EXIN3 is not available on xrX300 */
static const unsigned xrx300_pins_exin4[] = {GPIO10};
static const unsigned xrx300_pins_exin5[] = {GPIO9};
static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
static const unsigned xrx300_pins_nand_se[] = {GPIO61};
static const unsigned xrx300_pins_spi_di[] = {GPIO16};
static const unsigned xrx300_pins_spi_do[] = {GPIO17};
static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
/* SPI_CS2 is not available on xrX300 */
/* SPI_CS3 is not available on xrX300 */
static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
/* SPI_CS5 is not available on xrX300 */
static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
/* CLKOUT0 is not available on xrX300 */
/* CLKOUT1 is not available on xrX300 */
static const unsigned xrx300_pins_clkout2[] = {GPIO3};
static const struct ltq_pin_group xrx300_grps[] = {
GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
GRP_MUX("stp", STP, xrx300_pins_stp),
GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
};
static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
"spi_clk", "spi_cs1",
"spi_cs4", "spi_cs6"};
static const char * const xrx300_cgu_grps[] = {"clkout2"};
static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
"nand cle", "nand rdy",
"nand rd", "nand d1",
"nand d0", "nand d2",
"nand d7", "nand d6",
"nand d5", "nand d4",
"nand d3", "nand cs0",
"nand wr", "nand wp",
"nand se"};
static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
"exin4", "exin5"};
static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
"usif spi_di", "usif spi_do",
"usif spi_clk", "usif spi_cs0"};
static const char * const xrx300_stp_grps[] = {"stp"};
static const char * const xrx300_mdio_grps[] = {"mdio"};
static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
"ephy1 led0", "ephy1 led1"};
static const struct ltq_pmx_func xrx300_funcs[] = {
{"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
{"usif", ARRAY_AND_SIZE(xrx300_usif_grps)},
{"cgu", ARRAY_AND_SIZE(xrx300_cgu_grps)},
{"exin", ARRAY_AND_SIZE(xrx300_exin_grps)},
{"stp", ARRAY_AND_SIZE(xrx300_stp_grps)},
{"ebu", ARRAY_AND_SIZE(xrx300_ebu_grps)},
{"mdio", ARRAY_AND_SIZE(xrx300_mdio_grps)},
{"dfe", ARRAY_AND_SIZE(xrx300_dfe_grps)},
{"ephy", ARRAY_AND_SIZE(xrx300_gphy_grps)},
};
/* --------- pinconf related code --------- */
static int xway_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *config)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
int port = PORT(pin);
u32 reg;
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
*config = LTQ_PINCONF_PACK(param,
!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
break;
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
*config = LTQ_PINCONF_PACK(param, 0);
break;
}
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
*config = LTQ_PINCONF_PACK(param, 2);
else
*config = LTQ_PINCONF_PACK(param, 1);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
*config = LTQ_PINCONF_PACK(param,
gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
break;
default:
dev_err(pctldev->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
return 0;
}
static int xway_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
enum ltq_pinconf_param param;
int arg;
int port = PORT(pin);
u32 reg;
int i;
for (i = 0; i < num_configs; i++) {
param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
switch (param) {
case LTQ_PINCONF_PARAM_OPEN_DRAIN:
if (port == PORT3)
reg = GPIO3_OD;
else
reg = GPIO_OD(pin);
if (arg == 0)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
case LTQ_PINCONF_PARAM_PULL:
if (port == PORT3)
reg = GPIO3_PUDEN;
else
reg = GPIO_PUDEN(pin);
if (arg == 0) {
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
}
gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
if (port == PORT3)
reg = GPIO3_PUDSEL;
else
reg = GPIO_PUDSEL(pin);
if (arg == 1)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else if (arg == 2)
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
else
dev_err(pctldev->dev,
"Invalid pull value %d\n", arg);
break;
case LTQ_PINCONF_PARAM_OUTPUT:
reg = GPIO_DIR(pin);
if (arg == 0)
gpio_clearbit(info->membase[0],
reg,
PORT_PIN(pin));
else
gpio_setbit(info->membase[0],
reg,
PORT_PIN(pin));
break;
default:
dev_err(pctldev->dev,
"Invalid config param %04x\n", param);
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned long *configs,
unsigned num_configs)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
int i, ret = 0;
for (i = 0; i < info->grps[selector].npins && !ret; i++)
ret = xway_pinconf_set(pctldev,
info->grps[selector].pins[i],
configs,
num_configs);
return ret;
}
static const struct pinconf_ops xway_pinconf_ops = {
.pin_config_get = xway_pinconf_get,
.pin_config_set = xway_pinconf_set,
.pin_config_group_set = xway_pinconf_group_set,
};
static struct pinctrl_desc xway_pctrl_desc = {
.owner = THIS_MODULE,
.confops = &xway_pinconf_ops,
};
static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
int pin, int mux)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int port = PORT(pin);
u32 alt1_reg = GPIO_ALT1(pin);
if (port == PORT3)
alt1_reg = GPIO3_ALT1;
if (mux & MUX_ALT0)
gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
else
gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
if (mux & MUX_ALT1)
gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
else
gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
return 0;
}
static const struct ltq_cfg_param xway_cfg_params[] = {
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
{"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
{"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT},
};
static struct ltq_pinmux_info xway_info = {
.desc = &xway_pctrl_desc,
.apply_mux = xway_mux_apply,
.params = xway_cfg_params,
.num_params = ARRAY_SIZE(xway_cfg_params),
};
/* --------- gpio_chip related code --------- */
static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
if (val)
gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
else
gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
}
static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
}
static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
return 0;
}
static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
if (PORT(pin) == PORT3)
gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
else
gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
xway_gpio_set(chip, pin, val);
return 0;
}
/*
* gpiolib gpiod_to_irq callback function.
* Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
*/
static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
int i;
for (i = 0; i < info->num_exin; i++)
if (info->exin[i] == offset)
return ltq_eiu_get_irq(i);
return -1;
}
static struct gpio_chip xway_chip = {
.label = "gpio-xway",
.direction_input = xway_gpio_dir_in,
.direction_output = xway_gpio_dir_out,
.get = xway_gpio_get,
.set = xway_gpio_set,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.to_irq = xway_gpio_to_irq,
.base = -1,
};
/* --------- register the pinctrl layer --------- */
struct pinctrl_xway_soc {
int pin_count;
const struct ltq_mfp_pin *mfp;
const struct ltq_pin_group *grps;
unsigned int num_grps;
const struct ltq_pmx_func *funcs;
unsigned int num_funcs;
const unsigned *exin;
unsigned int num_exin;
};
/* XWAY AMAZON Family */
static struct pinctrl_xway_soc ase_pinctrl = {
.pin_count = ASE_MAX_PIN,
.mfp = ase_mfp,
.grps = ase_grps,
.num_grps = ARRAY_SIZE(ase_grps),
.funcs = ase_funcs,
.num_funcs = ARRAY_SIZE(ase_funcs),
.exin = ase_exin_pin_map,
.num_exin = 3
};
/* XWAY DANUBE Family */
static struct pinctrl_xway_soc danube_pinctrl = {
.pin_count = DANUBE_MAX_PIN,
.mfp = danube_mfp,
.grps = danube_grps,
.num_grps = ARRAY_SIZE(danube_grps),
.funcs = danube_funcs,
.num_funcs = ARRAY_SIZE(danube_funcs),
.exin = danube_exin_pin_map,
.num_exin = 3
};
/* XWAY xRX100 Family */
static struct pinctrl_xway_soc xrx100_pinctrl = {
.pin_count = XRX100_MAX_PIN,
.mfp = xrx100_mfp,
.grps = xrx100_grps,
.num_grps = ARRAY_SIZE(xrx100_grps),
.funcs = xrx100_funcs,
.num_funcs = ARRAY_SIZE(xrx100_funcs),
.exin = xrx100_exin_pin_map,
.num_exin = 6
};
/* XWAY xRX200 Family */
static struct pinctrl_xway_soc xrx200_pinctrl = {
.pin_count = XRX200_MAX_PIN,
.mfp = xrx200_mfp,
.grps = xrx200_grps,
.num_grps = ARRAY_SIZE(xrx200_grps),
.funcs = xrx200_funcs,
.num_funcs = ARRAY_SIZE(xrx200_funcs),
.exin = xrx200_exin_pin_map,
.num_exin = 6
};
/* XWAY xRX300 Family */
static struct pinctrl_xway_soc xrx300_pinctrl = {
.pin_count = XRX300_MAX_PIN,
.mfp = xrx300_mfp,
.grps = xrx300_grps,
.num_grps = ARRAY_SIZE(xrx300_grps),
.funcs = xrx300_funcs,
.num_funcs = ARRAY_SIZE(xrx300_funcs),
.exin = xrx300_exin_pin_map,
.num_exin = 5
};
static struct pinctrl_gpio_range xway_gpio_range = {
.name = "XWAY GPIO",
.gc = &xway_chip,
};
static const struct of_device_id xway_match[] = {
{ .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
{ .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
{ .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
{ .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
{ .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
{},
};
MODULE_DEVICE_TABLE(of, xway_match);
static int pinmux_xway_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
const struct pinctrl_xway_soc *xway_soc;
int ret, i;
/* get and remap our register range */
xway_info.membase[0] = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xway_info.membase[0]))
return PTR_ERR(xway_info.membase[0]);
match = of_match_device(xway_match, &pdev->dev);
if (match)
xway_soc = (const struct pinctrl_xway_soc *) match->data;
else
xway_soc = &danube_pinctrl;
/* find out how many pads we have */
xway_chip.ngpio = xway_soc->pin_count;
/* load our pad descriptors */
xway_info.pads = devm_kcalloc(&pdev->dev,
xway_chip.ngpio, sizeof(struct pinctrl_pin_desc),
GFP_KERNEL);
if (!xway_info.pads)
return -ENOMEM;
for (i = 0; i < xway_chip.ngpio; i++) {
char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i);
if (!name)
return -ENOMEM;
xway_info.pads[i].number = GPIO0 + i;
xway_info.pads[i].name = name;
}
xway_pctrl_desc.pins = xway_info.pads;
/* setup the data needed by pinctrl */
xway_pctrl_desc.name = dev_name(&pdev->dev);
xway_pctrl_desc.npins = xway_chip.ngpio;
xway_info.num_pads = xway_chip.ngpio;
xway_info.num_mfp = xway_chip.ngpio;
xway_info.mfp = xway_soc->mfp;
xway_info.grps = xway_soc->grps;
xway_info.num_grps = xway_soc->num_grps;
xway_info.funcs = xway_soc->funcs;
xway_info.num_funcs = xway_soc->num_funcs;
xway_info.exin = xway_soc->exin;
xway_info.num_exin = xway_soc->num_exin;
/* register with the generic lantiq layer */
ret = ltq_pinctrl_register(pdev, &xway_info);
if (ret) {
dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
return ret;
}
/* register the gpio chip */
xway_chip.parent = &pdev->dev;
xway_chip.owner = THIS_MODULE;
ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to register gpio chip\n");
return ret;
}
/*
* For DeviceTree-supported systems, the gpio core checks the
* pinctrl's device node for the "gpio-ranges" property.
* If it is present, it takes care of adding the pin ranges
* for the driver. In this case the driver can skip ahead.
*
* In order to remain compatible with older, existing DeviceTree
* files which don't set the "gpio-ranges" property or systems that
* utilize ACPI the driver has to call gpiochip_add_pin_range().
*/
if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) {
/* finish with registering the gpio range in pinctrl */
xway_gpio_range.npins = xway_chip.ngpio;
xway_gpio_range.base = xway_chip.base;
pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
}
dev_info(&pdev->dev, "Init done\n");
return 0;
}
static struct platform_driver pinmux_xway_driver = {
.probe = pinmux_xway_probe,
.driver = {
.name = "pinctrl-xway",
.of_match_table = xway_match,
},
};
static int __init pinmux_xway_init(void)
{
return platform_driver_register(&pinmux_xway_driver);
}
core_initcall_sync(pinmux_xway_init);
|
linux-master
|
drivers/pinctrl/pinctrl-xway.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* ZynqMP pin controller
*
* Copyright (C) 2020, 2021 Xilinx, Inc.
*
* Sai Krishna Potthuri <[email protected]>
* Rajan Vaja <[email protected]>
*/
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinctrl-utils.h"
#define ZYNQMP_PIN_PREFIX "MIO"
#define PINCTRL_GET_FUNC_NAME_RESP_LEN 16
#define MAX_FUNC_NAME_LEN 16
#define MAX_GROUP_PIN 50
#define MAX_PIN_GROUPS 50
#define END_OF_FUNCTIONS "END_OF_FUNCTIONS"
#define NUM_GROUPS_PER_RESP 6
#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12
#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12
#define NA_GROUP 0xFFFF
#define RESERVED_GROUP 0xFFFE
#define DRIVE_STRENGTH_2MA 2
#define DRIVE_STRENGTH_4MA 4
#define DRIVE_STRENGTH_8MA 8
#define DRIVE_STRENGTH_12MA 12
/**
* struct zynqmp_pmux_function - a pinmux function
* @name: Name of the pin mux function
* @groups: List of pin groups for this function
* @ngroups: Number of entries in @groups
* @node: Firmware node matching with the function
*
* This structure holds information about pin control function
* and function group names supporting that function.
*/
struct zynqmp_pmux_function {
char name[MAX_FUNC_NAME_LEN];
const char * const *groups;
unsigned int ngroups;
};
/**
* struct zynqmp_pinctrl - driver data
* @pctrl: Pin control device
* @groups: Pin groups
* @ngroups: Number of @groups
* @funcs: Pin mux functions
* @nfuncs: Number of @funcs
*
* This struct is stored as driver data and used to retrieve
* information regarding pin control functions, groups and
* group pins.
*/
struct zynqmp_pinctrl {
struct pinctrl_dev *pctrl;
const struct zynqmp_pctrl_group *groups;
unsigned int ngroups;
const struct zynqmp_pmux_function *funcs;
unsigned int nfuncs;
};
/**
* struct zynqmp_pctrl_group - Pin control group info
* @name: Group name
* @pins: Group pin numbers
* @npins: Number of pins in the group
*/
struct zynqmp_pctrl_group {
const char *name;
unsigned int pins[MAX_GROUP_PIN];
unsigned int npins;
};
static struct pinctrl_desc zynqmp_desc;
static int zynqmp_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->ngroups;
}
static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->groups[selector].name;
}
static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->groups[selector].pins;
*npins = pctrl->groups[selector].npins;
return 0;
}
static const struct pinctrl_ops zynqmp_pctrl_ops = {
.get_groups_count = zynqmp_pctrl_get_groups_count,
.get_group_name = zynqmp_pctrl_get_group_name,
.get_group_pins = zynqmp_pctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static int zynqmp_pinmux_request_pin(struct pinctrl_dev *pctldev,
unsigned int pin)
{
int ret;
ret = zynqmp_pm_pinctrl_request(pin);
if (ret) {
dev_err(pctldev->dev, "request failed for pin %u\n", pin);
return ret;
}
return 0;
}
static int zynqmp_pmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->nfuncs;
}
static const char *zynqmp_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->funcs[selector].name;
}
/**
* zynqmp_pmux_get_function_groups() - Get groups for the function
* @pctldev: Pincontrol device pointer.
* @selector: Function ID
* @groups: Group names.
* @num_groups: Number of function groups.
*
* Get function's group count and group names.
*
* Return: 0
*/
static int zynqmp_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->funcs[selector].groups;
*num_groups = pctrl->funcs[selector].ngroups;
return 0;
}
/**
* zynqmp_pinmux_set_mux() - Set requested function for the group
* @pctldev: Pincontrol device pointer.
* @function: Function ID.
* @group: Group ID.
*
* Loop through all pins of the group and call firmware API
* to set requested function for all pins in the group.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[group];
int ret, i;
for (i = 0; i < pgrp->npins; i++) {
unsigned int pin = pgrp->pins[i];
ret = zynqmp_pm_pinctrl_set_function(pin, function);
if (ret) {
dev_err(pctldev->dev, "set mux failed for pin %u\n",
pin);
return ret;
}
}
return 0;
}
static int zynqmp_pinmux_release_pin(struct pinctrl_dev *pctldev,
unsigned int pin)
{
int ret;
ret = zynqmp_pm_pinctrl_release(pin);
if (ret) {
dev_err(pctldev->dev, "free pin failed for pin %u\n",
pin);
return ret;
}
return 0;
}
static const struct pinmux_ops zynqmp_pinmux_ops = {
.request = zynqmp_pinmux_request_pin,
.get_functions_count = zynqmp_pmux_get_functions_count,
.get_function_name = zynqmp_pmux_get_function_name,
.get_function_groups = zynqmp_pmux_get_function_groups,
.set_mux = zynqmp_pinmux_set_mux,
.free = zynqmp_pinmux_release_pin,
};
/**
* zynqmp_pinconf_cfg_get() - get config value for the pin
* @pctldev: Pin control device pointer.
* @pin: Pin number.
* @config: Value of config param.
*
* Get value of the requested configuration parameter for the
* given pin.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_cfg_get(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *config)
{
unsigned int arg, param = pinconf_to_config_param(*config);
int ret;
switch (param) {
case PIN_CONFIG_SLEW_RATE:
param = PM_PINCTRL_CONFIG_SLEW_RATE;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_PULL_UP)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_PULL_DOWN)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
param = PM_PINCTRL_CONFIG_BIAS_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_DISABLE)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_POWER_SOURCE:
param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
switch (arg) {
case PM_PINCTRL_DRIVE_STRENGTH_2MA:
arg = DRIVE_STRENGTH_2MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_4MA:
arg = DRIVE_STRENGTH_4MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_8MA:
arg = DRIVE_STRENGTH_8MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_12MA:
arg = DRIVE_STRENGTH_12MA;
break;
default:
/* Invalid drive strength */
dev_warn(pctldev->dev,
"Invalid drive strength for pin %d\n",
pin);
return -EINVAL;
}
break;
default:
ret = -ENOTSUPP;
break;
}
if (ret)
return ret;
param = pinconf_to_config_param(*config);
*config = pinconf_to_config_packed(param, arg);
return 0;
}
/**
* zynqmp_pinconf_cfg_set() - Set requested config for the pin
* @pctldev: Pincontrol device pointer.
* @pin: Pin number.
* @configs: Configuration to set.
* @num_configs: Number of configurations.
*
* Loop through all configurations and call firmware API
* to set requested configurations for the pin.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
unsigned int value;
switch (param) {
case PIN_CONFIG_SLEW_RATE:
param = PM_PINCTRL_CONFIG_SLEW_RATE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
arg = PM_PINCTRL_BIAS_PULL_UP;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
arg = PM_PINCTRL_BIAS_PULL_DOWN;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_DISABLE:
param = PM_PINCTRL_CONFIG_BIAS_STATUS;
arg = PM_PINCTRL_BIAS_DISABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case DRIVE_STRENGTH_2MA:
value = PM_PINCTRL_DRIVE_STRENGTH_2MA;
break;
case DRIVE_STRENGTH_4MA:
value = PM_PINCTRL_DRIVE_STRENGTH_4MA;
break;
case DRIVE_STRENGTH_8MA:
value = PM_PINCTRL_DRIVE_STRENGTH_8MA;
break;
case DRIVE_STRENGTH_12MA:
value = PM_PINCTRL_DRIVE_STRENGTH_12MA;
break;
default:
/* Invalid drive strength */
dev_warn(pctldev->dev,
"Invalid drive strength for pin %d\n",
pin);
return -EINVAL;
}
param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
ret = zynqmp_pm_pinctrl_set_config(pin, param, value);
break;
case PIN_CONFIG_POWER_SOURCE:
param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
if (arg != value)
dev_warn(pctldev->dev,
"Invalid IO Standard requested for pin %d\n",
pin);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_ENABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_MODE_LOW_POWER:
/*
* These cases are mentioned in dts but configurable
* registers are unknown. So falling through to ignore
* boot time warnings as of now.
*/
ret = 0;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
param = PM_PINCTRL_CONFIG_TRI_STATE;
arg = PM_PINCTRL_TRI_STATE_DISABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter '%u'\n",
param);
ret = -ENOTSUPP;
break;
}
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
if (ret)
dev_warn(pctldev->dev,
"failed to set: pin %u param %u value %u\n",
pin, param, arg);
}
return 0;
}
/**
* zynqmp_pinconf_group_set() - Set requested config for the group
* @pctldev: Pincontrol device pointer.
* @selector: Group ID.
* @configs: Configuration to set.
* @num_configs: Number of configurations.
*
* Call function to set configs for each pin in the group.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[selector];
for (i = 0; i < pgrp->npins; i++) {
ret = zynqmp_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops zynqmp_pinconf_ops = {
.is_generic = true,
.pin_config_get = zynqmp_pinconf_cfg_get,
.pin_config_set = zynqmp_pinconf_cfg_set,
.pin_config_group_set = zynqmp_pinconf_group_set,
};
static struct pinctrl_desc zynqmp_desc = {
.name = "zynqmp_pinctrl",
.owner = THIS_MODULE,
.pctlops = &zynqmp_pctrl_ops,
.pmxops = &zynqmp_pinmux_ops,
.confops = &zynqmp_pinconf_ops,
};
static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_GROUPS;
qdata.arg1 = fid;
qdata.arg2 = index;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
memcpy(groups, &payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN);
return 0;
}
static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS;
qdata.arg1 = fid;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*ngroups = payload[1];
return 0;
}
/**
* zynqmp_pinctrl_prepare_func_groups() - prepare function and groups data
* @dev: Device pointer.
* @fid: Function ID.
* @func: Function data.
* @groups: Groups data.
*
* Query firmware to get group IDs for each function. Firmware returns
* group IDs. Based on the group index for the function, group names in
* the function are stored. For example, the first group in "eth0" function
* is named as "eth0_0" and the second group as "eth0_1" and so on.
*
* Based on the group ID received from the firmware, function stores name of
* the group for that group ID. For example, if "eth0" first group ID
* is x, groups[x] name will be stored as "eth0_0".
*
* Once done for each function, each function would have its group names
* and each group would also have their names.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid,
struct zynqmp_pmux_function *func,
struct zynqmp_pctrl_group *groups)
{
u16 resp[NUM_GROUPS_PER_RESP] = {0};
const char **fgroups;
int ret, index, i;
fgroups = devm_kzalloc(dev, sizeof(*fgroups) * func->ngroups, GFP_KERNEL);
if (!fgroups)
return -ENOMEM;
for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) {
ret = zynqmp_pinctrl_get_function_groups(fid, index, resp);
if (ret)
return ret;
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
if (resp[i] == NA_GROUP)
goto done;
if (resp[i] == RESERVED_GROUP)
continue;
fgroups[index + i] = devm_kasprintf(dev, GFP_KERNEL,
"%s_%d_grp",
func->name,
index + i);
if (!fgroups[index + i])
return -ENOMEM;
groups[resp[i]].name = devm_kasprintf(dev, GFP_KERNEL,
"%s_%d_grp",
func->name,
index + i);
if (!groups[resp[i]].name)
return -ENOMEM;
}
}
done:
func->groups = fgroups;
return 0;
}
static void zynqmp_pinctrl_get_function_name(u32 fid, char *name)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_NAME;
qdata.arg1 = fid;
/*
* Name of the function is maximum 16 bytes and cannot
* accommodate the return value in SMC buffers, hence ignoring
* the return value for this specific qid.
*/
zynqmp_pm_query_data(qdata, payload);
memcpy(name, payload, PINCTRL_GET_FUNC_NAME_RESP_LEN);
}
static int zynqmp_pinctrl_get_num_functions(unsigned int *nfuncs)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTIONS;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*nfuncs = payload[1];
return 0;
}
static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_PIN_GROUPS;
qdata.arg1 = pin;
qdata.arg2 = index;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
memcpy(groups, &payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN);
return 0;
}
static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group,
unsigned int pin)
{
group->pins[group->npins++] = pin;
}
/**
* zynqmp_pinctrl_create_pin_groups() - assign pins to respective groups
* @dev: Device pointer.
* @groups: Groups data.
* @pin: Pin number.
*
* Query firmware to get groups available for the given pin.
* Based on the firmware response(group IDs for the pin), add
* pin number to the respective group's pin array.
*
* Once all pins are queries, each group would have its number
* of pins and pin numbers data.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_create_pin_groups(struct device *dev,
struct zynqmp_pctrl_group *groups,
unsigned int pin)
{
u16 resp[NUM_GROUPS_PER_RESP] = {0};
int ret, i, index = 0;
do {
ret = zynqmp_pinctrl_get_pin_groups(pin, index, resp);
if (ret)
return ret;
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
if (resp[i] == NA_GROUP)
return ret;
if (resp[i] == RESERVED_GROUP)
continue;
zynqmp_pinctrl_group_add_pin(&groups[resp[i]], pin);
}
index += NUM_GROUPS_PER_RESP;
} while (index <= MAX_PIN_GROUPS);
return 0;
}
/**
* zynqmp_pinctrl_prepare_group_pins() - prepare each group's pin data
* @dev: Device pointer.
* @groups: Groups data.
* @ngroups: Number of groups.
*
* Prepare pin number and number of pins data for each pins.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_group_pins(struct device *dev,
struct zynqmp_pctrl_group *groups,
unsigned int ngroups)
{
unsigned int pin;
int ret;
for (pin = 0; pin < zynqmp_desc.npins; pin++) {
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, pin);
if (ret)
return ret;
}
return 0;
}
/**
* zynqmp_pinctrl_prepare_function_info() - prepare function info
* @dev: Device pointer.
* @pctrl: Pin control driver data.
*
* Query firmware for functions, groups and pin information and
* prepare pin control driver data.
*
* Query number of functions and number of function groups (number
* of groups in the given function) to allocate required memory buffers
* for functions and groups. Once buffers are allocated to store
* functions and groups data, query and store required information
* (number of groups and group names for each function, number of
* pins and pin numbers for each group).
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_function_info(struct device *dev,
struct zynqmp_pinctrl *pctrl)
{
struct zynqmp_pmux_function *funcs;
struct zynqmp_pctrl_group *groups;
int ret, i;
ret = zynqmp_pinctrl_get_num_functions(&pctrl->nfuncs);
if (ret)
return ret;
funcs = devm_kzalloc(dev, sizeof(*funcs) * pctrl->nfuncs, GFP_KERNEL);
if (!funcs)
return -ENOMEM;
for (i = 0; i < pctrl->nfuncs; i++) {
zynqmp_pinctrl_get_function_name(i, funcs[i].name);
ret = zynqmp_pinctrl_get_func_num_groups(i, &funcs[i].ngroups);
if (ret)
return ret;
pctrl->ngroups += funcs[i].ngroups;
}
groups = devm_kzalloc(dev, sizeof(*groups) * pctrl->ngroups, GFP_KERNEL);
if (!groups)
return -ENOMEM;
for (i = 0; i < pctrl->nfuncs; i++) {
ret = zynqmp_pinctrl_prepare_func_groups(dev, i, &funcs[i],
groups);
if (ret)
return ret;
}
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
if (ret)
return ret;
pctrl->funcs = funcs;
pctrl->groups = groups;
return 0;
}
static int zynqmp_pinctrl_get_num_pins(unsigned int *npins)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_PINS;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*npins = payload[1];
return 0;
}
/**
* zynqmp_pinctrl_prepare_pin_desc() - prepare pin description info
* @dev: Device pointer.
* @zynqmp_pins: Pin information.
* @npins: Number of pins.
*
* Query number of pins information from firmware and prepare pin
* description containing pin number and pin name.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
const struct pinctrl_pin_desc
**zynqmp_pins,
unsigned int *npins)
{
struct pinctrl_pin_desc *pins, *pin;
int ret;
int i;
ret = zynqmp_pinctrl_get_num_pins(npins);
if (ret)
return ret;
pins = devm_kzalloc(dev, sizeof(*pins) * *npins, GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < *npins; i++) {
pin = &pins[i];
pin->number = i;
pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d",
ZYNQMP_PIN_PREFIX, i);
if (!pin->name)
return -ENOMEM;
}
*zynqmp_pins = pins;
return 0;
}
static int zynqmp_pinctrl_probe(struct platform_device *pdev)
{
struct zynqmp_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
ret = zynqmp_pinctrl_prepare_pin_desc(&pdev->dev,
&zynqmp_desc.pins,
&zynqmp_desc.npins);
if (ret) {
dev_err(&pdev->dev, "pin desc prepare fail with %d\n", ret);
return ret;
}
ret = zynqmp_pinctrl_prepare_function_info(&pdev->dev, pctrl);
if (ret) {
dev_err(&pdev->dev, "function info prepare fail with %d\n", ret);
return ret;
}
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynqmp_desc, pctrl);
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
platform_set_drvdata(pdev, pctrl);
return ret;
}
static const struct of_device_id zynqmp_pinctrl_of_match[] = {
{ .compatible = "xlnx,zynqmp-pinctrl" },
{ }
};
MODULE_DEVICE_TABLE(of, zynqmp_pinctrl_of_match);
static struct platform_driver zynqmp_pinctrl_driver = {
.driver = {
.name = "zynqmp-pinctrl",
.of_match_table = zynqmp_pinctrl_of_match,
},
.probe = zynqmp_pinctrl_probe,
};
module_platform_driver(zynqmp_pinctrl_driver);
MODULE_AUTHOR("Sai Krishna Potthuri <[email protected]>");
MODULE_DESCRIPTION("ZynqMP Pin Controller Driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-zynqmp.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AXP20x pinctrl and GPIO driver
*
* Copyright (C) 2016 Maxime Ripard <[email protected]>
* Copyright (C) 2017 Quentin Schulz <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#define AXP20X_GPIO_FUNCTIONS 0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
#define AXP20X_GPIO_FUNCTION_INPUT 2
#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
#define AXP20X_GPIO3_FUNCTION_INPUT 4
#define AXP20X_FUNC_GPIO_OUT 0
#define AXP20X_FUNC_GPIO_IN 1
#define AXP20X_FUNC_LDO 2
#define AXP20X_FUNC_ADC 3
#define AXP20X_FUNCS_NB 4
#define AXP20X_MUX_GPIO_OUT 0
#define AXP20X_MUX_GPIO_IN BIT(1)
#define AXP20X_MUX_ADC BIT(2)
#define AXP813_MUX_ADC (BIT(2) | BIT(0))
struct axp20x_pctrl_desc {
const struct pinctrl_pin_desc *pins;
unsigned int npins;
/* Stores the pins supporting LDO function. Bit offset is pin number. */
u8 ldo_mask;
/* Stores the pins supporting ADC function. Bit offset is pin number. */
u8 adc_mask;
u8 gpio_status_offset;
u8 adc_mux;
};
struct axp20x_pinctrl_function {
const char *name;
unsigned int muxval;
const char **groups;
unsigned int ngroups;
};
struct axp20x_pctl {
struct gpio_chip chip;
struct regmap *regmap;
struct pinctrl_dev *pctl_dev;
struct device *dev;
const struct axp20x_pctrl_desc *desc;
struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
};
static const struct pinctrl_pin_desc axp209_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
PINCTRL_PIN(3, "GPIO3"),
};
static const struct pinctrl_pin_desc axp22x_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
};
static const struct axp20x_pctrl_desc axp20x_data = {
.pins = axp209_pins,
.npins = ARRAY_SIZE(axp209_pins),
.ldo_mask = BIT(0) | BIT(1),
.adc_mask = BIT(0) | BIT(1),
.gpio_status_offset = 4,
.adc_mux = AXP20X_MUX_ADC,
};
static const struct axp20x_pctrl_desc axp22x_data = {
.pins = axp22x_pins,
.npins = ARRAY_SIZE(axp22x_pins),
.ldo_mask = BIT(0) | BIT(1),
.gpio_status_offset = 0,
};
static const struct axp20x_pctrl_desc axp813_data = {
.pins = axp22x_pins,
.npins = ARRAY_SIZE(axp22x_pins),
.ldo_mask = BIT(0) | BIT(1),
.adc_mask = BIT(0),
.gpio_status_offset = 0,
.adc_mux = AXP813_MUX_ADC,
};
static int axp20x_gpio_get_reg(unsigned int offset)
{
switch (offset) {
case 0:
return AXP20X_GPIO0_CTRL;
case 1:
return AXP20X_GPIO1_CTRL;
case 2:
return AXP20X_GPIO2_CTRL;
}
return -EINVAL;
}
static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
unsigned int val;
int ret;
/* AXP209 has GPIO3 status sharing the settings register */
if (offset == 3) {
ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
if (ret)
return ret;
return !!(val & BIT(0));
}
ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
if (ret)
return ret;
return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}
static int axp20x_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
unsigned int val;
int reg, ret;
/* AXP209 GPIO3 settings have a different layout */
if (offset == 3) {
ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
if (ret)
return ret;
if (val & AXP20X_GPIO3_FUNCTION_INPUT)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
ret = regmap_read(pctl->regmap, reg, &val);
if (ret)
return ret;
/*
* This shouldn't really happen if the pin is in use already,
* or if it's not in use yet, it doesn't matter since we're
* going to change the value soon anyway. Default to output.
*/
if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
return GPIO_LINE_DIRECTION_OUT;
/*
* The GPIO directions are the three lowest values.
* 2 is input, 0 and 1 are output
*/
if (val & 2)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
chip->set(chip, offset, value);
return 0;
}
static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
int reg;
/* AXP209 has GPIO3 status sharing the settings register */
if (offset == 3) {
regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
AXP20X_GPIO3_FUNCTIONS,
value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
AXP20X_GPIO3_FUNCTION_OUT_LOW);
return;
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return;
regmap_update_bits(pctl->regmap, reg,
AXP20X_GPIO_FUNCTIONS,
value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
AXP20X_GPIO_FUNCTION_OUT_LOW);
}
static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
u8 config)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
int reg;
/* AXP209 GPIO3 settings have a different layout */
if (offset == 3) {
return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
AXP20X_GPIO3_FUNCTIONS,
config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
AXP20X_GPIO3_FUNCTION_INPUT);
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
config);
}
static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
return ARRAY_SIZE(pctl->funcs);
}
static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->funcs[selector].name;
}
static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int *num_groups)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->funcs[selector].groups;
*num_groups = pctl->funcs[selector].ngroups;
return 0;
}
static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned int mask;
/* Every pin supports GPIO_OUT and GPIO_IN functions */
if (function <= AXP20X_FUNC_GPIO_IN)
return axp20x_pmx_set(pctldev, group,
pctl->funcs[function].muxval);
if (function == AXP20X_FUNC_LDO)
mask = pctl->desc->ldo_mask;
else
mask = pctl->desc->adc_mask;
if (!(BIT(group) & mask))
return -EINVAL;
/*
* We let the regulator framework handle the LDO muxing as muxing bits
* are basically also regulators on/off bits. It's better not to enforce
* any state of the regulator when selecting LDO mux so that we don't
* interfere with the regulator driver.
*/
if (function == AXP20X_FUNC_LDO)
return 0;
return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}
static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
if (input)
return axp20x_pmx_set(pctldev, offset,
pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
return axp20x_pmx_set(pctldev, offset,
pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}
static const struct pinmux_ops axp20x_pmx_ops = {
.get_functions_count = axp20x_pmx_func_cnt,
.get_function_name = axp20x_pmx_func_name,
.get_function_groups = axp20x_pmx_func_groups,
.set_mux = axp20x_pmx_set_mux,
.gpio_set_direction = axp20x_pmx_gpio_set_direction,
.strict = true,
};
static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->desc->npins;
}
static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
const unsigned int **pins, unsigned int *num_pins)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned int *)&pctl->desc->pins[selector];
*num_pins = 1;
return 0;
}
static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->desc->pins[selector].name;
}
static const struct pinctrl_ops axp20x_pctrl_ops = {
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
.dt_free_map = pinconf_generic_dt_free_map,
.get_groups_count = axp20x_groups_cnt,
.get_group_name = axp20x_group_name,
.get_group_pins = axp20x_group_pins,
};
static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
unsigned int mask_len,
struct axp20x_pinctrl_function *func,
const struct pinctrl_pin_desc *pins)
{
unsigned long int mask_cpy = mask;
const char **group;
unsigned int ngroups = hweight8(mask);
int bit;
func->ngroups = ngroups;
if (func->ngroups > 0) {
func->groups = devm_kcalloc(dev,
ngroups, sizeof(const char *),
GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
group = func->groups;
for_each_set_bit(bit, &mask_cpy, mask_len) {
*group = pins[bit].name;
group++;
}
}
return 0;
}
static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
int i, ret, pin, npins = pctl->desc->npins;
pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
/*
* Muxval for LDO is useless as we won't use it.
* See comment in axp20x_pmx_set_mux.
*/
pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
/* Every pin supports GPIO_OUT and GPIO_IN functions */
for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
pctl->funcs[i].ngroups = npins;
pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
npins, sizeof(char *),
GFP_KERNEL);
if (!pctl->funcs[i].groups)
return -ENOMEM;
for (pin = 0; pin < npins; pin++)
pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
}
ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
npins, &pctl->funcs[AXP20X_FUNC_LDO],
pctl->desc->pins);
if (ret)
return ret;
ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
npins, &pctl->funcs[AXP20X_FUNC_ADC],
pctl->desc->pins);
if (ret)
return ret;
return 0;
}
static const struct of_device_id axp20x_pctl_match[] = {
{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
{ .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
static int axp20x_pctl_probe(struct platform_device *pdev)
{
struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
struct axp20x_pctl *pctl;
struct device *dev = &pdev->dev;
struct pinctrl_desc *pctrl_desc;
int ret;
if (!of_device_is_available(pdev->dev.of_node))
return -ENODEV;
if (!axp20x) {
dev_err(&pdev->dev, "Parent drvdata not set\n");
return -EINVAL;
}
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->chip.base = -1;
pctl->chip.can_sleep = true;
pctl->chip.request = gpiochip_generic_request;
pctl->chip.free = gpiochip_generic_free;
pctl->chip.parent = &pdev->dev;
pctl->chip.label = dev_name(&pdev->dev);
pctl->chip.owner = THIS_MODULE;
pctl->chip.get = axp20x_gpio_get;
pctl->chip.get_direction = axp20x_gpio_get_direction;
pctl->chip.set = axp20x_gpio_set;
pctl->chip.direction_input = axp20x_gpio_input;
pctl->chip.direction_output = axp20x_gpio_output;
pctl->desc = of_device_get_match_data(dev);
pctl->chip.ngpio = pctl->desc->npins;
pctl->regmap = axp20x->regmap;
pctl->dev = &pdev->dev;
platform_set_drvdata(pdev, pctl);
ret = axp20x_build_funcs_groups(pdev);
if (ret) {
dev_err(&pdev->dev, "failed to build groups\n");
return ret;
}
pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
if (!pctrl_desc)
return -ENOMEM;
pctrl_desc->name = dev_name(&pdev->dev);
pctrl_desc->owner = THIS_MODULE;
pctrl_desc->pins = pctl->desc->pins;
pctrl_desc->npins = pctl->desc->npins;
pctrl_desc->pctlops = &axp20x_pctrl_ops;
pctrl_desc->pmxops = &axp20x_pmx_ops;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
if (IS_ERR(pctl->pctl_dev)) {
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
return PTR_ERR(pctl->pctl_dev);
}
ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
if (ret) {
dev_err(&pdev->dev, "Failed to register GPIO chip\n");
return ret;
}
ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
pctl->desc->pins->number,
pctl->desc->pins->number,
pctl->desc->npins);
if (ret) {
dev_err(&pdev->dev, "failed to add pin range\n");
return ret;
}
dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
return 0;
}
static struct platform_driver axp20x_pctl_driver = {
.probe = axp20x_pctl_probe,
.driver = {
.name = "axp20x-gpio",
.of_match_table = axp20x_pctl_match,
},
};
module_platform_driver(axp20x_pctl_driver);
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_AUTHOR("Quentin Schulz <[email protected]>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-axp209.c
|
// SPDX-License-Identifier: GPL-2.0-only
/* MCP23S08 SPI GPIO driver */
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include "pinctrl-mcp23s08.h"
#define MCP_MAX_DEV_PER_CS 8
/*
* A given spi_device can represent up to eight mcp23sxx chips
* sharing the same chipselect but using different addresses
* (e.g. chips #0 and #3 might be populated, but not #1 or #2).
* Driver data holds all the per-chip data.
*/
struct mcp23s08_driver_data {
unsigned ngpio;
struct mcp23s08 *mcp[8];
struct mcp23s08 chip[];
};
static int mcp23sxx_spi_write(void *context, const void *data, size_t count)
{
struct mcp23s08 *mcp = context;
struct spi_device *spi = to_spi_device(mcp->dev);
struct spi_message m;
struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, },
{ .tx_buf = data, .len = count, }, };
spi_message_init(&m);
spi_message_add_tail(&t[0], &m);
spi_message_add_tail(&t[1], &m);
return spi_sync(spi, &m);
}
static int mcp23sxx_spi_gather_write(void *context,
const void *reg, size_t reg_size,
const void *val, size_t val_size)
{
struct mcp23s08 *mcp = context;
struct spi_device *spi = to_spi_device(mcp->dev);
struct spi_message m;
struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, },
{ .tx_buf = reg, .len = reg_size, },
{ .tx_buf = val, .len = val_size, }, };
spi_message_init(&m);
spi_message_add_tail(&t[0], &m);
spi_message_add_tail(&t[1], &m);
spi_message_add_tail(&t[2], &m);
return spi_sync(spi, &m);
}
static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct mcp23s08 *mcp = context;
struct spi_device *spi = to_spi_device(mcp->dev);
u8 tx[2];
if (reg_size != 1)
return -EINVAL;
tx[0] = mcp->addr | 0x01;
tx[1] = *((u8 *) reg);
return spi_write_then_read(spi, tx, sizeof(tx), val, val_size);
}
static const struct regmap_bus mcp23sxx_spi_regmap = {
.write = mcp23sxx_spi_write,
.gather_write = mcp23sxx_spi_gather_write,
.read = mcp23sxx_spi_read,
};
static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev,
unsigned int addr, unsigned int type)
{
const struct regmap_config *config;
struct regmap_config *copy;
const char *name;
switch (type) {
case MCP_TYPE_S08:
mcp->reg_shift = 0;
mcp->chip.ngpio = 8;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr);
if (!mcp->chip.label)
return -ENOMEM;
config = &mcp23x08_regmap;
name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr);
if (!name)
return -ENOMEM;
break;
case MCP_TYPE_S17:
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr);
if (!mcp->chip.label)
return -ENOMEM;
config = &mcp23x17_regmap;
name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr);
if (!name)
return -ENOMEM;
break;
case MCP_TYPE_S18:
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = "mcp23s18";
config = &mcp23x17_regmap;
name = config->name;
break;
default:
dev_err(dev, "invalid device type (%d)\n", type);
return -EINVAL;
}
copy = devm_kmemdup(dev, config, sizeof(*config), GFP_KERNEL);
if (!copy)
return -ENOMEM;
copy->name = name;
mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy);
if (IS_ERR(mcp->regmap))
dev_err(dev, "regmap init failed for %s\n", mcp->chip.label);
return PTR_ERR_OR_ZERO(mcp->regmap);
}
static int mcp23s08_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct mcp23s08_driver_data *data;
unsigned long spi_present_mask;
const void *match;
unsigned int addr;
unsigned int ngpio = 0;
int chips;
int type;
int ret;
u32 v;
match = device_get_match_data(dev);
if (match)
type = (int)(uintptr_t)match;
else
type = spi_get_device_id(spi)->driver_data;
ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v);
if (ret) {
ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v);
if (ret) {
dev_err(dev, "missing spi-present-mask");
return ret;
}
}
spi_present_mask = v;
if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) {
dev_err(dev, "invalid spi-present-mask");
return -ENODEV;
}
chips = hweight_long(spi_present_mask);
data = devm_kzalloc(dev, struct_size(data, chip, chips), GFP_KERNEL);
if (!data)
return -ENOMEM;
spi_set_drvdata(spi, data);
for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) {
data->mcp[addr] = &data->chip[--chips];
data->mcp[addr]->irq = spi->irq;
ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type);
if (ret)
return ret;
data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
"mcp23xxx-pinctrl.%d",
addr);
if (!data->mcp[addr]->pinctrl_desc.name)
return -ENOMEM;
ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1);
if (ret < 0)
return ret;
ngpio += data->mcp[addr]->chip.ngpio;
}
data->ngpio = ngpio;
return 0;
}
static const struct spi_device_id mcp23s08_ids[] = {
{ "mcp23s08", MCP_TYPE_S08 },
{ "mcp23s17", MCP_TYPE_S17 },
{ "mcp23s18", MCP_TYPE_S18 },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
static const struct of_device_id mcp23s08_spi_of_match[] = {
{
.compatible = "microchip,mcp23s08",
.data = (void *) MCP_TYPE_S08,
},
{
.compatible = "microchip,mcp23s17",
.data = (void *) MCP_TYPE_S17,
},
{
.compatible = "microchip,mcp23s18",
.data = (void *) MCP_TYPE_S18,
},
/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
{
.compatible = "mcp,mcp23s08",
.data = (void *) MCP_TYPE_S08,
},
{
.compatible = "mcp,mcp23s17",
.data = (void *) MCP_TYPE_S17,
},
{ }
};
MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
static struct spi_driver mcp23s08_driver = {
.probe = mcp23s08_probe,
.id_table = mcp23s08_ids,
.driver = {
.name = "mcp23s08",
.of_match_table = mcp23s08_spi_of_match,
},
};
static int __init mcp23s08_spi_init(void)
{
return spi_register_driver(&mcp23s08_driver);
}
/*
* Register after SPI postcore initcall and before
* subsys initcalls that may rely on these GPIOs.
*/
subsys_initcall(mcp23s08_spi_init);
static void mcp23s08_spi_exit(void)
{
spi_unregister_driver(&mcp23s08_driver);
}
module_exit(mcp23s08_spi_exit);
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-mcp23s08_spi.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Apple SoC pinctrl+GPIO+external IRQ driver
*
* Copyright (C) The Asahi Linux Contributors
* Copyright (C) 2020 Corellium LLC
*
* Based on: pinctrl-pistachio.c
* Copyright (C) 2014 Imagination Technologies Ltd.
* Copyright (C) 2014 Google, Inc.
*/
#include <dt-bindings/pinctrl/apple.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-utils.h"
#include "core.h"
#include "pinmux.h"
struct apple_gpio_pinctrl {
struct device *dev;
struct pinctrl_dev *pctldev;
void __iomem *base;
struct regmap *map;
struct pinctrl_desc pinctrl_desc;
struct gpio_chip gpio_chip;
u8 irqgrps[];
};
#define REG_GPIO(x) (4 * (x))
#define REG_GPIOx_DATA BIT(0)
#define REG_GPIOx_MODE GENMASK(3, 1)
#define REG_GPIOx_OUT 1
#define REG_GPIOx_IN_IRQ_HI 2
#define REG_GPIOx_IN_IRQ_LO 3
#define REG_GPIOx_IN_IRQ_UP 4
#define REG_GPIOx_IN_IRQ_DN 5
#define REG_GPIOx_IN_IRQ_ANY 6
#define REG_GPIOx_IN_IRQ_OFF 7
#define REG_GPIOx_PERIPH GENMASK(6, 5)
#define REG_GPIOx_PULL GENMASK(8, 7)
#define REG_GPIOx_PULL_OFF 0
#define REG_GPIOx_PULL_DOWN 1
#define REG_GPIOx_PULL_UP_STRONG 2
#define REG_GPIOx_PULL_UP 3
#define REG_GPIOx_INPUT_ENABLE BIT(9)
#define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
#define REG_GPIOx_SCHMITT BIT(15)
#define REG_GPIOx_GRP GENMASK(18, 16)
#define REG_GPIOx_LOCK BIT(21)
#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
#define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
.max_register = 512 * sizeof(u32),
.num_reg_defaults_raw = 512,
.use_relaxed_mmio = true,
.use_raw_spinlock = true,
};
/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
unsigned int pin, u32 mask, u32 value)
{
regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
}
static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
unsigned int pin)
{
int ret;
u32 val;
ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
if (ret)
return 0;
return val;
}
/* Pin controller functions */
static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *num_maps)
{
unsigned reserved_maps;
struct apple_gpio_pinctrl *pctl;
u32 pinfunc, pin, func;
int num_pins, i, ret;
const char *group_name;
const char *function_name;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
pctl = pinctrl_dev_get_drvdata(pctldev);
ret = of_property_count_u32_elems(node, "pinmux");
if (ret <= 0) {
dev_err(pctl->dev,
"missing or empty pinmux property in node %pOFn.\n",
node);
return ret ? ret : -EINVAL;
}
num_pins = ret;
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
if (ret)
return ret;
for (i = 0; i < num_pins; i++) {
ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
if (ret)
goto free_map;
pin = APPLE_PIN(pinfunc);
func = APPLE_FUNC(pinfunc);
if (func >= pinmux_generic_get_function_count(pctldev)) {
ret = -EINVAL;
goto free_map;
}
group_name = pinctrl_generic_get_group_name(pctldev, pin);
function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
&reserved_maps, num_maps,
group_name, function_name);
if (ret)
goto free_map;
}
free_map:
if (ret < 0)
pinctrl_utils_free_map(pctldev, *map, *num_maps);
return ret;
}
static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = apple_gpio_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
/* Pin multiplexer functions */
static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
unsigned group)
{
struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
apple_gpio_set_reg(
pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
return 0;
}
static const struct pinmux_ops apple_gpio_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = apple_gpio_pinmux_set,
.strict = true,
};
/* GPIO chip functions */
static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
unsigned int reg = apple_gpio_get_reg(pctl, offset);
if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
unsigned int reg = apple_gpio_get_reg(pctl, offset);
/*
* If this is an input GPIO, read the actual value (not the
* cached regmap value)
*/
if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
reg = readl_relaxed(pctl->base + REG_GPIO(offset));
return !!(reg & REG_GPIOx_DATA);
}
static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
}
static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
apple_gpio_set_reg(pctl, offset,
REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
REG_GPIOx_INPUT_ENABLE,
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
REG_GPIOx_INPUT_ENABLE);
return 0;
}
static int apple_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
apple_gpio_set_reg(pctl, offset,
REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
(value ? REG_GPIOx_DATA : 0));
return 0;
}
/* IRQ chip functions */
static void apple_gpio_irq_ack(struct irq_data *data)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
}
static unsigned int apple_gpio_irq_type(unsigned int type)
{
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
return REG_GPIOx_IN_IRQ_UP;
case IRQ_TYPE_EDGE_FALLING:
return REG_GPIOx_IN_IRQ_DN;
case IRQ_TYPE_EDGE_BOTH:
return REG_GPIOx_IN_IRQ_ANY;
case IRQ_TYPE_LEVEL_HIGH:
return REG_GPIOx_IN_IRQ_HI;
case IRQ_TYPE_LEVEL_LOW:
return REG_GPIOx_IN_IRQ_LO;
default:
return REG_GPIOx_IN_IRQ_OFF;
}
}
static void apple_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
gpiochip_disable_irq(gc, data->hwirq);
}
static void apple_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
gpiochip_enable_irq(gc, data->hwirq);
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
FIELD_PREP(REG_GPIOx_MODE, irqtype));
}
static unsigned int apple_gpio_irq_startup(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
FIELD_PREP(REG_GPIOx_GRP, 0));
apple_gpio_direction_input(chip, data->hwirq);
apple_gpio_irq_unmask(data);
return 0;
}
static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
unsigned int irqtype = apple_gpio_irq_type(type);
if (irqtype == REG_GPIOx_IN_IRQ_OFF)
return -EINVAL;
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
FIELD_PREP(REG_GPIOx_MODE, irqtype));
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);
return 0;
}
static void apple_gpio_irq_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
u8 *grpp = irq_desc_get_handler_data(desc);
struct apple_gpio_pinctrl *pctl;
unsigned int pinh, pinl;
unsigned long pending;
struct gpio_chip *gc;
pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
gc = &pctl->gpio_chip;
chained_irq_enter(chip, desc);
for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
for_each_set_bit(pinl, &pending, 32)
generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
}
chained_irq_exit(chip, desc);
}
static const struct irq_chip apple_gpio_irqchip = {
.name = "Apple-GPIO",
.irq_startup = apple_gpio_irq_startup,
.irq_ack = apple_gpio_irq_ack,
.irq_mask = apple_gpio_irq_mask,
.irq_unmask = apple_gpio_irq_unmask,
.irq_set_type = apple_gpio_irq_set_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
/* Probe & register */
static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
{
struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
void **irq_data = NULL;
int ret;
pctl->gpio_chip.label = dev_name(pctl->dev);
pctl->gpio_chip.request = gpiochip_generic_request;
pctl->gpio_chip.free = gpiochip_generic_free;
pctl->gpio_chip.get_direction = apple_gpio_get_direction;
pctl->gpio_chip.direction_input = apple_gpio_direction_input;
pctl->gpio_chip.direction_output = apple_gpio_direction_output;
pctl->gpio_chip.get = apple_gpio_get;
pctl->gpio_chip.set = apple_gpio_set;
pctl->gpio_chip.base = -1;
pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
pctl->gpio_chip.parent = pctl->dev;
if (girq->num_parents) {
int i;
gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
girq->parent_handler = apple_gpio_irq_handler;
girq->parents = kmalloc_array(girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
GFP_KERNEL);
if (!girq->parents || !irq_data) {
ret = -ENOMEM;
goto out_free_irq_data;
}
for (i = 0; i < girq->num_parents; i++) {
ret = platform_get_irq(to_platform_device(pctl->dev), i);
if (ret < 0)
goto out_free_irq_data;
girq->parents[i] = ret;
pctl->irqgrps[i] = i;
irq_data[i] = &pctl->irqgrps[i];
}
girq->parent_handler_data_array = irq_data;
girq->per_parent_data = true;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
}
ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
out_free_irq_data:
kfree(girq->parents);
kfree(irq_data);
return ret;
}
static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
{
struct apple_gpio_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
unsigned int npins;
const char **pin_names;
unsigned int *pin_nums;
static const char* pinmux_functions[] = {
"gpio", "periph1", "periph2", "periph3"
};
unsigned int i, nirqs = 0;
int res;
if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
res = platform_irq_count(pdev);
if (res > 0)
nirqs = res;
}
pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
GFP_KERNEL);
if (!pctl)
return -ENOMEM;
pctl->dev = &pdev->dev;
pctl->gpio_chip.irq.num_parents = nirqs;
dev_set_drvdata(&pdev->dev, pctl);
if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
return dev_err_probe(&pdev->dev, -EINVAL,
"apple,npins property not found\n");
pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
GFP_KERNEL);
pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
GFP_KERNEL);
pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
GFP_KERNEL);
if (!pins || !pin_names || !pin_nums)
return -ENOMEM;
pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctl->base))
return PTR_ERR(pctl->base);
pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config);
if (IS_ERR(pctl->map))
return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
"Failed to create regmap\n");
for (i = 0; i < npins; i++) {
pins[i].number = i;
pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
pins[i].drv_data = pctl;
pin_names[i] = pins[i].name;
pin_nums[i] = i;
}
pctl->pinctrl_desc.name = dev_name(pctl->dev);
pctl->pinctrl_desc.pins = pins;
pctl->pinctrl_desc.npins = npins;
pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
if (IS_ERR(pctl->pctldev))
return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
"Failed to register pinctrl device.\n");
for (i = 0; i < npins; i++) {
res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
pin_nums + i, 1, pctl);
if (res < 0)
return dev_err_probe(pctl->dev, res,
"Failed to register group");
}
for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
pin_names, npins, pctl);
if (res < 0)
return dev_err_probe(pctl->dev, res,
"Failed to register function.");
}
return apple_gpio_register(pctl);
}
static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
{ .compatible = "apple,pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
static struct platform_driver apple_gpio_pinctrl_driver = {
.driver = {
.name = "apple-gpio-pinctrl",
.of_match_table = apple_gpio_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = apple_gpio_pinctrl_probe,
};
module_platform_driver(apple_gpio_pinctrl_driver);
MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
MODULE_AUTHOR("Stan Skowronek <[email protected]>");
MODULE_AUTHOR("Joey Gouly <[email protected]>");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-apple-gpio.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Atmel PIO4 controller
*
* Copyright (C) 2015 Atmel,
* 2015 Ludovic Desroches <[email protected]>
*/
#include <dt-bindings/pinctrl/at91.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
/*
* Warning:
* In order to not introduce confusion between Atmel PIO groups and pinctrl
* framework groups, Atmel PIO groups will be called banks, line is kept to
* designed the pin id into this bank.
*/
#define ATMEL_PIO_MSKR 0x0000
#define ATMEL_PIO_CFGR 0x0004
#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
#define ATMEL_PIO_DIR_MASK BIT(8)
#define ATMEL_PIO_PUEN_MASK BIT(9)
#define ATMEL_PIO_PDEN_MASK BIT(10)
#define ATMEL_PIO_SR_MASK BIT(11)
#define ATMEL_PIO_IFEN_MASK BIT(12)
#define ATMEL_PIO_IFSCEN_MASK BIT(13)
#define ATMEL_PIO_OPD_MASK BIT(14)
#define ATMEL_PIO_SCHMITT_MASK BIT(15)
#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
#define ATMEL_PIO_DRVSTR_OFFSET 16
#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
#define ATMEL_PIO_PDSR 0x0008
#define ATMEL_PIO_LOCKSR 0x000C
#define ATMEL_PIO_SODR 0x0010
#define ATMEL_PIO_CODR 0x0014
#define ATMEL_PIO_ODSR 0x0018
#define ATMEL_PIO_IER 0x0020
#define ATMEL_PIO_IDR 0x0024
#define ATMEL_PIO_IMR 0x0028
#define ATMEL_PIO_ISR 0x002C
#define ATMEL_PIO_IOFR 0x003C
#define ATMEL_PIO_NPINS_PER_BANK 32
#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
#define ATMEL_PIO_BANK_OFFSET 0x40
#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
/* Custom pinconf parameters */
#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
/**
* struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
* @nbanks: number of PIO banks
* @last_bank_count: number of lines in the last bank (can be less than
* the rest of the banks).
* @slew_rate_support: slew rate support
*/
struct atmel_pioctrl_data {
unsigned int nbanks;
unsigned int last_bank_count;
unsigned int slew_rate_support;
};
struct atmel_group {
const char *name;
u32 pin;
};
struct atmel_pin {
unsigned int pin_id;
unsigned int mux;
unsigned int ioset;
unsigned int bank;
unsigned int line;
const char *device;
};
/**
* struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
* @reg_base: base address of the controller.
* @clk: clock of the controller.
* @nbanks: number of PIO groups, it can vary depending on the SoC.
* @pinctrl_dev: pinctrl device registered.
* @groups: groups table to provide group name and pin in the group to pinctrl.
* @group_names: group names table to provide all the group/pin names to
* pinctrl or gpio.
* @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
* fields are set at probe time. Other ones are set when parsing dt
* pinctrl.
* @npins: number of pins.
* @gpio_chip: gpio chip registered.
* @irq_domain: irq domain for the gpio controller.
* @irqs: table containing the hw irq number of the bank. The index of the
* table is the bank id.
* @pm_wakeup_sources: bitmap of wakeup sources (lines)
* @pm_suspend_backup: backup/restore register values on suspend/resume
* @dev: device entry for the Atmel PIO controller.
* @node: node of the Atmel PIO controller.
* @slew_rate_support: slew rate support
*/
struct atmel_pioctrl {
void __iomem *reg_base;
struct clk *clk;
unsigned int nbanks;
struct pinctrl_dev *pinctrl_dev;
struct atmel_group *groups;
const char * const *group_names;
struct atmel_pin **pins;
unsigned int npins;
struct gpio_chip *gpio_chip;
struct irq_domain *irq_domain;
int *irqs;
unsigned int *pm_wakeup_sources;
struct {
u32 imr;
u32 odsr;
u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
} *pm_suspend_backup;
struct device *dev;
struct device_node *node;
unsigned int slew_rate_support;
};
static const char * const atmel_functions[] = {
"GPIO", "A", "B", "C", "D", "E", "F", "G"
};
static const struct pinconf_generic_params atmel_custom_bindings[] = {
{"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
};
/* --- GPIO --- */
static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
unsigned int bank, unsigned int reg)
{
return readl_relaxed(atmel_pioctrl->reg_base
+ ATMEL_PIO_BANK_OFFSET * bank + reg);
}
static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
unsigned int bank, unsigned int reg,
unsigned int val)
{
writel_relaxed(val, atmel_pioctrl->reg_base
+ ATMEL_PIO_BANK_OFFSET * bank + reg);
}
static void atmel_gpio_irq_ack(struct irq_data *d)
{
/*
* Nothing to do, interrupt is cleared when reading the status
* register.
*/
}
static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
BIT(pin->line));
reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
irq_set_handler_locked(d, handle_edge_irq);
reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
irq_set_handler_locked(d, handle_edge_irq);
reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
irq_set_handler_locked(d, handle_edge_irq);
reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
break;
case IRQ_TYPE_LEVEL_LOW:
irq_set_handler_locked(d, handle_level_irq);
reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_set_handler_locked(d, handle_level_irq);
reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
break;
case IRQ_TYPE_NONE:
default:
return -EINVAL;
}
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
return 0;
}
static void atmel_gpio_irq_mask(struct irq_data *d)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
BIT(pin->line));
}
static void atmel_gpio_irq_unmask(struct irq_data *d)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
BIT(pin->line));
}
static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
int bank = ATMEL_PIO_BANK(d->hwirq);
int line = ATMEL_PIO_LINE(d->hwirq);
/* The gpio controller has one interrupt line per bank. */
irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
if (on)
atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
else
atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
return 0;
}
static struct irq_chip atmel_gpio_irq_chip = {
.name = "GPIO",
.irq_ack = atmel_gpio_irq_ack,
.irq_mask = atmel_gpio_irq_mask,
.irq_unmask = atmel_gpio_irq_unmask,
.irq_set_type = atmel_gpio_irq_set_type,
.irq_set_wake = pm_sleep_ptr(atmel_gpio_irq_set_wake),
};
static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
}
static void atmel_gpio_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long isr;
int n, bank = -1;
/* Find from which bank is the irq received. */
for (n = 0; n < atmel_pioctrl->nbanks; n++) {
if (atmel_pioctrl->irqs[n] == irq) {
bank = n;
break;
}
}
if (bank < 0) {
dev_err(atmel_pioctrl->dev,
"no bank associated to irq %u\n", irq);
return;
}
chained_irq_enter(chip, desc);
for (;;) {
isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
ATMEL_PIO_ISR);
isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
ATMEL_PIO_IMR);
if (!isr)
break;
for_each_set_bit(n, &isr, BITS_PER_LONG)
generic_handle_irq(atmel_gpio_to_irq(
atmel_pioctrl->gpio_chip,
bank * ATMEL_PIO_NPINS_PER_BANK + n));
}
chained_irq_exit(chip, desc);
}
static int atmel_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
BIT(pin->line));
reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
reg &= ~ATMEL_PIO_DIR_MASK;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
return 0;
}
static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
unsigned int reg;
reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
return !!(reg & BIT(pin->line));
}
static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
unsigned int bank;
bitmap_zero(bits, atmel_pioctrl->npins);
for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
unsigned int word = bank;
unsigned int offset = 0;
unsigned int reg;
#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
#endif
if (!mask[word])
continue;
reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
bits[word] |= mask[word] & (reg << offset);
}
return 0;
}
static int atmel_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset,
int value)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
unsigned int reg;
atmel_gpio_write(atmel_pioctrl, pin->bank,
value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
BIT(pin->line));
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
BIT(pin->line));
reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
reg |= ATMEL_PIO_DIR_MASK;
atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
return 0;
}
static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
atmel_gpio_write(atmel_pioctrl, pin->bank,
val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
BIT(pin->line));
}
static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
unsigned long *bits)
{
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
unsigned int bank;
for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
unsigned int bitmask;
unsigned int word = bank;
/*
* On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
* two 32bit words to handle the whole bitmask
*/
#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
#endif
if (!mask[word])
continue;
bitmask = mask[word] & bits[word];
atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
bitmask = mask[word] & ~bits[word];
atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
#endif
}
}
static struct gpio_chip atmel_gpio_chip = {
.direction_input = atmel_gpio_direction_input,
.get = atmel_gpio_get,
.get_multiple = atmel_gpio_get_multiple,
.direction_output = atmel_gpio_direction_output,
.set = atmel_gpio_set,
.set_multiple = atmel_gpio_set_multiple,
.to_irq = atmel_gpio_to_irq,
.base = 0,
};
/* --- PINCTRL --- */
static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
unsigned int pin_id)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
unsigned int line = atmel_pioctrl->pins[pin_id]->line;
void __iomem *addr = atmel_pioctrl->reg_base
+ bank * ATMEL_PIO_BANK_OFFSET;
writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
/* Have to set MSKR first, to access the right pin CFGR. */
wmb();
return readl_relaxed(addr + ATMEL_PIO_CFGR);
}
static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
unsigned int pin_id, u32 conf)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
unsigned int line = atmel_pioctrl->pins[pin_id]->line;
void __iomem *addr = atmel_pioctrl->reg_base
+ bank * ATMEL_PIO_BANK_OFFSET;
writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
/* Have to set MSKR first, to access the right pin CFGR. */
wmb();
writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
}
static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
return atmel_pioctrl->npins;
}
static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
return atmel_pioctrl->groups[selector].name;
}
static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
*num_pins = 1;
return 0;
}
static struct atmel_group *
atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
int i;
for (i = 0; i < atmel_pioctrl->npins; i++) {
struct atmel_group *grp = atmel_pioctrl->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
struct device_node *np,
u32 pinfunc, const char **grp_name,
const char **func_name)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int pin_id, func_id;
struct atmel_group *grp;
pin_id = ATMEL_GET_PIN_NO(pinfunc);
func_id = ATMEL_GET_PIN_FUNC(pinfunc);
if (func_id >= ARRAY_SIZE(atmel_functions))
return -EINVAL;
*func_name = atmel_functions[func_id];
grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
if (!grp)
return -EINVAL;
*grp_name = grp->name;
atmel_pioctrl->pins[pin_id]->mux = func_id;
atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
/* Want the device name not the group one. */
if (np->parent == atmel_pioctrl->node)
atmel_pioctrl->pins[pin_id]->device = np->name;
else
atmel_pioctrl->pins[pin_id]->device = np->parent->name;
return 0;
}
static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
unsigned int num_pins, num_configs, reserve;
unsigned long *configs;
struct property *pins;
u32 pinfunc;
int ret, i;
pins = of_find_property(np, "pinmux", NULL);
if (!pins)
return -EINVAL;
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(pctldev->dev, "%pOF: could not parse node property\n",
np);
return ret;
}
num_pins = pins->length / sizeof(u32);
if (!num_pins) {
dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
ret = -EINVAL;
goto exit;
}
/*
* Reserve maps, at least there is a mux map and an optional conf
* map for each pin.
*/
reserve = 1;
if (num_configs)
reserve++;
reserve *= num_pins;
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
reserve);
if (ret < 0)
goto exit;
for (i = 0; i < num_pins; i++) {
const char *group, *func;
ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
if (ret)
goto exit;
ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
&func);
if (ret)
goto exit;
pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
group, func);
if (num_configs) {
ret = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, group,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (ret < 0)
goto exit;
}
}
exit:
kfree(configs);
return ret;
}
static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct device_node *np;
unsigned int reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
/*
* If all the pins of a device have the same configuration (or no one),
* it is useless to add a subnode, so directly parse node referenced by
* phandle.
*/
ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
&reserved_maps, num_maps);
if (ret) {
for_each_child_of_node(np_config, np) {
ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
of_node_put(np);
break;
}
}
}
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
dev_err(pctldev->dev, "can't create maps for node %pOF\n",
np_config);
}
return ret;
}
static const struct pinctrl_ops atmel_pctlops = {
.get_groups_count = atmel_pctl_get_groups_count,
.get_group_name = atmel_pctl_get_group_name,
.get_group_pins = atmel_pctl_get_group_pins,
.dt_node_to_map = atmel_pctl_dt_node_to_map,
.dt_free_map = pinctrl_utils_free_map,
};
static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(atmel_functions);
}
static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return atmel_functions[selector];
}
static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = atmel_pioctrl->group_names;
*num_groups = atmel_pioctrl->npins;
return 0;
}
static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int pin;
u32 conf;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
atmel_functions[function], atmel_pioctrl->groups[group].name);
pin = atmel_pioctrl->groups[group].pin;
conf = atmel_pin_config_read(pctldev, pin);
conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
atmel_pin_config_write(pctldev, pin, conf);
return 0;
}
static const struct pinmux_ops atmel_pmxops = {
.get_functions_count = atmel_pmx_get_functions_count,
.get_function_name = atmel_pmx_get_function_name,
.get_function_groups = atmel_pmx_get_function_groups,
.set_mux = atmel_pmx_set_mux,
};
static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config), arg = 0;
struct atmel_group *grp = atmel_pioctrl->groups + group;
unsigned int pin_id = grp->pin;
u32 res;
res = atmel_pin_config_read(pctldev, pin_id);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
if (!(res & ATMEL_PIO_PUEN_MASK))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if ((res & ATMEL_PIO_PUEN_MASK) ||
(!(res & ATMEL_PIO_PDEN_MASK)))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
if ((res & ATMEL_PIO_PUEN_MASK) ||
((res & ATMEL_PIO_PDEN_MASK)))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(res & ATMEL_PIO_OPD_MASK))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (res & ATMEL_PIO_OPD_MASK)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!(res & ATMEL_PIO_SCHMITT_MASK))
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_SLEW_RATE:
if (!atmel_pioctrl->slew_rate_support)
return -EOPNOTSUPP;
if (!(res & ATMEL_PIO_SR_MASK))
return -EINVAL;
arg = 1;
break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
if (!(res & ATMEL_PIO_DRVSTR_MASK))
return -EINVAL;
arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
break;
case PIN_CONFIG_PERSIST_STATE:
return -ENOTSUPP;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *configs,
unsigned int num_configs)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
struct atmel_group *grp = atmel_pioctrl->groups + group;
unsigned int bank, pin, pin_id = grp->pin;
u32 mask, conf = 0;
int i;
conf = atmel_pin_config_read(pctldev, pin_id);
/* Keep slew rate enabled by default. */
if (atmel_pioctrl->slew_rate_support)
conf |= ATMEL_PIO_SR_MASK;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
__func__, pin_id, configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
conf &= (~ATMEL_PIO_PUEN_MASK);
conf &= (~ATMEL_PIO_PDEN_MASK);
break;
case PIN_CONFIG_BIAS_PULL_UP:
conf |= ATMEL_PIO_PUEN_MASK;
conf &= (~ATMEL_PIO_PDEN_MASK);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
conf |= ATMEL_PIO_PDEN_MASK;
conf &= (~ATMEL_PIO_PUEN_MASK);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
conf |= ATMEL_PIO_OPD_MASK;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
conf &= ~ATMEL_PIO_OPD_MASK;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (arg == 0)
conf |= ATMEL_PIO_SCHMITT_MASK;
else
conf &= (~ATMEL_PIO_SCHMITT_MASK);
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
if (arg == 0) {
conf &= (~ATMEL_PIO_IFEN_MASK);
conf &= (~ATMEL_PIO_IFSCEN_MASK);
} else {
/*
* We don't care about the debounce value for several reasons:
* - can't have different debounce periods inside a same group,
* - the register to configure this period is a secure register.
* The debouncing filter can filter a pulse with a duration of less
* than 1/2 slow clock period.
*/
conf |= ATMEL_PIO_IFEN_MASK;
conf |= ATMEL_PIO_IFSCEN_MASK;
}
break;
case PIN_CONFIG_OUTPUT:
conf |= ATMEL_PIO_DIR_MASK;
bank = ATMEL_PIO_BANK(pin_id);
pin = ATMEL_PIO_LINE(pin_id);
mask = 1 << pin;
if (arg == 0) {
writel_relaxed(mask, atmel_pioctrl->reg_base +
bank * ATMEL_PIO_BANK_OFFSET +
ATMEL_PIO_CODR);
} else {
writel_relaxed(mask, atmel_pioctrl->reg_base +
bank * ATMEL_PIO_BANK_OFFSET +
ATMEL_PIO_SODR);
}
break;
case PIN_CONFIG_SLEW_RATE:
if (!atmel_pioctrl->slew_rate_support)
break;
/* And remove it if explicitly requested. */
if (arg == 0)
conf &= ~ATMEL_PIO_SR_MASK;
break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case ATMEL_PIO_DRVSTR_LO:
case ATMEL_PIO_DRVSTR_ME:
case ATMEL_PIO_DRVSTR_HI:
conf &= (~ATMEL_PIO_DRVSTR_MASK);
conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
break;
default:
dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
}
break;
case PIN_CONFIG_PERSIST_STATE:
return -ENOTSUPP;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter: %u\n",
param);
continue;
}
}
dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
atmel_pin_config_write(pctldev, pin_id, conf);
return 0;
}
static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs,
unsigned num_configs)
{
struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs);
}
static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs)
{
struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs);
}
static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin_id)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
u32 conf;
if (!atmel_pioctrl->pins[pin_id]->device)
return;
seq_printf(s, " (%s, ioset %u) ",
atmel_pioctrl->pins[pin_id]->device,
atmel_pioctrl->pins[pin_id]->ioset);
conf = atmel_pin_config_read(pctldev, pin_id);
if (conf & ATMEL_PIO_PUEN_MASK)
seq_printf(s, "%s ", "pull-up");
if (conf & ATMEL_PIO_PDEN_MASK)
seq_printf(s, "%s ", "pull-down");
if (conf & ATMEL_PIO_IFEN_MASK)
seq_printf(s, "%s ", "debounce");
if (conf & ATMEL_PIO_OPD_MASK)
seq_printf(s, "%s ", "open-drain");
else
seq_printf(s, "%s ", "push-pull");
if (conf & ATMEL_PIO_SCHMITT_MASK)
seq_printf(s, "%s ", "schmitt");
if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
seq_printf(s, "%s ", "slew-rate");
if (conf & ATMEL_PIO_DRVSTR_MASK) {
switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
case ATMEL_PIO_DRVSTR_ME:
seq_printf(s, "%s ", "medium-drive");
break;
case ATMEL_PIO_DRVSTR_HI:
seq_printf(s, "%s ", "high-drive");
break;
/* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
default:
seq_printf(s, "%s ", "low-drive");
}
}
}
static const struct pinconf_ops atmel_confops = {
.pin_config_group_get = atmel_conf_pin_config_group_get,
.pin_config_group_set = atmel_conf_pin_config_group_set,
.pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
.pin_config_set = atmel_conf_pin_config_set,
.pin_config_get = atmel_conf_pin_config_get,
};
static struct pinctrl_desc atmel_pinctrl_desc = {
.name = "atmel_pinctrl",
.confops = &atmel_confops,
.pctlops = &atmel_pctlops,
.pmxops = &atmel_pmxops,
};
static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
{
struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
/*
* For each bank, save IMR to restore it later and disable all GPIO
* interrupts excepting the ones marked as wakeup sources.
*/
for (i = 0; i < atmel_pioctrl->nbanks; i++) {
atmel_pioctrl->pm_suspend_backup[i].imr =
atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
~atmel_pioctrl->pm_wakeup_sources[i]);
atmel_pioctrl->pm_suspend_backup[i].odsr =
atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
atmel_gpio_write(atmel_pioctrl, i,
ATMEL_PIO_MSKR, BIT(j));
atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
atmel_gpio_read(atmel_pioctrl, i,
ATMEL_PIO_CFGR);
}
}
return 0;
}
static int __maybe_unused atmel_pctrl_resume(struct device *dev)
{
struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
for (i = 0; i < atmel_pioctrl->nbanks; i++) {
atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
atmel_pioctrl->pm_suspend_backup[i].imr);
atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
atmel_pioctrl->pm_suspend_backup[i].odsr);
for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
atmel_gpio_write(atmel_pioctrl, i,
ATMEL_PIO_MSKR, BIT(j));
atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
}
}
return 0;
}
static const struct dev_pm_ops atmel_pctrl_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
};
/*
* The number of banks can be different from a SoC to another one.
* We can have up to 16 banks.
*/
static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
.nbanks = 4,
.last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
};
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
.nbanks = 5,
.last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
.slew_rate_support = 1,
};
static const struct of_device_id atmel_pctrl_of_match[] = {
{
.compatible = "atmel,sama5d2-pinctrl",
.data = &atmel_sama5d2_pioctrl_data,
}, {
.compatible = "microchip,sama7g5-pinctrl",
.data = µchip_sama7g5_pioctrl_data,
}, {
/* sentinel */
}
};
static int atmel_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pinctrl_pin_desc *pin_desc;
const char **group_names;
int i, ret;
struct atmel_pioctrl *atmel_pioctrl;
const struct atmel_pioctrl_data *atmel_pioctrl_data;
atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
if (!atmel_pioctrl)
return -ENOMEM;
atmel_pioctrl->dev = dev;
atmel_pioctrl->node = dev->of_node;
platform_set_drvdata(pdev, atmel_pioctrl);
atmel_pioctrl_data = device_get_match_data(dev);
if (!atmel_pioctrl_data)
return dev_err_probe(dev, -ENODEV, "Invalid device data\n");
atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
/* if last bank has limited number of pins, adjust accordingly */
if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
}
atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(atmel_pioctrl->reg_base))
return PTR_ERR(atmel_pioctrl->reg_base);
atmel_pioctrl->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(atmel_pioctrl->clk))
return dev_err_probe(dev, PTR_ERR(atmel_pioctrl->clk), "failed to get clock\n");
atmel_pioctrl->pins = devm_kcalloc(dev,
atmel_pioctrl->npins,
sizeof(*atmel_pioctrl->pins),
GFP_KERNEL);
if (!atmel_pioctrl->pins)
return -ENOMEM;
pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
GFP_KERNEL);
if (!pin_desc)
return -ENOMEM;
atmel_pinctrl_desc.pins = pin_desc;
atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
/* One pin is one group since a pin can achieve all functions. */
group_names = devm_kcalloc(dev,
atmel_pioctrl->npins, sizeof(*group_names),
GFP_KERNEL);
if (!group_names)
return -ENOMEM;
atmel_pioctrl->group_names = group_names;
atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
GFP_KERNEL);
if (!atmel_pioctrl->groups)
return -ENOMEM;
for (i = 0 ; i < atmel_pioctrl->npins; i++) {
struct atmel_group *group = atmel_pioctrl->groups + i;
unsigned int bank = ATMEL_PIO_BANK(i);
unsigned int line = ATMEL_PIO_LINE(i);
atmel_pioctrl->pins[i] = devm_kzalloc(dev,
sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
if (!atmel_pioctrl->pins[i])
return -ENOMEM;
atmel_pioctrl->pins[i]->pin_id = i;
atmel_pioctrl->pins[i]->bank = bank;
atmel_pioctrl->pins[i]->line = line;
pin_desc[i].number = i;
/* Pin naming convention: P(bank_name)(bank_pin_number). */
pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%u",
bank + 'A', line);
if (!pin_desc[i].name)
return -ENOMEM;
group->name = group_names[i] = pin_desc[i].name;
group->pin = pin_desc[i].number;
dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
}
atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
atmel_pioctrl->gpio_chip->label = dev_name(dev);
atmel_pioctrl->gpio_chip->parent = dev;
atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config;
atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
atmel_pioctrl->nbanks,
sizeof(*atmel_pioctrl->pm_wakeup_sources),
GFP_KERNEL);
if (!atmel_pioctrl->pm_wakeup_sources)
return -ENOMEM;
atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
atmel_pioctrl->nbanks,
sizeof(*atmel_pioctrl->pm_suspend_backup),
GFP_KERNEL);
if (!atmel_pioctrl->pm_suspend_backup)
return -ENOMEM;
atmel_pioctrl->irqs = devm_kcalloc(dev,
atmel_pioctrl->nbanks,
sizeof(*atmel_pioctrl->irqs),
GFP_KERNEL);
if (!atmel_pioctrl->irqs)
return -ENOMEM;
/* There is one controller but each bank has its own irq line. */
for (i = 0; i < atmel_pioctrl->nbanks; i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0) {
dev_dbg(dev, "missing irq resource for group %c\n",
'A' + i);
return ret;
}
atmel_pioctrl->irqs[i] = ret;
irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
}
atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
atmel_pioctrl->gpio_chip->ngpio,
&irq_domain_simple_ops, NULL);
if (!atmel_pioctrl->irq_domain)
return dev_err_probe(dev, -ENODEV, "can't add the irq domain\n");
for (i = 0; i < atmel_pioctrl->npins; i++) {
int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
handle_simple_irq);
irq_set_chip_data(irq, atmel_pioctrl);
dev_dbg(dev,
"atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
i, irq);
}
atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
&atmel_pinctrl_desc,
atmel_pioctrl);
if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
dev_err(dev, "pinctrl registration failed\n");
goto irq_domain_remove_error;
}
ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
if (ret) {
dev_err(dev, "failed to add gpiochip\n");
goto irq_domain_remove_error;
}
ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
0, 0, atmel_pioctrl->gpio_chip->ngpio);
if (ret) {
dev_err(dev, "failed to add gpio pin range\n");
goto gpiochip_add_pin_range_error;
}
dev_info(&pdev->dev, "atmel pinctrl initialized\n");
return 0;
gpiochip_add_pin_range_error:
gpiochip_remove(atmel_pioctrl->gpio_chip);
irq_domain_remove_error:
irq_domain_remove(atmel_pioctrl->irq_domain);
return ret;
}
static struct platform_driver atmel_pinctrl_driver = {
.driver = {
.name = "pinctrl-at91-pio4",
.of_match_table = atmel_pctrl_of_match,
.pm = &atmel_pctrl_pm_ops,
.suppress_bind_attrs = true,
},
.probe = atmel_pinctrl_probe,
};
builtin_platform_driver(atmel_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/pinctrl-at91-pio4.c
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Conexant Digicolor General Purpose Pin Mapping
*
* Author: Baruch Siach <[email protected]>
*
* Copyright (C) 2015 Paradox Innovation Ltd.
*
* TODO:
* - GPIO interrupt support
* - Pin pad configuration (pull up/down, strength)
*/
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-utils.h"
#define DRIVER_NAME "pinctrl-digicolor"
#define GP_CLIENTSEL(clct) ((clct)*8 + 0x20)
#define GP_DRIVE0(clct) (GP_CLIENTSEL(clct) + 2)
#define GP_OUTPUT0(clct) (GP_CLIENTSEL(clct) + 3)
#define GP_INPUT(clct) (GP_CLIENTSEL(clct) + 6)
#define PIN_COLLECTIONS ('R' - 'A' + 1)
#define PINS_PER_COLLECTION 8
#define PINS_COUNT (PIN_COLLECTIONS * PINS_PER_COLLECTION)
struct dc_pinmap {
void __iomem *regs;
struct device *dev;
struct pinctrl_dev *pctl;
struct pinctrl_desc *desc;
const char *pin_names[PINS_COUNT];
struct gpio_chip chip;
spinlock_t lock;
};
static int dc_get_groups_count(struct pinctrl_dev *pctldev)
{
return PINS_COUNT;
}
static const char *dc_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
/* Exactly one group per pin */
return pmap->desc->pins[selector].name;
}
static int dc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
*pins = &pmap->desc->pins[selector].number;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops dc_pinctrl_ops = {
.get_groups_count = dc_get_groups_count,
.get_group_name = dc_get_group_name,
.get_group_pins = dc_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinctrl_utils_free_map,
};
static const char *const dc_functions[] = {
"gpio",
"client_a",
"client_b",
"client_c",
};
static int dc_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(dc_functions);
}
static const char *dc_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
{
return dc_functions[selector];
}
static int dc_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
*groups = pmap->pin_names;
*num_groups = PINS_COUNT;
return 0;
}
static void dc_client_sel(int pin_num, int *reg, int *bit)
{
*bit = (pin_num % PINS_PER_COLLECTION) * 2;
*reg = GP_CLIENTSEL(pin_num/PINS_PER_COLLECTION);
if (*bit >= PINS_PER_COLLECTION) {
*bit -= PINS_PER_COLLECTION;
*reg += 1;
}
}
static int dc_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
int bit_off, reg_off;
u8 reg;
dc_client_sel(group, ®_off, &bit_off);
reg = readb_relaxed(pmap->regs + reg_off);
reg &= ~(3 << bit_off);
reg |= (selector << bit_off);
writeb_relaxed(reg, pmap->regs + reg_off);
return 0;
}
static int dc_pmx_request_gpio(struct pinctrl_dev *pcdev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pcdev);
int bit_off, reg_off;
u8 reg;
dc_client_sel(offset, ®_off, &bit_off);
reg = readb_relaxed(pmap->regs + reg_off);
if ((reg & (3 << bit_off)) != 0)
return -EBUSY;
return 0;
}
static const struct pinmux_ops dc_pmxops = {
.get_functions_count = dc_get_functions_count,
.get_function_name = dc_get_fname,
.get_function_groups = dc_get_groups,
.set_mux = dc_set_mux,
.gpio_request_enable = dc_pmx_request_gpio,
};
static int dc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct dc_pinmap *pmap = gpiochip_get_data(chip);
int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
int bit_off = gpio % PINS_PER_COLLECTION;
u8 drive;
unsigned long flags;
spin_lock_irqsave(&pmap->lock, flags);
drive = readb_relaxed(pmap->regs + reg_off);
drive &= ~BIT(bit_off);
writeb_relaxed(drive, pmap->regs + reg_off);
spin_unlock_irqrestore(&pmap->lock, flags);
return 0;
}
static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value);
static int dc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
int value)
{
struct dc_pinmap *pmap = gpiochip_get_data(chip);
int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
int bit_off = gpio % PINS_PER_COLLECTION;
u8 drive;
unsigned long flags;
dc_gpio_set(chip, gpio, value);
spin_lock_irqsave(&pmap->lock, flags);
drive = readb_relaxed(pmap->regs + reg_off);
drive |= BIT(bit_off);
writeb_relaxed(drive, pmap->regs + reg_off);
spin_unlock_irqrestore(&pmap->lock, flags);
return 0;
}
static int dc_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
struct dc_pinmap *pmap = gpiochip_get_data(chip);
int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION);
int bit_off = gpio % PINS_PER_COLLECTION;
u8 input;
input = readb_relaxed(pmap->regs + reg_off);
return !!(input & BIT(bit_off));
}
static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
{
struct dc_pinmap *pmap = gpiochip_get_data(chip);
int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION);
int bit_off = gpio % PINS_PER_COLLECTION;
u8 output;
unsigned long flags;
spin_lock_irqsave(&pmap->lock, flags);
output = readb_relaxed(pmap->regs + reg_off);
if (value)
output |= BIT(bit_off);
else
output &= ~BIT(bit_off);
writeb_relaxed(output, pmap->regs + reg_off);
spin_unlock_irqrestore(&pmap->lock, flags);
}
static int dc_gpiochip_add(struct dc_pinmap *pmap)
{
struct gpio_chip *chip = &pmap->chip;
int ret;
chip->label = DRIVER_NAME;
chip->parent = pmap->dev;
chip->request = gpiochip_generic_request;
chip->free = gpiochip_generic_free;
chip->direction_input = dc_gpio_direction_input;
chip->direction_output = dc_gpio_direction_output;
chip->get = dc_gpio_get;
chip->set = dc_gpio_set;
chip->base = -1;
chip->ngpio = PINS_COUNT;
spin_lock_init(&pmap->lock);
ret = gpiochip_add_data(chip, pmap);
if (ret < 0)
return ret;
ret = gpiochip_add_pin_range(chip, dev_name(pmap->dev), 0, 0,
PINS_COUNT);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
}
return 0;
}
static int dc_pinctrl_probe(struct platform_device *pdev)
{
struct dc_pinmap *pmap;
struct pinctrl_pin_desc *pins;
struct pinctrl_desc *pctl_desc;
char *pin_names;
int name_len = strlen("GP_xx") + 1;
int i, j;
pmap = devm_kzalloc(&pdev->dev, sizeof(*pmap), GFP_KERNEL);
if (!pmap)
return -ENOMEM;
pmap->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pmap->regs))
return PTR_ERR(pmap->regs);
pins = devm_kcalloc(&pdev->dev, PINS_COUNT, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
pin_names = devm_kcalloc(&pdev->dev, PINS_COUNT, name_len,
GFP_KERNEL);
if (!pin_names)
return -ENOMEM;
for (i = 0; i < PIN_COLLECTIONS; i++) {
for (j = 0; j < PINS_PER_COLLECTION; j++) {
int pin_id = i*PINS_PER_COLLECTION + j;
char *name = &pin_names[pin_id * name_len];
snprintf(name, name_len, "GP_%c%c", 'A'+i, '0'+j);
pins[pin_id].number = pin_id;
pins[pin_id].name = name;
pmap->pin_names[pin_id] = name;
}
}
pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
if (!pctl_desc)
return -ENOMEM;
pctl_desc->name = DRIVER_NAME,
pctl_desc->owner = THIS_MODULE,
pctl_desc->pctlops = &dc_pinctrl_ops,
pctl_desc->pmxops = &dc_pmxops,
pctl_desc->npins = PINS_COUNT;
pctl_desc->pins = pins;
pmap->desc = pctl_desc;
pmap->dev = &pdev->dev;
pmap->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, pmap);
if (IS_ERR(pmap->pctl)) {
dev_err(&pdev->dev, "pinctrl driver registration failed\n");
return PTR_ERR(pmap->pctl);
}
return dc_gpiochip_add(pmap);
}
static const struct of_device_id dc_pinctrl_ids[] = {
{ .compatible = "cnxt,cx92755-pinctrl" },
{ /* sentinel */ }
};
static struct platform_driver dc_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = dc_pinctrl_ids,
.suppress_bind_attrs = true,
},
.probe = dc_pinctrl_probe,
};
builtin_platform_driver(dc_pinctrl_driver);
|
linux-master
|
drivers/pinctrl/pinctrl-digicolor.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Ingenic SoCs pinctrl driver
*
* Copyright (c) 2017 Paul Cercueil <[email protected]>
* Copyright (c) 2017, 2019 Paul Boddie <[email protected]>
* Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <[email protected]>
*/
#include <linux/compiler.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#define GPIO_PIN 0x00
#define GPIO_MSK 0x20
#define JZ4730_GPIO_DATA 0x00
#define JZ4730_GPIO_GPDIR 0x04
#define JZ4730_GPIO_GPPUR 0x0c
#define JZ4730_GPIO_GPALR 0x10
#define JZ4730_GPIO_GPAUR 0x14
#define JZ4730_GPIO_GPIDLR 0x18
#define JZ4730_GPIO_GPIDUR 0x1c
#define JZ4730_GPIO_GPIER 0x20
#define JZ4730_GPIO_GPIMR 0x24
#define JZ4730_GPIO_GPFR 0x28
#define JZ4740_GPIO_DATA 0x10
#define JZ4740_GPIO_PULL_DIS 0x30
#define JZ4740_GPIO_FUNC 0x40
#define JZ4740_GPIO_SELECT 0x50
#define JZ4740_GPIO_DIR 0x60
#define JZ4740_GPIO_TRIG 0x70
#define JZ4740_GPIO_FLAG 0x80
#define JZ4770_GPIO_INT 0x10
#define JZ4770_GPIO_PAT1 0x30
#define JZ4770_GPIO_PAT0 0x40
#define JZ4770_GPIO_FLAG 0x50
#define JZ4770_GPIO_PEN 0x70
#define X1830_GPIO_PEL 0x110
#define X1830_GPIO_PEH 0x120
#define X1830_GPIO_SR 0x150
#define X1830_GPIO_SMT 0x160
#define X2000_GPIO_EDG 0x70
#define X2000_GPIO_PEPU 0x80
#define X2000_GPIO_PEPD 0x90
#define X2000_GPIO_SR 0xd0
#define X2000_GPIO_SMT 0xe0
#define REG_SET(x) ((x) + 0x4)
#define REG_CLEAR(x) ((x) + 0x8)
#define REG_PZ_BASE(x) ((x) * 7)
#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
#define GPIO_PULL_DIS 0
#define GPIO_PULL_UP 1
#define GPIO_PULL_DOWN 2
#define PINS_PER_GPIO_CHIP 32
#define JZ4730_PINS_PER_PAIRED_REG 16
#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \
{ \
name, \
id##_pins, \
ARRAY_SIZE(id##_pins), \
funcs, \
}
#define INGENIC_PIN_GROUP(name, id, func) \
INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
enum jz_version {
ID_JZ4730,
ID_JZ4740,
ID_JZ4725B,
ID_JZ4750,
ID_JZ4755,
ID_JZ4760,
ID_JZ4770,
ID_JZ4775,
ID_JZ4780,
ID_X1000,
ID_X1500,
ID_X1830,
ID_X2000,
ID_X2100,
};
struct ingenic_chip_info {
unsigned int num_chips;
unsigned int reg_offset;
enum jz_version version;
const struct group_desc *groups;
unsigned int num_groups;
const struct function_desc *functions;
unsigned int num_functions;
const u32 *pull_ups, *pull_downs;
const struct regmap_access_table *access_table;
};
struct ingenic_pinctrl {
struct device *dev;
struct regmap *map;
struct pinctrl_dev *pctl;
struct pinctrl_pin_desc *pdesc;
const struct ingenic_chip_info *info;
};
struct ingenic_gpio_chip {
struct ingenic_pinctrl *jzpc;
struct gpio_chip gc;
unsigned int irq, reg_base;
};
static const unsigned long enabled_socs =
IS_ENABLED(CONFIG_MACH_JZ4730) << ID_JZ4730 |
IS_ENABLED(CONFIG_MACH_JZ4740) << ID_JZ4740 |
IS_ENABLED(CONFIG_MACH_JZ4725B) << ID_JZ4725B |
IS_ENABLED(CONFIG_MACH_JZ4750) << ID_JZ4750 |
IS_ENABLED(CONFIG_MACH_JZ4755) << ID_JZ4755 |
IS_ENABLED(CONFIG_MACH_JZ4760) << ID_JZ4760 |
IS_ENABLED(CONFIG_MACH_JZ4770) << ID_JZ4770 |
IS_ENABLED(CONFIG_MACH_JZ4775) << ID_JZ4775 |
IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
static bool
is_soc_or_above(const struct ingenic_pinctrl *jzpc, enum jz_version version)
{
return (enabled_socs >> version) &&
(!(enabled_socs & GENMASK(version - 1, 0))
|| jzpc->info->version >= version);
}
static const u32 jz4730_pull_ups[4] = {
0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
};
static const u32 jz4730_pull_downs[4] = {
0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
};
static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
static int jz4730_lcd_8bit_pins[] = {
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x3a, 0x39, 0x38,
};
static int jz4730_lcd_16bit_pins[] = {
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
};
static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
static int jz4730_lcd_generic_pins[] = { 0x3b, };
static int jz4730_nand_cs1_pins[] = { 0x53, };
static int jz4730_nand_cs2_pins[] = { 0x54, };
static int jz4730_nand_cs3_pins[] = { 0x55, };
static int jz4730_nand_cs4_pins[] = { 0x56, };
static int jz4730_nand_cs5_pins[] = { 0x57, };
static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
static const struct group_desc jz4730_groups[] = {
INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
};
static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
static const char *jz4730_uart0_groups[] = { "uart0-data", };
static const char *jz4730_uart1_groups[] = { "uart1-data", };
static const char *jz4730_uart2_groups[] = { "uart2-data", };
static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4730_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
};
static const char *jz4730_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
};
static const char *jz4730_pwm0_groups[] = { "pwm0", };
static const char *jz4730_pwm1_groups[] = { "pwm1", };
static const struct function_desc jz4730_functions[] = {
{ "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
{ "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
{ "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
{ "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
{ "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
{ "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
{ "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
{ "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
{ "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
};
static const struct ingenic_chip_info jz4730_chip_info = {
.num_chips = 4,
.reg_offset = 0x30,
.version = ID_JZ4730,
.groups = jz4730_groups,
.num_groups = ARRAY_SIZE(jz4730_groups),
.functions = jz4730_functions,
.num_functions = ARRAY_SIZE(jz4730_functions),
.pull_ups = jz4730_pull_ups,
.pull_downs = jz4730_pull_downs,
};
static const u32 jz4740_pull_ups[4] = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
};
static const u32 jz4740_pull_downs[4] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
static int jz4740_lcd_8bit_pins[] = {
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x52, 0x53, 0x54,
};
static int jz4740_lcd_16bit_pins[] = {
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
};
static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
static int jz4740_lcd_generic_pins[] = { 0x55, };
static int jz4740_nand_cs1_pins[] = { 0x39, };
static int jz4740_nand_cs2_pins[] = { 0x3a, };
static int jz4740_nand_cs3_pins[] = { 0x3b, };
static int jz4740_nand_cs4_pins[] = { 0x3c, };
static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
static int jz4740_pwm_pwm0_pins[] = { 0x77, };
static int jz4740_pwm_pwm1_pins[] = { 0x78, };
static int jz4740_pwm_pwm2_pins[] = { 0x79, };
static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
static const struct group_desc jz4740_groups[] = {
INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
};
static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4740_uart1_groups[] = { "uart1-data", };
static const char *jz4740_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
};
static const char *jz4740_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
};
static const char *jz4740_pwm0_groups[] = { "pwm0", };
static const char *jz4740_pwm1_groups[] = { "pwm1", };
static const char *jz4740_pwm2_groups[] = { "pwm2", };
static const char *jz4740_pwm3_groups[] = { "pwm3", };
static const char *jz4740_pwm4_groups[] = { "pwm4", };
static const char *jz4740_pwm5_groups[] = { "pwm5", };
static const char *jz4740_pwm6_groups[] = { "pwm6", };
static const char *jz4740_pwm7_groups[] = { "pwm7", };
static const struct function_desc jz4740_functions[] = {
{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
{ "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
{ "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
{ "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
{ "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
{ "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
{ "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
{ "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
{ "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
{ "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
{ "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
{ "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
{ "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
};
static const struct ingenic_chip_info jz4740_chip_info = {
.num_chips = 4,
.reg_offset = 0x100,
.version = ID_JZ4740,
.groups = jz4740_groups,
.num_groups = ARRAY_SIZE(jz4740_groups),
.functions = jz4740_functions,
.num_functions = ARRAY_SIZE(jz4740_functions),
.pull_ups = jz4740_pull_ups,
.pull_downs = jz4740_pull_downs,
};
static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
static int jz4725b_lcd_8bit_pins[] = {
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x72, 0x73, 0x74,
};
static int jz4725b_lcd_16bit_pins[] = {
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
};
static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4725b_lcd_generic_pins[] = { 0x75, };
static int jz4725b_nand_cs1_pins[] = { 0x55, };
static int jz4725b_nand_cs2_pins[] = { 0x56, };
static int jz4725b_nand_cs3_pins[] = { 0x57, };
static int jz4725b_nand_cs4_pins[] = { 0x58, };
static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
static const struct group_desc jz4725b_groups[] = {
INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
jz4725b_mmc0_4bit_funcs),
INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
};
static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *jz4725b_uart_groups[] = { "uart-data", };
static const char *jz4725b_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4725b_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
"nand-cle-ale", "nand-fre-fwe",
};
static const char *jz4725b_pwm0_groups[] = { "pwm0", };
static const char *jz4725b_pwm1_groups[] = { "pwm1", };
static const char *jz4725b_pwm2_groups[] = { "pwm2", };
static const char *jz4725b_pwm3_groups[] = { "pwm3", };
static const char *jz4725b_pwm4_groups[] = { "pwm4", };
static const char *jz4725b_pwm5_groups[] = { "pwm5", };
static const struct function_desc jz4725b_functions[] = {
{ "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
{ "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
{ "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
{ "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
{ "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
{ "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
{ "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
{ "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
{ "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
{ "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
{ "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
};
static const struct ingenic_chip_info jz4725b_chip_info = {
.num_chips = 4,
.reg_offset = 0x100,
.version = ID_JZ4725B,
.groups = jz4725b_groups,
.num_groups = ARRAY_SIZE(jz4725b_groups),
.functions = jz4725b_functions,
.num_functions = ARRAY_SIZE(jz4725b_functions),
.pull_ups = jz4740_pull_ups,
.pull_downs = jz4740_pull_downs,
};
static const u32 jz4750_pull_ups[6] = {
0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
};
static const u32 jz4750_pull_downs[6] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
static int jz4750_cim_pins[] = {
0x89, 0x8b, 0x8a, 0x88,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
};
static int jz4750_lcd_8bit_pins[] = {
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x72, 0x73, 0x74,
};
static int jz4750_lcd_16bit_pins[] = {
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
};
static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4750_lcd_generic_pins[] = { 0x75, };
static int jz4750_nand_cs1_pins[] = { 0x55, };
static int jz4750_nand_cs2_pins[] = { 0x56, };
static int jz4750_nand_cs3_pins[] = { 0x57, };
static int jz4750_nand_cs4_pins[] = { 0x58, };
static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
static int jz4750_pwm_pwm0_pins[] = { 0x94, };
static int jz4750_pwm_pwm1_pins[] = { 0x95, };
static int jz4750_pwm_pwm2_pins[] = { 0x96, };
static int jz4750_pwm_pwm3_pins[] = { 0x97, };
static int jz4750_pwm_pwm4_pins[] = { 0x98, };
static int jz4750_pwm_pwm5_pins[] = { 0x99, };
static const struct group_desc jz4750_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
};
static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4750_uart2_groups[] = { "uart2-data", };
static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4750_mmc0_groups[] = {
"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
};
static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *jz4750_i2c_groups[] = { "i2c-data", };
static const char *jz4750_cim_groups[] = { "cim-data", };
static const char *jz4750_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4750_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
};
static const char *jz4750_pwm0_groups[] = { "pwm0", };
static const char *jz4750_pwm1_groups[] = { "pwm1", };
static const char *jz4750_pwm2_groups[] = { "pwm2", };
static const char *jz4750_pwm3_groups[] = { "pwm3", };
static const char *jz4750_pwm4_groups[] = { "pwm4", };
static const char *jz4750_pwm5_groups[] = { "pwm5", };
static const struct function_desc jz4750_functions[] = {
{ "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
{ "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
{ "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
{ "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
{ "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
{ "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
{ "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
{ "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
{ "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
{ "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
{ "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
{ "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
{ "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
{ "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
{ "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
{ "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
};
static const struct ingenic_chip_info jz4750_chip_info = {
.num_chips = 6,
.reg_offset = 0x100,
.version = ID_JZ4750,
.groups = jz4750_groups,
.num_groups = ARRAY_SIZE(jz4750_groups),
.functions = jz4750_functions,
.num_functions = ARRAY_SIZE(jz4750_functions),
.pull_ups = jz4750_pull_ups,
.pull_downs = jz4750_pull_downs,
};
static const u32 jz4755_pull_ups[6] = {
0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
};
static const u32 jz4755_pull_downs[6] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
static int jz4755_uart2_data_pins[] = { 0x9f, };
static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
static int jz4755_cim_pins[] = {
0x89, 0x8b, 0x8a, 0x88,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
};
static int jz4755_lcd_8bit_pins[] = {
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x72, 0x73, 0x74,
};
static int jz4755_lcd_16bit_pins[] = {
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
};
static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
static int jz4755_lcd_generic_pins[] = { 0x75, };
static int jz4755_nand_cs1_pins[] = { 0x55, };
static int jz4755_nand_cs2_pins[] = { 0x56, };
static int jz4755_nand_cs3_pins[] = { 0x57, };
static int jz4755_nand_cs4_pins[] = { 0x58, };
static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
static int jz4755_pwm_pwm0_pins[] = { 0x94, };
static int jz4755_pwm_pwm1_pins[] = { 0xab, };
static int jz4755_pwm_pwm2_pins[] = { 0x96, };
static int jz4755_pwm_pwm3_pins[] = { 0x97, };
static int jz4755_pwm_pwm4_pins[] = { 0x98, };
static int jz4755_pwm_pwm5_pins[] = { 0x99, };
static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
static const struct group_desc jz4755_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1),
INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
jz4755_mmc0_1bit_funcs),
INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
jz4755_mmc0_4bit_funcs),
INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
jz4755_lcd_24bit_funcs),
INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
};
static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4755_uart1_groups[] = { "uart1-data", };
static const char *jz4755_uart2_groups[] = { "uart2-data", };
static const char *jz4755_ssi_groups[] = {
"ssi-dt-b", "ssi-dt-f",
"ssi-dr-b", "ssi-dr-f",
"ssi-clk-b", "ssi-clk-f",
"ssi-gpc-b", "ssi-gpc-f",
"ssi-ce0-b", "ssi-ce0-f",
"ssi-ce1-b", "ssi-ce1-f",
};
static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *jz4755_i2c_groups[] = { "i2c-data", };
static const char *jz4755_cim_groups[] = { "cim-data", };
static const char *jz4755_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4755_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
};
static const char *jz4755_pwm0_groups[] = { "pwm0", };
static const char *jz4755_pwm1_groups[] = { "pwm1", };
static const char *jz4755_pwm2_groups[] = { "pwm2", };
static const char *jz4755_pwm3_groups[] = { "pwm3", };
static const char *jz4755_pwm4_groups[] = { "pwm4", };
static const char *jz4755_pwm5_groups[] = { "pwm5", };
static const struct function_desc jz4755_functions[] = {
{ "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
{ "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
{ "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
{ "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
{ "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
{ "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
{ "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
{ "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
{ "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
{ "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
{ "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
{ "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
{ "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
{ "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
{ "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
{ "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
};
static const struct ingenic_chip_info jz4755_chip_info = {
.num_chips = 6,
.reg_offset = 0x100,
.version = ID_JZ4755,
.groups = jz4755_groups,
.num_groups = ARRAY_SIZE(jz4755_groups),
.functions = jz4755_functions,
.num_functions = ARRAY_SIZE(jz4755_functions),
.pull_ups = jz4755_pull_ups,
.pull_downs = jz4755_pull_downs,
};
static const u32 jz4760_pull_ups[6] = {
0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
};
static const u32 jz4760_pull_downs[6] = {
0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
};
static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int jz4760_nemc_16bit_data_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
static int jz4760_nemc_wait_pins[] = { 0x1b, };
static int jz4760_nemc_cs1_pins[] = { 0x15, };
static int jz4760_nemc_cs2_pins[] = { 0x16, };
static int jz4760_nemc_cs3_pins[] = { 0x17, };
static int jz4760_nemc_cs4_pins[] = { 0x18, };
static int jz4760_nemc_cs5_pins[] = { 0x19, };
static int jz4760_nemc_cs6_pins[] = { 0x1a, };
static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
static int jz4760_cim_pins[] = {
0x26, 0x27, 0x28, 0x29,
0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
};
static int jz4760_lcd_8bit_pins[] = {
0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
0x4d, 0x52, 0x53,
};
static int jz4760_lcd_16bit_pins[] = {
0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
};
static int jz4760_lcd_18bit_pins[] = {
0x5a, 0x5b,
};
static int jz4760_lcd_24bit_pins[] = {
0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
};
static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
static int jz4760_lcd_generic_pins[] = { 0x49, };
static int jz4760_pwm_pwm0_pins[] = { 0x80, };
static int jz4760_pwm_pwm1_pins[] = { 0x81, };
static int jz4760_pwm_pwm2_pins[] = { 0x82, };
static int jz4760_pwm_pwm3_pins[] = { 0x83, };
static int jz4760_pwm_pwm4_pins[] = { 0x84, };
static int jz4760_pwm_pwm5_pins[] = { 0x85, };
static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
static int jz4760_otg_pins[] = { 0x8a, };
static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
static const struct group_desc jz4760_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
jz4760_uart3_data_funcs),
INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
jz4760_mmc0_1bit_a_funcs),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
};
static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4760_ssi0_groups[] = {
"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4760_ssi1_groups[] = {
"ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
"ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
"ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4760_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a",
"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
};
static const char *jz4760_mmc1_groups[] = {
"mmc1-1bit-d", "mmc1-4bit-d",
"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
};
static const char *jz4760_mmc2_groups[] = {
"mmc2-1bit-b", "mmc2-4bit-b",
"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
};
static const char *jz4760_nemc_groups[] = {
"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
};
static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
static const char *jz4760_cim_groups[] = { "cim-data", };
static const char *jz4760_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4760_pwm0_groups[] = { "pwm0", };
static const char *jz4760_pwm1_groups[] = { "pwm1", };
static const char *jz4760_pwm2_groups[] = { "pwm2", };
static const char *jz4760_pwm3_groups[] = { "pwm3", };
static const char *jz4760_pwm4_groups[] = { "pwm4", };
static const char *jz4760_pwm5_groups[] = { "pwm5", };
static const char *jz4760_pwm6_groups[] = { "pwm6", };
static const char *jz4760_pwm7_groups[] = { "pwm7", };
static const char *jz4760_otg_groups[] = { "otg-vbus", };
static const struct function_desc jz4760_functions[] = {
{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
{ "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
{ "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
{ "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
{ "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
{ "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
{ "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
{ "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
{ "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
{ "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
{ "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
{ "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
{ "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
{ "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
{ "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
{ "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
{ "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
{ "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
{ "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
{ "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
{ "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
{ "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
{ "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
{ "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
{ "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
};
static const struct ingenic_chip_info jz4760_chip_info = {
.num_chips = 6,
.reg_offset = 0x100,
.version = ID_JZ4760,
.groups = jz4760_groups,
.num_groups = ARRAY_SIZE(jz4760_groups),
.functions = jz4760_functions,
.num_functions = ARRAY_SIZE(jz4760_functions),
.pull_ups = jz4760_pull_ups,
.pull_downs = jz4760_pull_downs,
};
static const u32 jz4770_pull_ups[6] = {
0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
};
static const u32 jz4770_pull_downs[6] = {
0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
};
static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4770_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int jz4770_nemc_16bit_data_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
static int jz4770_nemc_wait_pins[] = { 0x1b, };
static int jz4770_nemc_cs1_pins[] = { 0x15, };
static int jz4770_nemc_cs2_pins[] = { 0x16, };
static int jz4770_nemc_cs3_pins[] = { 0x17, };
static int jz4770_nemc_cs4_pins[] = { 0x18, };
static int jz4770_nemc_cs5_pins[] = { 0x19, };
static int jz4770_nemc_cs6_pins[] = { 0x1a, };
static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
static int jz4770_cim_8bit_pins[] = {
0x26, 0x27, 0x28, 0x29,
0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
};
static int jz4770_cim_12bit_pins[] = {
0x32, 0x33, 0xb0, 0xb1,
};
static int jz4770_lcd_8bit_pins[] = {
0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
0x48, 0x52, 0x53,
};
static int jz4770_lcd_16bit_pins[] = {
0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
};
static int jz4770_lcd_18bit_pins[] = {
0x5a, 0x5b,
};
static int jz4770_lcd_24bit_pins[] = {
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b,
};
static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
static int jz4770_lcd_generic_pins[] = { 0x49, };
static int jz4770_pwm_pwm0_pins[] = { 0x80, };
static int jz4770_pwm_pwm1_pins[] = { 0x81, };
static int jz4770_pwm_pwm2_pins[] = { 0x82, };
static int jz4770_pwm_pwm3_pins[] = { 0x83, };
static int jz4770_pwm_pwm4_pins[] = { 0x84, };
static int jz4770_pwm_pwm5_pins[] = { 0x85, };
static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
static int jz4770_mac_rmii_pins[] = {
0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
};
static int jz4770_mac_mii_pins[] = {
0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
};
static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
jz4760_uart3_data_funcs),
INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
jz4760_mmc0_1bit_a_funcs),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
};
static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4770_ssi0_groups[] = {
"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4770_ssi1_groups[] = {
"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4770_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a",
"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
};
static const char *jz4770_mmc1_groups[] = {
"mmc1-1bit-d", "mmc1-4bit-d",
"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
};
static const char *jz4770_mmc2_groups[] = {
"mmc2-1bit-b", "mmc2-4bit-b",
"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
};
static const char *jz4770_nemc_groups[] = {
"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
};
static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
static const char *jz4770_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4770_pwm0_groups[] = { "pwm0", };
static const char *jz4770_pwm1_groups[] = { "pwm1", };
static const char *jz4770_pwm2_groups[] = { "pwm2", };
static const char *jz4770_pwm3_groups[] = { "pwm3", };
static const char *jz4770_pwm4_groups[] = { "pwm4", };
static const char *jz4770_pwm5_groups[] = { "pwm5", };
static const char *jz4770_pwm6_groups[] = { "pwm6", };
static const char *jz4770_pwm7_groups[] = { "pwm7", };
static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
static const struct function_desc jz4770_functions[] = {
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
{ "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
{ "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
};
static const struct ingenic_chip_info jz4770_chip_info = {
.num_chips = 6,
.reg_offset = 0x100,
.version = ID_JZ4770,
.groups = jz4770_groups,
.num_groups = ARRAY_SIZE(jz4770_groups),
.functions = jz4770_functions,
.num_functions = ARRAY_SIZE(jz4770_functions),
.pull_ups = jz4770_pull_ups,
.pull_downs = jz4770_pull_downs,
};
static const u32 jz4775_pull_ups[7] = {
0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
};
static const u32 jz4775_pull_downs[7] = {
0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
};
static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
static int jz4775_ssi_dt_a_pins[] = { 0x13, };
static int jz4775_ssi_dt_d_pins[] = { 0x75, };
static int jz4775_ssi_dr_a_pins[] = { 0x14, };
static int jz4775_ssi_dr_d_pins[] = { 0x74, };
static int jz4775_ssi_clk_a_pins[] = { 0x12, };
static int jz4775_ssi_clk_d_pins[] = { 0x78, };
static int jz4775_ssi_gpc_pins[] = { 0x76, };
static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
static int jz4775_ssi_ce1_pins[] = { 0x77, };
static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4775_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int jz4775_nemc_16bit_data_pins[] = {
0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
};
static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
static int jz4775_nemc_wait_pins[] = { 0x1b, };
static int jz4775_nemc_cs1_pins[] = { 0x15, };
static int jz4775_nemc_cs2_pins[] = { 0x16, };
static int jz4775_nemc_cs3_pins[] = { 0x17, };
static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
static int jz4775_i2s_sysclk_pins[] = { 0x83, };
static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
static int jz4775_cim_pins[] = {
0x26, 0x27, 0x28, 0x29,
0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
};
static int jz4775_lcd_8bit_pins[] = {
0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
0x48, 0x52, 0x53,
};
static int jz4775_lcd_16bit_pins[] = {
0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
};
static int jz4775_lcd_18bit_pins[] = {
0x5a, 0x5b,
};
static int jz4775_lcd_24bit_pins[] = {
0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
};
static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
static int jz4775_lcd_generic_pins[] = { 0x49, };
static int jz4775_pwm_pwm0_pins[] = { 0x80, };
static int jz4775_pwm_pwm1_pins[] = { 0x81, };
static int jz4775_pwm_pwm2_pins[] = { 0x82, };
static int jz4775_pwm_pwm3_pins[] = { 0x83, };
static int jz4775_mac_rmii_pins[] = {
0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
};
static int jz4775_mac_mii_pins[] = {
0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
};
static int jz4775_mac_rgmii_pins[] = {
0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
0xad, 0xae, 0xa7, 0xa6,
};
static int jz4775_mac_gmii_pins[] = {
0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
0xa8, 0x28, 0x24, 0xaf,
};
static int jz4775_otg_pins[] = { 0x8a, };
static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
static u8 jz4775_mac_rgmii_funcs[] = {
0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
0, 0, 0, 0,
};
static u8 jz4775_mac_gmii_funcs[] = {
1, 1, 1, 1, 1, 1, 1, 1,
0, 1, 1, 0,
};
static const struct group_desc jz4775_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
jz4775_uart3_data_funcs),
INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
jz4775_mac_mii_funcs),
INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
jz4775_mac_rgmii_funcs),
INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
jz4775_mac_gmii_funcs),
INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
};
static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
static const char *jz4775_uart3_groups[] = { "uart3-data", };
static const char *jz4775_ssi_groups[] = {
"ssi-dt-a", "ssi-dt-d",
"ssi-dr-a", "ssi-dr-d",
"ssi-clk-a", "ssi-clk-d",
"ssi-gpc",
"ssi-ce0-a", "ssi-ce0-d",
"ssi-ce1",
};
static const char *jz4775_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
"mmc0-1bit-e", "mmc0-4bit-e",
};
static const char *jz4775_mmc1_groups[] = {
"mmc1-1bit-d", "mmc1-4bit-d",
"mmc1-1bit-e", "mmc1-4bit-e",
};
static const char *jz4775_mmc2_groups[] = {
"mmc2-1bit-b", "mmc2-4bit-b",
"mmc2-1bit-e", "mmc2-4bit-e",
};
static const char *jz4775_nemc_groups[] = {
"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
};
static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
static const char *jz4775_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *jz4775_dmic_groups[] = { "dmic", };
static const char *jz4775_cim_groups[] = { "cim-data", };
static const char *jz4775_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
"lcd-special", "lcd-generic",
};
static const char *jz4775_pwm0_groups[] = { "pwm0", };
static const char *jz4775_pwm1_groups[] = { "pwm1", };
static const char *jz4775_pwm2_groups[] = { "pwm2", };
static const char *jz4775_pwm3_groups[] = { "pwm3", };
static const char *jz4775_mac_groups[] = {
"mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
};
static const char *jz4775_otg_groups[] = { "otg-vbus", };
static const struct function_desc jz4775_functions[] = {
{ "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
{ "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
{ "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
{ "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
{ "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
{ "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
{ "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
{ "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
{ "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
{ "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
{ "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
{ "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
{ "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
{ "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
{ "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
{ "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
{ "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
{ "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
{ "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
{ "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
{ "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
{ "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
{ "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
{ "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
{ "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
};
static const struct ingenic_chip_info jz4775_chip_info = {
.num_chips = 7,
.reg_offset = 0x100,
.version = ID_JZ4775,
.groups = jz4775_groups,
.num_groups = ARRAY_SIZE(jz4775_groups),
.functions = jz4775_functions,
.num_functions = ARRAY_SIZE(jz4775_functions),
.pull_ups = jz4775_pull_ups,
.pull_downs = jz4775_pull_downs,
};
static const u32 jz4780_pull_ups[6] = {
0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
};
static const u32 jz4780_pull_downs[6] = {
0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
};
static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
static int jz4780_i2s_data_tx_pins[] = { 0x87, };
static int jz4780_i2s_data_rx_pins[] = { 0x86, };
static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
static int jz4780_i2s_sysclk_pins[] = { 0x85, };
static int jz4780_dmic_pins[] = { 0x32, 0x33, };
static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
static const struct group_desc jz4780_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
jz4760_uart3_data_funcs),
INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
jz4760_mmc0_1bit_a_funcs),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
jz4780_i2s_clk_txrx_funcs),
INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
};
static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4780_uart4_groups[] = { "uart4-data", };
static const char *jz4780_ssi0_groups[] = {
"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4780_ssi1_groups[] = {
"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4780_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
"mmc0-1bit-e", "mmc0-4bit-e",
};
static const char *jz4780_mmc1_groups[] = {
"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
};
static const char *jz4780_mmc2_groups[] = {
"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
};
static const char *jz4780_nemc_groups[] = {
"nemc-data", "nemc-cle-ale", "nemc-addr",
"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
};
static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
static const char *jz4780_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
};
static const char *jz4780_dmic_groups[] = { "dmic", };
static const char *jz4780_cim_groups[] = { "cim-data", };
static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
static const struct function_desc jz4780_functions[] = {
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
{ "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
{ "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
{ "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
{ "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
{ "hdmi-ddc", jz4780_hdmi_ddc_groups,
ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
};
static const struct ingenic_chip_info jz4780_chip_info = {
.num_chips = 6,
.reg_offset = 0x100,
.version = ID_JZ4780,
.groups = jz4780_groups,
.num_groups = ARRAY_SIZE(jz4780_groups),
.functions = jz4780_functions,
.num_functions = ARRAY_SIZE(jz4780_functions),
.pull_ups = jz4780_pull_ups,
.pull_downs = jz4780_pull_downs,
};
static const u32 x1000_pull_ups[4] = {
0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
};
static const u32 x1000_pull_downs[4] = {
0x00000000, 0x02000000, 0x02000000, 0x00000000,
};
static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
static int x1000_sfc_clk_pins[] = { 0x1a, };
static int x1000_sfc_ce_pins[] = { 0x1b, };
static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
static int x1000_ssi_dt_d_pins[] = { 0x62, };
static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
static int x1000_ssi_dr_d_pins[] = { 0x63, };
static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
static int x1000_ssi_clk_d_pins[] = { 0x60, };
static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
static int x1000_ssi_ce0_d_pins[] = { 0x61, };
static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
static int x1000_emc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int x1000_emc_16bit_data_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int x1000_emc_addr_pins[] = {
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
};
static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
static int x1000_emc_wait_pins[] = { 0x34, };
static int x1000_emc_cs1_pins[] = { 0x32, };
static int x1000_emc_cs2_pins[] = { 0x33, };
static int x1000_i2c0_pins[] = { 0x38, 0x37, };
static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1000_i2c2_pins[] = { 0x61, 0x60, };
static int x1000_i2s_data_tx_pins[] = { 0x24, };
static int x1000_i2s_data_rx_pins[] = { 0x23, };
static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1000_i2s_sysclk_pins[] = { 0x20, };
static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
static int x1000_dmic_if1_pins[] = { 0x25, };
static int x1000_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
};
static int x1000_lcd_8bit_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x30, 0x31, 0x32, 0x33, 0x34,
};
static int x1000_lcd_16bit_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int x1000_pwm_pwm0_pins[] = { 0x59, };
static int x1000_pwm_pwm1_pins[] = { 0x5a, };
static int x1000_pwm_pwm2_pins[] = { 0x5b, };
static int x1000_pwm_pwm3_pins[] = { 0x26, };
static int x1000_pwm_pwm4_pins[] = { 0x58, };
static int x1000_mac_pins[] = {
0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
};
static const struct group_desc x1000_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
INGENIC_PIN_GROUP("mac", x1000_mac, 1),
};
static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1000_uart1_groups[] = {
"uart1-data-a", "uart1-data-d", "uart1-hwflow",
};
static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
static const char *x1000_ssi_groups[] = {
"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
"ssi-gpc-a-20", "ssi-gpc-a-31",
"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
"ssi-ce1-a-21", "ssi-ce1-a-30",
};
static const char *x1000_mmc0_groups[] = {
"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
};
static const char *x1000_mmc1_groups[] = {
"mmc1-1bit", "mmc1-4bit",
};
static const char *x1000_emc_groups[] = {
"emc-8bit-data", "emc-16bit-data",
"emc-addr", "emc-rd-we", "emc-wait",
};
static const char *x1000_cs1_groups[] = { "emc-cs1", };
static const char *x1000_cs2_groups[] = { "emc-cs2", };
static const char *x1000_i2c0_groups[] = { "i2c0-data", };
static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1000_i2c2_groups[] = { "i2c2-data", };
static const char *x1000_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1000_cim_groups[] = { "cim-data", };
static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
static const char *x1000_pwm0_groups[] = { "pwm0", };
static const char *x1000_pwm1_groups[] = { "pwm1", };
static const char *x1000_pwm2_groups[] = { "pwm2", };
static const char *x1000_pwm3_groups[] = { "pwm3", };
static const char *x1000_pwm4_groups[] = { "pwm4", };
static const char *x1000_mac_groups[] = { "mac", };
static const struct function_desc x1000_functions[] = {
{ "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
{ "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
{ "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
{ "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
{ "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
{ "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
{ "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
{ "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
{ "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
{ "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
{ "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
{ "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
{ "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
{ "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
{ "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
};
static const struct regmap_range x1000_access_ranges[] = {
regmap_reg_range(0x000, 0x400 - 4),
regmap_reg_range(0x700, 0x800 - 4),
};
/* shared with X1500 */
static const struct regmap_access_table x1000_access_table = {
.yes_ranges = x1000_access_ranges,
.n_yes_ranges = ARRAY_SIZE(x1000_access_ranges),
};
static const struct ingenic_chip_info x1000_chip_info = {
.num_chips = 4,
.reg_offset = 0x100,
.version = ID_X1000,
.groups = x1000_groups,
.num_groups = ARRAY_SIZE(x1000_groups),
.functions = x1000_functions,
.num_functions = ARRAY_SIZE(x1000_functions),
.pull_ups = x1000_pull_ups,
.pull_downs = x1000_pull_downs,
.access_table = &x1000_access_table,
};
static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
static int x1500_i2c0_pins[] = { 0x38, 0x37, };
static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1500_i2c2_pins[] = { 0x61, 0x60, };
static int x1500_i2s_data_tx_pins[] = { 0x24, };
static int x1500_i2s_data_rx_pins[] = { 0x23, };
static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1500_i2s_sysclk_pins[] = { 0x20, };
static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
static int x1500_dmic_if1_pins[] = { 0x25, };
static int x1500_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
};
static int x1500_pwm_pwm0_pins[] = { 0x59, };
static int x1500_pwm_pwm1_pins[] = { 0x5a, };
static int x1500_pwm_pwm2_pins[] = { 0x5b, };
static int x1500_pwm_pwm3_pins[] = { 0x26, };
static int x1500_pwm_pwm4_pins[] = { 0x58, };
static const struct group_desc x1500_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
};
static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1500_uart1_groups[] = {
"uart1-data-a", "uart1-data-d", "uart1-hwflow",
};
static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
static const char *x1500_i2c0_groups[] = { "i2c0-data", };
static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1500_i2c2_groups[] = { "i2c2-data", };
static const char *x1500_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1500_cim_groups[] = { "cim-data", };
static const char *x1500_pwm0_groups[] = { "pwm0", };
static const char *x1500_pwm1_groups[] = { "pwm1", };
static const char *x1500_pwm2_groups[] = { "pwm2", };
static const char *x1500_pwm3_groups[] = { "pwm3", };
static const char *x1500_pwm4_groups[] = { "pwm4", };
static const struct function_desc x1500_functions[] = {
{ "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
{ "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
{ "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
{ "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
{ "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
{ "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
{ "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
{ "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
{ "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
{ "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
{ "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
{ "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
{ "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
{ "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
{ "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
};
static const struct ingenic_chip_info x1500_chip_info = {
.num_chips = 4,
.reg_offset = 0x100,
.version = ID_X1500,
.groups = x1500_groups,
.num_groups = ARRAY_SIZE(x1500_groups),
.functions = x1500_functions,
.num_functions = ARRAY_SIZE(x1500_functions),
.pull_ups = x1000_pull_ups,
.pull_downs = x1000_pull_downs,
.access_table = &x1000_access_table,
};
static const u32 x1830_pull_ups[4] = {
0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
};
static const u32 x1830_pull_downs[4] = {
0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
};
static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
static int x1830_sfc_clk_pins[] = { 0x1b, };
static int x1830_sfc_ce_pins[] = { 0x1c, };
static int x1830_ssi0_dt_pins[] = { 0x4c, };
static int x1830_ssi0_dr_pins[] = { 0x4b, };
static int x1830_ssi0_clk_pins[] = { 0x4f, };
static int x1830_ssi0_gpc_pins[] = { 0x4d, };
static int x1830_ssi0_ce0_pins[] = { 0x50, };
static int x1830_ssi0_ce1_pins[] = { 0x4e, };
static int x1830_ssi1_dt_c_pins[] = { 0x53, };
static int x1830_ssi1_dt_d_pins[] = { 0x62, };
static int x1830_ssi1_dr_c_pins[] = { 0x54, };
static int x1830_ssi1_dr_d_pins[] = { 0x63, };
static int x1830_ssi1_clk_c_pins[] = { 0x57, };
static int x1830_ssi1_clk_d_pins[] = { 0x66, };
static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
static int x1830_i2s_data_tx_pins[] = { 0x53, };
static int x1830_i2s_data_rx_pins[] = { 0x54, };
static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
static int x1830_i2s_sysclk_pins[] = { 0x57, };
static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
static int x1830_dmic_if1_pins[] = { 0x5a, };
static int x1830_lcd_tft_8bit_pins[] = {
0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x73, 0x72, 0x69,
};
static int x1830_lcd_tft_24bit_pins[] = {
0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
};
static int x1830_lcd_slcd_8bit_pins[] = {
0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
0x69, 0x72, 0x73, 0x7b, 0x7a,
};
static int x1830_lcd_slcd_16bit_pins[] = {
0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
};
static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
static int x1830_mac_pins[] = {
0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
};
static const struct group_desc x1830_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
INGENIC_PIN_GROUP("mac", x1830_mac, 0),
};
static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1830_uart1_groups[] = { "uart1-data", };
static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
static const char *x1830_ssi0_groups[] = {
"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
};
static const char *x1830_ssi1_groups[] = {
"ssi1-dt-c", "ssi1-dt-d",
"ssi1-dr-c", "ssi1-dr-d",
"ssi1-clk-c", "ssi1-clk-d",
"ssi1-gpc-c", "ssi1-gpc-d",
"ssi1-ce0-c", "ssi1-ce0-d",
"ssi1-ce1-c", "ssi1-ce1-d",
};
static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *x1830_i2c0_groups[] = { "i2c0-data", };
static const char *x1830_i2c1_groups[] = { "i2c1-data", };
static const char *x1830_i2c2_groups[] = { "i2c2-data", };
static const char *x1830_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
};
static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
static const char *x1830_lcd_groups[] = {
"lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
};
static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
static const char *x1830_mac_groups[] = { "mac", };
static const struct function_desc x1830_functions[] = {
{ "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
{ "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
{ "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
{ "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
{ "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
{ "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
{ "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
{ "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
{ "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
{ "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
{ "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
{ "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
{ "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
{ "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
{ "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
{ "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
{ "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
{ "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
{ "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
{ "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
{ "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
{ "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
};
static const struct regmap_range x1830_access_ranges[] = {
regmap_reg_range(0x0000, 0x4000 - 4),
regmap_reg_range(0x7000, 0x8000 - 4),
};
static const struct regmap_access_table x1830_access_table = {
.yes_ranges = x1830_access_ranges,
.n_yes_ranges = ARRAY_SIZE(x1830_access_ranges),
};
static const struct ingenic_chip_info x1830_chip_info = {
.num_chips = 4,
.reg_offset = 0x1000,
.version = ID_X1830,
.groups = x1830_groups,
.num_groups = ARRAY_SIZE(x1830_groups),
.functions = x1830_functions,
.num_functions = ARRAY_SIZE(x1830_functions),
.pull_ups = x1830_pull_ups,
.pull_downs = x1830_pull_downs,
.access_table = &x1830_access_table,
};
static const u32 x2000_pull_ups[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
};
static const u32 x2000_pull_downs[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
};
static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
static int x2000_sfc_clk_d_pins[] = { 0x71, };
static int x2000_sfc_clk_e_pins[] = { 0x90, };
static int x2000_sfc_ce_d_pins[] = { 0x72, };
static int x2000_sfc_ce_e_pins[] = { 0x91, };
static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
static int x2000_ssi0_dt_d_pins[] = { 0x69, };
static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
static int x2000_ssi0_clk_d_pins[] = { 0x68, };
static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
static int x2000_ssi1_dt_d_pins[] = { 0x72, };
static int x2000_ssi1_dt_e_pins[] = { 0x91, };
static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
static int x2000_ssi1_dr_d_pins[] = { 0x73, };
static int x2000_ssi1_dr_e_pins[] = { 0x92, };
static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
static int x2000_ssi1_clk_d_pins[] = { 0x71, };
static int x2000_ssi1_clk_e_pins[] = { 0x90, };
static int x2000_ssi1_ce_c_pins[] = { 0x49, };
static int x2000_ssi1_ce_d_pins[] = { 0x76, };
static int x2000_ssi1_ce_e_pins[] = { 0x95, };
static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
static int x2000_emc_8bit_data_pins[] = {
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
};
static int x2000_emc_16bit_data_pins[] = {
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
};
static int x2000_emc_addr_pins[] = {
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c,
};
static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
static int x2000_emc_wait_pins[] = { 0x2f, };
static int x2000_emc_cs1_pins[] = { 0x57, };
static int x2000_emc_cs2_pins[] = { 0x58, };
static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
static int x2000_i2s1_data_tx_pins[] = { 0x47, };
static int x2000_i2s1_data_rx_pins[] = { 0x44, };
static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
static int x2000_dmic_if1_pins[] = { 0x56, };
static int x2000_dmic_if2_pins[] = { 0x57, };
static int x2000_dmic_if3_pins[] = { 0x58, };
static int x2000_cim_8bit_pins[] = {
0x0e, 0x0c, 0x0d, 0x4f,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
static int x2000_lcd_tft_8bit_pins[] = {
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x38, 0x3a, 0x39, 0x3b,
};
static int x2000_lcd_tft_16bit_pins[] = {
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
};
static int x2000_lcd_tft_18bit_pins[] = {
0x30, 0x31,
};
static int x2000_lcd_tft_24bit_pins[] = {
0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
};
static int x2000_lcd_slcd_8bit_pins[] = {
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x3a, 0x38, 0x3b, 0x30, 0x39,
};
static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
static int x2000_pwm_pwm8_pins[] = { 0x48, };
static int x2000_pwm_pwm9_pins[] = { 0x49, };
static int x2000_pwm_pwm10_pins[] = { 0x4a, };
static int x2000_pwm_pwm11_pins[] = { 0x4b, };
static int x2000_pwm_pwm12_pins[] = { 0x4c, };
static int x2000_pwm_pwm13_pins[] = { 0x4d, };
static int x2000_pwm_pwm14_pins[] = { 0x4e, };
static int x2000_pwm_pwm15_pins[] = { 0x4f, };
static int x2000_mac0_rmii_pins[] = {
0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
};
static int x2000_mac0_rgmii_pins[] = {
0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
0x4c, 0x4d, 0x4f, 0x4e, 0x41,
};
static int x2000_mac1_rmii_pins[] = {
0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
};
static int x2000_mac1_rgmii_pins[] = {
0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
0x33, 0x34, 0x36, 0x35, 0x37,
};
static int x2000_otg_pins[] = { 0x96, };
static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
static const struct group_desc x2000_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
x2000_cim_8bit_funcs),
INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
};
static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *x2000_uart2_groups[] = { "uart2-data", };
static const char *x2000_uart3_groups[] = {
"uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
};
static const char *x2000_uart4_groups[] = {
"uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
};
static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
static const char *x2000_uart8_groups[] = { "uart8-data", };
static const char *x2000_uart9_groups[] = { "uart9-data", };
static const char *x2000_sfc_groups[] = {
"sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
"sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
};
static const char *x2000_ssi0_groups[] = {
"ssi0-dt-b", "ssi0-dt-d",
"ssi0-dr-b", "ssi0-dr-d",
"ssi0-clk-b", "ssi0-clk-d",
"ssi0-ce-b", "ssi0-ce-d",
};
static const char *x2000_ssi1_groups[] = {
"ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
};
static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
static const char *x2000_emc_groups[] = {
"emc-8bit-data", "emc-16bit-data",
"emc-addr", "emc-rd-we", "emc-wait",
};
static const char *x2000_cs1_groups[] = { "emc-cs1", };
static const char *x2000_cs2_groups[] = { "emc-cs2", };
static const char *x2000_i2c0_groups[] = { "i2c0-data", };
static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
static const char *x2000_i2s1_groups[] = {
"i2s1-data-tx", "i2s1-data-rx",
"i2s1-clk-tx", "i2s1-clk-rx",
"i2s1-sysclk-tx", "i2s1-sysclk-rx",
};
static const char *x2000_i2s2_groups[] = {
"i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
"i2s2-clk-rx", "i2s2-sysclk-rx",
};
static const char *x2000_i2s3_groups[] = {
"i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
"i2s3-clk-tx", "i2s3-sysclk-tx",
};
static const char *x2000_dmic_groups[] = {
"dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
};
static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
static const char *x2000_lcd_groups[] = {
"lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
"lcd-slcd-8bit", "lcd-slcd-16bit",
};
static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
static const char *x2000_pwm8_groups[] = { "pwm8", };
static const char *x2000_pwm9_groups[] = { "pwm9", };
static const char *x2000_pwm10_groups[] = { "pwm10", };
static const char *x2000_pwm11_groups[] = { "pwm11", };
static const char *x2000_pwm12_groups[] = { "pwm12", };
static const char *x2000_pwm13_groups[] = { "pwm13", };
static const char *x2000_pwm14_groups[] = { "pwm14", };
static const char *x2000_pwm15_groups[] = { "pwm15", };
static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
static const char *x2000_otg_groups[] = { "otg-vbus", };
static const struct function_desc x2000_functions[] = {
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
{ "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
{ "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
{ "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
};
static const struct regmap_range x2000_access_ranges[] = {
regmap_reg_range(0x000, 0x500 - 4),
regmap_reg_range(0x700, 0x800 - 4),
};
/* shared with X2100 */
static const struct regmap_access_table x2000_access_table = {
.yes_ranges = x2000_access_ranges,
.n_yes_ranges = ARRAY_SIZE(x2000_access_ranges),
};
static const struct ingenic_chip_info x2000_chip_info = {
.num_chips = 5,
.reg_offset = 0x100,
.version = ID_X2000,
.groups = x2000_groups,
.num_groups = ARRAY_SIZE(x2000_groups),
.functions = x2000_functions,
.num_functions = ARRAY_SIZE(x2000_functions),
.pull_ups = x2000_pull_ups,
.pull_downs = x2000_pull_downs,
.access_table = &x2000_access_table,
};
static const u32 x2100_pull_ups[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
};
static const u32 x2100_pull_downs[5] = {
0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
};
static int x2100_mac_pins[] = {
0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
};
static const struct group_desc x2100_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
x2000_cim_8bit_funcs),
INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
INGENIC_PIN_GROUP("mac", x2100_mac, 1),
};
static const char *x2100_mac_groups[] = { "mac", };
static const struct function_desc x2100_functions[] = {
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
{ "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
};
static const struct ingenic_chip_info x2100_chip_info = {
.num_chips = 5,
.reg_offset = 0x100,
.version = ID_X2100,
.groups = x2100_groups,
.num_groups = ARRAY_SIZE(x2100_groups),
.functions = x2100_functions,
.num_functions = ARRAY_SIZE(x2100_functions),
.pull_ups = x2100_pull_ups,
.pull_downs = x2100_pull_downs,
.access_table = &x2000_access_table,
};
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
{
unsigned int val;
regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
return (u32) val;
}
static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
u8 reg, u8 offset, bool set)
{
if (!is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
BIT(offset), set ? BIT(offset) : 0);
return;
}
if (set)
reg = REG_SET(reg);
else
reg = REG_CLEAR(reg);
regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
}
static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
u8 reg, u8 offset, bool set)
{
if (set)
reg = REG_SET(reg);
else
reg = REG_CLEAR(reg);
regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
}
static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
{
regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
jzgc->jzpc->info->reg_offset),
jzgc->gc.base / PINS_PER_GPIO_CHIP);
}
static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
{
/*
* JZ4730 function and IRQ registers support two-bits-per-pin
* definitions, split into two groups of 16.
*/
u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
unsigned int mask = GENMASK(1, 0) << idx * 2;
regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
}
static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
u8 offset)
{
unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
return !!(val & BIT(offset));
}
static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
u8 offset, int value)
{
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
}
static void irq_set_type(struct ingenic_gpio_chip *jzgc,
u8 offset, unsigned int type)
{
u8 reg1, reg2;
bool val1, val2, val3;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
val1 = val2 = false;
val3 = true;
break;
case IRQ_TYPE_EDGE_RISING:
val1 = val2 = true;
val3 = false;
break;
case IRQ_TYPE_EDGE_FALLING:
val1 = val3 = false;
val2 = true;
break;
case IRQ_TYPE_LEVEL_HIGH:
val1 = true;
val2 = val3 = false;
break;
case IRQ_TYPE_LEVEL_LOW:
default:
val1 = val2 = val3 = false;
break;
}
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770)) {
reg1 = JZ4770_GPIO_PAT1;
reg2 = JZ4770_GPIO_PAT0;
} else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740)) {
reg1 = JZ4740_GPIO_TRIG;
reg2 = JZ4740_GPIO_DIR;
} else {
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
return;
}
if (is_soc_or_above(jzgc->jzpc, ID_X2000)) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
ingenic_gpio_shadow_set_bit_load(jzgc);
ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
} else if (is_soc_or_above(jzgc->jzpc, ID_X1000)) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
ingenic_gpio_shadow_set_bit_load(jzgc);
} else {
ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
}
}
static void ingenic_gpio_irq_mask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
}
static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
}
static void ingenic_gpio_irq_enable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
gpiochip_enable_irq(gc, irq);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
ingenic_gpio_irq_unmask(irqd);
}
static void ingenic_gpio_irq_disable(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
ingenic_gpio_irq_mask(irqd);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
gpiochip_disable_irq(gc, irq);
}
static void ingenic_gpio_irq_ack(struct irq_data *irqd)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
bool high;
if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
!is_soc_or_above(jzgc->jzpc, ID_X2000)) {
/*
* Switch to an interrupt for the opposite edge to the one that
* triggered the interrupt being ACKed.
*/
high = ingenic_gpio_get_value(jzgc, irq);
if (high)
irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
else
irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
}
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
}
static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
irq_hw_number_t irq = irqd_to_hwirq(irqd);
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
irq_set_handler_locked(irqd, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
case IRQ_TYPE_LEVEL_LOW:
irq_set_handler_locked(irqd, handle_level_irq);
break;
default:
irq_set_handler_locked(irqd, handle_bad_irq);
}
if ((type == IRQ_TYPE_EDGE_BOTH) && !is_soc_or_above(jzgc->jzpc, ID_X2000)) {
/*
* The hardware does not support interrupts on both edges. The
* best we can do is to set up a single-edge interrupt and then
* switch to the opposing edge when ACKing the interrupt.
*/
bool high = ingenic_gpio_get_value(jzgc, irq);
type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
}
irq_set_type(jzgc, irq, type);
return 0;
}
static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
return irq_set_irq_wake(jzgc->irq, on);
}
static void ingenic_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
unsigned long flag, i;
chained_irq_enter(irq_chip, desc);
if (is_soc_or_above(jzgc->jzpc, ID_JZ4770))
flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
else if (is_soc_or_above(jzgc->jzpc, ID_JZ4740))
flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
else
flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
for_each_set_bit(i, &flag, 32)
generic_handle_domain_irq(gc->irq.domain, i);
chained_irq_exit(irq_chip, desc);
}
static void ingenic_gpio_set(struct gpio_chip *gc,
unsigned int offset, int value)
{
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
ingenic_gpio_set_value(jzgc, offset, value);
}
static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
return (int) ingenic_gpio_get_value(jzgc, offset);
}
static int ingenic_gpio_direction_input(struct gpio_chip *gc,
unsigned int offset)
{
return pinctrl_gpio_direction_input(gc->base + offset);
}
static int ingenic_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
ingenic_gpio_set(gc, offset, value);
return pinctrl_gpio_direction_output(gc->base + offset);
}
static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int reg, bool set)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
if (set) {
if (is_soc_or_above(jzpc, ID_JZ4740))
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_SET(reg), BIT(idx));
else
regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
reg, BIT(idx));
} else {
if (is_soc_or_above(jzpc, ID_JZ4740))
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_CLEAR(reg), BIT(idx));
else
regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
reg, BIT(idx));
}
}
static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
unsigned int pin, u8 reg, bool set)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
}
static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
unsigned int pin)
{
regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
pin / PINS_PER_GPIO_CHIP);
}
static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
{
/*
* JZ4730 function and IRQ registers support two-bits-per-pin
* definitions, split into two groups of 16.
*/
unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
unsigned int mask = GENMASK(1, 0) << idx * 2;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
mask, value << (idx * 2));
}
static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int reg)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
unsigned int val;
regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
return val & BIT(idx);
}
static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
struct ingenic_pinctrl *jzpc = jzgc->jzpc;
unsigned int pin = gc->base + offset;
if (is_soc_or_above(jzpc, ID_JZ4770)) {
if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
} else if (!is_soc_or_above(jzpc, ID_JZ4740)) {
if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
return GPIO_LINE_DIRECTION_IN;
if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static const struct pinctrl_ops ingenic_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int ingenic_gpio_irq_request(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
irq_hw_number_t irq = irqd_to_hwirq(data);
int ret;
ret = ingenic_gpio_direction_input(gpio_chip, irq);
if (ret)
return ret;
return gpiochip_reqres_irq(gpio_chip, irq);
}
static void ingenic_gpio_irq_release(struct irq_data *data)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
irq_hw_number_t irq = irqd_to_hwirq(data);
return gpiochip_relres_irq(gpio_chip, irq);
}
static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
{
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
seq_printf(p, "%s", gpio_chip->label);
}
static const struct irq_chip ingenic_gpio_irqchip = {
.irq_enable = ingenic_gpio_irq_enable,
.irq_disable = ingenic_gpio_irq_disable,
.irq_unmask = ingenic_gpio_irq_unmask,
.irq_mask = ingenic_gpio_irq_mask,
.irq_ack = ingenic_gpio_irq_ack,
.irq_set_type = ingenic_gpio_irq_set_type,
.irq_set_wake = ingenic_gpio_irq_set_wake,
.irq_request_resources = ingenic_gpio_irq_request,
.irq_release_resources = ingenic_gpio_irq_release,
.irq_print_chip = ingenic_gpio_irq_print_chip,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
};
static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
int pin, int func)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
'A' + offt, idx, func);
if (is_soc_or_above(jzpc, ID_X1000)) {
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
} else {
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
}
return 0;
}
static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
struct group_desc *grp;
unsigned int i;
uintptr_t mode;
u8 *pin_modes;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
dev_dbg(pctldev->dev, "enable function %s group %s\n",
func->name, grp->name);
mode = (uintptr_t)grp->data;
if (mode <= 3) {
for (i = 0; i < grp->num_pins; i++)
ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
} else {
pin_modes = grp->data;
for (i = 0; i < grp->num_pins; i++)
ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
}
return 0;
}
static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
'A' + offt, idx, input ? "in" : "out");
if (is_soc_or_above(jzpc, ID_X1000)) {
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
} else {
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
}
return 0;
}
static const struct pinmux_ops ingenic_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = ingenic_pinmux_set_mux,
.gpio_set_direction = ingenic_pinmux_gpio_set_direction,
};
static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
unsigned int arg = 1;
unsigned int bias, reg;
bool pull, pullup, pulldown;
if (is_soc_or_above(jzpc, ID_X2000)) {
pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
(jzpc->info->pull_ups[offt] & BIT(idx));
pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
!ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
(jzpc->info->pull_downs[offt] & BIT(idx));
} else if (is_soc_or_above(jzpc, ID_X1830)) {
unsigned int half = PINS_PER_GPIO_CHIP / 2;
unsigned int idxh = (pin % half) * 2;
if (idx < half)
regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
X1830_GPIO_PEL, &bias);
else
regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
X1830_GPIO_PEH, &bias);
bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
} else {
if (is_soc_or_above(jzpc, ID_JZ4770))
pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
else if (is_soc_or_above(jzpc, ID_JZ4740))
pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
else
pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
}
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (pullup || pulldown)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (!pullup)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!pulldown)
return -EINVAL;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (is_soc_or_above(jzpc, ID_X2000))
reg = X2000_GPIO_SMT;
else if (is_soc_or_above(jzpc, ID_X1830))
reg = X1830_GPIO_SMT;
else
return -EINVAL;
arg = !!ingenic_get_pin_config(jzpc, pin, reg);
break;
case PIN_CONFIG_SLEW_RATE:
if (is_soc_or_above(jzpc, ID_X2000))
reg = X2000_GPIO_SR;
else if (is_soc_or_above(jzpc, ID_X1830))
reg = X1830_GPIO_SR;
else
return -EINVAL;
arg = !!ingenic_get_pin_config(jzpc, pin, reg);
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int bias)
{
if (is_soc_or_above(jzpc, ID_X2000)) {
switch (bias) {
case GPIO_PULL_UP:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
break;
case GPIO_PULL_DOWN:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
break;
case GPIO_PULL_DIS:
default:
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
}
} else if (is_soc_or_above(jzpc, ID_X1830)) {
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int half = PINS_PER_GPIO_CHIP / 2;
unsigned int idxh = (pin % half) * 2;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
if (idx < half) {
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_SET(X1830_GPIO_PEL), bias << idxh);
} else {
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
REG_SET(X1830_GPIO_PEH), bias << idxh);
}
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
} else {
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
}
}
static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool enable)
{
if (is_soc_or_above(jzpc, ID_X2000))
ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
else
ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
}
static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool high)
{
if (is_soc_or_above(jzpc, ID_JZ4770))
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
else if (is_soc_or_above(jzpc, ID_JZ4740))
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
else
ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
}
static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
unsigned int pin, unsigned int slew)
{
if (is_soc_or_above(jzpc, ID_X2000))
ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
else
ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
}
static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
unsigned int cfg, arg;
int ret;
for (cfg = 0; cfg < num_configs; cfg++) {
switch (pinconf_to_config_param(configs[cfg])) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
case PIN_CONFIG_OUTPUT:
case PIN_CONFIG_SLEW_RATE:
continue;
default:
return -ENOTSUPP;
}
}
for (cfg = 0; cfg < num_configs; cfg++) {
arg = pinconf_to_config_argument(configs[cfg]);
switch (pinconf_to_config_param(configs[cfg])) {
case PIN_CONFIG_BIAS_DISABLE:
dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
'A' + offt, idx);
ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
return -EINVAL;
dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
'A' + offt, idx);
ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
return -EINVAL;
dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
'A' + offt, idx);
ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!is_soc_or_above(jzpc, ID_X1830))
return -EINVAL;
ingenic_set_schmitt_trigger(jzpc, pin, arg);
break;
case PIN_CONFIG_OUTPUT:
ret = pinctrl_gpio_direction_output(pin);
if (ret)
return ret;
ingenic_set_output_level(jzpc, pin, arg);
break;
case PIN_CONFIG_SLEW_RATE:
if (!is_soc_or_above(jzpc, ID_X1830))
return -EINVAL;
ingenic_set_slew_rate(jzpc, pin, arg);
break;
default:
/* unreachable */
break;
}
}
return 0;
}
static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *config)
{
const unsigned int *pins;
unsigned int i, npins, old = 0;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (ingenic_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && (old != *config))
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int i, npins;
int ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = ingenic_pinconf_set(pctldev,
pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops ingenic_confops = {
.is_generic = true,
.pin_config_get = ingenic_pinconf_get,
.pin_config_set = ingenic_pinconf_set,
.pin_config_group_get = ingenic_pinconf_group_get,
.pin_config_group_set = ingenic_pinconf_group_set,
};
static const struct regmap_config ingenic_pinctrl_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
{ .compatible = "ingenic,jz4730-gpio" },
{ .compatible = "ingenic,jz4740-gpio" },
{ .compatible = "ingenic,jz4725b-gpio" },
{ .compatible = "ingenic,jz4750-gpio" },
{ .compatible = "ingenic,jz4755-gpio" },
{ .compatible = "ingenic,jz4760-gpio" },
{ .compatible = "ingenic,jz4770-gpio" },
{ .compatible = "ingenic,jz4775-gpio" },
{ .compatible = "ingenic,jz4780-gpio" },
{ .compatible = "ingenic,x1000-gpio" },
{ .compatible = "ingenic,x1830-gpio" },
{ .compatible = "ingenic,x2000-gpio" },
{ .compatible = "ingenic,x2100-gpio" },
{},
};
static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
struct fwnode_handle *fwnode)
{
struct ingenic_gpio_chip *jzgc;
struct device *dev = jzpc->dev;
struct gpio_irq_chip *girq;
unsigned int bank;
int err;
err = fwnode_property_read_u32(fwnode, "reg", &bank);
if (err) {
dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
return err;
}
jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
if (!jzgc)
return -ENOMEM;
jzgc->jzpc = jzpc;
jzgc->reg_base = bank * jzpc->info->reg_offset;
jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
if (!jzgc->gc.label)
return -ENOMEM;
/* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
* ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
* <linux/gpio/consumer.h> INSTEAD.
*/
jzgc->gc.base = bank * 32;
jzgc->gc.ngpio = 32;
jzgc->gc.parent = dev;
jzgc->gc.fwnode = fwnode;
jzgc->gc.owner = THIS_MODULE;
jzgc->gc.set = ingenic_gpio_set;
jzgc->gc.get = ingenic_gpio_get;
jzgc->gc.direction_input = ingenic_gpio_direction_input;
jzgc->gc.direction_output = ingenic_gpio_direction_output;
jzgc->gc.get_direction = ingenic_gpio_get_direction;
jzgc->gc.request = gpiochip_generic_request;
jzgc->gc.free = gpiochip_generic_free;
err = fwnode_irq_get(fwnode, 0);
if (err < 0)
return err;
if (!err)
return -EINVAL;
jzgc->irq = err;
girq = &jzgc->gc.irq;
gpio_irq_chip_set_chip(girq, &ingenic_gpio_irqchip);
girq->parent_handler = ingenic_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = jzgc->irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
if (err)
return err;
return 0;
}
static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ingenic_pinctrl *jzpc;
struct pinctrl_desc *pctl_desc;
void __iomem *base;
const struct ingenic_chip_info *chip_info;
struct regmap_config regmap_config;
struct fwnode_handle *fwnode;
unsigned int i;
int err;
chip_info = device_get_match_data(dev);
if (!chip_info) {
dev_err(dev, "Unsupported SoC\n");
return -EINVAL;
}
jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
if (!jzpc)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap_config = ingenic_pinctrl_regmap_config;
if (chip_info->access_table) {
regmap_config.rd_table = chip_info->access_table;
regmap_config.wr_table = chip_info->access_table;
} else {
regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4;
}
jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config);
if (IS_ERR(jzpc->map)) {
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(jzpc->map);
}
jzpc->dev = dev;
jzpc->info = chip_info;
pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
if (!pctl_desc)
return -ENOMEM;
/* fill in pinctrl_desc structure */
pctl_desc->name = dev_name(dev);
pctl_desc->owner = THIS_MODULE;
pctl_desc->pctlops = &ingenic_pctlops;
pctl_desc->pmxops = &ingenic_pmxops;
pctl_desc->confops = &ingenic_confops;
pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
if (!jzpc->pdesc)
return -ENOMEM;
for (i = 0; i < pctl_desc->npins; i++) {
jzpc->pdesc[i].number = i;
jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
'A' + (i / PINS_PER_GPIO_CHIP),
i % PINS_PER_GPIO_CHIP);
}
jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
if (IS_ERR(jzpc->pctl)) {
dev_err(dev, "Failed to register pinctrl\n");
return PTR_ERR(jzpc->pctl);
}
for (i = 0; i < chip_info->num_groups; i++) {
const struct group_desc *group = &chip_info->groups[i];
err = pinctrl_generic_add_group(jzpc->pctl, group->name,
group->pins, group->num_pins, group->data);
if (err < 0) {
dev_err(dev, "Failed to register group %s\n",
group->name);
return err;
}
}
for (i = 0; i < chip_info->num_functions; i++) {
const struct function_desc *func = &chip_info->functions[i];
err = pinmux_generic_add_function(jzpc->pctl, func->name,
func->group_names, func->num_group_names,
func->data);
if (err < 0) {
dev_err(dev, "Failed to register function %s\n",
func->name);
return err;
}
}
dev_set_drvdata(dev, jzpc->map);
device_for_each_child_node(dev, fwnode) {
if (of_match_node(ingenic_gpio_of_matches, to_of_node(fwnode))) {
err = ingenic_gpio_probe(jzpc, fwnode);
if (err) {
fwnode_handle_put(fwnode);
return err;
}
}
}
return 0;
}
#define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
static const struct of_device_id ingenic_pinctrl_of_matches[] = {
{
.compatible = "ingenic,jz4730-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
},
{
.compatible = "ingenic,jz4740-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
},
{
.compatible = "ingenic,jz4725b-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
},
{
.compatible = "ingenic,jz4750-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
},
{
.compatible = "ingenic,jz4755-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
},
{
.compatible = "ingenic,jz4760-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
},
{
.compatible = "ingenic,jz4760b-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
},
{
.compatible = "ingenic,jz4770-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
},
{
.compatible = "ingenic,jz4775-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
},
{
.compatible = "ingenic,jz4780-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
},
{
.compatible = "ingenic,x1000-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
},
{
.compatible = "ingenic,x1000e-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
},
{
.compatible = "ingenic,x1500-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
},
{
.compatible = "ingenic,x1830-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
},
{
.compatible = "ingenic,x2000-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
},
{
.compatible = "ingenic,x2000e-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
},
{
.compatible = "ingenic,x2100-pinctrl",
.data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
},
{ /* sentinel */ },
};
static struct platform_driver ingenic_pinctrl_driver = {
.driver = {
.name = "pinctrl-ingenic",
.of_match_table = ingenic_pinctrl_of_matches,
},
};
static int __init ingenic_pinctrl_drv_register(void)
{
return platform_driver_probe(&ingenic_pinctrl_driver,
ingenic_pinctrl_probe);
}
subsys_initcall(ingenic_pinctrl_drv_register);
|
linux-master
|
drivers/pinctrl/pinctrl-ingenic.c
|
/*
* Generic device tree based pinctrl driver for one register per pin
* type pinmux controllers
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/list.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_data/pinctrl-single.h>
#include "core.h"
#include "devicetree.h"
#include "pinconf.h"
#include "pinmux.h"
#define DRIVER_NAME "pinctrl-single"
#define PCS_OFF_DISABLED ~0U
/**
* struct pcs_func_vals - mux function register offset and value pair
* @reg: register virtual address
* @val: register value
* @mask: mask
*/
struct pcs_func_vals {
void __iomem *reg;
unsigned val;
unsigned mask;
};
/**
* struct pcs_conf_vals - pinconf parameter, pinconf register offset
* and value, enable, disable, mask
* @param: config parameter
* @val: user input bits in the pinconf register
* @enable: enable bits in the pinconf register
* @disable: disable bits in the pinconf register
* @mask: mask bits in the register value
*/
struct pcs_conf_vals {
enum pin_config_param param;
unsigned val;
unsigned enable;
unsigned disable;
unsigned mask;
};
/**
* struct pcs_conf_type - pinconf property name, pinconf param pair
* @name: property name in DTS file
* @param: config parameter
*/
struct pcs_conf_type {
const char *name;
enum pin_config_param param;
};
/**
* struct pcs_function - pinctrl function
* @name: pinctrl function name
* @vals: register and vals array
* @nvals: number of entries in vals array
* @pgnames: array of pingroup names the function uses
* @npgnames: number of pingroup names the function uses
* @conf: array of pin configurations
* @nconfs: number of pin configurations available
* @node: list node
*/
struct pcs_function {
const char *name;
struct pcs_func_vals *vals;
unsigned nvals;
const char **pgnames;
int npgnames;
struct pcs_conf_vals *conf;
int nconfs;
struct list_head node;
};
/**
* struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
* @offset: offset base of pins
* @npins: number pins with the same mux value of gpio function
* @gpiofunc: mux value of gpio function
* @node: list node
*/
struct pcs_gpiofunc_range {
unsigned offset;
unsigned npins;
unsigned gpiofunc;
struct list_head node;
};
/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
*
* REVISIT: We should be able to drop this eventually by adding
* support for registering pins individually in the pinctrl
* framework for those drivers that don't need a static array.
*/
struct pcs_data {
struct pinctrl_pin_desc *pa;
int cur;
};
/**
* struct pcs_soc_data - SoC specific settings
* @flags: initial SoC specific PCS_FEAT_xxx values
* @irq: optional interrupt for the controller
* @irq_enable_mask: optional SoC specific interrupt enable mask
* @irq_status_mask: optional SoC specific interrupt status mask
* @rearm: optional SoC specific wake-up rearm function
*/
struct pcs_soc_data {
unsigned flags;
int irq;
unsigned irq_enable_mask;
unsigned irq_status_mask;
void (*rearm)(void);
};
/**
* struct pcs_device - pinctrl device instance
* @res: resources
* @base: virtual address of the controller
* @saved_vals: saved values for the controller
* @size: size of the ioremapped area
* @dev: device entry
* @np: device tree node
* @pctl: pin controller device
* @flags: mask of PCS_FEAT_xxx values
* @missing_nr_pinctrl_cells: for legacy binding, may go away
* @socdata: soc specific data
* @lock: spinlock for register access
* @mutex: mutex protecting the lists
* @width: bits per mux register
* @fmask: function register mask
* @fshift: function register shift
* @foff: value to turn mux off
* @fmax: max number of functions in fmask
* @bits_per_mux: number of bits per mux
* @bits_per_pin: number of bits per pin
* @pins: physical pins on the SoC
* @gpiofuncs: list of gpio functions
* @irqs: list of interrupt registers
* @chip: chip container for this instance
* @domain: IRQ domain for this instance
* @desc: pin controller descriptor
* @read: register read function to use
* @write: register write function to use
*/
struct pcs_device {
struct resource *res;
void __iomem *base;
void *saved_vals;
unsigned size;
struct device *dev;
struct device_node *np;
struct pinctrl_dev *pctl;
unsigned flags;
#define PCS_CONTEXT_LOSS_OFF (1 << 3)
#define PCS_QUIRK_SHARED_IRQ (1 << 2)
#define PCS_FEAT_IRQ (1 << 1)
#define PCS_FEAT_PINCONF (1 << 0)
struct property *missing_nr_pinctrl_cells;
struct pcs_soc_data socdata;
raw_spinlock_t lock;
struct mutex mutex;
unsigned width;
unsigned fmask;
unsigned fshift;
unsigned foff;
unsigned fmax;
bool bits_per_mux;
unsigned bits_per_pin;
struct pcs_data pins;
struct list_head gpiofuncs;
struct list_head irqs;
struct irq_chip chip;
struct irq_domain *domain;
struct pinctrl_desc desc;
unsigned (*read)(void __iomem *reg);
void (*write)(unsigned val, void __iomem *reg);
};
#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *config);
static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs);
static enum pin_config_param pcs_bias[] = {
PIN_CONFIG_BIAS_PULL_DOWN,
PIN_CONFIG_BIAS_PULL_UP,
};
/*
* This lock class tells lockdep that irqchip core that this single
* pinctrl can be in a different category than its parents, so it won't
* report false recursion.
*/
static struct lock_class_key pcs_lock_class;
/* Class for the IRQ request mutex */
static struct lock_class_key pcs_request_class;
/*
* REVISIT: Reads and writes could eventually use regmap or something
* generic. But at least on omaps, some mux registers are performance
* critical as they may need to be remuxed every time before and after
* idle. Adding tests for register access width for every read and
* write like regmap is doing is not desired, and caching the registers
* does not help in this case.
*/
static unsigned __maybe_unused pcs_readb(void __iomem *reg)
{
return readb(reg);
}
static unsigned __maybe_unused pcs_readw(void __iomem *reg)
{
return readw(reg);
}
static unsigned __maybe_unused pcs_readl(void __iomem *reg)
{
return readl(reg);
}
static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
{
writeb(val, reg);
}
static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
{
writew(val, reg);
}
static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
{
writel(val, reg);
}
static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
unsigned int pin)
{
unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
if (pcs->bits_per_mux) {
unsigned int pin_offset_bytes;
pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
return (pin_offset_bytes / mux_bytes) * mux_bytes;
}
return pin * mux_bytes;
}
static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
unsigned int pin)
{
return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
}
static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned pin)
{
struct pcs_device *pcs;
unsigned int val;
unsigned long offset;
size_t pa;
pcs = pinctrl_dev_get_drvdata(pctldev);
offset = pcs_pin_reg_offset_get(pcs, pin);
val = pcs->read(pcs->base + offset);
if (pcs->bits_per_mux)
val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
pa = pcs->res->start + offset;
seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
}
static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
struct pcs_device *pcs;
pcs = pinctrl_dev_get_drvdata(pctldev);
devm_kfree(pcs->dev, map);
}
static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps);
static const struct pinctrl_ops pcs_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.pin_dbg_show = pcs_pin_dbg_show,
.dt_node_to_map = pcs_dt_node_to_map,
.dt_free_map = pcs_dt_free_map,
};
static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
struct pcs_function **func)
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
const struct pinctrl_setting_mux *setting;
struct function_desc *function;
unsigned fselector;
/* If pin is not described in DTS & enabled, mux_setting is NULL. */
setting = pdesc->mux_setting;
if (!setting)
return -ENOTSUPP;
fselector = setting->func;
function = pinmux_generic_get_function(pctldev, fselector);
*func = function->data;
if (!(*func)) {
dev_err(pcs->dev, "%s could not find function%i\n",
__func__, fselector);
return -ENOTSUPP;
}
return 0;
}
static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
struct pcs_device *pcs;
struct function_desc *function;
struct pcs_function *func;
int i;
pcs = pinctrl_dev_get_drvdata(pctldev);
/* If function mask is null, needn't enable it. */
if (!pcs->fmask)
return 0;
function = pinmux_generic_get_function(pctldev, fselector);
if (!function)
return -EINVAL;
func = function->data;
if (!func)
return -EINVAL;
dev_dbg(pcs->dev, "enabling %s function%i\n",
func->name, fselector);
for (i = 0; i < func->nvals; i++) {
struct pcs_func_vals *vals;
unsigned long flags;
unsigned val, mask;
vals = &func->vals[i];
raw_spin_lock_irqsave(&pcs->lock, flags);
val = pcs->read(vals->reg);
if (pcs->bits_per_mux)
mask = vals->mask;
else
mask = pcs->fmask;
val &= ~mask;
val |= (vals->val & mask);
pcs->write(val, vals->reg);
raw_spin_unlock_irqrestore(&pcs->lock, flags);
}
return 0;
}
static int pcs_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned pin)
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_gpiofunc_range *frange = NULL;
struct list_head *pos, *tmp;
unsigned data;
/* If function mask is null, return directly. */
if (!pcs->fmask)
return -ENOTSUPP;
list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
u32 offset;
frange = list_entry(pos, struct pcs_gpiofunc_range, node);
if (pin >= frange->offset + frange->npins
|| pin < frange->offset)
continue;
offset = pcs_pin_reg_offset_get(pcs, pin);
if (pcs->bits_per_mux) {
int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
data = pcs->read(pcs->base + offset);
data &= ~(pcs->fmask << pin_shift);
data |= frange->gpiofunc << pin_shift;
pcs->write(data, pcs->base + offset);
} else {
data = pcs->read(pcs->base + offset);
data &= ~pcs->fmask;
data |= frange->gpiofunc;
pcs->write(data, pcs->base + offset);
}
break;
}
return 0;
}
static const struct pinmux_ops pcs_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = pcs_set_mux,
.gpio_request_enable = pcs_request_gpio,
};
/* Clear BIAS value */
static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
{
unsigned long config;
int i;
for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
config = pinconf_to_config_packed(pcs_bias[i], 0);
pcs_pinconf_set(pctldev, pin, &config, 1);
}
}
/*
* Check whether PIN_CONFIG_BIAS_DISABLE is valid.
* It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
*/
static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
{
unsigned long config;
int i;
for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
config = pinconf_to_config_packed(pcs_bias[i], 0);
if (!pcs_pinconf_get(pctldev, pin, &config))
goto out;
}
return true;
out:
return false;
}
static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_function *func;
enum pin_config_param param;
unsigned offset = 0, data = 0, i, j, ret;
ret = pcs_get_function(pctldev, pin, &func);
if (ret)
return ret;
for (i = 0; i < func->nconfs; i++) {
param = pinconf_to_config_param(*config);
if (param == PIN_CONFIG_BIAS_DISABLE) {
if (pcs_pinconf_bias_disable(pctldev, pin)) {
*config = 0;
return 0;
} else {
return -ENOTSUPP;
}
} else if (param != func->conf[i].param) {
continue;
}
offset = pin * (pcs->width / BITS_PER_BYTE);
data = pcs->read(pcs->base + offset) & func->conf[i].mask;
switch (func->conf[i].param) {
/* 4 parameters */
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if ((data != func->conf[i].enable) ||
(data == func->conf[i].disable))
return -ENOTSUPP;
*config = 0;
break;
/* 2 parameters */
case PIN_CONFIG_INPUT_SCHMITT:
for (j = 0; j < func->nconfs; j++) {
switch (func->conf[j].param) {
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (data != func->conf[j].enable)
return -ENOTSUPP;
break;
default:
break;
}
}
*config = data;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_MODE_LOW_POWER:
case PIN_CONFIG_INPUT_ENABLE:
default:
*config = data;
break;
}
return 0;
}
return -ENOTSUPP;
}
static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *configs,
unsigned num_configs)
{
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_function *func;
unsigned offset = 0, shift = 0, i, data, ret;
u32 arg;
int j;
ret = pcs_get_function(pctldev, pin, &func);
if (ret)
return ret;
for (j = 0; j < num_configs; j++) {
for (i = 0; i < func->nconfs; i++) {
if (pinconf_to_config_param(configs[j])
!= func->conf[i].param)
continue;
offset = pin * (pcs->width / BITS_PER_BYTE);
data = pcs->read(pcs->base + offset);
arg = pinconf_to_config_argument(configs[j]);
switch (func->conf[i].param) {
/* 2 parameters */
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_MODE_LOW_POWER:
case PIN_CONFIG_INPUT_ENABLE:
shift = ffs(func->conf[i].mask) - 1;
data &= ~func->conf[i].mask;
data |= (arg << shift) & func->conf[i].mask;
break;
/* 4 parameters */
case PIN_CONFIG_BIAS_DISABLE:
pcs_pinconf_clear_bias(pctldev, pin);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_UP:
if (arg)
pcs_pinconf_clear_bias(pctldev, pin);
fallthrough;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
data &= ~func->conf[i].mask;
if (arg)
data |= func->conf[i].enable;
else
data |= func->conf[i].disable;
break;
default:
return -ENOTSUPP;
}
pcs->write(data, pcs->base + offset);
break;
}
if (i >= func->nconfs)
return -ENOTSUPP;
} /* for each config */
return 0;
}
static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
const unsigned *pins;
unsigned npins, old = 0;
int i, ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (pcs_pinconf_get(pctldev, pins[i], config))
return -ENOTSUPP;
/* configs do not match between two pins */
if (i && (old != *config))
return -ENOTSUPP;
old = *config;
}
return 0;
}
static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *configs,
unsigned num_configs)
{
const unsigned *pins;
unsigned npins;
int i, ret;
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
return -ENOTSUPP;
}
return 0;
}
static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin)
{
}
static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned selector)
{
}
static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned long config)
{
pinconf_generic_dump_config(pctldev, s, config);
}
static const struct pinconf_ops pcs_pinconf_ops = {
.pin_config_get = pcs_pinconf_get,
.pin_config_set = pcs_pinconf_set,
.pin_config_group_get = pcs_pinconf_group_get,
.pin_config_group_set = pcs_pinconf_group_set,
.pin_config_dbg_show = pcs_pinconf_dbg_show,
.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
.pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
.is_generic = true,
};
/**
* pcs_add_pin() - add a pin to the static per controller pin array
* @pcs: pcs driver instance
* @offset: register offset from base
*/
static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
{
struct pcs_soc_data *pcs_soc = &pcs->socdata;
struct pinctrl_pin_desc *pin;
int i;
i = pcs->pins.cur;
if (i >= pcs->desc.npins) {
dev_err(pcs->dev, "too many pins, max %i\n",
pcs->desc.npins);
return -ENOMEM;
}
if (pcs_soc->irq_enable_mask) {
unsigned val;
val = pcs->read(pcs->base + offset);
if (val & pcs_soc->irq_enable_mask) {
dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
(unsigned long)pcs->res->start + offset, val);
val &= ~pcs_soc->irq_enable_mask;
pcs->write(val, pcs->base + offset);
}
}
pin = &pcs->pins.pa[i];
pin->number = i;
pcs->pins.cur++;
return i;
}
/**
* pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
* @pcs: pcs driver instance
*
* In case of errors, resources are freed in pcs_free_resources.
*
* If your hardware needs holes in the address space, then just set
* up multiple driver instances.
*/
static int pcs_allocate_pin_table(struct pcs_device *pcs)
{
int mux_bytes, nr_pins, i;
mux_bytes = pcs->width / BITS_PER_BYTE;
if (pcs->bits_per_mux && pcs->fmask) {
pcs->bits_per_pin = fls(pcs->fmask);
nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
} else {
nr_pins = pcs->size / mux_bytes;
}
dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
pcs->pins.pa = devm_kcalloc(pcs->dev,
nr_pins, sizeof(*pcs->pins.pa),
GFP_KERNEL);
if (!pcs->pins.pa)
return -ENOMEM;
pcs->desc.pins = pcs->pins.pa;
pcs->desc.npins = nr_pins;
for (i = 0; i < pcs->desc.npins; i++) {
unsigned offset;
int res;
offset = pcs_pin_reg_offset_get(pcs, i);
res = pcs_add_pin(pcs, offset);
if (res < 0) {
dev_err(pcs->dev, "error adding pins: %i\n", res);
return res;
}
}
return 0;
}
/**
* pcs_add_function() - adds a new function to the function list
* @pcs: pcs driver instance
* @fcn: new function allocated
* @name: name of the function
* @vals: array of mux register value pairs used by the function
* @nvals: number of mux register value pairs
* @pgnames: array of pingroup names for the function
* @npgnames: number of pingroup names
*
* Caller must take care of locking.
*/
static int pcs_add_function(struct pcs_device *pcs,
struct pcs_function **fcn,
const char *name,
struct pcs_func_vals *vals,
unsigned int nvals,
const char **pgnames,
unsigned int npgnames)
{
struct pcs_function *function;
int selector;
function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
if (!function)
return -ENOMEM;
function->vals = vals;
function->nvals = nvals;
function->name = name;
selector = pinmux_generic_add_function(pcs->pctl, name,
pgnames, npgnames,
function);
if (selector < 0) {
devm_kfree(pcs->dev, function);
*fcn = NULL;
} else {
*fcn = function;
}
return selector;
}
/**
* pcs_get_pin_by_offset() - get a pin index based on the register offset
* @pcs: pcs driver instance
* @offset: register offset from the base
*
* Note that this is OK as long as the pins are in a static array.
*/
static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
{
unsigned index;
if (offset >= pcs->size) {
dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
offset, pcs->size);
return -EINVAL;
}
if (pcs->bits_per_mux)
index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
else
index = offset / (pcs->width / BITS_PER_BYTE);
return index;
}
/*
* check whether data matches enable bits or disable bits
* Return value: 1 for matching enable bits, 0 for matching disable bits,
* and negative value for matching failure.
*/
static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
{
int ret = -EINVAL;
if (data == enable)
ret = 1;
else if (data == disable)
ret = 0;
return ret;
}
static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
unsigned value, unsigned enable, unsigned disable,
unsigned mask)
{
(*conf)->param = param;
(*conf)->val = value;
(*conf)->enable = enable;
(*conf)->disable = disable;
(*conf)->mask = mask;
(*conf)++;
}
static void add_setting(unsigned long **setting, enum pin_config_param param,
unsigned arg)
{
**setting = pinconf_to_config_packed(param, arg);
(*setting)++;
}
/* add pinconf setting with 2 parameters */
static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
const char *name, enum pin_config_param param,
struct pcs_conf_vals **conf, unsigned long **settings)
{
unsigned value[2], shift;
int ret;
ret = of_property_read_u32_array(np, name, value, 2);
if (ret)
return;
/* set value & mask */
value[0] &= value[1];
shift = ffs(value[1]) - 1;
/* skip enable & disable */
add_config(conf, param, value[0], 0, 0, value[1]);
add_setting(settings, param, value[0] >> shift);
}
/* add pinconf setting with 4 parameters */
static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
const char *name, enum pin_config_param param,
struct pcs_conf_vals **conf, unsigned long **settings)
{
unsigned value[4];
int ret;
/* value to set, enable, disable, mask */
ret = of_property_read_u32_array(np, name, value, 4);
if (ret)
return;
if (!value[3]) {
dev_err(pcs->dev, "mask field of the property can't be 0\n");
return;
}
value[0] &= value[3];
value[1] &= value[3];
value[2] &= value[3];
ret = pcs_config_match(value[0], value[1], value[2]);
if (ret < 0)
dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
add_config(conf, param, value[0], value[1], value[2], value[3]);
add_setting(settings, param, ret);
}
static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
struct pcs_function *func,
struct pinctrl_map **map)
{
struct pinctrl_map *m = *map;
int i = 0, nconfs = 0;
unsigned long *settings = NULL, *s = NULL;
struct pcs_conf_vals *conf = NULL;
static const struct pcs_conf_type prop2[] = {
{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
{ "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },
{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
{ "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
};
static const struct pcs_conf_type prop4[] = {
{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
{ "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
{ "pinctrl-single,input-schmitt-enable",
PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
};
/* If pinconf isn't supported, don't parse properties in below. */
if (!PCS_HAS_PINCONF)
return -ENOTSUPP;
/* cacluate how much properties are supported in current node */
for (i = 0; i < ARRAY_SIZE(prop2); i++) {
if (of_property_present(np, prop2[i].name))
nconfs++;
}
for (i = 0; i < ARRAY_SIZE(prop4); i++) {
if (of_property_present(np, prop4[i].name))
nconfs++;
}
if (!nconfs)
return -ENOTSUPP;
func->conf = devm_kcalloc(pcs->dev,
nconfs, sizeof(struct pcs_conf_vals),
GFP_KERNEL);
if (!func->conf)
return -ENOMEM;
func->nconfs = nconfs;
conf = &(func->conf[0]);
m++;
settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
GFP_KERNEL);
if (!settings)
return -ENOMEM;
s = &settings[0];
for (i = 0; i < ARRAY_SIZE(prop2); i++)
pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
&conf, &s);
for (i = 0; i < ARRAY_SIZE(prop4); i++)
pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
&conf, &s);
m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
m->data.configs.group_or_pin = np->name;
m->data.configs.configs = settings;
m->data.configs.num_configs = nconfs;
return 0;
}
/**
* pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
* @pcs: pinctrl driver instance
* @np: device node of the mux entry
* @map: map entry
* @num_maps: number of map
* @pgnames: pingroup names
*
* Note that this binding currently supports only sets of one register + value.
*
* Also note that this driver tries to avoid understanding pin and function
* names because of the extra bloat they would cause especially in the case of
* a large number of pins. This driver just sets what is specified for the board
* in the .dts file. Further user space debugging tools can be developed to
* decipher the pin and function names using debugfs.
*
* If you are concerned about the boot time, set up the static pins in
* the bootloader, and only set up selected pins as device tree entries.
*/
static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
struct device_node *np,
struct pinctrl_map **map,
unsigned *num_maps,
const char **pgnames)
{
const char *name = "pinctrl-single,pins";
struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
struct pcs_function *function = NULL;
rows = pinctrl_count_index_with_args(np, name);
if (rows <= 0) {
dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
return -EINVAL;
}
vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
if (!vals)
return -ENOMEM;
pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
if (!pins)
goto free_vals;
for (i = 0; i < rows; i++) {
struct of_phandle_args pinctrl_spec;
unsigned int offset;
int pin;
res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
if (res)
return res;
if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
dev_err(pcs->dev, "invalid args_count for spec: %i\n",
pinctrl_spec.args_count);
break;
}
offset = pinctrl_spec.args[0];
vals[found].reg = pcs->base + offset;
switch (pinctrl_spec.args_count) {
case 2:
vals[found].val = pinctrl_spec.args[1];
break;
case 3:
vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
break;
}
dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
pinctrl_spec.np, offset, vals[found].val);
pin = pcs_get_pin_by_offset(pcs, offset);
if (pin < 0) {
dev_err(pcs->dev,
"could not add functions for %pOFn %ux\n",
np, offset);
break;
}
pins[found++] = pin;
}
pgnames[0] = np->name;
mutex_lock(&pcs->mutex);
fsel = pcs_add_function(pcs, &function, np->name, vals, found,
pgnames, 1);
if (fsel < 0) {
res = fsel;
goto free_pins;
}
gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (gsel < 0) {
res = gsel;
goto free_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
if (PCS_HAS_PINCONF && function) {
res = pcs_parse_pinconf(pcs, np, function, map);
if (res == 0)
*num_maps = 2;
else if (res == -ENOTSUPP)
*num_maps = 1;
else
goto free_pingroups;
} else {
*num_maps = 1;
}
mutex_unlock(&pcs->mutex);
return 0;
free_pingroups:
pinctrl_generic_remove_group(pcs->pctl, gsel);
*num_maps = 1;
free_function:
pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins:
mutex_unlock(&pcs->mutex);
devm_kfree(pcs->dev, pins);
free_vals:
devm_kfree(pcs->dev, vals);
return res;
}
static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
struct device_node *np,
struct pinctrl_map **map,
unsigned *num_maps,
const char **pgnames)
{
const char *name = "pinctrl-single,bits";
struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
int npins_in_row;
struct pcs_function *function = NULL;
rows = pinctrl_count_index_with_args(np, name);
if (rows <= 0) {
dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
return -EINVAL;
}
if (PCS_HAS_PINCONF) {
dev_err(pcs->dev, "pinconf not supported\n");
return -ENOTSUPP;
}
npins_in_row = pcs->width / pcs->bits_per_pin;
vals = devm_kzalloc(pcs->dev,
array3_size(rows, npins_in_row, sizeof(*vals)),
GFP_KERNEL);
if (!vals)
return -ENOMEM;
pins = devm_kzalloc(pcs->dev,
array3_size(rows, npins_in_row, sizeof(*pins)),
GFP_KERNEL);
if (!pins)
goto free_vals;
for (i = 0; i < rows; i++) {
struct of_phandle_args pinctrl_spec;
unsigned offset, val;
unsigned mask, bit_pos, val_pos, mask_pos, submask;
unsigned pin_num_from_lsb;
int pin;
res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
if (res)
return res;
if (pinctrl_spec.args_count < 3) {
dev_err(pcs->dev, "invalid args_count for spec: %i\n",
pinctrl_spec.args_count);
break;
}
/* Index plus two value cells */
offset = pinctrl_spec.args[0];
val = pinctrl_spec.args[1];
mask = pinctrl_spec.args[2];
dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
pinctrl_spec.np, offset, val, mask);
/* Parse pins in each row from LSB */
while (mask) {
bit_pos = __ffs(mask);
pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
mask_pos = ((pcs->fmask) << bit_pos);
val_pos = val & mask_pos;
submask = mask & mask_pos;
if ((mask & mask_pos) == 0) {
dev_err(pcs->dev,
"Invalid mask for %pOFn at 0x%x\n",
np, offset);
break;
}
mask &= ~mask_pos;
if (submask != mask_pos) {
dev_warn(pcs->dev,
"Invalid submask 0x%x for %pOFn at 0x%x\n",
submask, np, offset);
continue;
}
vals[found].mask = submask;
vals[found].reg = pcs->base + offset;
vals[found].val = val_pos;
pin = pcs_get_pin_by_offset(pcs, offset);
if (pin < 0) {
dev_err(pcs->dev,
"could not add functions for %pOFn %ux\n",
np, offset);
break;
}
pins[found++] = pin + pin_num_from_lsb;
}
}
pgnames[0] = np->name;
mutex_lock(&pcs->mutex);
fsel = pcs_add_function(pcs, &function, np->name, vals, found,
pgnames, 1);
if (fsel < 0) {
res = fsel;
goto free_pins;
}
res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (res < 0)
goto free_function;
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
*num_maps = 1;
mutex_unlock(&pcs->mutex);
return 0;
free_function:
pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins:
mutex_unlock(&pcs->mutex);
devm_kfree(pcs->dev, pins);
free_vals:
devm_kfree(pcs->dev, vals);
return res;
}
/**
* pcs_dt_node_to_map() - allocates and parses pinctrl maps
* @pctldev: pinctrl instance
* @np_config: device tree pinmux entry
* @map: array of map entries
* @num_maps: number of maps
*/
static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
struct pcs_device *pcs;
const char **pgnames;
int ret;
pcs = pinctrl_dev_get_drvdata(pctldev);
/* create 2 maps. One is for pinmux, and the other is for pinconf. */
*map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
if (!*map)
return -ENOMEM;
*num_maps = 0;
pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
if (!pgnames) {
ret = -ENOMEM;
goto free_map;
}
if (pcs->bits_per_mux) {
ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
num_maps, pgnames);
if (ret < 0) {
dev_err(pcs->dev, "no pins entries for %pOFn\n",
np_config);
goto free_pgnames;
}
} else {
ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
num_maps, pgnames);
if (ret < 0) {
dev_err(pcs->dev, "no pins entries for %pOFn\n",
np_config);
goto free_pgnames;
}
}
return 0;
free_pgnames:
devm_kfree(pcs->dev, pgnames);
free_map:
devm_kfree(pcs->dev, *map);
return ret;
}
/**
* pcs_irq_free() - free interrupt
* @pcs: pcs driver instance
*/
static void pcs_irq_free(struct pcs_device *pcs)
{
struct pcs_soc_data *pcs_soc = &pcs->socdata;
if (pcs_soc->irq < 0)
return;
if (pcs->domain)
irq_domain_remove(pcs->domain);
if (PCS_QUIRK_HAS_SHARED_IRQ)
free_irq(pcs_soc->irq, pcs_soc);
else
irq_set_chained_handler(pcs_soc->irq, NULL);
}
/**
* pcs_free_resources() - free memory used by this driver
* @pcs: pcs driver instance
*/
static void pcs_free_resources(struct pcs_device *pcs)
{
pcs_irq_free(pcs);
pinctrl_unregister(pcs->pctl);
#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
if (pcs->missing_nr_pinctrl_cells)
of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
#endif
}
static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
{
const char *propname = "pinctrl-single,gpio-range";
const char *cellname = "#pinctrl-single,gpio-range-cells";
struct of_phandle_args gpiospec;
struct pcs_gpiofunc_range *range;
int ret, i;
for (i = 0; ; i++) {
ret = of_parse_phandle_with_args(node, propname, cellname,
i, &gpiospec);
/* Do not treat it as error. Only treat it as end condition. */
if (ret) {
ret = 0;
break;
}
range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
if (!range) {
ret = -ENOMEM;
break;
}
range->offset = gpiospec.args[0];
range->npins = gpiospec.args[1];
range->gpiofunc = gpiospec.args[2];
mutex_lock(&pcs->mutex);
list_add_tail(&range->node, &pcs->gpiofuncs);
mutex_unlock(&pcs->mutex);
}
return ret;
}
/**
* struct pcs_interrupt
* @reg: virtual address of interrupt register
* @hwirq: hardware irq number
* @irq: virtual irq number
* @node: list node
*/
struct pcs_interrupt {
void __iomem *reg;
irq_hw_number_t hwirq;
unsigned int irq;
struct list_head node;
};
/**
* pcs_irq_set() - enables or disables an interrupt
* @pcs_soc: SoC specific settings
* @irq: interrupt
* @enable: enable or disable the interrupt
*
* Note that this currently assumes one interrupt per pinctrl
* register that is typically used for wake-up events.
*/
static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
int irq, const bool enable)
{
struct pcs_device *pcs;
struct list_head *pos;
unsigned mask;
pcs = container_of(pcs_soc, struct pcs_device, socdata);
list_for_each(pos, &pcs->irqs) {
struct pcs_interrupt *pcswi;
unsigned soc_mask;
pcswi = list_entry(pos, struct pcs_interrupt, node);
if (irq != pcswi->irq)
continue;
soc_mask = pcs_soc->irq_enable_mask;
raw_spin_lock(&pcs->lock);
mask = pcs->read(pcswi->reg);
if (enable)
mask |= soc_mask;
else
mask &= ~soc_mask;
pcs->write(mask, pcswi->reg);
/* flush posted write */
mask = pcs->read(pcswi->reg);
raw_spin_unlock(&pcs->lock);
}
if (pcs_soc->rearm)
pcs_soc->rearm();
}
/**
* pcs_irq_mask() - mask pinctrl interrupt
* @d: interrupt data
*/
static void pcs_irq_mask(struct irq_data *d)
{
struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
pcs_irq_set(pcs_soc, d->irq, false);
}
/**
* pcs_irq_unmask() - unmask pinctrl interrupt
* @d: interrupt data
*/
static void pcs_irq_unmask(struct irq_data *d)
{
struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
pcs_irq_set(pcs_soc, d->irq, true);
}
/**
* pcs_irq_set_wake() - toggle the suspend and resume wake up
* @d: interrupt data
* @state: wake-up state
*
* Note that this should be called only for suspend and resume.
* For runtime PM, the wake-up events should be enabled by default.
*/
static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
{
if (state)
pcs_irq_unmask(d);
else
pcs_irq_mask(d);
return 0;
}
/**
* pcs_irq_handle() - common interrupt handler
* @pcs_soc: SoC specific settings
*
* Note that this currently assumes we have one interrupt bit per
* mux register. This interrupt is typically used for wake-up events.
* For more complex interrupts different handlers can be specified.
*/
static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
{
struct pcs_device *pcs;
struct list_head *pos;
int count = 0;
pcs = container_of(pcs_soc, struct pcs_device, socdata);
list_for_each(pos, &pcs->irqs) {
struct pcs_interrupt *pcswi;
unsigned mask;
pcswi = list_entry(pos, struct pcs_interrupt, node);
raw_spin_lock(&pcs->lock);
mask = pcs->read(pcswi->reg);
raw_spin_unlock(&pcs->lock);
if (mask & pcs_soc->irq_status_mask) {
generic_handle_domain_irq(pcs->domain,
pcswi->hwirq);
count++;
}
}
return count;
}
/**
* pcs_irq_handler() - handler for the shared interrupt case
* @irq: interrupt
* @d: data
*
* Use this for cases where multiple instances of
* pinctrl-single share a single interrupt like on omaps.
*/
static irqreturn_t pcs_irq_handler(int irq, void *d)
{
struct pcs_soc_data *pcs_soc = d;
return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
}
/**
* pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
* @desc: interrupt descriptor
*
* Use this if you have a separate interrupt for each
* pinctrl-single instance.
*/
static void pcs_irq_chain_handler(struct irq_desc *desc)
{
struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
struct irq_chip *chip;
chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
pcs_irq_handle(pcs_soc);
/* REVISIT: export and add handle_bad_irq(irq, desc)? */
chained_irq_exit(chip, desc);
}
static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct pcs_soc_data *pcs_soc = d->host_data;
struct pcs_device *pcs;
struct pcs_interrupt *pcswi;
pcs = container_of(pcs_soc, struct pcs_device, socdata);
pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
if (!pcswi)
return -ENOMEM;
pcswi->reg = pcs->base + hwirq;
pcswi->hwirq = hwirq;
pcswi->irq = irq;
mutex_lock(&pcs->mutex);
list_add_tail(&pcswi->node, &pcs->irqs);
mutex_unlock(&pcs->mutex);
irq_set_chip_data(irq, pcs_soc);
irq_set_chip_and_handler(irq, &pcs->chip,
handle_level_irq);
irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops pcs_irqdomain_ops = {
.map = pcs_irqdomain_map,
.xlate = irq_domain_xlate_onecell,
};
/**
* pcs_irq_init_chained_handler() - set up a chained interrupt handler
* @pcs: pcs driver instance
* @np: device node pointer
*/
static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
struct device_node *np)
{
struct pcs_soc_data *pcs_soc = &pcs->socdata;
const char *name = "pinctrl";
int num_irqs;
if (!pcs_soc->irq_enable_mask ||
!pcs_soc->irq_status_mask) {
pcs_soc->irq = -1;
return -EINVAL;
}
INIT_LIST_HEAD(&pcs->irqs);
pcs->chip.name = name;
pcs->chip.irq_ack = pcs_irq_mask;
pcs->chip.irq_mask = pcs_irq_mask;
pcs->chip.irq_unmask = pcs_irq_unmask;
pcs->chip.irq_set_wake = pcs_irq_set_wake;
if (PCS_QUIRK_HAS_SHARED_IRQ) {
int res;
res = request_irq(pcs_soc->irq, pcs_irq_handler,
IRQF_SHARED | IRQF_NO_SUSPEND |
IRQF_NO_THREAD,
name, pcs_soc);
if (res) {
pcs_soc->irq = -1;
return res;
}
} else {
irq_set_chained_handler_and_data(pcs_soc->irq,
pcs_irq_chain_handler,
pcs_soc);
}
/*
* We can use the register offset as the hardirq
* number as irq_domain_add_simple maps them lazily.
* This way we can easily support more than one
* interrupt per function if needed.
*/
num_irqs = pcs->size;
pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
&pcs_irqdomain_ops,
pcs_soc);
if (!pcs->domain) {
irq_set_chained_handler(pcs_soc->irq, NULL);
return -EINVAL;
}
return 0;
}
#ifdef CONFIG_PM
static int pcs_save_context(struct pcs_device *pcs)
{
int i, mux_bytes;
u64 *regsl;
u32 *regsw;
u16 *regshw;
mux_bytes = pcs->width / BITS_PER_BYTE;
if (!pcs->saved_vals) {
pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
if (!pcs->saved_vals)
return -ENOMEM;
}
switch (pcs->width) {
case 64:
regsl = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regsl++ = pcs->read(pcs->base + i);
break;
case 32:
regsw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regsw++ = pcs->read(pcs->base + i);
break;
case 16:
regshw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regshw++ = pcs->read(pcs->base + i);
break;
}
return 0;
}
static void pcs_restore_context(struct pcs_device *pcs)
{
int i, mux_bytes;
u64 *regsl;
u32 *regsw;
u16 *regshw;
mux_bytes = pcs->width / BITS_PER_BYTE;
switch (pcs->width) {
case 64:
regsl = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regsl++, pcs->base + i);
break;
case 32:
regsw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regsw++, pcs->base + i);
break;
case 16:
regshw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regshw++, pcs->base + i);
break;
}
}
static int pinctrl_single_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct pcs_device *pcs;
pcs = platform_get_drvdata(pdev);
if (!pcs)
return -EINVAL;
if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
int ret;
ret = pcs_save_context(pcs);
if (ret < 0)
return ret;
}
return pinctrl_force_sleep(pcs->pctl);
}
static int pinctrl_single_resume(struct platform_device *pdev)
{
struct pcs_device *pcs;
pcs = platform_get_drvdata(pdev);
if (!pcs)
return -EINVAL;
if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
pcs_restore_context(pcs);
return pinctrl_force_default(pcs->pctl);
}
#endif
/**
* pcs_quirk_missing_pinctrl_cells - handle legacy binding
* @pcs: pinctrl driver instance
* @np: device tree node
* @cells: number of cells
*
* Handle legacy binding with no #pinctrl-cells. This should be
* always two pinctrl-single,bit-per-mux and one for others.
* At some point we may want to consider removing this.
*/
static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
struct device_node *np,
int cells)
{
struct property *p;
const char *name = "#pinctrl-cells";
int error;
u32 val;
error = of_property_read_u32(np, name, &val);
if (!error)
return 0;
dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
name, cells);
p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
p->length = sizeof(__be32);
p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
if (!p->value)
return -ENOMEM;
*(__be32 *)p->value = cpu_to_be32(cells);
p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
if (!p->name)
return -ENOMEM;
pcs->missing_nr_pinctrl_cells = p;
#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
#endif
return error;
}
static int pcs_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct pcs_pdata *pdata;
struct resource *res;
struct pcs_device *pcs;
const struct pcs_soc_data *soc;
int ret;
soc = of_device_get_match_data(&pdev->dev);
if (WARN_ON(!soc))
return -EINVAL;
pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
if (!pcs)
return -ENOMEM;
pcs->dev = &pdev->dev;
pcs->np = np;
raw_spin_lock_init(&pcs->lock);
mutex_init(&pcs->mutex);
INIT_LIST_HEAD(&pcs->gpiofuncs);
pcs->flags = soc->flags;
memcpy(&pcs->socdata, soc, sizeof(*soc));
ret = of_property_read_u32(np, "pinctrl-single,register-width",
&pcs->width);
if (ret) {
dev_err(pcs->dev, "register width not specified\n");
return ret;
}
ret = of_property_read_u32(np, "pinctrl-single,function-mask",
&pcs->fmask);
if (!ret) {
pcs->fshift = __ffs(pcs->fmask);
pcs->fmax = pcs->fmask >> pcs->fshift;
} else {
/* If mask property doesn't exist, function mux is invalid. */
pcs->fmask = 0;
pcs->fshift = 0;
pcs->fmax = 0;
}
ret = of_property_read_u32(np, "pinctrl-single,function-off",
&pcs->foff);
if (ret)
pcs->foff = PCS_OFF_DISABLED;
pcs->bits_per_mux = of_property_read_bool(np,
"pinctrl-single,bit-per-mux");
ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
pcs->bits_per_mux ? 2 : 1);
if (ret) {
dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
return ret;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(pcs->dev, "could not get resource\n");
return -ENODEV;
}
pcs->res = devm_request_mem_region(pcs->dev, res->start,
resource_size(res), DRIVER_NAME);
if (!pcs->res) {
dev_err(pcs->dev, "could not get mem_region\n");
return -EBUSY;
}
pcs->size = resource_size(pcs->res);
pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
if (!pcs->base) {
dev_err(pcs->dev, "could not ioremap\n");
return -ENODEV;
}
platform_set_drvdata(pdev, pcs);
switch (pcs->width) {
case 8:
pcs->read = pcs_readb;
pcs->write = pcs_writeb;
break;
case 16:
pcs->read = pcs_readw;
pcs->write = pcs_writew;
break;
case 32:
pcs->read = pcs_readl;
pcs->write = pcs_writel;
break;
default:
break;
}
pcs->desc.name = DRIVER_NAME;
pcs->desc.pctlops = &pcs_pinctrl_ops;
pcs->desc.pmxops = &pcs_pinmux_ops;
if (PCS_HAS_PINCONF)
pcs->desc.confops = &pcs_pinconf_ops;
pcs->desc.owner = THIS_MODULE;
ret = pcs_allocate_pin_table(pcs);
if (ret < 0)
goto free;
ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
if (ret) {
dev_err(pcs->dev, "could not register single pinctrl driver\n");
goto free;
}
ret = pcs_add_gpio_func(np, pcs);
if (ret < 0)
goto free;
pcs->socdata.irq = irq_of_parse_and_map(np, 0);
if (pcs->socdata.irq)
pcs->flags |= PCS_FEAT_IRQ;
/* We still need auxdata for some omaps for PRM interrupts */
pdata = dev_get_platdata(&pdev->dev);
if (pdata) {
if (pdata->rearm)
pcs->socdata.rearm = pdata->rearm;
if (pdata->irq) {
pcs->socdata.irq = pdata->irq;
pcs->flags |= PCS_FEAT_IRQ;
}
}
if (PCS_HAS_IRQ) {
ret = pcs_irq_init_chained_handler(pcs, np);
if (ret < 0)
dev_warn(pcs->dev, "initialized with no interrupts\n");
}
dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
return pinctrl_enable(pcs->pctl);
free:
pcs_free_resources(pcs);
return ret;
}
static int pcs_remove(struct platform_device *pdev)
{
struct pcs_device *pcs = platform_get_drvdata(pdev);
if (!pcs)
return 0;
pcs_free_resources(pcs);
return 0;
}
static const struct pcs_soc_data pinctrl_single_omap_wkup = {
.flags = PCS_QUIRK_SHARED_IRQ,
.irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
.irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
};
static const struct pcs_soc_data pinctrl_single_dra7 = {
.irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
.irq_status_mask = (1 << 25), /* WAKEUPEVENT */
};
static const struct pcs_soc_data pinctrl_single_am437x = {
.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
.irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
.irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
};
static const struct pcs_soc_data pinctrl_single_am654 = {
.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
.irq_enable_mask = (1 << 29), /* WKUP_EN */
.irq_status_mask = (1 << 30), /* WKUP_EVT */
};
static const struct pcs_soc_data pinctrl_single = {
};
static const struct pcs_soc_data pinconf_single = {
.flags = PCS_FEAT_PINCONF,
};
static const struct of_device_id pcs_of_match[] = {
{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
{ .compatible = "pinconf-single", .data = &pinconf_single },
{ },
};
MODULE_DEVICE_TABLE(of, pcs_of_match);
static struct platform_driver pcs_driver = {
.probe = pcs_probe,
.remove = pcs_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = pcs_of_match,
},
#ifdef CONFIG_PM
.suspend = pinctrl_single_suspend,
.resume = pinctrl_single_resume,
#endif
};
module_platform_driver(pcs_driver);
MODULE_AUTHOR("Tony Lindgren <[email protected]>");
MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
MODULE_LICENSE("GPL v2");
|
linux-master
|
drivers/pinctrl/pinctrl-single.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
*
* Copyright (C) 2022 9elements GmbH
* Authors: Patrick Rudolph <[email protected]>
* Naresh Solanki <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/dmi.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
/* Fast access registers */
#define CY8C95X0_INPUT 0x00
#define CY8C95X0_OUTPUT 0x08
#define CY8C95X0_INTSTATUS 0x10
#define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x))
#define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x))
#define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x))
/* Port Select configures the port */
#define CY8C95X0_PORTSEL 0x18
/* Port settings, write PORTSEL first */
#define CY8C95X0_INTMASK 0x19
#define CY8C95X0_PWMSEL 0x1A
#define CY8C95X0_INVERT 0x1B
#define CY8C95X0_DIRECTION 0x1C
/* Drive mode register change state on writing '1' */
#define CY8C95X0_DRV_PU 0x1D
#define CY8C95X0_DRV_PD 0x1E
#define CY8C95X0_DRV_ODH 0x1F
#define CY8C95X0_DRV_ODL 0x20
#define CY8C95X0_DRV_PP_FAST 0x21
#define CY8C95X0_DRV_PP_SLOW 0x22
#define CY8C95X0_DRV_HIZ 0x23
#define CY8C95X0_DEVID 0x2E
#define CY8C95X0_WATCHDOG 0x2F
#define CY8C95X0_COMMAND 0x30
#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
static const struct i2c_device_id cy8c95x0_id[] = {
{ "cy8c9520", 20, },
{ "cy8c9540", 40, },
{ "cy8c9560", 60, },
{ }
};
MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
static const struct of_device_id cy8c95x0_dt_ids[] = {
{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
{ }
};
MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
{ "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
{ }
};
static int cy8c95x0_acpi_get_irq(struct device *dev)
{
int ret;
ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios);
if (ret)
dev_warn(dev, "can't add GPIO ACPI mapping\n");
ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0);
if (ret < 0)
return ret;
dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
return ret;
}
static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
{
/*
* On Intel Galileo Gen 1 board the IRQ pin is provided
* as an absolute number instead of being relative.
* Since first controller (gpio-sch.c) and second
* (gpio-dwapb.c) are at the fixed bases, we may safely
* refer to the number in the global space to get an IRQ
* out of it.
*/
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
},
},
{}
};
#define MAX_BANK 8
#define BANK_SZ 8
#define MAX_LINE (MAX_BANK * BANK_SZ)
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
/**
* struct cy8c95x0_pinctrl - driver data
* @regmap: Device's regmap
* @irq_lock: IRQ bus lock
* @i2c_lock: Mutex for the device internal mux register
* @irq_mask: I/O bits affected by interrupts
* @irq_trig_raise: I/O bits affected by raising voltage level
* @irq_trig_fall: I/O bits affected by falling voltage level
* @irq_trig_low: I/O bits affected by a low voltage level
* @irq_trig_high: I/O bits affected by a high voltage level
* @push_pull: I/O bits configured as push pull driver
* @shiftmask: Mask used to compensate for Gport2 width
* @nport: Number of Gports in this chip
* @gpio_chip: gpiolib chip
* @driver_data: private driver data
* @regulator: Pointer to the regulator for the IC
* @dev: struct device
* @pctldev: pin controller device
* @pinctrl_desc: pin controller description
* @name: Chip controller name
* @tpin: Total number of pins
*/
struct cy8c95x0_pinctrl {
struct regmap *regmap;
struct mutex irq_lock;
struct mutex i2c_lock;
DECLARE_BITMAP(irq_mask, MAX_LINE);
DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
DECLARE_BITMAP(irq_trig_low, MAX_LINE);
DECLARE_BITMAP(irq_trig_high, MAX_LINE);
DECLARE_BITMAP(push_pull, MAX_LINE);
DECLARE_BITMAP(shiftmask, MAX_LINE);
int nport;
struct gpio_chip gpio_chip;
unsigned long driver_data;
struct regulator *regulator;
struct device *dev;
struct pinctrl_dev *pctldev;
struct pinctrl_desc pinctrl_desc;
char name[32];
unsigned int tpin;
struct gpio_desc *gpio_reset;
};
static const struct pinctrl_pin_desc cy8c9560_pins[] = {
PINCTRL_PIN(0, "gp00"),
PINCTRL_PIN(1, "gp01"),
PINCTRL_PIN(2, "gp02"),
PINCTRL_PIN(3, "gp03"),
PINCTRL_PIN(4, "gp04"),
PINCTRL_PIN(5, "gp05"),
PINCTRL_PIN(6, "gp06"),
PINCTRL_PIN(7, "gp07"),
PINCTRL_PIN(8, "gp10"),
PINCTRL_PIN(9, "gp11"),
PINCTRL_PIN(10, "gp12"),
PINCTRL_PIN(11, "gp13"),
PINCTRL_PIN(12, "gp14"),
PINCTRL_PIN(13, "gp15"),
PINCTRL_PIN(14, "gp16"),
PINCTRL_PIN(15, "gp17"),
PINCTRL_PIN(16, "gp20"),
PINCTRL_PIN(17, "gp21"),
PINCTRL_PIN(18, "gp22"),
PINCTRL_PIN(19, "gp23"),
PINCTRL_PIN(20, "gp30"),
PINCTRL_PIN(21, "gp31"),
PINCTRL_PIN(22, "gp32"),
PINCTRL_PIN(23, "gp33"),
PINCTRL_PIN(24, "gp34"),
PINCTRL_PIN(25, "gp35"),
PINCTRL_PIN(26, "gp36"),
PINCTRL_PIN(27, "gp37"),
PINCTRL_PIN(28, "gp40"),
PINCTRL_PIN(29, "gp41"),
PINCTRL_PIN(30, "gp42"),
PINCTRL_PIN(31, "gp43"),
PINCTRL_PIN(32, "gp44"),
PINCTRL_PIN(33, "gp45"),
PINCTRL_PIN(34, "gp46"),
PINCTRL_PIN(35, "gp47"),
PINCTRL_PIN(36, "gp50"),
PINCTRL_PIN(37, "gp51"),
PINCTRL_PIN(38, "gp52"),
PINCTRL_PIN(39, "gp53"),
PINCTRL_PIN(40, "gp54"),
PINCTRL_PIN(41, "gp55"),
PINCTRL_PIN(42, "gp56"),
PINCTRL_PIN(43, "gp57"),
PINCTRL_PIN(44, "gp60"),
PINCTRL_PIN(45, "gp61"),
PINCTRL_PIN(46, "gp62"),
PINCTRL_PIN(47, "gp63"),
PINCTRL_PIN(48, "gp64"),
PINCTRL_PIN(49, "gp65"),
PINCTRL_PIN(50, "gp66"),
PINCTRL_PIN(51, "gp67"),
PINCTRL_PIN(52, "gp70"),
PINCTRL_PIN(53, "gp71"),
PINCTRL_PIN(54, "gp72"),
PINCTRL_PIN(55, "gp73"),
PINCTRL_PIN(56, "gp74"),
PINCTRL_PIN(57, "gp75"),
PINCTRL_PIN(58, "gp76"),
PINCTRL_PIN(59, "gp77"),
};
static const char * const cy8c95x0_groups[] = {
"gp00",
"gp01",
"gp02",
"gp03",
"gp04",
"gp05",
"gp06",
"gp07",
"gp10",
"gp11",
"gp12",
"gp13",
"gp14",
"gp15",
"gp16",
"gp17",
"gp20",
"gp21",
"gp22",
"gp23",
"gp30",
"gp31",
"gp32",
"gp33",
"gp34",
"gp35",
"gp36",
"gp37",
"gp40",
"gp41",
"gp42",
"gp43",
"gp44",
"gp45",
"gp46",
"gp47",
"gp50",
"gp51",
"gp52",
"gp53",
"gp54",
"gp55",
"gp56",
"gp57",
"gp60",
"gp61",
"gp62",
"gp63",
"gp64",
"gp65",
"gp66",
"gp67",
"gp70",
"gp71",
"gp72",
"gp73",
"gp74",
"gp75",
"gp76",
"gp77",
};
static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin)
{
/* Account for GPORT2 which only has 4 bits */
return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;
}
static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
{
/* Account for GPORT2 which only has 4 bits */
return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);
}
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x24 ... 0x27:
return false;
default:
return true;
}
}
static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
return false;
case CY8C95X0_DEVID:
return false;
case 0x24 ... 0x27:
return false;
default:
return true;
}
}
static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
case CY8C95X0_INTMASK:
case CY8C95X0_INVERT:
case CY8C95X0_PWMSEL:
case CY8C95X0_DIRECTION:
case CY8C95X0_DRV_PU:
case CY8C95X0_DRV_PD:
case CY8C95X0_DRV_ODH:
case CY8C95X0_DRV_ODL:
case CY8C95X0_DRV_PP_FAST:
case CY8C95X0_DRV_PP_SLOW:
case CY8C95X0_DRV_HIZ:
return true;
default:
return false;
}
}
static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7):
return true;
default:
return false;
}
}
static const struct reg_default cy8c95x0_reg_defaults[] = {
{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
{ CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
{ CY8C95X0_PORTSEL, 0 },
{ CY8C95X0_PWMSEL, 0 },
};
static const struct regmap_config cy8c95x0_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = cy8c95x0_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
.readable_reg = cy8c95x0_readable_register,
.writeable_reg = cy8c95x0_writeable_register,
.volatile_reg = cy8c95x0_volatile_register,
.precious_reg = cy8c95x0_precious_register,
.cache_type = REGCACHE_FLAT,
.max_register = CY8C95X0_COMMAND,
};
static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
unsigned long *val, unsigned long *mask)
{
DECLARE_BITMAP(tmask, MAX_LINE);
DECLARE_BITMAP(tval, MAX_LINE);
int write_val;
int ret = 0;
int i, off = 0;
u8 bits;
/* Add the 4 bit gap of Gport2 */
bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
bitmap_shift_left(tval, tval, 4, MAX_LINE);
bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
mutex_lock(&chip->i2c_lock);
for (i = 0; i < chip->nport; i++) {
/* Skip over unused banks */
bits = bitmap_get_value8(tmask, i * BANK_SZ);
if (!bits)
continue;
switch (reg) {
/* Muxed registers */
case CY8C95X0_INTMASK:
case CY8C95X0_PWMSEL:
case CY8C95X0_INVERT:
case CY8C95X0_DIRECTION:
case CY8C95X0_DRV_PU:
case CY8C95X0_DRV_PD:
case CY8C95X0_DRV_ODH:
case CY8C95X0_DRV_ODL:
case CY8C95X0_DRV_PP_FAST:
case CY8C95X0_DRV_PP_SLOW:
case CY8C95X0_DRV_HIZ:
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
if (ret < 0)
goto out;
off = reg;
break;
/* Direct access registers */
case CY8C95X0_INPUT:
case CY8C95X0_OUTPUT:
case CY8C95X0_INTSTATUS:
off = reg + i;
break;
default:
ret = -EINVAL;
goto out;
}
write_val = bitmap_get_value8(tval, i * BANK_SZ);
ret = regmap_update_bits(chip->regmap, off, bits, write_val);
if (ret < 0)
goto out;
}
out:
mutex_unlock(&chip->i2c_lock);
if (ret < 0)
dev_err(chip->dev, "failed writing register %d: err %d\n", off, ret);
return ret;
}
static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
unsigned long *val, unsigned long *mask)
{
DECLARE_BITMAP(tmask, MAX_LINE);
DECLARE_BITMAP(tval, MAX_LINE);
DECLARE_BITMAP(tmp, MAX_LINE);
int read_val;
int ret = 0;
int i, off = 0;
u8 bits;
/* Add the 4 bit gap of Gport2 */
bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
bitmap_shift_left(tval, tval, 4, MAX_LINE);
bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
mutex_lock(&chip->i2c_lock);
for (i = 0; i < chip->nport; i++) {
/* Skip over unused banks */
bits = bitmap_get_value8(tmask, i * BANK_SZ);
if (!bits)
continue;
switch (reg) {
/* Muxed registers */
case CY8C95X0_INTMASK:
case CY8C95X0_PWMSEL:
case CY8C95X0_INVERT:
case CY8C95X0_DIRECTION:
case CY8C95X0_DRV_PU:
case CY8C95X0_DRV_PD:
case CY8C95X0_DRV_ODH:
case CY8C95X0_DRV_ODL:
case CY8C95X0_DRV_PP_FAST:
case CY8C95X0_DRV_PP_SLOW:
case CY8C95X0_DRV_HIZ:
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, i);
if (ret < 0)
goto out;
off = reg;
break;
/* Direct access registers */
case CY8C95X0_INPUT:
case CY8C95X0_OUTPUT:
case CY8C95X0_INTSTATUS:
off = reg + i;
break;
default:
ret = -EINVAL;
goto out;
}
ret = regmap_read(chip->regmap, off, &read_val);
if (ret < 0)
goto out;
read_val &= bits;
read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits;
bitmap_set_value8(tval, read_val, i * BANK_SZ);
}
/* Fill the 4 bit gap of Gport2 */
bitmap_shift_right(tmp, tval, 4, MAX_LINE);
bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
out:
mutex_unlock(&chip->i2c_lock);
if (ret < 0)
dev_err(chip->dev, "failed reading register %d: err %d\n", off, ret);
return ret;
}
static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
{
return pinctrl_gpio_direction_input(gc->base + off);
}
static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
unsigned int off, int val)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
u8 port = cypress_get_port(chip, off);
u8 outreg = CY8C95X0_OUTPUT_(port);
u8 bit = cypress_get_pin_mask(chip, off);
int ret;
/* Set output level */
ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
if (ret)
return ret;
return pinctrl_gpio_direction_output(gc->base + off);
}
static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
u8 inreg = CY8C95X0_INPUT_(cypress_get_port(chip, off));
u8 bit = cypress_get_pin_mask(chip, off);
u32 reg_val;
int ret;
ret = regmap_read(chip->regmap, inreg, ®_val);
if (ret < 0) {
/*
* NOTE:
* Diagnostic already emitted; that's all we should
* do unless gpio_*_value_cansleep() calls become different
* from their nonsleeping siblings (and report faults).
*/
return 0;
}
return !!(reg_val & bit);
}
static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
int val)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
u8 outreg = CY8C95X0_OUTPUT_(cypress_get_port(chip, off));
u8 bit = cypress_get_pin_mask(chip, off);
regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
}
static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
u8 port = cypress_get_port(chip, off);
u8 bit = cypress_get_pin_mask(chip, off);
u32 reg_val;
int ret;
mutex_lock(&chip->i2c_lock);
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
goto out;
ret = regmap_read(chip->regmap, CY8C95X0_DIRECTION, ®_val);
if (ret < 0)
goto out;
mutex_unlock(&chip->i2c_lock);
if (reg_val & bit)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
out:
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip,
unsigned int off,
unsigned long *config)
{
enum pin_config_param param = pinconf_to_config_param(*config);
u8 port = cypress_get_port(chip, off);
u8 bit = cypress_get_pin_mask(chip, off);
unsigned int reg;
u32 reg_val;
u16 arg = 0;
int ret;
mutex_lock(&chip->i2c_lock);
/* Select port */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
goto out;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
reg = CY8C95X0_DRV_PU;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
reg = CY8C95X0_DRV_PD;
break;
case PIN_CONFIG_BIAS_DISABLE:
reg = CY8C95X0_DRV_HIZ;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
reg = CY8C95X0_DRV_ODL;
break;
case PIN_CONFIG_DRIVE_OPEN_SOURCE:
reg = CY8C95X0_DRV_ODH;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
reg = CY8C95X0_DRV_PP_FAST;
break;
case PIN_CONFIG_INPUT_ENABLE:
reg = CY8C95X0_DIRECTION;
break;
case PIN_CONFIG_MODE_PWM:
reg = CY8C95X0_PWMSEL;
break;
case PIN_CONFIG_OUTPUT:
reg = CY8C95X0_OUTPUT_(port);
break;
case PIN_CONFIG_OUTPUT_ENABLE:
reg = CY8C95X0_DIRECTION;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
case PIN_CONFIG_BIAS_BUS_HOLD:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_DRIVE_STRENGTH_UA:
case PIN_CONFIG_INPUT_DEBOUNCE:
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
case PIN_CONFIG_MODE_LOW_POWER:
case PIN_CONFIG_PERSIST_STATE:
case PIN_CONFIG_POWER_SOURCE:
case PIN_CONFIG_SKEW_DELAY:
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
case PIN_CONFIG_SLEW_RATE:
default:
ret = -ENOTSUPP;
goto out;
}
/*
* Writing 1 to one of the drive mode registers will automatically
* clear conflicting set bits in the other drive mode registers.
*/
ret = regmap_read(chip->regmap, reg, ®_val);
if (reg_val & bit)
arg = 1;
*config = pinconf_to_config_packed(param, (u16)arg);
out:
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip,
unsigned int off,
unsigned long config)
{
u8 port = cypress_get_port(chip, off);
u8 bit = cypress_get_pin_mask(chip, off);
unsigned long param = pinconf_to_config_param(config);
unsigned int reg;
int ret;
mutex_lock(&chip->i2c_lock);
/* Select port */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
goto out;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
__clear_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_PU;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
__clear_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_PD;
break;
case PIN_CONFIG_BIAS_DISABLE:
__clear_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_HIZ;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
__clear_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_ODL;
break;
case PIN_CONFIG_DRIVE_OPEN_SOURCE:
__clear_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_ODH;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
__set_bit(off, chip->push_pull);
reg = CY8C95X0_DRV_PP_FAST;
break;
case PIN_CONFIG_MODE_PWM:
reg = CY8C95X0_PWMSEL;
break;
default:
ret = -ENOTSUPP;
goto out;
}
/*
* Writing 1 to one of the drive mode registers will automatically
* clear conflicting set bits in the other drive mode registers.
*/
ret = regmap_write_bits(chip->regmap, reg, bit, bit);
out:
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
}
static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
}
static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
{
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
struct device *dev = chip->dev;
int ret;
ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin);
if (ret)
dev_err(dev, "failed to add GPIO pin range\n");
return ret;
}
static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
{
struct gpio_chip *gc = &chip->gpio_chip;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->direction_input = cy8c95x0_gpio_direction_input;
gc->direction_output = cy8c95x0_gpio_direction_output;
gc->get = cy8c95x0_gpio_get_value;
gc->set = cy8c95x0_gpio_set_value;
gc->get_direction = cy8c95x0_gpio_get_direction;
gc->get_multiple = cy8c95x0_gpio_get_multiple;
gc->set_multiple = cy8c95x0_gpio_set_multiple;
gc->set_config = gpiochip_generic_config,
gc->can_sleep = true;
gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
gc->base = -1;
gc->ngpio = chip->tpin;
gc->parent = chip->dev;
gc->owner = THIS_MODULE;
gc->names = NULL;
gc->label = dev_name(chip->dev);
return devm_gpiochip_add_data(chip->dev, gc, chip);
}
static void cy8c95x0_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
set_bit(hwirq, chip->irq_mask);
gpiochip_disable_irq(gc, hwirq);
}
static void cy8c95x0_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
clear_bit(hwirq, chip->irq_mask);
}
static void cy8c95x0_irq_bus_lock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
mutex_lock(&chip->irq_lock);
}
static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
DECLARE_BITMAP(ones, MAX_LINE);
DECLARE_BITMAP(irq_mask, MAX_LINE);
DECLARE_BITMAP(reg_direction, MAX_LINE);
bitmap_fill(ones, MAX_LINE);
cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones);
/* Switch direction to input if needed */
cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask);
bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE);
bitmap_complement(irq_mask, irq_mask, MAX_LINE);
/* Look for any newly setup interrupt */
cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask);
mutex_unlock(&chip->irq_lock);
}
static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned int trig_type;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
trig_type = type;
break;
case IRQ_TYPE_LEVEL_HIGH:
trig_type = IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_LEVEL_LOW:
trig_type = IRQ_TYPE_EDGE_FALLING;
break;
default:
dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type);
return -EINVAL;
}
assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING);
assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING);
assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW);
assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH);
return 0;
}
static void cy8c95x0_irq_shutdown(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
clear_bit(hwirq, chip->irq_trig_raise);
clear_bit(hwirq, chip->irq_trig_fall);
clear_bit(hwirq, chip->irq_trig_low);
clear_bit(hwirq, chip->irq_trig_high);
}
static const struct irq_chip cy8c95x0_irqchip = {
.name = "cy8c95x0-irq",
.irq_mask = cy8c95x0_irq_mask,
.irq_unmask = cy8c95x0_irq_unmask,
.irq_bus_lock = cy8c95x0_irq_bus_lock,
.irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock,
.irq_set_type = cy8c95x0_irq_set_type,
.irq_shutdown = cy8c95x0_irq_shutdown,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending)
{
DECLARE_BITMAP(ones, MAX_LINE);
DECLARE_BITMAP(cur_stat, MAX_LINE);
DECLARE_BITMAP(new_stat, MAX_LINE);
DECLARE_BITMAP(trigger, MAX_LINE);
bitmap_fill(ones, MAX_LINE);
/* Read the current interrupt status from the device */
if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones))
return false;
/* Check latched inputs */
if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger))
return false;
/* Apply filter for rising/falling edge selection */
bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise,
cur_stat, MAX_LINE);
bitmap_and(pending, new_stat, trigger, MAX_LINE);
return !bitmap_empty(pending, MAX_LINE);
}
static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid)
{
struct cy8c95x0_pinctrl *chip = devid;
struct gpio_chip *gc = &chip->gpio_chip;
DECLARE_BITMAP(pending, MAX_LINE);
int nested_irq, level;
bool ret;
ret = cy8c95x0_irq_pending(chip, pending);
if (!ret)
return IRQ_RETVAL(0);
ret = 0;
for_each_set_bit(level, pending, MAX_LINE) {
/* Already accounted for 4bit gap in GPort2 */
nested_irq = irq_find_mapping(gc->irq.domain, level);
if (unlikely(nested_irq <= 0)) {
dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
continue;
}
if (test_bit(level, chip->irq_trig_low))
while (!cy8c95x0_gpio_get_value(gc, level))
handle_nested_irq(nested_irq);
else if (test_bit(level, chip->irq_trig_high))
while (cy8c95x0_gpio_get_value(gc, level))
handle_nested_irq(nested_irq);
else
handle_nested_irq(nested_irq);
ret = 1;
}
return IRQ_RETVAL(ret);
}
static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
return chip->tpin;
}
static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return cy8c95x0_groups[group];
}
static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = &cy8c9560_pins[group].number;
*num_pins = 1;
return 0;
}
static const char *cy8c95x0_get_fname(unsigned int selector)
{
if (selector == 0)
return "gpio";
else
return "pwm";
}
static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int pin)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
DECLARE_BITMAP(mask, MAX_LINE);
DECLARE_BITMAP(pwm, MAX_LINE);
bitmap_zero(mask, MAX_LINE);
__set_bit(pin, mask);
if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
seq_puts(s, "not available");
return;
}
seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
}
static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
.get_groups_count = cy8c95x0_pinctrl_get_groups_count,
.get_group_name = cy8c95x0_pinctrl_get_group_name,
.get_group_pins = cy8c95x0_pinctrl_get_group_pins,
#ifdef CONFIG_OF
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
#endif
.pin_dbg_show = cy8c95x0_pin_dbg_show,
};
static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector)
{
return cy8c95x0_get_fname(selector);
}
static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
{
return 2;
}
static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
*groups = cy8c95x0_groups;
*num_groups = chip->tpin;
return 0;
}
static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
{
u8 port = cypress_get_port(chip, off);
u8 bit = cypress_get_pin_mask(chip, off);
int ret;
/* Select port */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
return ret;
return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0);
}
static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
unsigned int selector, unsigned int group)
{
u8 port = cypress_get_port(chip, group);
u8 bit = cypress_get_pin_mask(chip, group);
int ret;
ret = cy8c95x0_set_mode(chip, group, selector);
if (ret < 0)
return ret;
if (selector == 0)
return 0;
/* Set direction to output & set output to 1 so that PWM can work */
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
if (ret < 0)
return ret;
return regmap_write_bits(chip->regmap, CY8C95X0_OUTPUT_(port), bit, bit);
}
static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
unsigned int group)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
int ret;
mutex_lock(&chip->i2c_lock);
ret = cy8c95x0_pinmux_mode(chip, selector, group);
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
int ret;
mutex_lock(&chip->i2c_lock);
ret = cy8c95x0_set_mode(chip, pin, false);
mutex_unlock(&chip->i2c_lock);
return ret;
}
static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
unsigned int pin, bool input)
{
u8 port = cypress_get_port(chip, pin);
u8 bit = cypress_get_pin_mask(chip, pin);
int ret;
/* Select port... */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret)
return ret;
/* ...then direction */
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0);
if (ret)
return ret;
/*
* Disable driving the pin by forcing it to HighZ. Only setting
* the direction register isn't sufficient in Push-Pull mode.
*/
if (input && test_bit(pin, chip->push_pull)) {
ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
if (ret)
return ret;
__clear_bit(pin, chip->push_pull);
}
return 0;
}
static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
int ret;
mutex_lock(&chip->i2c_lock);
ret = cy8c95x0_pinmux_direction(chip, pin, input);
mutex_unlock(&chip->i2c_lock);
return ret;
}
static const struct pinmux_ops cy8c95x0_pmxops = {
.get_functions_count = cy8c95x0_get_functions_count,
.get_function_name = cy8c95x0_get_function_name,
.get_function_groups = cy8c95x0_get_function_groups,
.set_mux = cy8c95x0_set_mux,
.gpio_request_enable = cy8c95x0_gpio_request_enable,
.gpio_set_direction = cy8c95x0_gpio_set_direction,
.strict = true,
};
static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
return cy8c95x0_gpio_get_pincfg(chip, pin, config);
}
static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
int ret = 0;
int i;
for (i = 0; i < num_configs; i++) {
ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]);
if (ret)
return ret;
}
return ret;
}
static const struct pinconf_ops cy8c95x0_pinconf_ops = {
.pin_config_get = cy8c95x0_pinconf_get,
.pin_config_set = cy8c95x0_pinconf_set,
.is_generic = true,
};
static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
{
struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
DECLARE_BITMAP(pending_irqs, MAX_LINE);
int ret;
mutex_init(&chip->irq_lock);
bitmap_zero(pending_irqs, MAX_LINE);
/* Read IRQ status register to clear all pending interrupts */
ret = cy8c95x0_irq_pending(chip, pending_irqs);
if (ret) {
dev_err(chip->dev, "failed to clear irq status register\n");
return ret;
}
/* Mask all interrupts */
bitmap_fill(chip->irq_mask, MAX_LINE);
gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip);
/* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL;
girq->num_parents = 0;
girq->parents = NULL;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
girq->threaded = true;
ret = devm_request_threaded_irq(chip->dev, irq,
NULL, cy8c95x0_irq_handler,
IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH,
dev_name(chip->dev), chip);
if (ret) {
dev_err(chip->dev, "failed to request irq %d\n", irq);
return ret;
}
dev_info(chip->dev, "Registered threaded IRQ\n");
return 0;
}
static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
{
struct pinctrl_desc *pd = &chip->pinctrl_desc;
pd->pctlops = &cy8c95x0_pinctrl_ops;
pd->confops = &cy8c95x0_pinconf_ops;
pd->pmxops = &cy8c95x0_pmxops;
pd->name = dev_name(chip->dev);
pd->pins = cy8c9560_pins;
pd->npins = chip->tpin;
pd->owner = THIS_MODULE;
chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
if (IS_ERR(chip->pctldev))
return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
"can't register controller\n");
return 0;
}
static int cy8c95x0_detect(struct i2c_client *client,
struct i2c_board_info *info)
{
struct i2c_adapter *adapter = client->adapter;
int ret;
const char *name;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -ENODEV;
ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID);
if (ret < 0)
return ret;
switch (ret & GENMASK(7, 4)) {
case 0x20:
name = cy8c95x0_id[0].name;
break;
case 0x40:
name = cy8c95x0_id[1].name;
break;
case 0x60:
name = cy8c95x0_id[2].name;
break;
default:
return -ENODEV;
}
dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr);
strscpy(info->type, name, I2C_NAME_SIZE);
return 0;
}
static int cy8c95x0_probe(struct i2c_client *client)
{
struct cy8c95x0_pinctrl *chip;
struct regulator *reg;
int ret;
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = &client->dev;
/* Set the device type */
chip->driver_data = (unsigned long)device_get_match_data(&client->dev);
if (!chip->driver_data)
chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data;
if (!chip->driver_data)
return -ENODEV;
i2c_set_clientdata(client, chip);
chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
switch (chip->tpin) {
case 20:
strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
break;
case 40:
strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
break;
case 60:
strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
break;
default:
return -ENODEV;
}
reg = devm_regulator_get(&client->dev, "vdd");
if (IS_ERR(reg)) {
if (PTR_ERR(reg) == -EPROBE_DEFER)
return -EPROBE_DEFER;
} else {
ret = regulator_enable(reg);
if (ret) {
dev_err(&client->dev, "failed to enable regulator vdd: %d\n", ret);
return ret;
}
chip->regulator = reg;
}
/* bring the chip out of reset if reset pin is provided */
chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(chip->gpio_reset)) {
ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset),
"Failed to get GPIO 'reset'\n");
goto err_exit;
} else if (chip->gpio_reset) {
usleep_range(1000, 2000);
gpiod_set_value_cansleep(chip->gpio_reset, 0);
usleep_range(250000, 300000);
gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
}
chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
goto err_exit;
}
bitmap_zero(chip->push_pull, MAX_LINE);
bitmap_zero(chip->shiftmask, MAX_LINE);
bitmap_set(chip->shiftmask, 0, 20);
mutex_init(&chip->i2c_lock);
if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
ret = cy8c95x0_acpi_get_irq(&client->dev);
if (ret > 0)
client->irq = ret;
}
if (client->irq) {
ret = cy8c95x0_irq_setup(chip, client->irq);
if (ret)
goto err_exit;
}
ret = cy8c95x0_setup_pinctrl(chip);
if (ret)
goto err_exit;
ret = cy8c95x0_setup_gpiochip(chip);
if (ret)
goto err_exit;
return 0;
err_exit:
if (!IS_ERR_OR_NULL(chip->regulator))
regulator_disable(chip->regulator);
return ret;
}
static void cy8c95x0_remove(struct i2c_client *client)
{
struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client);
if (!IS_ERR_OR_NULL(chip->regulator))
regulator_disable(chip->regulator);
}
static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
{ "INT3490", 40, },
{ }
};
MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
static struct i2c_driver cy8c95x0_driver = {
.driver = {
.name = "cy8c95x0-pinctrl",
.of_match_table = cy8c95x0_dt_ids,
.acpi_match_table = cy8c95x0_acpi_ids,
},
.probe = cy8c95x0_probe,
.remove = cy8c95x0_remove,
.id_table = cy8c95x0_id,
.detect = cy8c95x0_detect,
};
module_i2c_driver(cy8c95x0_driver);
MODULE_AUTHOR("Patrick Rudolph <[email protected]>");
MODULE_AUTHOR("Naresh Solanki <[email protected]>");
MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0");
MODULE_LICENSE("GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-cy8c95x0.c
|
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#define MLXBF3_NGPIOS_GPIO0 32
#define MLXBF3_MAX_GPIO_PINS 56
enum {
MLXBF3_GPIO_HW_MODE,
MLXBF3_GPIO_SW_MODE,
};
struct mlxbf3_pinctrl {
void __iomem *fw_ctrl_set0;
void __iomem *fw_ctrl_clr0;
void __iomem *fw_ctrl_set1;
void __iomem *fw_ctrl_clr1;
struct device *dev;
struct pinctrl_dev *pctl;
struct pinctrl_gpio_range gpio_range;
};
#define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
{ \
.name = "mlxbf3_gpio_range", \
.id = _id, \
.base = _gpiobase, \
.pin_base = _pinbase, \
.npins = _npins, \
}
static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = {
MLXBF3_GPIO_RANGE(0, 0, 480, 32),
MLXBF3_GPIO_RANGE(1, 32, 456, 24),
};
static const struct pinctrl_pin_desc mlxbf3_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
PINCTRL_PIN(48, "gpio48"),
PINCTRL_PIN(49, "gpio49"),
PINCTRL_PIN(50, "gpio50"),
PINCTRL_PIN(51, "gpio51"),
PINCTRL_PIN(52, "gpio52"),
PINCTRL_PIN(53, "gpio53"),
PINCTRL_PIN(54, "gpio54"),
PINCTRL_PIN(55, "gpio55"),
};
/*
* All single-pin functions can be mapped to any GPIO, however pinmux applies
* functions to pin groups and only those groups declared as supporting that
* function. To make this work we must put each pin in its own dummy group so
* that the functions can be described as applying to all pins.
* We use the same name as in the datasheet.
*/
static const char * const mlxbf3_pinctrl_single_group_names[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
"gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
};
static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev)
{
/* Number single-pin groups */
return MLXBF3_MAX_GPIO_PINS;
}
static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return mlxbf3_pinctrl_single_group_names[selector];
}
static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
/* return the dummy group for a single pin */
*pins = &selector;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = {
.get_groups_count = mlxbf3_get_groups_count,
.get_group_name = mlxbf3_get_group_name,
.get_group_pins = mlxbf3_get_group_pins,
};
/*
* Only 2 functions are supported and they apply to all pins:
* 1) Default hardware functionality
* 2) Software controlled GPIO
*/
static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" };
static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" };
static struct pinfunction mlxbf3_pmx_funcs[] = {
PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1),
PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1),
};
static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(mlxbf3_pmx_funcs);
}
static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
return mlxbf3_pmx_funcs[selector].name;
}
static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = mlxbf3_pmx_funcs[selector].groups;
*num_groups = MLXBF3_MAX_GPIO_PINS;
return 0;
}
static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned int group)
{
struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
if (selector == MLXBF3_GPIO_HW_MODE) {
if (group < MLXBF3_NGPIOS_GPIO0)
writel(BIT(group), priv->fw_ctrl_clr0);
else
writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
}
if (selector == MLXBF3_GPIO_SW_MODE) {
if (group < MLXBF3_NGPIOS_GPIO0)
writel(BIT(group), priv->fw_ctrl_set0);
else
writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
}
return 0;
}
static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
if (offset < MLXBF3_NGPIOS_GPIO0)
writel(BIT(offset), priv->fw_ctrl_set0);
else
writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
return 0;
}
static const struct pinmux_ops mlxbf3_pmx_ops = {
.get_functions_count = mlxbf3_pmx_get_funcs_count,
.get_function_name = mlxbf3_pmx_get_func_name,
.get_function_groups = mlxbf3_pmx_get_groups,
.set_mux = mlxbf3_pmx_set,
.gpio_request_enable = mlxbf3_gpio_request_enable,
};
static struct pinctrl_desc mlxbf3_pin_desc = {
.name = "pinctrl-mlxbf3",
.pins = mlxbf3_pins,
.npins = ARRAY_SIZE(mlxbf3_pins),
.pctlops = &mlxbf3_pinctrl_group_ops,
.pmxops = &mlxbf3_pmx_ops,
.owner = THIS_MODULE,
};
static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS);
static int mlxbf3_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mlxbf3_pinctrl *priv;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->fw_ctrl_set0))
return PTR_ERR(priv->fw_ctrl_set0);
priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(priv->fw_ctrl_set0))
return PTR_ERR(priv->fw_ctrl_set0);
priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(priv->fw_ctrl_set0))
return PTR_ERR(priv->fw_ctrl_set0);
priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
if (IS_ERR(priv->fw_ctrl_set0))
return PTR_ERR(priv->fw_ctrl_set0);
ret = devm_pinctrl_register_and_init(dev,
&mlxbf3_pin_desc,
priv,
&priv->pctl);
if (ret)
return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
ret = pinctrl_enable(priv->pctl);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable pinctrl\n");
pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2);
return 0;
}
static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = {
{ "MLNXBF34", 0 },
{}
};
MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids);
static struct platform_driver mlxbf3_pinctrl_driver = {
.driver = {
.name = "pinctrl-mlxbf3",
.acpi_match_table = mlxbf3_pinctrl_acpi_ids,
},
.probe = mlxbf3_pinctrl_probe,
};
module_platform_driver(mlxbf3_pinctrl_driver);
MODULE_DESCRIPTION("NVIDIA pinctrl driver");
MODULE_AUTHOR("Asmaa Mnebhi <[email protected]>");
MODULE_LICENSE("Dual BSD/GPL");
|
linux-master
|
drivers/pinctrl/pinctrl-mlxbf3.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for the pin muxing portions of the pin control subsystem
*
* Copyright (C) 2011-2012 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
* Based on bits of regulator core, gpio core and clk core
*
* Author: Linus Walleij <[email protected]>
*
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
*/
#define pr_fmt(fmt) "pinmux core: " fmt
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/radix-tree.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinmux.h"
int pinmux_check_ops(struct pinctrl_dev *pctldev)
{
const struct pinmux_ops *ops = pctldev->desc->pmxops;
unsigned nfuncs;
unsigned selector = 0;
/* Check that we implement required operations */
if (!ops ||
!ops->get_functions_count ||
!ops->get_function_name ||
!ops->get_function_groups ||
!ops->set_mux) {
dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
return -EINVAL;
}
/* Check that all functions registered have names */
nfuncs = ops->get_functions_count(pctldev);
while (selector < nfuncs) {
const char *fname = ops->get_function_name(pctldev,
selector);
if (!fname) {
dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
selector);
return -EINVAL;
}
selector++;
}
return 0;
}
int pinmux_validate_map(const struct pinctrl_map *map, int i)
{
if (!map->data.mux.function) {
pr_err("failed to register map %s (%d): no function given\n",
map->name, i);
return -EINVAL;
}
return 0;
}
/**
* pinmux_can_be_used_for_gpio() - check if a specific pin
* is either muxed to a different function or used as gpio.
*
* @pctldev: the associated pin controller device
* @pin: the pin number in the global pin space
*
* Controllers not defined as strict will always return true,
* menaning that the gpio can be used.
*/
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin)
{
struct pin_desc *desc = pin_desc_get(pctldev, pin);
const struct pinmux_ops *ops = pctldev->desc->pmxops;
/* Can't inspect pin, assume it can be used */
if (!desc || !ops)
return true;
if (ops->strict && desc->mux_usecount)
return false;
return !(ops->strict && !!desc->gpio_owner);
}
/**
* pin_request() - request a single pin to be muxed in, typically for GPIO
* @pctldev: the associated pin controller device
* @pin: the pin number in the global pin space
* @owner: a representation of the owner of this pin; typically the device
* name that controls its mux function, or the requested GPIO name
* @gpio_range: the range matching the GPIO pin if this is a request for a
* single GPIO pin
*/
static int pin_request(struct pinctrl_dev *pctldev,
int pin, const char *owner,
struct pinctrl_gpio_range *gpio_range)
{
struct pin_desc *desc;
const struct pinmux_ops *ops = pctldev->desc->pmxops;
int status = -EINVAL;
desc = pin_desc_get(pctldev, pin);
if (desc == NULL) {
dev_err(pctldev->dev,
"pin %d is not registered so it cannot be requested\n",
pin);
goto out;
}
dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
pin, desc->name, owner);
if ((!gpio_range || ops->strict) &&
desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
dev_err(pctldev->dev,
"pin %s already requested by %s; cannot claim for %s\n",
desc->name, desc->mux_owner, owner);
goto out;
}
if ((gpio_range || ops->strict) && desc->gpio_owner) {
dev_err(pctldev->dev,
"pin %s already requested by %s; cannot claim for %s\n",
desc->name, desc->gpio_owner, owner);
goto out;
}
if (gpio_range) {
desc->gpio_owner = owner;
} else {
desc->mux_usecount++;
if (desc->mux_usecount > 1)
return 0;
desc->mux_owner = owner;
}
/* Let each pin increase references to this module */
if (!try_module_get(pctldev->owner)) {
dev_err(pctldev->dev,
"could not increase module refcount for pin %d\n",
pin);
status = -EINVAL;
goto out_free_pin;
}
/*
* If there is no kind of request function for the pin we just assume
* we got it by default and proceed.
*/
if (gpio_range && ops->gpio_request_enable)
/* This requests and enables a single GPIO pin */
status = ops->gpio_request_enable(pctldev, gpio_range, pin);
else if (ops->request)
status = ops->request(pctldev, pin);
else
status = 0;
if (status) {
dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
module_put(pctldev->owner);
}
out_free_pin:
if (status) {
if (gpio_range) {
desc->gpio_owner = NULL;
} else {
desc->mux_usecount--;
if (!desc->mux_usecount)
desc->mux_owner = NULL;
}
}
out:
if (status)
dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
pin, owner, status);
return status;
}
/**
* pin_free() - release a single muxed in pin so something else can be muxed
* @pctldev: pin controller device handling this pin
* @pin: the pin to free
* @gpio_range: the range matching the GPIO pin if this is a request for a
* single GPIO pin
*
* This function returns a pointer to the previous owner. This is used
* for callers that dynamically allocate an owner name so it can be freed
* once the pin is free. This is done for GPIO request functions.
*/
static const char *pin_free(struct pinctrl_dev *pctldev, int pin,
struct pinctrl_gpio_range *gpio_range)
{
const struct pinmux_ops *ops = pctldev->desc->pmxops;
struct pin_desc *desc;
const char *owner;
desc = pin_desc_get(pctldev, pin);
if (desc == NULL) {
dev_err(pctldev->dev,
"pin is not registered so it cannot be freed\n");
return NULL;
}
if (!gpio_range) {
/*
* A pin should not be freed more times than allocated.
*/
if (WARN_ON(!desc->mux_usecount))
return NULL;
desc->mux_usecount--;
if (desc->mux_usecount)
return NULL;
}
/*
* If there is no kind of request function for the pin we just assume
* we got it by default and proceed.
*/
if (gpio_range && ops->gpio_disable_free)
ops->gpio_disable_free(pctldev, gpio_range, pin);
else if (ops->free)
ops->free(pctldev, pin);
if (gpio_range) {
owner = desc->gpio_owner;
desc->gpio_owner = NULL;
} else {
owner = desc->mux_owner;
desc->mux_owner = NULL;
desc->mux_setting = NULL;
}
module_put(pctldev->owner);
return owner;
}
/**
* pinmux_request_gpio() - request pinmuxing for a GPIO pin
* @pctldev: pin controller device affected
* @pin: the pin to mux in for GPIO
* @range: the applicable GPIO range
* @gpio: number of requested GPIO
*/
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin, unsigned gpio)
{
const char *owner;
int ret;
/* Conjure some name stating what chip and pin this is taken by */
owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio);
if (!owner)
return -ENOMEM;
ret = pin_request(pctldev, pin, owner, range);
if (ret < 0)
kfree(owner);
return ret;
}
/**
* pinmux_free_gpio() - release a pin from GPIO muxing
* @pctldev: the pin controller device for the pin
* @pin: the affected currently GPIO-muxed in pin
* @range: applicable GPIO range
*/
void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin,
struct pinctrl_gpio_range *range)
{
const char *owner;
owner = pin_free(pctldev, pin, range);
kfree(owner);
}
/**
* pinmux_gpio_direction() - set the direction of a single muxed-in GPIO pin
* @pctldev: the pin controller handling this pin
* @range: applicable GPIO range
* @pin: the affected GPIO pin in this controller
* @input: true if we set the pin as input, false for output
*/
int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin, bool input)
{
const struct pinmux_ops *ops;
int ret;
ops = pctldev->desc->pmxops;
if (ops->gpio_set_direction)
ret = ops->gpio_set_direction(pctldev, range, pin, input);
else
ret = 0;
return ret;
}
static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
const char *function)
{
const struct pinmux_ops *ops = pctldev->desc->pmxops;
unsigned nfuncs = ops->get_functions_count(pctldev);
unsigned selector = 0;
/* See if this pctldev has this function */
while (selector < nfuncs) {
const char *fname = ops->get_function_name(pctldev, selector);
if (!strcmp(function, fname))
return selector;
selector++;
}
return -EINVAL;
}
int pinmux_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
char const * const *groups;
unsigned num_groups;
int ret;
const char *group;
if (!pmxops) {
dev_err(pctldev->dev, "does not support mux function\n");
return -EINVAL;
}
ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
if (ret < 0) {
dev_err(pctldev->dev, "invalid function %s in map table\n",
map->data.mux.function);
return ret;
}
setting->data.mux.func = ret;
ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
&groups, &num_groups);
if (ret < 0) {
dev_err(pctldev->dev, "can't query groups for function %s\n",
map->data.mux.function);
return ret;
}
if (!num_groups) {
dev_err(pctldev->dev,
"function %s can't be selected on any group\n",
map->data.mux.function);
return -EINVAL;
}
if (map->data.mux.group) {
group = map->data.mux.group;
ret = match_string(groups, num_groups, group);
if (ret < 0) {
dev_err(pctldev->dev,
"invalid group \"%s\" for function \"%s\"\n",
group, map->data.mux.function);
return ret;
}
} else {
group = groups[0];
}
ret = pinctrl_get_group_selector(pctldev, group);
if (ret < 0) {
dev_err(pctldev->dev, "invalid group %s in map table\n",
map->data.mux.group);
return ret;
}
setting->data.mux.group = ret;
return 0;
}
void pinmux_free_setting(const struct pinctrl_setting *setting)
{
/* This function is currently unused */
}
int pinmux_enable_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
const struct pinmux_ops *ops = pctldev->desc->pmxops;
int ret = 0;
const unsigned *pins = NULL;
unsigned num_pins = 0;
int i;
struct pin_desc *desc;
if (pctlops->get_group_pins)
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
&pins, &num_pins);
if (ret) {
const char *gname;
/* errors only affect debug data, so just warn */
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"could not get pins for group %s\n",
gname);
num_pins = 0;
}
/* Try to allocate all pins in this group, one by one */
for (i = 0; i < num_pins; i++) {
ret = pin_request(pctldev, pins[i], setting->dev_name, NULL);
if (ret) {
const char *gname;
const char *pname;
desc = pin_desc_get(pctldev, pins[i]);
pname = desc ? desc->name : "non-existing";
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_err(pctldev->dev,
"could not request pin %d (%s) from group %s "
" on device %s\n",
pins[i], pname, gname,
pinctrl_dev_get_name(pctldev));
goto err_pin_request;
}
}
/* Now that we have acquired the pins, encode the mux setting */
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc == NULL) {
dev_warn(pctldev->dev,
"could not get pin desc for pin %d\n",
pins[i]);
continue;
}
desc->mux_setting = &(setting->data.mux);
}
ret = ops->set_mux(pctldev, setting->data.mux.func,
setting->data.mux.group);
if (ret)
goto err_set_mux;
return 0;
err_set_mux:
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc)
desc->mux_setting = NULL;
}
err_pin_request:
/* On error release all taken pins */
while (--i >= 0)
pin_free(pctldev, pins[i], NULL);
return ret;
}
void pinmux_disable_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
int ret = 0;
const unsigned *pins = NULL;
unsigned num_pins = 0;
int i;
struct pin_desc *desc;
if (pctlops->get_group_pins)
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group,
&pins, &num_pins);
if (ret) {
const char *gname;
/* errors only affect debug data, so just warn */
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"could not get pins for group %s\n",
gname);
num_pins = 0;
}
/* Flag the descs that no setting is active */
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc == NULL) {
dev_warn(pctldev->dev,
"could not get pin desc for pin %d\n",
pins[i]);
continue;
}
if (desc->mux_setting == &(setting->data.mux)) {
pin_free(pctldev, pins[i], NULL);
} else {
const char *gname;
gname = pctlops->get_group_name(pctldev,
setting->data.mux.group);
dev_warn(pctldev->dev,
"not freeing pin %d (%s) as part of "
"deactivating group %s - it is already "
"used for some other setting",
pins[i], desc->name, gname);
}
}
}
#ifdef CONFIG_DEBUG_FS
/* Called from pincontrol core */
static int pinmux_functions_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
unsigned nfuncs;
unsigned func_selector = 0;
if (!pmxops)
return 0;
mutex_lock(&pctldev->mutex);
nfuncs = pmxops->get_functions_count(pctldev);
while (func_selector < nfuncs) {
const char *func = pmxops->get_function_name(pctldev,
func_selector);
const char * const *groups;
unsigned num_groups;
int ret;
int i;
ret = pmxops->get_function_groups(pctldev, func_selector,
&groups, &num_groups);
if (ret) {
seq_printf(s, "function %s: COULD NOT GET GROUPS\n",
func);
func_selector++;
continue;
}
seq_printf(s, "function %d: %s, groups = [ ", func_selector, func);
for (i = 0; i < num_groups; i++)
seq_printf(s, "%s ", groups[i]);
seq_puts(s, "]\n");
func_selector++;
}
mutex_unlock(&pctldev->mutex);
return 0;
}
static int pinmux_pins_show(struct seq_file *s, void *what)
{
struct pinctrl_dev *pctldev = s->private;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
unsigned i, pin;
if (!pmxops)
return 0;
seq_puts(s, "Pinmux settings per pin\n");
if (pmxops->strict)
seq_puts(s,
"Format: pin (name): mux_owner|gpio_owner (strict) hog?\n");
else
seq_puts(s,
"Format: pin (name): mux_owner gpio_owner hog?\n");
mutex_lock(&pctldev->mutex);
/* The pin number can be retrived from the pin controller descriptor */
for (i = 0; i < pctldev->desc->npins; i++) {
struct pin_desc *desc;
bool is_hog = false;
pin = pctldev->desc->pins[i].number;
desc = pin_desc_get(pctldev, pin);
/* Skip if we cannot search the pin */
if (desc == NULL)
continue;
if (desc->mux_owner &&
!strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev)))
is_hog = true;
if (pmxops->strict) {
if (desc->mux_owner)
seq_printf(s, "pin %d (%s): device %s%s",
pin, desc->name, desc->mux_owner,
is_hog ? " (HOG)" : "");
else if (desc->gpio_owner)
seq_printf(s, "pin %d (%s): GPIO %s",
pin, desc->name, desc->gpio_owner);
else
seq_printf(s, "pin %d (%s): UNCLAIMED",
pin, desc->name);
} else {
/* For non-strict controllers */
seq_printf(s, "pin %d (%s): %s %s%s", pin, desc->name,
desc->mux_owner ? desc->mux_owner
: "(MUX UNCLAIMED)",
desc->gpio_owner ? desc->gpio_owner
: "(GPIO UNCLAIMED)",
is_hog ? " (HOG)" : "");
}
/* If mux: print function+group claiming the pin */
if (desc->mux_setting)
seq_printf(s, " function %s group %s\n",
pmxops->get_function_name(pctldev,
desc->mux_setting->func),
pctlops->get_group_name(pctldev,
desc->mux_setting->group));
else
seq_putc(s, '\n');
}
mutex_unlock(&pctldev->mutex);
return 0;
}
void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map)
{
seq_printf(s, "group %s\nfunction %s\n",
map->data.mux.group ? map->data.mux.group : "(default)",
map->data.mux.function);
}
void pinmux_show_setting(struct seq_file *s,
const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
seq_printf(s, "group: %s (%u) function: %s (%u)\n",
pctlops->get_group_name(pctldev, setting->data.mux.group),
setting->data.mux.group,
pmxops->get_function_name(pctldev, setting->data.mux.func),
setting->data.mux.func);
}
DEFINE_SHOW_ATTRIBUTE(pinmux_functions);
DEFINE_SHOW_ATTRIBUTE(pinmux_pins);
static ssize_t pinmux_select(struct file *file, const char __user *user_buf,
size_t len, loff_t *ppos)
{
struct seq_file *sfile = file->private_data;
struct pinctrl_dev *pctldev = sfile->private;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
const char *const *groups;
char *buf, *gname, *fname;
unsigned int num_groups;
int fsel, gsel, ret;
buf = memdup_user_nul(user_buf, len);
if (IS_ERR(buf))
return PTR_ERR(buf);
/* remove leading and trailing spaces of input buffer */
gname = strstrip(buf);
if (*gname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
/* find a separator which is a spacelike character */
for (fname = gname; !isspace(*fname); fname++) {
if (*fname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
}
*fname = '\0';
/* drop extra spaces between function and group names */
fname = skip_spaces(fname + 1);
if (*fname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
ret = pinmux_func_name_to_selector(pctldev, fname);
if (ret < 0) {
dev_err(pctldev->dev, "invalid function %s in map table\n", fname);
goto exit_free_buf;
}
fsel = ret;
ret = pmxops->get_function_groups(pctldev, fsel, &groups, &num_groups);
if (ret) {
dev_err(pctldev->dev, "no groups for function %d (%s)", fsel, fname);
goto exit_free_buf;
}
ret = match_string(groups, num_groups, gname);
if (ret < 0) {
dev_err(pctldev->dev, "invalid group %s", gname);
goto exit_free_buf;
}
ret = pinctrl_get_group_selector(pctldev, gname);
if (ret < 0)
goto exit_free_buf;
gsel = ret;
ret = pmxops->set_mux(pctldev, fsel, gsel);
if (ret) {
dev_err(pctldev->dev, "set_mux() failed: %d", ret);
goto exit_free_buf;
}
ret = len;
exit_free_buf:
kfree(buf);
return ret;
}
static int pinmux_select_open(struct inode *inode, struct file *file)
{
return single_open(file, NULL, inode->i_private);
}
static const struct file_operations pinmux_select_ops = {
.owner = THIS_MODULE,
.open = pinmux_select_open,
.write = pinmux_select,
.llseek = no_llseek,
.release = single_release,
};
void pinmux_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinmux-functions", 0444,
devroot, pctldev, &pinmux_functions_fops);
debugfs_create_file("pinmux-pins", 0444,
devroot, pctldev, &pinmux_pins_fops);
debugfs_create_file("pinmux-select", 0200,
devroot, pctldev, &pinmux_select_ops);
}
#endif /* CONFIG_DEBUG_FS */
#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS
/**
* pinmux_generic_get_function_count() - returns number of functions
* @pctldev: pin controller device
*/
int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev)
{
return pctldev->num_functions;
}
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_count);
/**
* pinmux_generic_get_function_name() - returns the function name
* @pctldev: pin controller device
* @selector: function number
*/
const char *
pinmux_generic_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct function_desc *function;
function = radix_tree_lookup(&pctldev->pin_function_tree,
selector);
if (!function)
return NULL;
return function->name;
}
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name);
/**
* pinmux_generic_get_function_groups() - gets the function groups
* @pctldev: pin controller device
* @selector: function number
* @groups: array of pin groups
* @num_groups: number of pin groups
*/
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct function_desc *function;
function = radix_tree_lookup(&pctldev->pin_function_tree,
selector);
if (!function) {
dev_err(pctldev->dev, "%s could not find function%i\n",
__func__, selector);
return -EINVAL;
}
*groups = function->group_names;
*num_groups = function->num_group_names;
return 0;
}
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_groups);
/**
* pinmux_generic_get_function() - returns a function based on the number
* @pctldev: pin controller device
* @selector: function number
*/
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct function_desc *function;
function = radix_tree_lookup(&pctldev->pin_function_tree,
selector);
if (!function)
return NULL;
return function;
}
EXPORT_SYMBOL_GPL(pinmux_generic_get_function);
/**
* pinmux_generic_add_function() - adds a function group
* @pctldev: pin controller device
* @name: name of the function
* @groups: array of pin groups
* @num_groups: number of pin groups
* @data: pin controller driver specific data
*/
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
const char *name,
const char * const *groups,
const unsigned int num_groups,
void *data)
{
struct function_desc *function;
int selector, error;
if (!name)
return -EINVAL;
selector = pinmux_func_name_to_selector(pctldev, name);
if (selector >= 0)
return selector;
selector = pctldev->num_functions;
function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL);
if (!function)
return -ENOMEM;
function->name = name;
function->group_names = groups;
function->num_group_names = num_groups;
function->data = data;
error = radix_tree_insert(&pctldev->pin_function_tree, selector, function);
if (error)
return error;
pctldev->num_functions++;
return selector;
}
EXPORT_SYMBOL_GPL(pinmux_generic_add_function);
/**
* pinmux_generic_remove_function() - removes a numbered function
* @pctldev: pin controller device
* @selector: function number
*
* Note that the caller must take care of locking.
*/
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct function_desc *function;
function = radix_tree_lookup(&pctldev->pin_function_tree,
selector);
if (!function)
return -ENOENT;
radix_tree_delete(&pctldev->pin_function_tree, selector);
devm_kfree(pctldev->dev, function);
pctldev->num_functions--;
return 0;
}
EXPORT_SYMBOL_GPL(pinmux_generic_remove_function);
/**
* pinmux_generic_free_functions() - removes all functions
* @pctldev: pin controller device
*
* Note that the caller must take care of locking. The pinctrl
* functions are allocated with devm_kzalloc() so no need to free
* them here.
*/
void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
{
struct radix_tree_iter iter;
void __rcu **slot;
radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0)
radix_tree_delete(&pctldev->pin_function_tree, iter.index);
pctldev->num_functions = 0;
}
#endif /* CONFIG_GENERIC_PINMUX_FUNCTIONS */
|
linux-master
|
drivers/pinctrl/pinmux.c
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
* Authors:
* Srinivas Kandagatla <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
/* PIO Block registers */
/* PIO output */
#define REG_PIO_POUT 0x00
/* Set bits of POUT */
#define REG_PIO_SET_POUT 0x04
/* Clear bits of POUT */
#define REG_PIO_CLR_POUT 0x08
/* PIO input */
#define REG_PIO_PIN 0x10
/* PIO configuration */
#define REG_PIO_PC(n) (0x20 + (n) * 0x10)
/* Set bits of PC[2:0] */
#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
/* Clear bits of PC[2:0] */
#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
/* PIO input comparison */
#define REG_PIO_PCOMP 0x50
/* Set bits of PCOMP */
#define REG_PIO_SET_PCOMP 0x54
/* Clear bits of PCOMP */
#define REG_PIO_CLR_PCOMP 0x58
/* PIO input comparison mask */
#define REG_PIO_PMASK 0x60
/* Set bits of PMASK */
#define REG_PIO_SET_PMASK 0x64
/* Clear bits of PMASK */
#define REG_PIO_CLR_PMASK 0x68
#define ST_GPIO_DIRECTION_BIDIR 0x1
#define ST_GPIO_DIRECTION_OUT 0x2
#define ST_GPIO_DIRECTION_IN 0x4
/*
* Packed style retime configuration.
* There are two registers cfg0 and cfg1 in this style for each bank.
* Each field in this register is 8 bit corresponding to 8 pins in the bank.
*/
#define RT_P_CFGS_PER_BANK 2
#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
/*
* Dedicated style retime Configuration register
* each register is dedicated per pin.
*/
#define RT_D_CFGS_PER_BANK 8
#define RT_D_CFG_CLK_SHIFT 0
#define RT_D_CFG_CLK_MASK (0x3 << 0)
#define RT_D_CFG_CLKNOTDATA_SHIFT 2
#define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
#define RT_D_CFG_DELAY_SHIFT 3
#define RT_D_CFG_DELAY_MASK (0xf << 3)
#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
#define RT_D_CFG_INVERTCLK_SHIFT 9
#define RT_D_CFG_INVERTCLK_MASK BIT(9)
#define RT_D_CFG_RETIME_SHIFT 10
#define RT_D_CFG_RETIME_MASK BIT(10)
/*
* Pinconf is represented in an opaque unsigned long variable.
* Below is the bit allocation details for each possible configuration.
* All the bit fields can be encapsulated into four variables
* (direction, retime-type, retime-clk, retime-delay)
*
* +----------------+
*[31:28]| reserved-3 |
* +----------------+-------------
*[27] | oe | |
* +----------------+ v
*[26] | pu | [Direction ]
* +----------------+ ^
*[25] | od | |
* +----------------+-------------
*[24] | reserved-2 |
* +----------------+-------------
*[23] | retime | |
* +----------------+ |
*[22] | retime-invclk | |
* +----------------+ v
*[21] |retime-clknotdat| [Retime-type ]
* +----------------+ ^
*[20] | retime-de | |
* +----------------+-------------
*[19:18]| retime-clk |------>[Retime-Clk ]
* +----------------+
*[17:16]| reserved-1 |
* +----------------+
*[15..0]| retime-delay |------>[Retime Delay]
* +----------------+
*/
#define ST_PINCONF_UNPACK(conf, param)\
((conf >> ST_PINCONF_ ##param ##_SHIFT) \
& ST_PINCONF_ ##param ##_MASK)
#define ST_PINCONF_PACK(conf, val, param) (conf |=\
((val & ST_PINCONF_ ##param ##_MASK) << \
ST_PINCONF_ ##param ##_SHIFT))
/* Output enable */
#define ST_PINCONF_OE_MASK 0x1
#define ST_PINCONF_OE_SHIFT 27
#define ST_PINCONF_OE BIT(27)
#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
/* Pull Up */
#define ST_PINCONF_PU_MASK 0x1
#define ST_PINCONF_PU_SHIFT 26
#define ST_PINCONF_PU BIT(26)
#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
/* Open Drain */
#define ST_PINCONF_OD_MASK 0x1
#define ST_PINCONF_OD_SHIFT 25
#define ST_PINCONF_OD BIT(25)
#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
#define ST_PINCONF_RT_MASK 0x1
#define ST_PINCONF_RT_SHIFT 23
#define ST_PINCONF_RT BIT(23)
#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
#define ST_PINCONF_RT_INVERTCLK_MASK 0x1
#define ST_PINCONF_RT_INVERTCLK_SHIFT 22
#define ST_PINCONF_RT_INVERTCLK BIT(22)
#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
#define ST_PINCONF_RT_CLKNOTDATA BIT(21)
#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
#define ST_PINCONF_RT_CLK_MASK 0x3
#define ST_PINCONF_RT_CLK_SHIFT 18
#define ST_PINCONF_RT_CLK BIT(18)
#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
/* RETIME_DELAY in Pico Secs */
#define ST_PINCONF_RT_DELAY_MASK 0xffff
#define ST_PINCONF_RT_DELAY_SHIFT 0
#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
#define ST_PINCONF_PACK_RT_DELAY(conf, val) \
ST_PINCONF_PACK(conf, val, RT_DELAY)
#define ST_GPIO_PINS_PER_BANK (8)
#define OF_GPIO_ARGS_MIN (4)
#define OF_RT_ARGS_MIN (2)
#define gpio_range_to_bank(chip) \
container_of(chip, struct st_gpio_bank, range)
#define pc_to_bank(pc) \
container_of(pc, struct st_gpio_bank, pc)
enum st_retime_style {
st_retime_style_none,
st_retime_style_packed,
st_retime_style_dedicated,
};
struct st_retime_dedicated {
struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
};
struct st_retime_packed {
struct regmap_field *clk1notclk0;
struct regmap_field *delay_0;
struct regmap_field *delay_1;
struct regmap_field *invertclk;
struct regmap_field *retime;
struct regmap_field *clknotdata;
struct regmap_field *double_edge;
};
struct st_pio_control {
u32 rt_pin_mask;
struct regmap_field *alt, *oe, *pu, *od;
/* retiming */
union {
struct st_retime_packed rt_p;
struct st_retime_dedicated rt_d;
} rt;
};
struct st_pctl_data {
const enum st_retime_style rt_style;
const unsigned int *input_delays;
const int ninput_delays;
const unsigned int *output_delays;
const int noutput_delays;
/* register offset information */
const int alt, oe, pu, od, rt;
};
struct st_pinconf {
int pin;
const char *name;
unsigned long config;
int altfunc;
};
struct st_pmx_func {
const char *name;
const char **groups;
unsigned ngroups;
};
struct st_pctl_group {
const char *name;
unsigned int *pins;
unsigned npins;
struct st_pinconf *pin_conf;
};
/*
* Edge triggers are not supported at hardware level, it is supported by
* software by exploiting the level trigger support in hardware.
* Software uses a virtual register (EDGE_CONF) for edge trigger configuration
* of each gpio pin in a GPIO bank.
*
* Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
* 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
*
* bit allocation per pin is:
* Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
* --------------------------------------------------------
* | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
* --------------------------------------------------------
*
* A pin can have one of following the values in its edge configuration field.
*
* ------- ----------------------------
* [0-3] - Description
* ------- ----------------------------
* 0000 - No edge IRQ.
* 0001 - Falling edge IRQ.
* 0010 - Rising edge IRQ.
* 0011 - Rising and Falling edge IRQ.
* ------- ----------------------------
*/
#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
#define ST_IRQ_EDGE_MASK 0xf
#define ST_IRQ_EDGE_FALLING BIT(0)
#define ST_IRQ_EDGE_RISING BIT(1)
#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
#define ST_IRQ_RISING_EDGE_CONF(pin) \
(ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
#define ST_IRQ_FALLING_EDGE_CONF(pin) \
(ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
#define ST_IRQ_BOTH_EDGE_CONF(pin) \
(ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
#define ST_IRQ_EDGE_CONF(conf, pin) \
(conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
struct st_gpio_bank {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
void __iomem *base;
struct st_pio_control pc;
unsigned long irq_edge_conf;
spinlock_t lock;
};
struct st_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
struct st_gpio_bank *banks;
int nbanks;
struct st_pmx_func *functions;
int nfunctions;
struct st_pctl_group *groups;
int ngroups;
struct regmap *regmap;
const struct st_pctl_data *data;
void __iomem *irqmux_base;
};
/* SOC specific data */
static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
static const struct st_pctl_data stih407_data = {
.rt_style = st_retime_style_dedicated,
.input_delays = stih407_delays,
.ninput_delays = ARRAY_SIZE(stih407_delays),
.output_delays = stih407_delays,
.noutput_delays = ARRAY_SIZE(stih407_delays),
.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};
static const struct st_pctl_data stih407_flashdata = {
.rt_style = st_retime_style_none,
.input_delays = stih407_delays,
.ninput_delays = ARRAY_SIZE(stih407_delays),
.output_delays = stih407_delays,
.noutput_delays = ARRAY_SIZE(stih407_delays),
.alt = 0,
.oe = -1, /* Not Available */
.pu = -1, /* Not Available */
.od = 60,
.rt = 100,
};
static struct st_pio_control *st_get_pio_control(
struct pinctrl_dev *pctldev, int pin)
{
struct pinctrl_gpio_range *range =
pinctrl_find_gpio_range_from_pin(pctldev, pin);
struct st_gpio_bank *bank = gpio_range_to_bank(range);
return &bank->pc;
}
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
return gpio/ST_GPIO_PINS_PER_BANK;
}
static inline int st_gpio_pin(int gpio)
{
return gpio%ST_GPIO_PINS_PER_BANK;
}
static void st_pinconf_set_config(struct st_pio_control *pc,
int pin, unsigned long config)
{
struct regmap_field *output_enable = pc->oe;
struct regmap_field *pull_up = pc->pu;
struct regmap_field *open_drain = pc->od;
unsigned int oe_value, pu_value, od_value;
unsigned long mask = BIT(pin);
if (output_enable) {
regmap_field_read(output_enable, &oe_value);
oe_value &= ~mask;
if (config & ST_PINCONF_OE)
oe_value |= mask;
regmap_field_write(output_enable, oe_value);
}
if (pull_up) {
regmap_field_read(pull_up, &pu_value);
pu_value &= ~mask;
if (config & ST_PINCONF_PU)
pu_value |= mask;
regmap_field_write(pull_up, pu_value);
}
if (open_drain) {
regmap_field_read(open_drain, &od_value);
od_value &= ~mask;
if (config & ST_PINCONF_OD)
od_value |= mask;
regmap_field_write(open_drain, od_value);
}
}
static void st_pctl_set_function(struct st_pio_control *pc,
int pin_id, int function)
{
struct regmap_field *alt = pc->alt;
unsigned int val;
int pin = st_gpio_pin(pin_id);
int offset = pin * 4;
if (!alt)
return;
regmap_field_read(alt, &val);
val &= ~(0xf << offset);
val |= function << offset;
regmap_field_write(alt, val);
}
static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
{
struct regmap_field *alt = pc->alt;
unsigned int val;
int offset = pin * 4;
if (!alt)
return 0;
regmap_field_read(alt, &val);
return (val >> offset) & 0xf;
}
static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
const struct st_pctl_data *data, unsigned long config)
{
const unsigned int *delay_times;
int num_delay_times, i, closest_index = -1;
unsigned int closest_divergence = UINT_MAX;
if (ST_PINCONF_UNPACK_OE(config)) {
delay_times = data->output_delays;
num_delay_times = data->noutput_delays;
} else {
delay_times = data->input_delays;
num_delay_times = data->ninput_delays;
}
for (i = 0; i < num_delay_times; i++) {
unsigned int divergence = abs(delay - delay_times[i]);
if (divergence == 0)
return i;
if (divergence < closest_divergence) {
closest_divergence = divergence;
closest_index = i;
}
}
pr_warn("Attempt to set delay %d, closest available %d\n",
delay, delay_times[closest_index]);
return closest_index;
}
static unsigned long st_pinconf_bit_to_delay(unsigned int index,
const struct st_pctl_data *data, unsigned long output)
{
const unsigned int *delay_times;
int num_delay_times;
if (output) {
delay_times = data->output_delays;
num_delay_times = data->noutput_delays;
} else {
delay_times = data->input_delays;
num_delay_times = data->ninput_delays;
}
if (index < num_delay_times) {
return delay_times[index];
} else {
pr_warn("Delay not found in/out delay list\n");
return 0;
}
}
static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
int enable, int pin)
{
unsigned int val = 0;
regmap_field_read(field, &val);
if (enable)
val |= BIT(pin);
else
val &= ~BIT(pin);
regmap_field_write(field, val);
}
static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
struct st_pio_control *pc, unsigned long config, int pin)
{
const struct st_pctl_data *data = info->data;
struct st_retime_packed *rt_p = &pc->rt.rt_p;
unsigned int delay;
st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
ST_PINCONF_UNPACK_RT_CLK(config), pin);
st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
st_regmap_field_bit_set_clear_pin(rt_p->retime,
ST_PINCONF_UNPACK_RT(config), pin);
delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
data, config);
/* 2 bit delay, lsb */
st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
/* 2 bit delay, msb */
st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
}
static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
struct st_pio_control *pc, unsigned long config, int pin)
{
int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
int clk = ST_PINCONF_UNPACK_RT_CLK(config);
int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
int retime = ST_PINCONF_UNPACK_RT(config);
unsigned long delay = st_pinconf_delay_to_bit(
ST_PINCONF_UNPACK_RT_DELAY(config),
info->data, config);
struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
unsigned long retime_config =
((clk) << RT_D_CFG_CLK_SHIFT) |
((delay) << RT_D_CFG_DELAY_SHIFT) |
((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
((retime) << RT_D_CFG_RETIME_SHIFT) |
((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
regmap_field_write(rt_d->rt[pin], retime_config);
}
static void st_pinconf_get_direction(struct st_pio_control *pc,
int pin, unsigned long *config)
{
unsigned int oe_value, pu_value, od_value;
if (pc->oe) {
regmap_field_read(pc->oe, &oe_value);
if (oe_value & BIT(pin))
ST_PINCONF_PACK_OE(*config);
}
if (pc->pu) {
regmap_field_read(pc->pu, &pu_value);
if (pu_value & BIT(pin))
ST_PINCONF_PACK_PU(*config);
}
if (pc->od) {
regmap_field_read(pc->od, &od_value);
if (od_value & BIT(pin))
ST_PINCONF_PACK_OD(*config);
}
}
static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
struct st_pio_control *pc, int pin, unsigned long *config)
{
const struct st_pctl_data *data = info->data;
struct st_retime_packed *rt_p = &pc->rt.rt_p;
unsigned int delay_bits, delay, delay0, delay1, val;
int output = ST_PINCONF_UNPACK_OE(*config);
if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
ST_PINCONF_PACK_RT(*config);
if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
ST_PINCONF_PACK_RT_CLK(*config, 1);
if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
ST_PINCONF_PACK_RT_INVERTCLK(*config);
regmap_field_read(rt_p->delay_0, &delay0);
regmap_field_read(rt_p->delay_1, &delay1);
delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
(((delay0 & BIT(pin)) ? 1 : 0));
delay = st_pinconf_bit_to_delay(delay_bits, data, output);
ST_PINCONF_PACK_RT_DELAY(*config, delay);
return 0;
}
static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
struct st_pio_control *pc, int pin, unsigned long *config)
{
unsigned int value;
unsigned long delay_bits, delay, rt_clk;
int output = ST_PINCONF_UNPACK_OE(*config);
struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
regmap_field_read(rt_d->rt[pin], &value);
rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
ST_PINCONF_PACK_RT_DELAY(*config, delay);
if (value & RT_D_CFG_CLKNOTDATA_MASK)
ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
if (value & RT_D_CFG_INVERTCLK_MASK)
ST_PINCONF_PACK_RT_INVERTCLK(*config);
if (value & RT_D_CFG_RETIME_MASK)
ST_PINCONF_PACK_RT(*config);
return 0;
}
/* GPIO related functions */
static inline void __st_gpio_set(struct st_gpio_bank *bank,
unsigned offset, int value)
{
if (value)
writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
else
writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
}
static void st_gpio_direction(struct st_gpio_bank *bank,
unsigned int gpio, unsigned int direction)
{
int offset = st_gpio_pin(gpio);
int i = 0;
/**
* There are three configuration registers (PIOn_PC0, PIOn_PC1
* and PIOn_PC2) for each port. These are used to configure the
* PIO port pins. Each pin can be configured as an input, output,
* bidirectional, or alternative function pin. Three bits, one bit
* from each of the three registers, configure the corresponding bit of
* the port. Valid bit settings is:
*
* PC2 PC1 PC0 Direction.
* 0 0 0 [Input Weak pull-up]
* 0 0 or 1 1 [Bidirection]
* 0 1 0 [Output]
* 1 0 0 [Input]
*
* PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
* individually.
*/
for (i = 0; i <= 2; i++) {
if (direction & BIT(i))
writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
else
writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
}
}
static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct st_gpio_bank *bank = gpiochip_get_data(chip);
return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
}
static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct st_gpio_bank *bank = gpiochip_get_data(chip);
__st_gpio_set(bank, offset, value);
}
static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
pinctrl_gpio_direction_input(chip->base + offset);
return 0;
}
static int st_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct st_gpio_bank *bank = gpiochip_get_data(chip);
__st_gpio_set(bank, offset, value);
pinctrl_gpio_direction_output(chip->base + offset);
return 0;
}
static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
struct st_gpio_bank *bank = gpiochip_get_data(chip);
struct st_pio_control pc = bank->pc;
unsigned long config;
unsigned int direction = 0;
unsigned int function;
unsigned int value;
int i = 0;
/* Alternate function direction is handled by Pinctrl */
function = st_pctl_get_pin_function(&pc, offset);
if (function) {
st_pinconf_get_direction(&pc, offset, &config);
if (ST_PINCONF_UNPACK_OE(config))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
/*
* GPIO direction is handled differently
* - See st_gpio_direction() above for an explanation
*/
for (i = 0; i <= 2; i++) {
value = readl(bank->base + REG_PIO_PC(i));
direction |= ((value >> offset) & 0x1) << i;
}
if (direction == ST_GPIO_DIRECTION_IN)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
/* Pinctrl Groups */
static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->ngroups;
}
static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->groups[selector].name;
}
static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector, const unsigned **pins, unsigned *npins)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pins;
*npins = info->groups[selector].npins;
return 0;
}
static inline const struct st_pctl_group *st_pctl_find_group_by_name(
const struct st_pinctrl *info, const char *name)
{
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name))
return &info->groups[i];
}
return NULL;
}
static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct st_pctl_group *grp;
struct device *dev = info->dev;
struct pinctrl_map *new_map;
struct device_node *parent;
int map_num, i;
grp = st_pctl_find_group_by_name(info, np->name);
if (!grp) {
dev_err(dev, "unable to find group for node %pOFn\n", np);
return -EINVAL;
}
map_num = grp->npins + 1;
new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);
if (!new_map)
return -ENOMEM;
parent = of_get_parent(np);
if (!parent) {
devm_kfree(dev, new_map);
return -EINVAL;
}
*map = new_map;
*num_maps = map_num;
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
new_map[0].data.mux.function = parent->name;
new_map[0].data.mux.group = np->name;
of_node_put(parent);
/* create config map per pin */
new_map++;
for (i = 0; i < grp->npins; i++) {
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[i].data.configs.group_or_pin =
pin_get_name(pctldev, grp->pins[i]);
new_map[i].data.configs.configs = &grp->pin_conf[i].config;
new_map[i].data.configs.num_configs = 1;
}
dev_info(dev, "maps: function %s group %s num %d\n",
(*map)->data.mux.function, grp->name, map_num);
return 0;
}
static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
}
static const struct pinctrl_ops st_pctlops = {
.get_groups_count = st_pctl_get_groups_count,
.get_group_pins = st_pctl_get_group_pins,
.get_group_name = st_pctl_get_group_name,
.dt_node_to_map = st_pctl_dt_node_to_map,
.dt_free_map = st_pctl_dt_free_map,
};
/* Pinmux */
static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->nfunctions;
}
static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->functions[selector].name;
}
static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
unsigned selector, const char * const **grps, unsigned * const ngrps)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*grps = info->functions[selector].groups;
*ngrps = info->functions[selector].ngroups;
return 0;
}
static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pinconf *conf = info->groups[group].pin_conf;
struct st_pio_control *pc;
int i;
for (i = 0; i < info->groups[group].npins; i++) {
pc = st_get_pio_control(pctldev, conf[i].pin);
st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
}
return 0;
}
static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned gpio,
bool input)
{
struct st_gpio_bank *bank = gpio_range_to_bank(range);
/*
* When a PIO bank is used in its primary function mode (altfunc = 0)
* Output Enable (OE), Open Drain(OD), and Pull Up (PU)
* for the primary PIO functions are driven by the related PIO block
*/
st_pctl_set_function(&bank->pc, gpio, 0);
st_gpio_direction(bank, gpio, input ?
ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
return 0;
}
static const struct pinmux_ops st_pmxops = {
.get_functions_count = st_pmx_get_funcs_count,
.get_function_name = st_pmx_get_fname,
.get_function_groups = st_pmx_get_groups,
.set_mux = st_pmx_set_mux,
.gpio_set_direction = st_pmx_set_gpio_direction,
.strict = true,
};
/* Pinconf */
static void st_pinconf_get_retime(struct st_pinctrl *info,
struct st_pio_control *pc, int pin, unsigned long *config)
{
if (info->data->rt_style == st_retime_style_packed)
st_pinconf_get_retime_packed(info, pc, pin, config);
else if (info->data->rt_style == st_retime_style_dedicated)
if ((BIT(pin) & pc->rt_pin_mask))
st_pinconf_get_retime_dedicated(info, pc,
pin, config);
}
static void st_pinconf_set_retime(struct st_pinctrl *info,
struct st_pio_control *pc, int pin, unsigned long config)
{
if (info->data->rt_style == st_retime_style_packed)
st_pinconf_set_retime_packed(info, pc, config, pin);
else if (info->data->rt_style == st_retime_style_dedicated)
if ((BIT(pin) & pc->rt_pin_mask))
st_pinconf_set_retime_dedicated(info, pc,
config, pin);
}
static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
{
int pin = st_gpio_pin(pin_id);
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
int i;
for (i = 0; i < num_configs; i++) {
st_pinconf_set_config(pc, pin, configs[i]);
st_pinconf_set_retime(info, pc, pin, configs[i]);
} /* for each config */
return 0;
}
static int st_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
int pin = st_gpio_pin(pin_id);
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
*config = 0;
st_pinconf_get_direction(pc, pin, config);
st_pinconf_get_retime(info, pc, pin, config);
return 0;
}
static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct st_pio_control *pc;
unsigned long config;
unsigned int function;
int offset = st_gpio_pin(pin_id);
char f[16];
int oe;
mutex_unlock(&pctldev->mutex);
pc = st_get_pio_control(pctldev, pin_id);
st_pinconf_get(pctldev, pin_id, &config);
mutex_lock(&pctldev->mutex);
function = st_pctl_get_pin_function(pc, offset);
if (function)
snprintf(f, 10, "Alt Fn %u", function);
else
snprintf(f, 5, "GPIO");
oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
"de:%ld,rt-clk:%ld,rt-delay:%ld]",
(oe == GPIO_LINE_DIRECTION_OUT),
ST_PINCONF_UNPACK_PU(config),
ST_PINCONF_UNPACK_OD(config),
f,
ST_PINCONF_UNPACK_RT(config),
ST_PINCONF_UNPACK_RT_INVERTCLK(config),
ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
ST_PINCONF_UNPACK_RT_CLK(config),
ST_PINCONF_UNPACK_RT_DELAY(config));
}
static const struct pinconf_ops st_confops = {
.pin_config_get = st_pinconf_get,
.pin_config_set = st_pinconf_set,
.pin_config_dbg_show = st_pinconf_dbg_show,
};
static void st_pctl_dt_child_count(struct st_pinctrl *info,
struct device_node *np)
{
struct device_node *child;
for_each_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
info->nbanks++;
} else {
info->nfunctions++;
info->ngroups += of_get_child_count(child);
}
}
}
static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
int bank, struct st_pio_control *pc)
{
struct device *dev = info->dev;
struct regmap *rm = info->regmap;
const struct st_pctl_data *data = info->data;
/* 2 registers per bank */
int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
struct st_retime_packed *rt_p = &pc->rt.rt_p;
/* cfg0 */
struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
/* cfg1 */
struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
IS_ERR(rt_p->double_edge))
return -EINVAL;
return 0;
}
static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
int bank, struct st_pio_control *pc)
{
struct device *dev = info->dev;
struct regmap *rm = info->regmap;
const struct st_pctl_data *data = info->data;
/* 8 registers per bank */
int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
unsigned int j;
u32 pin_mask = pc->rt_pin_mask;
for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
if (BIT(j) & pin_mask) {
struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
if (IS_ERR(rt_d->rt[j]))
return -EINVAL;
reg_offset += 4;
}
}
return 0;
}
static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
int bank, struct st_pio_control *pc)
{
const struct st_pctl_data *data = info->data;
if (data->rt_style == st_retime_style_packed)
return st_pctl_dt_setup_retime_packed(info, bank, pc);
else if (data->rt_style == st_retime_style_dedicated)
return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
return -EINVAL;
}
static struct regmap_field *st_pc_get_value(struct device *dev,
struct regmap *regmap, int bank,
int data, int lsb, int msb)
{
struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
if (data < 0)
return NULL;
return devm_regmap_field_alloc(dev, regmap, reg);
}
static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
struct device_node *np)
{
const struct st_pctl_data *data = info->data;
/**
* For a given shared register like OE/PU/OD, there are 8 bits per bank
* 0:7 belongs to bank0, 8:15 belongs to bank1 ...
* So each register is shared across 4 banks.
*/
int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
struct st_pio_control *pc = &info->banks[bank].pc;
struct device *dev = info->dev;
struct regmap *regmap = info->regmap;
pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
/* retime avaiable for all pins by default */
pc->rt_pin_mask = 0xff;
of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
st_pctl_dt_setup_retime(info, bank, pc);
return;
}
static int st_pctl_dt_calculate_pin(struct st_pinctrl *info,
phandle bank, unsigned int offset)
{
struct device_node *np;
struct gpio_chip *chip;
int retval = -EINVAL;
int i;
np = of_find_node_by_phandle(bank);
if (!np)
return -EINVAL;
for (i = 0; i < info->nbanks; i++) {
chip = &info->banks[i].gpio_chip;
if (chip->fwnode == of_fwnode_handle(np)) {
if (offset < chip->ngpio)
retval = chip->base + offset;
break;
}
}
of_node_put(np);
return retval;
}
/*
* Each pin is represented in of the below forms.
* <bank offset mux direction rt_type rt_delay rt_clk>
*/
static int st_pctl_dt_parse_groups(struct device_node *np,
struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
{
/* bank pad direction val altfunction */
const __be32 *list;
struct property *pp;
struct device *dev = info->dev;
struct st_pinconf *conf;
struct device_node *pins;
phandle bank;
unsigned int offset;
int i = 0, npins = 0, nr_props, ret = 0;
pins = of_get_child_by_name(np, "st,pins");
if (!pins)
return -ENODATA;
for_each_property_of_node(pins, pp) {
/* Skip those we do not want to proceed */
if (!strcmp(pp->name, "name"))
continue;
if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
npins++;
} else {
pr_warn("Invalid st,pins in %pOFn node\n", np);
ret = -EINVAL;
goto out_put_node;
}
}
grp->npins = npins;
grp->name = np->name;
grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
if (!grp->pins || !grp->pin_conf) {
ret = -ENOMEM;
goto out_put_node;
}
/* <bank offset mux direction rt_type rt_delay rt_clk> */
for_each_property_of_node(pins, pp) {
if (!strcmp(pp->name, "name"))
continue;
nr_props = pp->length/sizeof(u32);
list = pp->value;
conf = &grp->pin_conf[i];
/* bank & offset */
bank = be32_to_cpup(list++);
offset = be32_to_cpup(list++);
conf->pin = st_pctl_dt_calculate_pin(info, bank, offset);
conf->name = pp->name;
grp->pins[i] = conf->pin;
/* mux */
conf->altfunc = be32_to_cpup(list++);
conf->config = 0;
/* direction */
conf->config |= be32_to_cpup(list++);
/* rt_type rt_delay rt_clk */
if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
/* rt_type */
conf->config |= be32_to_cpup(list++);
/* rt_delay */
conf->config |= be32_to_cpup(list++);
/* rt_clk */
if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
conf->config |= be32_to_cpup(list++);
}
i++;
}
out_put_node:
of_node_put(pins);
return ret;
}
static int st_pctl_parse_functions(struct device_node *np,
struct st_pinctrl *info, u32 index, int *grp_index)
{
struct device *dev = info->dev;
struct device_node *child;
struct st_pmx_func *func;
struct st_pctl_group *grp;
int ret, i;
func = &info->functions[index];
func->name = np->name;
func->ngroups = of_get_child_count(np);
if (func->ngroups == 0)
return dev_err_probe(dev, -EINVAL, "No groups defined\n");
func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
i = 0;
for_each_child_of_node(np, child) {
func->groups[i] = child->name;
grp = &info->groups[*grp_index];
*grp_index += 1;
ret = st_pctl_dt_parse_groups(child, grp, info, i++);
if (ret) {
of_node_put(child);
return ret;
}
}
dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
return 0;
}
static void st_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct st_gpio_bank *bank = gpiochip_get_data(gc);
writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}
static void st_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct st_gpio_bank *bank = gpiochip_get_data(gc);
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);
}
static int st_gpio_irq_request_resources(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
st_gpio_direction_input(gc, d->hwirq);
return gpiochip_reqres_irq(gc, d->hwirq);
}
static void st_gpio_irq_release_resources(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
gpiochip_relres_irq(gc, d->hwirq);
}
static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct st_gpio_bank *bank = gpiochip_get_data(gc);
unsigned long flags;
int comp, pin = d->hwirq;
u32 val;
u32 pin_edge_conf = 0;
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
comp = 0;
break;
case IRQ_TYPE_EDGE_FALLING:
comp = 0;
pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
break;
case IRQ_TYPE_LEVEL_LOW:
comp = 1;
break;
case IRQ_TYPE_EDGE_RISING:
comp = 1;
pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
break;
case IRQ_TYPE_EDGE_BOTH:
comp = st_gpio_get(&bank->gpio_chip, pin);
pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&bank->lock, flags);
bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
bank->irq_edge_conf |= pin_edge_conf;
spin_unlock_irqrestore(&bank->lock, flags);
val = readl(bank->base + REG_PIO_PCOMP);
val &= ~BIT(pin);
val |= (comp << pin);
writel(val, bank->base + REG_PIO_PCOMP);
return 0;
}
/*
* As edge triggers are not supported at hardware level, it is supported by
* software by exploiting the level trigger support in hardware.
*
* Steps for detection raising edge interrupt in software.
*
* Step 1: CONFIGURE pin to detect level LOW interrupts.
*
* Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
* if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
* IGNORE calling the actual interrupt handler for the pin at this stage.
*
* Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
* if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
* DISPATCH the interrupt to the interrupt handler of the pin.
*
* step-1 ________ __________
* | | step - 3
* | |
* step -2 |_____|
*
* falling edge is also detected int the same way.
*
*/
static void __gpio_irq_handler(struct st_gpio_bank *bank)
{
unsigned long port_in, port_mask, port_comp, active_irqs;
unsigned long bank_edge_mask, flags;
int n, val, ecfg;
spin_lock_irqsave(&bank->lock, flags);
bank_edge_mask = bank->irq_edge_conf;
spin_unlock_irqrestore(&bank->lock, flags);
for (;;) {
port_in = readl(bank->base + REG_PIO_PIN);
port_comp = readl(bank->base + REG_PIO_PCOMP);
port_mask = readl(bank->base + REG_PIO_PMASK);
active_irqs = (port_in ^ port_comp) & port_mask;
if (active_irqs == 0)
break;
for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
/* check if we are detecting fake edges ... */
ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
if (ecfg) {
/* edge detection. */
val = st_gpio_get(&bank->gpio_chip, n);
writel(BIT(n),
val ? bank->base + REG_PIO_SET_PCOMP :
bank->base + REG_PIO_CLR_PCOMP);
if (ecfg != ST_IRQ_EDGE_BOTH &&
!((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
continue;
}
generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
}
}
}
static void st_gpio_irq_handler(struct irq_desc *desc)
{
/* interrupt dedicated per bank */
struct irq_chip *chip = irq_desc_get_chip(desc);
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct st_gpio_bank *bank = gpiochip_get_data(gc);
chained_irq_enter(chip, desc);
__gpio_irq_handler(bank);
chained_irq_exit(chip, desc);
}
static void st_gpio_irqmux_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct st_pinctrl *info = irq_desc_get_handler_data(desc);
unsigned long status;
int n;
chained_irq_enter(chip, desc);
status = readl(info->irqmux_base);
for_each_set_bit(n, &status, info->nbanks)
__gpio_irq_handler(&info->banks[n]);
chained_irq_exit(chip, desc);
}
static const struct gpio_chip st_gpio_template = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get = st_gpio_get,
.set = st_gpio_set,
.direction_input = st_gpio_direction_input,
.direction_output = st_gpio_direction_output,
.get_direction = st_gpio_get_direction,
.ngpio = ST_GPIO_PINS_PER_BANK,
};
static const struct irq_chip st_gpio_irqchip = {
.name = "GPIO",
.irq_request_resources = st_gpio_irq_request_resources,
.irq_release_resources = st_gpio_irq_release_resources,
.irq_disable = st_gpio_irq_mask,
.irq_mask = st_gpio_irq_mask,
.irq_unmask = st_gpio_irq_unmask,
.irq_set_type = st_gpio_irq_set_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
};
static int st_gpiolib_register_bank(struct st_pinctrl *info,
int bank_nr, struct device_node *np)
{
struct st_gpio_bank *bank = &info->banks[bank_nr];
struct pinctrl_gpio_range *range = &bank->range;
struct device *dev = info->dev;
int bank_num = of_alias_get_id(np, "gpio");
struct resource res, irq_res;
int err;
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
bank->base = devm_ioremap_resource(dev, &res);
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
bank->gpio_chip = st_gpio_template;
bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
bank->gpio_chip.fwnode = of_fwnode_handle(np);
bank->gpio_chip.parent = dev;
spin_lock_init(&bank->lock);
of_property_read_string(np, "st,bank-name", &range->name);
bank->gpio_chip.label = range->name;
range->id = bank_num;
range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
range->npins = bank->gpio_chip.ngpio;
range->gc = &bank->gpio_chip;
/**
* GPIO bank can have one of the two possible types of
* interrupt-wirings.
*
* First type is via irqmux, single interrupt is used by multiple
* gpio banks. This reduces number of overall interrupts numbers
* required. All these banks belong to a single pincontroller.
* _________
* | |----> [gpio-bank (n) ]
* | |----> [gpio-bank (n + 1)]
* [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
* | |----> [gpio-bank (... )]
* |_________|----> [gpio-bank (n + 7)]
*
* Second type has a dedicated interrupt per each gpio bank.
*
* [irqN]----> [gpio-bank (n)]
*/
if (of_irq_to_resource(np, 0, &irq_res) > 0) {
struct gpio_irq_chip *girq;
int gpio_irq = irq_res.start;
/* This is not a valid IRQ */
if (gpio_irq <= 0) {
dev_err(dev, "invalid IRQ for %pOF bank\n", np);
goto skip_irq;
}
/* We need to have a mux as well */
if (!info->irqmux_base) {
dev_err(dev, "no irqmux for %pOF bank\n", np);
goto skip_irq;
}
girq = &bank->gpio_chip.irq;
gpio_irq_chip_set_chip(girq, &st_gpio_irqchip);
girq->parent_handler = st_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = gpio_irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
}
skip_irq:
err = gpiochip_add_data(&bank->gpio_chip, bank);
if (err)
return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);
dev_info(dev, "%s bank added.\n", range->name);
return 0;
}
static const struct of_device_id st_pctl_of_match[] = {
{ .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
{ .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
{ .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
{ .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
{ /* sentinel */ }
};
static int st_pctl_probe_dt(struct platform_device *pdev,
struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
{
struct device *dev = &pdev->dev;
int ret = 0;
int i = 0, j = 0, k = 0, bank;
struct pinctrl_pin_desc *pdesc;
struct device_node *np = dev->of_node;
struct device_node *child;
int grp_index = 0;
int irq = 0;
st_pctl_dt_child_count(info, np);
if (!info->nbanks)
return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
dev_info(dev, "nbanks = %d\n", info->nbanks);
dev_info(dev, "nfunctions = %d\n", info->nfunctions);
dev_info(dev, "ngroups = %d\n", info->ngroups);
info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
if (!info->functions || !info->groups || !info->banks)
return -ENOMEM;
info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(info->regmap))
return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");
info->data = of_match_node(st_pctl_of_match, np)->data;
irq = platform_get_irq(pdev, 0);
if (irq > 0) {
info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");
if (IS_ERR(info->irqmux_base))
return PTR_ERR(info->irqmux_base);
irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
info);
}
pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
if (!pdesc)
return -ENOMEM;
pctl_desc->pins = pdesc;
bank = 0;
for_each_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
const char *bank_name = NULL;
char **pin_names;
ret = st_gpiolib_register_bank(info, bank, child);
if (ret) {
of_node_put(child);
return ret;
}
k = info->banks[bank].range.pin_base;
bank_name = info->banks[bank].range.name;
pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
if (IS_ERR(pin_names)) {
of_node_put(child);
return PTR_ERR(pin_names);
}
for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
pdesc->number = k;
pdesc->name = pin_names[j];
pdesc++;
}
st_parse_syscfgs(info, bank, child);
bank++;
} else {
ret = st_pctl_parse_functions(child, info,
i++, &grp_index);
if (ret) {
dev_err(dev, "No functions found.\n");
of_node_put(child);
return ret;
}
}
}
return 0;
}
static int st_pctl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct st_pinctrl *info;
struct pinctrl_desc *pctl_desc;
int ret, i;
if (!dev->of_node) {
dev_err(dev, "device node not found.\n");
return -EINVAL;
}
pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
if (!pctl_desc)
return -ENOMEM;
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->dev = dev;
platform_set_drvdata(pdev, info);
ret = st_pctl_probe_dt(pdev, pctl_desc, info);
if (ret)
return ret;
pctl_desc->owner = THIS_MODULE;
pctl_desc->pctlops = &st_pctlops;
pctl_desc->pmxops = &st_pmxops;
pctl_desc->confops = &st_confops;
pctl_desc->name = dev_name(dev);
info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
if (IS_ERR(info->pctl))
return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
for (i = 0; i < info->nbanks; i++)
pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
return 0;
}
static struct platform_driver st_pctl_driver = {
.driver = {
.name = "st-pinctrl",
.of_match_table = st_pctl_of_match,
},
.probe = st_pctl_probe,
};
static int __init st_pctl_init(void)
{
return platform_driver_register(&st_pctl_driver);
}
arch_initcall(st_pctl_init);
|
linux-master
|
drivers/pinctrl/pinctrl-st.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Merrifield SoC pinctrl driver
*
* Copyright (C) 2016, Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#include "pinctrl-tangier.h"
static const struct pinctrl_pin_desc mrfld_pins[] = {
/* Family 0: OCP2SSC (0 pins) */
/* Family 1: ULPI (13 pins) */
PINCTRL_PIN(0, "ULPI_CLK"),
PINCTRL_PIN(1, "ULPI_D0"),
PINCTRL_PIN(2, "ULPI_D1"),
PINCTRL_PIN(3, "ULPI_D2"),
PINCTRL_PIN(4, "ULPI_D3"),
PINCTRL_PIN(5, "ULPI_D4"),
PINCTRL_PIN(6, "ULPI_D5"),
PINCTRL_PIN(7, "ULPI_D6"),
PINCTRL_PIN(8, "ULPI_D7"),
PINCTRL_PIN(9, "ULPI_DIR"),
PINCTRL_PIN(10, "ULPI_NXT"),
PINCTRL_PIN(11, "ULPI_REFCLK"),
PINCTRL_PIN(12, "ULPI_STP"),
/* Family 2: eMMC (24 pins) */
PINCTRL_PIN(13, "EMMC_CLK"),
PINCTRL_PIN(14, "EMMC_CMD"),
PINCTRL_PIN(15, "EMMC_D0"),
PINCTRL_PIN(16, "EMMC_D1"),
PINCTRL_PIN(17, "EMMC_D2"),
PINCTRL_PIN(18, "EMMC_D3"),
PINCTRL_PIN(19, "EMMC_D4"),
PINCTRL_PIN(20, "EMMC_D5"),
PINCTRL_PIN(21, "EMMC_D6"),
PINCTRL_PIN(22, "EMMC_D7"),
PINCTRL_PIN(23, "EMMC_RST_N"),
PINCTRL_PIN(24, "GP154"),
PINCTRL_PIN(25, "GP155"),
PINCTRL_PIN(26, "GP156"),
PINCTRL_PIN(27, "GP157"),
PINCTRL_PIN(28, "GP158"),
PINCTRL_PIN(29, "GP159"),
PINCTRL_PIN(30, "GP160"),
PINCTRL_PIN(31, "GP161"),
PINCTRL_PIN(32, "GP162"),
PINCTRL_PIN(33, "GP163"),
PINCTRL_PIN(34, "GP97"),
PINCTRL_PIN(35, "GP14"),
PINCTRL_PIN(36, "GP15"),
/* Family 3: SDIO (20 pins) */
PINCTRL_PIN(37, "GP77_SD_CD"),
PINCTRL_PIN(38, "GP78_SD_CLK"),
PINCTRL_PIN(39, "GP79_SD_CMD"),
PINCTRL_PIN(40, "GP80_SD_D0"),
PINCTRL_PIN(41, "GP81_SD_D1"),
PINCTRL_PIN(42, "GP82_SD_D2"),
PINCTRL_PIN(43, "GP83_SD_D3"),
PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
PINCTRL_PIN(48, "GP87_SD_PD"),
PINCTRL_PIN(49, "GP89_SD_WP"),
PINCTRL_PIN(50, "GP90_SDIO_CLK"),
PINCTRL_PIN(51, "GP91_SDIO_CMD"),
PINCTRL_PIN(52, "GP92_SDIO_D0"),
PINCTRL_PIN(53, "GP93_SDIO_D1"),
PINCTRL_PIN(54, "GP94_SDIO_D2"),
PINCTRL_PIN(55, "GP95_SDIO_D3"),
PINCTRL_PIN(56, "GP96_SDIO_PD"),
/* Family 4: HSI (8 pins) */
PINCTRL_PIN(57, "HSI_ACDATA"),
PINCTRL_PIN(58, "HSI_ACFLAG"),
PINCTRL_PIN(59, "HSI_ACREADY"),
PINCTRL_PIN(60, "HSI_ACWAKE"),
PINCTRL_PIN(61, "HSI_CADATA"),
PINCTRL_PIN(62, "HSI_CAFLAG"),
PINCTRL_PIN(63, "HSI_CAREADY"),
PINCTRL_PIN(64, "HSI_CAWAKE"),
/* Family 5: SSP Audio (14 pins) */
PINCTRL_PIN(65, "GP70"),
PINCTRL_PIN(66, "GP71"),
PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
PINCTRL_PIN(68, "GP33_I2S_0_FS"),
PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
PINCTRL_PIN(72, "GP37_I2S_1_FS"),
PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
PINCTRL_PIN(76, "GP41_I2S_2_FS"),
PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
/* Family 6: GP SSP (22 pins) */
PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
PINCTRL_PIN(80, "GP121_SPI_0_SS"),
PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
PINCTRL_PIN(98, "GP117_SPI_3_SS"),
PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
/* Family 7: I2C (14 pins) */
PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
/* Family 8: UART (12 pins) */
PINCTRL_PIN(115, "GP124_UART_0_CTS"),
PINCTRL_PIN(116, "GP125_UART_0_RTS"),
PINCTRL_PIN(117, "GP126_UART_0_RX"),
PINCTRL_PIN(118, "GP127_UART_0_TX"),
PINCTRL_PIN(119, "GP128_UART_1_CTS"),
PINCTRL_PIN(120, "GP129_UART_1_RTS"),
PINCTRL_PIN(121, "GP130_UART_1_RX"),
PINCTRL_PIN(122, "GP131_UART_1_TX"),
PINCTRL_PIN(123, "GP132_UART_2_CTS"),
PINCTRL_PIN(124, "GP133_UART_2_RTS"),
PINCTRL_PIN(125, "GP134_UART_2_RX"),
PINCTRL_PIN(126, "GP135_UART_2_TX"),
/* Family 9: GPIO South (19 pins) */
PINCTRL_PIN(127, "GP177"),
PINCTRL_PIN(128, "GP178"),
PINCTRL_PIN(129, "GP179"),
PINCTRL_PIN(130, "GP180"),
PINCTRL_PIN(131, "GP181"),
PINCTRL_PIN(132, "GP182_PWM2"),
PINCTRL_PIN(133, "GP183_PWM3"),
PINCTRL_PIN(134, "GP184"),
PINCTRL_PIN(135, "GP185"),
PINCTRL_PIN(136, "GP186"),
PINCTRL_PIN(137, "GP187"),
PINCTRL_PIN(138, "GP188"),
PINCTRL_PIN(139, "GP189"),
PINCTRL_PIN(140, "GP64_FAST_INT0"),
PINCTRL_PIN(141, "GP65_FAST_INT1"),
PINCTRL_PIN(142, "GP66_FAST_INT2"),
PINCTRL_PIN(143, "GP67_FAST_INT3"),
PINCTRL_PIN(144, "GP12_PWM0"),
PINCTRL_PIN(145, "GP13_PWM1"),
/* Family 10: Camera Sideband (12 pins) */
PINCTRL_PIN(146, "GP0"),
PINCTRL_PIN(147, "GP1"),
PINCTRL_PIN(148, "GP2"),
PINCTRL_PIN(149, "GP3"),
PINCTRL_PIN(150, "GP4"),
PINCTRL_PIN(151, "GP5"),
PINCTRL_PIN(152, "GP6"),
PINCTRL_PIN(153, "GP7"),
PINCTRL_PIN(154, "GP8"),
PINCTRL_PIN(155, "GP9"),
PINCTRL_PIN(156, "GP10"),
PINCTRL_PIN(157, "GP11"),
/* Family 11: Clock (22 pins) */
PINCTRL_PIN(158, "GP137"),
PINCTRL_PIN(159, "GP138"),
PINCTRL_PIN(160, "GP139"),
PINCTRL_PIN(161, "GP140"),
PINCTRL_PIN(162, "GP141"),
PINCTRL_PIN(163, "GP142"),
PINCTRL_PIN(164, "GP16_HDMI_HPD"),
PINCTRL_PIN(165, "GP68_DSI_A_TE"),
PINCTRL_PIN(166, "GP69_DSI_C_TE"),
PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
PINCTRL_PIN(169, "OSC_CLK0"),
PINCTRL_PIN(170, "OSC_CLK1"),
PINCTRL_PIN(171, "OSC_CLK2"),
PINCTRL_PIN(172, "OSC_CLK3"),
PINCTRL_PIN(173, "OSC_CLK4"),
PINCTRL_PIN(174, "RESETOUT"),
PINCTRL_PIN(175, "PMODE"),
PINCTRL_PIN(176, "PRDY"),
PINCTRL_PIN(177, "PREQ"),
PINCTRL_PIN(178, "GP190"),
PINCTRL_PIN(179, "GP191"),
/* Family 12: MSIC (15 pins) */
PINCTRL_PIN(180, "I2C_0_SCL"),
PINCTRL_PIN(181, "I2C_0_SDA"),
PINCTRL_PIN(182, "IERR"),
PINCTRL_PIN(183, "JTAG_TCK"),
PINCTRL_PIN(184, "JTAG_TDI"),
PINCTRL_PIN(185, "JTAG_TDO"),
PINCTRL_PIN(186, "JTAG_TMS"),
PINCTRL_PIN(187, "JTAG_TRST"),
PINCTRL_PIN(188, "PROCHOT"),
PINCTRL_PIN(189, "RTC_CLK"),
PINCTRL_PIN(190, "SVID_ALERT"),
PINCTRL_PIN(191, "SVID_CLK"),
PINCTRL_PIN(192, "SVID_D"),
PINCTRL_PIN(193, "THERMTRIP"),
PINCTRL_PIN(194, "STANDBY"),
/* Family 13: Keyboard (20 pins) */
PINCTRL_PIN(195, "GP44"),
PINCTRL_PIN(196, "GP45"),
PINCTRL_PIN(197, "GP46"),
PINCTRL_PIN(198, "GP47"),
PINCTRL_PIN(199, "GP48"),
PINCTRL_PIN(200, "GP49"),
PINCTRL_PIN(201, "GP50"),
PINCTRL_PIN(202, "GP51"),
PINCTRL_PIN(203, "GP52"),
PINCTRL_PIN(204, "GP53"),
PINCTRL_PIN(205, "GP54"),
PINCTRL_PIN(206, "GP55"),
PINCTRL_PIN(207, "GP56"),
PINCTRL_PIN(208, "GP57"),
PINCTRL_PIN(209, "GP58"),
PINCTRL_PIN(210, "GP59"),
PINCTRL_PIN(211, "GP60"),
PINCTRL_PIN(212, "GP61"),
PINCTRL_PIN(213, "GP62"),
PINCTRL_PIN(214, "GP63"),
/* Family 14: GPIO North (13 pins) */
PINCTRL_PIN(215, "GP164"),
PINCTRL_PIN(216, "GP165"),
PINCTRL_PIN(217, "GP166"),
PINCTRL_PIN(218, "GP167"),
PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
PINCTRL_PIN(224, "GP173"),
PINCTRL_PIN(225, "GP174"),
PINCTRL_PIN(226, "GP175"),
PINCTRL_PIN(227, "GP176"),
/* Family 15: PTI (5 pins) */
PINCTRL_PIN(228, "GP72_PTI_CLK"),
PINCTRL_PIN(229, "GP73_PTI_D0"),
PINCTRL_PIN(230, "GP74_PTI_D1"),
PINCTRL_PIN(231, "GP75_PTI_D2"),
PINCTRL_PIN(232, "GP76_PTI_D3"),
/* Family 16: USB3 (0 pins) */
/* Family 17: HSIC (0 pins) */
/* Family 18: Broadcast (0 pins) */
};
static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
static const unsigned int mrfld_pwm0_pins[] = { 144 };
static const unsigned int mrfld_pwm1_pins[] = { 145 };
static const unsigned int mrfld_pwm2_pins[] = { 132 };
static const unsigned int mrfld_pwm3_pins[] = { 133 };
static const struct intel_pingroup mrfld_groups[] = {
PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
};
static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
static const struct intel_function mrfld_functions[] = {
FUNCTION("sdio", mrfld_sdio_groups),
FUNCTION("i2s2", mrfld_i2s2_groups),
FUNCTION("spi5", mrfld_spi5_groups),
FUNCTION("uart0", mrfld_uart0_groups),
FUNCTION("uart1", mrfld_uart1_groups),
FUNCTION("uart2", mrfld_uart2_groups),
FUNCTION("pwm0", mrfld_pwm0_groups),
FUNCTION("pwm1", mrfld_pwm1_groups),
FUNCTION("pwm2", mrfld_pwm2_groups),
FUNCTION("pwm3", mrfld_pwm3_groups),
};
static const struct tng_family mrfld_families[] = {
TNG_FAMILY(1, 0, 12),
TNG_FAMILY(2, 13, 36),
TNG_FAMILY(3, 37, 56),
TNG_FAMILY(4, 57, 64),
TNG_FAMILY(5, 65, 78),
TNG_FAMILY(6, 79, 100),
TNG_FAMILY_PROTECTED(7, 101, 114),
TNG_FAMILY(8, 115, 126),
TNG_FAMILY(9, 127, 145),
TNG_FAMILY(10, 146, 157),
TNG_FAMILY(11, 158, 179),
TNG_FAMILY_PROTECTED(12, 180, 194),
TNG_FAMILY(13, 195, 214),
TNG_FAMILY(14, 215, 227),
TNG_FAMILY(15, 228, 232),
};
static const struct tng_pinctrl mrfld_soc_data = {
.pins = mrfld_pins,
.npins = ARRAY_SIZE(mrfld_pins),
.groups = mrfld_groups,
.ngroups = ARRAY_SIZE(mrfld_groups),
.families = mrfld_families,
.nfamilies = ARRAY_SIZE(mrfld_families),
.functions = mrfld_functions,
.nfunctions = ARRAY_SIZE(mrfld_functions),
};
static const struct acpi_device_id mrfld_acpi_table[] = {
{ "INTC1002", (kernel_ulong_t)&mrfld_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
static struct platform_driver mrfld_pinctrl_driver = {
.probe = devm_tng_pinctrl_probe,
.driver = {
.name = "pinctrl-merrifield",
.acpi_match_table = mrfld_acpi_table,
},
};
static int __init mrfld_pinctrl_init(void)
{
return platform_driver_register(&mrfld_pinctrl_driver);
}
subsys_initcall(mrfld_pinctrl_init);
static void __exit mrfld_pinctrl_exit(void)
{
platform_driver_unregister(&mrfld_pinctrl_driver);
}
module_exit(mrfld_pinctrl_exit);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pinctrl-merrifield");
MODULE_IMPORT_NS(PINCTRL_TANGIER);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-merrifield.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Gemini Lake SoC pinctrl/GPIO driver
*
* Copyright (C) 2017 Intel Corporation
* Author: Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define GLK_PAD_OWN 0x020
#define GLK_PADCFGLOCK 0x080
#define GLK_HOSTSW_OWN 0x0b0
#define GLK_GPI_IS 0x100
#define GLK_GPI_IE 0x110
#define GLK_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK)
/* GLK */
static const struct pinctrl_pin_desc glk_northwest_pins[] = {
PINCTRL_PIN(0, "TCK"),
PINCTRL_PIN(1, "TRST_B"),
PINCTRL_PIN(2, "TMS"),
PINCTRL_PIN(3, "TDI"),
PINCTRL_PIN(4, "TDO"),
PINCTRL_PIN(5, "JTAGX"),
PINCTRL_PIN(6, "CX_PREQ_B"),
PINCTRL_PIN(7, "CX_PRDY_B"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "ISH_GPIO_0"),
PINCTRL_PIN(27, "ISH_GPIO_1"),
PINCTRL_PIN(28, "ISH_GPIO_2"),
PINCTRL_PIN(29, "ISH_GPIO_3"),
PINCTRL_PIN(30, "ISH_GPIO_4"),
PINCTRL_PIN(31, "ISH_GPIO_5"),
PINCTRL_PIN(32, "ISH_GPIO_6"),
PINCTRL_PIN(33, "ISH_GPIO_7"),
PINCTRL_PIN(34, "ISH_GPIO_8"),
PINCTRL_PIN(35, "ISH_GPIO_9"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GP_INTD_DSI_TE1"),
PINCTRL_PIN(43, "GP_INTD_DSI_TE2"),
PINCTRL_PIN(44, "USB_OC0_B"),
PINCTRL_PIN(45, "USB_OC1_B"),
PINCTRL_PIN(46, "DSI_I2C_SDA"),
PINCTRL_PIN(47, "DSI_I2C_SCL"),
PINCTRL_PIN(48, "PMC_I2C_SDA"),
PINCTRL_PIN(49, "PMC_I2C_SCL"),
PINCTRL_PIN(50, "LPSS_I2C0_SDA"),
PINCTRL_PIN(51, "LPSS_I2C0_SCL"),
PINCTRL_PIN(52, "LPSS_I2C1_SDA"),
PINCTRL_PIN(53, "LPSS_I2C1_SCL"),
PINCTRL_PIN(54, "LPSS_I2C2_SDA"),
PINCTRL_PIN(55, "LPSS_I2C2_SCL"),
PINCTRL_PIN(56, "LPSS_I2C3_SDA"),
PINCTRL_PIN(57, "LPSS_I2C3_SCL"),
PINCTRL_PIN(58, "LPSS_I2C4_SDA"),
PINCTRL_PIN(59, "LPSS_I2C4_SCL"),
PINCTRL_PIN(60, "LPSS_UART0_RXD"),
PINCTRL_PIN(61, "LPSS_UART0_TXD"),
PINCTRL_PIN(62, "LPSS_UART0_RTS_B"),
PINCTRL_PIN(63, "LPSS_UART0_CTS_B"),
PINCTRL_PIN(64, "LPSS_UART2_RXD"),
PINCTRL_PIN(65, "LPSS_UART2_TXD"),
PINCTRL_PIN(66, "LPSS_UART2_RTS_B"),
PINCTRL_PIN(67, "LPSS_UART2_CTS_B"),
PINCTRL_PIN(68, "PMC_SPI_FS0"),
PINCTRL_PIN(69, "PMC_SPI_FS1"),
PINCTRL_PIN(70, "PMC_SPI_FS2"),
PINCTRL_PIN(71, "PMC_SPI_RXD"),
PINCTRL_PIN(72, "PMC_SPI_TXD"),
PINCTRL_PIN(73, "PMC_SPI_CLK"),
PINCTRL_PIN(74, "THERMTRIP_B"),
PINCTRL_PIN(75, "PROCHOT_B"),
PINCTRL_PIN(76, "EMMC_RST_B"),
PINCTRL_PIN(77, "GPIO_212"),
PINCTRL_PIN(78, "GPIO_213"),
PINCTRL_PIN(79, "GPIO_214"),
};
static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };
static const unsigned int glk_northwest_pwm0_pins[] = { 42 };
static const unsigned int glk_northwest_pwm1_pins[] = { 43 };
static const unsigned int glk_northwest_pwm2_pins[] = { 44 };
static const unsigned int glk_northwest_pwm3_pins[] = { 45 };
static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };
static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };
static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };
static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };
static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };
static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };
static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };
static const struct intel_pingroup glk_northwest_groups[] = {
PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2),
PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2),
PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2),
PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2),
PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2),
PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1),
PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1),
PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1),
PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1),
PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1),
};
static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };
static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };
static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };
static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };
static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };
static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };
static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };
static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };
static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };
static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };
static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };
static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };
static const struct intel_function glk_northwest_functions[] = {
FUNCTION("uart1", glk_northwest_uart1_groups),
FUNCTION("pmw0", glk_northwest_pwm0_groups),
FUNCTION("pmw1", glk_northwest_pwm1_groups),
FUNCTION("pmw2", glk_northwest_pwm2_groups),
FUNCTION("pmw3", glk_northwest_pwm3_groups),
FUNCTION("i2c0", glk_northwest_i2c0_groups),
FUNCTION("i2c1", glk_northwest_i2c1_groups),
FUNCTION("i2c2", glk_northwest_i2c2_groups),
FUNCTION("i2c3", glk_northwest_i2c3_groups),
FUNCTION("i2c4", glk_northwest_i2c4_groups),
FUNCTION("uart0", glk_northwest_uart0_groups),
FUNCTION("uart2", glk_northwest_uart2_groups),
};
static const struct intel_community glk_northwest_communities[] = {
GLK_COMMUNITY(0, 0, 79),
};
static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
.uid = "1",
.pins = glk_northwest_pins,
.npins = ARRAY_SIZE(glk_northwest_pins),
.groups = glk_northwest_groups,
.ngroups = ARRAY_SIZE(glk_northwest_groups),
.functions = glk_northwest_functions,
.nfunctions = ARRAY_SIZE(glk_northwest_functions),
.communities = glk_northwest_communities,
.ncommunities = ARRAY_SIZE(glk_northwest_communities),
};
static const struct pinctrl_pin_desc glk_north_pins[] = {
PINCTRL_PIN(0, "SVID0_ALERT_B"),
PINCTRL_PIN(1, "SVID0_DATA"),
PINCTRL_PIN(2, "SVID0_CLK"),
PINCTRL_PIN(3, "LPSS_SPI_0_CLK"),
PINCTRL_PIN(4, "LPSS_SPI_0_FS0"),
PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
PINCTRL_PIN(14, "FST_SPI_CS0_B"),
PINCTRL_PIN(15, "FST_SPI_CS1_B"),
PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
PINCTRL_PIN(17, "FST_SPI_MISO_IO1"),
PINCTRL_PIN(18, "FST_SPI_IO2"),
PINCTRL_PIN(19, "FST_SPI_IO3"),
PINCTRL_PIN(20, "FST_SPI_CLK"),
PINCTRL_PIN(21, "FST_SPI_CLK_FB"),
PINCTRL_PIN(22, "PMU_PLTRST_B"),
PINCTRL_PIN(23, "PMU_PWRBTN_B"),
PINCTRL_PIN(24, "PMU_SLP_S0_B"),
PINCTRL_PIN(25, "PMU_SLP_S3_B"),
PINCTRL_PIN(26, "PMU_SLP_S4_B"),
PINCTRL_PIN(27, "SUSPWRDNACK"),
PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
PINCTRL_PIN(29, "GPIO_105"),
PINCTRL_PIN(30, "PMU_BATLOW_B"),
PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
PINCTRL_PIN(32, "PMU_SUSCLK"),
PINCTRL_PIN(33, "SUS_STAT_B"),
PINCTRL_PIN(34, "LPSS_I2C5_SDA"),
PINCTRL_PIN(35, "LPSS_I2C5_SCL"),
PINCTRL_PIN(36, "LPSS_I2C6_SDA"),
PINCTRL_PIN(37, "LPSS_I2C6_SCL"),
PINCTRL_PIN(38, "LPSS_I2C7_SDA"),
PINCTRL_PIN(39, "LPSS_I2C7_SCL"),
PINCTRL_PIN(40, "PCIE_WAKE0_B"),
PINCTRL_PIN(41, "PCIE_WAKE1_B"),
PINCTRL_PIN(42, "PCIE_WAKE2_B"),
PINCTRL_PIN(43, "PCIE_WAKE3_B"),
PINCTRL_PIN(44, "PCIE_CLKREQ0_B"),
PINCTRL_PIN(45, "PCIE_CLKREQ1_B"),
PINCTRL_PIN(46, "PCIE_CLKREQ2_B"),
PINCTRL_PIN(47, "PCIE_CLKREQ3_B"),
PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"),
PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"),
PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"),
PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"),
PINCTRL_PIN(52, "PANEL0_VDDEN"),
PINCTRL_PIN(53, "PANEL0_BKLTEN"),
PINCTRL_PIN(54, "PANEL0_BKLTCTL"),
PINCTRL_PIN(55, "HV_DDI0_HPD"),
PINCTRL_PIN(56, "HV_DDI1_HPD"),
PINCTRL_PIN(57, "HV_EDP_HPD"),
PINCTRL_PIN(58, "GPIO_134"),
PINCTRL_PIN(59, "GPIO_135"),
PINCTRL_PIN(60, "GPIO_136"),
PINCTRL_PIN(61, "GPIO_137"),
PINCTRL_PIN(62, "GPIO_138"),
PINCTRL_PIN(63, "GPIO_139"),
PINCTRL_PIN(64, "GPIO_140"),
PINCTRL_PIN(65, "GPIO_141"),
PINCTRL_PIN(66, "GPIO_142"),
PINCTRL_PIN(67, "GPIO_143"),
PINCTRL_PIN(68, "GPIO_144"),
PINCTRL_PIN(69, "GPIO_145"),
PINCTRL_PIN(70, "GPIO_146"),
PINCTRL_PIN(71, "LPC_ILB_SERIRQ"),
PINCTRL_PIN(72, "LPC_CLKOUT0"),
PINCTRL_PIN(73, "LPC_CLKOUT1"),
PINCTRL_PIN(74, "LPC_AD0"),
PINCTRL_PIN(75, "LPC_AD1"),
PINCTRL_PIN(76, "LPC_AD2"),
PINCTRL_PIN(77, "LPC_AD3"),
PINCTRL_PIN(78, "LPC_CLKRUNB"),
PINCTRL_PIN(79, "LPC_FRAMEB"),
};
static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };
static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };
static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };
static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };
static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };
static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };
static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };
static const struct intel_pingroup glk_north_groups[] = {
PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1),
PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1),
PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1),
PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1),
PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1),
PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2),
PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2),
};
static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" };
static const char * const glk_north_spi1_groups[] = { "spi1_grp" };
static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };
static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };
static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };
static const char * const glk_north_uart0_groups[] = { "uart0_grp" };
static const struct intel_function glk_north_functions[] = {
FUNCTION("spi0", glk_north_spi0_groups),
FUNCTION("spi1", glk_north_spi1_groups),
FUNCTION("i2c5", glk_north_i2c5_groups),
FUNCTION("i2c6", glk_north_i2c6_groups),
FUNCTION("i2c7", glk_north_i2c7_groups),
FUNCTION("uart0", glk_north_uart0_groups),
};
static const struct intel_community glk_north_communities[] = {
GLK_COMMUNITY(0, 0, 79),
};
static const struct intel_pinctrl_soc_data glk_north_soc_data = {
.uid = "2",
.pins = glk_north_pins,
.npins = ARRAY_SIZE(glk_north_pins),
.groups = glk_north_groups,
.ngroups = ARRAY_SIZE(glk_north_groups),
.functions = glk_north_functions,
.nfunctions = ARRAY_SIZE(glk_north_functions),
.communities = glk_north_communities,
.ncommunities = ARRAY_SIZE(glk_north_communities),
};
static const struct pinctrl_pin_desc glk_audio_pins[] = {
PINCTRL_PIN(0, "AVS_I2S0_MCLK"),
PINCTRL_PIN(1, "AVS_I2S0_BCLK"),
PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"),
PINCTRL_PIN(3, "AVS_I2S0_SDI"),
PINCTRL_PIN(4, "AVS_I2S0_SDO"),
PINCTRL_PIN(5, "AVS_I2S1_MCLK"),
PINCTRL_PIN(6, "AVS_I2S1_BCLK"),
PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"),
PINCTRL_PIN(8, "AVS_I2S1_SDI"),
PINCTRL_PIN(9, "AVS_I2S1_SDO"),
PINCTRL_PIN(10, "AVS_HDA_BCLK"),
PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"),
PINCTRL_PIN(12, "AVS_HDA_SDI"),
PINCTRL_PIN(13, "AVS_HDA_SDO"),
PINCTRL_PIN(14, "AVS_HDA_RSTB"),
PINCTRL_PIN(15, "AVS_M_CLK_A1"),
PINCTRL_PIN(16, "AVS_M_CLK_B1"),
PINCTRL_PIN(17, "AVS_M_DATA_1"),
PINCTRL_PIN(18, "AVS_M_CLK_AB2"),
PINCTRL_PIN(19, "AVS_M_DATA_2"),
};
static const struct intel_community glk_audio_communities[] = {
GLK_COMMUNITY(0, 0, 19),
};
static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
.uid = "3",
.pins = glk_audio_pins,
.npins = ARRAY_SIZE(glk_audio_pins),
.communities = glk_audio_communities,
.ncommunities = ARRAY_SIZE(glk_audio_communities),
};
static const struct pinctrl_pin_desc glk_scc_pins[] = {
PINCTRL_PIN(0, "SMB_ALERTB"),
PINCTRL_PIN(1, "SMB_CLK"),
PINCTRL_PIN(2, "SMB_DATA"),
PINCTRL_PIN(3, "SDCARD_LVL_WP"),
PINCTRL_PIN(4, "SDCARD_CLK"),
PINCTRL_PIN(5, "SDCARD_CLK_FB"),
PINCTRL_PIN(6, "SDCARD_D0"),
PINCTRL_PIN(7, "SDCARD_D1"),
PINCTRL_PIN(8, "SDCARD_D2"),
PINCTRL_PIN(9, "SDCARD_D3"),
PINCTRL_PIN(10, "SDCARD_CMD"),
PINCTRL_PIN(11, "SDCARD_CD_B"),
PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"),
PINCTRL_PIN(13, "GPIO_210"),
PINCTRL_PIN(14, "OSC_CLK_OUT_0"),
PINCTRL_PIN(15, "OSC_CLK_OUT_1"),
PINCTRL_PIN(16, "CNV_BRI_DT"),
PINCTRL_PIN(17, "CNV_BRI_RSP"),
PINCTRL_PIN(18, "CNV_RGI_DT"),
PINCTRL_PIN(19, "CNV_RGI_RSP"),
PINCTRL_PIN(20, "CNV_RF_RESET_B"),
PINCTRL_PIN(21, "XTAL_CLKREQ"),
PINCTRL_PIN(22, "SDIO_CLK_FB"),
PINCTRL_PIN(23, "EMMC0_CLK"),
PINCTRL_PIN(24, "EMMC0_CLK_FB"),
PINCTRL_PIN(25, "EMMC0_D0"),
PINCTRL_PIN(26, "EMMC0_D1"),
PINCTRL_PIN(27, "EMMC0_D2"),
PINCTRL_PIN(28, "EMMC0_D3"),
PINCTRL_PIN(29, "EMMC0_D4"),
PINCTRL_PIN(30, "EMMC0_D5"),
PINCTRL_PIN(31, "EMMC0_D6"),
PINCTRL_PIN(32, "EMMC0_D7"),
PINCTRL_PIN(33, "EMMC0_CMD"),
PINCTRL_PIN(34, "EMMC0_STROBE"),
};
static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };
static const unsigned int glk_scc_sdcard_pins[] = {
3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
};
static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };
static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };
static const unsigned int glk_scc_emmc_pins[] = {
23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
};
static const struct intel_pingroup glk_scc_groups[] = {
PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2),
PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1),
PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2),
PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3),
PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1),
};
static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };
static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };
static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };
static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };
static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };
static const struct intel_function glk_scc_functions[] = {
FUNCTION("i2c7", glk_scc_i2c7_groups),
FUNCTION("sdcard", glk_scc_sdcard_groups),
FUNCTION("sdio", glk_scc_sdio_groups),
FUNCTION("uart1", glk_scc_uart1_groups),
FUNCTION("emmc", glk_scc_emmc_groups),
};
static const struct intel_community glk_scc_communities[] = {
GLK_COMMUNITY(0, 0, 34),
};
static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
.uid = "4",
.pins = glk_scc_pins,
.npins = ARRAY_SIZE(glk_scc_pins),
.groups = glk_scc_groups,
.ngroups = ARRAY_SIZE(glk_scc_groups),
.functions = glk_scc_functions,
.nfunctions = ARRAY_SIZE(glk_scc_functions),
.communities = glk_scc_communities,
.ncommunities = ARRAY_SIZE(glk_scc_communities),
};
static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
&glk_northwest_soc_data,
&glk_north_soc_data,
&glk_audio_soc_data,
&glk_scc_soc_data,
NULL
};
static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
{ "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
static struct platform_driver glk_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "geminilake-pinctrl",
.acpi_match_table = glk_pinctrl_acpi_match,
.pm = &glk_pinctrl_pm_ops,
},
};
static int __init glk_pinctrl_init(void)
{
return platform_driver_register(&glk_pinctrl_driver);
}
subsys_initcall(glk_pinctrl_init);
static void __exit glk_pinctrl_exit(void)
{
platform_driver_unregister(&glk_pinctrl_driver);
}
module_exit(glk_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-geminilake.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Cherryview/Braswell pinctrl driver
*
* Copyright (C) 2014, 2020 Intel Corporation
* Author: Mika Westerberg <[email protected]>
*
* This driver is based on the original Cherryview GPIO driver by
* Ning Li <[email protected]>
* Alan Cox <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-intel.h"
#define CHV_INTSTAT 0x300
#define CHV_INTMASK 0x380
#define FAMILY_PAD_REGS_OFF 0x4400
#define FAMILY_PAD_REGS_SIZE 0x400
#define MAX_FAMILY_PAD_GPIO_NO 15
#define GPIO_REGS_SIZE 8
#define CHV_PADCTRL0 0x000
#define CHV_PADCTRL0_INTSEL_SHIFT 28
#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28)
#define CHV_PADCTRL0_TERM_UP BIT(23)
#define CHV_PADCTRL0_TERM_SHIFT 20
#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20)
#define CHV_PADCTRL0_TERM_20K 1
#define CHV_PADCTRL0_TERM_5K 2
#define CHV_PADCTRL0_TERM_1K 4
#define CHV_PADCTRL0_PMODE_SHIFT 16
#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16)
#define CHV_PADCTRL0_GPIOEN BIT(15)
#define CHV_PADCTRL0_GPIOCFG_SHIFT 8
#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8)
#define CHV_PADCTRL0_GPIOCFG_GPIO 0
#define CHV_PADCTRL0_GPIOCFG_GPO 1
#define CHV_PADCTRL0_GPIOCFG_GPI 2
#define CHV_PADCTRL0_GPIOCFG_HIZ 3
#define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
#define CHV_PADCTRL0_GPIORXSTATE BIT(0)
#define CHV_PADCTRL1 0x004
#define CHV_PADCTRL1_CFGLOCK BIT(31)
#define CHV_PADCTRL1_INVRXTX_SHIFT 4
#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
#define CHV_PADCTRL1_ODEN BIT(3)
#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0)
#define CHV_PADCTRL1_INTWAKECFG_FALLING 1
#define CHV_PADCTRL1_INTWAKECFG_RISING 2
#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
struct intel_pad_context {
u32 padctrl0;
u32 padctrl1;
};
#define CHV_INVALID_HWIRQ (~0U)
/**
* struct intel_community_context - community context for Cherryview
* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
* @saved_intmask: Interrupt mask saved for system sleep
*/
struct intel_community_context {
unsigned int intr_lines[16];
u32 saved_intmask;
};
#define PINMODE_INVERT_OE BIT(15)
#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
#define CHV_GPP(start, end) \
{ \
.base = (start), \
.size = (end) - (start) + 1, \
}
#define CHV_COMMUNITY(g, i, a) \
{ \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
.nirqs = (i), \
.acpi_space_id = (a), \
}
static const struct pinctrl_pin_desc southwest_pins[] = {
PINCTRL_PIN(0, "FST_SPI_D2"),
PINCTRL_PIN(1, "FST_SPI_D0"),
PINCTRL_PIN(2, "FST_SPI_CLK"),
PINCTRL_PIN(3, "FST_SPI_D3"),
PINCTRL_PIN(4, "FST_SPI_CS1_B"),
PINCTRL_PIN(5, "FST_SPI_D1"),
PINCTRL_PIN(6, "FST_SPI_CS0_B"),
PINCTRL_PIN(7, "FST_SPI_CS2_B"),
PINCTRL_PIN(15, "UART1_RTS_B"),
PINCTRL_PIN(16, "UART1_RXD"),
PINCTRL_PIN(17, "UART2_RXD"),
PINCTRL_PIN(18, "UART1_CTS_B"),
PINCTRL_PIN(19, "UART2_RTS_B"),
PINCTRL_PIN(20, "UART1_TXD"),
PINCTRL_PIN(21, "UART2_TXD"),
PINCTRL_PIN(22, "UART2_CTS_B"),
PINCTRL_PIN(30, "MF_HDA_CLK"),
PINCTRL_PIN(31, "MF_HDA_RSTB"),
PINCTRL_PIN(32, "MF_HDA_SDIO"),
PINCTRL_PIN(33, "MF_HDA_SDO"),
PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
PINCTRL_PIN(35, "MF_HDA_SYNC"),
PINCTRL_PIN(36, "MF_HDA_SDI1"),
PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
PINCTRL_PIN(45, "I2C5_SDA"),
PINCTRL_PIN(46, "I2C4_SDA"),
PINCTRL_PIN(47, "I2C6_SDA"),
PINCTRL_PIN(48, "I2C5_SCL"),
PINCTRL_PIN(49, "I2C_NFC_SDA"),
PINCTRL_PIN(50, "I2C4_SCL"),
PINCTRL_PIN(51, "I2C6_SCL"),
PINCTRL_PIN(52, "I2C_NFC_SCL"),
PINCTRL_PIN(60, "I2C1_SDA"),
PINCTRL_PIN(61, "I2C0_SDA"),
PINCTRL_PIN(62, "I2C2_SDA"),
PINCTRL_PIN(63, "I2C1_SCL"),
PINCTRL_PIN(64, "I2C3_SDA"),
PINCTRL_PIN(65, "I2C0_SCL"),
PINCTRL_PIN(66, "I2C2_SCL"),
PINCTRL_PIN(67, "I2C3_SCL"),
PINCTRL_PIN(75, "SATA_GP0"),
PINCTRL_PIN(76, "SATA_GP1"),
PINCTRL_PIN(77, "SATA_LEDN"),
PINCTRL_PIN(78, "SATA_GP2"),
PINCTRL_PIN(79, "MF_SMB_ALERTB"),
PINCTRL_PIN(80, "SATA_GP3"),
PINCTRL_PIN(81, "MF_SMB_CLK"),
PINCTRL_PIN(82, "MF_SMB_DATA"),
PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
PINCTRL_PIN(92, "GP_SSP_2_CLK"),
PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
PINCTRL_PIN(94, "GP_SSP_2_RXD"),
PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
PINCTRL_PIN(96, "GP_SSP_2_FS"),
PINCTRL_PIN(97, "GP_SSP_2_TXD"),
};
static const unsigned southwest_uart0_pins[] = { 16, 20 };
static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
static const unsigned southwest_i2c0_pins[] = { 61, 65 };
static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
static const unsigned southwest_lpe_pins[] = {
30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
};
static const unsigned southwest_i2c1_pins[] = { 60, 63 };
static const unsigned southwest_i2c2_pins[] = { 62, 66 };
static const unsigned southwest_i2c3_pins[] = { 64, 67 };
static const unsigned southwest_i2c4_pins[] = { 46, 50 };
static const unsigned southwest_i2c5_pins[] = { 45, 48 };
static const unsigned southwest_i2c6_pins[] = { 47, 51 };
static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
/* Some of LPE I2S TXD pins need to have OE inversion set */
static const unsigned int southwest_lpe_altfuncs[] = {
PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
};
/*
* Two spi3 chipselects are available in different mode than the main spi3
* functionality, which is using mode 2.
*/
static const unsigned int southwest_spi3_altfuncs[] = {
PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
PINMODE(2, 0), /* 82 */
};
static const struct intel_pingroup southwest_groups[] = {
PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
};
static const char * const southwest_uart0_groups[] = { "uart0_grp" };
static const char * const southwest_uart1_groups[] = { "uart1_grp" };
static const char * const southwest_uart2_groups[] = { "uart2_grp" };
static const char * const southwest_hda_groups[] = { "hda_grp" };
static const char * const southwest_lpe_groups[] = { "lpe_grp" };
static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
static const char * const southwest_spi3_groups[] = { "spi3_grp" };
/*
* Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
* enabled only as GPIOs.
*/
static const struct intel_function southwest_functions[] = {
FUNCTION("uart0", southwest_uart0_groups),
FUNCTION("uart1", southwest_uart1_groups),
FUNCTION("uart2", southwest_uart2_groups),
FUNCTION("hda", southwest_hda_groups),
FUNCTION("lpe", southwest_lpe_groups),
FUNCTION("i2c0", southwest_i2c0_groups),
FUNCTION("i2c1", southwest_i2c1_groups),
FUNCTION("i2c2", southwest_i2c2_groups),
FUNCTION("i2c3", southwest_i2c3_groups),
FUNCTION("i2c4", southwest_i2c4_groups),
FUNCTION("i2c5", southwest_i2c5_groups),
FUNCTION("i2c6", southwest_i2c6_groups),
FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
FUNCTION("spi3", southwest_spi3_groups),
};
static const struct intel_padgroup southwest_gpps[] = {
CHV_GPP(0, 7),
CHV_GPP(15, 22),
CHV_GPP(30, 37),
CHV_GPP(45, 52),
CHV_GPP(60, 67),
CHV_GPP(75, 82),
CHV_GPP(90, 97),
};
/*
* Southwest community can generate GPIO interrupts only for the first 8
* interrupts. The upper half (8-15) can only be used to trigger GPEs.
*/
static const struct intel_community southwest_communities[] = {
CHV_COMMUNITY(southwest_gpps, 8, 0x91),
};
static const struct intel_pinctrl_soc_data southwest_soc_data = {
.uid = "1",
.pins = southwest_pins,
.npins = ARRAY_SIZE(southwest_pins),
.groups = southwest_groups,
.ngroups = ARRAY_SIZE(southwest_groups),
.functions = southwest_functions,
.nfunctions = ARRAY_SIZE(southwest_functions),
.communities = southwest_communities,
.ncommunities = ARRAY_SIZE(southwest_communities),
};
static const struct pinctrl_pin_desc north_pins[] = {
PINCTRL_PIN(0, "GPIO_DFX_0"),
PINCTRL_PIN(1, "GPIO_DFX_3"),
PINCTRL_PIN(2, "GPIO_DFX_7"),
PINCTRL_PIN(3, "GPIO_DFX_1"),
PINCTRL_PIN(4, "GPIO_DFX_5"),
PINCTRL_PIN(5, "GPIO_DFX_4"),
PINCTRL_PIN(6, "GPIO_DFX_8"),
PINCTRL_PIN(7, "GPIO_DFX_2"),
PINCTRL_PIN(8, "GPIO_DFX_6"),
PINCTRL_PIN(15, "GPIO_SUS0"),
PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
PINCTRL_PIN(17, "GPIO_SUS3"),
PINCTRL_PIN(18, "GPIO_SUS7"),
PINCTRL_PIN(19, "GPIO_SUS1"),
PINCTRL_PIN(20, "GPIO_SUS5"),
PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
PINCTRL_PIN(22, "GPIO_SUS4"),
PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
PINCTRL_PIN(24, "GPIO_SUS2"),
PINCTRL_PIN(25, "GPIO_SUS6"),
PINCTRL_PIN(26, "CX_PREQ_B"),
PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
PINCTRL_PIN(30, "TRST_B"),
PINCTRL_PIN(31, "TCK"),
PINCTRL_PIN(32, "PROCHOT_B"),
PINCTRL_PIN(33, "SVIDO_DATA"),
PINCTRL_PIN(34, "TMS"),
PINCTRL_PIN(35, "CX_PRDY_B_2"),
PINCTRL_PIN(36, "TDO_2"),
PINCTRL_PIN(37, "CX_PRDY_B"),
PINCTRL_PIN(38, "SVIDO_ALERT_B"),
PINCTRL_PIN(39, "TDO"),
PINCTRL_PIN(40, "SVIDO_CLK"),
PINCTRL_PIN(41, "TDI"),
PINCTRL_PIN(45, "GP_CAMERASB_05"),
PINCTRL_PIN(46, "GP_CAMERASB_02"),
PINCTRL_PIN(47, "GP_CAMERASB_08"),
PINCTRL_PIN(48, "GP_CAMERASB_00"),
PINCTRL_PIN(49, "GP_CAMERASB_06"),
PINCTRL_PIN(50, "GP_CAMERASB_10"),
PINCTRL_PIN(51, "GP_CAMERASB_03"),
PINCTRL_PIN(52, "GP_CAMERASB_09"),
PINCTRL_PIN(53, "GP_CAMERASB_01"),
PINCTRL_PIN(54, "GP_CAMERASB_07"),
PINCTRL_PIN(55, "GP_CAMERASB_11"),
PINCTRL_PIN(56, "GP_CAMERASB_04"),
PINCTRL_PIN(60, "PANEL0_BKLTEN"),
PINCTRL_PIN(61, "HV_DDI0_HPD"),
PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
PINCTRL_PIN(64, "HV_DDI1_HPD"),
PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
PINCTRL_PIN(68, "HV_DDI2_HPD"),
PINCTRL_PIN(69, "PANEL1_VDDEN"),
PINCTRL_PIN(70, "PANEL1_BKLTEN"),
PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
PINCTRL_PIN(72, "PANEL0_VDDEN"),
};
static const struct intel_padgroup north_gpps[] = {
CHV_GPP(0, 8),
CHV_GPP(15, 27),
CHV_GPP(30, 41),
CHV_GPP(45, 56),
CHV_GPP(60, 72),
};
/*
* North community can generate GPIO interrupts only for the first 8
* interrupts. The upper half (8-15) can only be used to trigger GPEs.
*/
static const struct intel_community north_communities[] = {
CHV_COMMUNITY(north_gpps, 8, 0x92),
};
static const struct intel_pinctrl_soc_data north_soc_data = {
.uid = "2",
.pins = north_pins,
.npins = ARRAY_SIZE(north_pins),
.communities = north_communities,
.ncommunities = ARRAY_SIZE(north_communities),
};
static const struct pinctrl_pin_desc east_pins[] = {
PINCTRL_PIN(0, "PMU_SLP_S3_B"),
PINCTRL_PIN(1, "PMU_BATLOW_B"),
PINCTRL_PIN(2, "SUS_STAT_B"),
PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
PINCTRL_PIN(4, "PMU_AC_PRESENT"),
PINCTRL_PIN(5, "PMU_PLTRST_B"),
PINCTRL_PIN(6, "PMU_SUSCLK"),
PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
PINCTRL_PIN(8, "PMU_PWRBTN_B"),
PINCTRL_PIN(9, "PMU_SLP_S4_B"),
PINCTRL_PIN(10, "PMU_WAKE_B"),
PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
};
static const struct intel_padgroup east_gpps[] = {
CHV_GPP(0, 11),
CHV_GPP(15, 26),
};
static const struct intel_community east_communities[] = {
CHV_COMMUNITY(east_gpps, 16, 0x93),
};
static const struct intel_pinctrl_soc_data east_soc_data = {
.uid = "3",
.pins = east_pins,
.npins = ARRAY_SIZE(east_pins),
.communities = east_communities,
.ncommunities = ARRAY_SIZE(east_communities),
};
static const struct pinctrl_pin_desc southeast_pins[] = {
PINCTRL_PIN(0, "MF_PLT_CLK0"),
PINCTRL_PIN(1, "PWM1"),
PINCTRL_PIN(2, "MF_PLT_CLK1"),
PINCTRL_PIN(3, "MF_PLT_CLK4"),
PINCTRL_PIN(4, "MF_PLT_CLK3"),
PINCTRL_PIN(5, "PWM0"),
PINCTRL_PIN(6, "MF_PLT_CLK5"),
PINCTRL_PIN(7, "MF_PLT_CLK2"),
PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
PINCTRL_PIN(16, "SDMMC1_CLK"),
PINCTRL_PIN(17, "SDMMC1_D0"),
PINCTRL_PIN(18, "SDMMC2_D1"),
PINCTRL_PIN(19, "SDMMC2_CLK"),
PINCTRL_PIN(20, "SDMMC1_D2"),
PINCTRL_PIN(21, "SDMMC2_D2"),
PINCTRL_PIN(22, "SDMMC2_CMD"),
PINCTRL_PIN(23, "SDMMC1_CMD"),
PINCTRL_PIN(24, "SDMMC1_D1"),
PINCTRL_PIN(25, "SDMMC2_D0"),
PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
PINCTRL_PIN(30, "SDMMC3_D1"),
PINCTRL_PIN(31, "SDMMC3_CLK"),
PINCTRL_PIN(32, "SDMMC3_D3"),
PINCTRL_PIN(33, "SDMMC3_D2"),
PINCTRL_PIN(34, "SDMMC3_CMD"),
PINCTRL_PIN(35, "SDMMC3_D0"),
PINCTRL_PIN(45, "MF_LPC_AD2"),
PINCTRL_PIN(46, "LPC_CLKRUNB"),
PINCTRL_PIN(47, "MF_LPC_AD0"),
PINCTRL_PIN(48, "LPC_FRAMEB"),
PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
PINCTRL_PIN(50, "MF_LPC_AD3"),
PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
PINCTRL_PIN(52, "MF_LPC_AD1"),
PINCTRL_PIN(60, "SPI1_MISO"),
PINCTRL_PIN(61, "SPI1_CSO_B"),
PINCTRL_PIN(62, "SPI1_CLK"),
PINCTRL_PIN(63, "MMC1_D6"),
PINCTRL_PIN(64, "SPI1_MOSI"),
PINCTRL_PIN(65, "MMC1_D5"),
PINCTRL_PIN(66, "SPI1_CS1_B"),
PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
PINCTRL_PIN(68, "MMC1_D7"),
PINCTRL_PIN(69, "MMC1_RCLK"),
PINCTRL_PIN(75, "USB_OC1_B"),
PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
PINCTRL_PIN(77, "GPIO_ALERT"),
PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
PINCTRL_PIN(79, "ILB_SERIRQ"),
PINCTRL_PIN(80, "USB_OC0_B"),
PINCTRL_PIN(81, "SDMMC3_CD_B"),
PINCTRL_PIN(82, "SPKR"),
PINCTRL_PIN(83, "SUSPWRDNACK"),
PINCTRL_PIN(84, "SPARE_PIN"),
PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
};
static const unsigned southeast_pwm0_pins[] = { 5 };
static const unsigned southeast_pwm1_pins[] = { 1 };
static const unsigned southeast_sdmmc1_pins[] = {
16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
};
static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
static const unsigned southeast_sdmmc3_pins[] = {
30, 31, 32, 33, 34, 35, 78, 81, 85,
};
static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
static const struct intel_pingroup southeast_groups[] = {
PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
};
static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
static const char * const southeast_spi1_groups[] = { "spi1_grp" };
static const char * const southeast_spi2_groups[] = { "spi2_grp" };
static const struct intel_function southeast_functions[] = {
FUNCTION("pwm0", southeast_pwm0_groups),
FUNCTION("pwm1", southeast_pwm1_groups),
FUNCTION("sdmmc1", southeast_sdmmc1_groups),
FUNCTION("sdmmc2", southeast_sdmmc2_groups),
FUNCTION("sdmmc3", southeast_sdmmc3_groups),
FUNCTION("spi1", southeast_spi1_groups),
FUNCTION("spi2", southeast_spi2_groups),
};
static const struct intel_padgroup southeast_gpps[] = {
CHV_GPP(0, 7),
CHV_GPP(15, 26),
CHV_GPP(30, 35),
CHV_GPP(45, 52),
CHV_GPP(60, 69),
CHV_GPP(75, 85),
};
static const struct intel_community southeast_communities[] = {
CHV_COMMUNITY(southeast_gpps, 16, 0x94),
};
static const struct intel_pinctrl_soc_data southeast_soc_data = {
.uid = "4",
.pins = southeast_pins,
.npins = ARRAY_SIZE(southeast_pins),
.groups = southeast_groups,
.ngroups = ARRAY_SIZE(southeast_groups),
.functions = southeast_functions,
.nfunctions = ARRAY_SIZE(southeast_functions),
.communities = southeast_communities,
.ncommunities = ARRAY_SIZE(southeast_communities),
};
static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
&southwest_soc_data,
&north_soc_data,
&east_soc_data,
&southeast_soc_data,
NULL
};
/*
* Lock to serialize register accesses
*
* Due to a silicon issue, a shared lock must be used to prevent
* concurrent accesses across the 4 GPIO controllers.
*
* See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
* errata #CHT34, for further information.
*/
static DEFINE_RAW_SPINLOCK(chv_lock);
static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
{
const struct intel_community *community = &pctrl->communities[0];
return readl(community->regs + offset);
}
static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
{
const struct intel_community *community = &pctrl->communities[0];
void __iomem *reg = community->regs + offset;
/* Write and simple read back to confirm the bus transferring done */
writel(value, reg);
readl(reg);
}
static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
unsigned int reg)
{
const struct intel_community *community = &pctrl->communities[0];
unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
return community->pad_regs + offset + reg;
}
static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
{
return readl(chv_padreg(pctrl, pin, offset));
}
static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
{
void __iomem *reg = chv_padreg(pctrl, pin, offset);
/* Write and simple read back to confirm the bus transferring done */
writel(value, reg);
readl(reg);
}
/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
{
return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
}
static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 ctrl0, ctrl1;
bool locked;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
locked = chv_pad_locked(pctrl, offset);
raw_spin_unlock_irqrestore(&chv_lock, flags);
if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
seq_puts(s, "GPIO ");
} else {
u32 mode;
mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
mode >>= CHV_PADCTRL0_PMODE_SHIFT;
seq_printf(s, "mode %d ", mode);
}
seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
if (locked)
seq_puts(s, " [LOCKED]");
}
static const struct pinctrl_ops chv_pinctrl_ops = {
.get_groups_count = intel_get_groups_count,
.get_group_name = intel_get_group_name,
.get_group_pins = intel_get_group_pins,
.pin_dbg_show = chv_pin_dbg_show,
};
static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = pctrl->dev;
const struct intel_pingroup *grp;
unsigned long flags;
int i;
grp = &pctrl->soc->groups[group];
raw_spin_lock_irqsave(&chv_lock, flags);
/* Check first that the pad is not locked */
for (i = 0; i < grp->grp.npins; i++) {
if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
raw_spin_unlock_irqrestore(&chv_lock, flags);
dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
return -EBUSY;
}
}
for (i = 0; i < grp->grp.npins; i++) {
int pin = grp->grp.pins[i];
unsigned int mode;
bool invert_oe;
u32 value;
/* Check if there is pin-specific config */
if (grp->modes)
mode = grp->modes[i];
else
mode = grp->mode;
/* Extract OE inversion */
invert_oe = mode & PINMODE_INVERT_OE;
mode &= ~PINMODE_INVERT_OE;
value = chv_readl(pctrl, pin, CHV_PADCTRL0);
/* Disable GPIO mode */
value &= ~CHV_PADCTRL0_GPIOEN;
/* Set to desired mode */
value &= ~CHV_PADCTRL0_PMODE_MASK;
value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
chv_writel(pctrl, pin, CHV_PADCTRL0, value);
/* Update for invert_oe */
value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
if (invert_oe)
value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
chv_writel(pctrl, pin, CHV_PADCTRL1, value);
dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
invert_oe ? "" : "not ");
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
unsigned int offset)
{
u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
u32 value;
/*
* One some devices the GPIO should output the inverted value from what
* device-drivers / ACPI code expects (inverted external buffer?). The
* BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
* preserve this flag if the pin is already setup as GPIO.
*/
value = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (value & CHV_PADCTRL0_GPIOEN)
invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
value = chv_readl(pctrl, offset, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~invrxtx_mask;
chv_writel(pctrl, offset, CHV_PADCTRL1, value);
}
static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&chv_lock, flags);
if (chv_pad_locked(pctrl, offset)) {
value = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (!(value & CHV_PADCTRL0_GPIOEN)) {
/* Locked so cannot enable */
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
} else {
struct intel_community_context *cctx = &pctrl->context.communities[0];
int i;
/* Reset the interrupt mapping */
for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
if (cctx->intr_lines[i] == offset) {
cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
break;
}
}
/* Disable interrupt generation */
chv_gpio_clear_triggering(pctrl, offset);
value = chv_readl(pctrl, offset, CHV_PADCTRL0);
/*
* If the pin is in HiZ mode (both TX and RX buffers are
* disabled) we turn it to be input now.
*/
if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
(CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
}
/* Switch to a GPIO mode */
value |= CHV_PADCTRL0_GPIOEN;
chv_writel(pctrl, offset, CHV_PADCTRL0, value);
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
if (!chv_pad_locked(pctrl, offset))
chv_gpio_clear_triggering(pctrl, offset);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 ctrl0;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
if (input)
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
else
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static const struct pinmux_ops chv_pinmux_ops = {
.get_functions_count = intel_get_functions_count,
.get_function_name = intel_get_function_name,
.get_function_groups = intel_get_function_groups,
.set_mux = chv_pinmux_set_mux,
.gpio_request_enable = chv_gpio_request_enable,
.gpio_disable_free = chv_gpio_disable_free,
.gpio_set_direction = chv_gpio_set_direction,
};
static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
u32 ctrl0, ctrl1;
u16 arg = 0;
u32 term;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
raw_spin_unlock_irqrestore(&chv_lock, flags);
term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (term)
return -EINVAL;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
return -EINVAL;
switch (term) {
case CHV_PADCTRL0_TERM_20K:
arg = 20000;
break;
case CHV_PADCTRL0_TERM_5K:
arg = 5000;
break;
case CHV_PADCTRL0_TERM_1K:
arg = 1000;
break;
}
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
return -EINVAL;
switch (term) {
case CHV_PADCTRL0_TERM_20K:
arg = 20000;
break;
case CHV_PADCTRL0_TERM_5K:
arg = 5000;
break;
}
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
u32 cfg;
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (ctrl1 & CHV_PADCTRL1_ODEN)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
return -EINVAL;
break;
}
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 arg)
{
unsigned long flags;
u32 ctrl0, pull;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
break;
case PIN_CONFIG_BIAS_PULL_UP:
ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
switch (arg) {
case 1000:
/* For 1k there is only pull up */
pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
break;
case 5000:
pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
break;
case 20000:
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
switch (arg) {
case 5000:
pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
break;
case 20000:
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
ctrl0 |= pull;
break;
default:
raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
bool enable)
{
unsigned long flags;
u32 ctrl1;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
if (enable)
ctrl1 |= CHV_PADCTRL1_ODEN;
else
ctrl1 &= ~CHV_PADCTRL1_ODEN;
chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int nconfigs)
{
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct device *dev = pctrl->dev;
enum pin_config_param param;
int i, ret;
u32 arg;
if (chv_pad_locked(pctrl, pin))
return -EBUSY;
for (i = 0; i < nconfigs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = chv_config_set_pull(pctrl, pin, param, arg);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
ret = chv_config_set_oden(pctrl, pin, false);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
ret = chv_config_set_oden(pctrl, pin, true);
if (ret)
return ret;
break;
default:
return -ENOTSUPP;
}
dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
}
return 0;
}
static int chv_config_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
const unsigned int *pins;
unsigned int npins;
int ret;
ret = intel_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
ret = chv_config_get(pctldev, pins[0], config);
if (ret)
return ret;
return 0;
}
static int chv_config_group_set(struct pinctrl_dev *pctldev,
unsigned int group, unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int npins;
int i, ret;
ret = intel_get_group_pins(pctldev, group, &pins, &npins);
if (ret)
return ret;
for (i = 0; i < npins; i++) {
ret = chv_config_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops chv_pinconf_ops = {
.is_generic = true,
.pin_config_set = chv_config_set,
.pin_config_get = chv_config_get,
.pin_config_group_get = chv_config_group_get,
.pin_config_group_set = chv_config_group_set,
};
static struct pinctrl_desc chv_pinctrl_desc = {
.pctlops = &chv_pinctrl_ops,
.pmxops = &chv_pinmux_ops,
.confops = &chv_pinconf_ops,
.owner = THIS_MODULE,
};
static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
u32 ctrl0, cfg;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
}
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
u32 ctrl0;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
if (value)
ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
else
ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
u32 ctrl0, direction;
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
raw_spin_unlock_irqrestore(&chv_lock, flags);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
chv_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static const struct gpio_chip chv_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = chv_gpio_get_direction,
.direction_input = chv_gpio_direction_input,
.direction_output = chv_gpio_direction_output,
.get = chv_gpio_get,
.set = chv_gpio_set,
};
static void chv_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 intr_line;
raw_spin_lock(&chv_lock);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
raw_spin_unlock(&chv_lock);
}
static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
u32 value, intr_line;
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
value = chv_pctrl_readl(pctrl, CHV_INTMASK);
if (mask)
value &= ~BIT(intr_line);
else
value |= BIT(intr_line);
chv_pctrl_writel(pctrl, CHV_INTMASK, value);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static void chv_gpio_irq_mask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
chv_gpio_irq_mask_unmask(gc, hwirq, true);
gpiochip_disable_irq(gc, hwirq);
}
static void chv_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
gpiochip_enable_irq(gc, hwirq);
chv_gpio_irq_mask_unmask(gc, hwirq, false);
}
static unsigned chv_gpio_irq_startup(struct irq_data *d)
{
/*
* Check if the interrupt has been requested with 0 as triggering
* type. In that case it is assumed that the current values
* programmed to the hardware are used (e.g BIOS configured
* defaults).
*
* In that case ->irq_set_type() will never be called so we need to
* read back the values from hardware now, set correct flow handler
* and update mappings before the interrupt is being used.
*/
if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct device *dev = pctrl->dev;
struct intel_community_context *cctx = &pctrl->context.communities[0];
irq_hw_number_t hwirq = irqd_to_hwirq(d);
irq_flow_handler_t handler;
unsigned long flags;
u32 intsel, value;
raw_spin_lock_irqsave(&chv_lock, flags);
intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
handler = handle_level_irq;
else
handler = handle_edge_irq;
if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
irq_set_handler_locked(d, handler);
dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
intsel, hwirq);
cctx->intr_lines[intsel] = hwirq;
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
chv_gpio_irq_unmask(d);
return 0;
}
static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
{
struct device *dev = pctrl->dev;
struct intel_community_context *cctx = &pctrl->context.communities[0];
const struct intel_community *community = &pctrl->communities[0];
u32 value, intsel;
int i;
value = chv_readl(pctrl, pin, CHV_PADCTRL0);
intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
if (cctx->intr_lines[intsel] == pin)
return 0;
if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
cctx->intr_lines[intsel] = pin;
return 0;
}
/*
* The interrupt line selected by the BIOS is already in use by
* another pin, this is a known BIOS bug found on several models.
* But this may also be caused by Linux deciding to use a pin as
* IRQ which was not expected to be used as such by the BIOS authors,
* so log this at info level only.
*/
dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
cctx->intr_lines[intsel], pin);
if (chv_pad_locked(pctrl, pin))
return -EBUSY;
/*
* The BIOS fills the interrupt lines from 0 counting up, start at
* the other end to find a free interrupt line to workaround this.
*/
for (i = community->nirqs - 1; i >= 0; i--) {
if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
break;
}
if (i < 0)
return -EBUSY;
dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
chv_writel(pctrl, pin, CHV_PADCTRL0, value);
cctx->intr_lines[i] = pin;
return 0;
}
static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 value;
int ret;
raw_spin_lock_irqsave(&chv_lock, flags);
ret = chv_gpio_set_intr_line(pctrl, hwirq);
if (ret) {
raw_spin_unlock_irqrestore(&chv_lock, flags);
return ret;
}
/*
* Pins which can be used as shared interrupt are configured in
* BIOS. Driver trusts BIOS configurations and assigns different
* handler according to the irq type.
*
* Driver needs to save the mapping between each pin and
* its interrupt line.
* 1. If the pin cfg is locked in BIOS:
* Trust BIOS has programmed IntWakeCfg bits correctly,
* driver just needs to save the mapping.
* 2. If the pin cfg is not locked in BIOS:
* Driver programs the IntWakeCfg bits and save the mapping.
*/
if (!chv_pad_locked(pctrl, hwirq)) {
value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
if (type & IRQ_TYPE_EDGE_BOTH) {
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
else if (type & IRQ_TYPE_EDGE_RISING)
value |= CHV_PADCTRL1_INTWAKECFG_RISING;
else if (type & IRQ_TYPE_EDGE_FALLING)
value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
} else if (type & IRQ_TYPE_LEVEL_MASK) {
value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
if (type & IRQ_TYPE_LEVEL_LOW)
value |= CHV_PADCTRL1_INVRXTX_RXDATA;
}
chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
}
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static const struct irq_chip chv_gpio_irq_chip = {
.name = "chv-gpio",
.irq_startup = chv_gpio_irq_startup,
.irq_ack = chv_gpio_irq_ack,
.irq_mask = chv_gpio_irq_mask,
.irq_unmask = chv_gpio_irq_unmask,
.irq_set_type = chv_gpio_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static void chv_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct device *dev = pctrl->dev;
const struct intel_community *community = &pctrl->communities[0];
struct intel_community_context *cctx = &pctrl->context.communities[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
u32 intr_line;
chained_irq_enter(chip, desc);
raw_spin_lock_irqsave(&chv_lock, flags);
pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
raw_spin_unlock_irqrestore(&chv_lock, flags);
for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int offset;
offset = cctx->intr_lines[intr_line];
if (offset == CHV_INVALID_HWIRQ) {
dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line);
/* Some boards expect hwirq 0 to trigger in this case */
offset = 0;
}
generic_handle_domain_irq(gc->irq.domain, offset);
}
chained_irq_exit(chip, desc);
}
/*
* Certain machines seem to hardcode Linux IRQ numbers in their ACPI
* tables. Since we leave GPIOs that are not capable of generating
* interrupts out of the irqdomain the numbering will be different and
* cause devices using the hardcoded IRQ numbers fail. In order not to
* break such machines we will only mask pins from irqdomain if the machine
* is not listed below.
*/
static const struct dmi_system_id chv_no_valid_mask[] = {
/* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
{
.ident = "Intel_Strago based Chromebooks (All models)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
},
},
{
.ident = "HP Chromebook 11 G5 (Setzer)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
},
},
{
.ident = "Acer Chromebook R11 (Cyan)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
},
},
{
.ident = "Samsung Chromebook 3 (Celes)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
},
},
{}
};
static void chv_init_irq_valid_mask(struct gpio_chip *chip,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
const struct intel_community *community = &pctrl->communities[0];
int i;
/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
u32 intsel;
desc = &pctrl->soc->pins[i];
intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
if (intsel >= community->nirqs)
clear_bit(desc->number, valid_mask);
}
}
static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
const struct intel_community *community = &pctrl->communities[0];
/*
* The same set of machines in chv_no_valid_mask[] have incorrectly
* configured GPIOs that generate spurious interrupts so we use
* this same list to apply another quirk for them.
*
* See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
*/
if (!pctrl->chip.irq.init_valid_mask) {
/*
* Mask all interrupts the community is able to generate
* but leave the ones that can only generate GPEs unmasked.
*/
chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
}
/* Clear all interrupts */
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
return 0;
}
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
struct device *dev = pctrl->dev;
const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
int ret, i;
for (i = 0; i < community->ngpps; i++) {
gpp = &community->gpps[i];
ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
if (ret) {
dev_err(dev, "failed to add GPIO pin range\n");
return ret;
}
}
return 0;
}
static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
{
const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
struct gpio_chip *chip = &pctrl->chip;
struct device *dev = pctrl->dev;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
int ret, i, irq_base;
*chip = chv_gpio_chip;
chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
chip->label = dev_name(dev);
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
chip->parent = dev;
chip->base = -1;
pctrl->irq = irq;
gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
chip->irq.init_hw = chv_gpio_irq_init_hw;
chip->irq.parent_handler = chv_gpio_irq_handler;
chip->irq.num_parents = 1;
chip->irq.parents = &pctrl->irq;
chip->irq.default_type = IRQ_TYPE_NONE;
chip->irq.handler = handle_bad_irq;
if (need_valid_mask) {
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
} else {
irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
}
ret = devm_gpiochip_add_data(dev, chip, pctrl);
if (ret) {
dev_err(dev, "Failed to register gpiochip\n");
return ret;
}
if (!need_valid_mask) {
for (i = 0; i < community->ngpps; i++) {
gpp = &community->gpps[i];
irq_domain_associate_many(chip->irq.domain, irq_base,
gpp->base, gpp->size);
irq_base += gpp->size;
}
}
return 0;
}
static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
acpi_physical_address address, u32 bits, u64 *value,
void *handler_context, void *region_context)
{
struct intel_pinctrl *pctrl = region_context;
unsigned long flags;
acpi_status ret = AE_OK;
raw_spin_lock_irqsave(&chv_lock, flags);
if (function == ACPI_WRITE)
chv_pctrl_writel(pctrl, address, *value);
else if (function == ACPI_READ)
*value = chv_pctrl_readl(pctrl, address);
else
ret = AE_BAD_PARAMETER;
raw_spin_unlock_irqrestore(&chv_lock, flags);
return ret;
}
static int chv_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data;
struct intel_community_context *cctx;
struct intel_community *community;
struct device *dev = &pdev->dev;
struct intel_pinctrl *pctrl;
acpi_status status;
unsigned int i;
int ret, irq;
soc_data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(soc_data))
return PTR_ERR(soc_data);
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = dev;
pctrl->soc = soc_data;
pctrl->ncommunities = pctrl->soc->ncommunities;
pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
pctrl->ncommunities * sizeof(*pctrl->communities),
GFP_KERNEL);
if (!pctrl->communities)
return -ENOMEM;
community = &pctrl->communities[0];
community->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(community->regs))
return PTR_ERR(community->regs);
community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
#ifdef CONFIG_PM_SLEEP
pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
sizeof(*pctrl->context.pads),
GFP_KERNEL);
if (!pctrl->context.pads)
return -ENOMEM;
#endif
pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
sizeof(*pctrl->context.communities),
GFP_KERNEL);
if (!pctrl->context.communities)
return -ENOMEM;
cctx = &pctrl->context.communities[0];
for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
pctrl->pctldesc = chv_pinctrl_desc;
pctrl->pctldesc.name = dev_name(dev);
pctrl->pctldesc.pins = pctrl->soc->pins;
pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
if (IS_ERR(pctrl->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(pctrl->pctldev);
}
ret = chv_gpio_probe(pctrl, irq);
if (ret)
return ret;
status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
community->acpi_space_id,
chv_pinctrl_mmio_access_handler,
NULL, pctrl);
if (ACPI_FAILURE(status))
dev_err(dev, "failed to install ACPI addr space handler\n");
platform_set_drvdata(pdev, pctrl);
return 0;
}
static int chv_pinctrl_remove(struct platform_device *pdev)
{
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
const struct intel_community *community = &pctrl->communities[0];
acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
community->acpi_space_id,
chv_pinctrl_mmio_access_handler);
return 0;
}
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned long flags;
int i;
raw_spin_lock_irqsave(&chv_lock, flags);
cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
struct intel_pad_context *ctx = &pctrl->context.pads[i];
desc = &pctrl->soc->pins[i];
if (chv_pad_locked(pctrl, desc->number))
continue;
ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned long flags;
int i;
raw_spin_lock_irqsave(&chv_lock, flags);
/*
* Mask all interrupts before restoring per-pin configuration
* registers because we don't know in which state BIOS left them
* upon exiting suspend.
*/
chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
struct intel_pad_context *ctx = &pctrl->context.pads[i];
u32 val;
desc = &pctrl->soc->pins[i];
if (chv_pad_locked(pctrl, desc->number))
continue;
/* Only restore if our saved state differs from the current */
val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
val &= ~CHV_PADCTRL0_GPIORXSTATE;
if (ctx->padctrl0 != val) {
chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
chv_readl(pctrl, desc->number, CHV_PADCTRL0));
}
val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
if (ctx->padctrl1 != val) {
chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
chv_readl(pctrl, desc->number, CHV_PADCTRL1));
}
}
/*
* Now that all pins are restored to known state, we can restore
* the interrupt mask register as well.
*/
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops,
chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq);
static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
{ "INT33FF", (kernel_ulong_t)chv_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
static struct platform_driver chv_pinctrl_driver = {
.probe = chv_pinctrl_probe,
.remove = chv_pinctrl_remove,
.driver = {
.name = "cherryview-pinctrl",
.pm = pm_sleep_ptr(&chv_pinctrl_pm_ops),
.acpi_match_table = chv_pinctrl_acpi_match,
},
};
static int __init chv_pinctrl_init(void)
{
return platform_driver_register(&chv_pinctrl_driver);
}
subsys_initcall(chv_pinctrl_init);
static void __exit chv_pinctrl_exit(void)
{
platform_driver_unregister(&chv_pinctrl_driver);
}
module_exit(chv_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-cherryview.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Sunrisepoint PCH pinctrl/GPIO driver
*
* Copyright (C) 2015, Intel Corporation
* Authors: Mathias Nyman <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define SPT_H_PAD_OWN 0x020
#define SPT_H_PADCFGLOCK 0x090
#define SPT_H_HOSTSW_OWN 0x0d0
#define SPT_H_GPI_IS 0x100
#define SPT_H_GPI_IE 0x120
#define SPT_LP_PAD_OWN 0x020
#define SPT_LP_PADCFGLOCK 0x0a0
#define SPT_LP_HOSTSW_OWN 0x0d0
#define SPT_LP_GPI_IS 0x100
#define SPT_LP_GPI_IE 0x120
#define SPT_H_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define SPT_H_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H)
#define SPT_LP_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 24, 4, SPT_LP)
/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
PINCTRL_PIN(14, "SUS_STATB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "SD_1P8_SEL"),
PINCTRL_PIN(17, "SD_PWR_EN_B"),
PINCTRL_PIN(18, "ISH_GP_0"),
PINCTRL_PIN(19, "ISH_GP_1"),
PINCTRL_PIN(20, "ISH_GP_2"),
PINCTRL_PIN(21, "ISH_GP_3"),
PINCTRL_PIN(22, "ISH_GP_4"),
PINCTRL_PIN(23, "ISH_GP_5"),
/* GPP_B */
PINCTRL_PIN(24, "CORE_VID_0"),
PINCTRL_PIN(25, "CORE_VID_1"),
PINCTRL_PIN(26, "VRALERTB"),
PINCTRL_PIN(27, "CPU_GP_2"),
PINCTRL_PIN(28, "CPU_GP_3"),
PINCTRL_PIN(29, "SRCCLKREQB_0"),
PINCTRL_PIN(30, "SRCCLKREQB_1"),
PINCTRL_PIN(31, "SRCCLKREQB_2"),
PINCTRL_PIN(32, "SRCCLKREQB_3"),
PINCTRL_PIN(33, "SRCCLKREQB_4"),
PINCTRL_PIN(34, "SRCCLKREQB_5"),
PINCTRL_PIN(35, "EXT_PWR_GATEB"),
PINCTRL_PIN(36, "SLP_S0B"),
PINCTRL_PIN(37, "PLTRSTB"),
PINCTRL_PIN(38, "SPKR"),
PINCTRL_PIN(39, "GSPI0_CSB"),
PINCTRL_PIN(40, "GSPI0_CLK"),
PINCTRL_PIN(41, "GSPI0_MISO"),
PINCTRL_PIN(42, "GSPI0_MOSI"),
PINCTRL_PIN(43, "GSPI1_CSB"),
PINCTRL_PIN(44, "GSPI1_CLK"),
PINCTRL_PIN(45, "GSPI1_MISO"),
PINCTRL_PIN(46, "GSPI1_MOSI"),
PINCTRL_PIN(47, "SML1ALERTB"),
/* GPP_C */
PINCTRL_PIN(48, "SMBCLK"),
PINCTRL_PIN(49, "SMBDATA"),
PINCTRL_PIN(50, "SMBALERTB"),
PINCTRL_PIN(51, "SML0CLK"),
PINCTRL_PIN(52, "SML0DATA"),
PINCTRL_PIN(53, "SML0ALERTB"),
PINCTRL_PIN(54, "SML1CLK"),
PINCTRL_PIN(55, "SML1DATA"),
PINCTRL_PIN(56, "UART0_RXD"),
PINCTRL_PIN(57, "UART0_TXD"),
PINCTRL_PIN(58, "UART0_RTSB"),
PINCTRL_PIN(59, "UART0_CTSB"),
PINCTRL_PIN(60, "UART1_RXD"),
PINCTRL_PIN(61, "UART1_TXD"),
PINCTRL_PIN(62, "UART1_RTSB"),
PINCTRL_PIN(63, "UART1_CTSB"),
PINCTRL_PIN(64, "I2C0_SDA"),
PINCTRL_PIN(65, "I2C0_SCL"),
PINCTRL_PIN(66, "I2C1_SDA"),
PINCTRL_PIN(67, "I2C1_SCL"),
PINCTRL_PIN(68, "UART2_RXD"),
PINCTRL_PIN(69, "UART2_TXD"),
PINCTRL_PIN(70, "UART2_RTSB"),
PINCTRL_PIN(71, "UART2_CTSB"),
/* GPP_D */
PINCTRL_PIN(72, "SPI1_CSB"),
PINCTRL_PIN(73, "SPI1_CLK"),
PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(76, "FLASHTRIG"),
PINCTRL_PIN(77, "ISH_I2C0_SDA"),
PINCTRL_PIN(78, "ISH_I2C0_SCL"),
PINCTRL_PIN(79, "ISH_I2C1_SDA"),
PINCTRL_PIN(80, "ISH_I2C1_SCL"),
PINCTRL_PIN(81, "ISH_SPI_CSB"),
PINCTRL_PIN(82, "ISH_SPI_CLK"),
PINCTRL_PIN(83, "ISH_SPI_MISO"),
PINCTRL_PIN(84, "ISH_SPI_MOSI"),
PINCTRL_PIN(85, "ISH_UART0_RXD"),
PINCTRL_PIN(86, "ISH_UART0_TXD"),
PINCTRL_PIN(87, "ISH_UART0_RTSB"),
PINCTRL_PIN(88, "ISH_UART0_CTSB"),
PINCTRL_PIN(89, "DMIC_CLK_1"),
PINCTRL_PIN(90, "DMIC_DATA_1"),
PINCTRL_PIN(91, "DMIC_CLK_0"),
PINCTRL_PIN(92, "DMIC_DATA_0"),
PINCTRL_PIN(93, "SPI1_IO_2"),
PINCTRL_PIN(94, "SPI1_IO_3"),
PINCTRL_PIN(95, "SSP_MCLK"),
/* GPP_E */
PINCTRL_PIN(96, "SATAXPCIE_0"),
PINCTRL_PIN(97, "SATAXPCIE_1"),
PINCTRL_PIN(98, "SATAXPCIE_2"),
PINCTRL_PIN(99, "CPU_GP_0"),
PINCTRL_PIN(100, "SATA_DEVSLP_0"),
PINCTRL_PIN(101, "SATA_DEVSLP_1"),
PINCTRL_PIN(102, "SATA_DEVSLP_2"),
PINCTRL_PIN(103, "CPU_GP_1"),
PINCTRL_PIN(104, "SATA_LEDB"),
PINCTRL_PIN(105, "USB2_OCB_0"),
PINCTRL_PIN(106, "USB2_OCB_1"),
PINCTRL_PIN(107, "USB2_OCB_2"),
PINCTRL_PIN(108, "USB2_OCB_3"),
PINCTRL_PIN(109, "DDSP_HPD_0"),
PINCTRL_PIN(110, "DDSP_HPD_1"),
PINCTRL_PIN(111, "DDSP_HPD_2"),
PINCTRL_PIN(112, "DDSP_HPD_3"),
PINCTRL_PIN(113, "EDP_HPD"),
PINCTRL_PIN(114, "DDPB_CTRLCLK"),
PINCTRL_PIN(115, "DDPB_CTRLDATA"),
PINCTRL_PIN(116, "DDPC_CTRLCLK"),
PINCTRL_PIN(117, "DDPC_CTRLDATA"),
PINCTRL_PIN(118, "DDPD_CTRLCLK"),
PINCTRL_PIN(119, "DDPD_CTRLDATA"),
/* GPP_F */
PINCTRL_PIN(120, "SSP2_SCLK"),
PINCTRL_PIN(121, "SSP2_SFRM"),
PINCTRL_PIN(122, "SSP2_TXD"),
PINCTRL_PIN(123, "SSP2_RXD"),
PINCTRL_PIN(124, "I2C2_SDA"),
PINCTRL_PIN(125, "I2C2_SCL"),
PINCTRL_PIN(126, "I2C3_SDA"),
PINCTRL_PIN(127, "I2C3_SCL"),
PINCTRL_PIN(128, "I2C4_SDA"),
PINCTRL_PIN(129, "I2C4_SCL"),
PINCTRL_PIN(130, "I2C5_SDA"),
PINCTRL_PIN(131, "I2C5_SCL"),
PINCTRL_PIN(132, "EMMC_CMD"),
PINCTRL_PIN(133, "EMMC_DATA_0"),
PINCTRL_PIN(134, "EMMC_DATA_1"),
PINCTRL_PIN(135, "EMMC_DATA_2"),
PINCTRL_PIN(136, "EMMC_DATA_3"),
PINCTRL_PIN(137, "EMMC_DATA_4"),
PINCTRL_PIN(138, "EMMC_DATA_5"),
PINCTRL_PIN(139, "EMMC_DATA_6"),
PINCTRL_PIN(140, "EMMC_DATA_7"),
PINCTRL_PIN(141, "EMMC_RCLK"),
PINCTRL_PIN(142, "EMMC_CLK"),
PINCTRL_PIN(143, "GPP_F_23"),
/* GPP_G */
PINCTRL_PIN(144, "SD_CMD"),
PINCTRL_PIN(145, "SD_DATA_0"),
PINCTRL_PIN(146, "SD_DATA_1"),
PINCTRL_PIN(147, "SD_DATA_2"),
PINCTRL_PIN(148, "SD_DATA_3"),
PINCTRL_PIN(149, "SD_CDB"),
PINCTRL_PIN(150, "SD_CLK"),
PINCTRL_PIN(151, "SD_WP"),
};
static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
static const unsigned sptlp_emmc_pins[] = {
132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
};
static const unsigned sptlp_sd_pins[] = {
144, 145, 146, 147, 148, 149, 150, 151,
};
static const struct intel_pingroup sptlp_groups[] = {
PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
};
static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
static const char * const sptlp_sd_groups[] = { "sd_grp" };
static const struct intel_function sptlp_functions[] = {
FUNCTION("spi0", sptlp_spi0_groups),
FUNCTION("spi1", sptlp_spi1_groups),
FUNCTION("uart0", sptlp_uart0_groups),
FUNCTION("uart1", sptlp_uart1_groups),
FUNCTION("uart2", sptlp_uart2_groups),
FUNCTION("i2c0", sptlp_i2c0_groups),
FUNCTION("i2c1", sptlp_i2c1_groups),
FUNCTION("i2c2", sptlp_i2c2_groups),
FUNCTION("i2c3", sptlp_i2c3_groups),
FUNCTION("i2c4", sptlp_i2c4_groups),
FUNCTION("i2c5", sptlp_i2c5_groups),
FUNCTION("ssp2", sptlp_ssp2_groups),
FUNCTION("emmc", sptlp_emmc_groups),
FUNCTION("sd", sptlp_sd_groups),
};
static const struct intel_community sptlp_communities[] = {
SPT_LP_COMMUNITY(0, 0, 47),
SPT_LP_COMMUNITY(1, 48, 119),
SPT_LP_COMMUNITY(2, 120, 151),
};
static const struct intel_pinctrl_soc_data sptlp_soc_data = {
.pins = sptlp_pins,
.npins = ARRAY_SIZE(sptlp_pins),
.groups = sptlp_groups,
.ngroups = ARRAY_SIZE(sptlp_groups),
.functions = sptlp_functions,
.nfunctions = ARRAY_SIZE(sptlp_functions),
.communities = sptlp_communities,
.ncommunities = ARRAY_SIZE(sptlp_communities),
};
/* Sunrisepoint-H */
static const struct pinctrl_pin_desc spth_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
PINCTRL_PIN(14, "SUS_STATB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "CLKOUT_48"),
PINCTRL_PIN(17, "ISH_GP_7"),
PINCTRL_PIN(18, "ISH_GP_0"),
PINCTRL_PIN(19, "ISH_GP_1"),
PINCTRL_PIN(20, "ISH_GP_2"),
PINCTRL_PIN(21, "ISH_GP_3"),
PINCTRL_PIN(22, "ISH_GP_4"),
PINCTRL_PIN(23, "ISH_GP_5"),
/* GPP_B */
PINCTRL_PIN(24, "CORE_VID_0"),
PINCTRL_PIN(25, "CORE_VID_1"),
PINCTRL_PIN(26, "VRALERTB"),
PINCTRL_PIN(27, "CPU_GP_2"),
PINCTRL_PIN(28, "CPU_GP_3"),
PINCTRL_PIN(29, "SRCCLKREQB_0"),
PINCTRL_PIN(30, "SRCCLKREQB_1"),
PINCTRL_PIN(31, "SRCCLKREQB_2"),
PINCTRL_PIN(32, "SRCCLKREQB_3"),
PINCTRL_PIN(33, "SRCCLKREQB_4"),
PINCTRL_PIN(34, "SRCCLKREQB_5"),
PINCTRL_PIN(35, "EXT_PWR_GATEB"),
PINCTRL_PIN(36, "SLP_S0B"),
PINCTRL_PIN(37, "PLTRSTB"),
PINCTRL_PIN(38, "SPKR"),
PINCTRL_PIN(39, "GSPI0_CSB"),
PINCTRL_PIN(40, "GSPI0_CLK"),
PINCTRL_PIN(41, "GSPI0_MISO"),
PINCTRL_PIN(42, "GSPI0_MOSI"),
PINCTRL_PIN(43, "GSPI1_CSB"),
PINCTRL_PIN(44, "GSPI1_CLK"),
PINCTRL_PIN(45, "GSPI1_MISO"),
PINCTRL_PIN(46, "GSPI1_MOSI"),
PINCTRL_PIN(47, "SML1ALERTB"),
/* GPP_C */
PINCTRL_PIN(48, "SMBCLK"),
PINCTRL_PIN(49, "SMBDATA"),
PINCTRL_PIN(50, "SMBALERTB"),
PINCTRL_PIN(51, "SML0CLK"),
PINCTRL_PIN(52, "SML0DATA"),
PINCTRL_PIN(53, "SML0ALERTB"),
PINCTRL_PIN(54, "SML1CLK"),
PINCTRL_PIN(55, "SML1DATA"),
PINCTRL_PIN(56, "UART0_RXD"),
PINCTRL_PIN(57, "UART0_TXD"),
PINCTRL_PIN(58, "UART0_RTSB"),
PINCTRL_PIN(59, "UART0_CTSB"),
PINCTRL_PIN(60, "UART1_RXD"),
PINCTRL_PIN(61, "UART1_TXD"),
PINCTRL_PIN(62, "UART1_RTSB"),
PINCTRL_PIN(63, "UART1_CTSB"),
PINCTRL_PIN(64, "I2C0_SDA"),
PINCTRL_PIN(65, "I2C0_SCL"),
PINCTRL_PIN(66, "I2C1_SDA"),
PINCTRL_PIN(67, "I2C1_SCL"),
PINCTRL_PIN(68, "UART2_RXD"),
PINCTRL_PIN(69, "UART2_TXD"),
PINCTRL_PIN(70, "UART2_RTSB"),
PINCTRL_PIN(71, "UART2_CTSB"),
/* GPP_D */
PINCTRL_PIN(72, "SPI1_CSB"),
PINCTRL_PIN(73, "SPI1_CLK"),
PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(76, "ISH_I2C2_SDA"),
PINCTRL_PIN(77, "SSP0_SFRM"),
PINCTRL_PIN(78, "SSP0_TXD"),
PINCTRL_PIN(79, "SSP0_RXD"),
PINCTRL_PIN(80, "SSP0_SCLK"),
PINCTRL_PIN(81, "ISH_SPI_CSB"),
PINCTRL_PIN(82, "ISH_SPI_CLK"),
PINCTRL_PIN(83, "ISH_SPI_MISO"),
PINCTRL_PIN(84, "ISH_SPI_MOSI"),
PINCTRL_PIN(85, "ISH_UART0_RXD"),
PINCTRL_PIN(86, "ISH_UART0_TXD"),
PINCTRL_PIN(87, "ISH_UART0_RTSB"),
PINCTRL_PIN(88, "ISH_UART0_CTSB"),
PINCTRL_PIN(89, "DMIC_CLK_1"),
PINCTRL_PIN(90, "DMIC_DATA_1"),
PINCTRL_PIN(91, "DMIC_CLK_0"),
PINCTRL_PIN(92, "DMIC_DATA_0"),
PINCTRL_PIN(93, "SPI1_IO_2"),
PINCTRL_PIN(94, "SPI1_IO_3"),
PINCTRL_PIN(95, "ISH_I2C2_SCL"),
/* GPP_E */
PINCTRL_PIN(96, "SATAXPCIE_0"),
PINCTRL_PIN(97, "SATAXPCIE_1"),
PINCTRL_PIN(98, "SATAXPCIE_2"),
PINCTRL_PIN(99, "CPU_GP_0"),
PINCTRL_PIN(100, "SATA_DEVSLP_0"),
PINCTRL_PIN(101, "SATA_DEVSLP_1"),
PINCTRL_PIN(102, "SATA_DEVSLP_2"),
PINCTRL_PIN(103, "CPU_GP_1"),
PINCTRL_PIN(104, "SATA_LEDB"),
PINCTRL_PIN(105, "USB2_OCB_0"),
PINCTRL_PIN(106, "USB2_OCB_1"),
PINCTRL_PIN(107, "USB2_OCB_2"),
PINCTRL_PIN(108, "USB2_OCB_3"),
/* GPP_F */
PINCTRL_PIN(109, "SATAXPCIE_3"),
PINCTRL_PIN(110, "SATAXPCIE_4"),
PINCTRL_PIN(111, "SATAXPCIE_5"),
PINCTRL_PIN(112, "SATAXPCIE_6"),
PINCTRL_PIN(113, "SATAXPCIE_7"),
PINCTRL_PIN(114, "SATA_DEVSLP_3"),
PINCTRL_PIN(115, "SATA_DEVSLP_4"),
PINCTRL_PIN(116, "SATA_DEVSLP_5"),
PINCTRL_PIN(117, "SATA_DEVSLP_6"),
PINCTRL_PIN(118, "SATA_DEVSLP_7"),
PINCTRL_PIN(119, "SATA_SCLOCK"),
PINCTRL_PIN(120, "SATA_SLOAD"),
PINCTRL_PIN(121, "SATA_SDATAOUT1"),
PINCTRL_PIN(122, "SATA_SDATAOUT0"),
PINCTRL_PIN(123, "GPP_F_14"),
PINCTRL_PIN(124, "USB_OCB_4"),
PINCTRL_PIN(125, "USB_OCB_5"),
PINCTRL_PIN(126, "USB_OCB_6"),
PINCTRL_PIN(127, "USB_OCB_7"),
PINCTRL_PIN(128, "L_VDDEN"),
PINCTRL_PIN(129, "L_BKLTEN"),
PINCTRL_PIN(130, "L_BKLTCTL"),
PINCTRL_PIN(131, "GPP_F_22"),
PINCTRL_PIN(132, "GPP_F_23"),
/* GPP_G */
PINCTRL_PIN(133, "FAN_TACH_0"),
PINCTRL_PIN(134, "FAN_TACH_1"),
PINCTRL_PIN(135, "FAN_TACH_2"),
PINCTRL_PIN(136, "FAN_TACH_3"),
PINCTRL_PIN(137, "FAN_TACH_4"),
PINCTRL_PIN(138, "FAN_TACH_5"),
PINCTRL_PIN(139, "FAN_TACH_6"),
PINCTRL_PIN(140, "FAN_TACH_7"),
PINCTRL_PIN(141, "FAN_PWM_0"),
PINCTRL_PIN(142, "FAN_PWM_1"),
PINCTRL_PIN(143, "FAN_PWM_2"),
PINCTRL_PIN(144, "FAN_PWM_3"),
PINCTRL_PIN(145, "GSXDOUT"),
PINCTRL_PIN(146, "GSXSLOAD"),
PINCTRL_PIN(147, "GSXDIN"),
PINCTRL_PIN(148, "GSXRESETB"),
PINCTRL_PIN(149, "GSXCLK"),
PINCTRL_PIN(150, "ADR_COMPLETE"),
PINCTRL_PIN(151, "NMIB"),
PINCTRL_PIN(152, "SMIB"),
PINCTRL_PIN(153, "GPP_G_20"),
PINCTRL_PIN(154, "GPP_G_21"),
PINCTRL_PIN(155, "GPP_G_22"),
PINCTRL_PIN(156, "GPP_G_23"),
/* GPP_H */
PINCTRL_PIN(157, "SRCCLKREQB_6"),
PINCTRL_PIN(158, "SRCCLKREQB_7"),
PINCTRL_PIN(159, "SRCCLKREQB_8"),
PINCTRL_PIN(160, "SRCCLKREQB_9"),
PINCTRL_PIN(161, "SRCCLKREQB_10"),
PINCTRL_PIN(162, "SRCCLKREQB_11"),
PINCTRL_PIN(163, "SRCCLKREQB_12"),
PINCTRL_PIN(164, "SRCCLKREQB_13"),
PINCTRL_PIN(165, "SRCCLKREQB_14"),
PINCTRL_PIN(166, "SRCCLKREQB_15"),
PINCTRL_PIN(167, "SML2CLK"),
PINCTRL_PIN(168, "SML2DATA"),
PINCTRL_PIN(169, "SML2ALERTB"),
PINCTRL_PIN(170, "SML3CLK"),
PINCTRL_PIN(171, "SML3DATA"),
PINCTRL_PIN(172, "SML3ALERTB"),
PINCTRL_PIN(173, "SML4CLK"),
PINCTRL_PIN(174, "SML4DATA"),
PINCTRL_PIN(175, "SML4ALERTB"),
PINCTRL_PIN(176, "ISH_I2C0_SDA"),
PINCTRL_PIN(177, "ISH_I2C0_SCL"),
PINCTRL_PIN(178, "ISH_I2C1_SDA"),
PINCTRL_PIN(179, "ISH_I2C1_SCL"),
PINCTRL_PIN(180, "GPP_H_23"),
/* GPP_I */
PINCTRL_PIN(181, "DDSP_HDP_0"),
PINCTRL_PIN(182, "DDSP_HDP_1"),
PINCTRL_PIN(183, "DDSP_HDP_2"),
PINCTRL_PIN(184, "DDSP_HDP_3"),
PINCTRL_PIN(185, "EDP_HPD"),
PINCTRL_PIN(186, "DDPB_CTRLCLK"),
PINCTRL_PIN(187, "DDPB_CTRLDATA"),
PINCTRL_PIN(188, "DDPC_CTRLCLK"),
PINCTRL_PIN(189, "DDPC_CTRLDATA"),
PINCTRL_PIN(190, "DDPD_CTRLCLK"),
PINCTRL_PIN(191, "DDPD_CTRLDATA"),
};
static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
static const unsigned spth_i2c0_pins[] = { 64, 65 };
static const unsigned spth_i2c1_pins[] = { 66, 67 };
static const unsigned spth_i2c2_pins[] = { 76, 95 };
static const struct intel_pingroup spth_groups[] = {
PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
};
static const char * const spth_spi0_groups[] = { "spi0_grp" };
static const char * const spth_spi1_groups[] = { "spi0_grp" };
static const char * const spth_uart0_groups[] = { "uart0_grp" };
static const char * const spth_uart1_groups[] = { "uart1_grp" };
static const char * const spth_uart2_groups[] = { "uart2_grp" };
static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
static const struct intel_function spth_functions[] = {
FUNCTION("spi0", spth_spi0_groups),
FUNCTION("spi1", spth_spi1_groups),
FUNCTION("uart0", spth_uart0_groups),
FUNCTION("uart1", spth_uart1_groups),
FUNCTION("uart2", spth_uart2_groups),
FUNCTION("i2c0", spth_i2c0_groups),
FUNCTION("i2c1", spth_i2c1_groups),
FUNCTION("i2c2", spth_i2c2_groups),
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {
SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
};
static const struct intel_pinctrl_soc_data spth_soc_data = {
.pins = spth_pins,
.npins = ARRAY_SIZE(spth_pins),
.groups = spth_groups,
.ngroups = ARRAY_SIZE(spth_groups),
.functions = spth_functions,
.nfunctions = ARRAY_SIZE(spth_functions),
.communities = spth_communities,
.ncommunities = ARRAY_SIZE(spth_communities),
};
static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
{ "INT344B", (kernel_ulong_t)&sptlp_soc_data },
{ "INT3451", (kernel_ulong_t)&spth_soc_data },
{ "INT345D", (kernel_ulong_t)&spth_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
static struct platform_driver spt_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "sunrisepoint-pinctrl",
.acpi_match_table = spt_pinctrl_acpi_match,
.pm = &spt_pinctrl_pm_ops,
},
};
static int __init spt_pinctrl_init(void)
{
return platform_driver_register(&spt_pinctrl_driver);
}
subsys_initcall(spt_pinctrl_init);
static void __exit spt_pinctrl_exit(void)
{
platform_driver_unregister(&spt_pinctrl_driver);
}
module_exit(spt_pinctrl_exit);
MODULE_AUTHOR("Mathias Nyman <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Tiger Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2019 - 2020, Intel Corporation
* Authors: Andy Shevchenko <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define TGL_LP_PAD_OWN 0x020
#define TGL_LP_PADCFGLOCK 0x080
#define TGL_LP_HOSTSW_OWN 0x0b0
#define TGL_LP_GPI_IS 0x100
#define TGL_LP_GPI_IE 0x120
#define TGL_H_PAD_OWN 0x020
#define TGL_H_PADCFGLOCK 0x090
#define TGL_H_HOSTSW_OWN 0x0c0
#define TGL_H_GPI_IS 0x100
#define TGL_H_GPI_IE 0x120
#define TGL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)
#define TGL_H_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H)
/* Tiger Lake-LP */
static const struct pinctrl_pin_desc tgllp_pins[] = {
/* GPP_B */
PINCTRL_PIN(0, "CORE_VID_0"),
PINCTRL_PIN(1, "CORE_VID_1"),
PINCTRL_PIN(2, "VRALERTB"),
PINCTRL_PIN(3, "CPU_GP_2"),
PINCTRL_PIN(4, "CPU_GP_3"),
PINCTRL_PIN(5, "ISH_I2C0_SDA"),
PINCTRL_PIN(6, "ISH_I2C0_SCL"),
PINCTRL_PIN(7, "ISH_I2C1_SDA"),
PINCTRL_PIN(8, "ISH_I2C1_SCL"),
PINCTRL_PIN(9, "I2C5_SDA"),
PINCTRL_PIN(10, "I2C5_SCL"),
PINCTRL_PIN(11, "PMCALERTB"),
PINCTRL_PIN(12, "SLP_S0B"),
PINCTRL_PIN(13, "PLTRSTB"),
PINCTRL_PIN(14, "SPKR"),
PINCTRL_PIN(15, "GSPI0_CS0B"),
PINCTRL_PIN(16, "GSPI0_CLK"),
PINCTRL_PIN(17, "GSPI0_MISO"),
PINCTRL_PIN(18, "GSPI0_MOSI"),
PINCTRL_PIN(19, "GSPI1_CS0B"),
PINCTRL_PIN(20, "GSPI1_CLK"),
PINCTRL_PIN(21, "GSPI1_MISO"),
PINCTRL_PIN(22, "GSPI1_MOSI"),
PINCTRL_PIN(23, "SML1ALERTB"),
PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
/* GPP_T */
PINCTRL_PIN(26, "I2C6_SDA"),
PINCTRL_PIN(27, "I2C6_SCL"),
PINCTRL_PIN(28, "I2C7_SDA"),
PINCTRL_PIN(29, "I2C7_SCL"),
PINCTRL_PIN(30, "UART4_RXD"),
PINCTRL_PIN(31, "UART4_TXD"),
PINCTRL_PIN(32, "UART4_RTSB"),
PINCTRL_PIN(33, "UART4_CTSB"),
PINCTRL_PIN(34, "UART5_RXD"),
PINCTRL_PIN(35, "UART5_TXD"),
PINCTRL_PIN(36, "UART5_RTSB"),
PINCTRL_PIN(37, "UART5_CTSB"),
PINCTRL_PIN(38, "UART6_RXD"),
PINCTRL_PIN(39, "UART6_TXD"),
PINCTRL_PIN(40, "UART6_RTSB"),
PINCTRL_PIN(41, "UART6_CTSB"),
/* GPP_A */
PINCTRL_PIN(42, "ESPI_IO_0"),
PINCTRL_PIN(43, "ESPI_IO_1"),
PINCTRL_PIN(44, "ESPI_IO_2"),
PINCTRL_PIN(45, "ESPI_IO_3"),
PINCTRL_PIN(46, "ESPI_CSB"),
PINCTRL_PIN(47, "ESPI_CLK"),
PINCTRL_PIN(48, "ESPI_RESETB"),
PINCTRL_PIN(49, "I2S2_SCLK"),
PINCTRL_PIN(50, "I2S2_SFRM"),
PINCTRL_PIN(51, "I2S2_TXD"),
PINCTRL_PIN(52, "I2S2_RXD"),
PINCTRL_PIN(53, "PMC_I2C_SDA"),
PINCTRL_PIN(54, "SATAXPCIE_1"),
PINCTRL_PIN(55, "PMC_I2C_SCL"),
PINCTRL_PIN(56, "USB2_OCB_1"),
PINCTRL_PIN(57, "USB2_OCB_2"),
PINCTRL_PIN(58, "USB2_OCB_3"),
PINCTRL_PIN(59, "DDSP_HPD_C"),
PINCTRL_PIN(60, "DDSP_HPD_B"),
PINCTRL_PIN(61, "DDSP_HPD_1"),
PINCTRL_PIN(62, "DDSP_HPD_2"),
PINCTRL_PIN(63, "GPPC_A_21"),
PINCTRL_PIN(64, "GPPC_A_22"),
PINCTRL_PIN(65, "I2S1_SCLK"),
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
/* GPP_S */
PINCTRL_PIN(67, "SNDW0_CLK"),
PINCTRL_PIN(68, "SNDW0_DATA"),
PINCTRL_PIN(69, "SNDW1_CLK"),
PINCTRL_PIN(70, "SNDW1_DATA"),
PINCTRL_PIN(71, "SNDW2_CLK"),
PINCTRL_PIN(72, "SNDW2_DATA"),
PINCTRL_PIN(73, "SNDW3_CLK"),
PINCTRL_PIN(74, "SNDW3_DATA"),
/* GPP_H */
PINCTRL_PIN(75, "GPPC_H_0"),
PINCTRL_PIN(76, "GPPC_H_1"),
PINCTRL_PIN(77, "GPPC_H_2"),
PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(79, "I2C2_SDA"),
PINCTRL_PIN(80, "I2C2_SCL"),
PINCTRL_PIN(81, "I2C3_SDA"),
PINCTRL_PIN(82, "I2C3_SCL"),
PINCTRL_PIN(83, "I2C4_SDA"),
PINCTRL_PIN(84, "I2C4_SCL"),
PINCTRL_PIN(85, "SRCCLKREQB_4"),
PINCTRL_PIN(86, "SRCCLKREQB_5"),
PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
PINCTRL_PIN(91, "DDPB_CTRLCLK"),
PINCTRL_PIN(92, "DDPB_CTRLDATA"),
PINCTRL_PIN(93, "CPU_C10_GATEB"),
PINCTRL_PIN(94, "TIME_SYNC_0"),
PINCTRL_PIN(95, "IMGCLKOUT_1"),
PINCTRL_PIN(96, "IMGCLKOUT_2"),
PINCTRL_PIN(97, "IMGCLKOUT_3"),
PINCTRL_PIN(98, "IMGCLKOUT_4"),
/* GPP_D */
PINCTRL_PIN(99, "ISH_GP_0"),
PINCTRL_PIN(100, "ISH_GP_1"),
PINCTRL_PIN(101, "ISH_GP_2"),
PINCTRL_PIN(102, "ISH_GP_3"),
PINCTRL_PIN(103, "IMGCLKOUT_0"),
PINCTRL_PIN(104, "SRCCLKREQB_0"),
PINCTRL_PIN(105, "SRCCLKREQB_1"),
PINCTRL_PIN(106, "SRCCLKREQB_2"),
PINCTRL_PIN(107, "SRCCLKREQB_3"),
PINCTRL_PIN(108, "ISH_SPI_CSB"),
PINCTRL_PIN(109, "ISH_SPI_CLK"),
PINCTRL_PIN(110, "ISH_SPI_MISO"),
PINCTRL_PIN(111, "ISH_SPI_MOSI"),
PINCTRL_PIN(112, "ISH_UART0_RXD"),
PINCTRL_PIN(113, "ISH_UART0_TXD"),
PINCTRL_PIN(114, "ISH_UART0_RTSB"),
PINCTRL_PIN(115, "ISH_UART0_CTSB"),
PINCTRL_PIN(116, "ISH_GP_4"),
PINCTRL_PIN(117, "ISH_GP_5"),
PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
/* GPP_U */
PINCTRL_PIN(120, "UART3_RXD"),
PINCTRL_PIN(121, "UART3_TXD"),
PINCTRL_PIN(122, "UART3_RTSB"),
PINCTRL_PIN(123, "UART3_CTSB"),
PINCTRL_PIN(124, "GSPI3_CS0B"),
PINCTRL_PIN(125, "GSPI3_CLK"),
PINCTRL_PIN(126, "GSPI3_MISO"),
PINCTRL_PIN(127, "GSPI3_MOSI"),
PINCTRL_PIN(128, "GSPI4_CS0B"),
PINCTRL_PIN(129, "GSPI4_CLK"),
PINCTRL_PIN(130, "GSPI4_MISO"),
PINCTRL_PIN(131, "GSPI4_MOSI"),
PINCTRL_PIN(132, "GSPI5_CS0B"),
PINCTRL_PIN(133, "GSPI5_CLK"),
PINCTRL_PIN(134, "GSPI5_MISO"),
PINCTRL_PIN(135, "GSPI5_MOSI"),
PINCTRL_PIN(136, "GSPI6_CS0B"),
PINCTRL_PIN(137, "GSPI6_CLK"),
PINCTRL_PIN(138, "GSPI6_MISO"),
PINCTRL_PIN(139, "GSPI6_MOSI"),
PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
/* vGPIO */
PINCTRL_PIN(144, "CNV_BTEN"),
PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(155, "vUART0_TXD"),
PINCTRL_PIN(156, "vUART0_RXD"),
PINCTRL_PIN(157, "vUART0_CTS_B"),
PINCTRL_PIN(158, "vUART0_RTS_B"),
PINCTRL_PIN(159, "vISH_UART0_TXD"),
PINCTRL_PIN(160, "vISH_UART0_RXD"),
PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(167, "vI2S2_SCLK"),
PINCTRL_PIN(168, "vI2S2_SFRM"),
PINCTRL_PIN(169, "vI2S2_TXD"),
PINCTRL_PIN(170, "vI2S2_RXD"),
/* GPP_C */
PINCTRL_PIN(171, "SMBCLK"),
PINCTRL_PIN(172, "SMBDATA"),
PINCTRL_PIN(173, "SMBALERTB"),
PINCTRL_PIN(174, "SML0CLK"),
PINCTRL_PIN(175, "SML0DATA"),
PINCTRL_PIN(176, "SML0ALERTB"),
PINCTRL_PIN(177, "SML1CLK"),
PINCTRL_PIN(178, "SML1DATA"),
PINCTRL_PIN(179, "UART0_RXD"),
PINCTRL_PIN(180, "UART0_TXD"),
PINCTRL_PIN(181, "UART0_RTSB"),
PINCTRL_PIN(182, "UART0_CTSB"),
PINCTRL_PIN(183, "UART1_RXD"),
PINCTRL_PIN(184, "UART1_TXD"),
PINCTRL_PIN(185, "UART1_RTSB"),
PINCTRL_PIN(186, "UART1_CTSB"),
PINCTRL_PIN(187, "I2C0_SDA"),
PINCTRL_PIN(188, "I2C0_SCL"),
PINCTRL_PIN(189, "I2C1_SDA"),
PINCTRL_PIN(190, "I2C1_SCL"),
PINCTRL_PIN(191, "UART2_RXD"),
PINCTRL_PIN(192, "UART2_TXD"),
PINCTRL_PIN(193, "UART2_RTSB"),
PINCTRL_PIN(194, "UART2_CTSB"),
/* GPP_F */
PINCTRL_PIN(195, "CNV_BRI_DT"),
PINCTRL_PIN(196, "CNV_BRI_RSP"),
PINCTRL_PIN(197, "CNV_RGI_DT"),
PINCTRL_PIN(198, "CNV_RGI_RSP"),
PINCTRL_PIN(199, "CNV_RF_RESET_B"),
PINCTRL_PIN(200, "GPPC_F_5"),
PINCTRL_PIN(201, "CNV_PA_BLANKING"),
PINCTRL_PIN(202, "GPPC_F_7"),
PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
PINCTRL_PIN(204, "BOOTMPC"),
PINCTRL_PIN(205, "GPPC_F_10"),
PINCTRL_PIN(206, "GPPC_F_11"),
PINCTRL_PIN(207, "GSXDOUT"),
PINCTRL_PIN(208, "GSXSLOAD"),
PINCTRL_PIN(209, "GSXDIN"),
PINCTRL_PIN(210, "GSXSRESETB"),
PINCTRL_PIN(211, "GSXCLK"),
PINCTRL_PIN(212, "GMII_MDC"),
PINCTRL_PIN(213, "GMII_MDIO"),
PINCTRL_PIN(214, "SRCCLKREQB_6"),
PINCTRL_PIN(215, "EXT_PWR_GATEB"),
PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
PINCTRL_PIN(217, "VNN_CTRL"),
PINCTRL_PIN(218, "V1P05_CTRL"),
PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
/* HVCMOS */
PINCTRL_PIN(220, "L_BKLTEN"),
PINCTRL_PIN(221, "L_BKLTCTL"),
PINCTRL_PIN(222, "L_VDDEN"),
PINCTRL_PIN(223, "SYS_PWROK"),
PINCTRL_PIN(224, "SYS_RESETB"),
PINCTRL_PIN(225, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(226, "SATAXPCIE_0"),
PINCTRL_PIN(227, "SPI1_IO_2"),
PINCTRL_PIN(228, "SPI1_IO_3"),
PINCTRL_PIN(229, "CPU_GP_0"),
PINCTRL_PIN(230, "SATA_DEVSLP_0"),
PINCTRL_PIN(231, "SATA_DEVSLP_1"),
PINCTRL_PIN(232, "GPPC_E_6"),
PINCTRL_PIN(233, "CPU_GP_1"),
PINCTRL_PIN(234, "SPI1_CS1B"),
PINCTRL_PIN(235, "USB2_OCB_0"),
PINCTRL_PIN(236, "SPI1_CSB"),
PINCTRL_PIN(237, "SPI1_CLK"),
PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(240, "DDSP_HPD_A"),
PINCTRL_PIN(241, "ISH_GP_6"),
PINCTRL_PIN(242, "ISH_GP_7"),
PINCTRL_PIN(243, "GPPC_E_17"),
PINCTRL_PIN(244, "DDP1_CTRLCLK"),
PINCTRL_PIN(245, "DDP1_CTRLDATA"),
PINCTRL_PIN(246, "DDP2_CTRLCLK"),
PINCTRL_PIN(247, "DDP2_CTRLDATA"),
PINCTRL_PIN(248, "DDPA_CTRLCLK"),
PINCTRL_PIN(249, "DDPA_CTRLDATA"),
PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
/* JTAG */
PINCTRL_PIN(251, "JTAG_TDO"),
PINCTRL_PIN(252, "JTAGX"),
PINCTRL_PIN(253, "PRDYB"),
PINCTRL_PIN(254, "PREQB"),
PINCTRL_PIN(255, "CPU_TRSTB"),
PINCTRL_PIN(256, "JTAG_TDI"),
PINCTRL_PIN(257, "JTAG_TMS"),
PINCTRL_PIN(258, "JTAG_TCK"),
PINCTRL_PIN(259, "DBG_PMODE"),
/* GPP_R */
PINCTRL_PIN(260, "HDA_BCLK"),
PINCTRL_PIN(261, "HDA_SYNC"),
PINCTRL_PIN(262, "HDA_SDO"),
PINCTRL_PIN(263, "HDA_SDI_0"),
PINCTRL_PIN(264, "HDA_RSTB"),
PINCTRL_PIN(265, "HDA_SDI_1"),
PINCTRL_PIN(266, "GPP_R_6"),
PINCTRL_PIN(267, "GPP_R_7"),
/* SPI */
PINCTRL_PIN(268, "SPI0_IO_2"),
PINCTRL_PIN(269, "SPI0_IO_3"),
PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
PINCTRL_PIN(272, "SPI0_TPM_CSB"),
PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(275, "SPI0_CLK"),
PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
};
static const struct intel_padgroup tgllp_community0_gpps[] = {
TGL_GPP(0, 0, 25, 0), /* GPP_B */
TGL_GPP(1, 26, 41, 32), /* GPP_T */
TGL_GPP(2, 42, 66, 64), /* GPP_A */
};
static const struct intel_padgroup tgllp_community1_gpps[] = {
TGL_GPP(0, 67, 74, 96), /* GPP_S */
TGL_GPP(1, 75, 98, 128), /* GPP_H */
TGL_GPP(2, 99, 119, 160), /* GPP_D */
TGL_GPP(3, 120, 143, 192), /* GPP_U */
TGL_GPP(4, 144, 170, 224), /* vGPIO */
};
static const struct intel_padgroup tgllp_community4_gpps[] = {
TGL_GPP(0, 171, 194, 256), /* GPP_C */
TGL_GPP(1, 195, 219, 288), /* GPP_F */
TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
TGL_GPP(3, 226, 250, 320), /* GPP_E */
TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup tgllp_community5_gpps[] = {
TGL_GPP(0, 260, 267, 352), /* GPP_R */
TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community tgllp_communities[] = {
TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
};
static const struct intel_pinctrl_soc_data tgllp_soc_data = {
.pins = tgllp_pins,
.npins = ARRAY_SIZE(tgllp_pins),
.communities = tgllp_communities,
.ncommunities = ARRAY_SIZE(tgllp_communities),
};
/* Tiger Lake-H */
static const struct pinctrl_pin_desc tglh_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "SPI0_IO_2"),
PINCTRL_PIN(1, "SPI0_IO_3"),
PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
PINCTRL_PIN(4, "SPI0_TPM_CSB"),
PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(7, "SPI0_CLK"),
PINCTRL_PIN(8, "ESPI_IO_0"),
PINCTRL_PIN(9, "ESPI_IO_1"),
PINCTRL_PIN(10, "ESPI_IO_2"),
PINCTRL_PIN(11, "ESPI_IO_3"),
PINCTRL_PIN(12, "ESPI_CS0B"),
PINCTRL_PIN(13, "ESPI_CLK"),
PINCTRL_PIN(14, "ESPI_RESETB"),
PINCTRL_PIN(15, "ESPI_CS1B"),
PINCTRL_PIN(16, "ESPI_CS2B"),
PINCTRL_PIN(17, "ESPI_CS3B"),
PINCTRL_PIN(18, "ESPI_ALERT0B"),
PINCTRL_PIN(19, "ESPI_ALERT1B"),
PINCTRL_PIN(20, "ESPI_ALERT2B"),
PINCTRL_PIN(21, "ESPI_ALERT3B"),
PINCTRL_PIN(22, "GPPC_A_14"),
PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
/* GPP_R */
PINCTRL_PIN(25, "HDA_BCLK"),
PINCTRL_PIN(26, "HDA_SYNC"),
PINCTRL_PIN(27, "HDA_SDO"),
PINCTRL_PIN(28, "HDA_SDI_0"),
PINCTRL_PIN(29, "HDA_RSTB"),
PINCTRL_PIN(30, "HDA_SDI_1"),
PINCTRL_PIN(31, "GPP_R_6"),
PINCTRL_PIN(32, "GPP_R_7"),
PINCTRL_PIN(33, "GPP_R_8"),
PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
PINCTRL_PIN(35, "ISH_UART0_RTSB"),
PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(37, "CLKOUT_48"),
PINCTRL_PIN(38, "ISH_GP_7"),
PINCTRL_PIN(39, "ISH_GP_0"),
PINCTRL_PIN(40, "ISH_GP_1"),
PINCTRL_PIN(41, "ISH_GP_2"),
PINCTRL_PIN(42, "ISH_GP_3"),
PINCTRL_PIN(43, "ISH_GP_4"),
PINCTRL_PIN(44, "ISH_GP_5"),
/* GPP_B */
PINCTRL_PIN(45, "GSPI0_CS1B"),
PINCTRL_PIN(46, "GSPI1_CS1B"),
PINCTRL_PIN(47, "VRALERTB"),
PINCTRL_PIN(48, "CPU_GP_2"),
PINCTRL_PIN(49, "CPU_GP_3"),
PINCTRL_PIN(50, "SRCCLKREQB_0"),
PINCTRL_PIN(51, "SRCCLKREQB_1"),
PINCTRL_PIN(52, "SRCCLKREQB_2"),
PINCTRL_PIN(53, "SRCCLKREQB_3"),
PINCTRL_PIN(54, "SRCCLKREQB_4"),
PINCTRL_PIN(55, "SRCCLKREQB_5"),
PINCTRL_PIN(56, "I2S_MCLK"),
PINCTRL_PIN(57, "SLP_S0B"),
PINCTRL_PIN(58, "PLTRSTB"),
PINCTRL_PIN(59, "SPKR"),
PINCTRL_PIN(60, "GSPI0_CS0B"),
PINCTRL_PIN(61, "GSPI0_CLK"),
PINCTRL_PIN(62, "GSPI0_MISO"),
PINCTRL_PIN(63, "GSPI0_MOSI"),
PINCTRL_PIN(64, "GSPI1_CS0B"),
PINCTRL_PIN(65, "GSPI1_CLK"),
PINCTRL_PIN(66, "GSPI1_MISO"),
PINCTRL_PIN(67, "GSPI1_MOSI"),
PINCTRL_PIN(68, "SML1ALERTB"),
PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
/* vGPIO_0 */
PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
PINCTRL_PIN(75, "USB_CPU_OCB_0"),
PINCTRL_PIN(76, "USB_CPU_OCB_1"),
PINCTRL_PIN(77, "USB_CPU_OCB_2"),
PINCTRL_PIN(78, "USB_CPU_OCB_3"),
/* GPP_D */
PINCTRL_PIN(79, "SPI1_CSB"),
PINCTRL_PIN(80, "SPI1_CLK"),
PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(83, "SML1CLK"),
PINCTRL_PIN(84, "I2S2_SFRM"),
PINCTRL_PIN(85, "I2S2_TXD"),
PINCTRL_PIN(86, "I2S2_RXD"),
PINCTRL_PIN(87, "I2S2_SCLK"),
PINCTRL_PIN(88, "SML0CLK"),
PINCTRL_PIN(89, "SML0DATA"),
PINCTRL_PIN(90, "GPP_D_11"),
PINCTRL_PIN(91, "ISH_UART0_CTSB"),
PINCTRL_PIN(92, "SPI1_IO_2"),
PINCTRL_PIN(93, "SPI1_IO_3"),
PINCTRL_PIN(94, "SML1DATA"),
PINCTRL_PIN(95, "GSPI3_CS0B"),
PINCTRL_PIN(96, "GSPI3_CLK"),
PINCTRL_PIN(97, "GSPI3_MISO"),
PINCTRL_PIN(98, "GSPI3_MOSI"),
PINCTRL_PIN(99, "UART3_RXD"),
PINCTRL_PIN(100, "UART3_TXD"),
PINCTRL_PIN(101, "UART3_RTSB"),
PINCTRL_PIN(102, "UART3_CTSB"),
PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
/* GPP_C */
PINCTRL_PIN(105, "SMBCLK"),
PINCTRL_PIN(106, "SMBDATA"),
PINCTRL_PIN(107, "SMBALERTB"),
PINCTRL_PIN(108, "ISH_UART0_RXD"),
PINCTRL_PIN(109, "ISH_UART0_TXD"),
PINCTRL_PIN(110, "SML0ALERTB"),
PINCTRL_PIN(111, "ISH_I2C2_SDA"),
PINCTRL_PIN(112, "ISH_I2C2_SCL"),
PINCTRL_PIN(113, "UART0_RXD"),
PINCTRL_PIN(114, "UART0_TXD"),
PINCTRL_PIN(115, "UART0_RTSB"),
PINCTRL_PIN(116, "UART0_CTSB"),
PINCTRL_PIN(117, "UART1_RXD"),
PINCTRL_PIN(118, "UART1_TXD"),
PINCTRL_PIN(119, "UART1_RTSB"),
PINCTRL_PIN(120, "UART1_CTSB"),
PINCTRL_PIN(121, "I2C0_SDA"),
PINCTRL_PIN(122, "I2C0_SCL"),
PINCTRL_PIN(123, "I2C1_SDA"),
PINCTRL_PIN(124, "I2C1_SCL"),
PINCTRL_PIN(125, "UART2_RXD"),
PINCTRL_PIN(126, "UART2_TXD"),
PINCTRL_PIN(127, "UART2_RTSB"),
PINCTRL_PIN(128, "UART2_CTSB"),
/* GPP_S */
PINCTRL_PIN(129, "SNDW1_CLK"),
PINCTRL_PIN(130, "SNDW1_DATA"),
PINCTRL_PIN(131, "SNDW2_CLK"),
PINCTRL_PIN(132, "SNDW2_DATA"),
PINCTRL_PIN(133, "SNDW3_CLK"),
PINCTRL_PIN(134, "SNDW3_DATA"),
PINCTRL_PIN(135, "SNDW4_CLK"),
PINCTRL_PIN(136, "SNDW4_DATA"),
/* GPP_G */
PINCTRL_PIN(137, "DDPA_CTRLCLK"),
PINCTRL_PIN(138, "DDPA_CTRLDATA"),
PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
PINCTRL_PIN(140, "GMII_MDC_0"),
PINCTRL_PIN(141, "GMII_MDIO_0"),
PINCTRL_PIN(142, "SLP_DRAMB"),
PINCTRL_PIN(143, "GPPC_G_6"),
PINCTRL_PIN(144, "GPPC_G_7"),
PINCTRL_PIN(145, "ISH_SPI_CSB"),
PINCTRL_PIN(146, "ISH_SPI_CLK"),
PINCTRL_PIN(147, "ISH_SPI_MISO"),
PINCTRL_PIN(148, "ISH_SPI_MOSI"),
PINCTRL_PIN(149, "DDP1_CTRLCLK"),
PINCTRL_PIN(150, "DDP1_CTRLDATA"),
PINCTRL_PIN(151, "DDP2_CTRLCLK"),
PINCTRL_PIN(152, "DDP2_CTRLDATA"),
PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
/* vGPIO */
PINCTRL_PIN(154, "CNV_BTEN"),
PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(165, "vUART0_TXD"),
PINCTRL_PIN(166, "vUART0_RXD"),
PINCTRL_PIN(167, "vUART0_CTS_B"),
PINCTRL_PIN(168, "vUART0_RTS_B"),
PINCTRL_PIN(169, "vISH_UART0_TXD"),
PINCTRL_PIN(170, "vISH_UART0_RXD"),
PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(177, "vI2S2_SCLK"),
PINCTRL_PIN(178, "vI2S2_SFRM"),
PINCTRL_PIN(179, "vI2S2_TXD"),
PINCTRL_PIN(180, "vI2S2_RXD"),
/* GPP_E */
PINCTRL_PIN(181, "SATAXPCIE_0"),
PINCTRL_PIN(182, "SATAXPCIE_1"),
PINCTRL_PIN(183, "SATAXPCIE_2"),
PINCTRL_PIN(184, "CPU_GP_0"),
PINCTRL_PIN(185, "SATA_DEVSLP_0"),
PINCTRL_PIN(186, "SATA_DEVSLP_1"),
PINCTRL_PIN(187, "SATA_DEVSLP_2"),
PINCTRL_PIN(188, "CPU_GP_1"),
PINCTRL_PIN(189, "SATA_LEDB"),
PINCTRL_PIN(190, "USB2_OCB_0"),
PINCTRL_PIN(191, "USB2_OCB_1"),
PINCTRL_PIN(192, "USB2_OCB_2"),
PINCTRL_PIN(193, "USB2_OCB_3"),
/* GPP_F */
PINCTRL_PIN(194, "SATAXPCIE_3"),
PINCTRL_PIN(195, "SATAXPCIE_4"),
PINCTRL_PIN(196, "SATAXPCIE_5"),
PINCTRL_PIN(197, "SATAXPCIE_6"),
PINCTRL_PIN(198, "SATAXPCIE_7"),
PINCTRL_PIN(199, "SATA_DEVSLP_3"),
PINCTRL_PIN(200, "SATA_DEVSLP_4"),
PINCTRL_PIN(201, "SATA_DEVSLP_5"),
PINCTRL_PIN(202, "SATA_DEVSLP_6"),
PINCTRL_PIN(203, "SATA_DEVSLP_7"),
PINCTRL_PIN(204, "SATA_SCLOCK"),
PINCTRL_PIN(205, "SATA_SLOAD"),
PINCTRL_PIN(206, "SATA_SDATAOUT1"),
PINCTRL_PIN(207, "SATA_SDATAOUT0"),
PINCTRL_PIN(208, "PS_ONB"),
PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
PINCTRL_PIN(213, "L_VDDEN"),
PINCTRL_PIN(214, "L_BKLTEN"),
PINCTRL_PIN(215, "L_BKLTCTL"),
PINCTRL_PIN(216, "VNN_CTRL"),
PINCTRL_PIN(217, "GPP_F_23"),
/* GPP_H */
PINCTRL_PIN(218, "SRCCLKREQB_6"),
PINCTRL_PIN(219, "SRCCLKREQB_7"),
PINCTRL_PIN(220, "SRCCLKREQB_8"),
PINCTRL_PIN(221, "SRCCLKREQB_9"),
PINCTRL_PIN(222, "SRCCLKREQB_10"),
PINCTRL_PIN(223, "SRCCLKREQB_11"),
PINCTRL_PIN(224, "SRCCLKREQB_12"),
PINCTRL_PIN(225, "SRCCLKREQB_13"),
PINCTRL_PIN(226, "SRCCLKREQB_14"),
PINCTRL_PIN(227, "SRCCLKREQB_15"),
PINCTRL_PIN(228, "SML2CLK"),
PINCTRL_PIN(229, "SML2DATA"),
PINCTRL_PIN(230, "SML2ALERTB"),
PINCTRL_PIN(231, "SML3CLK"),
PINCTRL_PIN(232, "SML3DATA"),
PINCTRL_PIN(233, "SML3ALERTB"),
PINCTRL_PIN(234, "SML4CLK"),
PINCTRL_PIN(235, "SML4DATA"),
PINCTRL_PIN(236, "SML4ALERTB"),
PINCTRL_PIN(237, "ISH_I2C0_SDA"),
PINCTRL_PIN(238, "ISH_I2C0_SCL"),
PINCTRL_PIN(239, "ISH_I2C1_SDA"),
PINCTRL_PIN(240, "ISH_I2C1_SCL"),
PINCTRL_PIN(241, "TIME_SYNC_0"),
/* GPP_J */
PINCTRL_PIN(242, "CNV_PA_BLANKING"),
PINCTRL_PIN(243, "CPU_C10_GATEB"),
PINCTRL_PIN(244, "CNV_BRI_DT"),
PINCTRL_PIN(245, "CNV_BRI_RSP"),
PINCTRL_PIN(246, "CNV_RGI_DT"),
PINCTRL_PIN(247, "CNV_RGI_RSP"),
PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
PINCTRL_PIN(250, "GPP_J_8"),
PINCTRL_PIN(251, "GPP_J_9"),
/* GPP_K */
PINCTRL_PIN(252, "GSXDOUT"),
PINCTRL_PIN(253, "GSXSLOAD"),
PINCTRL_PIN(254, "GSXDIN"),
PINCTRL_PIN(255, "GSXSRESETB"),
PINCTRL_PIN(256, "GSXCLK"),
PINCTRL_PIN(257, "ADR_COMPLETE"),
PINCTRL_PIN(258, "DDSP_HPD_A"),
PINCTRL_PIN(259, "DDSP_HPD_B"),
PINCTRL_PIN(260, "CORE_VID_0"),
PINCTRL_PIN(261, "CORE_VID_1"),
PINCTRL_PIN(262, "DDSP_HPD_C"),
PINCTRL_PIN(263, "GPP_K_11"),
PINCTRL_PIN(264, "SYS_PWROK"),
PINCTRL_PIN(265, "SYS_RESETB"),
PINCTRL_PIN(266, "MLK_RSTB"),
/* GPP_I */
PINCTRL_PIN(267, "PMCALERTB"),
PINCTRL_PIN(268, "DDSP_HPD_1"),
PINCTRL_PIN(269, "DDSP_HPD_2"),
PINCTRL_PIN(270, "DDSP_HPD_3"),
PINCTRL_PIN(271, "DDSP_HPD_4"),
PINCTRL_PIN(272, "DDPB_CTRLCLK"),
PINCTRL_PIN(273, "DDPB_CTRLDATA"),
PINCTRL_PIN(274, "DDPC_CTRLCLK"),
PINCTRL_PIN(275, "DDPC_CTRLDATA"),
PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(278, "USB2_OCB_4"),
PINCTRL_PIN(279, "USB2_OCB_5"),
PINCTRL_PIN(280, "USB2_OCB_6"),
PINCTRL_PIN(281, "USB2_OCB_7"),
/* JTAG */
PINCTRL_PIN(282, "JTAG_TDO"),
PINCTRL_PIN(283, "JTAGX"),
PINCTRL_PIN(284, "PRDYB"),
PINCTRL_PIN(285, "PREQB"),
PINCTRL_PIN(286, "JTAG_TDI"),
PINCTRL_PIN(287, "JTAG_TMS"),
PINCTRL_PIN(288, "JTAG_TCK"),
PINCTRL_PIN(289, "DBG_PMODE"),
PINCTRL_PIN(290, "CPU_TRSTB"),
};
static const struct intel_padgroup tglh_community0_gpps[] = {
TGL_GPP(0, 0, 24, 0), /* GPP_A */
TGL_GPP(1, 25, 44, 32), /* GPP_R */
TGL_GPP(2, 45, 70, 64), /* GPP_B */
TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */
};
static const struct intel_padgroup tglh_community1_gpps[] = {
TGL_GPP(0, 79, 104, 128), /* GPP_D */
TGL_GPP(1, 105, 128, 160), /* GPP_C */
TGL_GPP(2, 129, 136, 192), /* GPP_S */
TGL_GPP(3, 137, 153, 224), /* GPP_G */
TGL_GPP(4, 154, 180, 256), /* vGPIO */
};
static const struct intel_padgroup tglh_community3_gpps[] = {
TGL_GPP(0, 181, 193, 288), /* GPP_E */
TGL_GPP(1, 194, 217, 320), /* GPP_F */
};
static const struct intel_padgroup tglh_community4_gpps[] = {
TGL_GPP(0, 218, 241, 352), /* GPP_H */
TGL_GPP(1, 242, 251, 384), /* GPP_J */
TGL_GPP(2, 252, 266, 416), /* GPP_K */
};
static const struct intel_padgroup tglh_community5_gpps[] = {
TGL_GPP(0, 267, 281, 448), /* GPP_I */
TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_community tglh_communities[] = {
TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),
TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),
TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),
};
static const struct intel_pinctrl_soc_data tglh_soc_data = {
.pins = tglh_pins,
.npins = ARRAY_SIZE(tglh_pins),
.communities = tglh_communities,
.ncommunities = ARRAY_SIZE(tglh_communities),
};
static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
{ "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
{ "INT34C6", (kernel_ulong_t)&tglh_soc_data },
{ "INTC1055", (kernel_ulong_t)&tgllp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
static struct platform_driver tgl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "tigerlake-pinctrl",
.acpi_match_table = tgl_pinctrl_acpi_match,
.pm = &tgl_pinctrl_pm_ops,
},
};
module_platform_driver(tgl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-tigerlake.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Denverton SoC pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define DNV_PAD_OWN 0x020
#define DNV_PADCFGLOCK 0x090
#define DNV_HOSTSW_OWN 0x0C0
#define DNV_GPI_IS 0x100
#define DNV_GPI_IE 0x120
#define DNV_GPP(n, s, e) \
{ \
.reg_num = (n), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define DNV_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
/* Denverton */
static const struct pinctrl_pin_desc dnv_pins[] = {
/* North ALL */
PINCTRL_PIN(0, "GBE0_SDP0"),
PINCTRL_PIN(1, "GBE1_SDP0"),
PINCTRL_PIN(2, "GBE0_SDP1"),
PINCTRL_PIN(3, "GBE1_SDP1"),
PINCTRL_PIN(4, "GBE0_SDP2"),
PINCTRL_PIN(5, "GBE1_SDP2"),
PINCTRL_PIN(6, "GBE0_SDP3"),
PINCTRL_PIN(7, "GBE1_SDP3"),
PINCTRL_PIN(8, "GBE2_LED0"),
PINCTRL_PIN(9, "GBE2_LED1"),
PINCTRL_PIN(10, "GBE0_I2C_CLK"),
PINCTRL_PIN(11, "GBE0_I2C_DATA"),
PINCTRL_PIN(12, "GBE1_I2C_CLK"),
PINCTRL_PIN(13, "GBE1_I2C_DATA"),
PINCTRL_PIN(14, "NCSI_RXD0"),
PINCTRL_PIN(15, "NCSI_CLK_IN"),
PINCTRL_PIN(16, "NCSI_RXD1"),
PINCTRL_PIN(17, "NCSI_CRS_DV"),
PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
PINCTRL_PIN(19, "NCSI_TX_EN"),
PINCTRL_PIN(20, "NCSI_TXD0"),
PINCTRL_PIN(21, "NCSI_TXD1"),
PINCTRL_PIN(22, "NCSI_ARB_OUT"),
PINCTRL_PIN(23, "GBE0_LED0"),
PINCTRL_PIN(24, "GBE0_LED1"),
PINCTRL_PIN(25, "GBE1_LED0"),
PINCTRL_PIN(26, "GBE1_LED1"),
PINCTRL_PIN(27, "SPARE_0"),
PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
PINCTRL_PIN(33, "GBE_MDC"),
PINCTRL_PIN(34, "GBE_MDIO"),
PINCTRL_PIN(35, "SVID_ALERT_N"),
PINCTRL_PIN(36, "SVID_DATA"),
PINCTRL_PIN(37, "SVID_CLK"),
PINCTRL_PIN(38, "THERMTRIP_N"),
PINCTRL_PIN(39, "PROCHOT_N"),
PINCTRL_PIN(40, "MEMHOT_N"),
/* South DFX */
PINCTRL_PIN(41, "DFX_PORT_CLK0"),
PINCTRL_PIN(42, "DFX_PORT_CLK1"),
PINCTRL_PIN(43, "DFX_PORT0"),
PINCTRL_PIN(44, "DFX_PORT1"),
PINCTRL_PIN(45, "DFX_PORT2"),
PINCTRL_PIN(46, "DFX_PORT3"),
PINCTRL_PIN(47, "DFX_PORT4"),
PINCTRL_PIN(48, "DFX_PORT5"),
PINCTRL_PIN(49, "DFX_PORT6"),
PINCTRL_PIN(50, "DFX_PORT7"),
PINCTRL_PIN(51, "DFX_PORT8"),
PINCTRL_PIN(52, "DFX_PORT9"),
PINCTRL_PIN(53, "DFX_PORT10"),
PINCTRL_PIN(54, "DFX_PORT11"),
PINCTRL_PIN(55, "DFX_PORT12"),
PINCTRL_PIN(56, "DFX_PORT13"),
PINCTRL_PIN(57, "DFX_PORT14"),
PINCTRL_PIN(58, "DFX_PORT15"),
/* South GPP0 */
PINCTRL_PIN(59, "SPI_TPM_CS_N"),
PINCTRL_PIN(60, "UART2_CTS"),
PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
PINCTRL_PIN(64, "UART0_RXD"),
PINCTRL_PIN(65, "UART0_TXD"),
PINCTRL_PIN(66, "CPU_RESET_N"),
PINCTRL_PIN(67, "NMI"),
PINCTRL_PIN(68, "ERROR2_N"),
PINCTRL_PIN(69, "ERROR1_N"),
PINCTRL_PIN(70, "ERROR0_N"),
PINCTRL_PIN(71, "IERR_N"),
PINCTRL_PIN(72, "MCERR_N"),
PINCTRL_PIN(73, "SMB0_LEG_CLK"),
PINCTRL_PIN(74, "SMB0_LEG_DATA"),
PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
PINCTRL_PIN(76, "SMB1_HOST_DATA"),
PINCTRL_PIN(77, "SMB1_HOST_CLK"),
PINCTRL_PIN(78, "SMB2_PECI_DATA"),
PINCTRL_PIN(79, "SMB2_PECI_CLK"),
PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
PINCTRL_PIN(83, "USB_OC0_N"),
PINCTRL_PIN(84, "FLEX_CLK_SE0"),
PINCTRL_PIN(85, "FLEX_CLK_SE1"),
PINCTRL_PIN(86, "SPARE_4"),
PINCTRL_PIN(87, "SMB3_IE0_CLK"),
PINCTRL_PIN(88, "SMB3_IE0_DATA"),
PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
PINCTRL_PIN(90, "SATA0_LED_N"),
PINCTRL_PIN(91, "SATA1_LED_N"),
PINCTRL_PIN(92, "SATA_PDETECT0"),
PINCTRL_PIN(93, "SATA_PDETECT1"),
PINCTRL_PIN(94, "UART1_RTS"),
PINCTRL_PIN(95, "UART1_CTS"),
PINCTRL_PIN(96, "UART1_RXD"),
PINCTRL_PIN(97, "UART1_TXD"),
PINCTRL_PIN(98, "SPARE_8"),
PINCTRL_PIN(99, "SPARE_9"),
PINCTRL_PIN(100, "TCK"),
PINCTRL_PIN(101, "TRST_N"),
PINCTRL_PIN(102, "TMS"),
PINCTRL_PIN(103, "TDI"),
PINCTRL_PIN(104, "TDO"),
PINCTRL_PIN(105, "CX_PRDY_N"),
PINCTRL_PIN(106, "CX_PREQ_N"),
PINCTRL_PIN(107, "TAP1_TCK"),
PINCTRL_PIN(108, "TAP1_TRST_N"),
PINCTRL_PIN(109, "TAP1_TMS"),
PINCTRL_PIN(110, "TAP1_TDI"),
PINCTRL_PIN(111, "TAP1_TDO"),
/* South GPP1 */
PINCTRL_PIN(112, "SUSPWRDNACK"),
PINCTRL_PIN(113, "PMU_SUSCLK"),
PINCTRL_PIN(114, "ADR_TRIGGER"),
PINCTRL_PIN(115, "PMU_SLP_S45_N"),
PINCTRL_PIN(116, "PMU_SLP_S3_N"),
PINCTRL_PIN(117, "PMU_WAKE_N"),
PINCTRL_PIN(118, "PMU_PWRBTN_N"),
PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
PINCTRL_PIN(120, "PMU_PLTRST_N"),
PINCTRL_PIN(121, "SUS_STAT_N"),
PINCTRL_PIN(122, "SLP_S0IX_N"),
PINCTRL_PIN(123, "SPI_CS0_N"),
PINCTRL_PIN(124, "SPI_CS1_N"),
PINCTRL_PIN(125, "SPI_MOSI_IO0"),
PINCTRL_PIN(126, "SPI_MISO_IO1"),
PINCTRL_PIN(127, "SPI_IO2"),
PINCTRL_PIN(128, "SPI_IO3"),
PINCTRL_PIN(129, "SPI_CLK"),
PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
PINCTRL_PIN(131, "ESPI_IO0"),
PINCTRL_PIN(132, "ESPI_IO1"),
PINCTRL_PIN(133, "ESPI_IO2"),
PINCTRL_PIN(134, "ESPI_IO3"),
PINCTRL_PIN(135, "ESPI_CS0_N"),
PINCTRL_PIN(136, "ESPI_CLK"),
PINCTRL_PIN(137, "ESPI_RST_N"),
PINCTRL_PIN(138, "ESPI_ALRT0_N"),
PINCTRL_PIN(139, "ESPI_CS1_N"),
PINCTRL_PIN(140, "ESPI_ALRT1_N"),
PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
PINCTRL_PIN(142, "EMMC_CMD"),
PINCTRL_PIN(143, "EMMC_STROBE"),
PINCTRL_PIN(144, "EMMC_CLK"),
PINCTRL_PIN(145, "EMMC_D0"),
PINCTRL_PIN(146, "EMMC_D1"),
PINCTRL_PIN(147, "EMMC_D2"),
PINCTRL_PIN(148, "EMMC_D3"),
PINCTRL_PIN(149, "EMMC_D4"),
PINCTRL_PIN(150, "EMMC_D5"),
PINCTRL_PIN(151, "EMMC_D6"),
PINCTRL_PIN(152, "EMMC_D7"),
PINCTRL_PIN(153, "SPARE_3"),
};
static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
static const unsigned int dnv_emmc_pins[] = {
142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
};
static const struct intel_pingroup dnv_groups[] = {
PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
};
static const char * const dnv_uart0_groups[] = { "uart0_grp" };
static const char * const dnv_uart1_groups[] = { "uart1_grp" };
static const char * const dnv_uart2_groups[] = { "uart2_grp" };
static const char * const dnv_emmc_groups[] = { "emmc_grp" };
static const struct intel_function dnv_functions[] = {
FUNCTION("uart0", dnv_uart0_groups),
FUNCTION("uart1", dnv_uart1_groups),
FUNCTION("uart2", dnv_uart2_groups),
FUNCTION("emmc", dnv_emmc_groups),
};
static const struct intel_padgroup dnv_north_gpps[] = {
DNV_GPP(0, 0, 31), /* North ALL_0 */
DNV_GPP(1, 32, 40), /* North ALL_1 */
};
static const struct intel_padgroup dnv_south_gpps[] = {
DNV_GPP(0, 41, 58), /* South DFX */
DNV_GPP(1, 59, 90), /* South GPP0_0 */
DNV_GPP(2, 91, 111), /* South GPP0_1 */
DNV_GPP(3, 112, 143), /* South GPP1_0 */
DNV_GPP(4, 144, 153), /* South GPP1_1 */
};
static const struct intel_community dnv_communities[] = {
DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
};
static const struct intel_pinctrl_soc_data dnv_soc_data = {
.pins = dnv_pins,
.npins = ARRAY_SIZE(dnv_pins),
.groups = dnv_groups,
.ngroups = ARRAY_SIZE(dnv_groups),
.functions = dnv_functions,
.nfunctions = ARRAY_SIZE(dnv_functions),
.communities = dnv_communities,
.ncommunities = ARRAY_SIZE(dnv_communities),
};
static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
static struct platform_driver dnv_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "denverton-pinctrl",
.acpi_match_table = dnv_pinctrl_acpi_match,
.pm = &dnv_pinctrl_pm_ops,
},
};
static int __init dnv_pinctrl_init(void)
{
return platform_driver_register(&dnv_pinctrl_driver);
}
subsys_initcall(dnv_pinctrl_init);
static void __exit dnv_pinctrl_exit(void)
{
platform_driver_unregister(&dnv_pinctrl_driver);
}
module_exit(dnv_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-denverton.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Meteor Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2022, Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define MTL_P_PAD_OWN 0x0b0
#define MTL_P_PADCFGLOCK 0x110
#define MTL_P_HOSTSW_OWN 0x140
#define MTL_P_GPI_IS 0x200
#define MTL_P_GPI_IE 0x210
#define MTL_S_PAD_OWN 0x0b0
#define MTL_S_PADCFGLOCK 0x0f0
#define MTL_S_HOSTSW_OWN 0x110
#define MTL_S_GPI_IS 0x200
#define MTL_S_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define MTL_P_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
#define MTL_S_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_S)
/* Meteor Lake-P */
static const struct pinctrl_pin_desc mtlp_pins[] = {
/* CPU */
PINCTRL_PIN(0, "PECI"),
PINCTRL_PIN(1, "UFS_RESET_B"),
PINCTRL_PIN(2, "VIDSOUT"),
PINCTRL_PIN(3, "VIDSCK"),
PINCTRL_PIN(4, "VIDALERT_B"),
/* GPP_V */
PINCTRL_PIN(5, "BATLOW_B"),
PINCTRL_PIN(6, "AC_PRESENT"),
PINCTRL_PIN(7, "SOC_WAKE_B"),
PINCTRL_PIN(8, "PWRBTN_B"),
PINCTRL_PIN(9, "SLP_S3_B"),
PINCTRL_PIN(10, "SLP_S4_B"),
PINCTRL_PIN(11, "SLP_A_B"),
PINCTRL_PIN(12, "GPP_V_7"),
PINCTRL_PIN(13, "SUSCLK"),
PINCTRL_PIN(14, "SLP_WLAN_B"),
PINCTRL_PIN(15, "SLP_S5_B"),
PINCTRL_PIN(16, "LANPHYPC"),
PINCTRL_PIN(17, "SLP_LAN_B"),
PINCTRL_PIN(18, "GPP_V_13"),
PINCTRL_PIN(19, "WAKE_B"),
PINCTRL_PIN(20, "GPP_V_15"),
PINCTRL_PIN(21, "GPP_V_16"),
PINCTRL_PIN(22, "GPP_V_17"),
PINCTRL_PIN(23, "GPP_V_18"),
PINCTRL_PIN(24, "CATERR_B"),
PINCTRL_PIN(25, "PROCHOT_B"),
PINCTRL_PIN(26, "THERMTRIP_B"),
PINCTRL_PIN(27, "DSI_DE_TE_2_GENLOCK_REF"),
PINCTRL_PIN(28, "DSI_DE_TE_1_DISP_UTILS"),
/* GPP_C */
PINCTRL_PIN(29, "SMBCLK"),
PINCTRL_PIN(30, "SMBDATA"),
PINCTRL_PIN(31, "SMBALERT_B"),
PINCTRL_PIN(32, "SML0CLK"),
PINCTRL_PIN(33, "SML0DATA"),
PINCTRL_PIN(34, "GPP_C_5"),
PINCTRL_PIN(35, "GPP_C_6"),
PINCTRL_PIN(36, "GPP_C_7"),
PINCTRL_PIN(37, "GPP_C_8"),
PINCTRL_PIN(38, "GPP_C_9"),
PINCTRL_PIN(39, "GPP_C_10"),
PINCTRL_PIN(40, "GPP_C_11"),
PINCTRL_PIN(41, "GPP_C_12"),
PINCTRL_PIN(42, "GPP_C_13"),
PINCTRL_PIN(43, "GPP_C_14"),
PINCTRL_PIN(44, "GPP_C_15"),
PINCTRL_PIN(45, "GPP_C_16"),
PINCTRL_PIN(46, "GPP_C_17"),
PINCTRL_PIN(47, "GPP_C_18"),
PINCTRL_PIN(48, "GPP_C_19"),
PINCTRL_PIN(49, "GPP_C_20"),
PINCTRL_PIN(50, "GPP_C_21"),
PINCTRL_PIN(51, "GPP_C_22"),
PINCTRL_PIN(52, "GPP_C_23"),
/* GPP_A */
PINCTRL_PIN(53, "ESPI_IO_0"),
PINCTRL_PIN(54, "ESPI_IO_1"),
PINCTRL_PIN(55, "ESPI_IO_2"),
PINCTRL_PIN(56, "ESPI_IO_3"),
PINCTRL_PIN(57, "ESPI_CS0_B"),
PINCTRL_PIN(58, "ESPI_CLK"),
PINCTRL_PIN(59, "ESPI_RESET_B"),
PINCTRL_PIN(60, "GPP_A_7"),
PINCTRL_PIN(61, "GPP_A_8"),
PINCTRL_PIN(62, "GPP_A_9"),
PINCTRL_PIN(63, "GPP_A_10"),
PINCTRL_PIN(64, "GPP_A_11"),
PINCTRL_PIN(65, "GPP_A_12"),
PINCTRL_PIN(66, "ESPI_CS1_B"),
PINCTRL_PIN(67, "ESPI_CS2_B"),
PINCTRL_PIN(68, "ESPI_CS3_B"),
PINCTRL_PIN(69, "ESPI_ALERT0_B"),
PINCTRL_PIN(70, "ESPI_ALERT1_B"),
PINCTRL_PIN(71, "ESPI_ALERT2_B"),
PINCTRL_PIN(72, "ESPI_ALERT3_B"),
PINCTRL_PIN(73, "GPP_A_20"),
PINCTRL_PIN(74, "GPP_A_21"),
PINCTRL_PIN(75, "GPP_A_22"),
PINCTRL_PIN(76, "GPP_A_23"),
PINCTRL_PIN(77, "ESPI_CLK_LOOPBK"),
/* GPP_E */
PINCTRL_PIN(78, "GPP_E_0"),
PINCTRL_PIN(79, "GPP_E_1"),
PINCTRL_PIN(80, "GPP_E_2"),
PINCTRL_PIN(81, "GPP_E_3"),
PINCTRL_PIN(82, "GPP_E_4"),
PINCTRL_PIN(83, "GPP_E_5"),
PINCTRL_PIN(84, "GPP_E_6"),
PINCTRL_PIN(85, "GPP_E_7"),
PINCTRL_PIN(86, "GPP_E_8"),
PINCTRL_PIN(87, "GPP_E_9"),
PINCTRL_PIN(88, "GPP_E_10"),
PINCTRL_PIN(89, "GPP_E_11"),
PINCTRL_PIN(90, "GPP_E_12"),
PINCTRL_PIN(91, "GPP_E_13"),
PINCTRL_PIN(92, "GPP_E_14"),
PINCTRL_PIN(93, "SLP_DRAM_B"),
PINCTRL_PIN(94, "GPP_E_16"),
PINCTRL_PIN(95, "GPP_E_17"),
PINCTRL_PIN(96, "GPP_E_18"),
PINCTRL_PIN(97, "GPP_E_19"),
PINCTRL_PIN(98, "GPP_E_20"),
PINCTRL_PIN(99, "GPP_E_21"),
PINCTRL_PIN(100, "DNX_FORCE_RELOAD"),
PINCTRL_PIN(101, "GPP_E_23"),
PINCTRL_PIN(102, "THC0_GSPI0_CLK_LOOPBK"),
/* GPP_H */
PINCTRL_PIN(103, "GPP_H_0"),
PINCTRL_PIN(104, "GPP_H_1"),
PINCTRL_PIN(105, "GPP_H_2"),
PINCTRL_PIN(106, "GPP_H_3"),
PINCTRL_PIN(107, "GPP_H_4"),
PINCTRL_PIN(108, "GPP_H_5"),
PINCTRL_PIN(109, "GPP_H_6"),
PINCTRL_PIN(110, "GPP_H_7"),
PINCTRL_PIN(111, "GPP_H_8"),
PINCTRL_PIN(112, "GPP_H_9"),
PINCTRL_PIN(113, "GPP_H_10"),
PINCTRL_PIN(114, "GPP_H_11"),
PINCTRL_PIN(115, "GPP_H_12"),
PINCTRL_PIN(116, "CPU_C10_GATE_B"),
PINCTRL_PIN(117, "GPP_H_14"),
PINCTRL_PIN(118, "GPP_H_15"),
PINCTRL_PIN(119, "GPP_H_16"),
PINCTRL_PIN(120, "GPP_H_17"),
PINCTRL_PIN(121, "GPP_H_18"),
PINCTRL_PIN(122, "GPP_H_19"),
PINCTRL_PIN(123, "GPP_H_20"),
PINCTRL_PIN(124, "GPP_H_21"),
PINCTRL_PIN(125, "GPP_H_22"),
PINCTRL_PIN(126, "GPP_H_23"),
PINCTRL_PIN(127, "LPI3C1_CLK_LOOPBK"),
PINCTRL_PIN(128, "I3C0_CLK_LOOPBK"),
/* GPP_F */
PINCTRL_PIN(129, "CNV_BRI_DT"),
PINCTRL_PIN(130, "CNV_BRI_RSP"),
PINCTRL_PIN(131, "CNV_RGI_DT"),
PINCTRL_PIN(132, "CNV_RGI_RSP"),
PINCTRL_PIN(133, "CNV_RF_RESET_B"),
PINCTRL_PIN(134, "CRF_CLKREQ"),
PINCTRL_PIN(135, "GPP_F_6"),
PINCTRL_PIN(136, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(137, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(138, "BOOTMPC"),
PINCTRL_PIN(139, "GPP_F_10"),
PINCTRL_PIN(140, "GPP_F_11"),
PINCTRL_PIN(141, "GSXDOUT"),
PINCTRL_PIN(142, "GSXSLOAD"),
PINCTRL_PIN(143, "GSXDIN"),
PINCTRL_PIN(144, "GSXSRESETB"),
PINCTRL_PIN(145, "GSXCLK"),
PINCTRL_PIN(146, "GMII_MDC_0"),
PINCTRL_PIN(147, "GMII_MDIO_0"),
PINCTRL_PIN(148, "GPP_F_19"),
PINCTRL_PIN(149, "GPP_F_20"),
PINCTRL_PIN(150, "GPP_F_21"),
PINCTRL_PIN(151, "GPP_F_22"),
PINCTRL_PIN(152, "GPP_F_23"),
PINCTRL_PIN(153, "THC1_GSPI1_CLK_LOOPBK"),
PINCTRL_PIN(154, "GSPI0A_CLK_LOOPBK"),
/* SPI0 */
PINCTRL_PIN(155, "SPI0_IO_2"),
PINCTRL_PIN(156, "SPI0_IO_3"),
PINCTRL_PIN(157, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(158, "SPI0_MISO_IO_1"),
PINCTRL_PIN(159, "SPI0_TPM_CS_B"),
PINCTRL_PIN(160, "SPI0_FLASH_0_CS_B"),
PINCTRL_PIN(161, "SPI0_FLASH_1_CS_B"),
PINCTRL_PIN(162, "SPI0_CLK"),
PINCTRL_PIN(163, "L_BKLTEN"),
PINCTRL_PIN(164, "L_BKLTCTL"),
PINCTRL_PIN(165, "L_VDDEN"),
PINCTRL_PIN(166, "SYS_PWROK"),
PINCTRL_PIN(167, "SYS_RESET_B"),
PINCTRL_PIN(168, "MLK_RST_B"),
PINCTRL_PIN(169, "SPI0_CLK_LOOPBK"),
/* vGPIO_3 */
PINCTRL_PIN(170, "ESPI_USB_OCB_0"),
PINCTRL_PIN(171, "ESPI_USB_OCB_1"),
PINCTRL_PIN(172, "ESPI_USB_OCB_2"),
PINCTRL_PIN(173, "ESPI_USB_OCB_3"),
PINCTRL_PIN(174, "USB_CPU_OCB_0"),
PINCTRL_PIN(175, "USB_CPU_OCB_1"),
PINCTRL_PIN(176, "USB_CPU_OCB_2"),
PINCTRL_PIN(177, "USB_CPU_OCB_3"),
PINCTRL_PIN(178, "TS0_IN_INT"),
PINCTRL_PIN(179, "TS1_IN_INT"),
PINCTRL_PIN(180, "THC0_WOT_INT"),
PINCTRL_PIN(181, "THC1_WOT_INT"),
PINCTRL_PIN(182, "THC0_WHC_INT"),
PINCTRL_PIN(183, "THC1_WHC_INT"),
/* GPP_S */
PINCTRL_PIN(184, "GPP_S_0"),
PINCTRL_PIN(185, "GPP_S_1"),
PINCTRL_PIN(186, "GPP_S_2"),
PINCTRL_PIN(187, "GPP_S_3"),
PINCTRL_PIN(188, "GPP_S_4"),
PINCTRL_PIN(189, "GPP_S_5"),
PINCTRL_PIN(190, "GPP_S_6"),
PINCTRL_PIN(191, "GPP_S_7"),
/* JTAG */
PINCTRL_PIN(192, "JTAG_MBPB0"),
PINCTRL_PIN(193, "JTAG_MBPB1"),
PINCTRL_PIN(194, "JTAG_MBPB2"),
PINCTRL_PIN(195, "JTAG_MBPB3"),
PINCTRL_PIN(196, "JTAG_TDO"),
PINCTRL_PIN(197, "PRDY_B"),
PINCTRL_PIN(198, "PREQ_B"),
PINCTRL_PIN(199, "JTAG_TDI"),
PINCTRL_PIN(200, "JTAG_TMS"),
PINCTRL_PIN(201, "JTAG_TCK"),
PINCTRL_PIN(202, "DBG_PMODE"),
PINCTRL_PIN(203, "JTAG_TRST_B"),
/* GPP_B */
PINCTRL_PIN(204, "ADM_VID_0"),
PINCTRL_PIN(205, "ADM_VID_1"),
PINCTRL_PIN(206, "GPP_B_2"),
PINCTRL_PIN(207, "GPP_B_3"),
PINCTRL_PIN(208, "GPP_B_4"),
PINCTRL_PIN(209, "GPP_B_5"),
PINCTRL_PIN(210, "GPP_B_6"),
PINCTRL_PIN(211, "GPP_B_7"),
PINCTRL_PIN(212, "GPP_B_8"),
PINCTRL_PIN(213, "GPP_B_9"),
PINCTRL_PIN(214, "GPP_B_10"),
PINCTRL_PIN(215, "GPP_B_11"),
PINCTRL_PIN(216, "SLP_S0_B"),
PINCTRL_PIN(217, "PLTRST_B"),
PINCTRL_PIN(218, "GPP_B_14"),
PINCTRL_PIN(219, "GPP_B_15"),
PINCTRL_PIN(220, "GPP_B_16"),
PINCTRL_PIN(221, "GPP_B_17"),
PINCTRL_PIN(222, "GPP_B_18"),
PINCTRL_PIN(223, "GPP_B_19"),
PINCTRL_PIN(224, "GPP_B_20"),
PINCTRL_PIN(225, "GPP_B_21"),
PINCTRL_PIN(226, "GPP_B_22"),
PINCTRL_PIN(227, "GPP_B_23"),
PINCTRL_PIN(228, "ISH_I3C0_CLK_LOOPBK"),
/* GPP_D */
PINCTRL_PIN(229, "GPP_D_0"),
PINCTRL_PIN(230, "GPP_D_1"),
PINCTRL_PIN(231, "GPP_D_2"),
PINCTRL_PIN(232, "GPP_D_3"),
PINCTRL_PIN(233, "GPP_D_4"),
PINCTRL_PIN(234, "GPP_D_5"),
PINCTRL_PIN(235, "GPP_D_6"),
PINCTRL_PIN(236, "GPP_D_7"),
PINCTRL_PIN(237, "GPP_D_8"),
PINCTRL_PIN(238, "GPP_D_9"),
PINCTRL_PIN(239, "HDA_BCLK"),
PINCTRL_PIN(240, "HDA_SYNC"),
PINCTRL_PIN(241, "HDA_SDO"),
PINCTRL_PIN(242, "HDA_SDI_0"),
PINCTRL_PIN(243, "GPP_D_14"),
PINCTRL_PIN(244, "GPP_D_15"),
PINCTRL_PIN(245, "GPP_D_16"),
PINCTRL_PIN(246, "HDA_RST_B"),
PINCTRL_PIN(247, "GPP_D_18"),
PINCTRL_PIN(248, "GPP_D_19"),
PINCTRL_PIN(249, "GPP_D_20"),
PINCTRL_PIN(250, "UFS_REFCLK"),
PINCTRL_PIN(251, "BPKI3C_SDA"),
PINCTRL_PIN(252, "BPKI3C_SCL"),
PINCTRL_PIN(253, "BOOTHALT_B"),
/* vGPIO */
PINCTRL_PIN(254, "CNV_BTEN"),
PINCTRL_PIN(255, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(256, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(257, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(258, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(259, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(260, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(261, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(262, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(263, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(264, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(265, "vUART0_TXD"),
PINCTRL_PIN(266, "vUART0_RXD"),
PINCTRL_PIN(267, "vUART0_CTS_B"),
PINCTRL_PIN(268, "vUART0_RTS_B"),
PINCTRL_PIN(269, "vISH_UART0_TXD"),
PINCTRL_PIN(270, "vISH_UART0_RXD"),
PINCTRL_PIN(271, "vISH_UART0_CTS_B"),
PINCTRL_PIN(272, "vISH_UART0_RTS_B"),
PINCTRL_PIN(273, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(274, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(275, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(276, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(277, "vI2S2_SCLK"),
PINCTRL_PIN(278, "vI2S2_SFRM"),
PINCTRL_PIN(279, "vI2S2_TXD"),
PINCTRL_PIN(280, "vI2S2_RXD"),
PINCTRL_PIN(281, "vCNV_BT_I2S_BCLK_2"),
PINCTRL_PIN(282, "vCNV_BT_I2S_WS_SYNC_2"),
PINCTRL_PIN(283, "vCNV_BT_I2S_SDO_2"),
PINCTRL_PIN(284, "vCNV_BT_I2S_SDI_2"),
PINCTRL_PIN(285, "vI2S2_SCLK_2"),
PINCTRL_PIN(286, "vI2S2_SFRM_2"),
PINCTRL_PIN(287, "vI2S2_TXD_2"),
PINCTRL_PIN(288, "vI2S2_RXD_2"),
};
static const struct intel_padgroup mtlp_community0_gpps[] = {
MTL_GPP(0, 0, 4, 0), /* CPU */
MTL_GPP(1, 5, 28, 32), /* GPP_V */
MTL_GPP(2, 29, 52, 64), /* GPP_C */
};
static const struct intel_padgroup mtlp_community1_gpps[] = {
MTL_GPP(0, 53, 77, 96), /* GPP_A */
MTL_GPP(1, 78, 102, 128), /* GPP_E */
};
static const struct intel_padgroup mtlp_community3_gpps[] = {
MTL_GPP(0, 103, 128, 160), /* GPP_H */
MTL_GPP(1, 129, 154, 192), /* GPP_F */
MTL_GPP(2, 155, 169, 224), /* SPI0 */
MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */
};
static const struct intel_padgroup mtlp_community4_gpps[] = {
MTL_GPP(0, 184, 191, 288), /* GPP_S */
MTL_GPP(1, 192, 203, 320), /* JTAG */
};
static const struct intel_padgroup mtlp_community5_gpps[] = {
MTL_GPP(0, 204, 228, 352), /* GPP_B */
MTL_GPP(1, 229, 253, 384), /* GPP_D */
MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */
MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */
};
static const struct intel_community mtlp_communities[] = {
MTL_P_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
MTL_P_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
MTL_P_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
MTL_P_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
MTL_P_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
};
static const struct intel_pinctrl_soc_data mtlp_soc_data = {
.pins = mtlp_pins,
.npins = ARRAY_SIZE(mtlp_pins),
.communities = mtlp_communities,
.ncommunities = ARRAY_SIZE(mtlp_communities),
};
/* Meteor Lake-S */
static const struct pinctrl_pin_desc mtls_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "DIR_ESPI_IO_0"),
PINCTRL_PIN(1, "DIR_ESPI_IO_1"),
PINCTRL_PIN(2, "DIR_ESPI_IO_2"),
PINCTRL_PIN(3, "DIR_ESPI_IO_3"),
PINCTRL_PIN(4, "DIR_ESPI_CS0_B"),
PINCTRL_PIN(5, "DIR_ESPI_CLK"),
PINCTRL_PIN(6, "DIR_ESPI_RCLK"),
PINCTRL_PIN(7, "DIR_ESPI_RESET_B"),
PINCTRL_PIN(8, "SLP_S0_B"),
PINCTRL_PIN(9, "DMI_PERSTB"),
PINCTRL_PIN(10, "CATERR_B"),
PINCTRL_PIN(11, "THERMTRIP_B"),
PINCTRL_PIN(12, "CPU_C10_GATE_B"),
PINCTRL_PIN(13, "PS_ONB"),
PINCTRL_PIN(14, "GPP_SA_14"),
PINCTRL_PIN(15, "GPP_SA_15"),
PINCTRL_PIN(16, "GPP_SA_16"),
PINCTRL_PIN(17, "GPP_SA_17"),
PINCTRL_PIN(18, "GPP_SA_18"),
PINCTRL_PIN(19, "GPP_SA_19"),
PINCTRL_PIN(20, "GPP_SA_20"),
PINCTRL_PIN(21, "GPP_SA_21"),
PINCTRL_PIN(22, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(23, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(24, "RTCCLKIN"),
PINCTRL_PIN(25, "RESET_SYNC_B"),
PINCTRL_PIN(26, "PCH_PWROK"),
PINCTRL_PIN(27, "DIR_ESPI_CLK_LOOPBACK"),
/* vGPIO_0 */
PINCTRL_PIN(28, "LPC_ME_FTPM_ENABLE"),
PINCTRL_PIN(29, "LPC_DTFUS_CORE_SPITPM_DIS"),
PINCTRL_PIN(30, "LPC_SPI_STRAP_TOS"),
PINCTRL_PIN(31, "ITSS_KU1_SHTDWN"),
PINCTRL_PIN(32, "LPC_PRR_TS_OVR"),
PINCTRL_PIN(33, "ESPI_PMC_EC_SCI"),
PINCTRL_PIN(34, "ESPI_PMC_EC_SCI1"),
PINCTRL_PIN(35, "vGPIO_SPARE0"),
PINCTRL_PIN(36, "vGPIO_SPARE1"),
PINCTRL_PIN(37, "vGPIO_SPARE2"),
PINCTRL_PIN(38, "vGPIO_SPARE3"),
PINCTRL_PIN(39, "vGPIO_SPARE8"),
PINCTRL_PIN(40, "vGPIO_SPARE9"),
PINCTRL_PIN(41, "vGPIO_SPARE10"),
PINCTRL_PIN(42, "vGPIO_SPARE11"),
PINCTRL_PIN(43, "vGPIO_SPARE12"),
PINCTRL_PIN(44, "vGPIO_SPARE13"),
PINCTRL_PIN(45, "vGPIO_SPARE14"),
PINCTRL_PIN(46, "vGPIO_SPARE15"),
/* GPP_C */
PINCTRL_PIN(47, "GPP_SC_0"),
PINCTRL_PIN(48, "GPP_SC_1"),
PINCTRL_PIN(49, "GPP_SC_2"),
PINCTRL_PIN(50, "GPP_SC_3"),
PINCTRL_PIN(51, "GPP_SC_4"),
PINCTRL_PIN(52, "GPP_SC_5"),
PINCTRL_PIN(53, "GPP_SC_6"),
PINCTRL_PIN(54, "GPP_SC_7"),
PINCTRL_PIN(55, "GPP_SC_8"),
PINCTRL_PIN(56, "GPP_SC_9"),
PINCTRL_PIN(57, "GPP_SC_10"),
PINCTRL_PIN(58, "GPP_SC_11"),
PINCTRL_PIN(59, "GPP_SC_12"),
PINCTRL_PIN(60, "GPP_SC_13"),
PINCTRL_PIN(61, "GPP_SC_14"),
PINCTRL_PIN(62, "GPP_SC_15"),
PINCTRL_PIN(63, "GPP_SC_16"),
PINCTRL_PIN(64, "GPP_SC_17"),
PINCTRL_PIN(65, "GPP_SC_18"),
PINCTRL_PIN(66, "GPP_SC_19"),
PINCTRL_PIN(67, "GPP_SC_20"),
PINCTRL_PIN(68, "GPP_SC_21"),
PINCTRL_PIN(69, "GPP_SC_22"),
PINCTRL_PIN(70, "GPP_SC_23"),
PINCTRL_PIN(71, "GPP_SC_24"),
PINCTRL_PIN(72, "GPP_SC_25"),
PINCTRL_PIN(73, "GPP_SC_26"),
/* GPP_B */
PINCTRL_PIN(74, "GPP_SB_0"),
PINCTRL_PIN(75, "GPP_SB_1"),
PINCTRL_PIN(76, "GPP_SB_2"),
PINCTRL_PIN(77, "GPP_SB_3"),
PINCTRL_PIN(78, "GPP_SB_4"),
PINCTRL_PIN(79, "GPP_SB_5"),
PINCTRL_PIN(80, "GPP_SB_6"),
PINCTRL_PIN(81, "GPP_SB_7"),
PINCTRL_PIN(82, "GPP_SB_8"),
PINCTRL_PIN(83, "GPP_SB_9"),
PINCTRL_PIN(84, "GPP_SB_10"),
PINCTRL_PIN(85, "GPP_SB_11"),
PINCTRL_PIN(86, "GPP_SB_12"),
PINCTRL_PIN(87, "GPP_SB_13"),
PINCTRL_PIN(88, "GPP_SB_14"),
PINCTRL_PIN(89, "GPP_SB_15"),
PINCTRL_PIN(90, "GPP_SB_16"),
PINCTRL_PIN(91, "PROCHOT_B"),
PINCTRL_PIN(92, "BPKI3C_SDA"),
PINCTRL_PIN(93, "BPKI3C_SCL"),
/* vGPIO_3 */
PINCTRL_PIN(94, "TS0_IN_INT"),
PINCTRL_PIN(95, "TS1_IN_INT"),
/* GPP_D */
PINCTRL_PIN(96, "TIME_SYNC_0"),
PINCTRL_PIN(97, "TIME_SYNC_1"),
PINCTRL_PIN(98, "DSI_DE_TE_2_GENLOCK_REF"),
PINCTRL_PIN(99, "DSI_DE_TE_1_DISP_UTILS"),
PINCTRL_PIN(100, "DSI_GENLOCK_2"),
PINCTRL_PIN(101, "DSI_GENLOCK_3"),
PINCTRL_PIN(102, "SRCCLKREQ2_B"),
PINCTRL_PIN(103, "SRCCLKREQ3_B"),
PINCTRL_PIN(104, "GPP_SD_8"),
PINCTRL_PIN(105, "GPP_SD_9"),
PINCTRL_PIN(106, "GPP_SD_10"),
PINCTRL_PIN(107, "GPP_SD_11"),
PINCTRL_PIN(108, "GPP_SD_12"),
PINCTRL_PIN(109, "GPP_SD_13"),
PINCTRL_PIN(110, "GPP_SD_14"),
PINCTRL_PIN(111, "GPP_SD_15"),
PINCTRL_PIN(112, "GPP_SD_16"),
PINCTRL_PIN(113, "GPP_SD_17"),
PINCTRL_PIN(114, "BOOTHALT_B"),
PINCTRL_PIN(115, "GPP_SD_19"),
PINCTRL_PIN(116, "GPP_SD_20"),
PINCTRL_PIN(117, "AUDCLK"),
PINCTRL_PIN(118, "AUDIN"),
PINCTRL_PIN(119, "AUDOUT"),
/* JTAG_CPU */
PINCTRL_PIN(120, "PECI"),
PINCTRL_PIN(121, "VIDSOUT"),
PINCTRL_PIN(122, "VIDSCK"),
PINCTRL_PIN(123, "VIDALERT_B"),
PINCTRL_PIN(124, "JTAG_MBPB0"),
PINCTRL_PIN(125, "JTAG_MBPB1"),
PINCTRL_PIN(126, "JTAG_MBPB2"),
PINCTRL_PIN(127, "JTAG_MBPB3"),
PINCTRL_PIN(128, "JTAG_TDO"),
PINCTRL_PIN(129, "PRDY_B"),
PINCTRL_PIN(130, "PREQ_B"),
PINCTRL_PIN(131, "JTAG_TDI"),
PINCTRL_PIN(132, "JTAG_TMS"),
PINCTRL_PIN(133, "JTAG_TCK"),
PINCTRL_PIN(134, "DBG_PMODE"),
PINCTRL_PIN(135, "JTAG_TRST_B"),
/* vGPIO_4 */
PINCTRL_PIN(136, "ISCLK_ESPI_XTAL_CLKREQ"),
PINCTRL_PIN(137, "ESPI_ISCLK_XTAL_CLKACK"),
PINCTRL_PIN(138, "vGPIO_SPARE4"),
PINCTRL_PIN(139, "vGPIO_SPARE5"),
PINCTRL_PIN(140, "vGPIO_SPARE6"),
PINCTRL_PIN(141, "vGPIO_SPARE7"),
PINCTRL_PIN(142, "vGPIO_SPARE16"),
PINCTRL_PIN(143, "vGPIO_SPARE17"),
PINCTRL_PIN(144, "vGPIO_SPARE18"),
PINCTRL_PIN(145, "vGPIO_SPARE19"),
PINCTRL_PIN(146, "vGPIO_SPARE20"),
PINCTRL_PIN(147, "vGPIO_SPARE21"),
};
static const struct intel_padgroup mtls_community0_gpps[] = {
MTL_GPP(0, 0, 27, 0), /* GPP_A */
MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */
MTL_GPP(2, 47, 73, 64), /* GPP_C */
};
static const struct intel_padgroup mtls_community1_gpps[] = {
MTL_GPP(0, 74, 93, 96), /* GPP_B */
MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */
MTL_GPP(2, 96, 119, 160), /* GPP_D */
};
static const struct intel_padgroup mtls_community3_gpps[] = {
MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */
MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */
};
static const struct intel_community mtls_communities[] = {
MTL_S_COMMUNITY(0, 0, 73, mtls_community0_gpps),
MTL_S_COMMUNITY(1, 74, 119, mtls_community1_gpps),
MTL_S_COMMUNITY(2, 120, 147, mtls_community3_gpps),
};
static const struct intel_pinctrl_soc_data mtls_soc_data = {
.pins = mtls_pins,
.npins = ARRAY_SIZE(mtls_pins),
.communities = mtls_communities,
.ncommunities = ARRAY_SIZE(mtls_communities),
};
static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
{ "INTC1082", (kernel_ulong_t)&mtls_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(mtl_pinctrl_pm_ops);
static struct platform_driver mtl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "meteorlake-pinctrl",
.acpi_match_table = mtl_pinctrl_acpi_match,
.pm = &mtl_pinctrl_pm_ops,
},
};
module_platform_driver(mtl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_DESCRIPTION("Intel Meteor Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-meteorlake.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Lynxpoint PCH pinctrl/GPIO driver
*
* Copyright (c) 2012, 2019, Intel Corporation
* Authors: Mathias Nyman <[email protected]>
* Andy Shevchenko <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-intel.h"
#define COMMUNITY(p, n) \
{ \
.pin_base = (p), \
.npins = (n), \
}
static const struct pinctrl_pin_desc lptlp_pins[] = {
PINCTRL_PIN(0, "GP0_UART1_RXD"),
PINCTRL_PIN(1, "GP1_UART1_TXD"),
PINCTRL_PIN(2, "GP2_UART1_RTSB"),
PINCTRL_PIN(3, "GP3_UART1_CTSB"),
PINCTRL_PIN(4, "GP4_I2C0_SDA"),
PINCTRL_PIN(5, "GP5_I2C0_SCL"),
PINCTRL_PIN(6, "GP6_I2C1_SDA"),
PINCTRL_PIN(7, "GP7_I2C1_SCL"),
PINCTRL_PIN(8, "GP8"),
PINCTRL_PIN(9, "GP9"),
PINCTRL_PIN(10, "GP10"),
PINCTRL_PIN(11, "GP11_SMBALERTB"),
PINCTRL_PIN(12, "GP12_LANPHYPC"),
PINCTRL_PIN(13, "GP13"),
PINCTRL_PIN(14, "GP14"),
PINCTRL_PIN(15, "GP15"),
PINCTRL_PIN(16, "GP16_MGPIO9"),
PINCTRL_PIN(17, "GP17_MGPIO10"),
PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
PINCTRL_PIN(24, "GP24_MGPIO0"),
PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
PINCTRL_PIN(26, "GP26_MGPIO5"),
PINCTRL_PIN(27, "GP27_MGPIO6"),
PINCTRL_PIN(28, "GP28_MGPIO7"),
PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
PINCTRL_PIN(32, "GP32_CLKRUNB"),
PINCTRL_PIN(33, "GP33_DEVSLP0"),
PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
PINCTRL_PIN(38, "GP38_DEVSLP1"),
PINCTRL_PIN(39, "GP39_DEVSLP2"),
PINCTRL_PIN(40, "GP40_OC0B"),
PINCTRL_PIN(41, "GP41_OC1B"),
PINCTRL_PIN(42, "GP42_OC2B"),
PINCTRL_PIN(43, "GP43_OC3B"),
PINCTRL_PIN(44, "GP44"),
PINCTRL_PIN(45, "GP45_TMS2"),
PINCTRL_PIN(46, "GP46_TDO2"),
PINCTRL_PIN(47, "GP47"),
PINCTRL_PIN(48, "GP48"),
PINCTRL_PIN(49, "GP49"),
PINCTRL_PIN(50, "GP50"),
PINCTRL_PIN(51, "GP51_GSXDOUT"),
PINCTRL_PIN(52, "GP52_GSXSLOAD"),
PINCTRL_PIN(53, "GP53_GSXDIN"),
PINCTRL_PIN(54, "GP54_GSXSRESETB"),
PINCTRL_PIN(55, "GP55_GSXCLK"),
PINCTRL_PIN(56, "GP56"),
PINCTRL_PIN(57, "GP57"),
PINCTRL_PIN(58, "GP58"),
PINCTRL_PIN(59, "GP59"),
PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
PINCTRL_PIN(61, "GP61_SUS_STATB"),
PINCTRL_PIN(62, "GP62_SUSCLK"),
PINCTRL_PIN(63, "GP63_SLP_S5B"),
PINCTRL_PIN(64, "GP64_SDIO_CLK"),
PINCTRL_PIN(65, "GP65_SDIO_CMD"),
PINCTRL_PIN(66, "GP66_SDIO_D0"),
PINCTRL_PIN(67, "GP67_SDIO_D1"),
PINCTRL_PIN(68, "GP68_SDIO_D2"),
PINCTRL_PIN(69, "GP69_SDIO_D3"),
PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
PINCTRL_PIN(71, "GP71_MPHYPC"),
PINCTRL_PIN(72, "GP72_BATLOWB"),
PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
PINCTRL_PIN(76, "GP76_BMBUSYB"),
PINCTRL_PIN(77, "GP77_PIRQAB"),
PINCTRL_PIN(78, "GP78_PIRQBB"),
PINCTRL_PIN(79, "GP79_PIRQCB"),
PINCTRL_PIN(80, "GP80_PIRQDB"),
PINCTRL_PIN(81, "GP81_SPKR"),
PINCTRL_PIN(82, "GP82_RCINB"),
PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
PINCTRL_PIN(91, "GP91_UART0_RXD"),
PINCTRL_PIN(92, "GP92_UART0_TXD"),
PINCTRL_PIN(93, "GP93_UART0_RTSB"),
PINCTRL_PIN(94, "GP94_UART0_CTSB"),
};
static const struct intel_community lptlp_communities[] = {
COMMUNITY(0, 95),
};
static const struct intel_pinctrl_soc_data lptlp_soc_data = {
.pins = lptlp_pins,
.npins = ARRAY_SIZE(lptlp_pins),
.communities = lptlp_communities,
.ncommunities = ARRAY_SIZE(lptlp_communities),
};
/* LynxPoint chipset has support for 95 GPIO pins */
#define LP_NUM_GPIO 95
/* Bitmapped register offsets */
#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
#define LP_INT_STAT 0x80
#define LP_INT_ENABLE 0x90
/* Each pin has two 32 bit config registers, starting at 0x100 */
#define LP_CONFIG1 0x100
#define LP_CONFIG2 0x104
/* LP_CONFIG1 reg bits */
#define OUT_LVL_BIT BIT(31)
#define IN_LVL_BIT BIT(30)
#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */
#define USE_SEL_NATIVE (0 << 0)
#define USE_SEL_GPIO (1 << 0)
/* LP_CONFIG2 reg bits */
#define GPINDIS_BIT BIT(2) /* disable input sensing */
#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
#define GPIWP_NONE 0 /* none */
#define GPIWP_DOWN 1 /* weak pull down */
#define GPIWP_UP 2 /* weak pull up */
/*
* Lynxpoint gpios are controlled through both bitmapped registers and
* per gpio specific registers. The bitmapped registers are in chunks of
* 3 x 32bit registers to cover all 95 GPIOs
*
* per gpio specific registers consist of two 32bit registers per gpio
* (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
* 190 config registers.
*
* A simplified view of the register layout look like this:
*
* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
* ...
* LP_INT_ENABLE[31:0] ...
* LP_INT_ENABLE[63:32] ...
* LP_INT_ENABLE[94:64] ...
* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
* LP2_CONFIG1 (gpio 2) ...
* LP2_CONFIG2 (gpio 2) ...
* ...
* LP94_CONFIG1 (gpio 94) ...
* LP94_CONFIG2 (gpio 94) ...
*
* IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
*/
static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
int reg)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
struct intel_community *comm;
int reg_offset;
comm = intel_get_community(lg, offset);
if (!comm)
return NULL;
offset -= comm->pin_base;
if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
/* per gpio specific config registers */
reg_offset = offset * 8;
else
/* bitmapped registers */
reg_offset = (offset / 32) * 4;
return comm->regs + reg_offset + reg;
}
static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
{
void __iomem *acpi_use;
acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
if (!acpi_use)
return true;
return !(ioread32(acpi_use) & BIT(pin % 32));
}
static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
u32 value;
value = ioread32(ioxapic_use);
if (offset >= 8 && offset <= 10)
return !!(value & BIT(offset - 8 + 0));
if (offset >= 13 && offset <= 14)
return !!(value & BIT(offset - 13 + 3));
if (offset >= 45 && offset <= 55)
return !!(value & BIT(offset - 45 + 5));
return false;
}
static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int pin)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
u32 value, mode;
value = ioread32(reg);
mode = value & USE_SEL_MASK;
if (mode == USE_SEL_GPIO)
seq_puts(s, "GPIO ");
else
seq_printf(s, "mode %d ", mode);
seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
if (lp_gpio_acpi_use(lg, pin))
seq_puts(s, " [ACPI]");
}
static const struct pinctrl_ops lptlp_pinctrl_ops = {
.get_groups_count = intel_get_groups_count,
.get_group_name = intel_get_group_name,
.get_group_pins = intel_get_group_pins,
.pin_dbg_show = lp_pin_dbg_show,
};
static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pingroup *grp = &lg->soc->groups[group];
unsigned long flags;
int i;
raw_spin_lock_irqsave(&lg->lock, flags);
/* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->grp.npins; i++) {
void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1);
u32 value;
value = ioread32(reg);
value &= ~USE_SEL_MASK;
if (grp->modes)
value |= grp->modes[i];
else
value |= grp->mode;
iowrite32(value, reg);
}
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
static void lp_gpio_enable_input(void __iomem *reg)
{
iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
}
static void lp_gpio_disable_input(void __iomem *reg)
{
iowrite32(ioread32(reg) | GPINDIS_BIT, reg);
}
static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
unsigned long flags;
u32 value;
pm_runtime_get(lg->dev);
raw_spin_lock_irqsave(&lg->lock, flags);
/*
* Reconfigure pin to GPIO mode if needed and issue a warning,
* since we expect firmware to configure it properly.
*/
value = ioread32(reg);
if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
}
/* Enable input sensing */
lp_gpio_enable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
/* Disable input sensing */
lp_gpio_disable_input(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
pm_runtime_put(lg->dev);
}
static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(reg);
value &= ~DIR_BIT;
if (input) {
value |= DIR_BIT;
} else {
/*
* Before making any direction modifications, do a check if GPIO
* is set for direct IRQ. On Lynxpoint, setting GPIO to output
* does not make sense, so let's at least warn the caller before
* they shoot themselves in the foot.
*/
WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
"Potential Error: Setting GPIO to output with IOxAPIC redirection");
}
iowrite32(value, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
static const struct pinmux_ops lptlp_pinmux_ops = {
.get_functions_count = intel_get_functions_count,
.get_function_name = intel_get_function_name,
.get_function_groups = intel_get_function_groups,
.set_mux = lp_pinmux_set_mux,
.gpio_request_enable = lp_gpio_request_enable,
.gpio_disable_free = lp_gpio_disable_free,
.gpio_set_direction = lp_gpio_set_direction,
};
static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
u32 value, pull;
u16 arg;
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
pull = value & GPIWP_MASK;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
if (pull != GPIWP_NONE)
return -EINVAL;
arg = 0;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
if (pull != GPIWP_DOWN)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (pull != GPIWP_UP)
return -EINVAL;
arg = 1;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
enum pin_config_param param;
unsigned long flags;
int i, ret = 0;
u32 value;
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(conf2);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
value &= ~GPIWP_MASK;
value |= GPIWP_NONE;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value &= ~GPIWP_MASK;
value |= GPIWP_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
value &= ~GPIWP_MASK;
value |= GPIWP_UP;
break;
default:
ret = -ENOTSUPP;
}
if (ret)
break;
}
if (!ret)
iowrite32(value, conf2);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return ret;
}
static const struct pinconf_ops lptlp_pinconf_ops = {
.is_generic = true,
.pin_config_get = lp_pin_config_get,
.pin_config_set = lp_pin_config_set,
};
static const struct pinctrl_desc lptlp_pinctrl_desc = {
.pctlops = &lptlp_pinctrl_ops,
.pmxops = &lptlp_pinmux_ops,
.confops = &lptlp_pinconf_ops,
.owner = THIS_MODULE,
};
static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
return !!(ioread32(reg) & IN_LVL_BIT);
}
static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
if (value)
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
else
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
int value)
{
lp_gpio_set(chip, offset, value);
return pinctrl_gpio_direction_output(chip->base + offset);
}
static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
if (ioread32(reg) & DIR_BIT)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static void lp_gpio_irq_handler(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
void __iomem *reg, *ena;
unsigned long pending;
u32 base, pin;
/* check from GPIO controller which pin triggered the interrupt */
for (base = 0; base < lg->chip.ngpio; base += 32) {
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
/* Only interrupts that are enabled */
pending = ioread32(reg) & ioread32(ena);
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
}
chip->irq_eoi(data);
}
static void lp_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static void lp_irq_unmask(struct irq_data *d)
{
}
static void lp_irq_mask(struct irq_data *d)
{
}
static void lp_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
gpiochip_enable_irq(gc, hwirq);
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
}
static void lp_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
unsigned long flags;
raw_spin_lock_irqsave(&lg->lock, flags);
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
raw_spin_unlock_irqrestore(&lg->lock, flags);
gpiochip_disable_irq(gc, hwirq);
}
static int lp_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *lg = gpiochip_get_data(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
void __iomem *reg;
u32 value;
reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
if (!reg)
return -EINVAL;
/* Fail if BIOS reserved pin for ACPI use */
if (lp_gpio_acpi_use(lg, hwirq)) {
dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq);
return -EBUSY;
}
raw_spin_lock_irqsave(&lg->lock, flags);
value = ioread32(reg);
/* set both TRIG_SEL and INV bits to 0 for rising edge */
if (type & IRQ_TYPE_EDGE_RISING)
value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
/* TRIG_SEL bit 0, INV bit 1 for falling edge */
if (type & IRQ_TYPE_EDGE_FALLING)
value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
/* TRIG_SEL bit 1, INV bit 0 for level low */
if (type & IRQ_TYPE_LEVEL_LOW)
value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
/* TRIG_SEL bit 1, INV bit 1 for level high */
if (type & IRQ_TYPE_LEVEL_HIGH)
value |= TRIG_SEL_BIT | INT_INV_BIT;
iowrite32(value, reg);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&lg->lock, flags);
return 0;
}
static const struct irq_chip lp_irqchip = {
.name = "LP-GPIO",
.irq_ack = lp_irq_ack,
.irq_mask = lp_irq_mask,
.irq_unmask = lp_irq_unmask,
.irq_enable = lp_irq_enable,
.irq_disable = lp_irq_disable,
.irq_set_type = lp_irq_set_type,
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
void __iomem *reg;
unsigned int base;
for (base = 0; base < lg->chip.ngpio; base += 32) {
/* disable gpio pin interrupts */
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
iowrite32(0, reg);
/* Clear interrupt status register */
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
iowrite32(0xffffffff, reg);
}
return 0;
}
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct intel_pinctrl *lg = gpiochip_get_data(chip);
struct device *dev = lg->dev;
int ret;
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
if (ret)
dev_err(dev, "failed to add GPIO pin range\n");
return ret;
}
static int lp_gpio_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc;
struct intel_pinctrl *lg;
struct gpio_chip *gc;
struct device *dev = &pdev->dev;
struct resource *io_rc;
void __iomem *regs;
unsigned int i;
int irq, ret;
soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
if (!soc)
return -ENODEV;
lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
if (!lg)
return -ENOMEM;
lg->dev = dev;
lg->soc = soc;
lg->ncommunities = lg->soc->ncommunities;
lg->communities = devm_kcalloc(dev, lg->ncommunities,
sizeof(*lg->communities), GFP_KERNEL);
if (!lg->communities)
return -ENOMEM;
lg->pctldesc = lptlp_pinctrl_desc;
lg->pctldesc.name = dev_name(dev);
lg->pctldesc.pins = lg->soc->pins;
lg->pctldesc.npins = lg->soc->npins;
lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
if (IS_ERR(lg->pctldev)) {
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(lg->pctldev);
}
platform_set_drvdata(pdev, lg);
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!io_rc) {
dev_err(dev, "missing IO resources\n");
return -EINVAL;
}
regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
if (!regs) {
dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
return -EBUSY;
}
for (i = 0; i < lg->soc->ncommunities; i++) {
struct intel_community *comm = &lg->communities[i];
*comm = lg->soc->communities[i];
comm->regs = regs;
comm->pad_regs = regs + 0x100;
}
raw_spin_lock_init(&lg->lock);
gc = &lg->chip;
gc->label = dev_name(dev);
gc->owner = THIS_MODULE;
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->direction_input = lp_gpio_direction_input;
gc->direction_output = lp_gpio_direction_output;
gc->get = lp_gpio_get;
gc->set = lp_gpio_set;
gc->set_config = gpiochip_generic_config;
gc->get_direction = lp_gpio_get_direction;
gc->base = -1;
gc->ngpio = LP_NUM_GPIO;
gc->can_sleep = false;
gc->add_pin_ranges = lp_gpio_add_pin_ranges;
gc->parent = dev;
/* set up interrupts */
irq = platform_get_irq_optional(pdev, 0);
if (irq > 0) {
struct gpio_irq_chip *girq;
girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &lp_irqchip);
girq->init_hw = lp_gpio_irq_init_hw;
girq->parent_handler = lp_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, girq->num_parents,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
ret = devm_gpiochip_add_data(dev, gc, lg);
if (ret) {
dev_err(dev, "failed adding lp-gpio chip\n");
return ret;
}
pm_runtime_enable(dev);
return 0;
}
static int lp_gpio_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
return 0;
}
static int lp_gpio_runtime_suspend(struct device *dev)
{
return 0;
}
static int lp_gpio_runtime_resume(struct device *dev)
{
return 0;
}
static int lp_gpio_resume(struct device *dev)
{
struct intel_pinctrl *lg = dev_get_drvdata(dev);
struct gpio_chip *chip = &lg->chip;
const char *dummy;
int i;
/* on some hardware suspend clears input sensing, re-enable it here */
for_each_requested_gpio(chip, i, dummy)
lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2));
return 0;
}
static const struct dev_pm_ops lp_gpio_pm_ops = {
SYSTEM_SLEEP_PM_OPS(NULL, lp_gpio_resume)
RUNTIME_PM_OPS(lp_gpio_runtime_suspend, lp_gpio_runtime_resume, NULL)
};
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
static struct platform_driver lp_gpio_driver = {
.probe = lp_gpio_probe,
.remove = lp_gpio_remove,
.driver = {
.name = "lp_gpio",
.pm = pm_ptr(&lp_gpio_pm_ops),
.acpi_match_table = lynxpoint_gpio_acpi_match,
},
};
static int __init lp_gpio_init(void)
{
return platform_driver_register(&lp_gpio_driver);
}
subsys_initcall(lp_gpio_init);
static void __exit lp_gpio_exit(void)
{
platform_driver_unregister(&lp_gpio_driver);
}
module_exit(lp_gpio_exit);
MODULE_AUTHOR("Mathias Nyman (Intel)");
MODULE_AUTHOR("Andy Shevchenko (Intel)");
MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:lp_gpio");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-lynxpoint.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Elkhart Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2019, Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define EHL_PAD_OWN 0x020
#define EHL_PADCFGLOCK 0x080
#define EHL_HOSTSW_OWN 0x0b0
#define EHL_GPI_IS 0x100
#define EHL_GPI_IE 0x120
#define EHL_GPP(r, s, e) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define EHL_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
/* Elkhart Lake */
static const struct pinctrl_pin_desc ehl_community0_pins[] = {
/* GPP_B */
PINCTRL_PIN(0, "CORE_VID_0"),
PINCTRL_PIN(1, "CORE_VID_1"),
PINCTRL_PIN(2, "VRALERTB"),
PINCTRL_PIN(3, "CPU_GP_2"),
PINCTRL_PIN(4, "CPU_GP_3"),
PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
PINCTRL_PIN(9, "I2C5_SDA"),
PINCTRL_PIN(10, "I2C5_SCL"),
PINCTRL_PIN(11, "PMCALERTB"),
PINCTRL_PIN(12, "SLP_S0B"),
PINCTRL_PIN(13, "PLTRSTB"),
PINCTRL_PIN(14, "SPKR"),
PINCTRL_PIN(15, "GSPI0_CS0B"),
PINCTRL_PIN(16, "GSPI0_CLK"),
PINCTRL_PIN(17, "GSPI0_MISO"),
PINCTRL_PIN(18, "GSPI0_MOSI"),
PINCTRL_PIN(19, "GSPI1_CS0B"),
PINCTRL_PIN(20, "GSPI1_CLK"),
PINCTRL_PIN(21, "GSPI1_MISO"),
PINCTRL_PIN(22, "GSPI1_MOSI"),
PINCTRL_PIN(23, "GPPC_B_23"),
PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
/* GPP_T */
PINCTRL_PIN(26, "OSE_QEPA_2"),
PINCTRL_PIN(27, "OSE_QEPB_2"),
PINCTRL_PIN(28, "OSE_QEPI_2"),
PINCTRL_PIN(29, "GPPC_T_3"),
PINCTRL_PIN(30, "RGMII0_INT"),
PINCTRL_PIN(31, "RGMII0_RESETB"),
PINCTRL_PIN(32, "RGMII0_AUXTS"),
PINCTRL_PIN(33, "RGMII0_PPS"),
PINCTRL_PIN(34, "USB2_OCB_2"),
PINCTRL_PIN(35, "OSE_HSUART2_EN"),
PINCTRL_PIN(36, "OSE_HSUART2_RE"),
PINCTRL_PIN(37, "USB2_OCB_3"),
PINCTRL_PIN(38, "OSE_UART2_RXD"),
PINCTRL_PIN(39, "OSE_UART2_TXD"),
PINCTRL_PIN(40, "OSE_UART2_RTSB"),
PINCTRL_PIN(41, "OSE_UART2_CTSB"),
/* GPP_G */
PINCTRL_PIN(42, "SD3_CMD"),
PINCTRL_PIN(43, "SD3_D0"),
PINCTRL_PIN(44, "SD3_D1"),
PINCTRL_PIN(45, "SD3_D2"),
PINCTRL_PIN(46, "SD3_D3"),
PINCTRL_PIN(47, "SD3_CDB"),
PINCTRL_PIN(48, "SD3_CLK"),
PINCTRL_PIN(49, "I2S2_SCLK"),
PINCTRL_PIN(50, "I2S2_SFRM"),
PINCTRL_PIN(51, "I2S2_TXD"),
PINCTRL_PIN(52, "I2S2_RXD"),
PINCTRL_PIN(53, "I2S3_SCLK"),
PINCTRL_PIN(54, "I2S3_SFRM"),
PINCTRL_PIN(55, "I2S3_TXD"),
PINCTRL_PIN(56, "I2S3_RXD"),
PINCTRL_PIN(57, "ESPI_IO_0"),
PINCTRL_PIN(58, "ESPI_IO_1"),
PINCTRL_PIN(59, "ESPI_IO_2"),
PINCTRL_PIN(60, "ESPI_IO_3"),
PINCTRL_PIN(61, "I2S1_SCLK"),
PINCTRL_PIN(62, "ESPI_CSB"),
PINCTRL_PIN(63, "ESPI_CLK"),
PINCTRL_PIN(64, "ESPI_RESETB"),
PINCTRL_PIN(65, "SD3_WP"),
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
};
static const struct intel_padgroup ehl_community0_gpps[] = {
EHL_GPP(0, 0, 25), /* GPP_B */
EHL_GPP(1, 26, 41), /* GPP_T */
EHL_GPP(2, 42, 66), /* GPP_G */
};
static const struct intel_community ehl_community0[] = {
EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
.uid = "0",
.pins = ehl_community0_pins,
.npins = ARRAY_SIZE(ehl_community0_pins),
.communities = ehl_community0,
.ncommunities = ARRAY_SIZE(ehl_community0),
};
static const struct pinctrl_pin_desc ehl_community1_pins[] = {
/* GPP_V */
PINCTRL_PIN(0, "EMMC_CMD"),
PINCTRL_PIN(1, "EMMC_DATA0"),
PINCTRL_PIN(2, "EMMC_DATA1"),
PINCTRL_PIN(3, "EMMC_DATA2"),
PINCTRL_PIN(4, "EMMC_DATA3"),
PINCTRL_PIN(5, "EMMC_DATA4"),
PINCTRL_PIN(6, "EMMC_DATA5"),
PINCTRL_PIN(7, "EMMC_DATA6"),
PINCTRL_PIN(8, "EMMC_DATA7"),
PINCTRL_PIN(9, "EMMC_RCLK"),
PINCTRL_PIN(10, "EMMC_CLK"),
PINCTRL_PIN(11, "EMMC_RESETB"),
PINCTRL_PIN(12, "OSE_TGPIO0"),
PINCTRL_PIN(13, "OSE_TGPIO1"),
PINCTRL_PIN(14, "OSE_TGPIO2"),
PINCTRL_PIN(15, "OSE_TGPIO3"),
/* GPP_H */
PINCTRL_PIN(16, "RGMII1_INT"),
PINCTRL_PIN(17, "RGMII1_RESETB"),
PINCTRL_PIN(18, "RGMII1_AUXTS"),
PINCTRL_PIN(19, "RGMII1_PPS"),
PINCTRL_PIN(20, "I2C2_SDA"),
PINCTRL_PIN(21, "I2C2_SCL"),
PINCTRL_PIN(22, "I2C3_SDA"),
PINCTRL_PIN(23, "I2C3_SCL"),
PINCTRL_PIN(24, "I2C4_SDA"),
PINCTRL_PIN(25, "I2C4_SCL"),
PINCTRL_PIN(26, "SRCCLKREQB_4"),
PINCTRL_PIN(27, "SRCCLKREQB_5"),
PINCTRL_PIN(28, "OSE_UART1_RXD"),
PINCTRL_PIN(29, "OSE_UART1_TXD"),
PINCTRL_PIN(30, "GPPC_H_14"),
PINCTRL_PIN(31, "OSE_UART1_CTSB"),
PINCTRL_PIN(32, "PCIE_LNK_DOWN"),
PINCTRL_PIN(33, "SD_PWR_EN_B"),
PINCTRL_PIN(34, "CPU_C10_GATEB"),
PINCTRL_PIN(35, "GPPC_H_19"),
PINCTRL_PIN(36, "OSE_PWM7"),
PINCTRL_PIN(37, "OSE_HSUART1_DE"),
PINCTRL_PIN(38, "OSE_HSUART1_RE"),
PINCTRL_PIN(39, "OSE_HSUART1_EN"),
/* GPP_D */
PINCTRL_PIN(40, "OSE_QEPA_0"),
PINCTRL_PIN(41, "OSE_QEPB_0"),
PINCTRL_PIN(42, "OSE_QEPI_0"),
PINCTRL_PIN(43, "OSE_PWM6"),
PINCTRL_PIN(44, "OSE_PWM2"),
PINCTRL_PIN(45, "SRCCLKREQB_0"),
PINCTRL_PIN(46, "SRCCLKREQB_1"),
PINCTRL_PIN(47, "SRCCLKREQB_2"),
PINCTRL_PIN(48, "SRCCLKREQB_3"),
PINCTRL_PIN(49, "OSE_SPI0_CSB"),
PINCTRL_PIN(50, "OSE_SPI0_SCLK"),
PINCTRL_PIN(51, "OSE_SPI0_MISO"),
PINCTRL_PIN(52, "OSE_SPI0_MOSI"),
PINCTRL_PIN(53, "OSE_QEPA_1"),
PINCTRL_PIN(54, "OSE_QEPB_1"),
PINCTRL_PIN(55, "OSE_PWM3"),
PINCTRL_PIN(56, "OSE_QEPI_1"),
PINCTRL_PIN(57, "OSE_PWM4"),
PINCTRL_PIN(58, "OSE_PWM5"),
PINCTRL_PIN(59, "I2S_MCLK1_OUT"),
PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"),
/* GPP_U */
PINCTRL_PIN(61, "RGMII2_INT"),
PINCTRL_PIN(62, "RGMII2_RESETB"),
PINCTRL_PIN(63, "RGMII2_PPS"),
PINCTRL_PIN(64, "RGMII2_AUXTS"),
PINCTRL_PIN(65, "ISI_SPIM_CS"),
PINCTRL_PIN(66, "ISI_SPIM_SCLK"),
PINCTRL_PIN(67, "ISI_SPIM_MISO"),
PINCTRL_PIN(68, "OSE_QEPA_3"),
PINCTRL_PIN(69, "ISI_SPIS_CS"),
PINCTRL_PIN(70, "ISI_SPIS_SCLK"),
PINCTRL_PIN(71, "ISI_SPIS_MISO"),
PINCTRL_PIN(72, "OSE_QEPB_3"),
PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"),
PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"),
PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"),
PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"),
PINCTRL_PIN(77, "ISI_OKNOK_0"),
PINCTRL_PIN(78, "ISI_OKNOK_1"),
PINCTRL_PIN(79, "ISI_ALERT"),
PINCTRL_PIN(80, "OSE_QEPI_3"),
PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"),
PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"),
PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"),
PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"),
/* vGPIO */
PINCTRL_PIN(85, "CNV_BTEN"),
PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(87, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(88, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(89, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(92, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(93, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(96, "vUART0_TXD"),
PINCTRL_PIN(97, "vUART0_RXD"),
PINCTRL_PIN(98, "vUART0_CTS_B"),
PINCTRL_PIN(99, "vUART0_RTS_B"),
PINCTRL_PIN(100, "vOSE_UART0_TXD"),
PINCTRL_PIN(101, "vOSE_UART0_RXD"),
PINCTRL_PIN(102, "vOSE_UART0_CTS_B"),
PINCTRL_PIN(103, "vOSE_UART0_RTS_B"),
PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(108, "vI2S2_SCLK"),
PINCTRL_PIN(109, "vI2S2_SFRM"),
PINCTRL_PIN(110, "vI2S2_TXD"),
PINCTRL_PIN(111, "vI2S2_RXD"),
PINCTRL_PIN(112, "vSD3_CD_B"),
};
static const struct intel_padgroup ehl_community1_gpps[] = {
EHL_GPP(0, 0, 15), /* GPP_V */
EHL_GPP(1, 16, 39), /* GPP_H */
EHL_GPP(2, 40, 60), /* GPP_D */
EHL_GPP(3, 61, 84), /* GPP_U */
EHL_GPP(4, 85, 112), /* vGPIO */
};
static const struct intel_community ehl_community1[] = {
EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
.uid = "1",
.pins = ehl_community1_pins,
.npins = ARRAY_SIZE(ehl_community1_pins),
.communities = ehl_community1,
.ncommunities = ARRAY_SIZE(ehl_community1),
};
static const struct pinctrl_pin_desc ehl_community3_pins[] = {
/* CPU */
PINCTRL_PIN(0, "HDACPU_SDI"),
PINCTRL_PIN(1, "HDACPU_SDO"),
PINCTRL_PIN(2, "HDACPU_BCLK"),
PINCTRL_PIN(3, "PM_SYNC"),
PINCTRL_PIN(4, "PECI"),
PINCTRL_PIN(5, "CPUPWRGD"),
PINCTRL_PIN(6, "THRMTRIPB"),
PINCTRL_PIN(7, "PLTRST_CPUB"),
PINCTRL_PIN(8, "PM_DOWN"),
PINCTRL_PIN(9, "TRIGGER_IN"),
PINCTRL_PIN(10, "TRIGGER_OUT"),
PINCTRL_PIN(11, "UFS_RESETB"),
PINCTRL_PIN(12, "CLKOUT_CPURTC"),
PINCTRL_PIN(13, "VCCST_OVERRIDE"),
PINCTRL_PIN(14, "C10_WAKE"),
PINCTRL_PIN(15, "PROCHOTB"),
PINCTRL_PIN(16, "CATERRB"),
/* GPP_S */
PINCTRL_PIN(17, "UFS_REF_CLK_0"),
PINCTRL_PIN(18, "UFS_REF_CLK_1"),
/* GPP_A */
PINCTRL_PIN(19, "RGMII0_TXDATA_3"),
PINCTRL_PIN(20, "RGMII0_TXDATA_2"),
PINCTRL_PIN(21, "RGMII0_TXDATA_1"),
PINCTRL_PIN(22, "RGMII0_TXDATA_0"),
PINCTRL_PIN(23, "RGMII0_TXCLK"),
PINCTRL_PIN(24, "RGMII0_TXCTL"),
PINCTRL_PIN(25, "RGMII0_RXCLK"),
PINCTRL_PIN(26, "RGMII0_RXDATA_3"),
PINCTRL_PIN(27, "RGMII0_RXDATA_2"),
PINCTRL_PIN(28, "RGMII0_RXDATA_1"),
PINCTRL_PIN(29, "RGMII0_RXDATA_0"),
PINCTRL_PIN(30, "RGMII1_TXDATA_3"),
PINCTRL_PIN(31, "RGMII1_TXDATA_2"),
PINCTRL_PIN(32, "RGMII1_TXDATA_1"),
PINCTRL_PIN(33, "RGMII1_TXDATA_0"),
PINCTRL_PIN(34, "RGMII1_TXCLK"),
PINCTRL_PIN(35, "RGMII1_TXCTL"),
PINCTRL_PIN(36, "RGMII1_RXCLK"),
PINCTRL_PIN(37, "RGMII1_RXCTL"),
PINCTRL_PIN(38, "RGMII1_RXDATA_3"),
PINCTRL_PIN(39, "RGMII1_RXDATA_2"),
PINCTRL_PIN(40, "RGMII1_RXDATA_1"),
PINCTRL_PIN(41, "RGMII1_RXDATA_0"),
PINCTRL_PIN(42, "RGMII0_RXCTL"),
/* vGPIO_3 */
PINCTRL_PIN(43, "ESPI_USB_OCB_0"),
PINCTRL_PIN(44, "ESPI_USB_OCB_1"),
PINCTRL_PIN(45, "ESPI_USB_OCB_2"),
PINCTRL_PIN(46, "ESPI_USB_OCB_3"),
};
static const struct intel_padgroup ehl_community3_gpps[] = {
EHL_GPP(0, 0, 16), /* CPU */
EHL_GPP(1, 17, 18), /* GPP_S */
EHL_GPP(2, 19, 42), /* GPP_A */
EHL_GPP(3, 43, 46), /* vGPIO_3 */
};
static const struct intel_community ehl_community3[] = {
EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
.uid = "3",
.pins = ehl_community3_pins,
.npins = ARRAY_SIZE(ehl_community3_pins),
.communities = ehl_community3,
.ncommunities = ARRAY_SIZE(ehl_community3),
};
static const struct pinctrl_pin_desc ehl_community4_pins[] = {
/* GPP_C */
PINCTRL_PIN(0, "SMBCLK"),
PINCTRL_PIN(1, "SMBDATA"),
PINCTRL_PIN(2, "OSE_PWM0"),
PINCTRL_PIN(3, "RGMII0_MDC"),
PINCTRL_PIN(4, "RGMII0_MDIO"),
PINCTRL_PIN(5, "OSE_PWM1"),
PINCTRL_PIN(6, "RGMII1_MDC"),
PINCTRL_PIN(7, "RGMII1_MDIO"),
PINCTRL_PIN(8, "OSE_TGPIO4"),
PINCTRL_PIN(9, "OSE_HSUART0_EN"),
PINCTRL_PIN(10, "OSE_TGPIO5"),
PINCTRL_PIN(11, "OSE_HSUART0_RE"),
PINCTRL_PIN(12, "OSE_UART0_RXD"),
PINCTRL_PIN(13, "OSE_UART0_TXD"),
PINCTRL_PIN(14, "OSE_UART0_RTSB"),
PINCTRL_PIN(15, "OSE_UART0_CTSB"),
PINCTRL_PIN(16, "RGMII2_MDIO"),
PINCTRL_PIN(17, "RGMII2_MDC"),
PINCTRL_PIN(18, "OSE_I2C4_SDAT"),
PINCTRL_PIN(19, "OSE_I2C4_SCLK"),
PINCTRL_PIN(20, "OSE_UART4_RXD"),
PINCTRL_PIN(21, "OSE_UART4_TXD"),
PINCTRL_PIN(22, "OSE_UART4_RTSB"),
PINCTRL_PIN(23, "OSE_UART4_CTSB"),
/* GPP_F */
PINCTRL_PIN(24, "CNV_BRI_DT"),
PINCTRL_PIN(25, "CNV_BRI_RSP"),
PINCTRL_PIN(26, "CNV_RGI_DT"),
PINCTRL_PIN(27, "CNV_RGI_RSP"),
PINCTRL_PIN(28, "CNV_RF_RESET_B"),
PINCTRL_PIN(29, "EMMC_HIP_MON"),
PINCTRL_PIN(30, "CNV_PA_BLANKING"),
PINCTRL_PIN(31, "OSE_I2S1_SCLK"),
PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
PINCTRL_PIN(33, "BOOTMPC"),
PINCTRL_PIN(34, "OSE_I2S1_SFRM"),
PINCTRL_PIN(35, "GPPC_F_11"),
PINCTRL_PIN(36, "GSXDOUT"),
PINCTRL_PIN(37, "GSXSLOAD"),
PINCTRL_PIN(38, "GSXDIN"),
PINCTRL_PIN(39, "GSXSRESETB"),
PINCTRL_PIN(40, "GSXCLK"),
PINCTRL_PIN(41, "GPPC_F_17"),
PINCTRL_PIN(42, "OSE_I2S1_TXD"),
PINCTRL_PIN(43, "OSE_I2S1_RXD"),
PINCTRL_PIN(44, "EXT_PWR_GATEB"),
PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
PINCTRL_PIN(46, "VNN_CTRL"),
PINCTRL_PIN(47, "V1P05_CTRL"),
PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
/* HVCMOS */
PINCTRL_PIN(49, "L_BKLTEN"),
PINCTRL_PIN(50, "L_BKLTCTL"),
PINCTRL_PIN(51, "L_VDDEN"),
PINCTRL_PIN(52, "SYS_PWROK"),
PINCTRL_PIN(53, "SYS_RESETB"),
PINCTRL_PIN(54, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(55, "SATA_LEDB"),
PINCTRL_PIN(56, "GPPC_E_1"),
PINCTRL_PIN(57, "GPPC_E_2"),
PINCTRL_PIN(58, "DDSP_HPD_B"),
PINCTRL_PIN(59, "SATA_DEVSLP_0"),
PINCTRL_PIN(60, "DDPB_CTRLDATA"),
PINCTRL_PIN(61, "GPPC_E_6"),
PINCTRL_PIN(62, "DDPB_CTRLCLK"),
PINCTRL_PIN(63, "GPPC_E_8"),
PINCTRL_PIN(64, "USB2_OCB_0"),
PINCTRL_PIN(65, "GPPC_E_10"),
PINCTRL_PIN(66, "GPPC_E_11"),
PINCTRL_PIN(67, "GPPC_E_12"),
PINCTRL_PIN(68, "GPPC_E_13"),
PINCTRL_PIN(69, "DDSP_HPD_A"),
PINCTRL_PIN(70, "OSE_I2S0_RXD"),
PINCTRL_PIN(71, "OSE_I2S0_TXD"),
PINCTRL_PIN(72, "DDSP_HPD_C"),
PINCTRL_PIN(73, "DDPA_CTRLDATA"),
PINCTRL_PIN(74, "DDPA_CTRLCLK"),
PINCTRL_PIN(75, "OSE_I2S0_SCLK"),
PINCTRL_PIN(76, "OSE_I2S0_SFRM"),
PINCTRL_PIN(77, "DDPC_CTRLDATA"),
PINCTRL_PIN(78, "DDPC_CTRLCLK"),
PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
};
static const struct intel_padgroup ehl_community4_gpps[] = {
EHL_GPP(0, 0, 23), /* GPP_C */
EHL_GPP(1, 24, 48), /* GPP_F */
EHL_GPP(2, 49, 54), /* HVCMOS */
EHL_GPP(3, 55, 79), /* GPP_E */
};
static const struct intel_community ehl_community4[] = {
EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
.uid = "4",
.pins = ehl_community4_pins,
.npins = ARRAY_SIZE(ehl_community4_pins),
.communities = ehl_community4,
.ncommunities = ARRAY_SIZE(ehl_community4),
};
static const struct pinctrl_pin_desc ehl_community5_pins[] = {
/* GPP_R */
PINCTRL_PIN(0, "HDA_BCLK"),
PINCTRL_PIN(1, "HDA_SYNC"),
PINCTRL_PIN(2, "HDA_SDO"),
PINCTRL_PIN(3, "HDA_SDI_0"),
PINCTRL_PIN(4, "HDA_RSTB"),
PINCTRL_PIN(5, "HDA_SDI_1"),
PINCTRL_PIN(6, "GPP_R_6"),
PINCTRL_PIN(7, "GPP_R_7"),
};
static const struct intel_padgroup ehl_community5_gpps[] = {
EHL_GPP(0, 0, 7), /* GPP_R */
};
static const struct intel_community ehl_community5[] = {
EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps),
};
static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
.uid = "5",
.pins = ehl_community5_pins,
.npins = ARRAY_SIZE(ehl_community5_pins),
.communities = ehl_community5,
.ncommunities = ARRAY_SIZE(ehl_community5),
};
static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
&ehl_community0_soc_data,
&ehl_community1_soc_data,
&ehl_community3_soc_data,
&ehl_community4_soc_data,
&ehl_community5_soc_data,
NULL
};
static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
{ "INTC1020", (kernel_ulong_t)ehl_soc_data_array },
{ }
};
MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
static struct platform_driver ehl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "elkhartlake-pinctrl",
.acpi_match_table = ehl_pinctrl_acpi_match,
.pm = &ehl_pinctrl_pm_ops,
},
};
module_platform_driver(ehl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-elkhartlake.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Lakefield PCH pinctrl/GPIO driver
*
* Copyright (C) 2020, Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define LKF_PAD_OWN 0x020
#define LKF_PADCFGLOCK 0x070
#define LKF_HOSTSW_OWN 0x090
#define LKF_GPI_IS 0x100
#define LKF_GPI_IE 0x110
#define LKF_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define LKF_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, LKF)
/* Lakefield */
static const struct pinctrl_pin_desc lkf_pins[] = {
/* EAST */
PINCTRL_PIN(0, "MDSI_A_TE0"),
PINCTRL_PIN(1, "MDSI_A_TE1"),
PINCTRL_PIN(2, "PANEL0_AVDD_EN"),
PINCTRL_PIN(3, "PANEL0_BKLTEN"),
PINCTRL_PIN(4, "PANEL0_BKLTCTL"),
PINCTRL_PIN(5, "PANEL1_AVDD_EN"),
PINCTRL_PIN(6, "PANEL1_BKLTEN"),
PINCTRL_PIN(7, "PANEL1_BKLTCTL"),
PINCTRL_PIN(8, "THC0_SPI1_IO_0"),
PINCTRL_PIN(9, "THC0_SPI1_IO_1"),
PINCTRL_PIN(10, "THC0_SPI1_IO_2"),
PINCTRL_PIN(11, "THC0_SPI1_IO_3"),
PINCTRL_PIN(12, "THC0_SPI1_CSB"),
PINCTRL_PIN(13, "THC0_SPI1_CLK"),
PINCTRL_PIN(14, "THC0_SPI1_RESETB"),
PINCTRL_PIN(15, "THC0_SPI1_CLK_FB"),
PINCTRL_PIN(16, "SPI_TOUCH_CLK_FB"),
PINCTRL_PIN(17, "THC1_SPI2_IO_0"),
PINCTRL_PIN(18, "THC1_SPI2_IO_1"),
PINCTRL_PIN(19, "THC1_SPI2_IO_2"),
PINCTRL_PIN(20, "THC1_SPI2_IO_3"),
PINCTRL_PIN(21, "THC1_SPI2_CSB"),
PINCTRL_PIN(22, "THC1_SPI2_CLK"),
PINCTRL_PIN(23, "THC1_SPI2_RESETB"),
PINCTRL_PIN(24, "THC1_SPI2_CLK_FB"),
PINCTRL_PIN(25, "eSPI_IO_0"),
PINCTRL_PIN(26, "eSPI_IO_1"),
PINCTRL_PIN(27, "eSPI_IO_2"),
PINCTRL_PIN(28, "eSPI_IO_3"),
PINCTRL_PIN(29, "eSPI_CSB"),
PINCTRL_PIN(30, "eSPI_RESETB"),
PINCTRL_PIN(31, "eSPI_CLK"),
PINCTRL_PIN(32, "eSPI_CLK_FB"),
PINCTRL_PIN(33, "FAST_SPI0_IO_0"),
PINCTRL_PIN(34, "FAST_SPI0_IO_1"),
PINCTRL_PIN(35, "FAST_SPI0_IO_2"),
PINCTRL_PIN(36, "FAST_SPI0_IO_3"),
PINCTRL_PIN(37, "FAST_SPI0_CSB_0"),
PINCTRL_PIN(38, "FAST_SPI0_CSB_2"),
PINCTRL_PIN(39, "FAST_SPI0_CLK"),
PINCTRL_PIN(40, "FAST_SPI_CLK_FB"),
PINCTRL_PIN(41, "FAST_SPI0_CSB_1"),
PINCTRL_PIN(42, "ISH_GP_12"),
PINCTRL_PIN(43, "THC0_SPI1_INTB"),
PINCTRL_PIN(44, "THC1_SPI2_INTB"),
PINCTRL_PIN(45, "PANEL0_AVEE_EN"),
PINCTRL_PIN(46, "PANEL0_VIO_EN"),
PINCTRL_PIN(47, "PANEL1_AVEE_EN"),
PINCTRL_PIN(48, "PANEL1_VIO_EN"),
PINCTRL_PIN(49, "PANEL0_RESET"),
PINCTRL_PIN(50, "PANEL1_RESET"),
PINCTRL_PIN(51, "ISH_GP_15"),
PINCTRL_PIN(52, "ISH_GP_16"),
PINCTRL_PIN(53, "ISH_GP_17"),
PINCTRL_PIN(54, "ISH_GP_18"),
PINCTRL_PIN(55, "ISH_GP_19"),
PINCTRL_PIN(56, "ISH_GP_20"),
PINCTRL_PIN(57, "ISH_GP_21"),
PINCTRL_PIN(58, "ISH_GP_22"),
PINCTRL_PIN(59, "ISH_GP_23"),
/* NORTHWEST */
PINCTRL_PIN(60, "MCSI_GPIO_0"),
PINCTRL_PIN(61, "MCSI_GPIO_1"),
PINCTRL_PIN(62, "MCSI_GPIO_2"),
PINCTRL_PIN(63, "MCSI_GPIO_3"),
PINCTRL_PIN(64, "LPSS_I2C0_SDA"),
PINCTRL_PIN(65, "LPSS_I2C0_SCL"),
PINCTRL_PIN(66, "LPSS_I2C1_SDA"),
PINCTRL_PIN(67, "LPSS_I2C1_SCL"),
PINCTRL_PIN(68, "LPSS_I2C2_SDA"),
PINCTRL_PIN(69, "LPSS_I2C2_SCL"),
PINCTRL_PIN(70, "LPSS_I2C3_SDA"),
PINCTRL_PIN(71, "LPSS_I2C3_SCL"),
PINCTRL_PIN(72, "LPSS_I2C4_SDA"),
PINCTRL_PIN(73, "LPSS_I2C4_SCL"),
PINCTRL_PIN(74, "LPSS_I2C5_SDA"),
PINCTRL_PIN(75, "LPSS_I2C5_SCL"),
PINCTRL_PIN(76, "LPSS_I3C0_SDA"),
PINCTRL_PIN(77, "LPSS_I3C0_SCL"),
PINCTRL_PIN(78, "LPSS_I3C0_SCL_FB"),
PINCTRL_PIN(79, "LPSS_I3C1_SDA"),
PINCTRL_PIN(80, "LPSS_I3C1_SCL"),
PINCTRL_PIN(81, "LPSS_I3C1_SCL_FB"),
PINCTRL_PIN(82, "ISH_I2C0_SDA"),
PINCTRL_PIN(83, "ISH_I2C0_SCL"),
PINCTRL_PIN(84, "ISH_I2C1_SCL"),
PINCTRL_PIN(85, "ISH_I2C1_SDA"),
PINCTRL_PIN(86, "DBG_PMODE"),
PINCTRL_PIN(87, "BJTAG_TCK"),
PINCTRL_PIN(88, "BJTAG_TDI"),
PINCTRL_PIN(89, "BJTAGX"),
PINCTRL_PIN(90, "BPREQ_B"),
PINCTRL_PIN(91, "BJTAG_TMS"),
PINCTRL_PIN(92, "BPRDY_B"),
PINCTRL_PIN(93, "BJTAG_TDO"),
PINCTRL_PIN(94, "BJTAG_TRST_B_0"),
PINCTRL_PIN(95, "ISH_I3C0_SDA"),
PINCTRL_PIN(96, "ISH_I3C0_SCL"),
PINCTRL_PIN(97, "ISH_I3C0_SCL_FB"),
PINCTRL_PIN(98, "AVS_I2S_BCLK_0"),
PINCTRL_PIN(99, "AVS_I2S_MCLK_0"),
PINCTRL_PIN(100, "AVS_I2S_SFRM_0"),
PINCTRL_PIN(101, "AVS_I2S_RXD_0"),
PINCTRL_PIN(102, "AVS_I2S_TXD_0"),
PINCTRL_PIN(103, "AVS_I2S_BCLK_1"),
PINCTRL_PIN(104, "AVS_I2S_SFRM_1"),
PINCTRL_PIN(105, "AVS_I2S_RXD_1"),
PINCTRL_PIN(106, "AVS_I2S_TXD_1"),
PINCTRL_PIN(107, "AVS_I2S_BCLK_2"),
PINCTRL_PIN(108, "AVS_I2S_SFRM_2"),
PINCTRL_PIN(109, "AVS_I2S_RXD_2"),
PINCTRL_PIN(110, "AVS_I2S_TXD_2"),
PINCTRL_PIN(111, "AVS_I2S_BCLK_3"),
PINCTRL_PIN(112, "AVS_I2S_SFRM_3"),
PINCTRL_PIN(113, "AVS_I2S_RXD_3"),
PINCTRL_PIN(114, "AVS_I2S_TXD_3"),
PINCTRL_PIN(115, "AVS_I2S_BCLK_4"),
PINCTRL_PIN(116, "AVS_I2S_SFRM_4"),
PINCTRL_PIN(117, "AVS_I2S_RXD_4"),
PINCTRL_PIN(118, "AVS_I2S_TXD_4"),
PINCTRL_PIN(119, "AVS_I2S_SFRM_5"),
PINCTRL_PIN(120, "AVS_I2S_RXD_5"),
PINCTRL_PIN(121, "AVS_I2S_TXD_5"),
PINCTRL_PIN(122, "AVS_I2S_BCLK_5"),
PINCTRL_PIN(123, "AVS_SNDW_CLK_0"),
PINCTRL_PIN(124, "AVS_SNDW_DATA_0"),
PINCTRL_PIN(125, "AVS_SNDW_CLK_1"),
PINCTRL_PIN(126, "AVS_SNDW_DATA_1"),
PINCTRL_PIN(127, "AVS_SNDW_CLK_2"),
PINCTRL_PIN(128, "AVS_SNDW_DATA_2"),
PINCTRL_PIN(129, "AVS_SNDW_CLK_3"),
PINCTRL_PIN(130, "AVS_SNDW_DATA_3"),
PINCTRL_PIN(131, "VISA_PTI_CH0_D0_internal"),
PINCTRL_PIN(132, "VISA_PTI_CH0_D1_internal"),
PINCTRL_PIN(133, "VISA_PTI_CH0_D2_internal"),
PINCTRL_PIN(134, "VISA_PTI_CH0_D3_internal"),
PINCTRL_PIN(135, "VISA_PTI_CH0_D4_internal"),
PINCTRL_PIN(136, "VISA_PTI_CH0_D5_internal"),
PINCTRL_PIN(137, "VISA_PTI_CH0_D6_internal"),
PINCTRL_PIN(138, "VISA_PTI_CH0_D7_internal"),
PINCTRL_PIN(139, "VISA_PTI_CH0_CLK_internal"),
PINCTRL_PIN(140, "VISA_PTI_CH1_D0_internal"),
PINCTRL_PIN(141, "VISA_PTI_CH1_D1_internal"),
PINCTRL_PIN(142, "VISA_PTI_CH1_D2_internal"),
PINCTRL_PIN(143, "VISA_PTI_CH1_D3_internal"),
PINCTRL_PIN(144, "VISA_PTI_CH1_D4_internal"),
PINCTRL_PIN(145, "VISA_PTI_CH1_D5_internal"),
PINCTRL_PIN(146, "VISA_PTI_CH1_D6_internal"),
PINCTRL_PIN(147, "VISA_PTI_CH1_D7_internal"),
PINCTRL_PIN(148, "VISA_PTI_CH1_CLK_internal"),
/* WEST */
PINCTRL_PIN(149, "LPSS_UART0_TXD"),
PINCTRL_PIN(150, "LPSS_UART0_RXD"),
PINCTRL_PIN(151, "LPSS_UART0_RTS_B"),
PINCTRL_PIN(152, "LPSS_UART0_CTS_B"),
PINCTRL_PIN(153, "LPSS_UART1_RXD"),
PINCTRL_PIN(154, "LPSS_UART1_TXD"),
PINCTRL_PIN(155, "LPSS_UART1_RTS_B"),
PINCTRL_PIN(156, "LPSS_UART1_CTS_B"),
PINCTRL_PIN(157, "ISH_UART0_RXD"),
PINCTRL_PIN(158, "ISH_UART0_TXD"),
PINCTRL_PIN(159, "ISH_UART0_RTSB"),
PINCTRL_PIN(160, "ISH_UART0_CTSB"),
PINCTRL_PIN(161, "LPSS_SSP_0_CLK"),
PINCTRL_PIN(162, "LPSS_SSP_0_CLK_FB"),
PINCTRL_PIN(163, "LPSS_SSP_0_FS0"),
PINCTRL_PIN(164, "LPSS_SSP_0_FS1"),
PINCTRL_PIN(165, "LPSS_SSP_0_RXD"),
PINCTRL_PIN(166, "LPSS_SSP_0_TXD"),
PINCTRL_PIN(167, "ISH_UART1_RXD"),
PINCTRL_PIN(168, "ISH_UART1_TXD"),
PINCTRL_PIN(169, "ISH_UART1_RTSB"),
PINCTRL_PIN(170, "ISH_UART1_CTSB"),
PINCTRL_PIN(171, "LPSS_SSP_1_FS0"),
PINCTRL_PIN(172, "LPSS_SSP_1_FS1"),
PINCTRL_PIN(173, "LPSS_SSP_1_CLK"),
PINCTRL_PIN(174, "LPSS_SSP_1_CLK_FB"),
PINCTRL_PIN(175, "LPSS_SSP_1_RXD"),
PINCTRL_PIN(176, "LPSS_SSP_1_TXD"),
PINCTRL_PIN(177, "LPSS_SSP_2_CLK"),
PINCTRL_PIN(178, "LPSS_SSP_2_CLK_FB"),
PINCTRL_PIN(179, "LPSS_SSP_2_FS0"),
PINCTRL_PIN(180, "LPSS_SSP_2_FS1"),
PINCTRL_PIN(181, "LPSS_SSP_2_RXD"),
PINCTRL_PIN(182, "LPSS_SSP_2_TXD"),
PINCTRL_PIN(183, "ISH_SPI0_CSB0"),
PINCTRL_PIN(184, "ISH_SPI0_CSB1"),
PINCTRL_PIN(185, "ISH_SPI0_CLK"),
PINCTRL_PIN(186, "ISH_SPI0_MISO"),
PINCTRL_PIN(187, "ISH_SPI0_MOSI"),
PINCTRL_PIN(188, "ISH_GP_0"),
PINCTRL_PIN(189, "ISH_GP_1"),
PINCTRL_PIN(190, "ISH_GP_2"),
PINCTRL_PIN(191, "ISH_GP_13"),
PINCTRL_PIN(192, "ISH_GP_3"),
PINCTRL_PIN(193, "ISH_GP_4"),
PINCTRL_PIN(194, "ISH_GP_5"),
PINCTRL_PIN(195, "ISH_GP_6"),
PINCTRL_PIN(196, "ISH_GP_7"),
PINCTRL_PIN(197, "ISH_GP_8"),
PINCTRL_PIN(198, "ISH_GP_9"),
PINCTRL_PIN(199, "ISH_GP_10"),
PINCTRL_PIN(200, "ISH_GP_11"),
PINCTRL_PIN(201, "ISH_GP_14"),
PINCTRL_PIN(202, "ISH_GP_15"),
PINCTRL_PIN(203, "ISH_GP_22"),
PINCTRL_PIN(204, "ISH_GP_12"),
PINCTRL_PIN(205, "ISH_GP_30_USB_OC"),
PINCTRL_PIN(206, "LPDDRx_RESET0_n"),
PINCTRL_PIN(207, "UFS_RESET_B"),
PINCTRL_PIN(208, "UFS_REFCLK0"),
PINCTRL_PIN(209, "EMMC_SD_CLK"),
PINCTRL_PIN(210, "EMMC_SD_D0"),
PINCTRL_PIN(211, "EMMC_SD_D1"),
PINCTRL_PIN(212, "EMMC_SD_D2"),
PINCTRL_PIN(213, "EMMC_SD_D3"),
PINCTRL_PIN(214, "EMMC_D4"),
PINCTRL_PIN(215, "EMMC_D5"),
PINCTRL_PIN(216, "EMMC_D6"),
PINCTRL_PIN(217, "EMMC_D7"),
PINCTRL_PIN(218, "EMMC_SD_CMD"),
PINCTRL_PIN(219, "EMMC_RCLK"),
PINCTRL_PIN(220, "SDCARD_CLK_FB"),
PINCTRL_PIN(221, "SD_Virtual_GPIO"),
PINCTRL_PIN(222, "OSC_CLK_OUT_NFC"),
PINCTRL_PIN(223, "OSC_CLK_OUT_CAM_0"),
PINCTRL_PIN(224, "OSC_CLK_OUT_CAM_1"),
PINCTRL_PIN(225, "OSC_CLK_OUT_CAM_2"),
PINCTRL_PIN(226, "OSC_CLK_OUT_CAM_3"),
PINCTRL_PIN(227, "PCIe_LINKDOWN"),
PINCTRL_PIN(228, "NFC_CLK_REQ"),
PINCTRL_PIN(229, "PCIE_CLKREQ_N_DEV2"),
PINCTRL_PIN(230, "PCIE_CLKREQ_N_DEV3"),
PINCTRL_PIN(231, "PCIE_CLKREQ_N_DEV4"),
PINCTRL_PIN(232, "PCIE_CLKREQ_N_DEV1"),
PINCTRL_PIN(233, "PCIE_CLKREQ_N_DEV0"),
PINCTRL_PIN(234, "GMBUS_1_SCL"),
PINCTRL_PIN(235, "GMBUS_1_SDA"),
PINCTRL_PIN(236, "GMBUS_0_SCL"),
PINCTRL_PIN(237, "GMBUS_0_SDA"),
/* SOUTHEAST */
PINCTRL_PIN(238, "COMPUTE_PMIC_SVID_DATA"),
PINCTRL_PIN(239, "COMPUTE_PMIC_SVID_CLK"),
PINCTRL_PIN(240, "COMPUTE_PMIC_SVID_ALERT_B"),
PINCTRL_PIN(241, "ROP_PMIC_I2C_SCL"),
PINCTRL_PIN(242, "ROP_PMIC_I2C_SDA"),
PINCTRL_PIN(243, "ISH_TYPEC_I2C2_SDA"),
PINCTRL_PIN(244, "ISH_TYPEC_I2C2_SCL"),
PINCTRL_PIN(245, "COMPUTE_PMU_PROCHOT_B"),
PINCTRL_PIN(246, "PMU_CATERR_B"),
PINCTRL_PIN(247, "COMPUTE_PMIC_VR_READY"),
PINCTRL_PIN(248, "FORCE_FW_RELOAD"),
PINCTRL_PIN(249, "ROP_PMIC_IRQ_ISH_GPIO31_TPC_ALERT_B"),
PINCTRL_PIN(250, "ROP_PMIC_RESET_B"),
PINCTRL_PIN(251, "ROP_PMIC_STNBY_SLP_S0_B"),
PINCTRL_PIN(252, "ROP_PMIC_THERMTRIP_B"),
PINCTRL_PIN(253, "MODEM_CLKREQ"),
PINCTRL_PIN(254, "TPC0_BSSB_SBU1"),
PINCTRL_PIN(255, "TPC0_BSSB_SBU2"),
PINCTRL_PIN(256, "OSC_CLK_OUT_CAM_4"),
PINCTRL_PIN(257, "HPD1"),
PINCTRL_PIN(258, "HPD0"),
PINCTRL_PIN(259, "PMC_TIME_SYNC_0"),
PINCTRL_PIN(260, "PMC_TIME_SYNC_1"),
PINCTRL_PIN(261, "OSC_CLK_OUT_CAM_5"),
PINCTRL_PIN(262, "ISH_GP_20"),
PINCTRL_PIN(263, "ISH_GP_16"),
PINCTRL_PIN(264, "ISH_GP_17"),
PINCTRL_PIN(265, "ISH_GP_18"),
PINCTRL_PIN(266, "ISH_GP_19"),
};
static const struct intel_padgroup lkf_community0_gpps[] = {
LKF_GPP(0, 0, 31, 0), /* EAST_0 */
LKF_GPP(1, 32, 59, 32), /* EAST_1 */
};
static const struct intel_padgroup lkf_community1_gpps[] = {
LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */
LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */
LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */
};
static const struct intel_padgroup lkf_community2_gpps[] = {
LKF_GPP(0, 149, 180, 160), /* WEST_0 */
LKF_GPP(1, 181, 212, 192), /* WEST_1 */
LKF_GPP(2, 213, 237, 224), /* WEST_2 */
};
static const struct intel_padgroup lkf_community3_gpps[] = {
LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */
};
static const struct intel_community lkf_communities[] = {
LKF_COMMUNITY(0, 0, 59, lkf_community0_gpps), /* EAST */
LKF_COMMUNITY(1, 60, 148, lkf_community1_gpps), /* NORTHWEST */
LKF_COMMUNITY(2, 149, 237, lkf_community2_gpps), /* WEST */
LKF_COMMUNITY(3, 238, 266, lkf_community3_gpps), /* SOUTHEAST */
};
static const struct intel_pinctrl_soc_data lkf_soc_data = {
.pins = lkf_pins,
.npins = ARRAY_SIZE(lkf_pins),
.communities = lkf_communities,
.ncommunities = ARRAY_SIZE(lkf_communities),
};
static const struct acpi_device_id lkf_pinctrl_acpi_match[] = {
{ "INT34C4", (kernel_ulong_t)&lkf_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, lkf_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(lkf_pinctrl_pm_ops);
static struct platform_driver lkf_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "lakefield-pinctrl",
.acpi_match_table = lkf_pinctrl_acpi_match,
.pm = &lkf_pinctrl_pm_ops,
},
};
module_platform_driver(lkf_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_DESCRIPTION("Intel Lakefield PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-lakefield.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Ice Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2018, 2022 Intel Corporation
* Authors: Andy Shevchenko <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define ICL_LP_PAD_OWN 0x020
#define ICL_LP_PADCFGLOCK 0x080
#define ICL_LP_HOSTSW_OWN 0x0b0
#define ICL_LP_GPI_IS 0x100
#define ICL_LP_GPI_IE 0x110
#define ICL_N_PAD_OWN 0x020
#define ICL_N_PADCFGLOCK 0x080
#define ICL_N_HOSTSW_OWN 0x0b0
#define ICL_N_GPI_IS 0x100
#define ICL_N_GPI_IE 0x120
#define ICL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ICL_LP_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
#define ICL_N_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_N)
/* Ice Lake-LP */
static const struct pinctrl_pin_desc icllp_pins[] = {
/* GPP_G */
PINCTRL_PIN(0, "SD3_CMD"),
PINCTRL_PIN(1, "SD3_D0"),
PINCTRL_PIN(2, "SD3_D1"),
PINCTRL_PIN(3, "SD3_D2"),
PINCTRL_PIN(4, "SD3_D3"),
PINCTRL_PIN(5, "SD3_CDB"),
PINCTRL_PIN(6, "SD3_CLK"),
PINCTRL_PIN(7, "SD3_WP"),
/* GPP_B */
PINCTRL_PIN(8, "CORE_VID_0"),
PINCTRL_PIN(9, "CORE_VID_1"),
PINCTRL_PIN(10, "VRALERTB"),
PINCTRL_PIN(11, "CPU_GP_2"),
PINCTRL_PIN(12, "CPU_GP_3"),
PINCTRL_PIN(13, "ISH_I2C0_SDA"),
PINCTRL_PIN(14, "ISH_I2C0_SCL"),
PINCTRL_PIN(15, "ISH_I2C1_SDA"),
PINCTRL_PIN(16, "ISH_I2C1_SCL"),
PINCTRL_PIN(17, "I2C5_SDA"),
PINCTRL_PIN(18, "I2C5_SCL"),
PINCTRL_PIN(19, "PMCALERTB"),
PINCTRL_PIN(20, "SLP_S0B"),
PINCTRL_PIN(21, "PLTRSTB"),
PINCTRL_PIN(22, "SPKR"),
PINCTRL_PIN(23, "GSPI0_CS0B"),
PINCTRL_PIN(24, "GSPI0_CLK"),
PINCTRL_PIN(25, "GSPI0_MISO"),
PINCTRL_PIN(26, "GSPI0_MOSI"),
PINCTRL_PIN(27, "GSPI1_CS0B"),
PINCTRL_PIN(28, "GSPI1_CLK"),
PINCTRL_PIN(29, "GSPI1_MISO"),
PINCTRL_PIN(30, "GSPI1_MOSI"),
PINCTRL_PIN(31, "SML1ALERTB"),
PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
/* GPP_A */
PINCTRL_PIN(34, "ESPI_IO_0"),
PINCTRL_PIN(35, "ESPI_IO_1"),
PINCTRL_PIN(36, "ESPI_IO_2"),
PINCTRL_PIN(37, "ESPI_IO_3"),
PINCTRL_PIN(38, "ESPI_CSB"),
PINCTRL_PIN(39, "ESPI_CLK"),
PINCTRL_PIN(40, "ESPI_RESETB"),
PINCTRL_PIN(41, "I2S2_SCLK"),
PINCTRL_PIN(42, "I2S2_SFRM"),
PINCTRL_PIN(43, "I2S2_TXD"),
PINCTRL_PIN(44, "I2S2_RXD"),
PINCTRL_PIN(45, "SATA_DEVSLP_2"),
PINCTRL_PIN(46, "SATAXPCIE_1"),
PINCTRL_PIN(47, "SATAXPCIE_2"),
PINCTRL_PIN(48, "USB2_OCB_1"),
PINCTRL_PIN(49, "USB2_OCB_2"),
PINCTRL_PIN(50, "USB2_OCB_3"),
PINCTRL_PIN(51, "DDSP_HPD_C"),
PINCTRL_PIN(52, "DDSP_HPD_B"),
PINCTRL_PIN(53, "DDSP_HPD_1"),
PINCTRL_PIN(54, "DDSP_HPD_2"),
PINCTRL_PIN(55, "I2S5_TXD"),
PINCTRL_PIN(56, "I2S5_RXD"),
PINCTRL_PIN(57, "I2S1_SCLK"),
PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
/* GPP_H */
PINCTRL_PIN(59, "SD_1P8_SEL"),
PINCTRL_PIN(60, "SD_PWR_EN_B"),
PINCTRL_PIN(61, "GPPC_H_2"),
PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(63, "I2C2_SDA"),
PINCTRL_PIN(64, "I2C2_SCL"),
PINCTRL_PIN(65, "I2C3_SDA"),
PINCTRL_PIN(66, "I2C3_SCL"),
PINCTRL_PIN(67, "I2C4_SDA"),
PINCTRL_PIN(68, "I2C4_SCL"),
PINCTRL_PIN(69, "SRCCLKREQB_4"),
PINCTRL_PIN(70, "SRCCLKREQB_5"),
PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
PINCTRL_PIN(75, "DDPB_CTRLCLK"),
PINCTRL_PIN(76, "DDPB_CTRLDATA"),
PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
PINCTRL_PIN(78, "TIME_SYNC_0"),
PINCTRL_PIN(79, "IMGCLKOUT_1"),
PINCTRL_PIN(80, "IMGCLKOUT_2"),
PINCTRL_PIN(81, "IMGCLKOUT_3"),
PINCTRL_PIN(82, "IMGCLKOUT_4"),
/* GPP_D */
PINCTRL_PIN(83, "ISH_GP_0"),
PINCTRL_PIN(84, "ISH_GP_1"),
PINCTRL_PIN(85, "ISH_GP_2"),
PINCTRL_PIN(86, "ISH_GP_3"),
PINCTRL_PIN(87, "IMGCLKOUT_0"),
PINCTRL_PIN(88, "SRCCLKREQB_0"),
PINCTRL_PIN(89, "SRCCLKREQB_1"),
PINCTRL_PIN(90, "SRCCLKREQB_2"),
PINCTRL_PIN(91, "SRCCLKREQB_3"),
PINCTRL_PIN(92, "ISH_SPI_CSB"),
PINCTRL_PIN(93, "ISH_SPI_CLK"),
PINCTRL_PIN(94, "ISH_SPI_MISO"),
PINCTRL_PIN(95, "ISH_SPI_MOSI"),
PINCTRL_PIN(96, "ISH_UART0_RXD"),
PINCTRL_PIN(97, "ISH_UART0_TXD"),
PINCTRL_PIN(98, "ISH_UART0_RTSB"),
PINCTRL_PIN(99, "ISH_UART0_CTSB"),
PINCTRL_PIN(100, "ISH_GP_4"),
PINCTRL_PIN(101, "ISH_GP_5"),
PINCTRL_PIN(102, "I2S_MCLK"),
PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
/* GPP_F */
PINCTRL_PIN(104, "CNV_BRI_DT"),
PINCTRL_PIN(105, "CNV_BRI_RSP"),
PINCTRL_PIN(106, "CNV_RGI_DT"),
PINCTRL_PIN(107, "CNV_RGI_RSP"),
PINCTRL_PIN(108, "CNV_RF_RESET_B"),
PINCTRL_PIN(109, "EMMC_HIP_MON"),
PINCTRL_PIN(110, "CNV_PA_BLANKING"),
PINCTRL_PIN(111, "EMMC_CMD"),
PINCTRL_PIN(112, "EMMC_DATA0"),
PINCTRL_PIN(113, "EMMC_DATA1"),
PINCTRL_PIN(114, "EMMC_DATA2"),
PINCTRL_PIN(115, "EMMC_DATA3"),
PINCTRL_PIN(116, "EMMC_DATA4"),
PINCTRL_PIN(117, "EMMC_DATA5"),
PINCTRL_PIN(118, "EMMC_DATA6"),
PINCTRL_PIN(119, "EMMC_DATA7"),
PINCTRL_PIN(120, "EMMC_RCLK"),
PINCTRL_PIN(121, "EMMC_CLK"),
PINCTRL_PIN(122, "EMMC_RESETB"),
PINCTRL_PIN(123, "A4WP_PRESENT"),
/* vGPIO */
PINCTRL_PIN(124, "CNV_BTEN"),
PINCTRL_PIN(125, "CNV_WCEN"),
PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(136, "vUART0_TXD"),
PINCTRL_PIN(137, "vUART0_RXD"),
PINCTRL_PIN(138, "vUART0_CTS_B"),
PINCTRL_PIN(139, "vUART0_RTS_B"),
PINCTRL_PIN(140, "vISH_UART0_TXD"),
PINCTRL_PIN(141, "vISH_UART0_RXD"),
PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(148, "vI2S2_SCLK"),
PINCTRL_PIN(149, "vI2S2_SFRM"),
PINCTRL_PIN(150, "vI2S2_TXD"),
PINCTRL_PIN(151, "vI2S2_RXD"),
PINCTRL_PIN(152, "vSD3_CD_B"),
/* GPP_C */
PINCTRL_PIN(153, "SMBCLK"),
PINCTRL_PIN(154, "SMBDATA"),
PINCTRL_PIN(155, "SMBALERTB"),
PINCTRL_PIN(156, "SML0CLK"),
PINCTRL_PIN(157, "SML0DATA"),
PINCTRL_PIN(158, "SML0ALERTB"),
PINCTRL_PIN(159, "SML1CLK"),
PINCTRL_PIN(160, "SML1DATA"),
PINCTRL_PIN(161, "UART0_RXD"),
PINCTRL_PIN(162, "UART0_TXD"),
PINCTRL_PIN(163, "UART0_RTSB"),
PINCTRL_PIN(164, "UART0_CTSB"),
PINCTRL_PIN(165, "UART1_RXD"),
PINCTRL_PIN(166, "UART1_TXD"),
PINCTRL_PIN(167, "UART1_RTSB"),
PINCTRL_PIN(168, "UART1_CTSB"),
PINCTRL_PIN(169, "I2C0_SDA"),
PINCTRL_PIN(170, "I2C0_SCL"),
PINCTRL_PIN(171, "I2C1_SDA"),
PINCTRL_PIN(172, "I2C1_SCL"),
PINCTRL_PIN(173, "UART2_RXD"),
PINCTRL_PIN(174, "UART2_TXD"),
PINCTRL_PIN(175, "UART2_RTSB"),
PINCTRL_PIN(176, "UART2_CTSB"),
/* HVCMOS */
PINCTRL_PIN(177, "L_BKLTEN"),
PINCTRL_PIN(178, "L_BKLTCTL"),
PINCTRL_PIN(179, "L_VDDEN"),
PINCTRL_PIN(180, "SYS_PWROK"),
PINCTRL_PIN(181, "SYS_RESETB"),
PINCTRL_PIN(182, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(183, "SATAXPCIE_0"),
PINCTRL_PIN(184, "SPI1_IO_2"),
PINCTRL_PIN(185, "SPI1_IO_3"),
PINCTRL_PIN(186, "CPU_GP_0"),
PINCTRL_PIN(187, "SATA_DEVSLP_0"),
PINCTRL_PIN(188, "SATA_DEVSLP_1"),
PINCTRL_PIN(189, "GPPC_E_6"),
PINCTRL_PIN(190, "CPU_GP_1"),
PINCTRL_PIN(191, "SATA_LEDB"),
PINCTRL_PIN(192, "USB2_OCB_0"),
PINCTRL_PIN(193, "SPI1_CSB"),
PINCTRL_PIN(194, "SPI1_CLK"),
PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(197, "DDSP_HPD_A"),
PINCTRL_PIN(198, "ISH_GP_6"),
PINCTRL_PIN(199, "ISH_GP_7"),
PINCTRL_PIN(200, "DISP_MISC_4"),
PINCTRL_PIN(201, "DDP1_CTRLCLK"),
PINCTRL_PIN(202, "DDP1_CTRLDATA"),
PINCTRL_PIN(203, "DDP2_CTRLCLK"),
PINCTRL_PIN(204, "DDP2_CTRLDATA"),
PINCTRL_PIN(205, "DDPA_CTRLCLK"),
PINCTRL_PIN(206, "DDPA_CTRLDATA"),
/* JTAG */
PINCTRL_PIN(207, "JTAG_TDO"),
PINCTRL_PIN(208, "JTAGX"),
PINCTRL_PIN(209, "PRDYB"),
PINCTRL_PIN(210, "PREQB"),
PINCTRL_PIN(211, "CPU_TRSTB"),
PINCTRL_PIN(212, "JTAG_TDI"),
PINCTRL_PIN(213, "JTAG_TMS"),
PINCTRL_PIN(214, "JTAG_TCK"),
PINCTRL_PIN(215, "ITP_PMODE"),
/* GPP_R */
PINCTRL_PIN(216, "HDA_BCLK"),
PINCTRL_PIN(217, "HDA_SYNC"),
PINCTRL_PIN(218, "HDA_SDO"),
PINCTRL_PIN(219, "HDA_SDI_0"),
PINCTRL_PIN(220, "HDA_RSTB"),
PINCTRL_PIN(221, "HDA_SDI_1"),
PINCTRL_PIN(222, "I2S1_TXD"),
PINCTRL_PIN(223, "I2S1_RXD"),
/* GPP_S */
PINCTRL_PIN(224, "SNDW1_CLK"),
PINCTRL_PIN(225, "SNDW1_DATA"),
PINCTRL_PIN(226, "SNDW2_CLK"),
PINCTRL_PIN(227, "SNDW2_DATA"),
PINCTRL_PIN(228, "SNDW3_CLK"),
PINCTRL_PIN(229, "SNDW3_DATA"),
PINCTRL_PIN(230, "SNDW4_CLK"),
PINCTRL_PIN(231, "SNDW4_DATA"),
/* SPI */
PINCTRL_PIN(232, "SPI0_IO_2"),
PINCTRL_PIN(233, "SPI0_IO_3"),
PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
PINCTRL_PIN(236, "SPI0_TPM_CSB"),
PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(239, "SPI0_CLK"),
PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
};
static const struct intel_padgroup icllp_community0_gpps[] = {
ICL_GPP(0, 0, 7, 0), /* GPP_G */
ICL_GPP(1, 8, 33, 32), /* GPP_B */
ICL_GPP(2, 34, 58, 64), /* GPP_A */
};
static const struct intel_padgroup icllp_community1_gpps[] = {
ICL_GPP(0, 59, 82, 96), /* GPP_H */
ICL_GPP(1, 83, 103, 128), /* GPP_D */
ICL_GPP(2, 104, 123, 160), /* GPP_F */
ICL_GPP(3, 124, 152, 192), /* vGPIO */
};
static const struct intel_padgroup icllp_community4_gpps[] = {
ICL_GPP(0, 153, 176, 224), /* GPP_C */
ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(2, 183, 206, 256), /* GPP_E */
ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};
static const struct intel_padgroup icllp_community5_gpps[] = {
ICL_GPP(0, 216, 223, 288), /* GPP_R */
ICL_GPP(1, 224, 231, 320), /* GPP_S */
ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
};
static const struct intel_community icllp_communities[] = {
ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
};
static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
static const struct intel_pingroup icllp_groups[] = {
PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
};
static const char * const icllp_spi0_groups[] = { "spi0_grp" };
static const char * const icllp_spi1_groups[] = { "spi1_grp" };
static const char * const icllp_spi2_groups[] = { "spi2_grp" };
static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
static const char * const icllp_uart0_groups[] = { "uart0_grp" };
static const char * const icllp_uart1_groups[] = { "uart1_grp" };
static const char * const icllp_uart2_groups[] = { "uart2_grp" };
static const struct intel_function icllp_functions[] = {
FUNCTION("spi0", icllp_spi0_groups),
FUNCTION("spi1", icllp_spi1_groups),
FUNCTION("spi2", icllp_spi2_groups),
FUNCTION("i2c0", icllp_i2c0_groups),
FUNCTION("i2c1", icllp_i2c1_groups),
FUNCTION("i2c2", icllp_i2c2_groups),
FUNCTION("i2c3", icllp_i2c3_groups),
FUNCTION("i2c4", icllp_i2c4_groups),
FUNCTION("uart0", icllp_uart0_groups),
FUNCTION("uart1", icllp_uart1_groups),
FUNCTION("uart2", icllp_uart2_groups),
};
static const struct intel_pinctrl_soc_data icllp_soc_data = {
.pins = icllp_pins,
.npins = ARRAY_SIZE(icllp_pins),
.groups = icllp_groups,
.ngroups = ARRAY_SIZE(icllp_groups),
.functions = icllp_functions,
.nfunctions = ARRAY_SIZE(icllp_functions),
.communities = icllp_communities,
.ncommunities = ARRAY_SIZE(icllp_communities),
};
/* Ice Lake-N */
static const struct pinctrl_pin_desc icln_pins[] = {
/* SPI */
PINCTRL_PIN(0, "SPI0_IO_2"),
PINCTRL_PIN(1, "SPI0_IO_3"),
PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
PINCTRL_PIN(4, "SPI0_TPM_CSB"),
PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(7, "SPI0_CLK"),
PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
/* GPP_B */
PINCTRL_PIN(9, "CORE_VID_0"),
PINCTRL_PIN(10, "CORE_VID_1"),
PINCTRL_PIN(11, "VRALERTB"),
PINCTRL_PIN(12, "CPU_GP_2"),
PINCTRL_PIN(13, "CPU_GP_3"),
PINCTRL_PIN(14, "SRCCLKREQB_0"),
PINCTRL_PIN(15, "SRCCLKREQB_1"),
PINCTRL_PIN(16, "SRCCLKREQB_2"),
PINCTRL_PIN(17, "SRCCLKREQB_3"),
PINCTRL_PIN(18, "SRCCLKREQB_4"),
PINCTRL_PIN(19, "SRCCLKREQB_5"),
PINCTRL_PIN(20, "EXT_PWR_GATEB"),
PINCTRL_PIN(21, "SLP_S0B"),
PINCTRL_PIN(22, "PLTRSTB"),
PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
PINCTRL_PIN(24, "GSPI0_CS0B"),
PINCTRL_PIN(25, "GSPI0_CLK"),
PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
PINCTRL_PIN(28, "GSPI1_CS0B"),
PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
PINCTRL_PIN(31, "GSPI1_MOSI"),
PINCTRL_PIN(32, "GSPI1_CS1B"),
PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
/* GPP_A */
PINCTRL_PIN(35, "ESPI_IO_0"),
PINCTRL_PIN(36, "ESPI_IO_1"),
PINCTRL_PIN(37, "ESPI_IO_2"),
PINCTRL_PIN(38, "ESPI_IO_3"),
PINCTRL_PIN(39, "ESPI_CSB"),
PINCTRL_PIN(40, "ESPI_CLK"),
PINCTRL_PIN(41, "ESPI_RESETB"),
PINCTRL_PIN(42, "SMBCLK"),
PINCTRL_PIN(43, "SMBDATA"),
PINCTRL_PIN(44, "SMBALERTB"),
PINCTRL_PIN(45, "CPU_GP_0"),
PINCTRL_PIN(46, "CPU_GP_1"),
PINCTRL_PIN(47, "USB2_OCB_1"),
PINCTRL_PIN(48, "USB2_OCB_2"),
PINCTRL_PIN(49, "USB2_OCB_3"),
PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
PINCTRL_PIN(52, "DDSP_HPD_C"),
PINCTRL_PIN(53, "USB2_OCB_0"),
PINCTRL_PIN(54, "PCHHOTB"),
PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
/* GPP_S */
PINCTRL_PIN(56, "SNDW1_CLK"),
PINCTRL_PIN(57, "SNDW1_DATA"),
PINCTRL_PIN(58, "SNDW2_CLK"),
PINCTRL_PIN(59, "SNDW2_DATA"),
PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
/* GPP_R */
PINCTRL_PIN(64, "HDA_BCLK"),
PINCTRL_PIN(65, "HDA_SYNC"),
PINCTRL_PIN(66, "HDA_SDO"),
PINCTRL_PIN(67, "HDA_SDI_0"),
PINCTRL_PIN(68, "HDA_RSTB"),
PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
PINCTRL_PIN(70, "I2S1_SFRM"),
PINCTRL_PIN(71, "I2S1_TXD"),
/* GPP_H */
PINCTRL_PIN(72, "GPPC_H_0"),
PINCTRL_PIN(73, "CNV_RF_RESET_B"),
PINCTRL_PIN(74, "MODEM_CLKREQ"),
PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(76, "I2C2_SDA"),
PINCTRL_PIN(77, "I2C2_SCL"),
PINCTRL_PIN(78, "I2C3_SDA"),
PINCTRL_PIN(79, "I2C3_SCL"),
PINCTRL_PIN(80, "I2C4_SDA"),
PINCTRL_PIN(81, "I2C4_SCL"),
PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
PINCTRL_PIN(83, "I2S2_SCLK"),
PINCTRL_PIN(84, "CNV_RF_RESET_B"),
PINCTRL_PIN(85, "MODEM_CLKREQ"),
PINCTRL_PIN(86, "I2S2_RXD"),
PINCTRL_PIN(87, "I2S1_SCLK"),
PINCTRL_PIN(88, "GPPC_H_16"),
PINCTRL_PIN(89, "GPPC_H_17"),
PINCTRL_PIN(90, "GPPC_H_18"),
PINCTRL_PIN(91, "GPPC_H_19"),
PINCTRL_PIN(92, "GPPC_H_20"),
PINCTRL_PIN(93, "GPPC_H_21"),
PINCTRL_PIN(94, "GPPC_H_22"),
PINCTRL_PIN(95, "GPPC_H_23"),
/* GPP_D */
PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
PINCTRL_PIN(100, "ISH_I2C0_SDA"),
PINCTRL_PIN(101, "ISH_I2C0_SCL"),
PINCTRL_PIN(102, "ISH_I2C1_SDA"),
PINCTRL_PIN(103, "ISH_I2C1_SCL"),
PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
PINCTRL_PIN(112, "SPI1_IO_2"),
PINCTRL_PIN(113, "SPI1_IO_3"),
PINCTRL_PIN(114, "I2S_MCLK"),
PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
PINCTRL_PIN(117, "CNV_PA_BLANKING"),
PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
/* vGPIO */
PINCTRL_PIN(122, "CNV_BTEN"),
PINCTRL_PIN(123, "CNV_WCEN"),
PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(134, "vUART0_TXD"),
PINCTRL_PIN(135, "vUART0_RXD"),
PINCTRL_PIN(136, "vUART0_CTS_B"),
PINCTRL_PIN(137, "vUART0_RTS_B"),
PINCTRL_PIN(138, "vISH_UART0_TXD"),
PINCTRL_PIN(139, "vISH_UART0_RXD"),
PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(146, "vI2S2_SCLK"),
PINCTRL_PIN(147, "vI2S2_SFRM"),
PINCTRL_PIN(148, "vI2S2_TXD"),
PINCTRL_PIN(149, "vI2S2_RXD"),
PINCTRL_PIN(150, "vSD3_CD_B"),
/* GPP_C */
PINCTRL_PIN(151, "GPPC_C_0"),
PINCTRL_PIN(152, "GPPC_C_1"),
PINCTRL_PIN(153, "GPPC_C_2"),
PINCTRL_PIN(154, "GPPC_C_3"),
PINCTRL_PIN(155, "GPPC_C_4"),
PINCTRL_PIN(156, "GPPC_C_5"),
PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(158, "SUSACKB"),
PINCTRL_PIN(159, "UART0_RXD"),
PINCTRL_PIN(160, "UART0_TXD"),
PINCTRL_PIN(161, "UART0_RTSB"),
PINCTRL_PIN(162, "UART0_CTSB"),
PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
PINCTRL_PIN(167, "I2C0_SDA"),
PINCTRL_PIN(168, "I2C0_SCL"),
PINCTRL_PIN(169, "I2C1_SDA"),
PINCTRL_PIN(170, "I2C1_SCL"),
PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
/* HVCMOS */
PINCTRL_PIN(175, "L_BKLTEN"),
PINCTRL_PIN(176, "L_BKLTCTL"),
PINCTRL_PIN(177, "L_VDDEN"),
PINCTRL_PIN(178, "SYS_PWROK"),
PINCTRL_PIN(179, "SYS_RESETB"),
PINCTRL_PIN(180, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
PINCTRL_PIN(182, "ISH_GP_1"),
PINCTRL_PIN(183, "IMGCLKOUT_1"),
PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
PINCTRL_PIN(185, "IMGCLKOUT_2"),
PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
PINCTRL_PIN(187, "IMGCLKOUT_3"),
PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
PINCTRL_PIN(189, "FIVR_DIGPB_0"),
PINCTRL_PIN(190, "SML0CLK"),
PINCTRL_PIN(191, "SML0DATA"),
PINCTRL_PIN(192, "BSSB_LS3_RX"),
PINCTRL_PIN(193, "BSSB_LS3_TX"),
PINCTRL_PIN(194, "BSSB_LS0_RX"),
PINCTRL_PIN(195, "BSSB_LS0_TX"),
PINCTRL_PIN(196, "BSSB_LS1_RX"),
PINCTRL_PIN(197, "BSSB_LS1_TX"),
PINCTRL_PIN(198, "BSSB_LS2_RX"),
PINCTRL_PIN(199, "BSSB_LS2_TX"),
PINCTRL_PIN(200, "FIVR_DIGPB_1"),
PINCTRL_PIN(201, "CNV_BRI_DT"),
PINCTRL_PIN(202, "CNV_BRI_RSP"),
PINCTRL_PIN(203, "CNV_RGI_DT"),
PINCTRL_PIN(204, "CNV_RGI_RSP"),
/* GPP_G */
PINCTRL_PIN(205, "SD3_CMD"),
PINCTRL_PIN(206, "SD3_D0"),
PINCTRL_PIN(207, "SD3_D1"),
PINCTRL_PIN(208, "SD3_D2"),
PINCTRL_PIN(209, "SD3_D3"),
PINCTRL_PIN(210, "SD3_CDB"),
PINCTRL_PIN(211, "SD3_CLK"),
PINCTRL_PIN(212, "SD3_WP"),
};
static const struct intel_padgroup icln_community0_gpps[] = {
ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
ICL_GPP(1, 9, 34, 32), /* GPP_B */
ICL_GPP(2, 35, 55, 64), /* GPP_A */
ICL_GPP(3, 56, 63, 96), /* GPP_S */
ICL_GPP(4, 64, 71, 128), /* GPP_R */
};
static const struct intel_padgroup icln_community1_gpps[] = {
ICL_GPP(0, 72, 95, 160), /* GPP_H */
ICL_GPP(1, 96, 121, 192), /* GPP_D */
ICL_GPP(2, 122, 150, 224), /* vGPIO */
ICL_GPP(3, 151, 174, 256), /* GPP_C */
};
static const struct intel_padgroup icln_community4_gpps[] = {
ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
ICL_GPP(1, 181, 204, 288), /* GPP_E */
};
static const struct intel_padgroup icln_community5_gpps[] = {
ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community icln_communities[] = {
ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
};
static const struct intel_pinctrl_soc_data icln_soc_data = {
.pins = icln_pins,
.npins = ARRAY_SIZE(icln_pins),
.communities = icln_communities,
.ncommunities = ARRAY_SIZE(icln_communities),
};
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
static struct platform_driver icl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "icelake-pinctrl",
.acpi_match_table = icl_pinctrl_acpi_match,
.pm = &icl_pinctrl_pm_ops,
},
};
module_platform_driver(icl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-icelake.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Cedar Fork PCH pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define CDF_PAD_OWN 0x020
#define CDF_PADCFGLOCK 0x0c0
#define CDF_HOSTSW_OWN 0x120
#define CDF_GPI_IS 0x200
#define CDF_GPI_IE 0x230
#define CDF_GPP(r, s, e) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define CDF_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
/* Cedar Fork PCH */
static const struct pinctrl_pin_desc cdf_pins[] = {
/* WEST2 */
PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
PINCTRL_PIN(4, "GBE0_I2C_CLK"),
PINCTRL_PIN(5, "GBE0_I2C_DATA"),
PINCTRL_PIN(6, "GBE1_I2C_CLK"),
PINCTRL_PIN(7, "GBE1_I2C_DATA"),
PINCTRL_PIN(8, "GBE2_I2C_CLK"),
PINCTRL_PIN(9, "GBE2_I2C_DATA"),
PINCTRL_PIN(10, "GBE3_I2C_CLK"),
PINCTRL_PIN(11, "GBE3_I2C_DATA"),
PINCTRL_PIN(12, "GBE0_LED0"),
PINCTRL_PIN(13, "GBE0_LED1"),
PINCTRL_PIN(14, "GBE0_LED2"),
PINCTRL_PIN(15, "GBE1_LED0"),
PINCTRL_PIN(16, "GBE1_LED1"),
PINCTRL_PIN(17, "GBE1_LED2"),
PINCTRL_PIN(18, "GBE2_LED0"),
PINCTRL_PIN(19, "GBE2_LED1"),
PINCTRL_PIN(20, "GBE2_LED2"),
PINCTRL_PIN(21, "GBE3_LED0"),
PINCTRL_PIN(22, "GBE3_LED1"),
PINCTRL_PIN(23, "GBE3_LED2"),
/* WEST3 */
PINCTRL_PIN(24, "NCSI_RXD0"),
PINCTRL_PIN(25, "NCSI_CLK_IN"),
PINCTRL_PIN(26, "NCSI_RXD1"),
PINCTRL_PIN(27, "NCSI_CRS_DV"),
PINCTRL_PIN(28, "NCSI_ARB_IN"),
PINCTRL_PIN(29, "NCSI_TX_EN"),
PINCTRL_PIN(30, "NCSI_TXD0"),
PINCTRL_PIN(31, "NCSI_TXD1"),
PINCTRL_PIN(32, "NCSI_ARB_OUT"),
PINCTRL_PIN(33, "GBE_SMB_CLK"),
PINCTRL_PIN(34, "GBE_SMB_DATA"),
PINCTRL_PIN(35, "GBE_SMB_ALRT_N"),
PINCTRL_PIN(36, "THERMTRIP_N"),
PINCTRL_PIN(37, "PCHHOT_N"),
PINCTRL_PIN(38, "ERROR0_N"),
PINCTRL_PIN(39, "ERROR1_N"),
PINCTRL_PIN(40, "ERROR2_N"),
PINCTRL_PIN(41, "MSMI_N"),
PINCTRL_PIN(42, "CATERR_N"),
PINCTRL_PIN(43, "MEMTRIP_N"),
PINCTRL_PIN(44, "UART0_RXD"),
PINCTRL_PIN(45, "UART0_TXD"),
PINCTRL_PIN(46, "GBE_UART_RXD"),
PINCTRL_PIN(47, "GBE_UART_TXD"),
/* WEST01 */
PINCTRL_PIN(48, "GBE_GPIO13"),
PINCTRL_PIN(49, "AUX_PWR"),
PINCTRL_PIN(50, "UART0_RTS"),
PINCTRL_PIN(51, "UART0_CTS"),
PINCTRL_PIN(52, "FAN_PWM_0"),
PINCTRL_PIN(53, "FAN_PWM_1"),
PINCTRL_PIN(54, "FAN_PWM_2"),
PINCTRL_PIN(55, "FAN_PWM_3"),
PINCTRL_PIN(56, "FAN_TACH_0"),
PINCTRL_PIN(57, "FAN_TACH_1"),
PINCTRL_PIN(58, "FAN_TACH_2"),
PINCTRL_PIN(59, "FAN_TACH_3"),
PINCTRL_PIN(60, "ME_SMB0_CLK"),
PINCTRL_PIN(61, "ME_SMB0_DATA"),
PINCTRL_PIN(62, "ME_SMB0_ALRT_N"),
PINCTRL_PIN(63, "ME_SMB1_CLK"),
PINCTRL_PIN(64, "ME_SMB1_DATA"),
PINCTRL_PIN(65, "ME_SMB1_ALRT_N"),
PINCTRL_PIN(66, "ME_SMB2_CLK"),
PINCTRL_PIN(67, "ME_SMB2_DATA"),
PINCTRL_PIN(68, "ME_SMB2_ALRT_N"),
PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"),
PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"),
/* WEST5 */
PINCTRL_PIN(71, "IE_UART_RXD"),
PINCTRL_PIN(72, "IE_UART_TXD"),
PINCTRL_PIN(73, "VPP_SMB_CLK"),
PINCTRL_PIN(74, "VPP_SMB_DATA"),
PINCTRL_PIN(75, "VPP_SMB_ALRT_N"),
PINCTRL_PIN(76, "PCIE_CLKREQ0_N"),
PINCTRL_PIN(77, "PCIE_CLKREQ1_N"),
PINCTRL_PIN(78, "PCIE_CLKREQ2_N"),
PINCTRL_PIN(79, "PCIE_CLKREQ3_N"),
PINCTRL_PIN(80, "PCIE_CLKREQ4_N"),
PINCTRL_PIN(81, "PCIE_CLKREQ5_N"),
PINCTRL_PIN(82, "PCIE_CLKREQ6_N"),
PINCTRL_PIN(83, "PCIE_CLKREQ7_N"),
PINCTRL_PIN(84, "PCIE_CLKREQ8_N"),
PINCTRL_PIN(85, "PCIE_CLKREQ9_N"),
PINCTRL_PIN(86, "FLEX_CLK_SE0"),
PINCTRL_PIN(87, "FLEX_CLK_SE1"),
PINCTRL_PIN(88, "FLEX_CLK1_50"),
PINCTRL_PIN(89, "FLEX_CLK2_50"),
PINCTRL_PIN(90, "FLEX_CLK_125"),
/* WESTC */
PINCTRL_PIN(91, "TCK_PCH"),
PINCTRL_PIN(92, "JTAGX_PCH"),
PINCTRL_PIN(93, "TRST_N_PCH"),
PINCTRL_PIN(94, "TMS_PCH"),
PINCTRL_PIN(95, "TDI_PCH"),
PINCTRL_PIN(96, "TDO_PCH"),
/* WESTC_DFX */
PINCTRL_PIN(97, "CX_PRDY_N"),
PINCTRL_PIN(98, "CX_PREQ_N"),
PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"),
PINCTRL_PIN(100, "TRIGGER0_N"),
PINCTRL_PIN(101, "TRIGGER1_N"),
/* WESTA */
PINCTRL_PIN(102, "DBG_PTI_CLK0"),
PINCTRL_PIN(103, "DBG_PTI_CLK3"),
PINCTRL_PIN(104, "DBG_PTI_DATA0"),
PINCTRL_PIN(105, "DBG_PTI_DATA1"),
PINCTRL_PIN(106, "DBG_PTI_DATA2"),
PINCTRL_PIN(107, "DBG_PTI_DATA3"),
PINCTRL_PIN(108, "DBG_PTI_DATA4"),
PINCTRL_PIN(109, "DBG_PTI_DATA5"),
PINCTRL_PIN(110, "DBG_PTI_DATA6"),
PINCTRL_PIN(111, "DBG_PTI_DATA7"),
/* WESTB */
PINCTRL_PIN(112, "DBG_PTI_DATA8"),
PINCTRL_PIN(113, "DBG_PTI_DATA9"),
PINCTRL_PIN(114, "DBG_PTI_DATA10"),
PINCTRL_PIN(115, "DBG_PTI_DATA11"),
PINCTRL_PIN(116, "DBG_PTI_DATA12"),
PINCTRL_PIN(117, "DBG_PTI_DATA13"),
PINCTRL_PIN(118, "DBG_PTI_DATA14"),
PINCTRL_PIN(119, "DBG_PTI_DATA15"),
PINCTRL_PIN(120, "DBG_SPARE0"),
PINCTRL_PIN(121, "DBG_SPARE1"),
PINCTRL_PIN(122, "DBG_SPARE2"),
PINCTRL_PIN(123, "DBG_SPARE3"),
/* WESTD */
PINCTRL_PIN(124, "CPU_PWR_GOOD"),
PINCTRL_PIN(125, "PLTRST_CPU_N"),
PINCTRL_PIN(126, "NAC_RESET_NAC_N"),
PINCTRL_PIN(127, "PCH_SBLINK_RX"),
PINCTRL_PIN(128, "PCH_SBLINK_TX"),
PINCTRL_PIN(129, "PMSYNC_CLK"),
PINCTRL_PIN(130, "CPU_ERR0_N"),
PINCTRL_PIN(131, "CPU_ERR1_N"),
PINCTRL_PIN(132, "CPU_ERR2_N"),
PINCTRL_PIN(133, "CPU_THERMTRIP_N"),
PINCTRL_PIN(134, "CPU_MSMI_N"),
PINCTRL_PIN(135, "CPU_CATERR_N"),
PINCTRL_PIN(136, "CPU_MEMTRIP_N"),
PINCTRL_PIN(137, "NAC_GR_N"),
PINCTRL_PIN(138, "NAC_XTAL_VALID"),
PINCTRL_PIN(139, "NAC_WAKE_N"),
PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"),
PINCTRL_PIN(141, "NAC_SBLINK_N2S"),
PINCTRL_PIN(142, "NAC_SBLINK_S2N"),
PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"),
/* WESTD_PECI */
PINCTRL_PIN(144, "ME_PECI"),
/* WESTF */
PINCTRL_PIN(145, "NAC_RMII_CLK"),
PINCTRL_PIN(146, "NAC_RGMII_CLK"),
PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
PINCTRL_PIN(149, "NAC_SPARE2"),
PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"),
PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"),
PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"),
PINCTRL_PIN(155, "NAC_NCSI_RXD0"),
PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"),
PINCTRL_PIN(157, "NAC_NCSI_RXD1"),
PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"),
PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"),
PINCTRL_PIN(160, "NAC_NCSI_TX_EN"),
PINCTRL_PIN(161, "NAC_NCSI_TXD0"),
PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
/* EAST2 */
PINCTRL_PIN(168, "USB_OC0_N"),
PINCTRL_PIN(169, "GBE_GPIO0"),
PINCTRL_PIN(170, "GBE_GPIO1"),
PINCTRL_PIN(171, "GBE_GPIO2"),
PINCTRL_PIN(172, "GBE_GPIO3"),
PINCTRL_PIN(173, "GBE_GPIO4"),
PINCTRL_PIN(174, "GBE_GPIO5"),
PINCTRL_PIN(175, "GBE_GPIO6"),
PINCTRL_PIN(176, "GBE_GPIO7"),
PINCTRL_PIN(177, "SPI_TPM_CS_N"),
PINCTRL_PIN(178, "GBE_GPIO9"),
PINCTRL_PIN(179, "GBE_GPIO10"),
PINCTRL_PIN(180, "GBE_GPIO11"),
PINCTRL_PIN(181, "GBE_GPIO12"),
PINCTRL_PIN(182, "PECI_SMB_DATA"),
PINCTRL_PIN(183, "SATA0_LED_N"),
PINCTRL_PIN(184, "SATA1_LED_N"),
PINCTRL_PIN(185, "SATA_PDETECT0"),
PINCTRL_PIN(186, "SATA_PDETECT1"),
PINCTRL_PIN(187, "SATA0_SDOUT"),
PINCTRL_PIN(188, "SATA1_SDOUT"),
PINCTRL_PIN(189, "SATA2_LED_N"),
PINCTRL_PIN(190, "SATA_PDETECT2"),
PINCTRL_PIN(191, "SATA2_SDOUT"),
/* EAST3 */
PINCTRL_PIN(192, "ESPI_IO0"),
PINCTRL_PIN(193, "ESPI_IO1"),
PINCTRL_PIN(194, "ESPI_IO2"),
PINCTRL_PIN(195, "ESPI_IO3"),
PINCTRL_PIN(196, "ESPI_CLK"),
PINCTRL_PIN(197, "ESPI_RST_N"),
PINCTRL_PIN(198, "ESPI_CS0_N"),
PINCTRL_PIN(199, "ESPI_ALRT0_N"),
PINCTRL_PIN(200, "ESPI_CS1_N"),
PINCTRL_PIN(201, "ESPI_ALRT1_N"),
PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"),
/* EAST0 */
PINCTRL_PIN(203, "SPI_CS0_N"),
PINCTRL_PIN(204, "SPI_CS1_N"),
PINCTRL_PIN(205, "SPI_MOSI_IO0"),
PINCTRL_PIN(206, "SPI_MISO_IO1"),
PINCTRL_PIN(207, "SPI_IO2"),
PINCTRL_PIN(208, "SPI_IO3"),
PINCTRL_PIN(209, "SPI_CLK"),
PINCTRL_PIN(210, "SPI_CLK_LOOPBK"),
PINCTRL_PIN(211, "SUSPWRDNACK"),
PINCTRL_PIN(212, "PMU_SUSCLK"),
PINCTRL_PIN(213, "ADR_COMPLETE"),
PINCTRL_PIN(214, "ADR_TRIGGER_N"),
PINCTRL_PIN(215, "PMU_SLP_S45_N"),
PINCTRL_PIN(216, "PMU_SLP_S3_N"),
PINCTRL_PIN(217, "PMU_WAKE_N"),
PINCTRL_PIN(218, "PMU_PWRBTN_N"),
PINCTRL_PIN(219, "PMU_RESETBUTTON_N"),
PINCTRL_PIN(220, "PMU_PLTRST_N"),
PINCTRL_PIN(221, "SUS_STAT_N"),
PINCTRL_PIN(222, "PMU_I2C_CLK"),
PINCTRL_PIN(223, "PMU_I2C_DATA"),
PINCTRL_PIN(224, "PECI_SMB_CLK"),
PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
/* EMMC */
PINCTRL_PIN(226, "EMMC_CMD"),
PINCTRL_PIN(227, "EMMC_STROBE"),
PINCTRL_PIN(228, "EMMC_CLK"),
PINCTRL_PIN(229, "EMMC_D0"),
PINCTRL_PIN(230, "EMMC_D1"),
PINCTRL_PIN(231, "EMMC_D2"),
PINCTRL_PIN(232, "EMMC_D3"),
PINCTRL_PIN(233, "EMMC_D4"),
PINCTRL_PIN(234, "EMMC_D5"),
PINCTRL_PIN(235, "EMMC_D6"),
PINCTRL_PIN(236, "EMMC_D7"),
};
static const struct intel_padgroup cdf_community0_gpps[] = {
CDF_GPP(0, 0, 23), /* WEST2 */
CDF_GPP(1, 24, 47), /* WEST3 */
CDF_GPP(2, 48, 70), /* WEST01 */
CDF_GPP(3, 71, 90), /* WEST5 */
CDF_GPP(4, 91, 96), /* WESTC */
CDF_GPP(5, 97, 101), /* WESTC_DFX */
CDF_GPP(6, 102, 111), /* WESTA */
CDF_GPP(7, 112, 123), /* WESTB */
CDF_GPP(8, 124, 143), /* WESTD */
CDF_GPP(9, 144, 144), /* WESTD_PECI */
CDF_GPP(10, 145, 167), /* WESTF */
};
static const struct intel_padgroup cdf_community1_gpps[] = {
CDF_GPP(0, 168, 191), /* EAST2 */
CDF_GPP(1, 192, 202), /* EAST3 */
CDF_GPP(2, 203, 225), /* EAST0 */
CDF_GPP(3, 226, 236), /* EMMC */
};
static const struct intel_community cdf_communities[] = {
CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */
CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */
};
static const struct intel_pinctrl_soc_data cdf_soc_data = {
.pins = cdf_pins,
.npins = ARRAY_SIZE(cdf_pins),
.communities = cdf_communities,
.ncommunities = ARRAY_SIZE(cdf_communities),
};
static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
static struct platform_driver cdf_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cedarfork-pinctrl",
.acpi_match_table = cdf_pinctrl_acpi_match,
.pm = &cdf_pinctrl_pm_ops,
},
};
static int __init cdf_pinctrl_init(void)
{
return platform_driver_register(&cdf_pinctrl_driver);
}
subsys_initcall(cdf_pinctrl_init);
static void __exit cdf_pinctrl_exit(void)
{
platform_driver_unregister(&cdf_pinctrl_driver);
}
module_exit(cdf_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-cedarfork.c
|
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Lewisburg pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <[email protected]>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define LBG_PAD_OWN 0x020
#define LBG_PADCFGLOCK 0x060
#define LBG_HOSTSW_OWN 0x080
#define LBG_GPI_IS 0x100
#define LBG_GPI_IE 0x110
#define LBG_COMMUNITY(b, s, e) \
INTEL_COMMUNITY_SIZE(b, s, e, 24, 3, LBG)
/* Lewisburg */
static const struct pinctrl_pin_desc lbg_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIRQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(14, "ESPI_RESETB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "CLKOUT_LPC_2"),
PINCTRL_PIN(17, "GPP_A_17"),
PINCTRL_PIN(18, "GPP_A_18"),
PINCTRL_PIN(19, "GPP_A_19"),
PINCTRL_PIN(20, "GPP_A_20"),
PINCTRL_PIN(21, "GPP_A_21"),
PINCTRL_PIN(22, "GPP_A_22"),
PINCTRL_PIN(23, "GPP_A_23"),
/* GPP_B */
PINCTRL_PIN(24, "CORE_VID_0"),
PINCTRL_PIN(25, "CORE_VID_1"),
PINCTRL_PIN(26, "VRALERTB"),
PINCTRL_PIN(27, "CPU_GP_2"),
PINCTRL_PIN(28, "CPU_GP_3"),
PINCTRL_PIN(29, "SRCCLKREQB_0"),
PINCTRL_PIN(30, "SRCCLKREQB_1"),
PINCTRL_PIN(31, "SRCCLKREQB_2"),
PINCTRL_PIN(32, "SRCCLKREQB_3"),
PINCTRL_PIN(33, "SRCCLKREQB_4"),
PINCTRL_PIN(34, "SRCCLKREQB_5"),
PINCTRL_PIN(35, "GPP_B_11"),
PINCTRL_PIN(36, "SLP_S0B"),
PINCTRL_PIN(37, "PLTRSTB"),
PINCTRL_PIN(38, "SPKR"),
PINCTRL_PIN(39, "GPP_B_15"),
PINCTRL_PIN(40, "GPP_B_16"),
PINCTRL_PIN(41, "GPP_B_17"),
PINCTRL_PIN(42, "GPP_B_18"),
PINCTRL_PIN(43, "GPP_B_19"),
PINCTRL_PIN(44, "GPP_B_20"),
PINCTRL_PIN(45, "GPP_B_21"),
PINCTRL_PIN(46, "GPP_B_22"),
PINCTRL_PIN(47, "SML1ALERTB"),
/* GPP_F */
PINCTRL_PIN(48, "SATAXPCIE_3"),
PINCTRL_PIN(49, "SATAXPCIE_4"),
PINCTRL_PIN(50, "SATAXPCIE_5"),
PINCTRL_PIN(51, "SATAXPCIE_6"),
PINCTRL_PIN(52, "SATAXPCIE_7"),
PINCTRL_PIN(53, "SATA_DEVSLP_3"),
PINCTRL_PIN(54, "SATA_DEVSLP_4"),
PINCTRL_PIN(55, "SATA_DEVSLP_5"),
PINCTRL_PIN(56, "SATA_DEVSLP_6"),
PINCTRL_PIN(57, "SATA_DEVSLP_7"),
PINCTRL_PIN(58, "SATA_SCLOCK"),
PINCTRL_PIN(59, "SATA_SLOAD"),
PINCTRL_PIN(60, "SATA_SDATAOUT1"),
PINCTRL_PIN(61, "SATA_SDATAOUT0"),
PINCTRL_PIN(62, "SSATA_LEDB"),
PINCTRL_PIN(63, "USB2_OCB_4"),
PINCTRL_PIN(64, "USB2_OCB_5"),
PINCTRL_PIN(65, "USB2_OCB_6"),
PINCTRL_PIN(66, "USB2_OCB_7"),
PINCTRL_PIN(67, "GBE_SMBUS_CLK"),
PINCTRL_PIN(68, "GBE_SMBDATA"),
PINCTRL_PIN(69, "GBE_SMBALRTN"),
PINCTRL_PIN(70, "SSATA_SCLOCK"),
PINCTRL_PIN(71, "SSATA_SLOAD"),
/* GPP_C */
PINCTRL_PIN(72, "SMBCLK"),
PINCTRL_PIN(73, "SMBDATA"),
PINCTRL_PIN(74, "SMBALERTB"),
PINCTRL_PIN(75, "SML0CLK"),
PINCTRL_PIN(76, "SML0DATA"),
PINCTRL_PIN(77, "SML0ALERTB"),
PINCTRL_PIN(78, "SML1CLK"),
PINCTRL_PIN(79, "SML1DATA"),
PINCTRL_PIN(80, "GPP_C_8"),
PINCTRL_PIN(81, "GPP_C_9"),
PINCTRL_PIN(82, "GPP_C_10"),
PINCTRL_PIN(83, "GPP_C_11"),
PINCTRL_PIN(84, "GPP_C_12"),
PINCTRL_PIN(85, "GPP_C_13"),
PINCTRL_PIN(86, "GPP_C_14"),
PINCTRL_PIN(87, "GPP_C_15"),
PINCTRL_PIN(88, "GPP_C_16"),
PINCTRL_PIN(89, "GPP_C_17"),
PINCTRL_PIN(90, "GPP_C_18"),
PINCTRL_PIN(91, "GPP_C_19"),
PINCTRL_PIN(92, "GPP_C_20"),
PINCTRL_PIN(93, "GPP_C_21"),
PINCTRL_PIN(94, "GPP_C_22"),
PINCTRL_PIN(95, "GPP_C_23"),
/* GPP_D */
PINCTRL_PIN(96, "GPP_D_0"),
PINCTRL_PIN(97, "GPP_D_1"),
PINCTRL_PIN(98, "GPP_D_2"),
PINCTRL_PIN(99, "GPP_D_3"),
PINCTRL_PIN(100, "GPP_D_4"),
PINCTRL_PIN(101, "SSP0_SFRM"),
PINCTRL_PIN(102, "SSP0_TXD"),
PINCTRL_PIN(103, "SSP0_RXD"),
PINCTRL_PIN(104, "SSP0_SCLK"),
PINCTRL_PIN(105, "SSATA_DEVSLP_3"),
PINCTRL_PIN(106, "SSATA_DEVSLP_4"),
PINCTRL_PIN(107, "SSATA_DEVSLP_5"),
PINCTRL_PIN(108, "SSATA_SDATAOUT1"),
PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"),
PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"),
PINCTRL_PIN(111, "SSATA_SDATAOUT0"),
PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"),
PINCTRL_PIN(113, "DMIC_CLK_1"),
PINCTRL_PIN(114, "DMIC_DATA_1"),
PINCTRL_PIN(115, "DMIC_CLK_0"),
PINCTRL_PIN(116, "DMIC_DATA_0"),
PINCTRL_PIN(117, "IE_UART_RXD"),
PINCTRL_PIN(118, "IE_UART_TXD"),
PINCTRL_PIN(119, "GPP_D_23"),
/* GPP_E */
PINCTRL_PIN(120, "SATAXPCIE_0"),
PINCTRL_PIN(121, "SATAXPCIE_1"),
PINCTRL_PIN(122, "SATAXPCIE_2"),
PINCTRL_PIN(123, "CPU_GP_0"),
PINCTRL_PIN(124, "SATA_DEVSLP_0"),
PINCTRL_PIN(125, "SATA_DEVSLP_1"),
PINCTRL_PIN(126, "SATA_DEVSLP_2"),
PINCTRL_PIN(127, "CPU_GP_1"),
PINCTRL_PIN(128, "SATA_LEDB"),
PINCTRL_PIN(129, "USB2_OCB_0"),
PINCTRL_PIN(130, "USB2_OCB_1"),
PINCTRL_PIN(131, "USB2_OCB_2"),
PINCTRL_PIN(132, "USB2_OCB_3"),
/* GPP_I */
PINCTRL_PIN(133, "GBE_TDO"),
PINCTRL_PIN(134, "GBE_TCK"),
PINCTRL_PIN(135, "GBE_TMS"),
PINCTRL_PIN(136, "GBE_TDI"),
PINCTRL_PIN(137, "DO_RESET_INB"),
PINCTRL_PIN(138, "DO_RESET_OUTB"),
PINCTRL_PIN(139, "RESET_DONE"),
PINCTRL_PIN(140, "GBE_TRST_N"),
PINCTRL_PIN(141, "GBE_PCI_DIS"),
PINCTRL_PIN(142, "GBE_LAN_DIS"),
PINCTRL_PIN(143, "GPP_I_10"),
/* GPP_J */
PINCTRL_PIN(144, "GBE_LED_0_0"),
PINCTRL_PIN(145, "GBE_LED_0_1"),
PINCTRL_PIN(146, "GBE_LED_1_0"),
PINCTRL_PIN(147, "GBE_LED_1_1"),
PINCTRL_PIN(148, "GBE_LED_2_0"),
PINCTRL_PIN(149, "GBE_LED_2_1"),
PINCTRL_PIN(150, "GBE_LED_3_0"),
PINCTRL_PIN(151, "GBE_LED_3_1"),
PINCTRL_PIN(152, "GBE_SCL_0"),
PINCTRL_PIN(153, "GBE_SDA_0"),
PINCTRL_PIN(154, "GBE_SCL_1"),
PINCTRL_PIN(155, "GBE_SDA_1"),
PINCTRL_PIN(156, "GBE_SCL_2"),
PINCTRL_PIN(157, "GBE_SDA_2"),
PINCTRL_PIN(158, "GBE_SCL_3"),
PINCTRL_PIN(159, "GBE_SDA_3"),
PINCTRL_PIN(160, "GBE_SDP_0_0"),
PINCTRL_PIN(161, "GBE_SDP_0_1"),
PINCTRL_PIN(162, "GBE_SDP_1_0"),
PINCTRL_PIN(163, "GBE_SDP_1_1"),
PINCTRL_PIN(164, "GBE_SDP_2_0"),
PINCTRL_PIN(165, "GBE_SDP_2_1"),
PINCTRL_PIN(166, "GBE_SDP_3_0"),
PINCTRL_PIN(167, "GBE_SDP_3_1"),
/* GPP_K */
PINCTRL_PIN(168, "GBE_RMIICLK"),
PINCTRL_PIN(169, "GBE_RMII_RXD_0"),
PINCTRL_PIN(170, "GBE_RMII_RXD_1"),
PINCTRL_PIN(171, "GBE_RMII_CRS_DV"),
PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
PINCTRL_PIN(173, "GBE_RMII_TXD_0"),
PINCTRL_PIN(174, "GBE_RMII_TXD_1"),
PINCTRL_PIN(175, "GBE_RMII_RX_ER"),
PINCTRL_PIN(176, "GBE_RMII_ARBIN"),
PINCTRL_PIN(177, "GBE_RMII_ARB_OUT"),
PINCTRL_PIN(178, "PE_RST_N"),
/* GPP_G */
PINCTRL_PIN(179, "FAN_TACH_0"),
PINCTRL_PIN(180, "FAN_TACH_1"),
PINCTRL_PIN(181, "FAN_TACH_2"),
PINCTRL_PIN(182, "FAN_TACH_3"),
PINCTRL_PIN(183, "FAN_TACH_4"),
PINCTRL_PIN(184, "FAN_TACH_5"),
PINCTRL_PIN(185, "FAN_TACH_6"),
PINCTRL_PIN(186, "FAN_TACH_7"),
PINCTRL_PIN(187, "FAN_PWM_0"),
PINCTRL_PIN(188, "FAN_PWM_1"),
PINCTRL_PIN(189, "FAN_PWM_2"),
PINCTRL_PIN(190, "FAN_PWM_3"),
PINCTRL_PIN(191, "GSXDOUT"),
PINCTRL_PIN(192, "GSXSLOAD"),
PINCTRL_PIN(193, "GSXDIN"),
PINCTRL_PIN(194, "GSXSRESETB"),
PINCTRL_PIN(195, "GSXCLK"),
PINCTRL_PIN(196, "ADR_COMPLETE"),
PINCTRL_PIN(197, "NMIB"),
PINCTRL_PIN(198, "SMIB"),
PINCTRL_PIN(199, "SSATA_DEVSLP_0"),
PINCTRL_PIN(200, "SSATA_DEVSLP_1"),
PINCTRL_PIN(201, "SSATA_DEVSLP_2"),
PINCTRL_PIN(202, "SSATAXPCIE0_SSATAGP0"),
/* GPP_H */
PINCTRL_PIN(203, "SRCCLKREQB_6"),
PINCTRL_PIN(204, "SRCCLKREQB_7"),
PINCTRL_PIN(205, "SRCCLKREQB_8"),
PINCTRL_PIN(206, "SRCCLKREQB_9"),
PINCTRL_PIN(207, "SRCCLKREQB_10"),
PINCTRL_PIN(208, "SRCCLKREQB_11"),
PINCTRL_PIN(209, "SRCCLKREQB_12"),
PINCTRL_PIN(210, "SRCCLKREQB_13"),
PINCTRL_PIN(211, "SRCCLKREQB_14"),
PINCTRL_PIN(212, "SRCCLKREQB_15"),
PINCTRL_PIN(213, "SML2CLK"),
PINCTRL_PIN(214, "SML2DATA"),
PINCTRL_PIN(215, "SML2ALERTB"),
PINCTRL_PIN(216, "SML3CLK"),
PINCTRL_PIN(217, "SML3DATA"),
PINCTRL_PIN(218, "SML3ALERTB"),
PINCTRL_PIN(219, "SML4CLK"),
PINCTRL_PIN(220, "SML4DATA"),
PINCTRL_PIN(221, "SML4ALERTB"),
PINCTRL_PIN(222, "SSATAXPCIE1_SSATAGP1"),
PINCTRL_PIN(223, "SSATAXPCIE2_SSATAGP2"),
PINCTRL_PIN(224, "SSATAXPCIE3_SSATAGP3"),
PINCTRL_PIN(225, "SSATAXPCIE4_SSATAGP4"),
PINCTRL_PIN(226, "SSATAXPCIE5_SSATAGP5"),
/* GPP_L */
PINCTRL_PIN(227, "GPP_L_0"),
PINCTRL_PIN(228, "EC_CSME_INTR_OUT"),
PINCTRL_PIN(229, "VISA2CH0_D0"),
PINCTRL_PIN(230, "VISA2CH0_D1"),
PINCTRL_PIN(231, "VISA2CH0_D2"),
PINCTRL_PIN(232, "VISA2CH0_D3"),
PINCTRL_PIN(233, "VISA2CH0_D4"),
PINCTRL_PIN(234, "VISA2CH0_D5"),
PINCTRL_PIN(235, "VISA2CH0_D6"),
PINCTRL_PIN(236, "VISA2CH0_D7"),
PINCTRL_PIN(237, "VISA2CH0_CLK"),
PINCTRL_PIN(238, "VISA2CH1_D0"),
PINCTRL_PIN(239, "VISA2CH1_D1"),
PINCTRL_PIN(240, "VISA2CH1_D2"),
PINCTRL_PIN(241, "VISA2CH1_D3"),
PINCTRL_PIN(242, "VISA2CH1_D4"),
PINCTRL_PIN(243, "VISA2CH1_D5"),
PINCTRL_PIN(244, "VISA2CH1_D6"),
PINCTRL_PIN(245, "VISA2CH1_D7"),
PINCTRL_PIN(246, "VISA2CH1_CLK"),
};
static const struct intel_community lbg_communities[] = {
LBG_COMMUNITY(0, 0, 71),
LBG_COMMUNITY(1, 72, 132),
LBG_COMMUNITY(3, 133, 143),
LBG_COMMUNITY(4, 144, 178),
LBG_COMMUNITY(5, 179, 246),
};
static const struct intel_pinctrl_soc_data lbg_soc_data = {
.pins = lbg_pins,
.npins = ARRAY_SIZE(lbg_pins),
.communities = lbg_communities,
.ncommunities = ARRAY_SIZE(lbg_communities),
};
static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
static struct platform_driver lbg_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "lewisburg-pinctrl",
.acpi_match_table = lbg_pinctrl_acpi_match,
.pm = &lbg_pinctrl_pm_ops,
},
};
module_platform_driver(lbg_pinctrl_driver);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(PINCTRL_INTEL);
|
linux-master
|
drivers/pinctrl/intel/pinctrl-lewisburg.c
|
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