hash
stringlengths 32
32
| doc_id
stringlengths 5
12
| section
stringlengths 4
595
| content
stringlengths 0
6.67M
|
|---|---|---|---|
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.2.1 General | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.2.2 Ancillary equipment | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3 Performance Criteria | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.1 Performance criteria A for continuous phenomena for BS | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.2 Performance criteria B for transient phenomena for BS | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.3 Performance criteria C for BS | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.4 Performance criteria A for continous phenomena for Ancillary equipment | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.5 Performance criteria B for transient phenomena for Ancillary equipment | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.3.6 Performance criteria C for Ancillary equipment | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.4 Applicability overview | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.4.1 Emission | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 7.4.2 Immunity | Common with 3.84 Mcps Chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8 BS conformance testing | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1 Frequency bands and channel arrangement | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.1 General | The information presented in this section is based on a chip rate of 1.28 Mcps. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.2 Frequency bands | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.3 TX–RX frequency separation | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.3.1 Description | No TX-RX frequency separation is required as Time Division Duplex (TDD) is employed. Each subframe of 1.28 Mcps TDD consists of 7 main timeslots (TS0 ~ TS6) where TS0 (before DL to UL switching point) are always allocated DL, the timeslots (at least the first one) before the switching point (vice versa) are allocated UL and the timeslots after the switching point (vice versa) are allocated DL. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.3.2 Explanation of difference | The frame structure for 3.84 Mcps TDD and 1.28 Mcps TDD is different. For 3.84 Mcps TDD, each TDMA frame consists of 15 timeslots where each timeslot can be allocated to either transmit or receive. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4 Channel arrangement | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4.1 Channel spacing | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4.1.1 Background | The roll filter factor is would be 0.22, then we select the nominal bandwidth as 1.6MHz.
Considering the easy co-existence with Wide-band TDD mode, for its 3 times bandwidth would be 4.8, less than the nominal bandwidth of wide band UTRA TDD.
It is just nominal for 1.6MHz, and it is also flexible to adjust the channel raster step 200kHz to narrow as 1.4MHz for strict requirement situations if needed.
Considering the easy to implementation, for too narrow band of the bandwidth would be very difficult to implementation. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4.1.2 Channel spacing | The channel spacing for 1.28 Mcps chip rate option is 1.6MHz. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4.2 Channel raster | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.1.4.3 Channel number | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2 General test conditions and declarations | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.1 Base station classes | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.2 Output power and determination of power class | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.3 Specified frequency range | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.4 Spectrum emission mask | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.5 Adjacent Channel Leakage power Ratio (ACLR) | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.6 Tx spurious emissions | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.6.1 Category of spurious emissions limit | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.6.2 Co-existence with GSM | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.6.3 Co-existence with DCS 1800 | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.6.4 Co-existence with UTRA FDD | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.7 Blocking characteristics | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.8 Test environments | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.9 Interpretation of measurement results | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.10 Selection of configurations for testing | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.11 BS Configurations | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.12 Overview of the conformance test requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.2.13 Format and interpretation of tests | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3 Transmitter characteristics | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.1 General | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2 Maximum output power | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.1 Definition and applicability | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.2 Conformance requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.4.1 Initial conditions | a) Common with the 3.84 Mcps chip rate
b) Common with the 3.84 Mcps chip rate
c) Common with the 3.84 Mcps chip rate
d) For 1.28 Mcps chip rate TDD option, set the parameters of the transmitted signal according to the following table.
Table 8.1: Parameters of the transmitted signal for maximum output power test for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, 3, 4, 5, 6:
transmit, if i is 0,4,5,6;
receive, if i is 1,2,3.
BS output power setting
PRAT
Number of DPCH in each active TS
8
Power of each DPCH
1/8 of Base Station output power
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.4.2 Procedure | 1) Measure thermal power over the 848 active chips of a transmit time slot (this excludes the guard periods), and with a measurement bandwidth of at least 1.6 MHz.
2) Average over TBD time slots.
3) Run steps (1) and (2) for RF channels Low / Mid / High. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.5 Test requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.2.6 Explanation difference | For the 1.28 Mcps chip rate TDD option, one frame(10ms) consists of two subframes(5ms), and one subframe consists of 7 timeslots, the structure of the subframe is shown in section 7.2.1 of TR 25.928. So the number of timeslot i should be 0, 1,…,6. In addition, for the 1.28 Mcps chip rate TDD option, the DL reference measurement channel for 144kbits/s need two timeslots, each consists of 8 DPCH(SF=16).So the number of DPCH in each active TS should be 8.
For the 1.28 Mcps chip rate TDD option, each TS consists of 864 chips, but 16 chips is for Guard Period, so the measuring thermal power should over 848 active chips. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3 Frequency stability | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.1 Definition and applicabilily | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.2 Conformance requirement | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.4.1 Initial conditions | 1) Common with the 3.84 Mcps chip rate
2) Common with the 3.84 Mcps chip rate
3) Common with the 3.84 Mcps chip rate
4) For 1.28 Mcps chip rate TDD option, set the parameters of the transmitted signal according to the following table.
Table 8.2: Parameters of the transmitted signal for Frequency stability test for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, ..., 6:
transmit, if i is 0, 4,5,6;
receive, if i is 1,2,3.
Number of DPCH in each active TS
1
BS output power setting
PRAT
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.4.2 Procedure | 1) Common with 3.84 Mcps chip rate TDD option.
2) Common with 3.84 Mcps chip rate TDD option.
3) Common with 3.84 Mcps chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.3.5 Test requirement | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 9.3.3.6 Explanation difference | For the 1.28 Mcps chip rate TDD option, one frame(10ms) consists of two subframes(5ms), and one subframe consists of 7 timeslots, (the structure of the subframe is shown in section7.2.1 of 3GPP TR 25.928), so the number of timeslot i should be 0, 1,…,6.
The frequency stability is a characteristic of the local oscillator and will not change, if the number of DPCH is varied. In these cases, it is felt that the use of only 1 DPCH will make the measurement easier and, at least for some parameters, more exact. Therefore, it is proposed to specify the test for frequency stability with 1 DPCH only also in the case of 1.28 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4 Output power dynamics | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.1 Inner loop power control | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2 Power control steps | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.1 Definition and applicability | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.2 Conformance requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.4.1 Initial conditions | 1) Common with the 3.84 Mcps chip rate
2) Common with the 3.84 Mcps chip rate
3) For 1.28 Mcps chip rate TDD option, set the initial parameters of the transmitted signal according to the following table.
4) Common with the 3.84 Mcps chip rate
5) Common with the 3.84 Mcps chip rate
Table 8.3: Parameters of the transmitted signal for Power control step test for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, ..., 6:
transmit, if i is 0, 4,5,6;
receive, if i is 1,2,3.
Number of DPCH in each active TS
1
DPCH power
Minimun
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.4.2 Procedure | 1) Common with 3.84 Mcps chip rate TDD option.
2) Set the BS tester to produce a sequence of TPC commands related to the active DPCH. This sequence shall be transmitted to the BS within the time slots TS i=1,2,3, and shall consist of a series of TPC commands with content "Increase Tx power", followed by a series of TPC commands with content "Decrease Tx power". Each of these series should be sufficiently long so that the transmit output power of the active DPCH is controlled to reach its maximum and its minimum, respectively.
3) Measure the power of the active DPCH over the 848 active chips of each time slot TS i=0,4,5,6 (-this excludes the guard period), and with a measurement filter that has a RRC filter response with a roll off = 0,22 and a bandwidth equal to the chip rate. The power is determined by calculating the RMS value of the signal samples at the measurement filter output taken at the decision points.
4) Common with 3.84 Mcps chip rate TDD option.
5) Common with 3.84 Mcps chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.5 Test requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.2.6 Explanation difference | For the 1.28 Mcps chip rate TDD option, one frame(10ms) consists of two subframes(5ms), and one subframe consists of 7 timeslots, (the Structure of subframe is shown in section7.2.1 of 3GPP TR 25.928), so the number of timeslot i should be 0, 1,…,6.
For the 1.28 Mcps chip rate TDD option, each TS consists of 864 chips, but 16 chips is for Guard Period,so the measuring power should over 848 active chips. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3 Power control dynamic range | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.1 Definition and applicability | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.2 Conformance requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.4.1 Initial conditions | 1) Common with the 3.84 Mcps chip rate
2) For 1.28 Mcps chip rate TDD option, set the initial parameters of the transmitted signal according to the following table.
3) Common with the 3.84 Mcps chip rate
4) Common with the 3.84 Mcps chip rate
Table 8.4: Parameters of the transmitted signal for Power control dynamic range test for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, ..., 6:
transmit, if i is 0, 4,5,6;
receive, if i is 1,2,3.
Number of DPCH in each active TS
1
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.4.2 Procedure | 1) Common with 3.84 Mcps chip rate TDD option.
2) Set the BS tester to produce a sequence of TPC commands related to the active DPCH, with content "Increase Tx power". This sequence shall be sufficiently long so that the transmit output power of the active DPCH is controlled to reach its maximum, and shall be transmitted to the BS within the TS i =1,2,3 time slots.
3) Measure the power of the active DPCH over the 848 active chips of each time slot TS i=0,4,5,6 (this excludes the guard period), and with a measurement filter that has a RRC filter response with a roll off = 0,22 and a bandwidth equal to the chip rate. The power is determined by calculating the RMS value of the signal samples at the measurement filter output taken at the decision points.
4) Common with 3.84 Mcps chip rate TDD option.
5) Set the BS tester to produce a sequence of TPC commands related to the active DPCH, with content "Decrease Tx power". This sequence shall be sufficiently long so that the transmit output power of the active DPCH is controlled to reach its minimum, and shall be transmitted to the BS within the time slots TS i=1,2,3.
6) Measure the power of the active DPCH over the 848 active chips of each time slot TS i=0,4,5,6 (this excludes the guard period), and with a measurement filter that has a RRC filter response with a roll off = 0,22 and a bandwidth equal to the chip rate. The power is determined by calculating the RMS value of the signal samples at the measurement filter output taken at the decision points.
7) Common with 3.84 Mcps chip rate TDD option.
8) Common with 3.84 Mcps chip rate TDD option.
9) Common with 3.84 Mcps chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.5 Test requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.3.6 Explanation difference | For the 1.28 Mcps chip rate TDD option, one frame(10ms) consists of two subframes(5ms), and one subframe consists of 7 timeslots, (the structure of the subframe is shown in section7.2.1 of 3GPP TR 25.928), so the number of timeslot i should be 0, 1,…,6.
For the 1.28 Mcps chip rate TDD option, each TS consists of 864 chips, but 16 chips is for Guard Period,so the measuring power should over 848 active chips. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4 Minimum transmit power | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.1 Definition and applicability | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.2 Conformance requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.4.1 Initial conditions | 1) Common with the 3.84 Mcps chip rate
2) For 1.28 Mcps chip rate TDD option, set the parameters of the transmitted signal according to the following table.
3) Common with the 3.84 Mcps chip rate
4) Common with the 3.84 Mcps chip rate
Table 8.5: Parameters of the transmitted signal for Minimum transmit power test for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, 3, 4, 5, 6:
transmit, if i is 0,4,5,6;
receive, if i is 1,2,3.
BS output power setting
PRAT
Number of DPCH in each active TS
8
Power of each DPCH
1/8 of Base Station output power
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.4.2 Procedure | 1) Common with 3.84 Mcps chip rate TDD option.
2) Set the BS tester to produce a sequence of TPC commands related to all active DPCH, with content "Decrease Tx power". This sequence shall be sufficiently long so that the transmit output power of all active DPCH is controlled to reach its minimum, and shall be transmitted to the BS within the time slots TS i=1,2,3(receive time slots of the BS).
3) Measure the power of the BS output signal over the 848 active chips of each time slot TS i=0,4,5,6 (this excludes the guard period), and with a measurement filter that has a RRC filter response with a roll off = 0,22 and a bandwidth equal to the chip rate. The power is determined by calculating the RMS value of the signal samples at the measurement filter output taken at the decision points.
4) Average over TBD time slots.
5) Common with 3.84 Mcps chip rate TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.5 Test requirements | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.4.6 Explanation difference | For the 1.28 Mcps chip rate TDD option, one frame(10ms) consists of two subframes(5ms), and one subframe consists of 7 timeslots, the structure of subframe is shown in Section 7.2.1 of TR 25.928.So the number of timeslot i should be 0, 1,…,6. In addition, for the 1.28 Mcps chip rate TDD option, the DL reference measurement channel for 144kbits/s need two timeslots, each consists of 8 DPCH(SF=16).So the number of DPCH in each active TS should be 8.
For the 1.28 Mcps chip rate TDD option, each TS consists of 864 chips, but 16 chips is for Guard Period,so the measuring thermal power should over 848 active chips. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5 Primary CCPCH power | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.1 Definition and applicabilily | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.2 Conformance requirement | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.3 Test purpose | Common with 3.84 Mcps TDD option. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.4 Method of test | |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.4.1 Initial conditions | 1) Common with the 3.84 Mcps chip rate
2) For 1.28 Mcps chip rate TDD option, set the parameters of the transmitted signal according to the following table.
Table 8.6: Parameters of the BS transmitted signal for Primary CCPCH power testing for 1.28 Mcps chip rate TDD option
Parameter
Value/description
TDD Duty Cycle
TS i; i = 0, 1, 2, ..., 6:
transmit, if i is 0,4,5,6;
receive, if i is 1,2,3.
Time slots carrying PCCPCH
TS 0
BS output power setting
PRAT
Relative power of PCCPCH
1/2 of BS output power
Data content of DPCH
real life
(sufficient irregular) |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.4.2 Procedure | 1) Measure the PCCPCH power in TS 0 by applying the global in-channel Tx test method described in Annex H.
2) Reduce the base station output power by 2 dB, 5 dB and 13 dB, without changing the relative powers of the PCCPCH, and repeat step (1) for each output power setting. |
1cc4b09fd057c9a5cf925fb9b5a5f4e7 | 25.945 | 8.3.4.5.5 Test requirement | Common with 3.84 Mcps TDD option. |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.