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/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <engine/disp.h>
#include <engine/fifo.h>
#include <nvif/class.h>
#include <nvif/event.h>
/*******************************************************************************
* software context
******************************************************************************/
static int
gf100_sw_chan_vblsem_release(struct nvkm_event_ntfy *notify, u32 bits)
{
struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->id]);
struct nvkm_sw *sw = chan->base.sw;
struct nvkm_device *device = sw->engine.subdev.device;
u32 inst = chan->base.fifo->inst->addr >> 12;
nvkm_wr32(device, 0x001718, 0x80000000 | inst);
nvkm_bar_flush(device->bar);
nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
nvkm_wr32(device, 0x060014, chan->vblank.value);
return NVKM_EVENT_DROP;
}
static bool
gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
{
struct nv50_sw_chan *chan = nv50_sw_chan(base);
struct nvkm_engine *engine = chan->base.object.engine;
struct nvkm_device *device = engine->subdev.device;
switch (mthd) {
case 0x0400:
chan->vblank.offset &= 0x00ffffffffULL;
chan->vblank.offset |= (u64)data << 32;
return true;
case 0x0404:
chan->vblank.offset &= 0xff00000000ULL;
chan->vblank.offset |= data;
return true;
case 0x0408:
chan->vblank.value = data;
return true;
case 0x040c:
if (data < device->disp->vblank.index_nr) {
nvkm_event_ntfy_allow(&chan->vblank.notify[data]);
return true;
}
break;
case 0x600: /* MP.PM_UNK000 */
nvkm_wr32(device, 0x419e00, data);
return true;
case 0x644: /* MP.TRAP_WARP_ERROR_EN */
if (!(data & ~0x001ffffe)) {
nvkm_wr32(device, 0x419e44, data);
return true;
}
break;
case 0x6ac: /* MP.PM_UNK0AC */
nvkm_wr32(device, 0x419eac, data);
return true;
default:
break;
}
return false;
}
static const struct nvkm_sw_chan_func
gf100_sw_chan = {
.dtor = nv50_sw_chan_dtor,
.mthd = gf100_sw_chan_mthd,
};
static int
gf100_sw_chan_new(struct nvkm_sw *sw, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct nvkm_disp *disp = sw->engine.subdev.device->disp;
struct nv50_sw_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
*pobject = &chan->base.object;
ret = nvkm_sw_chan_ctor(&gf100_sw_chan, sw, fifoch, oclass,
&chan->base);
if (ret)
return ret;
for (i = 0; disp && i < disp->vblank.index_nr; i++) {
nvkm_event_ntfy_add(&disp->vblank, i, NVKM_DISP_HEAD_EVENT_VBLANK, true,
gf100_sw_chan_vblsem_release, &chan->vblank.notify[i]);
}
return 0;
}
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static const struct nvkm_sw_func
gf100_sw = {
.chan_new = gf100_sw_chan_new,
.sclass = {
{ nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_GF100 } },
{}
}
};
int
gf100_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
{
return nvkm_sw_new_(&gf100_sw, device, type, inst, psw);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include "chan.h"
#include "nvsw.h"
#include <nvif/class.h>
/*******************************************************************************
* software context
******************************************************************************/
static const struct nvkm_sw_chan_func
nv10_sw_chan = {
};
static int
nv10_sw_chan_new(struct nvkm_sw *sw, struct nvkm_chan *fifo,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nvkm_sw_chan *chan;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
*pobject = &chan->object;
return nvkm_sw_chan_ctor(&nv10_sw_chan, sw, fifo, oclass, chan);
}
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static const struct nvkm_sw_func
nv10_sw = {
.chan_new = nv10_sw_chan_new,
.sclass = {
{ nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_NV10 } },
{}
}
};
int
nv10_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
{
return nvkm_sw_new_(&nv10_sw, device, type, inst, psw);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/gpuobj.h>
#include <engine/disp.h>
#include <engine/fifo/chan.h>
#include <subdev/bar.h>
#include <nvif/class.h>
#include <nvif/event.h>
/*******************************************************************************
* software context
******************************************************************************/
static int
nv50_sw_chan_vblsem_release(struct nvkm_event_ntfy *notify, u32 bits)
{
struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), vblank.notify[notify->id]);
struct nvkm_sw *sw = chan->base.sw;
struct nvkm_device *device = sw->engine.subdev.device;
nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12);
nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma);
nvkm_bar_flush(device->bar);
if (device->chipset == 0x50) {
nvkm_wr32(device, 0x001570, chan->vblank.offset);
nvkm_wr32(device, 0x001574, chan->vblank.value);
} else {
nvkm_wr32(device, 0x060010, chan->vblank.offset);
nvkm_wr32(device, 0x060014, chan->vblank.value);
}
return NVKM_EVENT_DROP;
}
static bool
nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
{
struct nv50_sw_chan *chan = nv50_sw_chan(base);
struct nvkm_engine *engine = chan->base.object.engine;
struct nvkm_device *device = engine->subdev.device;
switch (mthd) {
case 0x018c: chan->vblank.ctxdma = data; return true;
case 0x0400: chan->vblank.offset = data; return true;
case 0x0404: chan->vblank.value = data; return true;
case 0x0408:
if (data < device->disp->vblank.index_nr) {
nvkm_event_ntfy_allow(&chan->vblank.notify[data]);
return true;
}
break;
default:
break;
}
return false;
}
void *
nv50_sw_chan_dtor(struct nvkm_sw_chan *base)
{
struct nv50_sw_chan *chan = nv50_sw_chan(base);
int i;
for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
nvkm_event_ntfy_del(&chan->vblank.notify[i]);
return chan;
}
static const struct nvkm_sw_chan_func
nv50_sw_chan = {
.dtor = nv50_sw_chan_dtor,
.mthd = nv50_sw_chan_mthd,
};
static int
nv50_sw_chan_new(struct nvkm_sw *sw, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nvkm_disp *disp = sw->engine.subdev.device->disp;
struct nv50_sw_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
*pobject = &chan->base.object;
ret = nvkm_sw_chan_ctor(&nv50_sw_chan, sw, fifoch, oclass, &chan->base);
if (ret)
return ret;
for (i = 0; disp && i < disp->vblank.index_nr; i++) {
nvkm_event_ntfy_add(&disp->vblank, i, NVKM_DISP_HEAD_EVENT_VBLANK, true,
nv50_sw_chan_vblsem_release, &chan->vblank.notify[i]);
}
return 0;
}
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static const struct nvkm_sw_func
nv50_sw = {
.chan_new = nv50_sw_chan_new,
.sclass = {
{ nvkm_nvsw_new, { -1, -1, NVIF_CLASS_SW_NV50 } },
{}
}
};
int
nv50_sw_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
{
return nvkm_sw_new_(&nv50_sw, device, type, inst, psw);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "nvsw.h"
#include "chan.h"
#include <nvif/if0004.h>
static int
nvkm_nvsw_uevent(struct nvkm_object *object, void *argv, u32 argc, struct nvkm_uevent *uevent)
{
union nv04_nvsw_event_args *args = argv;
if (!uevent)
return 0;
if (argc != sizeof(args->vn))
return -ENOSYS;
return nvkm_uevent_add(uevent, &nvkm_nvsw(object)->chan->event, 0,
NVKM_SW_CHAN_EVENT_PAGE_FLIP, NULL);
}
static int
nvkm_nvsw_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
struct nvkm_nvsw *nvsw = nvkm_nvsw(object);
if (nvsw->func->mthd)
return nvsw->func->mthd(nvsw, mthd, data, size);
return -ENODEV;
}
static const struct nvkm_object_func
nvkm_nvsw_ = {
.mthd = nvkm_nvsw_mthd,
.uevent = nvkm_nvsw_uevent,
};
int
nvkm_nvsw_new_(const struct nvkm_nvsw_func *func, struct nvkm_sw_chan *chan,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_nvsw *nvsw;
if (!(nvsw = kzalloc(sizeof(*nvsw), GFP_KERNEL)))
return -ENOMEM;
*pobject = &nvsw->object;
nvkm_object_ctor(&nvkm_nvsw_, oclass, &nvsw->object);
nvsw->func = func;
nvsw->chan = chan;
return 0;
}
static const struct nvkm_nvsw_func
nvkm_nvsw = {
};
int
nvkm_nvsw_new(struct nvkm_sw_chan *chan, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
return nvkm_nvsw_new_(&nvkm_nvsw, chan, oclass, data, size, pobject);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "priv.h"
#include "chan.h"
#include <engine/fifo.h>
bool
nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data)
{
struct nvkm_sw_chan *chan;
bool handled = false;
unsigned long flags;
spin_lock_irqsave(&sw->engine.lock, flags);
list_for_each_entry(chan, &sw->chan, head) {
if (chan->fifo->id == chid) {
handled = nvkm_sw_chan_mthd(chan, subc, mthd, data);
list_del(&chan->head);
list_add(&chan->head, &sw->chan);
break;
}
}
spin_unlock_irqrestore(&sw->engine.lock, flags);
return handled;
}
static int
nvkm_sw_oclass_new(const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_sw_chan *chan = nvkm_sw_chan(oclass->parent);
const struct nvkm_sw_chan_sclass *sclass = oclass->engn;
return sclass->ctor(chan, oclass, data, size, pobject);
}
static int
nvkm_sw_oclass_get(struct nvkm_oclass *oclass, int index)
{
struct nvkm_sw *sw = nvkm_sw(oclass->engine);
int c = 0;
while (sw->func->sclass[c].ctor) {
if (c++ == index) {
oclass->engn = &sw->func->sclass[index];
oclass->base = sw->func->sclass[index].base;
oclass->base.ctor = nvkm_sw_oclass_new;
return index;
}
}
return c;
}
static int
nvkm_sw_cclass_get(struct nvkm_chan *fifoch, const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct nvkm_sw *sw = nvkm_sw(oclass->engine);
return sw->func->chan_new(sw, fifoch, oclass, pobject);
}
static void *
nvkm_sw_dtor(struct nvkm_engine *engine)
{
return nvkm_sw(engine);
}
static const struct nvkm_engine_func
nvkm_sw = {
.dtor = nvkm_sw_dtor,
.fifo.cclass = nvkm_sw_cclass_get,
.fifo.sclass = nvkm_sw_oclass_get,
};
int
nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_sw **psw)
{
struct nvkm_sw *sw;
if (!(sw = *psw = kzalloc(sizeof(*sw), GFP_KERNEL)))
return -ENOMEM;
INIT_LIST_HEAD(&sw->chan);
sw->func = func;
return nvkm_engine_ctor(&nvkm_sw, device, type, inst, true, &sw->engine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv31.h"
#include <subdev/instmem.h>
#include <nvif/class.h>
bool
nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
struct nvkm_instmem *imem = device->imem;
struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
u32 inst = data << 4;
u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;
/* only allow linear DMA objects */
if (!(dma0 & 0x00002000)) {
nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n",
inst, dma0, dma1, dma2);
return false;
}
if (mthd == 0x0190) {
/* DMA_CMD */
nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nvkm_wr32(device, 0x00b334, base);
nvkm_wr32(device, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nvkm_wr32(device, 0x00b360, base);
nvkm_wr32(device, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000)
return false;
nvkm_wr32(device, 0x00b370, base);
nvkm_wr32(device, 0x00b374, size);
}
return true;
}
static const struct nv31_mpeg_func
nv40_mpeg = {
.mthd_dma = nv40_mpeg_mthd_dma,
};
int
nv40_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv40_mpeg, device, type, inst, pmpeg);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, engine)
#include "priv.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <nvif/class.h>
struct nv44_mpeg {
struct nvkm_engine engine;
struct list_head chan;
};
/*******************************************************************************
* PMPEG context
******************************************************************************/
#define nv44_mpeg_chan(p) container_of((p), struct nv44_mpeg_chan, object)
struct nv44_mpeg_chan {
struct nvkm_object object;
struct nv44_mpeg *mpeg;
struct nvkm_chan *fifo;
struct list_head head;
u32 inst;
};
static int
nv44_mpeg_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
int ret = nvkm_gpuobj_new(chan->object.engine->subdev.device, 264 * 4,
align, true, parent, pgpuobj);
if (ret == 0) {
chan->inst = (*pgpuobj)->addr;
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1);
nvkm_done(*pgpuobj);
}
return ret;
}
static int
nv44_mpeg_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
struct nv44_mpeg *mpeg = chan->mpeg;
struct nvkm_device *device = mpeg->engine.subdev.device;
u32 inst = 0x80000000 | (chan->inst >> 4);
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000);
if (nvkm_rd32(device, 0x00b318) == inst)
nvkm_mask(device, 0x00b318, 0x80000000, 0x00000000);
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
return 0;
}
static void *
nv44_mpeg_chan_dtor(struct nvkm_object *object)
{
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
struct nv44_mpeg *mpeg = chan->mpeg;
unsigned long flags;
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_del(&chan->head);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return chan;
}
static const struct nvkm_object_func
nv44_mpeg_chan = {
.dtor = nv44_mpeg_chan_dtor,
.fini = nv44_mpeg_chan_fini,
.bind = nv44_mpeg_chan_bind,
};
static int
nv44_mpeg_chan_new(struct nvkm_chan *fifoch, const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct nv44_mpeg *mpeg = nv44_mpeg(oclass->engine);
struct nv44_mpeg_chan *chan;
unsigned long flags;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv44_mpeg_chan, oclass, &chan->object);
chan->mpeg = mpeg;
chan->fifo = fifoch;
*pobject = &chan->object;
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_add(&chan->head, &mpeg->chan);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return 0;
}
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
static bool
nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data)
{
switch (mthd) {
case 0x190:
case 0x1a0:
case 0x1b0:
return nv40_mpeg_mthd_dma(device, mthd, data);
default:
break;
}
return false;
}
static void
nv44_mpeg_intr(struct nvkm_engine *engine)
{
struct nv44_mpeg *mpeg = nv44_mpeg(engine);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
struct nvkm_device *device = subdev->device;
struct nv44_mpeg_chan *temp, *chan = NULL;
unsigned long flags;
u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
u32 stat = nvkm_rd32(device, 0x00b100);
u32 type = nvkm_rd32(device, 0x00b230);
u32 mthd = nvkm_rd32(device, 0x00b234);
u32 data = nvkm_rd32(device, 0x00b238);
u32 show = stat;
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_for_each_entry(temp, &mpeg->chan, head) {
if (temp->inst >> 4 == inst) {
chan = temp;
list_del(&chan->head);
list_add(&chan->head, &mpeg->chan);
break;
}
}
if (stat & 0x01000000) {
/* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) {
nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000;
}
if (type == 0x00000010) {
if (nv44_mpeg_mthd(subdev->device, mthd, data))
show &= ~0x01000000;
}
}
nvkm_wr32(device, 0x00b100, stat);
nvkm_wr32(device, 0x00b230, 0x00000001);
if (show) {
nvkm_error(subdev, "ch %d [%08x %s] %08x %08x %08x %08x\n",
chan ? chan->fifo->id : -1, inst << 4,
chan ? chan->fifo->name : "unknown",
stat, type, mthd, data);
}
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
}
static const struct nvkm_engine_func
nv44_mpeg = {
.init = nv31_mpeg_init,
.intr = nv44_mpeg_intr,
.tile = nv31_mpeg_tile,
.fifo.cclass = nv44_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
int
nv44_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
struct nv44_mpeg *mpeg;
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
return -ENOMEM;
INIT_LIST_HEAD(&mpeg->chan);
*pmpeg = &mpeg->engine;
return nvkm_engine_ctor(&nv44_mpeg, device, type, inst, true, &mpeg->engine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv31.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
#include <nvif/class.h>
/*******************************************************************************
* MPEG object classes
******************************************************************************/
static int
nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align,
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm_done(*pgpuobj);
}
return ret;
}
const struct nvkm_object_func
nv31_mpeg_object = {
.bind = nv31_mpeg_object_bind,
};
/*******************************************************************************
* PMPEG context
******************************************************************************/
static void *
nv31_mpeg_chan_dtor(struct nvkm_object *object)
{
struct nv31_mpeg_chan *chan = nv31_mpeg_chan(object);
struct nv31_mpeg *mpeg = chan->mpeg;
unsigned long flags;
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (mpeg->chan == chan)
mpeg->chan = NULL;
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return chan;
}
static const struct nvkm_object_func
nv31_mpeg_chan = {
.dtor = nv31_mpeg_chan_dtor,
};
int
nv31_mpeg_chan_new(struct nvkm_chan *fifoch, const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine);
struct nv31_mpeg_chan *chan;
unsigned long flags;
int ret = -EBUSY;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv31_mpeg_chan, oclass, &chan->object);
chan->mpeg = mpeg;
chan->fifo = fifoch;
*pobject = &chan->object;
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (!mpeg->chan) {
mpeg->chan = chan;
ret = 0;
}
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return ret;
}
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
void
nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
{
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
struct nvkm_device *device = mpeg->engine.subdev.device;
nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr);
}
static bool
nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
u32 inst = data << 4;
u32 dma0 = nvkm_rd32(device, 0x700000 + inst);
u32 dma1 = nvkm_rd32(device, 0x700004 + inst);
u32 dma2 = nvkm_rd32(device, 0x700008 + inst);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;
/* only allow linear DMA objects */
if (!(dma0 & 0x00002000)) {
nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n",
inst, dma0, dma1, dma2);
return false;
}
if (mthd == 0x0190) {
/* DMA_CMD */
nvkm_mask(device, 0x00b300, 0x00010000,
(dma0 & 0x00030000) ? 0x00010000 : 0);
nvkm_wr32(device, 0x00b334, base);
nvkm_wr32(device, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nvkm_mask(device, 0x00b300, 0x00020000,
(dma0 & 0x00030000) ? 0x00020000 : 0);
nvkm_wr32(device, 0x00b360, base);
nvkm_wr32(device, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000)
return false;
nvkm_wr32(device, 0x00b370, base);
nvkm_wr32(device, 0x00b374, size);
}
return true;
}
static bool
nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data)
{
struct nvkm_device *device = mpeg->engine.subdev.device;
switch (mthd) {
case 0x190:
case 0x1a0:
case 0x1b0:
return mpeg->func->mthd_dma(device, mthd, data);
default:
break;
}
return false;
}
static void
nv31_mpeg_intr(struct nvkm_engine *engine)
{
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x00b100);
u32 type = nvkm_rd32(device, 0x00b230);
u32 mthd = nvkm_rd32(device, 0x00b234);
u32 data = nvkm_rd32(device, 0x00b238);
u32 show = stat;
unsigned long flags;
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) {
nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000;
}
if (type == 0x00000010) {
if (nv31_mpeg_mthd(mpeg, mthd, data))
show &= ~0x01000000;
}
}
nvkm_wr32(device, 0x00b100, stat);
nvkm_wr32(device, 0x00b230, 0x00000001);
if (show) {
nvkm_error(subdev, "ch %d [%s] %08x %08x %08x %08x\n",
mpeg->chan ? mpeg->chan->fifo->id : -1,
mpeg->chan ? mpeg->chan->fifo->name :
"unknown", stat, type, mthd, data);
}
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
}
int
nv31_mpeg_init(struct nvkm_engine *mpeg)
{
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
/* VPE init */
nvkm_wr32(device, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
nvkm_wr32(device, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
/* PMPEG init */
nvkm_wr32(device, 0x00b32c, 0x00000000);
nvkm_wr32(device, 0x00b314, 0x00000100);
nvkm_wr32(device, 0x00b220, 0x00000031);
nvkm_wr32(device, 0x00b300, 0x02001ec1);
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
nvkm_wr32(device, 0x00b100, 0xffffffff);
nvkm_wr32(device, 0x00b140, 0xffffffff);
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x00b200) & 0x00000001))
break;
) < 0) {
nvkm_error(subdev, "timeout %08x\n",
nvkm_rd32(device, 0x00b200));
return -EBUSY;
}
return 0;
}
static void *
nv31_mpeg_dtor(struct nvkm_engine *engine)
{
return nv31_mpeg(engine);
}
static const struct nvkm_engine_func
nv31_mpeg_ = {
.dtor = nv31_mpeg_dtor,
.init = nv31_mpeg_init,
.intr = nv31_mpeg_intr,
.tile = nv31_mpeg_tile,
.fifo.cclass = nv31_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
int
nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg)
{
struct nv31_mpeg *mpeg;
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
return -ENOMEM;
mpeg->func = func;
*pmpeg = &mpeg->engine;
return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine);
}
static const struct nv31_mpeg_func
nv31_mpeg = {
.mthd_dma = nv31_mpeg_mthd_dma,
};
int
nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <core/gpuobj.h>
#include <core/object.h>
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PMPEG context
******************************************************************************/
static int
nv50_mpeg_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 128 * 4,
align, true, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1);
nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c);
nvkm_done(*pgpuobj);
}
return ret;
}
const struct nvkm_object_func
nv50_mpeg_cclass = {
.bind = nv50_mpeg_cclass_bind,
};
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
void
nv50_mpeg_intr(struct nvkm_engine *mpeg)
{
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x00b100);
u32 type = nvkm_rd32(device, 0x00b230);
u32 mthd = nvkm_rd32(device, 0x00b234);
u32 data = nvkm_rd32(device, 0x00b238);
u32 show = stat;
if (stat & 0x01000000) {
/* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) {
nvkm_wr32(device, 0x00b308, 0x00000100);
show &= ~0x01000000;
}
}
if (show) {
nvkm_info(subdev, "%08x %08x %08x %08x\n",
stat, type, mthd, data);
}
nvkm_wr32(device, 0x00b100, stat);
nvkm_wr32(device, 0x00b230, 0x00000001);
}
int
nv50_mpeg_init(struct nvkm_engine *mpeg)
{
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
nvkm_wr32(device, 0x00b32c, 0x00000000);
nvkm_wr32(device, 0x00b314, 0x00000100);
nvkm_wr32(device, 0x00b0e0, 0x0000001a);
nvkm_wr32(device, 0x00b220, 0x00000044);
nvkm_wr32(device, 0x00b300, 0x00801ec1);
nvkm_wr32(device, 0x00b390, 0x00000000);
nvkm_wr32(device, 0x00b394, 0x00000000);
nvkm_wr32(device, 0x00b398, 0x00000000);
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
nvkm_wr32(device, 0x00b100, 0xffffffff);
nvkm_wr32(device, 0x00b140, 0xffffffff);
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x00b200) & 0x00000001))
break;
) < 0) {
nvkm_error(subdev, "timeout %08x\n",
nvkm_rd32(device, 0x00b200));
return -EBUSY;
}
return 0;
}
static const struct nvkm_engine_func
nv50_mpeg = {
.init = nv50_mpeg_init,
.intr = nv50_mpeg_intr,
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
int
nv50_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nvkm_engine_new_(&nv50_mpeg, device, type, inst, true, pmpeg);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_engine_func
g84_mpeg = {
.init = nv50_mpeg_init,
.intr = nv50_mpeg_intr,
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, G82_MPEG, &nv31_mpeg_object },
{}
}
};
int
g84_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pmpeg)
{
return nvkm_engine_new_(&g84_mpeg, device, type, inst, true, pmpeg);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
u64
nv40_gr_units(struct nvkm_gr *gr)
{
return nvkm_rd32(gr->engine.subdev.device, 0x1540);
}
/*******************************************************************************
* Graphics object classes
******************************************************************************/
static int
nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align,
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
#ifdef __BIG_ENDIAN
nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000);
#endif
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
nvkm_done(*pgpuobj);
}
return ret;
}
const struct nvkm_object_func
nv40_gr_object = {
.bind = nv40_gr_object_bind,
};
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static int
nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
struct nv40_gr_chan *chan = nv40_gr_chan(object);
struct nv40_gr *gr = chan->gr;
int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
align, true, parent, pgpuobj);
if (ret == 0) {
chan->inst = (*pgpuobj)->addr;
nvkm_kmap(*pgpuobj);
nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4);
nvkm_done(*pgpuobj);
}
return ret;
}
static int
nv40_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv40_gr_chan *chan = nv40_gr_chan(object);
struct nv40_gr *gr = chan->gr;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 inst = 0x01000000 | chan->inst >> 4;
int ret = 0;
nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
if (nvkm_rd32(device, 0x40032c) == inst) {
if (suspend) {
nvkm_wr32(device, 0x400720, 0x00000000);
nvkm_wr32(device, 0x400784, inst);
nvkm_mask(device, 0x400310, 0x00000020, 0x00000020);
nvkm_mask(device, 0x400304, 0x00000001, 0x00000001);
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x400300) & 0x00000001))
break;
) < 0) {
u32 insn = nvkm_rd32(device, 0x400308);
nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
ret = -EBUSY;
}
}
nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000);
}
if (nvkm_rd32(device, 0x400330) == inst)
nvkm_mask(device, 0x400330, 0x01000000, 0x00000000);
nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
return ret;
}
static void *
nv40_gr_chan_dtor(struct nvkm_object *object)
{
struct nv40_gr_chan *chan = nv40_gr_chan(object);
unsigned long flags;
spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
list_del(&chan->head);
spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
return chan;
}
static const struct nvkm_object_func
nv40_gr_chan = {
.dtor = nv40_gr_chan_dtor,
.fini = nv40_gr_chan_fini,
.bind = nv40_gr_chan_bind,
};
int
nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv40_gr *gr = nv40_gr(base);
struct nv40_gr_chan *chan;
unsigned long flags;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->fifo = fifoch;
*pobject = &chan->object;
spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
list_add(&chan->head, &gr->chan);
spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static void
nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
struct nv40_gr *gr = nv40_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fifo *fifo = device->fifo;
unsigned long flags;
nvkm_fifo_pause(fifo, &flags);
nv04_gr_idle(&gr->base);
switch (device->chipset) {
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x45:
nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
switch (device->chipset) {
case 0x40:
case 0x45:
nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
case 0x41:
case 0x42:
case 0x43:
nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
default:
break;
}
break;
case 0x47:
case 0x49:
case 0x4b:
nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
break;
default:
WARN_ON(1);
break;
}
nvkm_fifo_start(fifo, &flags);
}
void
nv40_gr_intr(struct nvkm_gr *base)
{
struct nv40_gr *gr = nv40_gr(base);
struct nv40_gr_chan *temp, *chan = NULL;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff;
u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
spin_lock_irqsave(&gr->base.engine.lock, flags);
list_for_each_entry(temp, &gr->chan, head) {
if (temp->inst >> 4 == inst) {
chan = temp;
list_del(&chan->head);
list_add(&chan->head, &gr->chan);
break;
}
}
if (stat & NV_PGRAPH_INTR_ERROR) {
if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
nvkm_mask(device, 0x402000, 0, 0);
}
}
nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%08x %s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta,
chan ? chan->fifo->id : -1, inst << 4,
chan ? chan->fifo->name : "unknown",
subc, class, mthd, data);
}
spin_unlock_irqrestore(&gr->base.engine.lock, flags);
}
int
nv40_gr_init(struct nvkm_gr *base)
{
struct nv40_gr *gr = nv40_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret, i, j;
u32 vramsz;
/* generate and upload context program */
ret = nv40_grctx_init(device, &gr->size);
if (ret)
return ret;
/* No context present currently */
nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
j = nvkm_rd32(device, 0x1540) & 0xff;
if (j) {
for (i = 0; !(j & 1); j >>= 1, i++)
;
nvkm_wr32(device, 0x405000, i);
}
if (device->chipset == 0x40) {
nvkm_wr32(device, 0x4009b0, 0x83280fff);
nvkm_wr32(device, 0x4009b4, 0x000000a0);
} else {
nvkm_wr32(device, 0x400820, 0x83280eff);
nvkm_wr32(device, 0x400824, 0x000000a0);
}
switch (device->chipset) {
case 0x40:
case 0x45:
nvkm_wr32(device, 0x4009b8, 0x0078e366);
nvkm_wr32(device, 0x4009bc, 0x0000014c);
break;
case 0x41:
case 0x42: /* pciid also 0x00Cx */
/* case 0x0120: XXX (pciid) */
nvkm_wr32(device, 0x400828, 0x007596ff);
nvkm_wr32(device, 0x40082c, 0x00000108);
break;
case 0x43:
nvkm_wr32(device, 0x400828, 0x0072cb77);
nvkm_wr32(device, 0x40082c, 0x00000108);
break;
case 0x44:
case 0x46: /* G72 */
case 0x4a:
case 0x4c: /* G7x-based C51 */
case 0x4e:
nvkm_wr32(device, 0x400860, 0);
nvkm_wr32(device, 0x400864, 0);
break;
case 0x47: /* G70 */
case 0x49: /* G71 */
case 0x4b: /* G73 */
nvkm_wr32(device, 0x400828, 0x07830610);
nvkm_wr32(device, 0x40082c, 0x0000016A);
break;
default:
break;
}
nvkm_wr32(device, 0x400b38, 0x2ffff800);
nvkm_wr32(device, 0x400b3c, 0x00006000);
/* Tiling related stuff. */
switch (device->chipset) {
case 0x44:
case 0x4a:
nvkm_wr32(device, 0x400bc4, 0x1003d888);
nvkm_wr32(device, 0x400bbc, 0xb7a7b500);
break;
case 0x46:
nvkm_wr32(device, 0x400bc4, 0x0000e024);
nvkm_wr32(device, 0x400bbc, 0xb7a7b520);
break;
case 0x4c:
case 0x4e:
case 0x67:
nvkm_wr32(device, 0x400bc4, 0x1003d888);
nvkm_wr32(device, 0x400bbc, 0xb7a7b540);
break;
default:
break;
}
/* begin RAM config */
vramsz = device->func->resource_size(device, 1) - 1;
switch (device->chipset) {
case 0x40:
nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204));
nvkm_wr32(device, 0x400820, 0);
nvkm_wr32(device, 0x400824, 0);
nvkm_wr32(device, 0x400864, vramsz);
nvkm_wr32(device, 0x400868, vramsz);
break;
default:
switch (device->chipset) {
case 0x41:
case 0x42:
case 0x43:
case 0x45:
case 0x4e:
case 0x44:
case 0x4a:
nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204));
break;
default:
nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204));
break;
}
nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204));
nvkm_wr32(device, 0x400840, 0);
nvkm_wr32(device, 0x400844, 0);
nvkm_wr32(device, 0x4008A0, vramsz);
nvkm_wr32(device, 0x4008A4, vramsz);
break;
}
return 0;
}
int
nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv40_gr *gr;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
*pgr = &gr->base;
INIT_LIST_HEAD(&gr->chan);
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
nv40_gr = {
.init = nv40_gr_init,
.intr = nv40_gr_intr,
.tile = nv40_gr_tile,
.units = nv40_gr_units,
.chan_new = nv40_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv40_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv40_gr_object }, /* null */
{ -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv40_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv40_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
{ -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
{ -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
{ -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
{ -1, -1, 0x4097, &nv40_gr_object }, /* curie */
{}
}
};
int
nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv40_gr_new_(&nv40_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c |
/*
* Copyright 2017 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gp107_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x300,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gp100_grctx_generate_attrib_cb,
.attrib = gp102_grctx_generate_attrib,
.attrib_nr_max = 0x15de,
.attrib_nr = 0x540,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xe94,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.tpc_mask = gm200_grctx_generate_tpc_mask,
.smid_config = gp100_grctx_generate_smid_config,
.r419a3c = gm200_grctx_generate_r419a3c,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp107.c |
/*
* Copyright 2007 Stephane Marchesin
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
static u32
nv04_gr_ctx_regs[] = {
0x0040053c,
0x00400544,
0x00400540,
0x00400548,
NV04_PGRAPH_CTX_SWITCH1,
NV04_PGRAPH_CTX_SWITCH2,
NV04_PGRAPH_CTX_SWITCH3,
NV04_PGRAPH_CTX_SWITCH4,
NV04_PGRAPH_CTX_CACHE1,
NV04_PGRAPH_CTX_CACHE2,
NV04_PGRAPH_CTX_CACHE3,
NV04_PGRAPH_CTX_CACHE4,
0x00400184,
0x004001a4,
0x004001c4,
0x004001e4,
0x00400188,
0x004001a8,
0x004001c8,
0x004001e8,
0x0040018c,
0x004001ac,
0x004001cc,
0x004001ec,
0x00400190,
0x004001b0,
0x004001d0,
0x004001f0,
0x00400194,
0x004001b4,
0x004001d4,
0x004001f4,
0x00400198,
0x004001b8,
0x004001d8,
0x004001f8,
0x0040019c,
0x004001bc,
0x004001dc,
0x004001fc,
0x00400174,
NV04_PGRAPH_DMA_START_0,
NV04_PGRAPH_DMA_START_1,
NV04_PGRAPH_DMA_LENGTH,
NV04_PGRAPH_DMA_MISC,
NV04_PGRAPH_DMA_PITCH,
NV04_PGRAPH_BOFFSET0,
NV04_PGRAPH_BBASE0,
NV04_PGRAPH_BLIMIT0,
NV04_PGRAPH_BOFFSET1,
NV04_PGRAPH_BBASE1,
NV04_PGRAPH_BLIMIT1,
NV04_PGRAPH_BOFFSET2,
NV04_PGRAPH_BBASE2,
NV04_PGRAPH_BLIMIT2,
NV04_PGRAPH_BOFFSET3,
NV04_PGRAPH_BBASE3,
NV04_PGRAPH_BLIMIT3,
NV04_PGRAPH_BOFFSET4,
NV04_PGRAPH_BBASE4,
NV04_PGRAPH_BLIMIT4,
NV04_PGRAPH_BOFFSET5,
NV04_PGRAPH_BBASE5,
NV04_PGRAPH_BLIMIT5,
NV04_PGRAPH_BPITCH0,
NV04_PGRAPH_BPITCH1,
NV04_PGRAPH_BPITCH2,
NV04_PGRAPH_BPITCH3,
NV04_PGRAPH_BPITCH4,
NV04_PGRAPH_SURFACE,
NV04_PGRAPH_STATE,
NV04_PGRAPH_BSWIZZLE2,
NV04_PGRAPH_BSWIZZLE5,
NV04_PGRAPH_BPIXEL,
NV04_PGRAPH_NOTIFY,
NV04_PGRAPH_PATT_COLOR0,
NV04_PGRAPH_PATT_COLOR1,
NV04_PGRAPH_PATT_COLORRAM+0x00,
NV04_PGRAPH_PATT_COLORRAM+0x04,
NV04_PGRAPH_PATT_COLORRAM+0x08,
NV04_PGRAPH_PATT_COLORRAM+0x0c,
NV04_PGRAPH_PATT_COLORRAM+0x10,
NV04_PGRAPH_PATT_COLORRAM+0x14,
NV04_PGRAPH_PATT_COLORRAM+0x18,
NV04_PGRAPH_PATT_COLORRAM+0x1c,
NV04_PGRAPH_PATT_COLORRAM+0x20,
NV04_PGRAPH_PATT_COLORRAM+0x24,
NV04_PGRAPH_PATT_COLORRAM+0x28,
NV04_PGRAPH_PATT_COLORRAM+0x2c,
NV04_PGRAPH_PATT_COLORRAM+0x30,
NV04_PGRAPH_PATT_COLORRAM+0x34,
NV04_PGRAPH_PATT_COLORRAM+0x38,
NV04_PGRAPH_PATT_COLORRAM+0x3c,
NV04_PGRAPH_PATT_COLORRAM+0x40,
NV04_PGRAPH_PATT_COLORRAM+0x44,
NV04_PGRAPH_PATT_COLORRAM+0x48,
NV04_PGRAPH_PATT_COLORRAM+0x4c,
NV04_PGRAPH_PATT_COLORRAM+0x50,
NV04_PGRAPH_PATT_COLORRAM+0x54,
NV04_PGRAPH_PATT_COLORRAM+0x58,
NV04_PGRAPH_PATT_COLORRAM+0x5c,
NV04_PGRAPH_PATT_COLORRAM+0x60,
NV04_PGRAPH_PATT_COLORRAM+0x64,
NV04_PGRAPH_PATT_COLORRAM+0x68,
NV04_PGRAPH_PATT_COLORRAM+0x6c,
NV04_PGRAPH_PATT_COLORRAM+0x70,
NV04_PGRAPH_PATT_COLORRAM+0x74,
NV04_PGRAPH_PATT_COLORRAM+0x78,
NV04_PGRAPH_PATT_COLORRAM+0x7c,
NV04_PGRAPH_PATT_COLORRAM+0x80,
NV04_PGRAPH_PATT_COLORRAM+0x84,
NV04_PGRAPH_PATT_COLORRAM+0x88,
NV04_PGRAPH_PATT_COLORRAM+0x8c,
NV04_PGRAPH_PATT_COLORRAM+0x90,
NV04_PGRAPH_PATT_COLORRAM+0x94,
NV04_PGRAPH_PATT_COLORRAM+0x98,
NV04_PGRAPH_PATT_COLORRAM+0x9c,
NV04_PGRAPH_PATT_COLORRAM+0xa0,
NV04_PGRAPH_PATT_COLORRAM+0xa4,
NV04_PGRAPH_PATT_COLORRAM+0xa8,
NV04_PGRAPH_PATT_COLORRAM+0xac,
NV04_PGRAPH_PATT_COLORRAM+0xb0,
NV04_PGRAPH_PATT_COLORRAM+0xb4,
NV04_PGRAPH_PATT_COLORRAM+0xb8,
NV04_PGRAPH_PATT_COLORRAM+0xbc,
NV04_PGRAPH_PATT_COLORRAM+0xc0,
NV04_PGRAPH_PATT_COLORRAM+0xc4,
NV04_PGRAPH_PATT_COLORRAM+0xc8,
NV04_PGRAPH_PATT_COLORRAM+0xcc,
NV04_PGRAPH_PATT_COLORRAM+0xd0,
NV04_PGRAPH_PATT_COLORRAM+0xd4,
NV04_PGRAPH_PATT_COLORRAM+0xd8,
NV04_PGRAPH_PATT_COLORRAM+0xdc,
NV04_PGRAPH_PATT_COLORRAM+0xe0,
NV04_PGRAPH_PATT_COLORRAM+0xe4,
NV04_PGRAPH_PATT_COLORRAM+0xe8,
NV04_PGRAPH_PATT_COLORRAM+0xec,
NV04_PGRAPH_PATT_COLORRAM+0xf0,
NV04_PGRAPH_PATT_COLORRAM+0xf4,
NV04_PGRAPH_PATT_COLORRAM+0xf8,
NV04_PGRAPH_PATT_COLORRAM+0xfc,
NV04_PGRAPH_PATTERN,
0x0040080c,
NV04_PGRAPH_PATTERN_SHAPE,
0x00400600,
NV04_PGRAPH_ROP3,
NV04_PGRAPH_CHROMA,
NV04_PGRAPH_BETA_AND,
NV04_PGRAPH_BETA_PREMULT,
NV04_PGRAPH_CONTROL0,
NV04_PGRAPH_CONTROL1,
NV04_PGRAPH_CONTROL2,
NV04_PGRAPH_BLEND,
NV04_PGRAPH_STORED_FMT,
NV04_PGRAPH_SOURCE_COLOR,
0x00400560,
0x00400568,
0x00400564,
0x0040056c,
0x00400400,
0x00400480,
0x00400404,
0x00400484,
0x00400408,
0x00400488,
0x0040040c,
0x0040048c,
0x00400410,
0x00400490,
0x00400414,
0x00400494,
0x00400418,
0x00400498,
0x0040041c,
0x0040049c,
0x00400420,
0x004004a0,
0x00400424,
0x004004a4,
0x00400428,
0x004004a8,
0x0040042c,
0x004004ac,
0x00400430,
0x004004b0,
0x00400434,
0x004004b4,
0x00400438,
0x004004b8,
0x0040043c,
0x004004bc,
0x00400440,
0x004004c0,
0x00400444,
0x004004c4,
0x00400448,
0x004004c8,
0x0040044c,
0x004004cc,
0x00400450,
0x004004d0,
0x00400454,
0x004004d4,
0x00400458,
0x004004d8,
0x0040045c,
0x004004dc,
0x00400460,
0x004004e0,
0x00400464,
0x004004e4,
0x00400468,
0x004004e8,
0x0040046c,
0x004004ec,
0x00400470,
0x004004f0,
0x00400474,
0x004004f4,
0x00400478,
0x004004f8,
0x0040047c,
0x004004fc,
0x00400534,
0x00400538,
0x00400514,
0x00400518,
0x0040051c,
0x00400520,
0x00400524,
0x00400528,
0x0040052c,
0x00400530,
0x00400d00,
0x00400d40,
0x00400d80,
0x00400d04,
0x00400d44,
0x00400d84,
0x00400d08,
0x00400d48,
0x00400d88,
0x00400d0c,
0x00400d4c,
0x00400d8c,
0x00400d10,
0x00400d50,
0x00400d90,
0x00400d14,
0x00400d54,
0x00400d94,
0x00400d18,
0x00400d58,
0x00400d98,
0x00400d1c,
0x00400d5c,
0x00400d9c,
0x00400d20,
0x00400d60,
0x00400da0,
0x00400d24,
0x00400d64,
0x00400da4,
0x00400d28,
0x00400d68,
0x00400da8,
0x00400d2c,
0x00400d6c,
0x00400dac,
0x00400d30,
0x00400d70,
0x00400db0,
0x00400d34,
0x00400d74,
0x00400db4,
0x00400d38,
0x00400d78,
0x00400db8,
0x00400d3c,
0x00400d7c,
0x00400dbc,
0x00400590,
0x00400594,
0x00400598,
0x0040059c,
0x004005a8,
0x004005ac,
0x004005b0,
0x004005b4,
0x004005c0,
0x004005c4,
0x004005c8,
0x004005cc,
0x004005d0,
0x004005d4,
0x004005d8,
0x004005dc,
0x004005e0,
NV04_PGRAPH_PASSTHRU_0,
NV04_PGRAPH_PASSTHRU_1,
NV04_PGRAPH_PASSTHRU_2,
NV04_PGRAPH_DVD_COLORFMT,
NV04_PGRAPH_SCALED_FORMAT,
NV04_PGRAPH_MISC24_0,
NV04_PGRAPH_MISC24_1,
NV04_PGRAPH_MISC24_2,
0x00400500,
0x00400504,
NV04_PGRAPH_VALID1,
NV04_PGRAPH_VALID2,
NV04_PGRAPH_DEBUG_3
};
#define nv04_gr(p) container_of((p), struct nv04_gr, base)
struct nv04_gr {
struct nvkm_gr base;
struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
#define nv04_gr_chan(p) container_of((p), struct nv04_gr_chan, object)
struct nv04_gr_chan {
struct nvkm_object object;
struct nv04_gr *gr;
int chid;
u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
};
/*******************************************************************************
* Graphics object classes
******************************************************************************/
/*
* Software methods, why they are needed, and how they all work:
*
* NV04 and NV05 keep most of the state in PGRAPH context itself, but some
* 2d engine settings are kept inside the grobjs themselves. The grobjs are
* 3 words long on both. grobj format on NV04 is:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surf3d valid [for tex_tri and multitex_tri only]
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* On NV05 it's:
*
* word 0:
* - bits 0-7: class
* - bit 12: color key active
* - bit 13: clip rect active
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
* NV03_CONTEXT_SURFACE_DST].
* - bits 15-17: 2d operation [aka patch config]
* - bits 20-22: dither mode
* - bit 24: patch valid [enables rendering using this object]
* - bit 25: surface_dst/surface_color/surf2d/surf3d valid
* - bit 26: surface_src/surface_zeta valid
* - bit 27: pattern valid
* - bit 28: rop valid
* - bit 29: beta1 valid
* - bit 30: beta4 valid
* word 1:
* - bits 0-1: mono format
* - bits 8-13: color format
* - bits 16-31: DMA_NOTIFY instance
* word 2:
* - bits 0-15: DMA_A instance
* - bits 16-31: DMA_B instance
*
* NV05 will set/unset the relevant valid bits when you poke the relevant
* object-binding methods with object of the proper type, or with the NULL
* type. It'll only allow rendering using the grobj if all needed objects
* are bound. The needed set of objects depends on selected operation: for
* example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
*
* NV04 doesn't have these methods implemented at all, and doesn't have the
* relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
* is set. So we have to emulate them in software, internally keeping the
* same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
* but the last word isn't actually used for anything, we abuse it for this
* purpose.
*
* Actually, NV05 can optionally check bit 24 too, but we disable this since
* there's no use for it.
*
* For unknown reasons, NV04 implements surf3d binding in hardware as an
* exception. Also for unknown reasons, NV04 doesn't implement the clipping
* methods on the surf3d object, so we have to emulate them too.
*/
static void
nv04_gr_set_ctx1(struct nvkm_device *device, u32 inst, u32 mask, u32 value)
{
int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
u32 tmp;
tmp = nvkm_rd32(device, 0x700000 + inst);
tmp &= ~mask;
tmp |= value;
nvkm_wr32(device, 0x700000 + inst, tmp);
nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp);
nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc << 2), tmp);
}
static void
nv04_gr_set_ctx_val(struct nvkm_device *device, u32 inst, u32 mask, u32 value)
{
int class, op, valid = 1;
u32 tmp, ctx1;
ctx1 = nvkm_rd32(device, 0x700000 + inst);
class = ctx1 & 0xff;
op = (ctx1 >> 15) & 7;
tmp = nvkm_rd32(device, 0x70000c + inst);
tmp &= ~mask;
tmp |= value;
nvkm_wr32(device, 0x70000c + inst, tmp);
/* check for valid surf2d/surf_dst/surf_color */
if (!(tmp & 0x02000000))
valid = 0;
/* check for valid surf_src/surf_zeta */
if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
valid = 0;
switch (op) {
/* SRCCOPY_AND, SRCCOPY: no extra objects required */
case 0:
case 3:
break;
/* ROP_AND: requires pattern and rop */
case 1:
if (!(tmp & 0x18000000))
valid = 0;
break;
/* BLEND_AND: requires beta1 */
case 2:
if (!(tmp & 0x20000000))
valid = 0;
break;
/* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
case 4:
case 5:
if (!(tmp & 0x40000000))
valid = 0;
break;
}
nv04_gr_set_ctx1(device, inst, 0x01000000, valid << 24);
}
static bool
nv04_gr_mthd_set_operation(struct nvkm_device *device, u32 inst, u32 data)
{
u8 class = nvkm_rd32(device, 0x700000) & 0x000000ff;
if (data > 5)
return false;
/* Old versions of the objects only accept first three operations. */
if (data > 2 && class < 0x40)
return false;
nv04_gr_set_ctx1(device, inst, 0x00038000, data << 15);
/* changing operation changes set of objects needed for validation */
nv04_gr_set_ctx_val(device, inst, 0, 0);
return true;
}
static bool
nv04_gr_mthd_surf3d_clip_h(struct nvkm_device *device, u32 inst, u32 data)
{
u32 min = data & 0xffff, max;
u32 w = data >> 16;
if (min & 0x8000)
/* too large */
return false;
if (w & 0x8000)
/* yes, it accepts negative for some reason. */
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nvkm_wr32(device, 0x40053c, min);
nvkm_wr32(device, 0x400544, max);
return true;
}
static bool
nv04_gr_mthd_surf3d_clip_v(struct nvkm_device *device, u32 inst, u32 data)
{
u32 min = data & 0xffff, max;
u32 w = data >> 16;
if (min & 0x8000)
/* too large */
return false;
if (w & 0x8000)
/* yes, it accepts negative for some reason. */
w |= 0xffff0000;
max = min + w;
max &= 0x3ffff;
nvkm_wr32(device, 0x400540, min);
nvkm_wr32(device, 0x400548, max);
return true;
}
static u8
nv04_gr_mthd_bind_class(struct nvkm_device *device, u32 inst)
{
return nvkm_rd32(device, 0x700000 + (inst << 4));
}
static bool
nv04_gr_mthd_bind_surf2d(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
return true;
case 0x42:
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
return true;
case 0x42:
nv04_gr_set_ctx1(device, inst, 0x00004000, 0);
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
return true;
case 0x52:
nv04_gr_set_ctx1(device, inst, 0x00004000, 0x00004000);
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
return true;
}
return false;
}
static bool
nv01_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0);
return true;
case 0x18:
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0);
return true;
case 0x44:
nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_rop(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x10000000, 0);
return true;
case 0x43:
nv04_gr_set_ctx_val(device, inst, 0x10000000, 0x10000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_beta1(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x20000000, 0);
return true;
case 0x12:
nv04_gr_set_ctx_val(device, inst, 0x20000000, 0x20000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_beta4(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x40000000, 0);
return true;
case 0x72:
nv04_gr_set_ctx_val(device, inst, 0x40000000, 0x40000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_surf_dst(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
return true;
case 0x58:
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_surf_src(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0);
return true;
case 0x59:
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_surf_color(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0);
return true;
case 0x5a:
nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000);
return true;
}
return false;
}
static bool
nv04_gr_mthd_bind_surf_zeta(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0);
return true;
case 0x5b:
nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000);
return true;
}
return false;
}
static bool
nv01_gr_mthd_bind_clip(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx1(device, inst, 0x2000, 0);
return true;
case 0x19:
nv04_gr_set_ctx1(device, inst, 0x2000, 0x2000);
return true;
}
return false;
}
static bool
nv01_gr_mthd_bind_chroma(struct nvkm_device *device, u32 inst, u32 data)
{
switch (nv04_gr_mthd_bind_class(device, data)) {
case 0x30:
nv04_gr_set_ctx1(device, inst, 0x1000, 0);
return true;
/* Yes, for some reason even the old versions of objects
* accept 0x57 and not 0x17. Consistency be damned.
*/
case 0x57:
nv04_gr_set_ctx1(device, inst, 0x1000, 0x1000);
return true;
}
return false;
}
static bool
nv03_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_patt; break;
case 0x0188: func = nv04_gr_mthd_bind_rop; break;
case 0x018c: func = nv04_gr_mthd_bind_beta1; break;
case 0x0190: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0188: func = nv04_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_beta4; break;
case 0x0198: func = nv04_gr_mthd_bind_surf2d; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv01_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv01_gr_mthd_bind_clip; break;
case 0x018c: func = nv01_gr_mthd_bind_patt; break;
case 0x0190: func = nv04_gr_mthd_bind_rop; break;
case 0x0194: func = nv04_gr_mthd_bind_beta1; break;
case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x019c: func = nv04_gr_mthd_bind_surf_src; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv01_gr_mthd_bind_clip; break;
case 0x018c: func = nv04_gr_mthd_bind_patt; break;
case 0x0190: func = nv04_gr_mthd_bind_rop; break;
case 0x0194: func = nv04_gr_mthd_bind_beta1; break;
case 0x0198: func = nv04_gr_mthd_bind_beta4; break;
case 0x019c: func = nv04_gr_mthd_bind_surf2d; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_iifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0188: func = nv01_gr_mthd_bind_chroma; break;
case 0x018c: func = nv01_gr_mthd_bind_clip; break;
case 0x0190: func = nv04_gr_mthd_bind_patt; break;
case 0x0194: func = nv04_gr_mthd_bind_rop; break;
case 0x0198: func = nv04_gr_mthd_bind_beta1; break;
case 0x019c: func = nv04_gr_mthd_bind_beta4; break;
case 0x01a0: func = nv04_gr_mthd_bind_surf2d_swzsurf; break;
case 0x03e4: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv01_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv01_gr_mthd_bind_clip; break;
case 0x018c: func = nv01_gr_mthd_bind_patt; break;
case 0x0190: func = nv04_gr_mthd_bind_rop; break;
case 0x0194: func = nv04_gr_mthd_bind_beta1; break;
case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv01_gr_mthd_bind_clip; break;
case 0x018c: func = nv04_gr_mthd_bind_patt; break;
case 0x0190: func = nv04_gr_mthd_bind_rop; break;
case 0x0194: func = nv04_gr_mthd_bind_beta1; break;
case 0x0198: func = nv04_gr_mthd_bind_beta4; break;
case 0x019c: func = nv04_gr_mthd_bind_surf2d; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv03_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv01_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_chroma; break;
case 0x0188: func = nv04_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_beta4; break;
case 0x0198: func = nv04_gr_mthd_bind_surf2d; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv03_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0188: func = nv01_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x0304: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0188: func = nv04_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_beta4; break;
case 0x0198: func = nv04_gr_mthd_bind_surf2d; break;
case 0x0304: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_surf3d(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x02f8: func = nv04_gr_mthd_surf3d_clip_h; break;
case 0x02fc: func = nv04_gr_mthd_surf3d_clip_v; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv03_gr_mthd_ttri(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0188: func = nv01_gr_mthd_bind_clip; break;
case 0x018c: func = nv04_gr_mthd_bind_surf_color; break;
case 0x0190: func = nv04_gr_mthd_bind_surf_zeta; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv01_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_clip; break;
case 0x0188: func = nv01_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32);
switch (mthd) {
case 0x0184: func = nv01_gr_mthd_bind_clip; break;
case 0x0188: func = nv04_gr_mthd_bind_patt; break;
case 0x018c: func = nv04_gr_mthd_bind_rop; break;
case 0x0190: func = nv04_gr_mthd_bind_beta1; break;
case 0x0194: func = nv04_gr_mthd_bind_beta4; break;
case 0x0198: func = nv04_gr_mthd_bind_surf2d; break;
case 0x02fc: func = nv04_gr_mthd_set_operation; break;
default:
return false;
}
return func(device, inst, data);
}
static bool
nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data)
{
bool (*func)(struct nvkm_device *, u32, u32, u32);
switch (nvkm_rd32(device, 0x700000 + inst) & 0x000000ff) {
case 0x1c ... 0x1e:
func = nv01_gr_mthd_prim; break;
case 0x1f: func = nv01_gr_mthd_blit; break;
case 0x21: func = nv01_gr_mthd_ifc; break;
case 0x36: func = nv03_gr_mthd_sifc; break;
case 0x37: func = nv03_gr_mthd_sifm; break;
case 0x48: func = nv03_gr_mthd_ttri; break;
case 0x4a: func = nv04_gr_mthd_gdi; break;
case 0x4b: func = nv03_gr_mthd_gdi; break;
case 0x53: func = nv04_gr_mthd_surf3d; break;
case 0x5c ... 0x5e:
func = nv04_gr_mthd_prim; break;
case 0x5f: func = nv04_gr_mthd_blit; break;
case 0x60: func = nv04_gr_mthd_iifc; break;
case 0x61: func = nv04_gr_mthd_ifc; break;
case 0x76: func = nv04_gr_mthd_sifc; break;
case 0x77: func = nv04_gr_mthd_sifm; break;
default:
return false;
}
return func(device, inst, mthd, data);
}
static int
nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align,
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, object->oclass);
#ifdef __BIG_ENDIAN
nvkm_mo32(*pgpuobj, 0x00, 0x00080000, 0x00080000);
#endif
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm_done(*pgpuobj);
}
return ret;
}
const struct nvkm_object_func
nv04_gr_object = {
.bind = nv04_gr_object_bind,
};
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static struct nv04_gr_chan *
nv04_gr_channel(struct nv04_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv04_gr_chan *chan = NULL;
if (nvkm_rd32(device, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) {
int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24;
if (chid < ARRAY_SIZE(gr->chan))
chan = gr->chan[chid];
}
return chan;
}
static int
nv04_gr_load_context(struct nv04_gr_chan *chan, int chid)
{
struct nvkm_device *device = chan->gr->base.engine.subdev.device;
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
nvkm_wr32(device, nv04_gr_ctx_regs[i], chan->nv04[i]);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
nvkm_mask(device, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000);
return 0;
}
static int
nv04_gr_unload_context(struct nv04_gr_chan *chan)
{
struct nvkm_device *device = chan->gr->base.engine.subdev.device;
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++)
chan->nv04[i] = nvkm_rd32(device, nv04_gr_ctx_regs[i]);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
return 0;
}
static void
nv04_gr_context_switch(struct nv04_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv04_gr_chan *prev = NULL;
struct nv04_gr_chan *next = NULL;
int chid;
nv04_gr_idle(&gr->base);
/* If previous context is valid, we need to save it */
prev = nv04_gr_channel(gr);
if (prev)
nv04_gr_unload_context(prev);
/* load context for next channel */
chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
next = gr->chan[chid];
if (next)
nv04_gr_load_context(next, chid);
}
static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) {
if (nv04_gr_ctx_regs[i] == reg)
return &chan->nv04[i];
}
return NULL;
}
static void *
nv04_gr_chan_dtor(struct nvkm_object *object)
{
struct nv04_gr_chan *chan = nv04_gr_chan(object);
struct nv04_gr *gr = chan->gr;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
gr->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&gr->lock, flags);
return chan;
}
static int
nv04_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_gr_chan *chan = nv04_gr_chan(object);
struct nv04_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (nv04_gr_channel(gr) == chan)
nv04_gr_unload_context(chan);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
static const struct nvkm_object_func
nv04_gr_chan = {
.dtor = nv04_gr_chan_dtor,
.fini = nv04_gr_chan_fini,
};
static int
nv04_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv04_gr *gr = nv04_gr(base);
struct nv04_gr_chan *chan;
unsigned long flags;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv04_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
*ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
spin_lock_irqsave(&gr->lock, flags);
gr->chan[chan->chid] = chan;
spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
bool
nv04_gr_idle(struct nvkm_gr *gr)
{
struct nvkm_subdev *subdev = &gr->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 mask = 0xffffffff;
if (device->card_type == NV_40)
mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask))
break;
) < 0) {
nvkm_error(subdev, "idle timed out with status %08x\n",
nvkm_rd32(device, NV04_PGRAPH_STATUS));
return false;
}
return true;
}
static const struct nvkm_bitfield
nv04_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{}
};
static const struct nvkm_bitfield
nv04_gr_nstatus[] = {
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
{}
};
const struct nvkm_bitfield
nv04_gr_nsource[] = {
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
{ NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
{ NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
{}
};
static void
nv04_gr_intr(struct nvkm_gr *base)
{
struct nv04_gr *gr = nv04_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x0f000000) >> 24;
u32 subc = (addr & 0x0000e000) >> 13;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff;
u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4;
u32 show = stat;
char msg[128], src[128], sta[128];
struct nv04_gr_chan *chan;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
chan = gr->chan[chid];
if (stat & NV_PGRAPH_INTR_NOTIFY) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
if (!nv04_gr_mthd(device, inst, mthd, data))
show &= ~NV_PGRAPH_INTR_NOTIFY;
}
}
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
nv04_gr_context_switch(gr);
}
nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nvkm_snprintbf(msg, sizeof(msg), nv04_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv04_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
chan ? chan->object.client->name : "unknown",
subc, class, mthd, data);
}
spin_unlock_irqrestore(&gr->lock, flags);
}
static int
nv04_gr_init(struct nvkm_gr *base)
{
struct nv04_gr *gr = nv04_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
/* Enable PGRAPH interrupts */
nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_VALID1, 0);
nvkm_wr32(device, NV04_PGRAPH_VALID2, 0);
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000);
/*1231C000 blob, 001 haiku*/
/*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100);
/*0x72111100 blob , 01 haiku*/
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
/*haiku same*/
/*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
/*haiku and blob 10d4*/
nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000);
/* These don't belong here, they're part of a per-channel context */
nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
return 0;
}
static const struct nvkm_gr_func
nv04_gr = {
.init = nv04_gr_init,
.intr = nv04_gr_intr,
.chan_new = nv04_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0017, &nv04_gr_object }, /* chroma */
{ -1, -1, 0x0018, &nv04_gr_object }, /* pattern (nv01) */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x001c, &nv04_gr_object }, /* line */
{ -1, -1, 0x001d, &nv04_gr_object }, /* tri */
{ -1, -1, 0x001e, &nv04_gr_object }, /* rect */
{ -1, -1, 0x001f, &nv04_gr_object },
{ -1, -1, 0x0021, &nv04_gr_object },
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0036, &nv04_gr_object },
{ -1, -1, 0x0037, &nv04_gr_object },
{ -1, -1, 0x0038, &nv04_gr_object }, /* dvd subpicture */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0042, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
{ -1, -1, 0x0048, &nv04_gr_object },
{ -1, -1, 0x004a, &nv04_gr_object },
{ -1, -1, 0x004b, &nv04_gr_object },
{ -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x0053, &nv04_gr_object },
{ -1, -1, 0x0054, &nv04_gr_object }, /* ttri */
{ -1, -1, 0x0055, &nv04_gr_object }, /* mtri */
{ -1, -1, 0x0057, &nv04_gr_object }, /* chroma */
{ -1, -1, 0x0058, &nv04_gr_object }, /* surf_dst */
{ -1, -1, 0x0059, &nv04_gr_object }, /* surf_src */
{ -1, -1, 0x005a, &nv04_gr_object }, /* surf_color */
{ -1, -1, 0x005b, &nv04_gr_object }, /* surf_zeta */
{ -1, -1, 0x005c, &nv04_gr_object }, /* line */
{ -1, -1, 0x005d, &nv04_gr_object }, /* tri */
{ -1, -1, 0x005e, &nv04_gr_object }, /* rect */
{ -1, -1, 0x005f, &nv04_gr_object },
{ -1, -1, 0x0060, &nv04_gr_object },
{ -1, -1, 0x0061, &nv04_gr_object },
{ -1, -1, 0x0064, &nv04_gr_object }, /* iifc (nv05) */
{ -1, -1, 0x0065, &nv04_gr_object }, /* ifc (nv05) */
{ -1, -1, 0x0066, &nv04_gr_object }, /* sifc (nv05) */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0076, &nv04_gr_object },
{ -1, -1, 0x0077, &nv04_gr_object },
{}
}
};
int
nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv04_gr *gr;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(&nv04_gr, device, type, inst, true, &gr->base);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/init.h>
#include <subdev/bios/P0260.h>
#include <subdev/fb.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gm107_gr_init_main_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408910, 1, 0x04, 0x00000000 },
{ 0x408984, 1, 0x04, 0x00000000 },
{ 0x41a8a0, 1, 0x04, 0x00000000 },
{ 0x400080, 1, 0x04, 0x003003c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00060000 },
{ 0x400090, 1, 0x04, 0x00000030 },
{ 0x40013c, 1, 0x04, 0x003901f3 },
{ 0x400140, 1, 0x04, 0x00000100 },
{ 0x400144, 1, 0x04, 0x00000000 },
{ 0x400148, 1, 0x04, 0x00000110 },
{ 0x400138, 1, 0x04, 0x00000000 },
{ 0x400130, 2, 0x04, 0x00000000 },
{ 0x400124, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gm107_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000010 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x40440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
const struct gf100_gr_init
gm107_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gm107_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00010201 },
{}
};
const struct gf100_gr_init
gm107_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
{ 0x418930, 2, 0x04, 0x00000000 },
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{}
};
const struct gf100_gr_init
gm107_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_tpccs_0[] = {
{ 0x419dc4, 1, 0x04, 0x00000000 },
{ 0x419dc8, 1, 0x04, 0x00000501 },
{ 0x419dd0, 1, 0x04, 0x00000000 },
{ 0x419dd4, 1, 0x04, 0x00000100 },
{ 0x419dd8, 1, 0x04, 0x00000001 },
{ 0x419ddc, 1, 0x04, 0x00000002 },
{ 0x419de0, 1, 0x04, 0x00000001 },
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
const struct gf100_gr_init
gm107_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 1, 0x04, 0x00000000 },
{ 0x419acc, 1, 0x04, 0x000000ff },
{ 0x419ac0, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{ 0x419ad0, 2, 0x04, 0x00000000 },
{ 0x419ae0, 2, 0x04, 0x00000000 },
{ 0x419af0, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_pe_0[] = {
{ 0x419900, 1, 0x04, 0x000000ff },
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419838, 1, 0x04, 0x000000ff },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{ 0x419894, 3, 0x04, 0x00100401 },
{}
};
const struct gf100_gr_init
gm107_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_sm_0[] = {
{ 0x419e30, 1, 0x04, 0x000000ff },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x01000000 },
{ 0x419ee8, 1, 0x04, 0x00000091 },
{ 0x419eb4, 1, 0x04, 0x00000000 },
{ 0x419ebc, 2, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x000c1810 },
{ 0x419ed8, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00000000 },
{ 0x419f74, 1, 0x04, 0x00005155 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_l1c_1[] = {
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x3f006022 },
{ 0x419c88, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_pes_0[] = {
{ 0x41be50, 1, 0x04, 0x000000ff },
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
{ 0x41be0c, 1, 0x04, 0x00000008 },
{ 0x41be10, 1, 0x04, 0x0e3b8bc7 },
{ 0x41be14, 2, 0x04, 0x00000000 },
{ 0x41be3c, 5, 0x04, 0x00100401 },
{}
};
const struct gf100_gr_init
gm107_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gm107_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_be_0[] = {
{ 0x408890, 1, 0x04, 0x000000ff },
{ 0x408850, 1, 0x04, 0x00000004 },
{ 0x408878, 1, 0x04, 0x00c81603 },
{ 0x40887c, 1, 0x04, 0x80543432 },
{ 0x408880, 1, 0x04, 0x0010581e },
{ 0x408884, 1, 0x04, 0x00001205 },
{ 0x408974, 1, 0x04, 0x000000ff },
{ 0x408914, 8, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
{ 0x408954, 1, 0x04, 0x0000ffff },
{ 0x408958, 1, 0x04, 0x00000034 },
{ 0x40895c, 1, 0x04, 0x8531a003 },
{ 0x408960, 1, 0x04, 0x0561985a },
{ 0x408964, 1, 0x04, 0x04e15c4f },
{ 0x408968, 1, 0x04, 0x02808833 },
{ 0x40896c, 1, 0x04, 0x01f02438 },
{ 0x408970, 1, 0x04, 0x00012c00 },
{ 0x408988, 1, 0x04, 0x08040201 },
{ 0x40898c, 1, 0x04, 0x80402010 },
{}
};
static const struct gf100_gr_init
gm107_gr_init_sm_1[] = {
{ 0x419e5c, 1, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gm107_gr_pack_mmio[] = {
{ gm107_gr_init_main_0 },
{ gk110_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gm107_gr_init_ds_0 },
{ gm107_gr_init_scc_0 },
{ gm107_gr_init_sked_0 },
{ gk110_gr_init_cwd_0 },
{ gm107_gr_init_prop_0 },
{ gk208_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gm107_gr_init_setup_1 },
{ gm107_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gm107_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gk104_gr_init_gpc_unk_2 },
{ gm107_gr_init_tpccs_0 },
{ gm107_gr_init_tex_0 },
{ gm107_gr_init_pe_0 },
{ gm107_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gm107_gr_init_sm_0 },
{ gm107_gr_init_l1c_1 },
{ gm107_gr_init_pes_0 },
{ gm107_gr_init_wwdx_0 },
{ gm107_gr_init_cbm_0 },
{ gm107_gr_init_be_0 },
{ gm107_gr_init_sm_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
void
gm107_gr_init_400054(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63);
}
void
gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
}
void
gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
}
static void
gm107_gr_init_bios_2(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct bit_entry bit_P;
if (!bit_entry(bios, 'P', &bit_P) &&
bit_P.version == 2 && bit_P.length >= 0x2c) {
u32 data = nvbios_rd32(bios, bit_P.offset + 0x28);
if (data) {
u8 ver = nvbios_rd08(bios, data + 0x00);
u8 hdr = nvbios_rd08(bios, data + 0x01);
if (ver == 0x20 && hdr >= 8) {
data = nvbios_rd32(bios, data + 0x04);
if (data) {
u32 save = nvkm_rd32(device, 0x619444);
nvbios_init(subdev, data);
nvkm_wr32(device, 0x619444, save);
}
}
}
}
}
void
gm107_gr_init_bios(struct gf100_gr *gr)
{
static const struct {
u32 ctrl;
u32 data;
} regs[] = {
{ 0x419ed8, 0x419ee0 },
{ 0x419ad0, 0x419ad4 },
{ 0x419ae0, 0x419ae4 },
{ 0x419af0, 0x419af4 },
{ 0x419af8, 0x419afc },
};
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_bios *bios = device->bios;
struct nvbios_P0260E infoE;
struct nvbios_P0260X infoX;
int E = -1, X;
u8 ver, hdr;
while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) {
if (X = -1, E < ARRAY_SIZE(regs)) {
nvkm_wr32(device, regs[E].ctrl, infoE.data);
while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX))
nvkm_wr32(device, regs[E].data, infoX.data);
}
}
}
static void
gm107_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000);
nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8);
}
#include "fuc/hubgm107.fuc5.h"
static struct gf100_gr_ucode
gm107_gr_fecs_ucode = {
.code.data = gm107_grhub_code,
.code.size = sizeof(gm107_grhub_code),
.data.data = gm107_grhub_data,
.data.size = sizeof(gm107_grhub_data),
};
#include "fuc/gpcgm107.fuc5.h"
static struct gf100_gr_ucode
gm107_gr_gpccs_ucode = {
.code.data = gm107_grgpc_code,
.code.size = sizeof(gm107_grgpc_code),
.data.data = gm107_grgpc_data,
.data.size = sizeof(gm107_grgpc_data),
};
static const struct gf100_gr_func
gm107_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm107_gr_init_gpc_mmu,
.init_bios = gm107_gr_init_bios,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_bios_2 = gm107_gr_init_bios_2,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gm107_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gm107_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gm107_gr_pack_mmio,
.fecs.ucode = &gm107_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gm107_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 2,
.grctx = &gm107_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, MAXWELL_A, &gf100_fermi },
{ -1, -1, MAXWELL_COMPUTE_A },
{}
}
};
static const struct gf100_gr_fwif
gm107_gr_fwif[] = {
{ -1, gf100_gr_load, &gm107_gr },
{ -1, gf100_gr_nofw, &gm107_gr },
{}
};
int
gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c |
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
static const struct gf100_gr_init
gv100_grctx_init_sw_veid_bundle_init_0[] = {
{ 0x00001000, 64, 0x00100000, 0x00000008 },
{ 0x00000941, 64, 0x00100000, 0x00000000 },
{ 0x0000097e, 64, 0x00100000, 0x00000000 },
{ 0x0000097f, 64, 0x00100000, 0x00000100 },
{ 0x0000035c, 64, 0x00100000, 0x00000000 },
{ 0x0000035d, 64, 0x00100000, 0x00000000 },
{ 0x00000a08, 64, 0x00100000, 0x00000000 },
{ 0x00000a09, 64, 0x00100000, 0x00000000 },
{ 0x00000a0a, 64, 0x00100000, 0x00000000 },
{ 0x00000352, 64, 0x00100000, 0x00000000 },
{ 0x00000353, 64, 0x00100000, 0x00000000 },
{ 0x00000358, 64, 0x00100000, 0x00000000 },
{ 0x00000359, 64, 0x00100000, 0x00000000 },
{ 0x00000370, 64, 0x00100000, 0x00000000 },
{ 0x00000371, 64, 0x00100000, 0x00000000 },
{ 0x00000372, 64, 0x00100000, 0x000fffff },
{ 0x00000366, 64, 0x00100000, 0x00000000 },
{ 0x00000367, 64, 0x00100000, 0x00000000 },
{ 0x00000368, 64, 0x00100000, 0x00000fff },
{ 0x00000623, 64, 0x00100000, 0x00000000 },
{ 0x00000624, 64, 0x00100000, 0x00000000 },
{ 0x0001e100, 1, 0x00000001, 0x02000001 },
{}
};
static const struct gf100_gr_pack
gv100_grctx_pack_sw_veid_bundle_init[] = {
{ gv100_grctx_init_sw_veid_bundle_init_0 },
{}
};
void
gv100_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr;
const u32 gfxp = grctx->gfxp_nr;
const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0;
u32 bo = ao + size;
int gpc, ppc, n = 0;
gf100_grctx_patch_wr32(chan, 0x405830, attrib);
gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_max;
const u32 gs = gfxp * gr->ppc_tpc_max;
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
gf100_grctx_patch_wr32(chan, o + 0xc0, gs);
gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
bo += gs;
gf100_grctx_patch_wr32(chan, o + 0xe4, as);
gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, u, bs);
}
}
gf100_grctx_patch_wr32(chan, 0x4181e4, 0x00000100);
gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000100);
}
void
gv100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gm107_grctx_generate_attrib_cb(chan, addr, size);
gf100_grctx_patch_wr32(chan, 0x419e00, 0x00000000 | addr >> 12);
gf100_grctx_patch_wr32(chan, 0x419e04, 0x80000000 | size >> 7);
}
void
gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 mapregs = DIV_ROUND_UP(gr->func->gpc_nr * gr->func->tpc_nr, 6);
u32 data;
int i, j;
/* Pack tile map into register format. */
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < mapregs; i++) {
for (data = 0, j = 0; j < 6; j++)
data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
nvkm_wr32(device, 0x418b08 + (i * 4), data);
nvkm_wr32(device, 0x41bf00 + (i * 4), data);
nvkm_wr32(device, 0x40780c + (i * 4), data);
}
/* GPC_BROADCAST.TP_BROADCAST */
nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0, j = 1; i < 5; i++, j += 4) {
u8 v19 = (1 << (j + 0)) % gr->tpc_total;
u8 v20 = (1 << (j + 1)) % gr->tpc_total;
u8 v21 = (1 << (j + 2)) % gr->tpc_total;
u8 v22 = (1 << (j + 3)) % gr->tpc_total;
nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
(v21 << 16) |
(v20 << 8) |
v19);
}
/* UNK78xx */
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
}
void
gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
}
static void
gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}
void
gv100_grctx_generate_unkn(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
void
gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
nvkm_mask(device, 0x40988c, mask, data);
nvkm_rd32(device, 0x40988c);
nvkm_mask(device, 0x41a88c, mask, data);
nvkm_rd32(device, 0x41a88c);
nvkm_mask(device, 0x408a14, mask, data);
nvkm_rd32(device, 0x408a14);
}
const struct gf100_grctx_func
gv100_grctx = {
.unkn88c = gv100_grctx_unkn88c,
.main = gf100_grctx_generate_main,
.unkn = gv100_grctx_generate_unkn,
.sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x1680,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gv100_grctx_generate_attrib_cb,
.attrib = gv100_grctx_generate_attrib,
.attrib_nr_max = 0x6c0,
.attrib_nr = 0x480,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xd10,
.sm_id = gv100_grctx_generate_sm_id,
.rop_mapping = gv100_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.smid_config = gp100_grctx_generate_smid_config,
.r400088 = gv100_grctx_generate_r400088,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "gk104.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gk104_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001ffe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
{ 0x400090, 1, 0x04, 0x00000030 },
{ 0x40013c, 1, 0x04, 0x003901f7 },
{ 0x400140, 1, 0x04, 0x00000100 },
{ 0x400144, 1, 0x04, 0x00000000 },
{ 0x400148, 1, 0x04, 0x00000110 },
{ 0x400138, 1, 0x04, 0x00000000 },
{ 0x400130, 2, 0x04, 0x00000000 },
{ 0x400124, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff34 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_cwd_0[] = {
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000060 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk104_gr_init_gpc_unk_2[] = {
{ 0x418884, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk104_gr_init_tpccs_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
const struct gf100_gr_init
gk104_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
{ 0x419854, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00b08bea },
{ 0x419c84, 1, 0x04, 0x00010384 },
{ 0x419cbc, 1, 0x04, 0x28137646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00020232 },
{}
};
static const struct gf100_gr_init
gk104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00000000 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f74, 1, 0x04, 0x00000555 },
{}
};
const struct gf100_gr_init
gk104_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
{ 0x408910, 9, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
{ 0x408954, 1, 0x04, 0x0000ffff },
{ 0x408958, 1, 0x04, 0x00000034 },
{ 0x408984, 1, 0x04, 0x00000000 },
{ 0x408988, 1, 0x04, 0x08040201 },
{ 0x40898c, 1, 0x04, 0x80402010 },
{}
};
const struct gf100_gr_pack
gk104_gr_pack_mmio[] = {
{ gk104_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gk104_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gk104_gr_init_sked_0 },
{ gk104_gr_init_cwd_0 },
{ gf119_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gk104_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gk104_gr_init_gpc_unk_2 },
{ gk104_gr_init_tpccs_0 },
{ gf119_gr_init_tex_0 },
{ gk104_gr_init_pe_0 },
{ gk104_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gk104_gr_init_sm_0 },
{ gf117_gr_init_pes_0 },
{ gf117_gr_init_wwdx_0 },
{ gf117_gr_init_cbm_0 },
{ gk104_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_main_0[] = {
{ 0x4041f0, 1, 0x00004046 },
{ 0x409890, 1, 0x00000045 },
{ 0x4098b0, 1, 0x0000007f },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_rstr2d_0[] = {
{ 0x4078c0, 1, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_unk_0[] = {
{ 0x406000, 1, 0x00004044 },
{ 0x405860, 1, 0x00004042 },
{ 0x40590c, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gcc_0[] = {
{ 0x408040, 1, 0x00004044 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_sked_0[] = {
{ 0x407000, 1, 0x00004044 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_unk_1[] = {
{ 0x405bf0, 1, 0x00004044 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_ctxctl_0[] = {
{ 0x41a890, 1, 0x00000042 },
{ 0x41a8b0, 1, 0x0000007f },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_unk_0[] = {
{ 0x418500, 1, 0x00004042 },
{ 0x418608, 1, 0x00004042 },
{ 0x418688, 1, 0x00004042 },
{ 0x418718, 1, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_esetup_0[] = {
{ 0x418828, 1, 0x00000044 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_tpbus_0[] = {
{ 0x418bbc, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_zcull_0[] = {
{ 0x418970, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_tpconf_0[] = {
{ 0x418c70, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_unk_1[] = {
{ 0x418cf0, 1, 0x00004042 },
{ 0x418d70, 1, 0x00004042 },
{ 0x418f0c, 1, 0x00004042 },
{ 0x418e0c, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_gcc_0[] = {
{ 0x419020, 1, 0x00004042 },
{ 0x419038, 1, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_ffb_0[] = {
{ 0x418898, 1, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_tex_0[] = {
{ 0x419a40, 9, 0x00004042 },
{ 0x419acc, 1, 0x00004047 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_poly_0[] = {
{ 0x419868, 1, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_l1c_0[] = {
{ 0x419ccc, 3, 0x00000042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_unk_2[] = {
{ 0x419c70, 1, 0x00004045 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_mp_0[] = {
{ 0x419fd0, 1, 0x00004043 },
{ 0x419fd8, 1, 0x00004049 },
{ 0x419fe0, 2, 0x00004042 },
{ 0x419ff0, 1, 0x00004046 },
{ 0x419ff8, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_gpc_ppc_0[] = {
{ 0x41be28, 1, 0x00000042 },
{ 0x41bfe8, 1, 0x00004042 },
{ 0x41bed0, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_rop_zrop_0[] = {
{ 0x408810, 2, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_rop_0[] = {
{ 0x408a80, 6, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_rop_crop_0[] = {
{ 0x4089a8, 1, 0x00004042 },
{ 0x4089b0, 1, 0x00000042 },
{ 0x4089b8, 1, 0x00004042 },
{}
};
const struct nvkm_therm_clkgate_init
gk104_clkgate_blcg_init_pxbar_0[] = {
{ 0x13c820, 1, 0x0001007f },
{ 0x13cbe0, 1, 0x00000042 },
{}
};
static const struct nvkm_therm_clkgate_pack
gk104_clkgate_pack[] = {
{ gk104_clkgate_blcg_init_main_0 },
{ gk104_clkgate_blcg_init_rstr2d_0 },
{ gk104_clkgate_blcg_init_unk_0 },
{ gk104_clkgate_blcg_init_gcc_0 },
{ gk104_clkgate_blcg_init_sked_0 },
{ gk104_clkgate_blcg_init_unk_1 },
{ gk104_clkgate_blcg_init_gpc_ctxctl_0 },
{ gk104_clkgate_blcg_init_gpc_unk_0 },
{ gk104_clkgate_blcg_init_gpc_esetup_0 },
{ gk104_clkgate_blcg_init_gpc_tpbus_0 },
{ gk104_clkgate_blcg_init_gpc_zcull_0 },
{ gk104_clkgate_blcg_init_gpc_tpconf_0 },
{ gk104_clkgate_blcg_init_gpc_unk_1 },
{ gk104_clkgate_blcg_init_gpc_gcc_0 },
{ gk104_clkgate_blcg_init_gpc_ffb_0 },
{ gk104_clkgate_blcg_init_gpc_tex_0 },
{ gk104_clkgate_blcg_init_gpc_poly_0 },
{ gk104_clkgate_blcg_init_gpc_l1c_0 },
{ gk104_clkgate_blcg_init_gpc_unk_2 },
{ gk104_clkgate_blcg_init_gpc_mp_0 },
{ gk104_clkgate_blcg_init_gpc_ppc_0 },
{ gk104_clkgate_blcg_init_rop_zrop_0 },
{ gk104_clkgate_blcg_init_rop_0 },
{ gk104_clkgate_blcg_init_rop_crop_0 },
{ gk104_clkgate_blcg_init_pxbar_0 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
void
gk104_gr_init_sked_hww_esr(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000);
}
static void
gk104_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409ffc, 0x00000000);
nvkm_wr32(device, 0x409c14, 0x00003e3e);
nvkm_wr32(device, 0x409c24, 0x000f0001);
}
void
gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x120074);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void
gk104_gr_init_ppc_exceptions(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, ppc;
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
}
}
}
void
gk104_gr_init_vsc_stream_master(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001);
}
#include "fuc/hubgk104.fuc3.h"
static struct gf100_gr_ucode
gk104_gr_fecs_ucode = {
.code.data = gk104_grhub_code,
.code.size = sizeof(gk104_grhub_code),
.data.data = gk104_grhub_data,
.data.size = sizeof(gk104_grhub_data),
};
#include "fuc/gpcgk104.fuc3.h"
static struct gf100_gr_ucode
gk104_gr_gpccs_ucode = {
.code.data = gk104_grgpc_code,
.code.size = sizeof(gk104_grgpc_code),
.data.data = gk104_grgpc_data,
.data.size = sizeof(gk104_grgpc_data),
};
static const struct gf100_gr_func
gk104_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gk104_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gk104_gr_pack_mmio,
.fecs.ucode = &gk104_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gk104_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 1,
.grctx = &gk104_grctx,
.clkgate_pack = gk104_clkgate_pack,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },
{ -1, -1, KEPLER_A, &gf100_fermi },
{ -1, -1, KEPLER_COMPUTE_A },
{}
}
};
static const struct gf100_gr_fwif
gk104_gr_fwif[] = {
{ -1, gf100_gr_load, &gk104_gr },
{ -1, gf100_gr_nofw, &gk104_gr },
{}
};
int
gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gf110_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00001100 },
{ 0x419eac, 1, 0x04, 0x11100f02 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x06060618 },
{ 0x419ed0, 1, 0x04, 0x0eff0e38 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf110_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gf100_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf100_gr_init_prop_0 },
{ gf100_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gf100_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf100_gr_init_tex_0 },
{ gf100_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_wwdx_0 },
{ gf100_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf110_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{ gf100_gr_init_pe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct gf100_gr_func
gf110_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf110_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf100_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.grctx = &gf110_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_B, &gf100_fermi },
{ -1, -1, FERMI_C, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{ -1, -1, FERMI_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gf110_gr_fwif[] = {
{ -1, gf100_gr_load, &gf110_gr },
{ -1, gf100_gr_nofw, &gf110_gr },
{}
};
int
gf110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf110_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk208_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x0002f2, 2, 0x01, 0x00000001 },
{ 0x0002f5, 1, 0x01, 0x00000001 },
{ 0x0002f7, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000383, 1, 0x01, 0x00000011 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000662, 1, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x00080b, 1, 0x01, 0x00000002 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x000a0d, 1, 0x01, 0x00000006 },
{ 0x00097d, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x003fffff },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00400008 },
{ 0x000841, 1, 0x01, 0x08000080 },
{ 0x000842, 1, 0x01, 0x00400008 },
{ 0x000843, 1, 0x01, 0x08000080 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000008 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_icmd[] = {
{ gk208_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
{ 0x4040a8, 8, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf800008f },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404100, 10, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x40417c, 2, 0x04, 0x00000000 },
{ 0x404194, 1, 0x04, 0x01000700 },
{ 0x4041a0, 4, 0x04, 0x00000000 },
{ 0x404200, 1, 0x04, 0x0000a197 },
{ 0x404204, 1, 0x04, 0x0000a1c0 },
{ 0x404208, 1, 0x04, 0x0000a140 },
{ 0x40420c, 1, 0x04, 0x0000902d },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{ 0x405a1c, 1, 0x04, 0x000000ff },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b0, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x802000f0 },
{ 0x4064c4, 1, 0x04, 0x0192ffff },
{ 0x4064c8, 1, 0x04, 0x00c20200 },
{ 0x4064cc, 9, 0x04, 0x00000000 },
{ 0x4064fc, 1, 0x04, 0x0000022a },
{}
};
const struct gf100_gr_init
gk208_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000063 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
{ 0x407814, 1, 0x04, 0x020398a4 },
{ 0x407818, 1, 0x04, 0x0e629062 },
{ 0x40781c, 1, 0x04, 0x0a418820 },
{ 0x407820, 1, 0x04, 0x000000e6 },
{ 0x4078bc, 1, 0x04, 0x00000103 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
{ 0x408840, 1, 0x04, 0x0000000b },
{ 0x408900, 1, 0x04, 0xb080b801 },
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x02c8102f },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gk208_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gk208_grctx_init_ds_0 },
{ gk110_grctx_init_cwd_0 },
{ gk208_grctx_init_pd_0 },
{ gk208_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gk208_grctx_init_be_0 },
{}
};
const struct gf100_gr_init
gk208_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38005e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
{ 0x418410, 1, 0x04, 0x0fff0fff },
{ 0x418414, 1, 0x04, 0x02200fff },
{ 0x418450, 6, 0x04, 0x00000000 },
{ 0x418468, 1, 0x04, 0x00000001 },
{ 0x41846c, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 2, 0x04, 0x00000080 },
{ 0x41870c, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
{ 0x418810, 1, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100058 },
{}
};
const struct gf100_gr_init
gk208_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x0000001e },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
{ 0x418b10, 1, 0x04, 0x020398a4 },
{ 0x418b14, 1, 0x04, 0x0e629062 },
{ 0x418b18, 1, 0x04, 0x0a418820 },
{ 0x418b1c, 1, 0x04, 0x000000e6 },
{ 0x418bb8, 1, 0x04, 0x00000103 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
{ 0x418c6c, 1, 0x04, 0x00000001 },
{ 0x418c80, 1, 0x04, 0x2020000c },
{ 0x418c8c, 1, 0x04, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gk208_grctx_init_prop_0 },
{ gk208_grctx_init_gpc_unk_1 },
{ gk208_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_gpc_1[] = {
{ gk208_grctx_init_crstr_0 },
{ gk208_grctx_init_gpm_0 },
{ gk110_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000421 },
{ 0x419a0c, 1, 0x04, 0x00120000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x0000c000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000007f },
{ 0x419e50, 2, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000001 },
{ 0x419e5c, 3, 0x04, 0x00000000 },
{ 0x419e68, 1, 0x04, 0x00000002 },
{ 0x419e6c, 12, 0x04, 0x00000000 },
{ 0x419eac, 1, 0x04, 0x00001f8f },
{ 0x419eb0, 1, 0x04, 0x0db00d2f },
{ 0x419eb8, 1, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0001304f },
{ 0x419f30, 4, 0x04, 0x00000000 },
{ 0x419f40, 1, 0x04, 0x00000018 },
{ 0x419f44, 3, 0x04, 0x00000000 },
{ 0x419f58, 1, 0x04, 0x00000020 },
{ 0x419f70, 1, 0x04, 0x00000000 },
{ 0x419f78, 1, 0x04, 0x000001eb },
{ 0x419f7c, 1, 0x04, 0x00000404 },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk208_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk208_grctx_init_sm_0 },
{}
};
static const struct gf100_gr_init
gk208_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{ 0x41bef0, 1, 0x04, 0x000003ff },
{}
};
static const struct gf100_gr_pack
gk208_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gk208_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gk208_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk208_grctx_pack_hub,
.gpc_0 = gk208_grctx_pack_gpc_0,
.gpc_1 = gk208_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk208_grctx_pack_tpc,
.ppc = gk208_grctx_pack_ppc,
.icmd = gk208_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
.alpha_nr = 0x648,
.patch_ltc = gk104_grctx_generate_patch_ltc,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.r418800 = gk104_grctx_generate_r418800,
.r419f78 = gk110_grctx_generate_r419f78,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
#include "regs.h"
#include <subdev/fb.h>
#include <engine/fifo.h>
static void
nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
struct nv40_gr *gr = nv40_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fifo *fifo = device->fifo;
unsigned long flags;
nvkm_fifo_pause(fifo, &flags);
nv04_gr_idle(&gr->base);
switch (device->chipset) {
case 0x44:
case 0x4a:
nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
break;
case 0x46:
case 0x4c:
case 0x63:
case 0x67:
case 0x68:
nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
break;
case 0x4e:
nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
break;
default:
WARN_ON(1);
break;
}
nvkm_fifo_start(fifo, &flags);
}
static const struct nvkm_gr_func
nv44_gr = {
.init = nv40_gr_init,
.intr = nv40_gr_intr,
.tile = nv44_gr_tile,
.units = nv40_gr_units,
.chan_new = nv40_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv40_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv40_gr_object }, /* null */
{ -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv40_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv40_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
{ -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
{ -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
{ -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
{ -1, -1, 0x4497, &nv40_gr_object }, /* curie */
{}
}
};
int
nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv40_gr_new_(&nv44_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct nvkm_object_func
nv25_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x3724, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x035c, 0xffff0000);
nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000);
nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000);
nvkm_wo32(chan->inst, 0x049c, 0x00000101);
nvkm_wo32(chan->inst, 0x04b0, 0x00000111);
nvkm_wo32(chan->inst, 0x04c8, 0x00000080);
nvkm_wo32(chan->inst, 0x04cc, 0xffff0000);
nvkm_wo32(chan->inst, 0x04d0, 0x00000001);
nvkm_wo32(chan->inst, 0x04e4, 0x44400000);
nvkm_wo32(chan->inst, 0x04fc, 0x4b800000);
for (i = 0x0510; i <= 0x051c; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x0530; i <= 0x053c; i += 4)
nvkm_wo32(chan->inst, i, 0x00080000);
for (i = 0x0548; i <= 0x0554; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x0558; i <= 0x0564; i += 4)
nvkm_wo32(chan->inst, i, 0x000105b8);
for (i = 0x0568; i <= 0x0574; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
for (i = 0x0598; i <= 0x05d4; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x05e0, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x0620, 0x00000080);
nvkm_wo32(chan->inst, 0x0624, 0x30201000);
nvkm_wo32(chan->inst, 0x0628, 0x70605040);
nvkm_wo32(chan->inst, 0x062c, 0xb0a09080);
nvkm_wo32(chan->inst, 0x0630, 0xf0e0d0c0);
nvkm_wo32(chan->inst, 0x0664, 0x00000001);
nvkm_wo32(chan->inst, 0x066c, 0x00004000);
nvkm_wo32(chan->inst, 0x0678, 0x00000001);
nvkm_wo32(chan->inst, 0x0680, 0x00040000);
nvkm_wo32(chan->inst, 0x0684, 0x00010000);
for (i = 0x1b04; i <= 0x2374; i += 16) {
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
}
nvkm_wo32(chan->inst, 0x2704, 0x3f800000);
nvkm_wo32(chan->inst, 0x2718, 0x3f800000);
nvkm_wo32(chan->inst, 0x2744, 0x40000000);
nvkm_wo32(chan->inst, 0x2748, 0x3f800000);
nvkm_wo32(chan->inst, 0x274c, 0x3f000000);
nvkm_wo32(chan->inst, 0x2754, 0x40000000);
nvkm_wo32(chan->inst, 0x2758, 0x3f800000);
nvkm_wo32(chan->inst, 0x2760, 0xbf800000);
nvkm_wo32(chan->inst, 0x2768, 0xbf800000);
nvkm_wo32(chan->inst, 0x308c, 0x000fe000);
nvkm_wo32(chan->inst, 0x3108, 0x000003f8);
nvkm_wo32(chan->inst, 0x3468, 0x002fe000);
for (i = 0x3484; i <= 0x34a0; i += 4)
nvkm_wo32(chan->inst, i, 0x001c527c);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct nvkm_gr_func
nv25_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv20_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv25_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
{}
}
};
int
nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv25_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "gf100.h"
#include "ctxgf100.h"
#include "fuc/os.h"
#include <core/client.h>
#include <core/firmware.h>
#include <core/option.h>
#include <subdev/acr.h>
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/pmu.h>
#include <subdev/therm.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
#include <nvif/class.h>
#include <nvif/cl9097.h>
#include <nvif/if900d.h>
#include <nvif/unpack.h>
/*******************************************************************************
* Zero Bandwidth Clear
******************************************************************************/
static void
gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
if (gr->zbc_color[zbc].format) {
nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
}
nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
nvkm_wr32(device, 0x405820, zbc);
nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
}
static int
gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
const u32 ds[4], const u32 l2[4])
{
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_color_min; i <= ltc->zbc_color_max; i++) {
if (gr->zbc_color[i].format) {
if (gr->zbc_color[i].format != format)
continue;
if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
gr->zbc_color[i].ds)))
continue;
if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
gr->zbc_color[i].l2))) {
WARN_ON(1);
return -EINVAL;
}
return i;
} else {
zbc = (zbc < 0) ? i : zbc;
}
}
if (zbc < 0)
return zbc;
memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
gr->zbc_color[zbc].format = format;
nvkm_ltc_zbc_color_get(ltc, zbc, l2);
gr->func->zbc->clear_color(gr, zbc);
return zbc;
}
static void
gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
if (gr->zbc_depth[zbc].format)
nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
nvkm_wr32(device, 0x405820, zbc);
nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
}
static int
gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
if (gr->zbc_depth[i].format) {
if (gr->zbc_depth[i].format != format)
continue;
if (gr->zbc_depth[i].ds != ds)
continue;
if (gr->zbc_depth[i].l2 != l2) {
WARN_ON(1);
return -EINVAL;
}
return i;
} else {
zbc = (zbc < 0) ? i : zbc;
}
}
if (zbc < 0)
return zbc;
gr->zbc_depth[zbc].format = format;
gr->zbc_depth[zbc].ds = ds;
gr->zbc_depth[zbc].l2 = l2;
nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
gr->func->zbc->clear_depth(gr, zbc);
return zbc;
}
const struct gf100_gr_func_zbc
gf100_gr_zbc = {
.clear_color = gf100_gr_zbc_clear_color,
.clear_depth = gf100_gr_zbc_clear_depth,
};
/*******************************************************************************
* Graphics object classes
******************************************************************************/
#define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
struct gf100_gr_object {
struct nvkm_object object;
struct gf100_gr_chan *chan;
};
static int
gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{
struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
int ret = -ENOSYS;
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
switch (args->v0.format) {
case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
ret = gf100_gr_zbc_color_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
if (ret >= 0) {
args->v0.index = ret;
return 0;
}
break;
default:
return -EINVAL;
}
}
return ret;
}
static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{
struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
int ret = -ENOSYS;
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
args->v0.ds,
args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
default:
return -EINVAL;
}
}
return ret;
}
static int
gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
nvif_ioctl(object, "fermi mthd %08x\n", mthd);
switch (mthd) {
case FERMI_A_ZBC_COLOR:
return gf100_fermi_mthd_zbc_color(object, data, size);
case FERMI_A_ZBC_DEPTH:
return gf100_fermi_mthd_zbc_depth(object, data, size);
default:
break;
}
return -EINVAL;
}
const struct nvkm_object_func
gf100_fermi = {
.mthd = gf100_fermi_mthd,
};
static void
gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
{
nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
}
static bool
gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
{
switch (class & 0x00ff) {
case 0x97:
case 0xc0:
switch (mthd) {
case 0x1528:
gf100_gr_mthd_set_shader_exceptions(device, data);
return true;
default:
break;
}
break;
default:
break;
}
return false;
}
static const struct nvkm_object_func
gf100_gr_object_func = {
};
static int
gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
struct gf100_gr_object *object;
if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
return -ENOMEM;
*pobject = &object->object;
nvkm_object_ctor(oclass->base.func ? oclass->base.func :
&gf100_gr_object_func, oclass, &object->object);
object->chan = chan;
return 0;
}
static int
gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
{
struct gf100_gr *gr = gf100_gr(base);
int c = 0;
while (gr->func->sclass[c].oclass) {
if (c++ == index) {
*sclass = gr->func->sclass[index];
sclass->ctor = gf100_gr_object_new;
return index;
}
}
return c;
}
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static int
gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
struct gf100_gr_chan *chan = gf100_gr_chan(object);
struct gf100_gr *gr = chan->gr;
int ret, i;
ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
align, false, parent, pgpuobj);
if (ret)
return ret;
nvkm_kmap(*pgpuobj);
for (i = 0; i < gr->size; i += 4)
nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
if (!gr->firmware) {
nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
} else {
nvkm_wo32(*pgpuobj, 0xf4, 0);
nvkm_wo32(*pgpuobj, 0xf8, 0);
nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
nvkm_wo32(*pgpuobj, 0x1c, 1);
nvkm_wo32(*pgpuobj, 0x20, 0);
nvkm_wo32(*pgpuobj, 0x28, 0);
nvkm_wo32(*pgpuobj, 0x2c, 0);
}
nvkm_done(*pgpuobj);
return 0;
}
static void *
gf100_gr_chan_dtor(struct nvkm_object *object)
{
struct gf100_gr_chan *chan = gf100_gr_chan(object);
nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
nvkm_memory_unref(&chan->mmio);
nvkm_vmm_put(chan->vmm, &chan->attrib_cb);
nvkm_vmm_put(chan->vmm, &chan->unknown);
nvkm_vmm_put(chan->vmm, &chan->bundle_cb);
nvkm_vmm_put(chan->vmm, &chan->pagepool);
nvkm_vmm_unref(&chan->vmm);
return chan;
}
static const struct nvkm_object_func
gf100_gr_chan = {
.dtor = gf100_gr_chan_dtor,
.bind = gf100_gr_chan_bind,
};
static int
gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct gf100_gr *gr = gf100_gr(base);
struct gf100_gr_chan *chan;
struct gf100_vmm_map_v0 args = { .priv = 1 };
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->vmm = nvkm_vmm_ref(fifoch->vmm);
*pobject = &chan->object;
/* Map pagepool. */
ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->pagepool), &chan->pagepool);
if (ret)
return ret;
ret = nvkm_memory_map(gr->pagepool, 0, chan->vmm, chan->pagepool, &args, sizeof(args));
if (ret)
return ret;
/* Map bundle circular buffer. */
ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->bundle_cb), &chan->bundle_cb);
if (ret)
return ret;
ret = nvkm_memory_map(gr->bundle_cb, 0, chan->vmm, chan->bundle_cb, &args, sizeof(args));
if (ret)
return ret;
/* Map attribute circular buffer. */
ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->attrib_cb), &chan->attrib_cb);
if (ret)
return ret;
if (device->card_type < GP100) {
ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb, NULL, 0);
if (ret)
return ret;
} else {
ret = nvkm_memory_map(gr->attrib_cb, 0, chan->vmm, chan->attrib_cb,
&args, sizeof(args));;
if (ret)
return ret;
}
/* Map some context buffer of unknown purpose. */
if (gr->func->grctx->unknown_size) {
ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->unknown), &chan->unknown);
if (ret)
return ret;
ret = nvkm_memory_map(gr->unknown, 0, chan->vmm, chan->unknown,
&args, sizeof(args));
if (ret)
return ret;
}
/* Generate golden context image. */
mutex_lock(&gr->fecs.mutex);
if (gr->data == NULL) {
ret = gf100_grctx_generate(gr, chan, fifoch->inst);
if (ret) {
nvkm_error(&base->engine.subdev, "failed to construct context\n");
return ret;
}
}
mutex_unlock(&gr->fecs.mutex);
/* allocate memory for a "mmio list" buffer that's used by the HUB
* fuc to modify some per-context register settings on first load
* of the context.
*/
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
false, &chan->mmio);
if (ret)
return ret;
ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
if (ret)
return ret;
ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
chan->mmio_vma, &args, sizeof(args));
if (ret)
return ret;
/* finally, fill in the mmio list and point the context at it */
nvkm_kmap(chan->mmio);
gr->func->grctx->pagepool(chan, chan->pagepool->addr);
gr->func->grctx->bundle(chan, chan->bundle_cb->addr, gr->func->grctx->bundle_size);
gr->func->grctx->attrib_cb(chan, chan->attrib_cb->addr, gr->func->grctx->attrib_cb_size(gr));
gr->func->grctx->attrib(chan);
if (gr->func->grctx->patch_ltc)
gr->func->grctx->patch_ltc(chan);
if (gr->func->grctx->unknown_size)
gr->func->grctx->unknown(chan, chan->unknown->addr, gr->func->grctx->unknown_size);
nvkm_done(chan->mmio);
return 0;
}
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf100_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x00006fe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
{ 0x400090, 1, 0x04, 0x00000030 },
{ 0x40013c, 1, 0x04, 0x013901f7 },
{ 0x400140, 1, 0x04, 0x00000100 },
{ 0x400144, 1, 0x04, 0x00000000 },
{ 0x400148, 1, 0x04, 0x00000110 },
{ 0x400138, 1, 0x04, 0x00000000 },
{ 0x400130, 2, 0x04, 0x00000000 },
{ 0x400124, 1, 0x04, 0x00000002 },
{}
};
const struct gf100_gr_init
gf100_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_pri_0[] = {
{ 0x404488, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_rstr2d_0[] = {
{ 0x407808, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_prop_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x80000000 },
{ 0x418384, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_setup_0[] = {
{ 0x418814, 3, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_crstr_0[] = {
{ 0x418b04, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_setup_1[] = {
{ 0x4188c8, 1, 0x04, 0x80000000 },
{ 0x4188cc, 1, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{}
};
const struct gf100_gr_init
gf100_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{}
};
const struct gf100_gr_init
gf100_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000050 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_gcc_0[] = {
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_tpccs_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
const struct gf100_gr_init
gf100_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00008bf4 },
{ 0x419cbc, 1, 0x04, 0x28137606 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_mpc_0[] = {
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x06060618 },
{ 0x419ed0, 1, 0x04, 0x0eff0e38 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408910, 9, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
{ 0x408954, 1, 0x04, 0x0000ffff },
{ 0x408984, 1, 0x04, 0x00000000 },
{ 0x408988, 1, 0x04, 0x08040201 },
{ 0x40898c, 1, 0x04, 0x80402010 },
{}
};
const struct gf100_gr_init
gf100_gr_init_fe_1[] = {
{ 0x4040f0, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_gr_init_pe_1[] = {
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_pack
gf100_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gf100_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf100_gr_init_prop_0 },
{ gf100_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf100_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gf100_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf100_gr_init_tex_0 },
{ gf100_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_wwdx_0 },
{ gf100_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf100_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{ gf100_gr_init_pe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static u32
gf100_gr_ctxsw_inst(struct nvkm_gr *gr)
{
return nvkm_rd32(gr->engine.subdev.device, 0x409b00);
}
static int
gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409804, 0xffffffff);
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0xffffffff);
nvkm_wr32(device, 0x409504, mthd);
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x409804);
if (stat == 0x00000002)
return -EIO;
if (stat == 0x00000001)
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
int ret = 0;
mutex_lock(&gr->fecs.mutex);
if (!--gr->fecs.disable) {
if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39)))
gr->fecs.disable++;
}
mutex_unlock(&gr->fecs.mutex);
return ret;
}
static int
gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
int ret = 0;
mutex_lock(&gr->fecs.mutex);
if (!gr->fecs.disable++) {
if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38)))
gr->fecs.disable--;
}
mutex_unlock(&gr->fecs.mutex);
return ret;
}
static int
gf100_gr_fecs_halt_pipeline(struct gf100_gr *gr)
{
int ret = 0;
if (gr->firmware) {
mutex_lock(&gr->fecs.mutex);
ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x04);
mutex_unlock(&gr->fecs.mutex);
}
return ret;
}
int
gf100_gr_fecs_wfi_golden_save(struct gf100_gr *gr, u32 inst)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x409800, 0x00000003, 0x00000000);
nvkm_wr32(device, 0x409500, inst);
nvkm_wr32(device, 0x409504, 0x00000009);
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x409800);
if (stat & 0x00000002)
return -EIO;
if (stat & 0x00000001)
return 0;
);
return -ETIMEDOUT;
}
int
gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x409800, 0x00000030, 0x00000000);
nvkm_wr32(device, 0x409500, inst);
nvkm_wr32(device, 0x409504, 0x00000003);
nvkm_msec(device, 2000,
u32 stat = nvkm_rd32(device, 0x409800);
if (stat & 0x00000020)
return -EIO;
if (stat & 0x00000010)
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409810, addr >> 8);
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000032);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) == 0x00000001)
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409810, inst);
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000031);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) == 0x00000001)
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000030);
nvkm_msec(device, 2000,
if ((*psize = nvkm_rd32(device, 0x409800)))
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_elpg_bind(struct gf100_gr *gr)
{
u32 size;
int ret;
ret = gf100_gr_fecs_discover_reglist_image_size(gr, &size);
if (ret)
return ret;
/*XXX: We need to allocate + map the above into PMU's inst block,
* which which means we probably need a proper PMU before we
* even bother.
*/
ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0);
if (ret)
return ret;
return gf100_gr_fecs_set_reglist_virtual_address(gr, 0);
}
static int
gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000025);
nvkm_msec(device, 2000,
if ((*psize = nvkm_rd32(device, 0x409800)))
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000016);
nvkm_msec(device, 2000,
if ((*psize = nvkm_rd32(device, 0x409800)))
return 0;
);
return -ETIMEDOUT;
}
static int
gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000010);
nvkm_msec(device, 2000,
if ((*psize = nvkm_rd32(device, 0x409800)))
return 0;
);
return -ETIMEDOUT;
}
static void
gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, timeout);
nvkm_wr32(device, 0x409504, 0x00000021);
}
static bool
gf100_gr_chsw_load(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
if (!gr->firmware) {
u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
if (trace & 0x00000040)
return true;
} else {
u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
if (mthd & 0x00080000)
return true;
}
return false;
}
int
gf100_gr_rops(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
}
void
gf100_gr_zbc_init(struct gf100_gr *gr)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int index, c = ltc->zbc_color_min, d = ltc->zbc_depth_min, s = ltc->zbc_depth_min;
if (!gr->zbc_color[0].format) {
gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++;
gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++;
gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++;
gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++;
gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;
gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;
if (gr->func->zbc->stencil_get) {
gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++;
gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++;
gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++;
}
}
for (index = c; index <= ltc->zbc_color_max; index++)
gr->func->zbc->clear_color(gr, index);
for (index = d; index <= ltc->zbc_depth_max; index++)
gr->func->zbc->clear_depth(gr, index);
if (gr->func->zbc->clear_stencil) {
for (index = s; index <= ltc->zbc_depth_max; index++)
gr->func->zbc->clear_stencil(gr, index);
}
}
/**
* Wait until GR goes idle. GR is considered idle if it is disabled by the
* MC (0x200) register, or GR is not busy and a context switch is not in
* progress.
*/
int
gf100_gr_wait_idle(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
bool gr_enabled, ctxsw_active, gr_busy;
do {
/*
* required to make sure FIFO_ENGINE_STATUS (0x2640) is
* up-to-date
*/
nvkm_rd32(device, 0x400700);
gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
ctxsw_active = nvkm_fifo_ctxsw_in_progress(&gr->base.engine);
gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
if (!gr_enabled || (!gr_busy && !ctxsw_active))
return 0;
} while (time_before(jiffies, end_jiffies));
nvkm_error(subdev,
"wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
gr_enabled, ctxsw_active, gr_busy);
return -EAGAIN;
}
void
gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
while (addr < next) {
nvkm_wr32(device, addr, init->data);
addr += init->pitch;
}
}
}
void
gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u64 data = 0;
nvkm_wr32(device, 0x400208, 0x80000000);
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
nvkm_wr32(device, 0x400204, init->data);
if (pack->type == 64)
nvkm_wr32(device, 0x40020c, upper_32_bits(init->data));
data = init->data;
}
while (addr < next) {
nvkm_wr32(device, 0x400200, addr);
/**
* Wait for GR to go idle after submitting a
* GO_IDLE bundle
*/
if ((addr & 0xffff) == 0xe100)
gf100_gr_wait_idle(gr);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
break;
);
addr += init->pitch;
}
}
nvkm_wr32(device, 0x400208, 0x00000000);
}
void
gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_gr_pack *pack;
const struct gf100_gr_init *init;
u32 data = 0;
pack_for_each_init(init, pack, p) {
u32 ctrl = 0x80000000 | pack->type;
u32 next = init->addr + init->count * init->pitch;
u32 addr = init->addr;
if ((pack == p && init == p->init) || data != init->data) {
nvkm_wr32(device, 0x40448c, init->data);
data = init->data;
}
while (addr < next) {
nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
addr += init->pitch;
}
}
}
u64
gf100_gr_units(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
u64 cfg;
cfg = (u32)gr->gpc_nr;
cfg |= (u32)gr->tpc_total << 8;
cfg |= (u64)gr->rop_nr << 32;
return cfg;
}
static const struct nvkm_bitfield gf100_dispatch_error[] = {
{ 0x00000001, "INJECTED_BUNDLE_ERROR" },
{ 0x00000002, "CLASS_SUBCH_MISMATCH" },
{ 0x00000004, "SUBCHSW_DURING_NOTIFY" },
{}
};
static const struct nvkm_bitfield gf100_m2mf_error[] = {
{ 0x00000001, "PUSH_TOO_MUCH_DATA" },
{ 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
{}
};
static const struct nvkm_bitfield gf100_unk6_error[] = {
{ 0x00000001, "TEMP_TOO_SMALL" },
{}
};
static const struct nvkm_bitfield gf100_ccache_error[] = {
{ 0x00000001, "INTR" },
{ 0x00000002, "LDCONST_OOB" },
{}
};
static const struct nvkm_bitfield gf100_macro_error[] = {
{ 0x00000001, "TOO_FEW_PARAMS" },
{ 0x00000002, "TOO_MANY_PARAMS" },
{ 0x00000004, "ILLEGAL_OPCODE" },
{ 0x00000008, "DOUBLE_BRANCH" },
{ 0x00000010, "WATCHDOG" },
{}
};
static const struct nvkm_bitfield gk104_sked_error[] = {
{ 0x00000040, "CTA_RESUME" },
{ 0x00000080, "CONSTANT_BUFFER_SIZE" },
{ 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
{ 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
{ 0x00000800, "WARP_CSTACK_SIZE" },
{ 0x00001000, "TOTAL_TEMP_SIZE" },
{ 0x00002000, "REGISTER_COUNT" },
{ 0x00040000, "TOTAL_THREADS" },
{ 0x00100000, "PROGRAM_OFFSET" },
{ 0x00200000, "SHARED_MEMORY_SIZE" },
{ 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
{ 0x01000000, "MEMORY_WINDOW_OVERLAP" },
{ 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
{ 0x04000000, "TOTAL_REGISTER_COUNT" },
{}
};
static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
{ 0x00000002, "RT_PITCH_OVERRUN" },
{ 0x00000010, "RT_WIDTH_OVERRUN" },
{ 0x00000020, "RT_HEIGHT_OVERRUN" },
{ 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
{ 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
{ 0x00000400, "RT_LINEAR_MISMATCH" },
{}
};
static void
gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
char error[128];
u32 trap[4];
trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
"format = %x, storage type = %x\n",
gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
(trap[2] >> 8) & 0x3f, trap[3] & 0xff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
const struct nvkm_enum gf100_mp_warp_error[] = {
{ 0x01, "STACK_ERROR" },
{ 0x02, "API_STACK_ERROR" },
{ 0x03, "RET_EMPTY_STACK_ERROR" },
{ 0x04, "PC_WRAP" },
{ 0x05, "MISALIGNED_PC" },
{ 0x06, "PC_OVERFLOW" },
{ 0x07, "MISALIGNED_IMMC_ADDR" },
{ 0x08, "MISALIGNED_REG" },
{ 0x09, "ILLEGAL_INSTR_ENCODING" },
{ 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
{ 0x0b, "ILLEGAL_INSTR_PARAM" },
{ 0x0c, "INVALID_CONST_ADDR" },
{ 0x0d, "OOR_REG" },
{ 0x0e, "OOR_ADDR" },
{ 0x0f, "MISALIGNED_ADDR" },
{ 0x10, "INVALID_ADDR_SPACE" },
{ 0x11, "ILLEGAL_INSTR_PARAM2" },
{ 0x12, "INVALID_CONST_ADDR_LDC" },
{ 0x13, "GEOMETRY_SM_ERROR" },
{ 0x14, "DIVERGENT" },
{ 0x15, "WARP_EXIT" },
{}
};
const struct nvkm_bitfield gf100_mp_global_error[] = {
{ 0x00000001, "SM_TO_SM_FAULT" },
{ 0x00000002, "L1_ERROR" },
{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
{ 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
{ 0x00000010, "BPT_INT" },
{ 0x00000020, "BPT_PAUSE" },
{ 0x00000040, "SINGLE_STEP_COMPLETE" },
{ 0x20000000, "ECC_SEC_ERROR" },
{ 0x40000000, "ECC_DED_ERROR" },
{ 0x80000000, "TIMEOUT" },
{}
};
void
gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
const struct nvkm_enum *warp;
char glob[128];
nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
"global %08x [%s] warp %04x [%s]\n",
gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
}
static void
gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
if (stat & 0x00000001) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
gr->func->trap_mp(gr, gpc, tpc);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
stat &= ~0x00000008;
}
if (stat & 0x00000010) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
stat &= ~0x00000010;
}
if (stat) {
nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
}
}
static void
gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
gf100_gr_trap_gpc_rop(gr, gpc);
stat &= ~0x00000001;
}
if (stat & 0x00000002) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
stat &= ~0x00000009;
}
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
gf100_gr_trap_tpc(gr, gpc, tpc);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
}
if (stat) {
nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
}
}
static void
gf100_gr_trap_intr(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
char error[128];
u32 trap = nvkm_rd32(device, 0x400108);
int rop, gpc;
if (trap & 0x00000001) {
u32 stat = nvkm_rd32(device, 0x404000);
nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
stat & 0x3fffffff);
nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000001);
trap &= ~0x00000001;
}
if (trap & 0x00000002) {
u32 stat = nvkm_rd32(device, 0x404600);
nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
stat & 0x3fffffff);
nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000002);
trap &= ~0x00000002;
}
if (trap & 0x00000008) {
u32 stat = nvkm_rd32(device, 0x408030);
nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
stat & 0x3fffffff);
nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000008);
trap &= ~0x00000008;
}
if (trap & 0x00000010) {
u32 stat = nvkm_rd32(device, 0x405840);
nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
stat, stat & 0xffffff, (stat >> 24) & 0x3f);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000010);
trap &= ~0x00000010;
}
if (trap & 0x00000040) {
u32 stat = nvkm_rd32(device, 0x40601c);
nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
stat & 0x3fffffff);
nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
nvkm_wr32(device, 0x40601c, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000040);
trap &= ~0x00000040;
}
if (trap & 0x00000080) {
u32 stat = nvkm_rd32(device, 0x404490);
u32 pc = nvkm_rd32(device, 0x404494);
u32 op = nvkm_rd32(device, 0x40449c);
nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
stat & 0x1fffffff);
nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
stat, error, pc & 0x7ff,
(pc & 0x10000000) ? "" : " (invalid)",
op);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000080);
trap &= ~0x00000080;
}
if (trap & 0x00000100) {
u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
if (stat)
nvkm_wr32(device, 0x407020, 0x40000000);
nvkm_wr32(device, 0x400108, 0x00000100);
trap &= ~0x00000100;
}
if (trap & 0x01000000) {
u32 stat = nvkm_rd32(device, 0x400118);
for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
gf100_gr_trap_gpc(gr, gpc);
nvkm_wr32(device, 0x400118, mask);
stat &= ~mask;
}
}
nvkm_wr32(device, 0x400108, 0x01000000);
trap &= ~0x01000000;
}
if (trap & 0x02000000) {
for (rop = 0; rop < gr->rop_nr; rop++) {
u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
nvkm_error(subdev, "ROP%d %08x %08x\n",
rop, statz, statc);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
}
nvkm_wr32(device, 0x400108, 0x02000000);
trap &= ~0x02000000;
}
if (trap) {
nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
nvkm_wr32(device, 0x400108, trap);
}
}
static void
gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
nvkm_error(subdev, "%06x - done %08x\n", base,
nvkm_rd32(device, base + 0x400));
nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
nvkm_rd32(device, base + 0x800),
nvkm_rd32(device, base + 0x804),
nvkm_rd32(device, base + 0x808),
nvkm_rd32(device, base + 0x80c));
nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
nvkm_rd32(device, base + 0x810),
nvkm_rd32(device, base + 0x814),
nvkm_rd32(device, base + 0x818),
nvkm_rd32(device, base + 0x81c));
}
void
gf100_gr_ctxctl_debug(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
u32 gpc;
gf100_gr_ctxctl_debug_unit(gr, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
}
static void
gf100_gr_ctxctl_isr(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x409c18);
if (!gr->firmware && (stat & 0x00000001)) {
u32 code = nvkm_rd32(device, 0x409814);
if (code == E_BAD_FWMTHD) {
u32 class = nvkm_rd32(device, 0x409808);
u32 addr = nvkm_rd32(device, 0x40980c);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00003ffc);
u32 data = nvkm_rd32(device, 0x409810);
nvkm_error(subdev, "FECS MTHD subc %d class %04x "
"mthd %04x data %08x\n",
subc, class, mthd, data);
} else {
nvkm_error(subdev, "FECS ucode error %d\n", code);
}
nvkm_wr32(device, 0x409c20, 0x00000001);
stat &= ~0x00000001;
}
if (!gr->firmware && (stat & 0x00080000)) {
nvkm_error(subdev, "FECS watchdog timeout\n");
gf100_gr_ctxctl_debug(gr);
nvkm_wr32(device, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nvkm_error(subdev, "FECS %08x\n", stat);
gf100_gr_ctxctl_debug(gr);
nvkm_wr32(device, 0x409c20, stat);
}
}
static irqreturn_t
gf100_gr_intr(struct nvkm_inth *inth)
{
struct gf100_gr *gr = container_of(inth, typeof(*gr), base.engine.subdev.inth);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_chan *chan;
unsigned long flags;
u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
u32 stat = nvkm_rd32(device, 0x400100);
u32 addr = nvkm_rd32(device, 0x400704);
u32 mthd = (addr & 0x00003ffc);
u32 subc = (addr & 0x00070000) >> 16;
u32 data = nvkm_rd32(device, 0x400708);
u32 code = nvkm_rd32(device, 0x400110);
u32 class;
const char *name = "unknown";
int chid = -1;
chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags);
if (chan) {
name = chan->name;
chid = chan->id;
}
if (device->card_type < NV_E0 || subc < 4)
class = nvkm_rd32(device, 0x404200 + (subc * 4));
else
class = 0x0000;
if (stat & 0x00000001) {
/*
* notifier interrupt, only needed for cyclestats
* can be safely ignored
*/
nvkm_wr32(device, 0x400100, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00000010) {
if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
chid, inst << 12, name, subc,
class, mthd, data);
}
nvkm_wr32(device, 0x400100, 0x00000010);
stat &= ~0x00000010;
}
if (stat & 0x00000020) {
nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
chid, inst << 12, name, subc, class, mthd, data);
nvkm_wr32(device, 0x400100, 0x00000020);
stat &= ~0x00000020;
}
if (stat & 0x00100000) {
const struct nvkm_enum *en =
nvkm_enum_find(nv50_data_error_names, code);
nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
code, en ? en->name : "", chid, inst << 12,
name, subc, class, mthd, data);
nvkm_wr32(device, 0x400100, 0x00100000);
stat &= ~0x00100000;
}
if (stat & 0x00200000) {
nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
chid, inst << 12, name);
gf100_gr_trap_intr(gr);
nvkm_wr32(device, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
gf100_gr_ctxctl_isr(gr);
nvkm_wr32(device, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nvkm_error(subdev, "intr %08x\n", stat);
nvkm_wr32(device, 0x400100, stat);
}
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_chan_put(&chan, flags);
return IRQ_HANDLED;
}
static void
gf100_gr_init_fw(struct nvkm_falcon *falcon,
struct nvkm_blob *code, struct nvkm_blob *data)
{
nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
}
static void
gf100_gr_init_csdata(struct gf100_gr *gr,
const struct gf100_gr_pack *pack,
u32 falcon, u32 starstar, u32 base)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_gr_pack *iter;
const struct gf100_gr_init *init;
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
star = nvkm_rd32(device, falcon + 0x01c4);
temp = nvkm_rd32(device, falcon + 0x01c4);
if (temp > star)
star = temp;
nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
pack_for_each_init(init, iter, pack) {
u32 head = init->addr - base;
u32 tail = head + init->count * init->pitch;
while (head < tail) {
if (head != prev + 4 || xfer >= 32) {
if (xfer) {
u32 data = ((--xfer << 26) | addr);
nvkm_wr32(device, falcon + 0x01c4, data);
star += 4;
}
addr = head;
xfer = 0;
}
prev = head;
xfer = xfer + 1;
head = head + init->pitch;
}
}
nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
nvkm_wr32(device, falcon + 0x01c4, star + 4);
}
/* Initialize context from an external (secure or not) firmware */
static int
gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 lsf_mask = 0;
int ret;
/* load fuc microcode */
nvkm_mc_unk260(device, 0);
/* securely-managed falcons must be reset using secure boot */
if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_FECS)) {
gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst,
&gr->fecs.data);
} else {
lsf_mask |= BIT(NVKM_ACR_LSF_FECS);
}
if (!nvkm_acr_managed_falcon(device, NVKM_ACR_LSF_GPCCS)) {
gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst,
&gr->gpccs.data);
} else {
lsf_mask |= BIT(NVKM_ACR_LSF_GPCCS);
}
if (lsf_mask) {
ret = nvkm_acr_bootstrap_falcons(device, lsf_mask);
if (ret)
return ret;
}
nvkm_mc_unk260(device, 1);
/* start both of them running */
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x41a10c, 0x00000000);
nvkm_wr32(device, 0x40910c, 0x00000000);
nvkm_falcon_start(&gr->gpccs.falcon);
nvkm_falcon_start(&gr->fecs.falcon);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) & 0x00000001)
break;
) < 0)
return -EBUSY;
gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff);
/* Determine how much memory is required to store main context image. */
ret = gf100_gr_fecs_discover_image_size(gr, &gr->size);
if (ret)
return ret;
/* Determine how much memory is required to store ZCULL image. */
ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull);
if (ret)
return ret;
/* Determine how much memory is required to store PerfMon image. */
ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm);
if (ret)
return ret;
/*XXX: We (likely) require PMU support to even bother with this.
*
* Also, it seems like not all GPUs support ELPG. Traces I
* have here show RM enabling it on Kepler/Turing, but none
* of the GPUs between those. NVGPU decides this by PCIID.
*/
if (0) {
ret = gf100_gr_fecs_elpg_bind(gr);
if (ret)
return ret;
}
return 0;
}
static int
gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
{
const struct gf100_grctx_func *grctx = gr->func->grctx;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
if (!gr->func->fecs.ucode) {
return -ENOSYS;
}
/* load HUB microcode */
nvkm_mc_unk260(device, 0);
nvkm_falcon_load_dmem(&gr->fecs.falcon,
gr->func->fecs.ucode->data.data, 0x0,
gr->func->fecs.ucode->data.size, 0);
nvkm_falcon_load_imem(&gr->fecs.falcon,
gr->func->fecs.ucode->code.data, 0x0,
gr->func->fecs.ucode->code.size, 0, 0, false);
/* load GPC microcode */
nvkm_falcon_load_dmem(&gr->gpccs.falcon,
gr->func->gpccs.ucode->data.data, 0x0,
gr->func->gpccs.ucode->data.size, 0);
nvkm_falcon_load_imem(&gr->gpccs.falcon,
gr->func->gpccs.ucode->code.data, 0x0,
gr->func->gpccs.ucode->code.size, 0, 0, false);
nvkm_mc_unk260(device, 1);
/* load register lists */
gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000);
gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000);
gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
nvkm_wr32(device, 0x40910c, 0x00000000);
nvkm_wr32(device, 0x409100, 0x00000002);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) & 0x80000000)
break;
) < 0) {
gf100_gr_ctxctl_debug(gr);
return -EBUSY;
}
gr->size = nvkm_rd32(device, 0x409804);
return 0;
}
int
gf100_gr_init_ctxctl(struct gf100_gr *gr)
{
int ret;
if (gr->firmware)
ret = gf100_gr_init_ctxctl_ext(gr);
else
ret = gf100_gr_init_ctxctl_int(gr);
return ret;
}
int
gf100_gr_oneinit_sm_id(struct gf100_gr *gr)
{
int tpc, gpc;
for (tpc = 0; tpc < gr->tpc_max; tpc++) {
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
if (tpc < gr->tpc_nr[gpc]) {
gr->sm[gr->sm_nr].gpc = gpc;
gr->sm[gr->sm_nr].tpc = tpc;
gr->sm_nr++;
}
}
}
return 0;
}
void
gf100_gr_oneinit_tiles(struct gf100_gr *gr)
{
static const u8 primes[] = {
3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61
};
int init_frac[GPC_MAX], init_err[GPC_MAX], run_err[GPC_MAX], i, j;
u32 mul_factor, comm_denom;
u8 gpc_map[GPC_MAX];
bool sorted;
switch (gr->tpc_total) {
case 15: gr->screen_tile_row_offset = 0x06; break;
case 14: gr->screen_tile_row_offset = 0x05; break;
case 13: gr->screen_tile_row_offset = 0x02; break;
case 11: gr->screen_tile_row_offset = 0x07; break;
case 10: gr->screen_tile_row_offset = 0x06; break;
case 7:
case 5: gr->screen_tile_row_offset = 0x01; break;
case 3: gr->screen_tile_row_offset = 0x02; break;
case 2:
case 1: gr->screen_tile_row_offset = 0x01; break;
default: gr->screen_tile_row_offset = 0x03;
for (i = 0; i < ARRAY_SIZE(primes); i++) {
if (gr->tpc_total % primes[i]) {
gr->screen_tile_row_offset = primes[i];
break;
}
}
break;
}
/* Sort GPCs by TPC count, highest-to-lowest. */
for (i = 0; i < gr->gpc_nr; i++)
gpc_map[i] = i;
sorted = false;
while (!sorted) {
for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) {
if (gr->tpc_nr[gpc_map[i + 1]] >
gr->tpc_nr[gpc_map[i + 0]]) {
u8 swap = gpc_map[i];
gpc_map[i + 0] = gpc_map[i + 1];
gpc_map[i + 1] = swap;
sorted = false;
}
}
}
/* Determine tile->GPC mapping */
mul_factor = gr->gpc_nr * gr->tpc_max;
if (mul_factor & 1)
mul_factor = 2;
else
mul_factor = 1;
comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor;
for (i = 0; i < gr->gpc_nr; i++) {
init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor;
init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2;
run_err[i] = init_frac[i] + init_err[i];
}
for (i = 0; i < gr->tpc_total;) {
for (j = 0; j < gr->gpc_nr; j++) {
if ((run_err[j] * 2) >= comm_denom) {
gr->tile[i++] = gpc_map[j];
run_err[j] += init_frac[j] - comm_denom;
} else {
run_err[j] += init_frac[j];
}
}
}
}
static int
gf100_gr_oneinit(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_intr *intr = &device->mc->intr;
enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;
int ret, i, j;
if (gr->func->oneinit_intr)
intr = gr->func->oneinit_intr(gr, &intr_type);
ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,
gf100_gr_intr, &gr->base.engine.subdev.inth);
if (ret)
return ret;
nvkm_pmu_pgob(device->pmu, false);
gr->rop_nr = gr->func->rops(gr);
gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
for (i = 0; i < gr->gpc_nr; i++) {
gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]);
gr->tpc_total += gr->tpc_nr[i];
for (j = 0; j < gr->func->ppc_nr; j++) {
gr->ppc_tpc_mask[i][j] =
nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
if (gr->ppc_tpc_mask[i][j] == 0)
continue;
gr->ppc_nr[i]++;
gr->ppc_mask[i] |= (1 << j);
gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]);
if (gr->ppc_tpc_min == 0 ||
gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j])
gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j];
if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])
gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];
}
gr->ppc_total += gr->ppc_nr[i];
}
/* Allocate global context buffers. */
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->pagepool_size,
0x100, false, &gr->pagepool);
if (ret)
return ret;
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->bundle_size,
0x100, false, &gr->bundle_cb);
if (ret)
return ret;
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->attrib_cb_size(gr),
0x1000, false, &gr->attrib_cb);
if (ret)
return ret;
if (gr->func->grctx->unknown_size) {
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->unknown_size,
0x100, false, &gr->unknown);
if (ret)
return ret;
}
memset(gr->tile, 0xff, sizeof(gr->tile));
gr->func->oneinit_tiles(gr);
return gr->func->oneinit_sm_id(gr);
}
static int
gf100_gr_init_(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &base->engine.subdev;
struct nvkm_device *device = subdev->device;
bool reset = device->chipset == 0x137 || device->chipset == 0x138;
int ret;
/* On certain GP107/GP108 boards, we trigger a weird issue where
* GR will stop responding to PRI accesses after we've asked the
* SEC2 RTOS to boot the GR falcons. This happens with far more
* frequency when cold-booting a board (ie. returning from D3).
*
* The root cause for this is not known and has proven difficult
* to isolate, with many avenues being dead-ends.
*
* A workaround was discovered by Karol, whereby putting GR into
* reset for an extended period right before initialisation
* prevents the problem from occuring.
*
* XXX: As RM does not require any such workaround, this is more
* of a hack than a true fix.
*/
reset = nvkm_boolopt(device->cfgopt, "NvGrResetWar", reset);
if (reset) {
nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
nvkm_rd32(device, 0x000200);
msleep(50);
nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
nvkm_rd32(device, 0x000200);
}
nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
ret = nvkm_falcon_get(&gr->fecs.falcon, subdev);
if (ret)
return ret;
ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev);
if (ret)
return ret;
ret = gr->func->init(gr);
if (ret)
return ret;
nvkm_inth_allow(&subdev->inth);
return 0;
}
static int
gf100_gr_fini(struct nvkm_gr *base, bool suspend)
{
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
nvkm_inth_block(&subdev->inth);
nvkm_falcon_put(&gr->gpccs.falcon, subdev);
nvkm_falcon_put(&gr->fecs.falcon, subdev);
return 0;
}
static void *
gf100_gr_dtor(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
kfree(gr->data);
nvkm_memory_unref(&gr->unknown);
nvkm_memory_unref(&gr->attrib_cb);
nvkm_memory_unref(&gr->bundle_cb);
nvkm_memory_unref(&gr->pagepool);
nvkm_falcon_dtor(&gr->gpccs.falcon);
nvkm_falcon_dtor(&gr->fecs.falcon);
nvkm_blob_dtor(&gr->fecs.inst);
nvkm_blob_dtor(&gr->fecs.data);
nvkm_blob_dtor(&gr->gpccs.inst);
nvkm_blob_dtor(&gr->gpccs.data);
vfree(gr->bundle64);
vfree(gr->bundle_veid);
vfree(gr->bundle);
vfree(gr->method);
vfree(gr->sw_ctx);
vfree(gr->sw_nonctx);
vfree(gr->sw_nonctx1);
vfree(gr->sw_nonctx2);
vfree(gr->sw_nonctx3);
vfree(gr->sw_nonctx4);
return gr;
}
static const struct nvkm_falcon_func
gf100_gr_flcn = {
.load_imem = nvkm_falcon_v1_load_imem,
.load_dmem = nvkm_falcon_v1_load_dmem,
.start = nvkm_falcon_v1_start,
};
void
gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, i, j;
u32 data;
for (gpc = 0, i = 0; i < 4; i++) {
for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++)
data |= gr->tpc_nr[gpc] << (j * 4);
if (pd)
nvkm_wr32(device, 0x406028 + (i * 4), data);
if (ds)
nvkm_wr32(device, 0x405870 + (i * 4), data);
}
}
void
gf100_gr_init_400054(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
}
void
gf100_gr_init_exception2(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
}
void
gf100_gr_init_rop_exceptions(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int rop;
for (rop = 0; rop < gr->rop_nr; rop++) {
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
}
}
void
gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
}
void
gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
}
void
gf100_gr_init_419eb4(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
}
void
gf100_gr_init_419cc0(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc;
nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++)
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
}
}
void
gf100_gr_init_40601c(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
}
void
gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001;
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
}
void
gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fb *fb = device->fb;
nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
nvkm_wr32(device, 0x4188a4, 0x03000000);
nvkm_wr32(device, 0x418888, 0x00000000);
nvkm_wr32(device, 0x41888c, 0x00000000);
nvkm_wr32(device, 0x418890, 0x00000000);
nvkm_wr32(device, 0x418894, 0x00000000);
nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
}
void
gf100_gr_init_num_active_ltcs(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
}
void
gf100_gr_init_zcull(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
const u8 tile_nr = ALIGN(gr->tpc_total, 32);
u8 bank[GPC_MAX] = {}, gpc, i, j;
u32 data;
for (i = 0; i < tile_nr; i += 8) {
for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
data |= bank[gr->tile[i + j]] << (j * 4);
bank[gr->tile[i + j]]++;
}
nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
}
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
}
void
gf100_gr_init_vsc_stream_master(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
}
static int
gf100_gr_reset(struct nvkm_gr *base)
{
struct nvkm_subdev *subdev = &base->engine.subdev;
struct nvkm_device *device = subdev->device;
struct gf100_gr *gr = gf100_gr(base);
nvkm_mask(device, 0x400500, 0x00000001, 0x00000000);
WARN_ON(gf100_gr_fecs_halt_pipeline(gr));
subdev->func->fini(subdev, false);
nvkm_mc_disable(device, subdev->type, subdev->inst);
if (gr->func->gpccs.reset)
gr->func->gpccs.reset(gr);
nvkm_mc_enable(device, subdev->type, subdev->inst);
return subdev->func->init(subdev);
}
int
gf100_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc;
nvkm_mask(device, 0x400500, 0x00010001, 0x00000000);
gr->func->init_gpc_mmu(gr);
if (gr->sw_nonctx1) {
gf100_gr_mmio(gr, gr->sw_nonctx1);
gf100_gr_mmio(gr, gr->sw_nonctx2);
gf100_gr_mmio(gr, gr->sw_nonctx3);
gf100_gr_mmio(gr, gr->sw_nonctx4);
} else
if (gr->sw_nonctx) {
gf100_gr_mmio(gr, gr->sw_nonctx);
} else {
gf100_gr_mmio(gr, gr->func->mmio);
}
gf100_gr_wait_idle(gr);
if (gr->func->init_r405a14)
gr->func->init_r405a14(gr);
if (gr->func->clkgate_pack)
nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack);
if (gr->func->init_bios)
gr->func->init_bios(gr);
gr->func->init_vsc_stream_master(gr);
gr->func->init_zcull(gr);
gr->func->init_num_active_ltcs(gr);
if (gr->func->init_rop_active_fbps)
gr->func->init_rop_active_fbps(gr);
if (gr->func->init_bios_2)
gr->func->init_bios_2(gr);
if (gr->func->init_swdx_pes_mask)
gr->func->init_swdx_pes_mask(gr);
if (gr->func->init_fs)
gr->func->init_fs(gr);
nvkm_wr32(device, 0x400500, 0x00010001);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
gr->func->init_fecs_exceptions(gr);
if (gr->func->init_40a790)
gr->func->init_40a790(gr);
if (gr->func->init_ds_hww_esr_2)
gr->func->init_ds_hww_esr_2(gr);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
if (gr->func->init_40601c)
gr->func->init_40601c(gr);
nvkm_wr32(device, 0x406018, 0xc0000000);
nvkm_wr32(device, 0x404490, 0xc0000000);
if (gr->func->init_sked_hww_esr)
gr->func->init_sked_hww_esr(gr);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x405844, 0x00ffffff);
if (gr->func->init_419cc0)
gr->func->init_419cc0(gr);
if (gr->func->init_419eb4)
gr->func->init_419eb4(gr);
if (gr->func->init_419c9c)
gr->func->init_419c9c(gr);
if (gr->func->init_ppc_exceptions)
gr->func->init_ppc_exceptions(gr);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
if (gr->func->init_tex_hww_esr)
gr->func->init_tex_hww_esr(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
if (gr->func->init_504430)
gr->func->init_504430(gr, gpc, tpc);
gr->func->init_shader_exceptions(gr, gpc, tpc);
}
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
}
gr->func->init_rop_exceptions(gr);
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
if (gr->func->init_exception2)
gr->func->init_exception2(gr);
if (gr->func->init_400054)
gr->func->init_400054(gr);
gf100_gr_zbc_init(gr);
if (gr->func->init_4188a4)
gr->func->init_4188a4(gr);
return gf100_gr_init_ctxctl(gr);
}
void
gf100_gr_fecs_reset(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409614, 0x00000070);
nvkm_usec(device, 10, NVKM_DELAY);
nvkm_mask(device, 0x409614, 0x00000700, 0x00000700);
nvkm_usec(device, 10, NVKM_DELAY);
nvkm_rd32(device, 0x409614);
}
#include "fuc/hubgf100.fuc3.h"
struct gf100_gr_ucode
gf100_gr_fecs_ucode = {
.code.data = gf100_grhub_code,
.code.size = sizeof(gf100_grhub_code),
.data.data = gf100_grhub_data,
.data.size = sizeof(gf100_grhub_data),
};
#include "fuc/gpcgf100.fuc3.h"
struct gf100_gr_ucode
gf100_gr_gpccs_ucode = {
.code.data = gf100_grgpc_code,
.code.size = sizeof(gf100_grgpc_code),
.data.data = gf100_grgpc_data,
.data.size = sizeof(gf100_grgpc_data),
};
static int
gf100_gr_nonstall(struct nvkm_gr *base)
{
struct gf100_gr *gr = gf100_gr(base);
if (gr->func->nonstall)
return gr->func->nonstall(gr);
return -EINVAL;
}
static const struct nvkm_gr_func
gf100_gr_ = {
.dtor = gf100_gr_dtor,
.oneinit = gf100_gr_oneinit,
.init = gf100_gr_init_,
.fini = gf100_gr_fini,
.nonstall = gf100_gr_nonstall,
.reset = gf100_gr_reset,
.units = gf100_gr_units,
.chan_new = gf100_gr_chan_new,
.object_get = gf100_gr_object_get,
.chsw_load = gf100_gr_chsw_load,
.ctxsw.pause = gf100_gr_fecs_stop_ctxsw,
.ctxsw.resume = gf100_gr_fecs_start_ctxsw,
.ctxsw.inst = gf100_gr_ctxsw_inst,
};
static const struct gf100_gr_func
gf100_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf100_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf100_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.grctx = &gf100_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{}
}
};
int
gf100_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
gr->firmware = false;
return 0;
}
static int
gf100_gr_load_fw(struct gf100_gr *gr, const char *name,
struct nvkm_blob *blob)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
const struct firmware *fw;
char f[32];
int ret;
snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, name);
ret = request_firmware(&fw, f, device->dev);
if (ret) {
snprintf(f, sizeof(f), "nouveau/%s", name);
ret = request_firmware(&fw, f, device->dev);
if (ret) {
nvkm_error(subdev, "failed to load %s\n", name);
return ret;
}
}
blob->size = fw->size;
blob->data = kmemdup(fw->data, blob->size, GFP_KERNEL);
release_firmware(fw);
return (blob->data != NULL) ? 0 : -ENOMEM;
}
int
gf100_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
if (!nvkm_boolopt(device->cfgopt, "NvGrUseFW", false))
return -EINVAL;
if (gf100_gr_load_fw(gr, "fuc409c", &gr->fecs.inst) ||
gf100_gr_load_fw(gr, "fuc409d", &gr->fecs.data) ||
gf100_gr_load_fw(gr, "fuc41ac", &gr->gpccs.inst) ||
gf100_gr_load_fw(gr, "fuc41ad", &gr->gpccs.data))
return -ENOENT;
gr->firmware = true;
return 0;
}
static const struct gf100_gr_fwif
gf100_gr_fwif[] = {
{ -1, gf100_gr_load, &gf100_gr },
{ -1, gf100_gr_nofw, &gf100_gr },
{}
};
int
gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct gf100_gr *gr;
int ret;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
*pgr = &gr->base;
ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base);
if (ret)
return ret;
fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr);
if (IS_ERR(fwif))
return PTR_ERR(fwif);
gr->func = fwif->func;
ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev,
"fecs", 0x409000, &gr->fecs.falcon);
if (ret)
return ret;
mutex_init(&gr->fecs.mutex);
ret = nvkm_falcon_ctor(&gf100_gr_flcn, &gr->base.engine.subdev,
"gpccs", 0x41a000, &gr->gpccs.falcon);
if (ret)
return ret;
return 0;
}
int
gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c |
/*
* Copyright 2007 Matthieu CASTET <[email protected]>
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nv10.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
struct pipe_state {
u32 pipe_0x0000[0x040/4];
u32 pipe_0x0040[0x010/4];
u32 pipe_0x0200[0x0c0/4];
u32 pipe_0x4400[0x080/4];
u32 pipe_0x6400[0x3b0/4];
u32 pipe_0x6800[0x2f0/4];
u32 pipe_0x6c00[0x030/4];
u32 pipe_0x7000[0x130/4];
u32 pipe_0x7400[0x0c0/4];
u32 pipe_0x7800[0x0c0/4];
};
static int nv10_gr_ctx_regs[] = {
NV10_PGRAPH_CTX_SWITCH(0),
NV10_PGRAPH_CTX_SWITCH(1),
NV10_PGRAPH_CTX_SWITCH(2),
NV10_PGRAPH_CTX_SWITCH(3),
NV10_PGRAPH_CTX_SWITCH(4),
NV10_PGRAPH_CTX_CACHE(0, 0),
NV10_PGRAPH_CTX_CACHE(0, 1),
NV10_PGRAPH_CTX_CACHE(0, 2),
NV10_PGRAPH_CTX_CACHE(0, 3),
NV10_PGRAPH_CTX_CACHE(0, 4),
NV10_PGRAPH_CTX_CACHE(1, 0),
NV10_PGRAPH_CTX_CACHE(1, 1),
NV10_PGRAPH_CTX_CACHE(1, 2),
NV10_PGRAPH_CTX_CACHE(1, 3),
NV10_PGRAPH_CTX_CACHE(1, 4),
NV10_PGRAPH_CTX_CACHE(2, 0),
NV10_PGRAPH_CTX_CACHE(2, 1),
NV10_PGRAPH_CTX_CACHE(2, 2),
NV10_PGRAPH_CTX_CACHE(2, 3),
NV10_PGRAPH_CTX_CACHE(2, 4),
NV10_PGRAPH_CTX_CACHE(3, 0),
NV10_PGRAPH_CTX_CACHE(3, 1),
NV10_PGRAPH_CTX_CACHE(3, 2),
NV10_PGRAPH_CTX_CACHE(3, 3),
NV10_PGRAPH_CTX_CACHE(3, 4),
NV10_PGRAPH_CTX_CACHE(4, 0),
NV10_PGRAPH_CTX_CACHE(4, 1),
NV10_PGRAPH_CTX_CACHE(4, 2),
NV10_PGRAPH_CTX_CACHE(4, 3),
NV10_PGRAPH_CTX_CACHE(4, 4),
NV10_PGRAPH_CTX_CACHE(5, 0),
NV10_PGRAPH_CTX_CACHE(5, 1),
NV10_PGRAPH_CTX_CACHE(5, 2),
NV10_PGRAPH_CTX_CACHE(5, 3),
NV10_PGRAPH_CTX_CACHE(5, 4),
NV10_PGRAPH_CTX_CACHE(6, 0),
NV10_PGRAPH_CTX_CACHE(6, 1),
NV10_PGRAPH_CTX_CACHE(6, 2),
NV10_PGRAPH_CTX_CACHE(6, 3),
NV10_PGRAPH_CTX_CACHE(6, 4),
NV10_PGRAPH_CTX_CACHE(7, 0),
NV10_PGRAPH_CTX_CACHE(7, 1),
NV10_PGRAPH_CTX_CACHE(7, 2),
NV10_PGRAPH_CTX_CACHE(7, 3),
NV10_PGRAPH_CTX_CACHE(7, 4),
NV10_PGRAPH_CTX_USER,
NV04_PGRAPH_DMA_START_0,
NV04_PGRAPH_DMA_START_1,
NV04_PGRAPH_DMA_LENGTH,
NV04_PGRAPH_DMA_MISC,
NV10_PGRAPH_DMA_PITCH,
NV04_PGRAPH_BOFFSET0,
NV04_PGRAPH_BBASE0,
NV04_PGRAPH_BLIMIT0,
NV04_PGRAPH_BOFFSET1,
NV04_PGRAPH_BBASE1,
NV04_PGRAPH_BLIMIT1,
NV04_PGRAPH_BOFFSET2,
NV04_PGRAPH_BBASE2,
NV04_PGRAPH_BLIMIT2,
NV04_PGRAPH_BOFFSET3,
NV04_PGRAPH_BBASE3,
NV04_PGRAPH_BLIMIT3,
NV04_PGRAPH_BOFFSET4,
NV04_PGRAPH_BBASE4,
NV04_PGRAPH_BLIMIT4,
NV04_PGRAPH_BOFFSET5,
NV04_PGRAPH_BBASE5,
NV04_PGRAPH_BLIMIT5,
NV04_PGRAPH_BPITCH0,
NV04_PGRAPH_BPITCH1,
NV04_PGRAPH_BPITCH2,
NV04_PGRAPH_BPITCH3,
NV04_PGRAPH_BPITCH4,
NV10_PGRAPH_SURFACE,
NV10_PGRAPH_STATE,
NV04_PGRAPH_BSWIZZLE2,
NV04_PGRAPH_BSWIZZLE5,
NV04_PGRAPH_BPIXEL,
NV10_PGRAPH_NOTIFY,
NV04_PGRAPH_PATT_COLOR0,
NV04_PGRAPH_PATT_COLOR1,
NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
0x00400904,
0x00400908,
0x0040090c,
0x00400910,
0x00400914,
0x00400918,
0x0040091c,
0x00400920,
0x00400924,
0x00400928,
0x0040092c,
0x00400930,
0x00400934,
0x00400938,
0x0040093c,
0x00400940,
0x00400944,
0x00400948,
0x0040094c,
0x00400950,
0x00400954,
0x00400958,
0x0040095c,
0x00400960,
0x00400964,
0x00400968,
0x0040096c,
0x00400970,
0x00400974,
0x00400978,
0x0040097c,
0x00400980,
0x00400984,
0x00400988,
0x0040098c,
0x00400990,
0x00400994,
0x00400998,
0x0040099c,
0x004009a0,
0x004009a4,
0x004009a8,
0x004009ac,
0x004009b0,
0x004009b4,
0x004009b8,
0x004009bc,
0x004009c0,
0x004009c4,
0x004009c8,
0x004009cc,
0x004009d0,
0x004009d4,
0x004009d8,
0x004009dc,
0x004009e0,
0x004009e4,
0x004009e8,
0x004009ec,
0x004009f0,
0x004009f4,
0x004009f8,
0x004009fc,
NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
0x0040080c,
NV04_PGRAPH_PATTERN_SHAPE,
NV03_PGRAPH_MONO_COLOR0,
NV04_PGRAPH_ROP3,
NV04_PGRAPH_CHROMA,
NV04_PGRAPH_BETA_AND,
NV04_PGRAPH_BETA_PREMULT,
0x00400e70,
0x00400e74,
0x00400e78,
0x00400e7c,
0x00400e80,
0x00400e84,
0x00400e88,
0x00400e8c,
0x00400ea0,
0x00400ea4,
0x00400ea8,
0x00400e90,
0x00400e94,
0x00400e98,
0x00400e9c,
NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */
NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */
0x00400f04,
0x00400f24,
0x00400f08,
0x00400f28,
0x00400f0c,
0x00400f2c,
0x00400f10,
0x00400f30,
0x00400f14,
0x00400f34,
0x00400f18,
0x00400f38,
0x00400f1c,
0x00400f3c,
NV10_PGRAPH_XFMODE0,
NV10_PGRAPH_XFMODE1,
NV10_PGRAPH_GLOBALSTATE0,
NV10_PGRAPH_GLOBALSTATE1,
NV04_PGRAPH_STORED_FMT,
NV04_PGRAPH_SOURCE_COLOR,
NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
0x00400404,
0x00400484,
0x00400408,
0x00400488,
0x0040040c,
0x0040048c,
0x00400410,
0x00400490,
0x00400414,
0x00400494,
0x00400418,
0x00400498,
0x0040041c,
0x0040049c,
0x00400420,
0x004004a0,
0x00400424,
0x004004a4,
0x00400428,
0x004004a8,
0x0040042c,
0x004004ac,
0x00400430,
0x004004b0,
0x00400434,
0x004004b4,
0x00400438,
0x004004b8,
0x0040043c,
0x004004bc,
0x00400440,
0x004004c0,
0x00400444,
0x004004c4,
0x00400448,
0x004004c8,
0x0040044c,
0x004004cc,
0x00400450,
0x004004d0,
0x00400454,
0x004004d4,
0x00400458,
0x004004d8,
0x0040045c,
0x004004dc,
0x00400460,
0x004004e0,
0x00400464,
0x004004e4,
0x00400468,
0x004004e8,
0x0040046c,
0x004004ec,
0x00400470,
0x004004f0,
0x00400474,
0x004004f4,
0x00400478,
0x004004f8,
0x0040047c,
0x004004fc,
NV03_PGRAPH_ABS_UCLIP_XMIN,
NV03_PGRAPH_ABS_UCLIP_XMAX,
NV03_PGRAPH_ABS_UCLIP_YMIN,
NV03_PGRAPH_ABS_UCLIP_YMAX,
0x00400550,
0x00400558,
0x00400554,
0x0040055c,
NV03_PGRAPH_ABS_UCLIPA_XMIN,
NV03_PGRAPH_ABS_UCLIPA_XMAX,
NV03_PGRAPH_ABS_UCLIPA_YMIN,
NV03_PGRAPH_ABS_UCLIPA_YMAX,
NV03_PGRAPH_ABS_ICLIP_XMAX,
NV03_PGRAPH_ABS_ICLIP_YMAX,
NV03_PGRAPH_XY_LOGIC_MISC0,
NV03_PGRAPH_XY_LOGIC_MISC1,
NV03_PGRAPH_XY_LOGIC_MISC2,
NV03_PGRAPH_XY_LOGIC_MISC3,
NV03_PGRAPH_CLIPX_0,
NV03_PGRAPH_CLIPX_1,
NV03_PGRAPH_CLIPY_0,
NV03_PGRAPH_CLIPY_1,
NV10_PGRAPH_COMBINER0_IN_ALPHA,
NV10_PGRAPH_COMBINER1_IN_ALPHA,
NV10_PGRAPH_COMBINER0_IN_RGB,
NV10_PGRAPH_COMBINER1_IN_RGB,
NV10_PGRAPH_COMBINER_COLOR0,
NV10_PGRAPH_COMBINER_COLOR1,
NV10_PGRAPH_COMBINER0_OUT_ALPHA,
NV10_PGRAPH_COMBINER1_OUT_ALPHA,
NV10_PGRAPH_COMBINER0_OUT_RGB,
NV10_PGRAPH_COMBINER1_OUT_RGB,
NV10_PGRAPH_COMBINER_FINAL0,
NV10_PGRAPH_COMBINER_FINAL1,
0x00400e00,
0x00400e04,
0x00400e08,
0x00400e0c,
0x00400e10,
0x00400e14,
0x00400e18,
0x00400e1c,
0x00400e20,
0x00400e24,
0x00400e28,
0x00400e2c,
0x00400e30,
0x00400e34,
0x00400e38,
0x00400e3c,
NV04_PGRAPH_PASSTHRU_0,
NV04_PGRAPH_PASSTHRU_1,
NV04_PGRAPH_PASSTHRU_2,
NV10_PGRAPH_DIMX_TEXTURE,
NV10_PGRAPH_WDIMX_TEXTURE,
NV10_PGRAPH_DVD_COLORFMT,
NV10_PGRAPH_SCALED_FORMAT,
NV04_PGRAPH_MISC24_0,
NV04_PGRAPH_MISC24_1,
NV04_PGRAPH_MISC24_2,
NV03_PGRAPH_X_MISC,
NV03_PGRAPH_Y_MISC,
NV04_PGRAPH_VALID1,
NV04_PGRAPH_VALID2,
};
static int nv17_gr_ctx_regs[] = {
NV10_PGRAPH_DEBUG_4,
0x004006b0,
0x00400eac,
0x00400eb0,
0x00400eb4,
0x00400eb8,
0x00400ebc,
0x00400ec0,
0x00400ec4,
0x00400ec8,
0x00400ecc,
0x00400ed0,
0x00400ed4,
0x00400ed8,
0x00400edc,
0x00400ee0,
0x00400a00,
0x00400a04,
};
#define nv10_gr(p) container_of((p), struct nv10_gr, base)
struct nv10_gr {
struct nvkm_gr base;
struct nv10_gr_chan *chan[32];
spinlock_t lock;
};
#define nv10_gr_chan(p) container_of((p), struct nv10_gr_chan, object)
struct nv10_gr_chan {
struct nvkm_object object;
struct nv10_gr *gr;
int chid;
int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
struct pipe_state pipe_state;
u32 lma_window[4];
};
/*******************************************************************************
* Graphics object classes
******************************************************************************/
#define PIPE_SAVE(gr, state, addr) \
do { \
int __i; \
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \
} while (0)
#define PIPE_RESTORE(gr, state, addr) \
do { \
int __i; \
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
for (__i = 0; __i < ARRAY_SIZE(state); __i++) \
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
} while (0)
static void
nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data)
{
struct nvkm_device *device = chan->object.engine->subdev.device;
struct nvkm_gr *gr = &chan->gr->base;
struct pipe_state *pipe = &chan->pipe_state;
u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
u32 xfmode0, xfmode1;
int i;
chan->lma_window[(mthd - 0x1638) / 4] = data;
if (mthd != 0x1644)
return;
nv04_gr_idle(gr);
PIPE_SAVE(device, pipe_0x0040, 0x0040);
PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200);
PIPE_RESTORE(device, chan->lma_window, 0x6790);
nv04_gr_idle(gr);
xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0);
xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1);
PIPE_SAVE(device, pipe->pipe_0x4400, 0x4400);
PIPE_SAVE(device, pipe_0x64c0, 0x64c0);
PIPE_SAVE(device, pipe_0x6ab0, 0x6ab0);
PIPE_SAVE(device, pipe_0x6a80, 0x6a80);
nv04_gr_idle(gr);
nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);
nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);
PIPE_RESTORE(device, pipe->pipe_0x0200, 0x0200);
nv04_gr_idle(gr);
PIPE_RESTORE(device, pipe_0x0040, 0x0040);
nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);
nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);
PIPE_RESTORE(device, pipe_0x64c0, 0x64c0);
PIPE_RESTORE(device, pipe_0x6ab0, 0x6ab0);
PIPE_RESTORE(device, pipe_0x6a80, 0x6a80);
PIPE_RESTORE(device, pipe->pipe_0x4400, 0x4400);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0);
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
nv04_gr_idle(gr);
}
static void
nv17_gr_mthd_lma_enable(struct nv10_gr_chan *chan, u32 mthd, u32 data)
{
struct nvkm_device *device = chan->object.engine->subdev.device;
struct nvkm_gr *gr = &chan->gr->base;
nv04_gr_idle(gr);
nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100);
nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000);
}
static bool
nv17_gr_mthd_celcius(struct nv10_gr_chan *chan, u32 mthd, u32 data)
{
void (*func)(struct nv10_gr_chan *, u32, u32);
switch (mthd) {
case 0x1638 ... 0x1644:
func = nv17_gr_mthd_lma_window; break;
case 0x1658: func = nv17_gr_mthd_lma_enable; break;
default:
return false;
}
func(chan, mthd, data);
return true;
}
static bool
nv10_gr_mthd(struct nv10_gr_chan *chan, u8 class, u32 mthd, u32 data)
{
bool (*func)(struct nv10_gr_chan *, u32, u32);
switch (class) {
case 0x99: func = nv17_gr_mthd_celcius; break;
default:
return false;
}
return func(chan, mthd, data);
}
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static struct nv10_gr_chan *
nv10_gr_channel(struct nv10_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv10_gr_chan *chan = NULL;
if (nvkm_rd32(device, 0x400144) & 0x00010000) {
int chid = nvkm_rd32(device, 0x400148) >> 24;
if (chid < ARRAY_SIZE(gr->chan))
chan = gr->chan[chid];
}
return chan;
}
static void
nv10_gr_save_pipe(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = chan->gr;
struct pipe_state *pipe = &chan->pipe_state;
struct nvkm_device *device = gr->base.engine.subdev.device;
PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400);
PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200);
PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400);
PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800);
PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00);
PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000);
PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400);
PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800);
PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040);
PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000);
}
static void
nv10_gr_load_pipe(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = chan->gr;
struct pipe_state *pipe = &chan->pipe_state;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 xfmode0, xfmode1;
int i;
nv04_gr_idle(&gr->base);
/* XXX check haiku comments */
xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0);
xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1);
nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000);
nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
for (i = 0; i < 4; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
for (i = 0; i < 4; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
for (i = 0; i < 3; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
for (i = 0; i < 3; i++)
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008);
PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200);
nv04_gr_idle(&gr->base);
/* restore XFMODE */
nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0);
nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1);
PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400);
PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800);
PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00);
PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000);
PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400);
PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800);
PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400);
PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000);
PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040);
nv04_gr_idle(&gr->base);
}
static void
nv10_gr_create_pipe(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = chan->gr;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct pipe_state *pipe_state = &chan->pipe_state;
u32 *pipe_state_addr;
int i;
#define PIPE_INIT(addr) \
do { \
pipe_state_addr = pipe_state->pipe_##addr; \
} while (0)
#define PIPE_INIT_END(addr) \
do { \
u32 *__end_addr = pipe_state->pipe_##addr + \
ARRAY_SIZE(pipe_state->pipe_##addr); \
if (pipe_state_addr != __end_addr) \
nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \
addr, pipe_state_addr, __end_addr); \
} while (0)
#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
PIPE_INIT(0x0200);
for (i = 0; i < 48; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x0200);
PIPE_INIT(0x6400);
for (i = 0; i < 211; i++)
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x40000000);
NV_WRITE_PIPE_INIT(0x40000000);
NV_WRITE_PIPE_INIT(0x40000000);
NV_WRITE_PIPE_INIT(0x40000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f000000);
NV_WRITE_PIPE_INIT(0x3f000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x3f800000);
NV_WRITE_PIPE_INIT(0x3f800000);
PIPE_INIT_END(0x6400);
PIPE_INIT(0x6800);
for (i = 0; i < 162; i++)
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x3f800000);
for (i = 0; i < 25; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x6800);
PIPE_INIT(0x6c00);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0xbf800000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x6c00);
PIPE_INIT(0x7000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x00000000);
NV_WRITE_PIPE_INIT(0x7149f2ca);
for (i = 0; i < 35; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x7000);
PIPE_INIT(0x7400);
for (i = 0; i < 48; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x7400);
PIPE_INIT(0x7800);
for (i = 0; i < 48; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x7800);
PIPE_INIT(0x4400);
for (i = 0; i < 32; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x4400);
PIPE_INIT(0x0000);
for (i = 0; i < 16; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x0000);
PIPE_INIT(0x0040);
for (i = 0; i < 4; i++)
NV_WRITE_PIPE_INIT(0x00000000);
PIPE_INIT_END(0x0040);
#undef PIPE_INIT
#undef PIPE_INIT_END
#undef NV_WRITE_PIPE_INIT
}
static int
nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
if (nv10_gr_ctx_regs[i] == reg)
return i;
}
nvkm_error(subdev, "unknown offset nv10_ctx_regs %d\n", reg);
return -1;
}
static int
nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
if (nv17_gr_ctx_regs[i] == reg)
return i;
}
nvkm_error(subdev, "unknown offset nv17_ctx_regs %d\n", reg);
return -1;
}
static void
nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst)
{
struct nv10_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
u32 ctx_user, ctx_switch[5];
int i, subchan = -1;
/* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
* that cannot be restored via MMIO. Do it through the FIFO
* instead.
*/
/* Look for a celsius object */
for (i = 0; i < 8; i++) {
int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
if (class == 0x56 || class == 0x96 || class == 0x99) {
subchan = i;
break;
}
}
if (subchan < 0 || !inst)
return;
/* Save the current ctx object */
ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER);
for (i = 0; i < 5; i++)
ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i));
/* Save the FIFO state */
st2 = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2);
st2_dl = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DL);
st2_dh = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DH);
fifo_ptr = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR);
for (i = 0; i < ARRAY_SIZE(fifo); i++)
fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i);
/* Switch to the celsius subchannel */
for (i = 0; i < 5; i++)
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i),
nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(subchan, i)));
nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
/* Inject NV10TCL_DMA_VTXBUF */
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2,
0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Restore the FIFO state */
for (i = 0; i < ARRAY_SIZE(fifo); i++)
nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, st2);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
/* Restore the current ctx object */
for (i = 0; i < 5; i++)
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
nvkm_wr32(device, NV10_PGRAPH_CTX_USER, ctx_user);
}
static int
nv10_gr_load_context(struct nv10_gr_chan *chan, int chid)
{
struct nv10_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 inst;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]);
if (device->card_type >= NV_11 && device->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]);
}
nv10_gr_load_pipe(chan);
inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff;
nv10_gr_load_dma_vtxbuf(chan, chid, inst);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000);
return 0;
}
static int
nv10_gr_unload_context(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++)
chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]);
if (device->card_type >= NV_11 && device->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++)
chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]);
}
nv10_gr_save_pipe(chan);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
return 0;
}
static void
nv10_gr_context_switch(struct nv10_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nv10_gr_chan *prev = NULL;
struct nv10_gr_chan *next = NULL;
int chid;
nv04_gr_idle(&gr->base);
/* If previous context is valid, we need to save it */
prev = nv10_gr_channel(gr);
if (prev)
nv10_gr_unload_context(prev);
/* load context for next channel */
chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
next = gr->chan[chid];
if (next)
nv10_gr_load_context(next, chid);
}
static int
nv10_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv10_gr_chan *chan = nv10_gr_chan(object);
struct nv10_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
if (nv10_gr_channel(gr) == chan)
nv10_gr_unload_context(chan);
nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
static void *
nv10_gr_chan_dtor(struct nvkm_object *object)
{
struct nv10_gr_chan *chan = nv10_gr_chan(object);
struct nv10_gr *gr = chan->gr;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
gr->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&gr->lock, flags);
return chan;
}
static const struct nvkm_object_func
nv10_gr_chan = {
.dtor = nv10_gr_chan_dtor,
.fini = nv10_gr_chan_fini,
};
#define NV_WRITE_CTX(reg, val) do { \
int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \
if (offset > 0) \
chan->nv10[offset] = val; \
} while (0)
#define NV17_WRITE_CTX(reg, val) do { \
int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \
if (offset > 0) \
chan->nv17[offset] = val; \
} while (0)
int
nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv10_gr *gr = nv10_gr(base);
struct nv10_gr_chan *chan;
struct nvkm_device *device = gr->base.engine.subdev.device;
unsigned long flags;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv10_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
NV_WRITE_CTX(0x00400e88, 0x08000000);
NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
NV_WRITE_CTX(0x00400e10, 0x00001000);
NV_WRITE_CTX(0x00400e14, 0x00001000);
NV_WRITE_CTX(0x00400e30, 0x00080008);
NV_WRITE_CTX(0x00400e34, 0x00080008);
if (device->card_type >= NV_11 && device->chipset >= 0x17) {
/* is it really needed ??? */
NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
nvkm_rd32(device, NV10_PGRAPH_DEBUG_4));
NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0));
NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
NV17_WRITE_CTX(0x00400ec0, 0x00000080);
NV17_WRITE_CTX(0x00400ed0, 0x00000080);
}
NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24);
nv10_gr_create_pipe(chan);
spin_lock_irqsave(&gr->lock, flags);
gr->chan[chan->chid] = chan;
spin_unlock_irqrestore(&gr->lock, flags);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
void
nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
struct nv10_gr *gr = nv10_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fifo *fifo = device->fifo;
unsigned long flags;
nvkm_fifo_pause(fifo, &flags);
nv04_gr_idle(&gr->base);
nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);
nvkm_fifo_start(fifo, &flags);
}
const struct nvkm_bitfield nv10_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{ NV_PGRAPH_INTR_ERROR, "ERROR" },
{}
};
const struct nvkm_bitfield nv10_gr_nstatus[] = {
{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
{ NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
{}
};
void
nv10_gr_intr(struct nvkm_gr *base)
{
struct nv10_gr *gr = nv10_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x01f00000) >> 20;
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
struct nv10_gr_chan *chan;
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
chan = gr->chan[chid];
if (stat & NV_PGRAPH_INTR_ERROR) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
if (!nv10_gr_mthd(chan, class, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
}
}
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
nv10_gr_context_switch(gr);
}
nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
chan ? chan->object.client->name : "unknown",
subc, class, mthd, data);
}
spin_unlock_irqrestore(&gr->lock, flags);
}
int
nv10_gr_init(struct nvkm_gr *base)
{
struct nv10_gr *gr = nv10_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
/* nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */
nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
if (device->card_type >= NV_11 && device->chipset >= 0x17) {
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000);
nvkm_wr32(device, 0x400a10, 0x03ff3fb6);
nvkm_wr32(device, 0x400838, 0x002f8684);
nvkm_wr32(device, 0x40083c, 0x00115f3f);
nvkm_wr32(device, 0x4006b0, 0x40000020);
} else {
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
}
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF);
nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000);
return 0;
}
int
nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv10_gr *gr;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
nv10_gr = {
.init = nv10_gr_init,
.intr = nv10_gr_intr,
.tile = nv10_gr_tile,
.chan_new = nv10_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x005f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
{ -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
{ -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
{ -1, -1, 0x0056, &nv04_gr_object }, /* celcius */
{}
}
};
int
nv10_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv10_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf108_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000b2, 40, 0x01, 0x00000000 },
{ 0x000210, 8, 0x01, 0x00000040 },
{ 0x000218, 8, 0x01, 0x0000c080 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00001fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x003fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x0005e0, 5, 0x01, 0x00000022 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x00000c48 },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00300008 },
{ 0x000841, 1, 0x01, 0x04000080 },
{ 0x000842, 1, 0x01, 0x00300008 },
{ 0x000843, 1, 0x01, 0x04000080 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x000944, 1, 0x01, 0x00000022 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_icmd[] = {
{ gf108_grctx_init_icmd_0 },
{}
};
const struct gf100_gr_init
gf108_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
{ 0x00080c, 8, 0x40, 0x00000300 },
{ 0x000810, 1, 0x04, 0x000000cf },
{ 0x000850, 7, 0x40, 0x00000000 },
{ 0x000814, 8, 0x40, 0x00000040 },
{ 0x000818, 8, 0x40, 0x00000001 },
{ 0x00081c, 8, 0x40, 0x00000000 },
{ 0x000820, 8, 0x40, 0x00000000 },
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x002710, 8, 0x20, 0x00014000 },
{ 0x002714, 8, 0x20, 0x00000040 },
{ 0x001c00, 16, 0x10, 0x00000000 },
{ 0x001c04, 16, 0x10, 0x00000000 },
{ 0x001c08, 16, 0x10, 0x00000000 },
{ 0x001c0c, 16, 0x10, 0x00000000 },
{ 0x001d00, 16, 0x10, 0x00000000 },
{ 0x001d04, 16, 0x10, 0x00000000 },
{ 0x001d08, 16, 0x10, 0x00000000 },
{ 0x001d0c, 16, 0x10, 0x00000000 },
{ 0x001f00, 16, 0x08, 0x00000000 },
{ 0x001f04, 16, 0x08, 0x00000000 },
{ 0x001f80, 16, 0x08, 0x00000000 },
{ 0x001f84, 16, 0x08, 0x00000000 },
{ 0x002200, 5, 0x10, 0x00000022 },
{ 0x002000, 1, 0x04, 0x00000000 },
{ 0x002040, 1, 0x04, 0x00000011 },
{ 0x002080, 1, 0x04, 0x00000020 },
{ 0x0020c0, 1, 0x04, 0x00000030 },
{ 0x002100, 1, 0x04, 0x00000040 },
{ 0x002140, 1, 0x04, 0x00000051 },
{ 0x00200c, 6, 0x40, 0x00000001 },
{ 0x002010, 1, 0x04, 0x00000000 },
{ 0x002050, 1, 0x04, 0x00000000 },
{ 0x002090, 1, 0x04, 0x00000001 },
{ 0x0020d0, 1, 0x04, 0x00000002 },
{ 0x002110, 1, 0x04, 0x00000003 },
{ 0x002150, 1, 0x04, 0x00000004 },
{ 0x000380, 4, 0x20, 0x00000000 },
{ 0x000384, 4, 0x20, 0x00000000 },
{ 0x000388, 4, 0x20, 0x00000000 },
{ 0x00038c, 4, 0x20, 0x00000000 },
{ 0x000700, 4, 0x10, 0x00000000 },
{ 0x000704, 4, 0x10, 0x00000000 },
{ 0x000708, 4, 0x10, 0x00000000 },
{ 0x002800, 128, 0x04, 0x00000000 },
{ 0x000a00, 16, 0x20, 0x00000000 },
{ 0x000a04, 16, 0x20, 0x00000000 },
{ 0x000a08, 16, 0x20, 0x00000000 },
{ 0x000a0c, 16, 0x20, 0x00000000 },
{ 0x000a10, 16, 0x20, 0x00000000 },
{ 0x000a14, 16, 0x20, 0x00000000 },
{ 0x000c00, 16, 0x10, 0x00000000 },
{ 0x000c04, 16, 0x10, 0x00000000 },
{ 0x000c08, 16, 0x10, 0x00000000 },
{ 0x000c0c, 16, 0x10, 0x3f800000 },
{ 0x000d00, 8, 0x08, 0xffff0000 },
{ 0x000d04, 8, 0x08, 0xffff0000 },
{ 0x000e00, 16, 0x10, 0x00000000 },
{ 0x000e04, 16, 0x10, 0xffff0000 },
{ 0x000e08, 16, 0x10, 0xffff0000 },
{ 0x000d40, 4, 0x08, 0x00000000 },
{ 0x000d44, 4, 0x08, 0x00000000 },
{ 0x001e00, 8, 0x20, 0x00000001 },
{ 0x001e04, 8, 0x20, 0x00000001 },
{ 0x001e08, 8, 0x20, 0x00000002 },
{ 0x001e0c, 8, 0x20, 0x00000001 },
{ 0x001e10, 8, 0x20, 0x00000001 },
{ 0x001e14, 8, 0x20, 0x00000002 },
{ 0x001e18, 8, 0x20, 0x00000001 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x001514, 1, 0x04, 0x00000000 },
{ 0x000d68, 1, 0x04, 0x0000ffff },
{ 0x00121c, 1, 0x04, 0x0fac6881 },
{ 0x000fac, 1, 0x04, 0x00000001 },
{ 0x001538, 1, 0x04, 0x00000001 },
{ 0x000fe0, 2, 0x04, 0x00000000 },
{ 0x000fe8, 1, 0x04, 0x00000014 },
{ 0x000fec, 1, 0x04, 0x00000040 },
{ 0x000ff0, 1, 0x04, 0x00000000 },
{ 0x00179c, 1, 0x04, 0x00000000 },
{ 0x001228, 1, 0x04, 0x00000400 },
{ 0x00122c, 1, 0x04, 0x00000300 },
{ 0x001230, 1, 0x04, 0x00010001 },
{ 0x0007f8, 1, 0x04, 0x00000000 },
{ 0x0015b4, 1, 0x04, 0x00000001 },
{ 0x0015cc, 1, 0x04, 0x00000000 },
{ 0x001534, 1, 0x04, 0x00000000 },
{ 0x000fb0, 1, 0x04, 0x00000000 },
{ 0x0015d0, 1, 0x04, 0x00000000 },
{ 0x00153c, 1, 0x04, 0x00000000 },
{ 0x0016b4, 1, 0x04, 0x00000003 },
{ 0x000fbc, 4, 0x04, 0x0000ffff },
{ 0x000df8, 2, 0x04, 0x00000000 },
{ 0x001948, 1, 0x04, 0x00000000 },
{ 0x001970, 1, 0x04, 0x00000001 },
{ 0x00161c, 1, 0x04, 0x000009f0 },
{ 0x000dcc, 1, 0x04, 0x00000010 },
{ 0x00163c, 1, 0x04, 0x00000000 },
{ 0x0015e4, 1, 0x04, 0x00000000 },
{ 0x001160, 32, 0x04, 0x25e00040 },
{ 0x001880, 32, 0x04, 0x00000000 },
{ 0x000f84, 2, 0x04, 0x00000000 },
{ 0x0017c8, 2, 0x04, 0x00000000 },
{ 0x0017d0, 1, 0x04, 0x000000ff },
{ 0x0017d4, 1, 0x04, 0xffffffff },
{ 0x0017d8, 1, 0x04, 0x00000002 },
{ 0x0017dc, 1, 0x04, 0x00000000 },
{ 0x0015f4, 2, 0x04, 0x00000000 },
{ 0x001434, 2, 0x04, 0x00000000 },
{ 0x000d74, 1, 0x04, 0x00000000 },
{ 0x000dec, 1, 0x04, 0x00000001 },
{ 0x0013a4, 1, 0x04, 0x00000000 },
{ 0x001318, 1, 0x04, 0x00000001 },
{ 0x001644, 1, 0x04, 0x00000000 },
{ 0x000748, 1, 0x04, 0x00000000 },
{ 0x000de8, 1, 0x04, 0x00000000 },
{ 0x001648, 1, 0x04, 0x00000000 },
{ 0x0012a4, 1, 0x04, 0x00000000 },
{ 0x001120, 4, 0x04, 0x00000000 },
{ 0x001118, 1, 0x04, 0x00000000 },
{ 0x00164c, 1, 0x04, 0x00000000 },
{ 0x001658, 1, 0x04, 0x00000000 },
{ 0x001910, 1, 0x04, 0x00000290 },
{ 0x001518, 1, 0x04, 0x00000000 },
{ 0x00165c, 1, 0x04, 0x00000001 },
{ 0x001520, 1, 0x04, 0x00000000 },
{ 0x001604, 1, 0x04, 0x00000000 },
{ 0x001570, 1, 0x04, 0x00000000 },
{ 0x0013b0, 2, 0x04, 0x3f800000 },
{ 0x00020c, 1, 0x04, 0x00000000 },
{ 0x001670, 1, 0x04, 0x30201000 },
{ 0x001674, 1, 0x04, 0x70605040 },
{ 0x001678, 1, 0x04, 0xb8a89888 },
{ 0x00167c, 1, 0x04, 0xf8e8d8c8 },
{ 0x00166c, 1, 0x04, 0x00000000 },
{ 0x001680, 1, 0x04, 0x00ffff00 },
{ 0x0012d0, 1, 0x04, 0x00000003 },
{ 0x0012d4, 1, 0x04, 0x00000002 },
{ 0x001684, 2, 0x04, 0x00000000 },
{ 0x000dac, 2, 0x04, 0x00001b02 },
{ 0x000db4, 1, 0x04, 0x00000000 },
{ 0x00168c, 1, 0x04, 0x00000000 },
{ 0x0015bc, 1, 0x04, 0x00000000 },
{ 0x00156c, 1, 0x04, 0x00000000 },
{ 0x00187c, 1, 0x04, 0x00000000 },
{ 0x001110, 1, 0x04, 0x00000001 },
{ 0x000dc0, 3, 0x04, 0x00000000 },
{ 0x001234, 1, 0x04, 0x00000000 },
{ 0x001690, 1, 0x04, 0x00000000 },
{ 0x0012ac, 1, 0x04, 0x00000001 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x001000, 1, 0x04, 0x00000010 },
{ 0x0010fc, 1, 0x04, 0x00000000 },
{ 0x001290, 1, 0x04, 0x00000000 },
{ 0x000218, 1, 0x04, 0x00000010 },
{ 0x0012d8, 1, 0x04, 0x00000000 },
{ 0x0012dc, 1, 0x04, 0x00000010 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x00155c, 2, 0x04, 0x00000000 },
{ 0x001564, 1, 0x04, 0x00001fff },
{ 0x001574, 2, 0x04, 0x00000000 },
{ 0x00157c, 1, 0x04, 0x003fffff },
{ 0x001354, 1, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{ 0x001610, 1, 0x04, 0x00000012 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x00162c, 1, 0x04, 0x00000003 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000324, 6, 0x04, 0x3f800000 },
{ 0x000750, 1, 0x04, 0x00000000 },
{ 0x000760, 1, 0x04, 0x39291909 },
{ 0x000764, 1, 0x04, 0x79695949 },
{ 0x000768, 1, 0x04, 0xb9a99989 },
{ 0x00076c, 1, 0x04, 0xf9e9d9c9 },
{ 0x000770, 1, 0x04, 0x30201000 },
{ 0x000774, 1, 0x04, 0x70605040 },
{ 0x000778, 1, 0x04, 0x00009080 },
{ 0x000780, 1, 0x04, 0x39291909 },
{ 0x000784, 1, 0x04, 0x79695949 },
{ 0x000788, 1, 0x04, 0xb9a99989 },
{ 0x00078c, 1, 0x04, 0xf9e9d9c9 },
{ 0x0007d0, 1, 0x04, 0x30201000 },
{ 0x0007d4, 1, 0x04, 0x70605040 },
{ 0x0007d8, 1, 0x04, 0x00009080 },
{ 0x00037c, 1, 0x04, 0x00000001 },
{ 0x000740, 2, 0x04, 0x00000000 },
{ 0x002600, 1, 0x04, 0x00000000 },
{ 0x001918, 1, 0x04, 0x00000000 },
{ 0x00191c, 1, 0x04, 0x00000900 },
{ 0x001920, 1, 0x04, 0x00000405 },
{ 0x001308, 1, 0x04, 0x00000001 },
{ 0x001924, 1, 0x04, 0x00000000 },
{ 0x0013ac, 1, 0x04, 0x00000000 },
{ 0x00192c, 1, 0x04, 0x00000001 },
{ 0x00193c, 1, 0x04, 0x00002c1c },
{ 0x000d7c, 1, 0x04, 0x00000000 },
{ 0x000f8c, 1, 0x04, 0x00000000 },
{ 0x0002c0, 1, 0x04, 0x00000001 },
{ 0x001510, 1, 0x04, 0x00000000 },
{ 0x001940, 1, 0x04, 0x00000000 },
{ 0x000ff4, 2, 0x04, 0x00000000 },
{ 0x00194c, 2, 0x04, 0x00000000 },
{ 0x001968, 1, 0x04, 0x00000000 },
{ 0x001590, 1, 0x04, 0x0000003f },
{ 0x0007e8, 4, 0x04, 0x00000000 },
{ 0x00196c, 1, 0x04, 0x00000011 },
{ 0x00197c, 1, 0x04, 0x00000000 },
{ 0x000fcc, 2, 0x04, 0x00000000 },
{ 0x0002d8, 1, 0x04, 0x00000040 },
{ 0x001980, 1, 0x04, 0x00000080 },
{ 0x001504, 1, 0x04, 0x00000080 },
{ 0x001984, 1, 0x04, 0x00000000 },
{ 0x000300, 1, 0x04, 0x00000001 },
{ 0x0013a8, 1, 0x04, 0x00000000 },
{ 0x0012ec, 1, 0x04, 0x00000000 },
{ 0x001310, 1, 0x04, 0x00000000 },
{ 0x001314, 1, 0x04, 0x00000001 },
{ 0x001380, 1, 0x04, 0x00000000 },
{ 0x001384, 4, 0x04, 0x00000001 },
{ 0x001394, 1, 0x04, 0x00000000 },
{ 0x00139c, 1, 0x04, 0x00000000 },
{ 0x001398, 1, 0x04, 0x00000000 },
{ 0x001594, 1, 0x04, 0x00000000 },
{ 0x001598, 4, 0x04, 0x00000001 },
{ 0x000f54, 3, 0x04, 0x00000000 },
{ 0x0019bc, 1, 0x04, 0x00000000 },
{ 0x000f9c, 2, 0x04, 0x00000000 },
{ 0x0012cc, 1, 0x04, 0x00000000 },
{ 0x0012e8, 1, 0x04, 0x00000000 },
{ 0x00130c, 1, 0x04, 0x00000001 },
{ 0x001360, 8, 0x04, 0x00000000 },
{ 0x00133c, 2, 0x04, 0x00000001 },
{ 0x001344, 1, 0x04, 0x00000002 },
{ 0x001348, 2, 0x04, 0x00000001 },
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
{ 0x0019c8, 1, 0x04, 0x00001500 },
{ 0x00135c, 1, 0x04, 0x00000000 },
{ 0x000f90, 1, 0x04, 0x00000000 },
{ 0x0019e0, 8, 0x04, 0x00000001 },
{ 0x0019cc, 1, 0x04, 0x00000001 },
{ 0x0015b8, 1, 0x04, 0x00000000 },
{ 0x001a00, 1, 0x04, 0x00001111 },
{ 0x001a04, 7, 0x04, 0x00000000 },
{ 0x000d6c, 2, 0x04, 0xffff0000 },
{ 0x0010f8, 1, 0x04, 0x00001010 },
{ 0x000d80, 5, 0x04, 0x00000000 },
{ 0x000da0, 1, 0x04, 0x00000000 },
{ 0x001508, 1, 0x04, 0x80000000 },
{ 0x00150c, 1, 0x04, 0x40000000 },
{ 0x001668, 1, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000008 },
{ 0x000d9c, 1, 0x04, 0x00000001 },
{ 0x0007dc, 1, 0x04, 0x00000000 },
{ 0x00074c, 1, 0x04, 0x00000055 },
{ 0x001420, 1, 0x04, 0x00000003 },
{ 0x0017bc, 2, 0x04, 0x00000000 },
{ 0x0017c4, 1, 0x04, 0x00000001 },
{ 0x001008, 1, 0x04, 0x00000008 },
{ 0x00100c, 1, 0x04, 0x00000040 },
{ 0x001010, 1, 0x04, 0x0000012c },
{ 0x000d60, 1, 0x04, 0x00000040 },
{ 0x00075c, 1, 0x04, 0x00000003 },
{ 0x001018, 1, 0x04, 0x00000020 },
{ 0x00101c, 1, 0x04, 0x00000001 },
{ 0x001020, 1, 0x04, 0x00000020 },
{ 0x001024, 1, 0x04, 0x00000001 },
{ 0x001444, 3, 0x04, 0x00000000 },
{ 0x000360, 1, 0x04, 0x20164010 },
{ 0x000364, 1, 0x04, 0x00000020 },
{ 0x000368, 1, 0x04, 0x00000000 },
{ 0x000de4, 1, 0x04, 0x00000000 },
{ 0x000204, 1, 0x04, 0x00000006 },
{ 0x000208, 1, 0x04, 0x00000000 },
{ 0x0002cc, 1, 0x04, 0x003fffff },
{ 0x0002d0, 1, 0x04, 0x00000c48 },
{ 0x001220, 1, 0x04, 0x00000005 },
{ 0x000fdc, 1, 0x04, 0x00000000 },
{ 0x000f98, 1, 0x04, 0x00300008 },
{ 0x001284, 1, 0x04, 0x04000080 },
{ 0x001450, 1, 0x04, 0x00300008 },
{ 0x001454, 1, 0x04, 0x04000080 },
{ 0x000214, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf108_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf108_grctx_init_9197_0, 0x9197 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct gf100_gr_init
gf108_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 2, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf108_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 2, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x80140078 },
{ 0x4064c4, 1, 0x04, 0x0086ffff },
{}
};
static const struct gf100_gr_init
gf108_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
{ 0x408900, 1, 0x04, 0x3080b801 },
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c80929 },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf100_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf108_grctx_init_ds_0 },
{ gf108_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf108_grctx_init_be_0 },
{}
};
static const struct gf100_gr_init
gf108_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x00100018 },
{}
};
const struct gf100_gr_init
gf108_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c6c, 1, 0x04, 0x00000001 },
{ 0x418c80, 1, 0x04, 0x20200004 },
{ 0x418c8c, 1, 0x04, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf100_grctx_init_prop_0 },
{ gf100_grctx_init_gpc_unk_1 },
{ gf108_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_gpc_1[] = {
{ gf100_grctx_init_crstr_0 },
{ gf108_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct gf100_gr_init
gf108_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf108_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
{ 0x419b0c, 1, 0x04, 0x0e629062 },
{ 0x419b10, 1, 0x04, 0x0a418820 },
{ 0x419b14, 1, 0x04, 0x000000e6 },
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00400001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf108_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{}
};
static const struct gf100_gr_pack
gf108_grctx_pack_tpc[] = {
{ gf108_grctx_init_pe_0 },
{ gf104_grctx_init_tex_0 },
{ gf108_grctx_init_wwdx_0 },
{ gf100_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf108_grctx_init_tpccs_0 },
{ gf104_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gf108_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 beta = grctx->attrib_nr;
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
int gpc, tpc;
gf100_grctx_patch_wr32(chan, 0x405830, (beta << 16) | alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 a = alpha;
const u32 b = beta;
const u32 t = timeslice_mode;
const u32 o = TPC_UNIT(gpc, tpc, 0x500);
gf100_grctx_patch_wr32(chan, o + 0x20, (t << 28) | (b << 16) | bo);
bo += grctx->attrib_nr_max;
gf100_grctx_patch_wr32(chan, o + 0x44, (a << 16) | ao);
ao += grctx->alpha_nr_max;
}
}
}
void
gf108_grctx_generate_unkn(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001);
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x419814, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
const struct gf100_grctx_func
gf108_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gf108_grctx_generate_unkn,
.hub = gf108_grctx_pack_hub,
.gpc_0 = gf108_grctx_pack_gpc_0,
.gpc_1 = gf108_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf108_grctx_pack_tpc,
.icmd = gf108_grctx_pack_icmd,
.mthd = gf108_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf100_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct nvkm_object_func
nv35_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x577c, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x040c, 0x00000101);
nvkm_wo32(chan->inst, 0x0420, 0x00000111);
nvkm_wo32(chan->inst, 0x0424, 0x00000060);
nvkm_wo32(chan->inst, 0x0440, 0x00000080);
nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
nvkm_wo32(chan->inst, 0x0448, 0x00000001);
nvkm_wo32(chan->inst, 0x045c, 0x44400000);
nvkm_wo32(chan->inst, 0x0488, 0xffff0000);
for (i = 0x04dc; i < 0x04e4; i += 4)
nvkm_wo32(chan->inst, i, 0x0fff0000);
nvkm_wo32(chan->inst, 0x04e8, 0x00011100);
for (i = 0x0504; i < 0x0544; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x0588, 0x00000080);
nvkm_wo32(chan->inst, 0x058c, 0x30201000);
nvkm_wo32(chan->inst, 0x0590, 0x70605040);
nvkm_wo32(chan->inst, 0x0594, 0xb8a89888);
nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8);
nvkm_wo32(chan->inst, 0x05ac, 0xb0000000);
for (i = 0x0604; i < 0x0644; i += 4)
nvkm_wo32(chan->inst, i, 0x00010588);
for (i = 0x0644; i < 0x0684; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x06c4; i < 0x0704; i += 4)
nvkm_wo32(chan->inst, i, 0x0008aae4);
for (i = 0x0704; i < 0x0744; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x0744; i < 0x0784; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
nvkm_wo32(chan->inst, 0x0860, 0x00040000);
nvkm_wo32(chan->inst, 0x0864, 0x00010000);
for (i = 0x0868; i < 0x0878; i += 4)
nvkm_wo32(chan->inst, i, 0x00040004);
for (i = 0x1f1c; i <= 0x308c ; i += 16) {
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
}
for (i = 0x30bc; i < 0x30cc; i += 4)
nvkm_wo32(chan->inst, i, 0x0000ffff);
nvkm_wo32(chan->inst, 0x3450, 0x3f800000);
nvkm_wo32(chan->inst, 0x380c, 0x3f800000);
nvkm_wo32(chan->inst, 0x3820, 0x3f800000);
nvkm_wo32(chan->inst, 0x384c, 0x40000000);
nvkm_wo32(chan->inst, 0x3850, 0x3f800000);
nvkm_wo32(chan->inst, 0x3854, 0x3f000000);
nvkm_wo32(chan->inst, 0x385c, 0x40000000);
nvkm_wo32(chan->inst, 0x3860, 0x3f800000);
nvkm_wo32(chan->inst, 0x3868, 0xbf800000);
nvkm_wo32(chan->inst, 0x3870, 0xbf800000);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct nvkm_gr_func
nv35_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv30_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv35_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
{ -1, -1, 0x0497, &nv04_gr_object }, /* rankine */
{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
{}
}
};
int
nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv35_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
void
tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003);
}
void
tu102_gr_init_fs(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int sm;
gp100_grctx_generate_smid_config(gr);
gk104_grctx_generate_gpc_tpc_nr(gr);
for (sm = 0; sm < gr->sm_nr; sm++) {
int tpc = gv100_gr_nonpes_aware_tpc(gr, gr->sm[sm].gpc, gr->sm[sm].tpc);
nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm);
}
gm200_grctx_generate_dist_skip_table(gr);
gf100_gr_init_num_tpc_per_gpc(gr, true, true);
}
void
tu102_gr_init_zcull(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
const u8 tile_nr = gr->func->gpc_nr * gr->func->tpc_nr;
u8 bank[GPC_MAX] = {}, gpc, i, j;
u32 data;
for (i = 0; i < tile_nr; i += 8) {
for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
data |= bank[gr->tile[i + j]] << (j * 4);
bank[gr->tile[i + j]]++;
}
nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
}
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
}
static void
tu102_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
nvkm_wr32(device, 0x418890, 0x00000000);
nvkm_wr32(device, 0x418894, 0x00000000);
nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
}
static const struct gf100_gr_func
tu102_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gv100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_419bd8 = gv100_gr_init_419bd8,
.init_gpc_mmu = tu102_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = tu102_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fs = tu102_gr_init_fs,
.init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_504430 = gv100_gr_init_504430,
.init_shader_exceptions = gv100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_4188a4 = gv100_gr_init_4188a4,
.trap_mp = gv100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 6,
.ppc_nr = 3,
.grctx = &tu102_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, TURING_A, &gf100_fermi },
{ -1, -1, TURING_COMPUTE_A },
{}
}
};
MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu102/gr/sw_veid_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu104/gr/sw_veid_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu106/gr/sw_veid_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu117/gr/sw_veid_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/tu116/gr/sw_veid_bundle_init.bin");
int
tu102_gr_av_to_init_veid(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
{
return gk20a_gr_av_to_init_(blob, 64, 0x00100000, ppack);
}
static const struct gf100_gr_fwif
tu102_gr_fwif[] = {
{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000007f },
{ 0x419e50, 2, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000001 },
{ 0x419e5c, 3, 0x04, 0x00000000 },
{ 0x419e68, 1, 0x04, 0x00000002 },
{ 0x419e6c, 12, 0x04, 0x00000000 },
{ 0x419eac, 1, 0x04, 0x00001f8f },
{ 0x419eb0, 1, 0x04, 0x0db00d2f },
{ 0x419eb8, 1, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0001304f },
{ 0x419f30, 4, 0x04, 0x00000000 },
{ 0x419f40, 1, 0x04, 0x00000018 },
{ 0x419f44, 3, 0x04, 0x00000000 },
{ 0x419f58, 1, 0x04, 0x00000000 },
{ 0x419f70, 1, 0x04, 0x00006300 },
{ 0x419f78, 1, 0x04, 0x000000eb },
{ 0x419f7c, 1, 0x04, 0x00000404 },
{}
};
static const struct gf100_gr_pack
gk110b_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk110_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk110b_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gk110b_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk110_grctx_pack_hub,
.gpc_0 = gk110_grctx_pack_gpc_0,
.gpc_1 = gk110_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk110b_grctx_pack_tpc,
.ppc = gk110_grctx_pack_ppc,
.icmd = gk110_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
.alpha_nr = 0x648,
.patch_ltc = gk104_grctx_generate_patch_ltc,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.r418800 = gk104_grctx_generate_r418800,
.r419eb0 = gk110_grctx_generate_r419eb0,
.r419f78 = gk110_grctx_generate_r419f78,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <nvif/class.h>
u64
nv50_gr_units(struct nvkm_gr *gr)
{
return nvkm_rd32(gr->engine.subdev.device, 0x1540);
}
/*******************************************************************************
* Graphics object classes
******************************************************************************/
static int
nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
align, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm_done(*pgpuobj);
}
return ret;
}
const struct nvkm_object_func
nv50_gr_object = {
.bind = nv50_gr_object_bind,
};
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static int
nv50_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
struct nv50_gr *gr = nv50_gr_chan(object)->gr;
int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
align, true, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
nvkm_done(*pgpuobj);
}
return ret;
}
static const struct nvkm_object_func
nv50_gr_chan = {
.bind = nv50_gr_chan_bind,
};
int
nv50_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv50_gr *gr = nv50_gr(base);
struct nv50_gr_chan *chan;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object);
chan->gr = gr;
*pobject = &chan->object;
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct nvkm_bitfield nv50_mp_exec_errors[] = {
{ 0x01, "STACK_UNDERFLOW" },
{ 0x02, "STACK_MISMATCH" },
{ 0x04, "QUADON_ACTIVE" },
{ 0x08, "TIMEOUT" },
{ 0x10, "INVALID_OPCODE" },
{ 0x20, "PM_OVERFLOW" },
{ 0x40, "BREAKPOINT" },
{}
};
static const struct nvkm_bitfield nv50_mpc_traps[] = {
{ 0x0000001, "LOCAL_LIMIT_READ" },
{ 0x0000010, "LOCAL_LIMIT_WRITE" },
{ 0x0000040, "STACK_LIMIT" },
{ 0x0000100, "GLOBAL_LIMIT_READ" },
{ 0x0001000, "GLOBAL_LIMIT_WRITE" },
{ 0x0010000, "MP0" },
{ 0x0020000, "MP1" },
{ 0x0040000, "GLOBAL_LIMIT_RED" },
{ 0x0400000, "GLOBAL_LIMIT_ATOM" },
{ 0x4000000, "MP2" },
{}
};
static const struct nvkm_bitfield nv50_tex_traps[] = {
{ 0x00000001, "" }, /* any bit set? */
{ 0x00000002, "FAULT" },
{ 0x00000004, "STORAGE_TYPE_MISMATCH" },
{ 0x00000008, "LINEAR_MISMATCH" },
{ 0x00000020, "WRONG_MEMTYPE" },
{}
};
static const struct nvkm_bitfield nv50_gr_trap_m2mf[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "IN" },
{ 0x00000004, "OUT" },
{}
};
static const struct nvkm_bitfield nv50_gr_trap_vfetch[] = {
{ 0x00000001, "FAULT" },
{}
};
static const struct nvkm_bitfield nv50_gr_trap_strmout[] = {
{ 0x00000001, "FAULT" },
{}
};
static const struct nvkm_bitfield nv50_gr_trap_ccache[] = {
{ 0x00000001, "FAULT" },
{}
};
/* There must be a *lot* of these. Will take some time to gather them up. */
const struct nvkm_enum nv50_data_error_names[] = {
{ 0x00000003, "INVALID_OPERATION", NULL },
{ 0x00000004, "INVALID_VALUE", NULL },
{ 0x00000005, "INVALID_ENUM", NULL },
{ 0x00000008, "INVALID_OBJECT", NULL },
{ 0x00000009, "READ_ONLY_OBJECT", NULL },
{ 0x0000000a, "SUPERVISOR_OBJECT", NULL },
{ 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
{ 0x0000000c, "INVALID_BITFIELD", NULL },
{ 0x0000000d, "BEGIN_END_ACTIVE", NULL },
{ 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
{ 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
{ 0x00000010, "RT_DOUBLE_BIND", NULL },
{ 0x00000011, "RT_TYPES_MISMATCH", NULL },
{ 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
{ 0x00000015, "FP_TOO_FEW_REGS", NULL },
{ 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
{ 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
{ 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
{ 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
{ 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
{ 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
{ 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
{ 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
{ 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
{ 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
{ 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
{ 0x00000024, "VP_ZERO_INPUTS", NULL },
{ 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
{ 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
{ 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
{ 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
{ 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
{ 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
{ 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
{ 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
{ 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
{ 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
{ 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
{ 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
{ 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
{ 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
{ 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
{}
};
static const struct nvkm_bitfield nv50_gr_intr_name[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "COMPUTE_QUERY" },
{ 0x00000010, "ILLEGAL_MTHD" },
{ 0x00000020, "ILLEGAL_CLASS" },
{ 0x00000040, "DOUBLE_NOTIFY" },
{ 0x00001000, "CONTEXT_SWITCH" },
{ 0x00010000, "BUFFER_NOTIFY" },
{ 0x00100000, "DATA_ERROR" },
{ 0x00200000, "TRAP" },
{ 0x01000000, "SINGLE_STEP" },
{}
};
static const struct nvkm_bitfield nv50_gr_trap_prop[] = {
{ 0x00000004, "SURF_WIDTH_OVERRUN" },
{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
{ 0x00000010, "DST2D_FAULT" },
{ 0x00000020, "ZETA_FAULT" },
{ 0x00000040, "RT_FAULT" },
{ 0x00000080, "CUDA_FAULT" },
{ 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
{ 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
{ 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
{ 0x00000800, "DST2D_LINEAR_MISMATCH" },
{ 0x00001000, "RT_LINEAR_MISMATCH" },
{}
};
static void
nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04);
u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08);
u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c);
u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10);
u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14);
u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18);
u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c);
char msg[128];
/* CUDA memory: l[], g[] or stack. */
if (ustatus & 0x00000080) {
if (e18 & 0x80000000) {
/* g[] read fault? */
nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 24) & 0x1f));
e18 &= ~0x1f000000;
} else if (e18 & 0xc) {
/* g[] write fault? */
nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 7) & 0x1f));
e18 &= ~0x00000f80;
} else {
nvkm_error(subdev, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
tp, e14, e10);
}
ustatus &= ~0x00000080;
}
if (ustatus) {
nvkm_snprintbf(msg, sizeof(msg), nv50_gr_trap_prop, ustatus);
nvkm_error(subdev, "TRAP_PROP - TP %d - %08x [%s] - "
"Address %02x%08x\n",
tp, ustatus, msg, e14, e10);
}
nvkm_error(subdev, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
tp, e0c, e18, e1c, e20, e24);
}
static void
nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 units = nvkm_rd32(device, 0x1540);
u32 addr, mp10, status, pc, oplow, ophigh;
char msg[128];
int i;
int mps = 0;
for (i = 0; i < 4; i++) {
if (!(units & 1 << (i+24)))
continue;
if (device->chipset < 0xa0)
addr = 0x408200 + (tpid << 12) + (i << 7);
else
addr = 0x408100 + (tpid << 11) + (i << 7);
mp10 = nvkm_rd32(device, addr + 0x10);
status = nvkm_rd32(device, addr + 0x14);
if (!status)
continue;
if (display) {
nvkm_rd32(device, addr + 0x20);
pc = nvkm_rd32(device, addr + 0x24);
oplow = nvkm_rd32(device, addr + 0x70);
ophigh = nvkm_rd32(device, addr + 0x74);
nvkm_snprintbf(msg, sizeof(msg),
nv50_mp_exec_errors, status);
nvkm_error(subdev, "TRAP_MP_EXEC - TP %d MP %d: "
"%08x [%s] at %06x warp %d, "
"opcode %08x %08x\n",
tpid, i, status, msg, pc & 0xffffff,
pc >> 24, oplow, ophigh);
}
nvkm_wr32(device, addr + 0x10, mp10);
nvkm_wr32(device, addr + 0x14, 0);
mps++;
}
if (!mps && display)
nvkm_error(subdev, "TRAP_MP_EXEC - TP %d: "
"No MPs claiming errors?\n", tpid);
}
static void
nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
u32 ustatus_new, int display, const char *name)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 units = nvkm_rd32(device, 0x1540);
int tps = 0;
int i, r;
char msg[128];
u32 ustatus_addr, ustatus;
for (i = 0; i < 16; i++) {
if (!(units & (1 << i)))
continue;
if (device->chipset < 0xa0)
ustatus_addr = ustatus_old + (i << 12);
else
ustatus_addr = ustatus_new + (i << 11);
ustatus = nvkm_rd32(device, ustatus_addr) & 0x7fffffff;
if (!ustatus)
continue;
tps++;
switch (type) {
case 6: /* texture error... unknown for now */
if (display) {
nvkm_error(subdev, "magic set %d:\n", i);
for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
nvkm_error(subdev, "\t%08x: %08x\n", r,
nvkm_rd32(device, r));
if (ustatus) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_tex_traps, ustatus);
nvkm_error(subdev,
"%s - TP%d: %08x [%s]\n",
name, i, ustatus, msg);
ustatus = 0;
}
}
break;
case 7: /* MP error */
if (ustatus & 0x04030000) {
nv50_gr_mp_trap(gr, i, display);
ustatus &= ~0x04030000;
}
if (ustatus && display) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_mpc_traps, ustatus);
nvkm_error(subdev, "%s - TP%d: %08x [%s]\n",
name, i, ustatus, msg);
ustatus = 0;
}
break;
case 8: /* PROP error */
if (display)
nv50_gr_prop_trap(
gr, ustatus_addr, ustatus, i);
ustatus = 0;
break;
}
if (ustatus) {
if (display)
nvkm_error(subdev, "%s - TP%d: Unhandled ustatus %08x\n", name, i, ustatus);
}
nvkm_wr32(device, ustatus_addr, 0xc0000000);
}
if (!tps && display)
nvkm_warn(subdev, "%s - No TPs claiming errors?\n", name);
}
static int
nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
int chid, u64 inst, const char *name)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 status = nvkm_rd32(device, 0x400108);
u32 ustatus;
char msg[128];
if (!status && display) {
nvkm_error(subdev, "TRAP: no units reporting traps?\n");
return 1;
}
/* DISPATCH: Relays commands to other units and handles NOTIFY,
* COND, QUERY. If you get a trap from it, the command is still stuck
* in DISPATCH and you need to do something about it. */
if (status & 0x001) {
ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff;
if (!ustatus && display) {
nvkm_error(subdev, "TRAP_DISPATCH - no ustatus?\n");
}
nvkm_wr32(device, 0x400500, 0x00000000);
/* Known to be triggered by screwed up NOTIFY and COND... */
if (ustatus & 0x00000001) {
u32 addr = nvkm_rd32(device, 0x400808);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 datal = nvkm_rd32(device, 0x40080c);
u32 datah = nvkm_rd32(device, 0x400810);
u32 class = nvkm_rd32(device, 0x400814);
u32 r848 = nvkm_rd32(device, 0x400848);
nvkm_error(subdev, "TRAP DISPATCH_FAULT\n");
if (display && (addr & 0x80000000)) {
nvkm_error(subdev,
"ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x%08x "
"400808 %08x 400848 %08x\n",
chid, inst, name, subc, class, mthd,
datah, datal, addr, r848);
} else
if (display) {
nvkm_error(subdev, "no stuck command?\n");
}
nvkm_wr32(device, 0x400808, 0);
nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3);
nvkm_wr32(device, 0x400848, 0);
ustatus &= ~0x00000001;
}
if (ustatus & 0x00000002) {
u32 addr = nvkm_rd32(device, 0x40084c);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, 0x40085c);
u32 class = nvkm_rd32(device, 0x400814);
nvkm_error(subdev, "TRAP DISPATCH_QUERY\n");
if (display && (addr & 0x80000000)) {
nvkm_error(subdev,
"ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x "
"40084c %08x\n", chid, inst, name,
subc, class, mthd, data, addr);
} else
if (display) {
nvkm_error(subdev, "no stuck command?\n");
}
nvkm_wr32(device, 0x40084c, 0);
ustatus &= ~0x00000002;
}
if (ustatus && display) {
nvkm_error(subdev, "TRAP_DISPATCH "
"(unknown %08x)\n", ustatus);
}
nvkm_wr32(device, 0x400804, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x001);
status &= ~0x001;
if (!status)
return 0;
}
/* M2MF: Memory to memory copy engine. */
if (status & 0x002) {
u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff;
if (display) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_m2mf, ustatus);
nvkm_error(subdev, "TRAP_M2MF %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_M2MF %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x406804),
nvkm_rd32(device, 0x406808),
nvkm_rd32(device, 0x40680c),
nvkm_rd32(device, 0x406810));
}
/* No sane way found yet -- just reset the bugger. */
nvkm_wr32(device, 0x400040, 2);
nvkm_wr32(device, 0x400040, 0);
nvkm_wr32(device, 0x406800, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x002);
status &= ~0x002;
}
/* VFETCH: Fetches data from vertex buffers. */
if (status & 0x004) {
u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff;
if (display) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_vfetch, ustatus);
nvkm_error(subdev, "TRAP_VFETCH %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_VFETCH %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x400c00),
nvkm_rd32(device, 0x400c08),
nvkm_rd32(device, 0x400c0c),
nvkm_rd32(device, 0x400c10));
}
nvkm_wr32(device, 0x400c04, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x004);
status &= ~0x004;
}
/* STRMOUT: DirectX streamout / OpenGL transform feedback. */
if (status & 0x008) {
ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff;
if (display) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_strmout, ustatus);
nvkm_error(subdev, "TRAP_STRMOUT %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x401804),
nvkm_rd32(device, 0x401808),
nvkm_rd32(device, 0x40180c),
nvkm_rd32(device, 0x401810));
}
/* No sane way found yet -- just reset the bugger. */
nvkm_wr32(device, 0x400040, 0x80);
nvkm_wr32(device, 0x400040, 0);
nvkm_wr32(device, 0x401800, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x008);
status &= ~0x008;
}
/* CCACHE: Handles code and c[] caches and fills them. */
if (status & 0x010) {
ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff;
if (display) {
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_ccache, ustatus);
nvkm_error(subdev, "TRAP_CCACHE %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_CCACHE %08x %08x %08x %08x "
"%08x %08x %08x\n",
nvkm_rd32(device, 0x405000),
nvkm_rd32(device, 0x405004),
nvkm_rd32(device, 0x405008),
nvkm_rd32(device, 0x40500c),
nvkm_rd32(device, 0x405010),
nvkm_rd32(device, 0x405014),
nvkm_rd32(device, 0x40501c));
}
nvkm_wr32(device, 0x405018, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x010);
status &= ~0x010;
}
/* Unknown, not seen yet... 0x402000 is the only trap status reg
* remaining, so try to handle it anyway. Perhaps related to that
* unknown DMA slot on tesla? */
if (status & 0x20) {
ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff;
if (display)
nvkm_error(subdev, "TRAP_UNKC04 %08x\n", ustatus);
nvkm_wr32(device, 0x402000, 0xc0000000);
/* no status modifiction on purpose */
}
/* TEXTURE: CUDA texturing units */
if (status & 0x040) {
nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display,
"TRAP_TEXTURE");
nvkm_wr32(device, 0x400108, 0x040);
status &= ~0x040;
}
/* MP: CUDA execution engines. */
if (status & 0x080) {
nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display,
"TRAP_MP");
nvkm_wr32(device, 0x400108, 0x080);
status &= ~0x080;
}
/* PROP: Handles TP-initiated uncached memory accesses:
* l[], g[], stack, 2d surfaces, render targets. */
if (status & 0x100) {
nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display,
"TRAP_PROP");
nvkm_wr32(device, 0x400108, 0x100);
status &= ~0x100;
}
if (status) {
if (display)
nvkm_error(subdev, "TRAP: unknown %08x\n", status);
nvkm_wr32(device, 0x400108, status);
}
return 1;
}
void
nv50_gr_intr(struct nvkm_gr *base)
{
struct nv50_gr *gr = nv50_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_chan *chan;
u32 stat = nvkm_rd32(device, 0x400100);
u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff;
u32 addr = nvkm_rd32(device, 0x400704);
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, 0x400708);
u32 class = nvkm_rd32(device, 0x400814);
u32 show = stat, show_bitfield = stat;
const struct nvkm_enum *en;
unsigned long flags;
const char *name = "unknown";
char msg[128];
int chid = -1;
chan = nvkm_chan_get_inst(&gr->base.engine, (u64)inst << 12, &flags);
if (chan) {
name = chan->name;
chid = chan->id;
}
if (show & 0x00100000) {
u32 ecode = nvkm_rd32(device, 0x400110);
en = nvkm_enum_find(nv50_data_error_names, ecode);
nvkm_error(subdev, "DATA_ERROR %08x [%s]\n",
ecode, en ? en->name : "");
show_bitfield &= ~0x00100000;
}
if (stat & 0x00200000) {
if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name))
show &= ~0x00200000;
show_bitfield &= ~0x00200000;
}
nvkm_wr32(device, 0x400100, stat);
nvkm_wr32(device, 0x400500, 0x00010001);
if (show) {
show &= show_bitfield;
nvkm_snprintbf(msg, sizeof(msg), nv50_gr_intr_name, show);
nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x\n",
stat, msg, chid, (u64)inst << 12, name,
subc, class, mthd, data);
}
if (nvkm_rd32(device, 0x400824) & (1 << 31))
nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31));
nvkm_chan_put(&chan, flags);
}
int
nv50_gr_init(struct nvkm_gr *base)
{
struct nv50_gr *gr = nv50_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret, units, i;
/* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
nvkm_wr32(device, 0x40008c, 0x00000004);
/* reset/enable traps and interrupts */
nvkm_wr32(device, 0x400804, 0xc0000000);
nvkm_wr32(device, 0x406800, 0xc0000000);
nvkm_wr32(device, 0x400c04, 0xc0000000);
nvkm_wr32(device, 0x401800, 0xc0000000);
nvkm_wr32(device, 0x405018, 0xc0000000);
nvkm_wr32(device, 0x402000, 0xc0000000);
units = nvkm_rd32(device, 0x001540);
for (i = 0; i < 16; i++) {
if (!(units & (1 << i)))
continue;
if (device->chipset < 0xa0) {
nvkm_wr32(device, 0x408900 + (i << 12), 0xc0000000);
nvkm_wr32(device, 0x408e08 + (i << 12), 0xc0000000);
nvkm_wr32(device, 0x408314 + (i << 12), 0xc0000000);
} else {
nvkm_wr32(device, 0x408600 + (i << 11), 0xc0000000);
nvkm_wr32(device, 0x408708 + (i << 11), 0xc0000000);
nvkm_wr32(device, 0x40831c + (i << 11), 0xc0000000);
}
}
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400500, 0x00010001);
/* upload context program, initialise ctxctl defaults */
ret = nv50_grctx_init(device, &gr->size);
if (ret)
return ret;
nvkm_wr32(device, 0x400824, 0x00000000);
nvkm_wr32(device, 0x400828, 0x00000000);
nvkm_wr32(device, 0x40082c, 0x00000000);
nvkm_wr32(device, 0x400830, 0x00000000);
nvkm_wr32(device, 0x40032c, 0x00000000);
nvkm_wr32(device, 0x400330, 0x00000000);
/* some unknown zcull magic */
switch (device->chipset & 0xf0) {
case 0x50:
case 0x80:
case 0x90:
nvkm_wr32(device, 0x402ca8, 0x00000800);
break;
case 0xa0:
default:
if (device->chipset == 0xa0 ||
device->chipset == 0xaa ||
device->chipset == 0xac) {
nvkm_wr32(device, 0x402ca8, 0x00000802);
} else {
nvkm_wr32(device, 0x402cc0, 0x00000000);
nvkm_wr32(device, 0x402ca8, 0x00000002);
}
break;
}
/* zero out zcull regions */
for (i = 0; i < 8; i++) {
nvkm_wr32(device, 0x402c20 + (i * 0x10), 0x00000000);
nvkm_wr32(device, 0x402c24 + (i * 0x10), 0x00000000);
nvkm_wr32(device, 0x402c28 + (i * 0x10), 0x00000000);
nvkm_wr32(device, 0x402c2c + (i * 0x10), 0x00000000);
}
return 0;
}
int
nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv50_gr *gr;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
nv50_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_TESLA, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{}
}
};
int
nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&nv50_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct nvkm_object_func
nv2a_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x36b0, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
nvkm_wo32(chan->inst, 0x047c, 0x00000101);
nvkm_wo32(chan->inst, 0x0490, 0x00000111);
nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
for (i = 0x04d4; i <= 0x04e0; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x04f4; i <= 0x0500; i += 4)
nvkm_wo32(chan->inst, i, 0x00080000);
for (i = 0x050c; i <= 0x0518; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x051c; i <= 0x0528; i += 4)
nvkm_wo32(chan->inst, i, 0x000105b8);
for (i = 0x052c; i <= 0x0538; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
for (i = 0x055c; i <= 0x0598; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
nvkm_wo32(chan->inst, 0x0604, 0x00004000);
nvkm_wo32(chan->inst, 0x0610, 0x00000001);
nvkm_wo32(chan->inst, 0x0618, 0x00040000);
nvkm_wo32(chan->inst, 0x061c, 0x00010000);
for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
}
nvkm_wo32(chan->inst, 0x269c, 0x3f800000);
nvkm_wo32(chan->inst, 0x26b0, 0x3f800000);
nvkm_wo32(chan->inst, 0x26dc, 0x40000000);
nvkm_wo32(chan->inst, 0x26e0, 0x3f800000);
nvkm_wo32(chan->inst, 0x26e4, 0x3f000000);
nvkm_wo32(chan->inst, 0x26ec, 0x40000000);
nvkm_wo32(chan->inst, 0x26f0, 0x3f800000);
nvkm_wo32(chan->inst, 0x26f8, 0xbf800000);
nvkm_wo32(chan->inst, 0x2700, 0xbf800000);
nvkm_wo32(chan->inst, 0x3024, 0x000fe000);
nvkm_wo32(chan->inst, 0x30a0, 0x000003f8);
nvkm_wo32(chan->inst, 0x33fc, 0x002fe000);
for (i = 0x341c; i <= 0x3438; i += 4)
nvkm_wo32(chan->inst, i, 0x001c527c);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct nvkm_gr_func
nv2a_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv20_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv2a_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
{}
}
};
int
nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "gk104.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gk110_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{ 0x4041b4, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk110_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff00 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk110_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
const struct gf100_gr_init
gk110_gr_init_cwd_0[] = {
{ 0x405b44, 1, 0x04, 0x00000000 },
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk110_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000000 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk110_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419aec, 1, 0x04, 0x00000000 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk110_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00b08bea },
{ 0x419c84, 1, 0x04, 0x00010384 },
{ 0x419cbc, 1, 0x04, 0x281b3646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00020230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk110_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00000000 },
{ 0x419eb4, 1, 0x04, 0x00000000 },
{ 0x419ebc, 2, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419ed0, 1, 0x04, 0x00003234 },
{ 0x419f74, 1, 0x04, 0x00015555 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gk110_gr_pack_mmio[] = {
{ gk104_gr_init_main_0 },
{ gk110_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gk110_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gk110_gr_init_sked_0 },
{ gk110_gr_init_cwd_0 },
{ gf119_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gk110_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gk104_gr_init_gpc_unk_2 },
{ gk104_gr_init_tpccs_0 },
{ gk110_gr_init_tex_0 },
{ gk104_gr_init_pe_0 },
{ gk110_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gk110_gr_init_sm_0 },
{ gf117_gr_init_pes_0 },
{ gf117_gr_init_wwdx_0 },
{ gf117_gr_init_cbm_0 },
{ gk104_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_blcg_init_sked_0[] = {
{ 0x407000, 1, 0x00004041 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_blcg_init_gpc_gcc_0[] = {
{ 0x419020, 1, 0x00000042 },
{ 0x419038, 1, 0x00000042 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_blcg_init_gpc_l1c_0[] = {
{ 0x419cd4, 2, 0x00004042 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_blcg_init_gpc_mp_0[] = {
{ 0x419fd0, 1, 0x00004043 },
{ 0x419fd8, 1, 0x00004049 },
{ 0x419fe0, 2, 0x00004042 },
{ 0x419ff0, 1, 0x00000046 },
{ 0x419ff8, 1, 0x00004042 },
{ 0x419f90, 1, 0x00004042 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_main_0[] = {
{ 0x4041f4, 1, 0x00000000 },
{ 0x409894, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_unk_0[] = {
{ 0x406004, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_sked_0[] = {
{ 0x407004, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_ctxctl_0[] = {
{ 0x41a894, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_unk_0[] = {
{ 0x418504, 1, 0x00000000 },
{ 0x41860c, 1, 0x00000000 },
{ 0x41868c, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_esetup_0[] = {
{ 0x41882c, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_zcull_0[] = {
{ 0x418974, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_l1c_0[] = {
{ 0x419cd8, 2, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_unk_1[] = {
{ 0x419c74, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_mp_0[] = {
{ 0x419fd4, 1, 0x00004a4a },
{ 0x419fdc, 1, 0x00000014 },
{ 0x419fe4, 1, 0x00000000 },
{ 0x419ff4, 1, 0x00001724 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_gpc_ppc_0[] = {
{ 0x41be2c, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_init
gk110_clkgate_slcg_init_pcounter_0[] = {
{ 0x1be018, 1, 0x000001ff },
{ 0x1bc018, 1, 0x000001ff },
{ 0x1b8018, 1, 0x000001ff },
{ 0x1b4124, 1, 0x00000000 },
{}
};
static const struct nvkm_therm_clkgate_pack
gk110_clkgate_pack[] = {
{ gk104_clkgate_blcg_init_main_0 },
{ gk104_clkgate_blcg_init_rstr2d_0 },
{ gk104_clkgate_blcg_init_unk_0 },
{ gk104_clkgate_blcg_init_gcc_0 },
{ gk110_clkgate_blcg_init_sked_0 },
{ gk104_clkgate_blcg_init_unk_1 },
{ gk104_clkgate_blcg_init_gpc_ctxctl_0 },
{ gk104_clkgate_blcg_init_gpc_unk_0 },
{ gk104_clkgate_blcg_init_gpc_esetup_0 },
{ gk104_clkgate_blcg_init_gpc_tpbus_0 },
{ gk104_clkgate_blcg_init_gpc_zcull_0 },
{ gk104_clkgate_blcg_init_gpc_tpconf_0 },
{ gk104_clkgate_blcg_init_gpc_unk_1 },
{ gk110_clkgate_blcg_init_gpc_gcc_0 },
{ gk104_clkgate_blcg_init_gpc_ffb_0 },
{ gk104_clkgate_blcg_init_gpc_tex_0 },
{ gk104_clkgate_blcg_init_gpc_poly_0 },
{ gk110_clkgate_blcg_init_gpc_l1c_0 },
{ gk104_clkgate_blcg_init_gpc_unk_2 },
{ gk110_clkgate_blcg_init_gpc_mp_0 },
{ gk104_clkgate_blcg_init_gpc_ppc_0 },
{ gk104_clkgate_blcg_init_rop_zrop_0 },
{ gk104_clkgate_blcg_init_rop_0 },
{ gk104_clkgate_blcg_init_rop_crop_0 },
{ gk104_clkgate_blcg_init_pxbar_0 },
{ gk110_clkgate_slcg_init_main_0 },
{ gk110_clkgate_slcg_init_unk_0 },
{ gk110_clkgate_slcg_init_sked_0 },
{ gk110_clkgate_slcg_init_gpc_ctxctl_0 },
{ gk110_clkgate_slcg_init_gpc_unk_0 },
{ gk110_clkgate_slcg_init_gpc_esetup_0 },
{ gk110_clkgate_slcg_init_gpc_zcull_0 },
{ gk110_clkgate_slcg_init_gpc_l1c_0 },
{ gk110_clkgate_slcg_init_gpc_unk_1 },
{ gk110_clkgate_slcg_init_gpc_mp_0 },
{ gk110_clkgate_slcg_init_gpc_ppc_0 },
{ gk110_clkgate_slcg_init_pcounter_0 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
#include "fuc/hubgk110.fuc3.h"
struct gf100_gr_ucode
gk110_gr_fecs_ucode = {
.code.data = gk110_grhub_code,
.code.size = sizeof(gk110_grhub_code),
.data.data = gk110_grhub_data,
.data.size = sizeof(gk110_grhub_data),
};
#include "fuc/gpcgk110.fuc3.h"
struct gf100_gr_ucode
gk110_gr_gpccs_ucode = {
.code.data = gk110_grgpc_code,
.code.size = sizeof(gk110_grgpc_code),
.data.data = gk110_grgpc_data,
.data.size = sizeof(gk110_grgpc_data),
};
void
gk110_gr_init_419eb4(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
nvkm_mask(device, 0x419eb4, 0x00002000, 0x00002000);
nvkm_mask(device, 0x419eb4, 0x00004000, 0x00004000);
nvkm_mask(device, 0x419eb4, 0x00008000, 0x00008000);
nvkm_mask(device, 0x419eb4, 0x00001000, 0x00000000);
nvkm_mask(device, 0x419eb4, 0x00002000, 0x00000000);
nvkm_mask(device, 0x419eb4, 0x00004000, 0x00000000);
nvkm_mask(device, 0x419eb4, 0x00008000, 0x00000000);
}
static const struct gf100_gr_func
gk110_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gk110_gr_init_419eb4,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gk110_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gk110_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 2,
.grctx = &gk110_grctx,
.clkgate_pack = gk110_clkgate_pack,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, KEPLER_B, &gf100_fermi },
{ -1, -1, KEPLER_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gk110_gr_fwif[] = {
{ -1, gf100_gr_load, &gk110_gr },
{ -1, gf100_gr_nofw, &gk110_gr },
{}
};
int
gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf104_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf104_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
const struct gf100_gr_init
gf104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf104_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gf104_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf100_gr_init_prop_0 },
{ gf100_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf100_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gf100_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf104_gr_init_tex_0 },
{ gf104_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_wwdx_0 },
{ gf100_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf104_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct gf100_gr_func
gf104_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf104_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf100_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.grctx = &gf104_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{}
}
};
static const struct gf100_gr_fwif
gf104_gr_fwif[] = {
{ -1, gf100_gr_load, &gf104_gr },
{ -1, gf100_gr_nofw, &gf104_gr },
{}
};
int
gf104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf104_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
static void
ga102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
}
static void
ga102_grctx_generate_unkn(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
}
static void
ga102_grctx_generate_r419ea8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x419ea8, nvkm_rd32(device, 0x504728) | 0x08000000);
}
const struct gf100_grctx_func
ga102_grctx = {
.main = gf100_grctx_generate_main,
.unkn = ga102_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x1140,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gv100_grctx_generate_attrib_cb,
.attrib = gv100_grctx_generate_attrib,
.attrib_nr_max = 0x800,
.attrib_nr = 0x4a1,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.unknown_size = 0x80000,
.unknown = tu102_grctx_generate_unknown,
.gfxp_nr = 0xd28,
.sm_id = ga102_grctx_generate_sm_id,
.skip_pd_num_tpc_per_gpc = true,
.rop_mapping = gv100_grctx_generate_rop_mapping,
.r406500 = gm200_grctx_generate_r406500,
.r400088 = gv100_grctx_generate_r400088,
.r419ea8 = ga102_grctx_generate_r419ea8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxga102.c |
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
const struct gf100_grctx_func
gp104_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x900,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gp100_grctx_generate_attrib_cb,
.attrib = gp102_grctx_generate_attrib,
.attrib_nr_max = 0x4b0,
.attrib_nr = 0x320,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xba8,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.tpc_mask = gm200_grctx_generate_tpc_mask,
.smid_config = gp100_grctx_generate_smid_config,
.r419a3c = gm200_grctx_generate_r419a3c,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp104.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gf117_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
{ 0x419850, 3, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf117_gr_init_pes_0[] = {
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
{ 0x41be0c, 1, 0x04, 0x00000000 },
{ 0x41be10, 1, 0x04, 0x003b8bc7 },
{ 0x41be14, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf117_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{ 0x41bff8, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf117_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{ 0x41bee8, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf117_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gf119_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf119_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gf119_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf119_gr_init_tex_0 },
{ gf117_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gf119_gr_init_sm_0 },
{ gf117_gr_init_pes_0 },
{ gf117_gr_init_wwdx_0 },
{ gf117_gr_init_cbm_0 },
{ gf100_gr_init_be_0 },
{ gf119_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
#include "fuc/hubgf117.fuc3.h"
static struct gf100_gr_ucode
gf117_gr_fecs_ucode = {
.code.data = gf117_grhub_code,
.code.size = sizeof(gf117_grhub_code),
.data.data = gf117_grhub_data,
.data.size = sizeof(gf117_grhub_data),
};
#include "fuc/gpcgf117.fuc3.h"
static struct gf100_gr_ucode
gf117_gr_gpccs_ucode = {
.code.data = gf117_grgpc_code,
.code.size = sizeof(gf117_grgpc_code),
.data.data = gf117_grgpc_data,
.data.size = sizeof(gf117_grgpc_data),
};
void
gf117_gr_init_zcull(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
/*TODO: fill in litter vals for gf117-gm2xx */
const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) :
(gr->func->gpc_nr * gr->func->tpc_nr);
u8 bank[GPC_MAX] = {}, gpc, i, j;
u32 data;
for (i = 0; i < tile_nr; i += 8) {
for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
data |= bank[gr->tile[i + j]] << (j * 4);
bank[gr->tile[i + j]]++;
}
nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
}
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
gr->tpc_total);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
}
static const struct gf100_gr_func
gf117_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf117_gr_pack_mmio,
.fecs.ucode = &gf117_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf117_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 1,
.grctx = &gf117_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_B, &gf100_fermi },
{ -1, -1, FERMI_C, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{ -1, -1, FERMI_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gf117_gr_fwif[] = {
{ -1, gf100_gr_load, &gf117_gr },
{ -1, gf100_gr_nofw, &gf117_gr },
{}
};
int
gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c |
/*
* Copyright 2009 Marcin Kościelnicki
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#define CP_FLAG_CLEAR 0
#define CP_FLAG_SET 1
#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
#define CP_FLAG_SWAP_DIRECTION_LOAD 0
#define CP_FLAG_SWAP_DIRECTION_SAVE 1
#define CP_FLAG_UNK01 ((0 * 32) + 1)
#define CP_FLAG_UNK01_CLEAR 0
#define CP_FLAG_UNK01_SET 1
#define CP_FLAG_UNK03 ((0 * 32) + 3)
#define CP_FLAG_UNK03_CLEAR 0
#define CP_FLAG_UNK03_SET 1
#define CP_FLAG_USER_SAVE ((0 * 32) + 5)
#define CP_FLAG_USER_SAVE_NOT_PENDING 0
#define CP_FLAG_USER_SAVE_PENDING 1
#define CP_FLAG_USER_LOAD ((0 * 32) + 6)
#define CP_FLAG_USER_LOAD_NOT_PENDING 0
#define CP_FLAG_USER_LOAD_PENDING 1
#define CP_FLAG_UNK0B ((0 * 32) + 0xb)
#define CP_FLAG_UNK0B_CLEAR 0
#define CP_FLAG_UNK0B_SET 1
#define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe)
#define CP_FLAG_XFER_SWITCH_DISABLE 0
#define CP_FLAG_XFER_SWITCH_ENABLE 1
#define CP_FLAG_STATE ((0 * 32) + 0x1c)
#define CP_FLAG_STATE_STOPPED 0
#define CP_FLAG_STATE_RUNNING 1
#define CP_FLAG_UNK1D ((0 * 32) + 0x1d)
#define CP_FLAG_UNK1D_CLEAR 0
#define CP_FLAG_UNK1D_SET 1
#define CP_FLAG_UNK20 ((1 * 32) + 0)
#define CP_FLAG_UNK20_CLEAR 0
#define CP_FLAG_UNK20_SET 1
#define CP_FLAG_STATUS ((2 * 32) + 0)
#define CP_FLAG_STATUS_BUSY 0
#define CP_FLAG_STATUS_IDLE 1
#define CP_FLAG_AUTO_SAVE ((2 * 32) + 4)
#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
#define CP_FLAG_AUTO_SAVE_PENDING 1
#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
#define CP_FLAG_AUTO_LOAD_PENDING 1
#define CP_FLAG_NEWCTX ((2 * 32) + 10)
#define CP_FLAG_NEWCTX_BUSY 0
#define CP_FLAG_NEWCTX_DONE 1
#define CP_FLAG_XFER ((2 * 32) + 11)
#define CP_FLAG_XFER_IDLE 0
#define CP_FLAG_XFER_BUSY 1
#define CP_FLAG_ALWAYS ((2 * 32) + 13)
#define CP_FLAG_ALWAYS_FALSE 0
#define CP_FLAG_ALWAYS_TRUE 1
#define CP_FLAG_INTR ((2 * 32) + 15)
#define CP_FLAG_INTR_NOT_PENDING 0
#define CP_FLAG_INTR_PENDING 1
#define CP_CTX 0x00100000
#define CP_CTX_COUNT 0x000f0000
#define CP_CTX_COUNT_SHIFT 16
#define CP_CTX_REG 0x00003fff
#define CP_LOAD_SR 0x00200000
#define CP_LOAD_SR_VALUE 0x000fffff
#define CP_BRA 0x00400000
#define CP_BRA_IP 0x0001ff00
#define CP_BRA_IP_SHIFT 8
#define CP_BRA_IF_CLEAR 0x00000080
#define CP_BRA_FLAG 0x0000007f
#define CP_WAIT 0x00500000
#define CP_WAIT_SET 0x00000080
#define CP_WAIT_FLAG 0x0000007f
#define CP_SET 0x00700000
#define CP_SET_1 0x00000080
#define CP_SET_FLAG 0x0000007f
#define CP_NEWCTX 0x00600004
#define CP_NEXT_TO_SWAP 0x00600005
#define CP_SET_CONTEXT_POINTER 0x00600006
#define CP_SET_XFER_POINTER 0x00600007
#define CP_ENABLE 0x00600009
#define CP_END 0x0060000c
#define CP_NEXT_TO_CURRENT 0x0060000d
#define CP_DISABLE1 0x0090ffff
#define CP_DISABLE2 0x0091ffff
#define CP_XFER_1 0x008000ff
#define CP_XFER_2 0x008800ff
#define CP_SEEK_1 0x00c000ff
#define CP_SEEK_2 0x00c800ff
#include "ctxnv40.h"
#include "nv50.h"
#include <subdev/fb.h>
#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
/*
* This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
* the GPU itself that does context-switching, but it needs a special
* microcode to do it. And it's the driver's task to supply this microcode,
* further known as ctxprog, as well as the initial context values, known
* as ctxvals.
*
* Without ctxprog, you cannot switch contexts. Not even in software, since
* the majority of context [xfer strands] isn't accessible directly. You're
* stuck with a single channel, and you also suffer all the problems resulting
* from missing ctxvals, since you cannot load them.
*
* Without ctxvals, you're stuck with PGRAPH's default context. It's enough to
* run 2d operations, but trying to utilise 3d or CUDA will just lock you up,
* since you don't have... some sort of needed setup.
*
* Nouveau will just disable acceleration if not given ctxprog + ctxvals, since
* it's too much hassle to handle no-ctxprog as a special case.
*/
/*
* How ctxprogs work.
*
* The ctxprog is written in its own kind of microcode, with very small and
* crappy set of available commands. You upload it to a small [512 insns]
* area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to
* switch channel. or when the driver explicitely requests it. Stuff visible
* to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands,
* the per-channel context save area in VRAM [known as ctxvals or grctx],
* 4 flags registers, a scratch register, two grctx pointers, plus many
* random poorly-understood details.
*
* When ctxprog runs, it's supposed to check what operations are asked of it,
* save old context if requested, optionally reset PGRAPH and switch to the
* new channel, and load the new context. Context consists of three major
* parts: subset of MMIO registers and two "xfer areas".
*/
/* TODO:
* - document unimplemented bits compared to nvidia
* - NVAx: make a TP subroutine, use it.
* - use 0x4008fc instead of 0x1540?
*/
enum cp_label {
cp_check_load = 1,
cp_setup_auto_load,
cp_setup_load,
cp_setup_save,
cp_swap_state,
cp_prepare_exit,
cp_exit,
};
static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx);
static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx);
static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx);
/* Main function: construct the ctxprog skeleton, call the other functions. */
static int
nv50_grctx_generate(struct nvkm_grctx *ctx)
{
cp_set (ctx, STATE, RUNNING);
cp_set (ctx, XFER_SWITCH, ENABLE);
/* decide whether we're loading/unloading the context */
cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
cp_name(ctx, cp_check_load);
cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit);
/* setup for context load */
cp_name(ctx, cp_setup_auto_load);
cp_out (ctx, CP_DISABLE1);
cp_out (ctx, CP_DISABLE2);
cp_out (ctx, CP_ENABLE);
cp_out (ctx, CP_NEXT_TO_SWAP);
cp_set (ctx, UNK01, SET);
cp_name(ctx, cp_setup_load);
cp_out (ctx, CP_NEWCTX);
cp_wait(ctx, NEWCTX, BUSY);
cp_set (ctx, UNK1D, CLEAR);
cp_set (ctx, SWAP_DIRECTION, LOAD);
cp_bra (ctx, UNK0B, SET, cp_prepare_exit);
cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
/* setup for context save */
cp_name(ctx, cp_setup_save);
cp_set (ctx, UNK1D, SET);
cp_wait(ctx, STATUS, BUSY);
cp_wait(ctx, INTR, PENDING);
cp_bra (ctx, STATUS, BUSY, cp_setup_save);
cp_set (ctx, UNK01, SET);
cp_set (ctx, SWAP_DIRECTION, SAVE);
/* general PGRAPH state */
cp_name(ctx, cp_swap_state);
cp_set (ctx, UNK03, SET);
cp_pos (ctx, 0x00004/4);
cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
cp_pos (ctx, 0x00100/4);
nv50_gr_construct_mmio(ctx);
nv50_gr_construct_xfer1(ctx);
nv50_gr_construct_xfer2(ctx);
cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
cp_set (ctx, UNK20, SET);
cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */
cp_lsr (ctx, ctx->ctxvals_base);
cp_out (ctx, CP_SET_XFER_POINTER);
cp_lsr (ctx, 4);
cp_out (ctx, CP_SEEK_1);
cp_out (ctx, CP_XFER_1);
cp_wait(ctx, XFER, BUSY);
/* pre-exit state updates */
cp_name(ctx, cp_prepare_exit);
cp_set (ctx, UNK01, CLEAR);
cp_set (ctx, UNK03, CLEAR);
cp_set (ctx, UNK1D, CLEAR);
cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
cp_out (ctx, CP_NEXT_TO_CURRENT);
cp_name(ctx, cp_exit);
cp_set (ctx, USER_SAVE, NOT_PENDING);
cp_set (ctx, USER_LOAD, NOT_PENDING);
cp_set (ctx, XFER_SWITCH, DISABLE);
cp_set (ctx, STATE, STOPPED);
cp_out (ctx, CP_END);
ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */
return 0;
}
void
nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
nv50_grctx_generate(&(struct nvkm_grctx) {
.device = device,
.mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
nv50_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
struct nvkm_grctx ctx = {
.device = device,
.mode = NVKM_GRCTX_PROG,
.ucode = ctxprog,
.ctxprog_max = 512,
};
if (!ctxprog)
return -ENOMEM;
nv50_grctx_generate(&ctx);
nvkm_wr32(device, 0x400324, 0);
for (i = 0; i < ctx.ctxprog_len; i++)
nvkm_wr32(device, 0x400328, ctxprog[i]);
*size = ctx.ctxvals_pos * 4;
kfree(ctxprog);
return 0;
}
/*
* Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
* registers to save/restore and the default values for them.
*/
static void
nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx);
static void
nv50_gr_construct_mmio(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i, j;
int offset, base;
u32 units = nvkm_rd32(device, 0x1540);
/* 0800: DISPATCH */
cp_ctx(ctx, 0x400808, 7);
gr_def(ctx, 0x400814, 0x00000030);
cp_ctx(ctx, 0x400834, 0x32);
if (device->chipset == 0x50) {
gr_def(ctx, 0x400834, 0xff400040);
gr_def(ctx, 0x400838, 0xfff00080);
gr_def(ctx, 0x40083c, 0xfff70090);
gr_def(ctx, 0x400840, 0xffe806a8);
}
gr_def(ctx, 0x400844, 0x00000002);
if (IS_NVA3F(device->chipset))
gr_def(ctx, 0x400894, 0x00001000);
gr_def(ctx, 0x4008e8, 0x00000003);
gr_def(ctx, 0x4008ec, 0x00001000);
if (device->chipset == 0x50)
cp_ctx(ctx, 0x400908, 0xb);
else if (device->chipset < 0xa0)
cp_ctx(ctx, 0x400908, 0xc);
else
cp_ctx(ctx, 0x400908, 0xe);
if (device->chipset >= 0xa0)
cp_ctx(ctx, 0x400b00, 0x1);
if (IS_NVA3F(device->chipset)) {
cp_ctx(ctx, 0x400b10, 0x1);
gr_def(ctx, 0x400b10, 0x0001629d);
cp_ctx(ctx, 0x400b20, 0x1);
gr_def(ctx, 0x400b20, 0x0001629d);
}
nv50_gr_construct_mmio_ddata(ctx);
/* 0C00: VFETCH */
cp_ctx(ctx, 0x400c08, 0x2);
gr_def(ctx, 0x400c08, 0x0000fe0c);
/* 1000 */
if (device->chipset < 0xa0) {
cp_ctx(ctx, 0x401008, 0x4);
gr_def(ctx, 0x401014, 0x00001000);
} else if (!IS_NVA3F(device->chipset)) {
cp_ctx(ctx, 0x401008, 0x5);
gr_def(ctx, 0x401018, 0x00001000);
} else {
cp_ctx(ctx, 0x401008, 0x5);
gr_def(ctx, 0x401018, 0x00004000);
}
/* 1400 */
cp_ctx(ctx, 0x401400, 0x8);
cp_ctx(ctx, 0x401424, 0x3);
if (device->chipset == 0x50)
gr_def(ctx, 0x40142c, 0x0001fd87);
else
gr_def(ctx, 0x40142c, 0x00000187);
cp_ctx(ctx, 0x401540, 0x5);
gr_def(ctx, 0x401550, 0x00001018);
/* 1800: STREAMOUT */
cp_ctx(ctx, 0x401814, 0x1);
gr_def(ctx, 0x401814, 0x000000ff);
if (device->chipset == 0x50) {
cp_ctx(ctx, 0x40181c, 0xe);
gr_def(ctx, 0x401850, 0x00000004);
} else if (device->chipset < 0xa0) {
cp_ctx(ctx, 0x40181c, 0xf);
gr_def(ctx, 0x401854, 0x00000004);
} else {
cp_ctx(ctx, 0x40181c, 0x13);
gr_def(ctx, 0x401864, 0x00000004);
}
/* 1C00 */
cp_ctx(ctx, 0x401c00, 0x1);
switch (device->chipset) {
case 0x50:
gr_def(ctx, 0x401c00, 0x0001005f);
break;
case 0x84:
case 0x86:
case 0x94:
gr_def(ctx, 0x401c00, 0x044d00df);
break;
case 0x92:
case 0x96:
case 0x98:
case 0xa0:
case 0xaa:
case 0xac:
gr_def(ctx, 0x401c00, 0x042500df);
break;
case 0xa3:
case 0xa5:
case 0xa8:
case 0xaf:
gr_def(ctx, 0x401c00, 0x142500df);
break;
}
/* 2000 */
/* 2400 */
cp_ctx(ctx, 0x402400, 0x1);
if (device->chipset == 0x50)
cp_ctx(ctx, 0x402408, 0x1);
else
cp_ctx(ctx, 0x402408, 0x2);
gr_def(ctx, 0x402408, 0x00000600);
/* 2800: CSCHED */
cp_ctx(ctx, 0x402800, 0x1);
if (device->chipset == 0x50)
gr_def(ctx, 0x402800, 0x00000006);
/* 2C00: ZCULL */
cp_ctx(ctx, 0x402c08, 0x6);
if (device->chipset != 0x50)
gr_def(ctx, 0x402c14, 0x01000000);
gr_def(ctx, 0x402c18, 0x000000ff);
if (device->chipset == 0x50)
cp_ctx(ctx, 0x402ca0, 0x1);
else
cp_ctx(ctx, 0x402ca0, 0x2);
if (device->chipset < 0xa0)
gr_def(ctx, 0x402ca0, 0x00000400);
else if (!IS_NVA3F(device->chipset))
gr_def(ctx, 0x402ca0, 0x00000800);
else
gr_def(ctx, 0x402ca0, 0x00000400);
cp_ctx(ctx, 0x402cac, 0x4);
/* 3000: ENG2D */
cp_ctx(ctx, 0x403004, 0x1);
gr_def(ctx, 0x403004, 0x00000001);
/* 3400 */
if (device->chipset >= 0xa0) {
cp_ctx(ctx, 0x403404, 0x1);
gr_def(ctx, 0x403404, 0x00000001);
}
/* 5000: CCACHE */
cp_ctx(ctx, 0x405000, 0x1);
switch (device->chipset) {
case 0x50:
gr_def(ctx, 0x405000, 0x00300080);
break;
case 0x84:
case 0xa0:
case 0xa3:
case 0xa5:
case 0xa8:
case 0xaa:
case 0xac:
case 0xaf:
gr_def(ctx, 0x405000, 0x000e0080);
break;
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0x98:
gr_def(ctx, 0x405000, 0x00000080);
break;
}
cp_ctx(ctx, 0x405014, 0x1);
gr_def(ctx, 0x405014, 0x00000004);
cp_ctx(ctx, 0x40501c, 0x1);
cp_ctx(ctx, 0x405024, 0x1);
cp_ctx(ctx, 0x40502c, 0x1);
/* 6000? */
if (device->chipset == 0x50)
cp_ctx(ctx, 0x4063e0, 0x1);
/* 6800: M2MF */
if (device->chipset < 0x90) {
cp_ctx(ctx, 0x406814, 0x2b);
gr_def(ctx, 0x406818, 0x00000f80);
gr_def(ctx, 0x406860, 0x007f0080);
gr_def(ctx, 0x40689c, 0x007f0080);
} else {
cp_ctx(ctx, 0x406814, 0x4);
if (device->chipset == 0x98)
gr_def(ctx, 0x406818, 0x00000f80);
else
gr_def(ctx, 0x406818, 0x00001f80);
if (IS_NVA3F(device->chipset))
gr_def(ctx, 0x40681c, 0x00000030);
cp_ctx(ctx, 0x406830, 0x3);
}
/* 7000: per-ROP group state */
for (i = 0; i < 8; i++) {
if (units & (1<<(i+16))) {
cp_ctx(ctx, 0x407000 + (i<<8), 3);
if (device->chipset == 0x50)
gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
else if (device->chipset != 0xa5)
gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
else
gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
if (device->chipset == 0x50) {
cp_ctx(ctx, 0x407010 + (i<<8), 1);
} else if (device->chipset < 0xa0) {
cp_ctx(ctx, 0x407010 + (i<<8), 2);
gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
} else {
cp_ctx(ctx, 0x407010 + (i<<8), 3);
gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
if (device->chipset != 0xa5)
gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
else
gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
}
cp_ctx(ctx, 0x407080 + (i<<8), 4);
if (device->chipset != 0xa5)
gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
else
gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
if (device->chipset == 0x50)
gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
else
gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
if (device->chipset < 0xa0)
cp_ctx(ctx, 0x407094 + (i<<8), 1);
else if (!IS_NVA3F(device->chipset))
cp_ctx(ctx, 0x407094 + (i<<8), 3);
else {
cp_ctx(ctx, 0x407094 + (i<<8), 4);
gr_def(ctx, 0x4070a0 + (i<<8), 1);
}
}
}
cp_ctx(ctx, 0x407c00, 0x3);
if (device->chipset < 0x90)
gr_def(ctx, 0x407c00, 0x00010040);
else if (device->chipset < 0xa0)
gr_def(ctx, 0x407c00, 0x00390040);
else
gr_def(ctx, 0x407c00, 0x003d0040);
gr_def(ctx, 0x407c08, 0x00000022);
if (device->chipset >= 0xa0) {
cp_ctx(ctx, 0x407c10, 0x3);
cp_ctx(ctx, 0x407c20, 0x1);
cp_ctx(ctx, 0x407c2c, 0x1);
}
if (device->chipset < 0xa0) {
cp_ctx(ctx, 0x407d00, 0x9);
} else {
cp_ctx(ctx, 0x407d00, 0x15);
}
if (device->chipset == 0x98)
gr_def(ctx, 0x407d08, 0x00380040);
else {
if (device->chipset < 0x90)
gr_def(ctx, 0x407d08, 0x00010040);
else if (device->chipset < 0xa0)
gr_def(ctx, 0x407d08, 0x00390040);
else {
if (device->fb->ram->type != NVKM_RAM_TYPE_GDDR5)
gr_def(ctx, 0x407d08, 0x003d0040);
else
gr_def(ctx, 0x407d08, 0x003c0040);
}
gr_def(ctx, 0x407d0c, 0x00000022);
}
/* 8000+: per-TP state */
for (i = 0; i < 10; i++) {
if (units & (1<<i)) {
if (device->chipset < 0xa0)
base = 0x408000 + (i<<12);
else
base = 0x408000 + (i<<11);
if (device->chipset < 0xa0)
offset = base + 0xc00;
else
offset = base + 0x80;
cp_ctx(ctx, offset + 0x00, 1);
gr_def(ctx, offset + 0x00, 0x0000ff0a);
cp_ctx(ctx, offset + 0x08, 1);
/* per-MP state */
for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) {
if (!(units & (1 << (j+24)))) continue;
if (device->chipset < 0xa0)
offset = base + 0x200 + (j<<7);
else
offset = base + 0x100 + (j<<7);
cp_ctx(ctx, offset, 0x20);
gr_def(ctx, offset + 0x00, 0x01800000);
gr_def(ctx, offset + 0x04, 0x00160000);
gr_def(ctx, offset + 0x08, 0x01800000);
gr_def(ctx, offset + 0x18, 0x0003ffff);
switch (device->chipset) {
case 0x50:
gr_def(ctx, offset + 0x1c, 0x00080000);
break;
case 0x84:
gr_def(ctx, offset + 0x1c, 0x00880000);
break;
case 0x86:
gr_def(ctx, offset + 0x1c, 0x018c0000);
break;
case 0x92:
case 0x96:
case 0x98:
gr_def(ctx, offset + 0x1c, 0x118c0000);
break;
case 0x94:
gr_def(ctx, offset + 0x1c, 0x10880000);
break;
case 0xa0:
case 0xa5:
gr_def(ctx, offset + 0x1c, 0x310c0000);
break;
case 0xa3:
case 0xa8:
case 0xaa:
case 0xac:
case 0xaf:
gr_def(ctx, offset + 0x1c, 0x300c0000);
break;
}
gr_def(ctx, offset + 0x40, 0x00010401);
if (device->chipset == 0x50)
gr_def(ctx, offset + 0x48, 0x00000040);
else
gr_def(ctx, offset + 0x48, 0x00000078);
gr_def(ctx, offset + 0x50, 0x000000bf);
gr_def(ctx, offset + 0x58, 0x00001210);
if (device->chipset == 0x50)
gr_def(ctx, offset + 0x5c, 0x00000080);
else
gr_def(ctx, offset + 0x5c, 0x08000080);
if (device->chipset >= 0xa0)
gr_def(ctx, offset + 0x68, 0x0000003e);
}
if (device->chipset < 0xa0)
cp_ctx(ctx, base + 0x300, 0x4);
else
cp_ctx(ctx, base + 0x300, 0x5);
if (device->chipset == 0x50)
gr_def(ctx, base + 0x304, 0x00007070);
else if (device->chipset < 0xa0)
gr_def(ctx, base + 0x304, 0x00027070);
else if (!IS_NVA3F(device->chipset))
gr_def(ctx, base + 0x304, 0x01127070);
else
gr_def(ctx, base + 0x304, 0x05127070);
if (device->chipset < 0xa0)
cp_ctx(ctx, base + 0x318, 1);
else
cp_ctx(ctx, base + 0x320, 1);
if (device->chipset == 0x50)
gr_def(ctx, base + 0x318, 0x0003ffff);
else if (device->chipset < 0xa0)
gr_def(ctx, base + 0x318, 0x03ffffff);
else
gr_def(ctx, base + 0x320, 0x07ffffff);
if (device->chipset < 0xa0)
cp_ctx(ctx, base + 0x324, 5);
else
cp_ctx(ctx, base + 0x328, 4);
if (device->chipset < 0xa0) {
cp_ctx(ctx, base + 0x340, 9);
offset = base + 0x340;
} else if (!IS_NVA3F(device->chipset)) {
cp_ctx(ctx, base + 0x33c, 0xb);
offset = base + 0x344;
} else {
cp_ctx(ctx, base + 0x33c, 0xd);
offset = base + 0x344;
}
gr_def(ctx, offset + 0x0, 0x00120407);
gr_def(ctx, offset + 0x4, 0x05091507);
if (device->chipset == 0x84)
gr_def(ctx, offset + 0x8, 0x05100202);
else
gr_def(ctx, offset + 0x8, 0x05010202);
gr_def(ctx, offset + 0xc, 0x00030201);
if (device->chipset == 0xa3)
cp_ctx(ctx, base + 0x36c, 1);
cp_ctx(ctx, base + 0x400, 2);
gr_def(ctx, base + 0x404, 0x00000040);
cp_ctx(ctx, base + 0x40c, 2);
gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
gr_def(ctx, base + 0x410, 0x00141210);
if (device->chipset < 0xa0)
offset = base + 0x800;
else
offset = base + 0x500;
cp_ctx(ctx, offset, 6);
gr_def(ctx, offset + 0x0, 0x000001f0);
gr_def(ctx, offset + 0x4, 0x00000001);
gr_def(ctx, offset + 0x8, 0x00000003);
if (device->chipset == 0x50 || IS_NVAAF(device->chipset))
gr_def(ctx, offset + 0xc, 0x00008000);
gr_def(ctx, offset + 0x14, 0x00039e00);
cp_ctx(ctx, offset + 0x1c, 2);
if (device->chipset == 0x50)
gr_def(ctx, offset + 0x1c, 0x00000040);
else
gr_def(ctx, offset + 0x1c, 0x00000100);
gr_def(ctx, offset + 0x20, 0x00003800);
if (device->chipset >= 0xa0) {
cp_ctx(ctx, base + 0x54c, 2);
if (!IS_NVA3F(device->chipset))
gr_def(ctx, base + 0x54c, 0x003fe006);
else
gr_def(ctx, base + 0x54c, 0x003fe007);
gr_def(ctx, base + 0x550, 0x003fe000);
}
if (device->chipset < 0xa0)
offset = base + 0xa00;
else
offset = base + 0x680;
cp_ctx(ctx, offset, 1);
gr_def(ctx, offset, 0x00404040);
if (device->chipset < 0xa0)
offset = base + 0xe00;
else
offset = base + 0x700;
cp_ctx(ctx, offset, 2);
if (device->chipset < 0xa0)
gr_def(ctx, offset, 0x0077f005);
else if (device->chipset == 0xa5)
gr_def(ctx, offset, 0x6cf7f007);
else if (device->chipset == 0xa8)
gr_def(ctx, offset, 0x6cfff007);
else if (device->chipset == 0xac)
gr_def(ctx, offset, 0x0cfff007);
else
gr_def(ctx, offset, 0x0cf7f007);
if (device->chipset == 0x50)
gr_def(ctx, offset + 0x4, 0x00007fff);
else if (device->chipset < 0xa0)
gr_def(ctx, offset + 0x4, 0x003f7fff);
else
gr_def(ctx, offset + 0x4, 0x02bf7fff);
cp_ctx(ctx, offset + 0x2c, 1);
if (device->chipset == 0x50) {
cp_ctx(ctx, offset + 0x50, 9);
gr_def(ctx, offset + 0x54, 0x000003ff);
gr_def(ctx, offset + 0x58, 0x00000003);
gr_def(ctx, offset + 0x5c, 0x00000003);
gr_def(ctx, offset + 0x60, 0x000001ff);
gr_def(ctx, offset + 0x64, 0x0000001f);
gr_def(ctx, offset + 0x68, 0x0000000f);
gr_def(ctx, offset + 0x6c, 0x0000000f);
} else if (device->chipset < 0xa0) {
cp_ctx(ctx, offset + 0x50, 1);
cp_ctx(ctx, offset + 0x70, 1);
} else {
cp_ctx(ctx, offset + 0x50, 1);
cp_ctx(ctx, offset + 0x60, 5);
}
}
}
}
static void
dd_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
if (val && ctx->mode == NVKM_GRCTX_VALS) {
for (i = 0; i < num; i++)
nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
}
ctx->ctxvals_pos += num;
}
static void
nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int base, num;
base = ctx->ctxvals_pos;
/* tesla state */
dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */
dd_emit(ctx, 1, 0); /* 00000001 UNK135C */
/* SRC_TIC state */
dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */
dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */
dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */
dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */
dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */
if (device->chipset >= 0x94)
dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */
dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */
dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */
/* turing state */
dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */
dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */
dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */
dd_emit(ctx, 1, 1); /* 00000001 LANES32 */
dd_emit(ctx, 1, 0); /* 000000ff UNK370 */
dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */
dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */
dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */
dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */
dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */
dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */
dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */
dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */
dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */
if (IS_NVA3F(device->chipset))
dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */
dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */
dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */
dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */
dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */
dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */
dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */
/* compat 2d state */
if (device->chipset == 0x50) {
dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */
dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */
dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */
dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */
dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */
dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */
dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */
dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */
dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */
dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */
dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */
dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */
dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */
dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */
dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */
dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */
dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */
dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */
dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */
dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */
}
/* m2mf state */
dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */
dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */
dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */
dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */
dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */
dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */
dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */
dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */
dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */
dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */
/* more compat 2d state */
if (device->chipset == 0x50) {
dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */
dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */
dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */
dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */
dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */
dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */
dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */
dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */
dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */
dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */
dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */
}
/* tesla state */
dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */
dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */
dd_emit(ctx, 1, 0); /* 000000ff */
dd_emit(ctx, 1, 0); /* ffffffff */
dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */
dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */
dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */
dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */
dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */
dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */
if (IS_NVA3F(device->chipset)) {
dd_emit(ctx, 1, 0); /* ffffffff */
dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
} else {
dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
}
dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
if (device->chipset != 0x50)
dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */
dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */
if (device->chipset == 0x50) {
dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */
dd_emit(ctx, 1, 0); /* 00000001 */
} else {
dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */
dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */
dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */
dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */
dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */
}
dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */
dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */
dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */
dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */
dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */
dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */
dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */
dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */
dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */
dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */
dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */
dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */
if (device->chipset != 0x50)
dd_emit(ctx, 3, 0); /* 1, 1, 1 */
else
dd_emit(ctx, 2, 0); /* 1, 1 */
dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */
dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
if (IS_NVA3F(device->chipset)) {
dd_emit(ctx, 1, 3); /* 00000003 */
dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */
}
if (device->chipset != 0x50)
dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */
dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */
dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */
if (device->chipset != 0x50)
dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */
dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
if (device->chipset >= 0xa0)
dd_emit(ctx, 1, 0); /* ffffffff */
dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */
dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/
if (device->chipset != 0x50)
dd_emit(ctx, 8, 0); /* 00000001 */
if (device->chipset >= 0xa0) {
dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */
dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */
dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */
dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */
}
dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */
dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */
dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */
if (IS_NVA3F(device->chipset))
dd_emit(ctx, 1, 0); /* 00000001 */
dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */
if (device->chipset >= 0xa0)
dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
if (device->chipset >= 0xa0)
dd_emit(ctx, 1, 0); /* 00000003 */
dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */
dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */
dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */
dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */
dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */
if (device->chipset != 0x50) {
dd_emit(ctx, 1, 0xe00); /* 7fff */
dd_emit(ctx, 1, 0x1000); /* 7fff */
dd_emit(ctx, 1, 0x1e00); /* 7fff */
}
dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */
dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */
dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */
dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
dd_emit(ctx, 1, 1); /* 00000001 */
dd_emit(ctx, 1, 0); /* 00000001 */
dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
if (IS_NVA3F(device->chipset))
dd_emit(ctx, 1, 0x200);
dd_emit(ctx, 1, 0); /* 00000001 */
if (device->chipset < 0xa0) {
dd_emit(ctx, 1, 1); /* 00000001 */
dd_emit(ctx, 1, 0x70); /* 000000ff */
dd_emit(ctx, 1, 0x80); /* 000000ff */
dd_emit(ctx, 1, 0); /* 000000ff */
dd_emit(ctx, 1, 0); /* 00000001 */
dd_emit(ctx, 1, 1); /* 00000001 */
dd_emit(ctx, 1, 0x70); /* 000000ff */
dd_emit(ctx, 1, 0x80); /* 000000ff */
dd_emit(ctx, 1, 0); /* 000000ff */
} else {
dd_emit(ctx, 1, 1); /* 00000001 */
dd_emit(ctx, 1, 0xf0); /* 000000ff */
dd_emit(ctx, 1, 0xff); /* 000000ff */
dd_emit(ctx, 1, 0); /* 000000ff */
dd_emit(ctx, 1, 0); /* 00000001 */
dd_emit(ctx, 1, 1); /* 00000001 */
dd_emit(ctx, 1, 0xf0); /* 000000ff */
dd_emit(ctx, 1, 0xff); /* 000000ff */
dd_emit(ctx, 1, 0); /* 000000ff */
dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */
}
/* eng2d state */
dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */
dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */
dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */
dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */
dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */
dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */
dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */
dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */
dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */
dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */
dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */
dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */
dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */
dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */
dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */
dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */
num = ctx->ctxvals_pos - base;
ctx->ctxvals_pos = base;
if (IS_NVA3F(device->chipset))
cp_ctx(ctx, 0x404800, num);
else
cp_ctx(ctx, 0x405400, num);
}
/*
* xfer areas. These are a pain.
*
* There are 2 xfer areas: the first one is big and contains all sorts of
* stuff, the second is small and contains some per-TP context.
*
* Each area is split into 8 "strands". The areas, when saved to grctx,
* are made of 8-word blocks. Each block contains a single word from
* each strand. The strands are independent of each other, their
* addresses are unrelated to each other, and data in them is closely
* packed together. The strand layout varies a bit between cards: here
* and there, a single word is thrown out in the middle and the whole
* strand is offset by a bit from corresponding one on another chipset.
* For this reason, addresses of stuff in strands are almost useless.
* Knowing sequence of stuff and size of gaps between them is much more
* useful, and that's how we build the strands in our generator.
*
* NVA0 takes this mess to a whole new level by cutting the old strands
* into a few dozen pieces [known as genes], rearranging them randomly,
* and putting them back together to make new strands. Hopefully these
* genes correspond more or less directly to the same PGRAPH subunits
* as in 400040 register.
*
* The most common value in default context is 0, and when the genes
* are separated by 0's, gene bounduaries are quite speculative...
* some of them can be clearly deduced, others can be guessed, and yet
* others won't be resolved without figuring out the real meaning of
* given ctxval. For the same reason, ending point of each strand
* is unknown. Except for strand 0, which is the longest strand and
* its end corresponds to end of the whole xfer.
*
* An unsolved mystery is the seek instruction: it takes an argument
* in bits 8-18, and that argument is clearly the place in strands to
* seek to... but the offsets don't seem to correspond to offsets as
* seen in grctx. Perhaps there's another, real, not randomly-changing
* addressing in strands, and the xfer insn just happens to skip over
* the unused bits? NV10-NV30 PIPE comes to mind...
*
* As far as I know, there's no way to access the xfer areas directly
* without the help of ctxprog.
*/
static void
xf_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
if (val && ctx->mode == NVKM_GRCTX_VALS) {
for (i = 0; i < num; i++)
nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
}
ctx->ctxvals_pos += num << 3;
}
/* Gene declarations... */
static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx);
static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx);
static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx);
static void
nv50_gr_construct_xfer1(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
int offset;
int size = 0;
u32 units = nvkm_rd32(device, 0x1540);
offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
ctx->ctxvals_base = offset;
if (device->chipset < 0xa0) {
/* Strand 0 */
ctx->ctxvals_pos = offset;
nv50_gr_construct_gene_dispatch(ctx);
nv50_gr_construct_gene_m2mf(ctx);
nv50_gr_construct_gene_unk24xx(ctx);
nv50_gr_construct_gene_clipid(ctx);
nv50_gr_construct_gene_zcull(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1 */
ctx->ctxvals_pos = offset + 0x1;
nv50_gr_construct_gene_vfetch(ctx);
nv50_gr_construct_gene_eng2d(ctx);
nv50_gr_construct_gene_csched(ctx);
nv50_gr_construct_gene_ropm1(ctx);
nv50_gr_construct_gene_ropm2(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2 */
ctx->ctxvals_pos = offset + 0x2;
nv50_gr_construct_gene_ccache(ctx);
nv50_gr_construct_gene_unk1cxx(ctx);
nv50_gr_construct_gene_strmout(ctx);
nv50_gr_construct_gene_unk14xx(ctx);
nv50_gr_construct_gene_unk10xx(ctx);
nv50_gr_construct_gene_unk34xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 3: per-ROP group state */
ctx->ctxvals_pos = offset + 3;
for (i = 0; i < 6; i++)
if (units & (1 << (i + 16)))
nv50_gr_construct_gene_ropc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strands 4-7: per-TP state */
for (i = 0; i < 4; i++) {
ctx->ctxvals_pos = offset + 4 + i;
if (units & (1 << (2 * i)))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << (2 * i + 1)))
nv50_gr_construct_xfer_tp(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
} else {
/* Strand 0 */
ctx->ctxvals_pos = offset;
nv50_gr_construct_gene_dispatch(ctx);
nv50_gr_construct_gene_m2mf(ctx);
nv50_gr_construct_gene_unk34xx(ctx);
nv50_gr_construct_gene_csched(ctx);
nv50_gr_construct_gene_unk1cxx(ctx);
nv50_gr_construct_gene_strmout(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1 */
ctx->ctxvals_pos = offset + 1;
nv50_gr_construct_gene_unk10xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2 */
ctx->ctxvals_pos = offset + 2;
if (device->chipset == 0xa0)
nv50_gr_construct_gene_unk14xx(ctx);
nv50_gr_construct_gene_unk24xx(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 3 */
ctx->ctxvals_pos = offset + 3;
nv50_gr_construct_gene_vfetch(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 4 */
ctx->ctxvals_pos = offset + 4;
nv50_gr_construct_gene_ccache(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 5 */
ctx->ctxvals_pos = offset + 5;
nv50_gr_construct_gene_ropm2(ctx);
nv50_gr_construct_gene_ropm1(ctx);
/* per-ROP context */
for (i = 0; i < 8; i++)
if (units & (1<<(i+16)))
nv50_gr_construct_gene_ropc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 6 */
ctx->ctxvals_pos = offset + 6;
nv50_gr_construct_gene_zcull(ctx);
nv50_gr_construct_gene_clipid(ctx);
nv50_gr_construct_gene_eng2d(ctx);
if (units & (1 << 0))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 1))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 2))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 3))
nv50_gr_construct_xfer_tp(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 7 */
ctx->ctxvals_pos = offset + 7;
if (device->chipset == 0xa0) {
if (units & (1 << 4))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 5))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 6))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 7))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 8))
nv50_gr_construct_xfer_tp(ctx);
if (units & (1 << 9))
nv50_gr_construct_xfer_tp(ctx);
} else {
nv50_gr_construct_gene_unk14xx(ctx);
}
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
ctx->ctxvals_pos = offset + size * 8;
ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
cp_lsr (ctx, offset);
cp_out (ctx, CP_SET_XFER_POINTER);
cp_lsr (ctx, size);
cp_out (ctx, CP_SEEK_1);
cp_out (ctx, CP_XFER_1);
cp_wait(ctx, XFER, BUSY);
}
/*
* non-trivial demagiced parts of ctx init go here
*/
static void
nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx)
{
/* start of strand 0 */
struct nvkm_device *device = ctx->device;
/* SEEK */
if (device->chipset == 0x50)
xf_emit(ctx, 5, 0);
else if (!IS_NVA3F(device->chipset))
xf_emit(ctx, 6, 0);
else
xf_emit(ctx, 4, 0);
/* SEEK */
/* the PGRAPH's internal FIFO */
if (device->chipset == 0x50)
xf_emit(ctx, 8*3, 0);
else
xf_emit(ctx, 0x100*3, 0);
/* and another bonus slot?!? */
xf_emit(ctx, 3, 0);
/* and YET ANOTHER bonus slot? */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 3, 0);
/* SEEK */
/* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */
xf_emit(ctx, 9, 0);
/* SEEK */
xf_emit(ctx, 9, 0);
/* SEEK */
xf_emit(ctx, 9, 0);
/* SEEK */
xf_emit(ctx, 9, 0);
/* SEEK */
if (device->chipset < 0x90)
xf_emit(ctx, 4, 0);
/* SEEK */
xf_emit(ctx, 2, 0);
/* SEEK */
xf_emit(ctx, 6*2, 0);
xf_emit(ctx, 2, 0);
/* SEEK */
xf_emit(ctx, 2, 0);
/* SEEK */
xf_emit(ctx, 6*2, 0);
xf_emit(ctx, 2, 0);
/* SEEK */
if (device->chipset == 0x50)
xf_emit(ctx, 0x1c, 0);
else if (device->chipset < 0xa0)
xf_emit(ctx, 0x1e, 0);
else
xf_emit(ctx, 0x22, 0);
/* SEEK */
xf_emit(ctx, 0x15, 0);
}
static void
nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx)
{
/* Strand 0, right after dispatch */
struct nvkm_device *device = ctx->device;
int smallm2mf = 0;
if (device->chipset < 0x92 || device->chipset == 0x98)
smallm2mf = 1;
/* SEEK */
xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */
xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */
xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */
xf_emit (ctx, 1, 0); /* OFFSET_IN */
xf_emit (ctx, 1, 0); /* OFFSET_OUT */
xf_emit (ctx, 1, 0); /* PITCH_IN */
xf_emit (ctx, 1, 0); /* PITCH_OUT */
xf_emit (ctx, 1, 0); /* LINE_LENGTH */
xf_emit (ctx, 1, 0); /* LINE_COUNT */
xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */
xf_emit (ctx, 1, 1); /* LINEAR_IN */
xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */
xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */
xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */
xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */
xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */
xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */
xf_emit (ctx, 1, 1); /* LINEAR_OUT */
xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */
xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */
xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */
xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */
xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */
xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */
xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */
xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */
/* SEEK */
if (smallm2mf)
xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */
else
xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */
xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */
/* SEEK */
if (smallm2mf)
xf_emit(ctx, 0x400, 0); /* ffffffff */
else
xf_emit(ctx, 0x800, 0); /* ffffffff */
xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */
/* SEEK */
xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */
xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */
}
static void
nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* RO */
xf_emit(ctx, 0x800, 0); /* ffffffff */
switch (device->chipset) {
case 0x50:
case 0x92:
case 0xa0:
xf_emit(ctx, 0x2b, 0);
break;
case 0x84:
xf_emit(ctx, 0x29, 0);
break;
case 0x94:
case 0x96:
case 0xa3:
xf_emit(ctx, 0x27, 0);
break;
case 0x86:
case 0x98:
case 0xa5:
case 0xa8:
case 0xaa:
case 0xac:
case 0xaf:
xf_emit(ctx, 0x25, 0);
break;
}
/* CB bindings, 0x80 of them. first word is address >> 8, second is
* size >> 4 | valid << 24 */
xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */
xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */
xf_emit(ctx, 1, 0); /* 0 */
xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */
xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */
xf_emit(ctx, 4, 0); /* RO */
xf_emit(ctx, 0x100, 0); /* ffffffff */
xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */
xf_emit(ctx, 8, 0); /* ffffffff */
xf_emit(ctx, 4, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 3 */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */
xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */
xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */
xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */
xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */
xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */
}
static void
nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0x3ff);
else
xf_emit(ctx, 1, 0x7ff); /* 000007ff */
xf_emit(ctx, 1, 0); /* 111/113 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
for (i = 0; i < 8; i++) {
switch (device->chipset) {
case 0x50:
case 0x86:
case 0x98:
case 0xaa:
case 0xac:
xf_emit(ctx, 0xa0, 0); /* ffffffff */
break;
case 0x84:
case 0x92:
case 0x94:
case 0x96:
xf_emit(ctx, 0x120, 0);
break;
case 0xa5:
case 0xa8:
xf_emit(ctx, 0x100, 0); /* ffffffff */
break;
case 0xa0:
case 0xa3:
case 0xaf:
xf_emit(ctx, 0x400, 0); /* ffffffff */
break;
}
xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */
xf_emit(ctx, 4, 0); /* ffffffff */
}
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */
xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
}
static void
nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */
xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */
xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0x0fac6881);
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 1);
xf_emit(ctx, 3, 0);
}
}
static void
nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
if (device->chipset != 0x50) {
xf_emit(ctx, 5, 0); /* ffffffff */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 000003ff */
xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 2, 4); /* 7f, ff */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
}
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 3ff */
xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0); /* 0000000f */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
else
xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */
xf_emit(ctx, 3, 0); /* f, 0, 0 */
xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */
xf_emit(ctx, 3, 0); /* f, 0, 0 */
xf_emit(ctx, 3, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
if (device->chipset != 0x50) {
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 000003ff */
}
xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */
xf_emit(ctx, 1, 0); /* f */
xf_emit(ctx, 1, 0); /* 0? */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 003fffff */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
xf_emit(ctx, 1, 0); /* 0000000f */
}
static void
nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
xf_emit(ctx, 1, 0); /* 0000ffff */
xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */
xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
xf_emit(ctx, 1, 0); /* 00000007 */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
/* SEEK */
xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */
}
static void
nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx)
{
/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */
/* SEEK */
xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */
xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */
xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */
xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */
xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */
xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */
xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */
}
static void
nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
/* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
/* SEEK */
xf_emit(ctx, 0x33, 0);
/* SEEK */
xf_emit(ctx, 2, 0);
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
/* SEEK */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 4, 0); /* RO */
xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
xf_emit(ctx, 1, 0); /* 1ff */
xf_emit(ctx, 8, 0); /* 0? */
xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
xf_emit(ctx, 4, 0); /* RO */
xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
xf_emit(ctx, 1, 0); /* 1ff */
xf_emit(ctx, 8, 0); /* 0? */
xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
} else {
xf_emit(ctx, 0xc, 0); /* RO */
/* SEEK */
xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
xf_emit(ctx, 1, 0); /* 1ff */
xf_emit(ctx, 8, 0); /* 0? */
/* SEEK */
xf_emit(ctx, 0xc, 0); /* RO */
/* SEEK */
xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
xf_emit(ctx, 1, 0); /* 1ff */
xf_emit(ctx, 8, 0); /* 0? */
}
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 1); /* 00000001 */
/* SEEK */
if (device->chipset >= 0xa0)
xf_emit(ctx, 2, 4); /* 000000ff */
xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 1); /* 00000001 */
for (i = 0; i < 10; i++) {
/* SEEK */
xf_emit(ctx, 0x40, 0); /* ffffffff */
xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */
xf_emit(ctx, 0x10, 0); /* ffffffff */
}
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */
xf_emit(ctx, 1, 1); /* 00000001 */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 000003ff */
}
static void
nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int acnt = 0x10, rep, i;
/* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
if (IS_NVA3F(device->chipset))
acnt = 0x20;
/* SEEK */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */
xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */
}
xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */
xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */
xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */
xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */
xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */
xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */
xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
/* SEEK */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0xb, 0); /* RO */
else if (device->chipset >= 0xa0)
xf_emit(ctx, 0x9, 0); /* RO */
else
xf_emit(ctx, 0x8, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */
xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
/* SEEK */
xf_emit(ctx, 0xc, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0); /* 7f/ff */
xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */
xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */
else
xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */
if (device->chipset == 0xa8)
xf_emit(ctx, 1, 0x1e00); /* 7fff */
/* SEEK */
xf_emit(ctx, 0xc, 0); /* RO or close */
/* SEEK */
xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
if (device->chipset > 0x50 && device->chipset < 0xa0)
xf_emit(ctx, 2, 0); /* ffffffff */
else
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */
/* SEEK */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 0x10, 0); /* 0? */
xf_emit(ctx, 2, 0); /* weird... */
xf_emit(ctx, 2, 0); /* RO */
} else {
xf_emit(ctx, 8, 0); /* 0? */
xf_emit(ctx, 1, 0); /* weird... */
xf_emit(ctx, 2, 0); /* RO */
}
/* SEEK */
xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */
xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */
xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */
/* SEEK */
xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
xf_emit(ctx, 1, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
xf_emit(ctx, 1, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* RO */
xf_emit(ctx, 2, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */
xf_emit(ctx, 1, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */
/* SEEK */
xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */
xf_emit(ctx, 3, 0); /* f/1f */
/* SEEK */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, acnt, 0); /* f */
xf_emit(ctx, 3, 0); /* f/1f */
}
/* SEEK */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 2, 0); /* RO */
else
xf_emit(ctx, 5, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */
/* SEEK */
if (device->chipset < 0xa0) {
xf_emit(ctx, 0x41, 0); /* RO */
/* SEEK */
xf_emit(ctx, 0x11, 0); /* RO */
} else if (!IS_NVA3F(device->chipset))
xf_emit(ctx, 0x50, 0); /* RO */
else
xf_emit(ctx, 0x58, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, 1, 1); /* 1 UNK0DEC */
/* SEEK */
xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */
xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */
/* SEEK */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0x1d, 0); /* RO */
else
xf_emit(ctx, 0x16, 0); /* RO */
/* SEEK */
xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
/* SEEK */
if (device->chipset < 0xa0)
xf_emit(ctx, 8, 0); /* RO */
else if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0xc, 0); /* RO */
else
xf_emit(ctx, 7, 0); /* RO */
/* SEEK */
xf_emit(ctx, 0xa, 0); /* RO */
if (device->chipset == 0xa0)
rep = 0xc;
else
rep = 4;
for (i = 0; i < rep; i++) {
/* SEEK */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0x20, 0); /* ffffffff */
xf_emit(ctx, 0x200, 0); /* ffffffff */
xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */
xf_emit(ctx, 4, 0); /* ffffffff */
}
/* SEEK */
xf_emit(ctx, 1, 0); /* 113/111 */
xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */
xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
/* SEEK */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 7, 0); /* weird... */
else
xf_emit(ctx, 5, 0); /* weird... */
}
static void
nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */
xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */
xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */
if (device->chipset < 0xa0) {
/* this is useless on everything but the original NV50,
* guess they forgot to nuke it. Or just didn't bother. */
xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */
xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */
xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */
}
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */
xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */
xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */
xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */
xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */
xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */
xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */
xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */
xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */
xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */
xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */
xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */
xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */
xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */
xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */
xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */
xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */
xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */
xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */
xf_emit(ctx, 1, 0); /* 00000001 UNK888 */
xf_emit(ctx, 1, 4); /* 0000003f UNK884 */
xf_emit(ctx, 1, 0); /* 00000007 UNK880 */
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */
xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */
xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */
xf_emit(ctx, 1, 0); /* 00000001 UNK260 */
xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */
/* SEEK */
xf_emit(ctx, 0x10, 0);
/* SEEK */
xf_emit(ctx, 0x27, 0);
}
static void
nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 0); /* 000003ff */
/* SEEK */
xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */
xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */
xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */
xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */
xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */
xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */
xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
/* SEEK */
xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */
switch (device->chipset) {
case 0x50:
case 0x92:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0x80, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */
break;
case 0x84:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0x60, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
break;
case 0x94:
case 0x96:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0x40, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */
break;
case 0x86:
case 0x98:
xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
xf_emit(ctx, 0x10, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
break;
case 0xa0:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0xf0, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */
break;
case 0xa3:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0x60, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
break;
case 0xa5:
case 0xaf:
xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
xf_emit(ctx, 0x30, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */
break;
case 0xaa:
xf_emit(ctx, 0x12, 0);
break;
case 0xa8:
case 0xac:
xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
xf_emit(ctx, 0x10, 0); /* fff */
xf_emit(ctx, 2, 0); /* ff, fff */
xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
break;
}
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 0); /* 00000000 */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 0000001f */
xf_emit(ctx, 4, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 4, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 000000ff */
}
static void
nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */
xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */
xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */
else if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */
xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */
xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */
if (device->chipset != 0x50) {
xf_emit(ctx, 1, 0); /* 3ff */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */
}
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
if (device->chipset < 0xa0)
xf_emit(ctx, 0x1c, 0); /* RO */
else if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0x9, 0);
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
if (device->chipset != 0x50) {
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
xf_emit(ctx, 1, 0); /* 3ff */
}
/* XXX: the following block could belong either to unk1cxx, or
* to STRMOUT. Rather hard to tell. */
if (device->chipset < 0xa0)
xf_emit(ctx, 0x25, 0);
else
xf_emit(ctx, 0x3b, 0);
}
static void
nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
}
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
else
xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
/* SEEK */
xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */
xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */
xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
}
xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */
xf_emit(ctx, 2, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
/* SEEK */
xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 0); /* 00000000? */
xf_emit(ctx, 2, 0); /* ffffffff */
}
static void
nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* 000003ff */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
}
static void
nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
/* SEEK */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 2, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 0); /* 7 */
/* SEEK */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* 00000007 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
}
static void
nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int magic2;
if (device->chipset == 0x50) {
magic2 = 0x00003e60;
} else if (!IS_NVA3F(device->chipset)) {
magic2 = 0x001ffe67;
} else {
magic2 = 0x00087e67;
}
xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset))
xf_emit(ctx, 1, 0x15); /* 000000ff */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) {
xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */
xf_emit(ctx, 1, 4); /* 7 */
xf_emit(ctx, 1, 0x400); /* fffffff */
xf_emit(ctx, 1, 0x300); /* ffff */
xf_emit(ctx, 1, 0x1001); /* 1fff */
if (device->chipset != 0xa0) {
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */
else
xf_emit(ctx, 1, 0x15); /* ff */
}
}
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 2, 0);
xf_emit(ctx, 1, 0x1001);
xf_emit(ctx, 0xb, 0);
} else {
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
}
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, 0x11); /* 3f/7f */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
if (device->chipset != 0x50) {
xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
xf_emit(ctx, 1, 0); /* 000000ff */
}
xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */
xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
xf_emit(ctx, 2, 0); /* 00000001 */
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* 0000000f */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 2, 0); /* 00000001 */
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 000003ff */
} else if (device->chipset >= 0xa0) {
xf_emit(ctx, 2, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 2, 0); /* 00000001 */
} else {
xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
}
xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */
xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */
xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */
if (device->chipset >= 0xa0)
xf_emit(ctx, 2, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 000003ff */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
}
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */
xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */
xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */
xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */
xf_emit(ctx, 1, 0); /* 000000ff ROP */
xf_emit(ctx, 1, 0); /* ffffffff BETA1 */
xf_emit(ctx, 1, 0); /* ffffffff BETA4 */
xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */
}
static void
nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int magic3;
switch (device->chipset) {
case 0x50:
magic3 = 0x1000;
break;
case 0x86:
case 0x98:
case 0xa8:
case 0xaa:
case 0xac:
case 0xaf:
magic3 = 0x1e00;
break;
default:
magic3 = 0;
}
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0x1f, 0); /* ffffffff */
else if (device->chipset >= 0xa0)
xf_emit(ctx, 0x0f, 0); /* ffffffff */
else
xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */
xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */
xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0x03020100); /* ffffffff */
else
xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */
xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
if (magic3)
xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */
xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 111/113 */
xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */
xf_emit(ctx, 1, 0); /* 0000001f */
xf_emit(ctx, 1, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */
xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
if (magic3)
xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */
xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 111/113 */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */
xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
xf_emit(ctx, 1, 0); /* 111/113 */
if (device->chipset == 0x94 || device->chipset == 0x96)
xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
else if (device->chipset < 0xa0)
xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
else if (!IS_NVA3F(device->chipset))
xf_emit(ctx, 0x210, 0); /* ffffffff */
else
xf_emit(ctx, 0x410, 0); /* ffffffff */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
}
static void
nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int magic1, magic2;
if (device->chipset == 0x50) {
magic1 = 0x3ff;
magic2 = 0x00003e60;
} else if (!IS_NVA3F(device->chipset)) {
magic1 = 0x7ff;
magic2 = 0x001ffe67;
} else {
magic1 = 0x7ff;
magic2 = 0x00087e67;
}
xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */
xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */
xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
xf_emit(ctx, 1, 0); /* 7 */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */
xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */
xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */
xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */
} else if (device->chipset >= 0xa0) {
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */
xf_emit(ctx, 1, 0); /* 00000003 */
} else {
xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
}
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */
xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
}
xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
xf_emit(ctx, 1, 0); /* 7 */
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */
xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0); /* ff */
else
xf_emit(ctx, 3, 0); /* 1, 7, 3ff */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */
xf_emit(ctx, 1, 0); /* 7 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */
xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */
xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */
xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */
xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */
xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */
xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */
xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
xf_emit(ctx, 1, 0); /* 0000ffff */
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
xf_emit(ctx, 1, 0); /* 00000007 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 2, 0); /* ffff, ff/3ff */
xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */
xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */
xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */
xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */
xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 0); /* 00000001 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
xf_emit(ctx, 1, 0); /* 7 */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
}
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0x0fac6881); /* fffffff */
xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */
}
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */
xf_emit(ctx, 1, 0xfac6881); /* fffffff */
xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */
xf_emit(ctx, 1, 4); /* 7 */
xf_emit(ctx, 1, 0); /* 1 */
xf_emit(ctx, 2, 1); /* 1 */
xf_emit(ctx, 2, 0); /* 7, f */
xf_emit(ctx, 1, 1); /* 1 */
xf_emit(ctx, 1, 0); /* 7/f */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 0x9, 0); /* 1 */
else
xf_emit(ctx, 0x8, 0); /* 1 */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 8, 1); /* 1 */
xf_emit(ctx, 1, 0x11); /* 7f */
xf_emit(ctx, 7, 0); /* 7f */
xf_emit(ctx, 1, 0xfac6881); /* fffffff */
xf_emit(ctx, 1, 0xf); /* f */
xf_emit(ctx, 7, 0); /* f */
xf_emit(ctx, 1, 0x11); /* 7f */
xf_emit(ctx, 1, 1); /* 1 */
xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
}
}
}
static void
nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 3 */
xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */
xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */
xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */
xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */
if (device->chipset == 0x50)
xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */
else
xf_emit(ctx, 2, 0); /* 3ff, 1 */
xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */
xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */
xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */
xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */
xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */
xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */
xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */
xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */
if (device->chipset == 0x50) {
xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */
xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */
xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */
} else if (!IS_NVAAF(device->chipset)) {
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* 000003ff */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* 000003ff */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */
xf_emit(ctx, 1, 0); /* 00000003 */
xf_emit(ctx, 1, 0); /* 000003ff */
} else {
xf_emit(ctx, 0x6, 0);
}
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */
}
static void
nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
xf_emit(ctx, 1, 0); /* ffff0ff3 */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */
xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */
xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */
xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */
xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
}
static void
nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
if (device->chipset < 0xa0) {
nv50_gr_construct_xfer_unk84xx(ctx);
nv50_gr_construct_xfer_tprop(ctx);
nv50_gr_construct_xfer_tex(ctx);
nv50_gr_construct_xfer_unk8cxx(ctx);
} else {
nv50_gr_construct_xfer_tex(ctx);
nv50_gr_construct_xfer_tprop(ctx);
nv50_gr_construct_xfer_unk8cxx(ctx);
nv50_gr_construct_xfer_unk84xx(ctx);
}
}
static void
nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i, mpcnt = 2;
switch (device->chipset) {
case 0x98:
case 0xaa:
mpcnt = 1;
break;
case 0x50:
case 0x84:
case 0x86:
case 0x92:
case 0x94:
case 0x96:
case 0xa8:
case 0xac:
mpcnt = 2;
break;
case 0xa0:
case 0xa3:
case 0xa5:
case 0xaf:
mpcnt = 3;
break;
}
for (i = 0; i < mpcnt; i++) {
xf_emit(ctx, 1, 0); /* ff */
xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */
xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */
xf_emit(ctx, 1, 0x04000400); /* ffffffff */
if (device->chipset >= 0xa0)
xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */
xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) {
xf_emit(ctx, 1, 0xe00); /* 7fff */
xf_emit(ctx, 1, 0x1e00); /* 7fff */
}
xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */
xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
if (device->chipset == 0x50)
xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */
xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */
xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
if (IS_NVAAF(device->chipset))
xf_emit(ctx, 0xb, 0); /* RO */
else if (device->chipset >= 0xa0)
xf_emit(ctx, 0xc, 0); /* RO */
else
xf_emit(ctx, 0xa, 0); /* RO */
}
xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 0); /* ff/3ff */
if (device->chipset >= 0xa0) {
xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */
}
xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */
xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */
xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
xf_emit(ctx, 1, 0); /* ff/3ff */
xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */
xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */
xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */
xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
xf_emit(ctx, 1, 0); /* 00000007 */
xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */
xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
if (IS_NVA3F(device->chipset))
xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */
xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
if (IS_NVA3F(device->chipset)) {
xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
}
xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
/* XXX: demagic this part some day */
if (device->chipset == 0x50)
xf_emit(ctx, 0x3a0, 0);
else if (device->chipset < 0x94)
xf_emit(ctx, 0x3a2, 0);
else if (device->chipset == 0x98 || device->chipset == 0xaa)
xf_emit(ctx, 0x39f, 0);
else
xf_emit(ctx, 0x3a3, 0);
xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
xf_emit(ctx, 1, 0); /* 7 OPERATION */
xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */
xf_emit(ctx, 0x2d, 0);
}
static void
nv50_gr_construct_xfer2(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
u32 offset;
u32 units = nvkm_rd32(device, 0x1540);
int size = 0;
offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
if (device->chipset < 0xa0) {
for (i = 0; i < 8; i++) {
ctx->ctxvals_pos = offset + i;
/* that little bugger belongs to csched. No idea
* what it's doing here. */
if (i == 0)
xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
if (units & (1 << i))
nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
} else {
/* Strand 0: TPs 0, 1 */
ctx->ctxvals_pos = offset;
/* that little bugger belongs to csched. No idea
* what it's doing here. */
xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
if (units & (1 << 0))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 1))
nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 1: TPs 2, 3 */
ctx->ctxvals_pos = offset + 1;
if (units & (1 << 2))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 3))
nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 2: TPs 4, 5, 6 */
ctx->ctxvals_pos = offset + 2;
if (units & (1 << 4))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 5))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 6))
nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
/* Strand 3: TPs 7, 8, 9 */
ctx->ctxvals_pos = offset + 3;
if (units & (1 << 7))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 8))
nv50_gr_construct_xfer_mpc(ctx);
if (units & (1 << 9))
nv50_gr_construct_xfer_mpc(ctx);
if ((ctx->ctxvals_pos-offset)/8 > size)
size = (ctx->ctxvals_pos-offset)/8;
}
ctx->ctxvals_pos = offset + size * 8;
ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
cp_lsr (ctx, offset);
cp_out (ctx, CP_SET_XFER_POINTER);
cp_lsr (ctx, size);
cp_out (ctx, CP_SEEK_2);
cp_out (ctx, CP_XFER_2);
cp_wait(ctx, XFER, BUSY);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <core/firmware.h>
#include <subdev/acr.h>
#include <nvfw/flcn.h>
#include <nvif/class.h>
int
gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n");
return -ENODEV;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static void
gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct flcn_bl_dmem_desc_v1 hdr;
nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
hdr.code_dma_base = hdr.code_dma_base + adjust;
hdr.data_dma_base = hdr.data_dma_base + adjust;
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
}
static void
gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
const u64 base = lsfw->offset.img + lsfw->app_start_offset;
const u64 code = base + lsfw->app_resident_code_offset;
const u64 data = base + lsfw->app_resident_data_offset;
const struct flcn_bl_dmem_desc_v1 hdr = {
.ctx_dma = FALCON_DMAIDX_UCODE,
.code_dma_base = code,
.non_sec_code_off = lsfw->app_resident_code_offset,
.non_sec_code_size = lsfw->app_resident_code_size,
.code_entry_point = lsfw->app_imem_entry,
.data_dma_base = data,
.data_size = lsfw->app_resident_data_size,
};
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
}
const struct nvkm_acr_lsf_func
gm200_gr_gpccs_acr = {
.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
.bld_write = gm200_gr_acr_bld_write,
.bld_patch = gm200_gr_acr_bld_patch,
};
const struct nvkm_acr_lsf_func
gm200_gr_fecs_acr = {
.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
.bld_write = gm200_gr_acr_bld_write,
.bld_patch = gm200_gr_acr_bld_patch,
};
int
gm200_gr_rops(struct gf100_gr *gr)
{
return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
}
void
gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x405848, 0xc0000000);
nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001);
}
void
gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
}
void
gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
nvkm_wr32(device, 0x418890, 0x00000000);
nvkm_wr32(device, 0x418894, 0x00000000);
nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
}
static void
gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x12006c);
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
static u8
gm200_gr_tile_map_6_24[] = {
0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2,
};
static u8
gm200_gr_tile_map_4_16[] = {
0, 1, 2, 3, 2, 3, 0, 1, 3, 0, 1, 2, 1, 2, 3, 0,
};
static u8
gm200_gr_tile_map_2_8[] = {
0, 1, 1, 0, 0, 1, 1, 0,
};
int
gm200_gr_oneinit_sm_id(struct gf100_gr *gr)
{
/*XXX: There's a different algorithm here I've not yet figured out. */
return gf100_gr_oneinit_sm_id(gr);
}
void
gm200_gr_oneinit_tiles(struct gf100_gr *gr)
{
/*XXX: Not sure what this is about. The algorithm from NVGPU
* seems to work for all boards I tried from earlier (and
* later) GPUs except in these specific configurations.
*
* Let's just hardcode them for now.
*/
if (gr->gpc_nr == 2 && gr->tpc_total == 8) {
memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
gr->screen_tile_row_offset = 1;
} else
if (gr->gpc_nr == 4 && gr->tpc_total == 16) {
memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
gr->screen_tile_row_offset = 4;
} else
if (gr->gpc_nr == 6 && gr->tpc_total == 24) {
memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);
gr->screen_tile_row_offset = 5;
} else {
gf100_gr_oneinit_tiles(gr);
}
}
static const struct gf100_gr_func
gm200_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_bios = gm107_gr_init_bios,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gm107_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gm107_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.tpc_nr = 4,
.ppc_nr = 2,
.grctx = &gm200_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, MAXWELL_B, &gf100_fermi },
{ -1, -1, MAXWELL_COMPUTE_B },
{}
}
};
int
gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
int ret;
ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
&gr->fecs.falcon,
NVKM_ACR_LSF_FECS,
"gr/fecs_", ver, fwif->fecs);
if (ret)
return ret;
ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
&gr->gpccs.falcon,
NVKM_ACR_LSF_GPCCS,
"gr/gpccs_", ver,
fwif->gpccs);
if (ret)
return ret;
gr->firmware = true;
return gk20a_gr_load_sw(gr, "gr/", ver);
}
MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gm200_gr_fwif[] = {
{ 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <nvif/class.h>
static const struct nvkm_gr_func
gt200_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{ -1, -1, GT200_TESLA, &nv50_gr_object },
{}
}
};
int
gt200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(>200_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c |
/*
* Copyright 2016 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
void
gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const int znum = zbc - 1;
const u32 zoff = znum * 4;
if (gr->zbc_stencil[zbc].format)
nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds);
nvkm_mask(device, 0x418198 + ((znum / 4) * 4),
0x0000007f << ((znum % 4) * 7),
gr->zbc_stencil[zbc].format << ((znum % 4) * 7));
}
int
gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_depth_min; i <= ltc->zbc_depth_max; i++) {
if (gr->zbc_stencil[i].format) {
if (gr->zbc_stencil[i].format != format)
continue;
if (gr->zbc_stencil[i].ds != ds)
continue;
if (gr->zbc_stencil[i].l2 != l2) {
WARN_ON(1);
return -EINVAL;
}
return i;
} else {
zbc = (zbc < 0) ? i : zbc;
}
}
if (zbc < 0)
return zbc;
gr->zbc_stencil[zbc].format = format;
gr->zbc_stencil[zbc].ds = ds;
gr->zbc_stencil[zbc].l2 = l2;
nvkm_ltc_zbc_stencil_get(ltc, zbc, l2);
gr->func->zbc->clear_stencil(gr, zbc);
return zbc;
}
const struct gf100_gr_func_zbc
gp102_gr_zbc = {
.clear_color = gp100_gr_zbc_clear_color,
.clear_depth = gp100_gr_zbc_clear_depth,
.stencil_get = gp102_gr_zbc_stencil_get,
.clear_stencil = gp102_gr_zbc_clear_stencil,
};
void
gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 mask = 0, data, gpc;
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f;
mask |= data << (gpc * 4);
}
nvkm_wr32(device, 0x4181d0, mask);
}
static const struct gf100_gr_func
gp102_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gp100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 5,
.ppc_nr = 3,
.grctx = &gp102_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, PASCAL_B, &gf100_fermi },
{ -1, -1, PASCAL_COMPUTE_B },
{}
}
};
MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gp102_gr_fwif[] = {
{ 0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp102_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include <subdev/acr.h>
#include <nvfw/flcn.h>
void
gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct flcn_bl_dmem_desc_v2 hdr;
nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
hdr.code_dma_base = hdr.code_dma_base + adjust;
hdr.data_dma_base = hdr.data_dma_base + adjust;
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
}
void
gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
const u64 base = lsfw->offset.img + lsfw->app_start_offset;
const u64 code = base + lsfw->app_resident_code_offset;
const u64 data = base + lsfw->app_resident_data_offset;
const struct flcn_bl_dmem_desc_v2 hdr = {
.ctx_dma = FALCON_DMAIDX_UCODE,
.code_dma_base = code,
.non_sec_code_off = lsfw->app_resident_code_offset,
.non_sec_code_size = lsfw->app_resident_code_size,
.code_entry_point = lsfw->app_imem_entry,
.data_dma_base = data,
.data_size = lsfw->app_resident_data_size,
};
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
}
const struct nvkm_acr_lsf_func
gp108_gr_gpccs_acr = {
.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp108_gr_acr_bld_write,
.bld_patch = gp108_gr_acr_bld_patch,
};
const struct nvkm_acr_lsf_func
gp108_gr_fecs_acr = {
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp108_gr_acr_bld_write,
.bld_patch = gp108_gr_acr_bld_patch,
};
MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gp108_gr_fwif[] = {
{ 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp108_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c |
/*
* Copyright 2016 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gp100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408010, 0x8007d800);
gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
}
static void
gp100_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr;
const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0;
u32 bo = ao + size;
int gpc, ppc, n = 0;
gf100_grctx_patch_wr32(chan, 0x405830, attrib);
gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_max;
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
gf100_grctx_patch_wr32(chan, o + 0xc0, bs);
gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
bo += grctx->attrib_nr_max * gr->ppc_tpc_max;
gf100_grctx_patch_wr32(chan, o + 0xe4, as);
gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, u, bs);
}
}
gf100_grctx_patch_wr32(chan, 0x418eec, 0x00000000);
gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000000);
}
void
gp100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gm107_grctx_generate_attrib_cb(chan, addr, size);
gf100_grctx_patch_wr32(chan, 0x419b00, 0x00000000 | addr >> 12);
gf100_grctx_patch_wr32(chan, 0x419b04, 0x80000000 | size >> 7);
}
static u32
gp100_grctx_generate_attrib_cb_size(struct gf100_gr *gr)
{
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
int gpc;
for (gpc = 0; gpc < gr->gpc_nr; gpc++)
size += grctx->attrib_nr_max * gr->func->ppc_nr * gr->ppc_tpc_max;
return ((size * 0x20) + 128) & ~127;
}
void
gp100_grctx_generate_smid_config(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
u32 dist[TPC_MAX / 4] = {}, gpcs[16] = {};
u8 sm, i;
for (sm = 0; sm < gr->sm_nr; sm++) {
const u8 gpc = gr->sm[sm].gpc;
const u8 tpc = gr->sm[sm].tpc;
dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8);
}
for (i = 0; i < dist_nr; i++)
nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
for (i = 0; i < ARRAY_SIZE(gpcs); i++)
nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
}
const struct gf100_grctx_func
gp100_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x1080,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp100_grctx_generate_attrib_cb_size,
.attrib_cb = gp100_grctx_generate_attrib_cb,
.attrib = gp100_grctx_generate_attrib,
.attrib_nr_max = 0x660,
.attrib_nr = 0x440,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.tpc_mask = gm200_grctx_generate_tpc_mask,
.smid_config = gp100_grctx_generate_smid_config,
.r419a3c = gm200_grctx_generate_r419a3c,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf119_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{ 0x4064f0, 3, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{ 0x418cb4, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf119_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x0000a918 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_init
gf119_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf119_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x02001100 },
{ 0x419eac, 1, 0x04, 0x11100702 },
{ 0x419eb0, 1, 0x04, 0x00000003 },
{ 0x419eb4, 4, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0e063818 },
{ 0x419ecc, 1, 0x04, 0x0e060e06 },
{ 0x419ed0, 1, 0x04, 0x00003818 },
{ 0x419ed4, 1, 0x04, 0x011104f1 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419f2c, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_gr_init_fe_1[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf119_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gf119_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf119_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gf119_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf119_gr_init_tex_0 },
{ gf119_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf119_gr_init_wwdx_0 },
{ gf119_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf119_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf119_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct gf100_gr_func
gf119_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf119_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf100_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.grctx = &gf119_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_B, &gf100_fermi },
{ -1, -1, FERMI_C, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{ -1, -1, FERMI_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gf119_gr_fwif[] = {
{ -1, gf100_gr_load, &gf119_gr },
{ -1, gf100_gr_nofw, &gf119_gr },
{}
};
int
gf119_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf119_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c |
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
#include "gf100.h"
#include <subdev/mc.h>
static void
gk20a_grctx_generate_main(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
int i;
gf100_gr_mmio(gr, gr->sw_ctx);
gf100_gr_wait_idle(gr);
idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr));
grctx->attrib(chan);
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
for (i = 0; i < 8; i++)
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
gf100_gr_wait_idle(gr);
nvkm_wr32(device, 0x404154, idle_timeout);
gf100_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->method);
gf100_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->bundle);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(chan, chan->bundle_cb->addr, grctx->bundle_size);
}
const struct gf100_grctx_func
gk20a_grctx = {
.main = gk20a_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x240,
.attrib_nr = 0x240,
.alpha_nr_max = 0x648 + (0x648 / 2),
.alpha_nr = 0x648,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "priv.h"
#include <engine/fifo.h>
u32
nvkm_gr_ctxsw_inst(struct nvkm_device *device)
{
struct nvkm_gr *gr = device->gr;
if (gr && gr->func->ctxsw.inst)
return gr->func->ctxsw.inst(gr);
return 0;
}
int
nvkm_gr_ctxsw_resume(struct nvkm_device *device)
{
struct nvkm_gr *gr = device->gr;
if (gr && gr->func->ctxsw.resume)
return gr->func->ctxsw.resume(gr);
return 0;
}
int
nvkm_gr_ctxsw_pause(struct nvkm_device *device)
{
struct nvkm_gr *gr = device->gr;
if (gr && gr->func->ctxsw.pause)
return gr->func->ctxsw.pause(gr);
return 0;
}
static bool
nvkm_gr_chsw_load(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->chsw_load)
return gr->func->chsw_load(gr);
return false;
}
static void
nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->tile)
gr->func->tile(gr, region, tile);
}
u64
nvkm_gr_units(struct nvkm_gr *gr)
{
if (gr->func->units)
return gr->func->units(gr);
return 0;
}
int
nvkm_gr_tlb_flush(struct nvkm_gr *gr)
{
if (gr->func->tlb_flush)
return gr->func->tlb_flush(gr);
return -ENODEV;
}
static int
nvkm_gr_oclass_get(struct nvkm_oclass *oclass, int index)
{
struct nvkm_gr *gr = nvkm_gr(oclass->engine);
int c = 0;
if (gr->func->object_get) {
int ret = gr->func->object_get(gr, index, &oclass->base);
if (oclass->base.oclass)
return index;
return ret;
}
while (gr->func->sclass[c].oclass) {
if (c++ == index) {
oclass->base = gr->func->sclass[index];
return index;
}
}
return c;
}
static int
nvkm_gr_cclass_new(struct nvkm_chan *chan, const struct nvkm_oclass *oclass,
struct nvkm_object **pobject)
{
struct nvkm_gr *gr = nvkm_gr(oclass->engine);
if (gr->func->chan_new)
return gr->func->chan_new(gr, chan, oclass, pobject);
return 0;
}
static void
nvkm_gr_intr(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
gr->func->intr(gr);
}
static int
nvkm_gr_nonstall(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->nonstall)
return gr->func->nonstall(gr);
return -EINVAL;
}
static int
nvkm_gr_oneinit(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->oneinit)
return gr->func->oneinit(gr);
return 0;
}
static int
nvkm_gr_reset(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->reset)
return gr->func->reset(gr);
return -ENOSYS;
}
static int
nvkm_gr_init(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
return gr->func->init(gr);
}
static int
nvkm_gr_fini(struct nvkm_engine *engine, bool suspend)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->fini)
return gr->func->fini(gr, suspend);
return 0;
}
static void *
nvkm_gr_dtor(struct nvkm_engine *engine)
{
struct nvkm_gr *gr = nvkm_gr(engine);
if (gr->func->dtor)
return gr->func->dtor(gr);
return gr;
}
static const struct nvkm_engine_func
nvkm_gr = {
.dtor = nvkm_gr_dtor,
.oneinit = nvkm_gr_oneinit,
.init = nvkm_gr_init,
.fini = nvkm_gr_fini,
.reset = nvkm_gr_reset,
.nonstall = nvkm_gr_nonstall,
.intr = nvkm_gr_intr,
.tile = nvkm_gr_tile,
.chsw_load = nvkm_gr_chsw_load,
.fifo.cclass = nvkm_gr_cclass_new,
.fifo.sclass = nvkm_gr_oclass_get,
};
int
nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr)
{
gr->func = func;
return nvkm_engine_ctor(&nvkm_gr, device, type, inst, enable, &gr->engine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c |
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/acr.h>
#include <nvif/class.h>
#include <nvfw/flcn.h>
static const struct nvkm_acr_lsf_func
gp10b_gr_gpccs_acr = {
.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
.bld_size = sizeof(struct flcn_bl_dmem_desc),
.bld_write = gm20b_gr_acr_bld_write,
.bld_patch = gm20b_gr_acr_bld_patch,
};
static const struct gf100_gr_func
gp10b_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gp100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 1,
.tpc_nr = 2,
.ppc_nr = 1,
.grctx = &gp100_grctx,
.zbc = &gp100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, PASCAL_A, &gf100_fermi },
{ -1, -1, PASCAL_COMPUTE_A },
{}
}
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin");
#endif
static const struct gf100_gr_fwif
gp10b_gr_fwif[] = {
{ 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c |
/*
* Copyright 2007 Matthieu CASTET <[email protected]>
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nv10.h"
static const struct nvkm_gr_func
nv17_gr = {
.init = nv10_gr_init,
.intr = nv10_gr_intr,
.tile = nv10_gr_tile,
.chan_new = nv10_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x005f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
{ -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
{ -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
{ -1, -1, 0x0099, &nv04_gr_object },
{}
}
};
int
nv17_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv17_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c |
/*
* Copyright 2009 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
/* NVIDIA context programs handle a number of other conditions which are
* not implemented in our versions. It's not clear why NVIDIA context
* programs have this code, nor whether it's strictly necessary for
* correct operation. We'll implement additional handling if/when we
* discover it's necessary.
*
* - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state"
* flag is set, this gets saved into the context.
* - On context save, the context program for all cards load nsource
* into a flag register and check for ILLEGAL_MTHD. If it's set,
* opcode 0x60000d is called before resuming normal operation.
* - Some context programs check more conditions than the above. NV44
* checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001))
* and calls 0x60000d before resuming normal operation.
* - At the very beginning of NVIDIA's context programs, flag 9 is checked
* and if true 0x800001 is called with count=0, pos=0, the flag is cleared
* and then the ctxprog is aborted. It looks like a complicated NOP,
* its purpose is unknown.
* - In the section of code that loads the per-vs state, NVIDIA check
* flag 10. If it's set, they only transfer the small 0x300 byte block
* of state + the state for a single vs as opposed to the state for
* all vs units. It doesn't seem likely that it'll occur in normal
* operation, especially seeing as it appears NVIDIA may have screwed
* up the ctxprogs for some cards and have an invalid instruction
* rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction.
* - There's a number of places where context offset 0 (where we place
* the PRAMIN offset of the context) is loaded into either 0x408000,
* 0x408004 or 0x408008. Not sure what's up there either.
* - The ctxprogs for some cards save 0x400a00 again during the cleanup
* path for auto-loadctx.
*/
#define CP_FLAG_CLEAR 0
#define CP_FLAG_SET 1
#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
#define CP_FLAG_SWAP_DIRECTION_LOAD 0
#define CP_FLAG_SWAP_DIRECTION_SAVE 1
#define CP_FLAG_USER_SAVE ((0 * 32) + 5)
#define CP_FLAG_USER_SAVE_NOT_PENDING 0
#define CP_FLAG_USER_SAVE_PENDING 1
#define CP_FLAG_USER_LOAD ((0 * 32) + 6)
#define CP_FLAG_USER_LOAD_NOT_PENDING 0
#define CP_FLAG_USER_LOAD_PENDING 1
#define CP_FLAG_STATUS ((3 * 32) + 0)
#define CP_FLAG_STATUS_IDLE 0
#define CP_FLAG_STATUS_BUSY 1
#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4)
#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
#define CP_FLAG_AUTO_SAVE_PENDING 1
#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5)
#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
#define CP_FLAG_AUTO_LOAD_PENDING 1
#define CP_FLAG_UNK54 ((3 * 32) + 6)
#define CP_FLAG_UNK54_CLEAR 0
#define CP_FLAG_UNK54_SET 1
#define CP_FLAG_ALWAYS ((3 * 32) + 8)
#define CP_FLAG_ALWAYS_FALSE 0
#define CP_FLAG_ALWAYS_TRUE 1
#define CP_FLAG_UNK57 ((3 * 32) + 9)
#define CP_FLAG_UNK57_CLEAR 0
#define CP_FLAG_UNK57_SET 1
#define CP_CTX 0x00100000
#define CP_CTX_COUNT 0x000fc000
#define CP_CTX_COUNT_SHIFT 14
#define CP_CTX_REG 0x00003fff
#define CP_LOAD_SR 0x00200000
#define CP_LOAD_SR_VALUE 0x000fffff
#define CP_BRA 0x00400000
#define CP_BRA_IP 0x0000ff00
#define CP_BRA_IP_SHIFT 8
#define CP_BRA_IF_CLEAR 0x00000080
#define CP_BRA_FLAG 0x0000007f
#define CP_WAIT 0x00500000
#define CP_WAIT_SET 0x00000080
#define CP_WAIT_FLAG 0x0000007f
#define CP_SET 0x00700000
#define CP_SET_1 0x00000080
#define CP_SET_FLAG 0x0000007f
#define CP_NEXT_TO_SWAP 0x00600007
#define CP_NEXT_TO_CURRENT 0x00600009
#define CP_SET_CONTEXT_POINTER 0x0060000a
#define CP_END 0x0060000e
#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */
#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
#include "ctxnv40.h"
#include "nv40.h"
/* TODO:
* - get vs count from 0x1540
*/
static int
nv40_gr_vs_count(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x47:
case 0x49:
case 0x4b:
return 8;
case 0x40:
return 6;
case 0x41:
case 0x42:
return 5;
case 0x43:
case 0x44:
case 0x46:
case 0x4a:
return 3;
case 0x4c:
case 0x4e:
case 0x67:
default:
return 1;
}
}
enum cp_label {
cp_check_load = 1,
cp_setup_auto_load,
cp_setup_load,
cp_setup_save,
cp_swap_state,
cp_swap_state3d_3_is_save,
cp_prepare_exit,
cp_exit,
};
static void
nv40_gr_construct_general(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x4000a4, 1);
gr_def(ctx, 0x4000a4, 0x00000008);
cp_ctx(ctx, 0x400144, 58);
gr_def(ctx, 0x400144, 0x00000001);
cp_ctx(ctx, 0x400314, 1);
gr_def(ctx, 0x400314, 0x00000000);
cp_ctx(ctx, 0x400400, 10);
cp_ctx(ctx, 0x400480, 10);
cp_ctx(ctx, 0x400500, 19);
gr_def(ctx, 0x400514, 0x00040000);
gr_def(ctx, 0x400524, 0x55555555);
gr_def(ctx, 0x400528, 0x55555555);
gr_def(ctx, 0x40052c, 0x55555555);
gr_def(ctx, 0x400530, 0x55555555);
cp_ctx(ctx, 0x400560, 6);
gr_def(ctx, 0x400568, 0x0000ffff);
gr_def(ctx, 0x40056c, 0x0000ffff);
cp_ctx(ctx, 0x40057c, 5);
cp_ctx(ctx, 0x400710, 3);
gr_def(ctx, 0x400710, 0x20010001);
gr_def(ctx, 0x400714, 0x0f73ef00);
cp_ctx(ctx, 0x400724, 1);
gr_def(ctx, 0x400724, 0x02008821);
cp_ctx(ctx, 0x400770, 3);
if (device->chipset == 0x40) {
cp_ctx(ctx, 0x400814, 4);
cp_ctx(ctx, 0x400828, 5);
cp_ctx(ctx, 0x400840, 5);
gr_def(ctx, 0x400850, 0x00000040);
cp_ctx(ctx, 0x400858, 4);
gr_def(ctx, 0x400858, 0x00000040);
gr_def(ctx, 0x40085c, 0x00000040);
gr_def(ctx, 0x400864, 0x80000000);
cp_ctx(ctx, 0x40086c, 9);
gr_def(ctx, 0x40086c, 0x80000000);
gr_def(ctx, 0x400870, 0x80000000);
gr_def(ctx, 0x400874, 0x80000000);
gr_def(ctx, 0x400878, 0x80000000);
gr_def(ctx, 0x400888, 0x00000040);
gr_def(ctx, 0x40088c, 0x80000000);
cp_ctx(ctx, 0x4009c0, 8);
gr_def(ctx, 0x4009cc, 0x80000000);
gr_def(ctx, 0x4009dc, 0x80000000);
} else {
cp_ctx(ctx, 0x400840, 20);
if (nv44_gr_class(ctx->device)) {
for (i = 0; i < 8; i++)
gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
}
gr_def(ctx, 0x400880, 0x00000040);
gr_def(ctx, 0x400884, 0x00000040);
gr_def(ctx, 0x400888, 0x00000040);
cp_ctx(ctx, 0x400894, 11);
gr_def(ctx, 0x400894, 0x00000040);
if (!nv44_gr_class(ctx->device)) {
for (i = 0; i < 8; i++)
gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
}
cp_ctx(ctx, 0x4008e0, 2);
cp_ctx(ctx, 0x4008f8, 2);
if (device->chipset == 0x4c ||
(device->chipset & 0xf0) == 0x60)
cp_ctx(ctx, 0x4009f8, 1);
}
cp_ctx(ctx, 0x400a00, 73);
gr_def(ctx, 0x400b0c, 0x0b0b0b0c);
cp_ctx(ctx, 0x401000, 4);
cp_ctx(ctx, 0x405004, 1);
switch (device->chipset) {
case 0x47:
case 0x49:
case 0x4b:
cp_ctx(ctx, 0x403448, 1);
gr_def(ctx, 0x403448, 0x00001010);
break;
default:
cp_ctx(ctx, 0x403440, 1);
switch (device->chipset) {
case 0x40:
gr_def(ctx, 0x403440, 0x00000010);
break;
case 0x44:
case 0x46:
case 0x4a:
gr_def(ctx, 0x403440, 0x00003010);
break;
case 0x41:
case 0x42:
case 0x43:
case 0x4c:
case 0x4e:
case 0x67:
default:
gr_def(ctx, 0x403440, 0x00001010);
break;
}
break;
}
}
static void
nv40_gr_construct_state3d(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
if (device->chipset == 0x40) {
cp_ctx(ctx, 0x401880, 51);
gr_def(ctx, 0x401940, 0x00000100);
} else
if (device->chipset == 0x46 || device->chipset == 0x47 ||
device->chipset == 0x49 || device->chipset == 0x4b) {
cp_ctx(ctx, 0x401880, 32);
for (i = 0; i < 16; i++)
gr_def(ctx, 0x401880 + (i * 4), 0x00000111);
if (device->chipset == 0x46)
cp_ctx(ctx, 0x401900, 16);
cp_ctx(ctx, 0x401940, 3);
}
cp_ctx(ctx, 0x40194c, 18);
gr_def(ctx, 0x401954, 0x00000111);
gr_def(ctx, 0x401958, 0x00080060);
gr_def(ctx, 0x401974, 0x00000080);
gr_def(ctx, 0x401978, 0xffff0000);
gr_def(ctx, 0x40197c, 0x00000001);
gr_def(ctx, 0x401990, 0x46400000);
if (device->chipset == 0x40) {
cp_ctx(ctx, 0x4019a0, 2);
cp_ctx(ctx, 0x4019ac, 5);
} else {
cp_ctx(ctx, 0x4019a0, 1);
cp_ctx(ctx, 0x4019b4, 3);
}
gr_def(ctx, 0x4019bc, 0xffff0000);
switch (device->chipset) {
case 0x46:
case 0x47:
case 0x49:
case 0x4b:
cp_ctx(ctx, 0x4019c0, 18);
for (i = 0; i < 16; i++)
gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888);
break;
}
cp_ctx(ctx, 0x401a08, 8);
gr_def(ctx, 0x401a10, 0x0fff0000);
gr_def(ctx, 0x401a14, 0x0fff0000);
gr_def(ctx, 0x401a1c, 0x00011100);
cp_ctx(ctx, 0x401a2c, 4);
cp_ctx(ctx, 0x401a44, 26);
for (i = 0; i < 16; i++)
gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000);
gr_def(ctx, 0x401a8c, 0x4b7fffff);
if (device->chipset == 0x40) {
cp_ctx(ctx, 0x401ab8, 3);
} else {
cp_ctx(ctx, 0x401ab8, 1);
cp_ctx(ctx, 0x401ac0, 1);
}
cp_ctx(ctx, 0x401ad0, 8);
gr_def(ctx, 0x401ad0, 0x30201000);
gr_def(ctx, 0x401ad4, 0x70605040);
gr_def(ctx, 0x401ad8, 0xb8a89888);
gr_def(ctx, 0x401adc, 0xf8e8d8c8);
cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1);
gr_def(ctx, 0x401b10, 0x40100000);
cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5);
gr_def(ctx, 0x401b28, device->chipset == 0x40 ?
0x00000004 : 0x00000000);
cp_ctx(ctx, 0x401b30, 25);
gr_def(ctx, 0x401b34, 0x0000ffff);
gr_def(ctx, 0x401b68, 0x435185d6);
gr_def(ctx, 0x401b6c, 0x2155b699);
gr_def(ctx, 0x401b70, 0xfedcba98);
gr_def(ctx, 0x401b74, 0x00000098);
gr_def(ctx, 0x401b84, 0xffffffff);
gr_def(ctx, 0x401b88, 0x00ff7000);
gr_def(ctx, 0x401b8c, 0x0000ffff);
if (device->chipset != 0x44 && device->chipset != 0x4a &&
device->chipset != 0x4e)
cp_ctx(ctx, 0x401b94, 1);
cp_ctx(ctx, 0x401b98, 8);
gr_def(ctx, 0x401b9c, 0x00ff0000);
cp_ctx(ctx, 0x401bc0, 9);
gr_def(ctx, 0x401be0, 0x00ffff00);
cp_ctx(ctx, 0x401c00, 192);
for (i = 0; i < 16; i++) { /* fragment texture units */
gr_def(ctx, 0x401c40 + (i * 4), 0x00018488);
gr_def(ctx, 0x401c80 + (i * 4), 0x00028202);
gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4);
gr_def(ctx, 0x401d40 + (i * 4), 0x01012000);
gr_def(ctx, 0x401d80 + (i * 4), 0x00080008);
gr_def(ctx, 0x401e00 + (i * 4), 0x00100008);
}
for (i = 0; i < 4; i++) { /* vertex texture units */
gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80);
gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202);
gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008);
gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008);
}
cp_ctx(ctx, 0x400f5c, 3);
gr_def(ctx, 0x400f5c, 0x00000002);
cp_ctx(ctx, 0x400f84, 1);
}
static void
nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x402000, 1);
cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2);
switch (device->chipset) {
case 0x40:
gr_def(ctx, 0x402404, 0x00000001);
break;
case 0x4c:
case 0x4e:
case 0x67:
gr_def(ctx, 0x402404, 0x00000020);
break;
case 0x46:
case 0x49:
case 0x4b:
gr_def(ctx, 0x402404, 0x00000421);
break;
default:
gr_def(ctx, 0x402404, 0x00000021);
}
if (device->chipset != 0x40)
gr_def(ctx, 0x402408, 0x030c30c3);
switch (device->chipset) {
case 0x44:
case 0x46:
case 0x4a:
case 0x4c:
case 0x4e:
case 0x67:
cp_ctx(ctx, 0x402440, 1);
gr_def(ctx, 0x402440, 0x00011001);
break;
default:
break;
}
cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9);
gr_def(ctx, 0x402488, 0x3e020200);
gr_def(ctx, 0x40248c, 0x00ffffff);
switch (device->chipset) {
case 0x40:
gr_def(ctx, 0x402490, 0x60103f00);
break;
case 0x47:
gr_def(ctx, 0x402490, 0x40103f00);
break;
case 0x41:
case 0x42:
case 0x49:
case 0x4b:
gr_def(ctx, 0x402490, 0x20103f00);
break;
default:
gr_def(ctx, 0x402490, 0x0c103f00);
break;
}
gr_def(ctx, 0x40249c, device->chipset <= 0x43 ?
0x00020000 : 0x00040000);
cp_ctx(ctx, 0x402500, 31);
gr_def(ctx, 0x402530, 0x00008100);
if (device->chipset == 0x40)
cp_ctx(ctx, 0x40257c, 6);
cp_ctx(ctx, 0x402594, 16);
cp_ctx(ctx, 0x402800, 17);
gr_def(ctx, 0x402800, 0x00000001);
switch (device->chipset) {
case 0x47:
case 0x49:
case 0x4b:
cp_ctx(ctx, 0x402864, 1);
gr_def(ctx, 0x402864, 0x00001001);
cp_ctx(ctx, 0x402870, 3);
gr_def(ctx, 0x402878, 0x00000003);
if (device->chipset != 0x47) { /* belong at end!! */
cp_ctx(ctx, 0x402900, 1);
cp_ctx(ctx, 0x402940, 1);
cp_ctx(ctx, 0x402980, 1);
cp_ctx(ctx, 0x4029c0, 1);
cp_ctx(ctx, 0x402a00, 1);
cp_ctx(ctx, 0x402a40, 1);
cp_ctx(ctx, 0x402a80, 1);
cp_ctx(ctx, 0x402ac0, 1);
}
break;
case 0x40:
cp_ctx(ctx, 0x402844, 1);
gr_def(ctx, 0x402844, 0x00000001);
cp_ctx(ctx, 0x402850, 1);
break;
default:
cp_ctx(ctx, 0x402844, 1);
gr_def(ctx, 0x402844, 0x00001001);
cp_ctx(ctx, 0x402850, 2);
gr_def(ctx, 0x402854, 0x00000003);
break;
}
cp_ctx(ctx, 0x402c00, 4);
gr_def(ctx, 0x402c00, device->chipset == 0x40 ?
0x80800001 : 0x00888001);
switch (device->chipset) {
case 0x47:
case 0x49:
case 0x4b:
cp_ctx(ctx, 0x402c20, 40);
for (i = 0; i < 32; i++)
gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff);
cp_ctx(ctx, 0x4030b8, 13);
gr_def(ctx, 0x4030dc, 0x00000005);
gr_def(ctx, 0x4030e8, 0x0000ffff);
break;
default:
cp_ctx(ctx, 0x402c10, 4);
if (device->chipset == 0x40)
cp_ctx(ctx, 0x402c20, 36);
else
if (device->chipset <= 0x42)
cp_ctx(ctx, 0x402c20, 24);
else
if (device->chipset <= 0x4a)
cp_ctx(ctx, 0x402c20, 16);
else
cp_ctx(ctx, 0x402c20, 8);
cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13);
gr_def(ctx, 0x402cd4, 0x00000005);
if (device->chipset != 0x40)
gr_def(ctx, 0x402ce0, 0x0000ffff);
break;
}
cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3);
cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3);
cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device));
for (i = 0; i < nv40_gr_vs_count(ctx->device); i++)
gr_def(ctx, 0x403420 + (i * 4), 0x00005555);
if (device->chipset != 0x40) {
cp_ctx(ctx, 0x403600, 1);
gr_def(ctx, 0x403600, 0x00000001);
}
cp_ctx(ctx, 0x403800, 1);
cp_ctx(ctx, 0x403c18, 1);
gr_def(ctx, 0x403c18, 0x00000001);
switch (device->chipset) {
case 0x46:
case 0x47:
case 0x49:
case 0x4b:
cp_ctx(ctx, 0x405018, 1);
gr_def(ctx, 0x405018, 0x08e00001);
cp_ctx(ctx, 0x405c24, 1);
gr_def(ctx, 0x405c24, 0x000e3000);
break;
}
if (device->chipset != 0x4e)
cp_ctx(ctx, 0x405800, 11);
cp_ctx(ctx, 0x407000, 1);
}
static void
nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx)
{
int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
cp_out (ctx, 0x300000);
cp_lsr (ctx, len - 4);
cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save);
cp_lsr (ctx, len);
cp_name(ctx, cp_swap_state3d_3_is_save);
cp_out (ctx, 0x800001);
ctx->ctxvals_pos += len;
}
static void
nv40_gr_construct_shader(struct nvkm_grctx *ctx)
{
struct nvkm_device *device = ctx->device;
struct nvkm_gpuobj *obj = ctx->data;
int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
int offset, i;
vs_nr = nv40_gr_vs_count(ctx->device);
vs_nr_b0 = 363;
vs_nr_b1 = device->chipset == 0x40 ? 128 : 64;
if (device->chipset == 0x40) {
b0_offset = 0x2200/4; /* 33a0 */
b1_offset = 0x55a0/4; /* 1500 */
vs_len = 0x6aa0/4;
} else
if (device->chipset == 0x41 || device->chipset == 0x42) {
b0_offset = 0x2200/4; /* 2200 */
b1_offset = 0x4400/4; /* 0b00 */
vs_len = 0x4f00/4;
} else {
b0_offset = 0x1d40/4; /* 2200 */
b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4;
}
cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041);
offset = ctx->ctxvals_pos;
ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
if (ctx->mode != NVKM_GRCTX_VALS)
return;
offset += 0x0280/4;
for (i = 0; i < 16; i++, offset += 2)
nvkm_wo32(obj, offset * 4, 0x3f800000);
for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {
for (i = 0; i < vs_nr_b0 * 6; i += 6)
nvkm_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001);
for (i = 0; i < vs_nr_b1 * 4; i += 4)
nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000);
}
}
static void
nv40_grctx_generate(struct nvkm_grctx *ctx)
{
/* decide whether we're loading/unloading the context */
cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
cp_name(ctx, cp_check_load);
cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
cp_bra (ctx, ALWAYS, TRUE, cp_exit);
/* setup for context load */
cp_name(ctx, cp_setup_auto_load);
cp_wait(ctx, STATUS, IDLE);
cp_out (ctx, CP_NEXT_TO_SWAP);
cp_name(ctx, cp_setup_load);
cp_wait(ctx, STATUS, IDLE);
cp_set (ctx, SWAP_DIRECTION, LOAD);
cp_out (ctx, 0x00910880); /* ?? */
cp_out (ctx, 0x00901ffe); /* ?? */
cp_out (ctx, 0x01940000); /* ?? */
cp_lsr (ctx, 0x20);
cp_out (ctx, 0x0060000b); /* ?? */
cp_wait(ctx, UNK57, CLEAR);
cp_out (ctx, 0x0060000c); /* ?? */
cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
/* setup for context save */
cp_name(ctx, cp_setup_save);
cp_set (ctx, SWAP_DIRECTION, SAVE);
/* general PGRAPH state */
cp_name(ctx, cp_swap_state);
cp_pos (ctx, 0x00020/4);
nv40_gr_construct_general(ctx);
cp_wait(ctx, STATUS, IDLE);
/* 3D state, block 1 */
cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
nv40_gr_construct_state3d(ctx);
cp_wait(ctx, STATUS, IDLE);
/* 3D state, block 2 */
nv40_gr_construct_state3d_2(ctx);
/* Some other block of "random" state */
nv40_gr_construct_state3d_3(ctx);
/* Per-vertex shader state */
cp_pos (ctx, ctx->ctxvals_pos);
nv40_gr_construct_shader(ctx);
/* pre-exit state updates */
cp_name(ctx, cp_prepare_exit);
cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
cp_out (ctx, CP_NEXT_TO_CURRENT);
cp_name(ctx, cp_exit);
cp_set (ctx, USER_SAVE, NOT_PENDING);
cp_set (ctx, USER_LOAD, NOT_PENDING);
cp_out (ctx, CP_END);
}
void
nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
nv40_grctx_generate(&(struct nvkm_grctx) {
.device = device,
.mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
nv40_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
struct nvkm_grctx ctx = {
.device = device,
.mode = NVKM_GRCTX_PROG,
.ucode = ctxprog,
.ctxprog_max = 256,
};
if (!ctxprog)
return -ENOMEM;
nv40_grctx_generate(&ctx);
nvkm_wr32(device, 0x400324, 0);
for (i = 0; i < ctx.ctxprog_len; i++)
nvkm_wr32(device, 0x400328, ctxprog[i]);
*size = ctx.ctxvals_pos * 4;
kfree(ctxprog);
return 0;
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c |
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
static void
gm20b_grctx_generate_main(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
int i, tmp;
gf100_gr_mmio(gr, gr->sw_ctx);
gf100_gr_wait_idle(gr);
idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr));
grctx->attrib(chan);
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
for (i = 0; i < 8; i++)
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nvkm_wr32(device, 0x4041c4, tmp);
gm200_grctx_generate_smid_config(gr);
gf100_gr_wait_idle(gr);
nvkm_wr32(device, 0x404154, idle_timeout);
gf100_gr_wait_idle(gr);
gf100_gr_mthd(gr, gr->method);
gf100_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->bundle);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(chan, chan->bundle_cb->addr, grctx->bundle_size);
}
const struct gf100_grctx_func
gm20b_grctx = {
.main = gm20b_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x182,
.bundle_token_limit = 0x1c0,
.pagepool = gm107_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gm107_grctx_generate_attrib_cb,
.attrib = gm107_grctx_generate_attrib,
.attrib_nr_max = 0x600,
.attrib_nr = 0x400,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <nvif/class.h>
static const struct nvkm_gr_func
mcp89_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{ -1, -1, GT214_COMPUTE, &nv50_gr_object },
{ -1, -1, GT21A_TESLA, &nv50_gr_object },
{}
}
};
int
mcp89_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&mcp89_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c |
/*
* Copyright 2017 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
const struct gf100_gr_func
gp107_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gp100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 2,
.tpc_nr = 3,
.ppc_nr = 1,
.grctx = &gp107_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, PASCAL_B, &gf100_fermi },
{ -1, -1, PASCAL_COMPUTE_B },
{}
}
};
MODULE_FIRMWARE("nvidia/gp107/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gp107_gr_fwif[] = {
{ 0, gm200_gr_load, &gp107_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gm107_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x0000b1, 2, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000a8, 1, 0x01, 0x0000ffff },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002f2, 2, 0x01, 0x00000001 },
{ 0x0002f5, 1, 0x01, 0x00000001 },
{ 0x0002f7, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x0000de, 1, 0x01, 0x00000001 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000383, 1, 0x01, 0x00000011 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x0005d0, 1, 0x01, 0x20181008 },
{ 0x0005d1, 1, 0x01, 0x40383028 },
{ 0x0005d2, 1, 0x01, 0x60585048 },
{ 0x0005d3, 1, 0x01, 0x80787068 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000550, 32, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x000595, 1, 0x01, 0x00400040 },
{ 0x000596, 1, 0x01, 0x00000492 },
{ 0x000597, 1, 0x01, 0x08080203 },
{ 0x0005ad, 1, 0x01, 0x00000008 },
{ 0x000598, 1, 0x01, 0x00020001 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000662, 1, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x000a0d, 1, 0x01, 0x00000006 },
{ 0x00097d, 1, 0x01, 0x0000000c },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000687, 1, 0x01, 0x003fffff },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00400008 },
{ 0x000841, 1, 0x01, 0x08000080 },
{ 0x000842, 1, 0x01, 0x00400008 },
{ 0x000843, 1, 0x01, 0x08000080 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000008 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_icmd[] = {
{ gm107_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_b097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
{ 0x00080c, 8, 0x40, 0x00000300 },
{ 0x000810, 1, 0x04, 0x000000cf },
{ 0x000850, 7, 0x40, 0x00000000 },
{ 0x000814, 8, 0x40, 0x00000040 },
{ 0x000818, 8, 0x40, 0x00000001 },
{ 0x00081c, 8, 0x40, 0x00000000 },
{ 0x000820, 8, 0x40, 0x00000000 },
{ 0x001c00, 16, 0x10, 0x00000000 },
{ 0x001c04, 16, 0x10, 0x00000000 },
{ 0x001c08, 16, 0x10, 0x00000000 },
{ 0x001c0c, 16, 0x10, 0x00000000 },
{ 0x001d00, 16, 0x10, 0x00000000 },
{ 0x001d04, 16, 0x10, 0x00000000 },
{ 0x001d08, 16, 0x10, 0x00000000 },
{ 0x001d0c, 16, 0x10, 0x00000000 },
{ 0x001f00, 16, 0x08, 0x00000000 },
{ 0x001f04, 16, 0x08, 0x00000000 },
{ 0x001f80, 16, 0x08, 0x00000000 },
{ 0x001f84, 16, 0x08, 0x00000000 },
{ 0x002000, 1, 0x04, 0x00000000 },
{ 0x002040, 1, 0x04, 0x00000011 },
{ 0x002080, 1, 0x04, 0x00000020 },
{ 0x0020c0, 1, 0x04, 0x00000030 },
{ 0x002100, 1, 0x04, 0x00000040 },
{ 0x002140, 1, 0x04, 0x00000051 },
{ 0x00200c, 6, 0x40, 0x00000001 },
{ 0x002010, 1, 0x04, 0x00000000 },
{ 0x002050, 1, 0x04, 0x00000000 },
{ 0x002090, 1, 0x04, 0x00000001 },
{ 0x0020d0, 1, 0x04, 0x00000002 },
{ 0x002110, 1, 0x04, 0x00000003 },
{ 0x002150, 1, 0x04, 0x00000004 },
{ 0x000380, 4, 0x20, 0x00000000 },
{ 0x000384, 4, 0x20, 0x00000000 },
{ 0x000388, 4, 0x20, 0x00000000 },
{ 0x00038c, 4, 0x20, 0x00000000 },
{ 0x000700, 4, 0x10, 0x00000000 },
{ 0x000704, 4, 0x10, 0x00000000 },
{ 0x000708, 4, 0x10, 0x00000000 },
{ 0x002800, 128, 0x04, 0x00000000 },
{ 0x000a00, 16, 0x20, 0x00000000 },
{ 0x000a04, 16, 0x20, 0x00000000 },
{ 0x000a08, 16, 0x20, 0x00000000 },
{ 0x000a0c, 16, 0x20, 0x00000000 },
{ 0x000a10, 16, 0x20, 0x00000000 },
{ 0x000a14, 16, 0x20, 0x00000000 },
{ 0x000c00, 16, 0x10, 0x00000000 },
{ 0x000c04, 16, 0x10, 0x00000000 },
{ 0x000c08, 16, 0x10, 0x00000000 },
{ 0x000c0c, 16, 0x10, 0x3f800000 },
{ 0x000d00, 8, 0x08, 0xffff0000 },
{ 0x000d04, 8, 0x08, 0xffff0000 },
{ 0x000e00, 16, 0x10, 0x00000000 },
{ 0x000e04, 16, 0x10, 0xffff0000 },
{ 0x000e08, 16, 0x10, 0xffff0000 },
{ 0x000d40, 4, 0x08, 0x00000000 },
{ 0x000d44, 4, 0x08, 0x00000000 },
{ 0x001e00, 8, 0x20, 0x00000001 },
{ 0x001e04, 8, 0x20, 0x00000001 },
{ 0x001e08, 8, 0x20, 0x00000002 },
{ 0x001e0c, 8, 0x20, 0x00000001 },
{ 0x001e10, 8, 0x20, 0x00000001 },
{ 0x001e14, 8, 0x20, 0x00000002 },
{ 0x001e18, 8, 0x20, 0x00000001 },
{ 0x001480, 8, 0x10, 0x00000000 },
{ 0x001484, 8, 0x10, 0x00000000 },
{ 0x001488, 8, 0x10, 0x00000000 },
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x001514, 1, 0x04, 0x00000000 },
{ 0x000d68, 1, 0x04, 0x0000ffff },
{ 0x00121c, 1, 0x04, 0x0fac6881 },
{ 0x000fac, 1, 0x04, 0x00000001 },
{ 0x001538, 1, 0x04, 0x00000001 },
{ 0x000fe0, 2, 0x04, 0x00000000 },
{ 0x000fe8, 1, 0x04, 0x00000014 },
{ 0x000fec, 1, 0x04, 0x00000040 },
{ 0x000ff0, 1, 0x04, 0x00000000 },
{ 0x00179c, 1, 0x04, 0x00000000 },
{ 0x001228, 1, 0x04, 0x00000400 },
{ 0x00122c, 1, 0x04, 0x00000300 },
{ 0x001230, 1, 0x04, 0x00010001 },
{ 0x0007f8, 1, 0x04, 0x00000000 },
{ 0x0015b4, 1, 0x04, 0x00000001 },
{ 0x0015cc, 1, 0x04, 0x00000000 },
{ 0x001534, 1, 0x04, 0x00000000 },
{ 0x000754, 1, 0x04, 0x00000001 },
{ 0x000fb0, 1, 0x04, 0x00000000 },
{ 0x0015d0, 1, 0x04, 0x00000000 },
{ 0x00153c, 1, 0x04, 0x00000000 },
{ 0x0016b4, 1, 0x04, 0x00000003 },
{ 0x000fbc, 4, 0x04, 0x0000ffff },
{ 0x000df8, 2, 0x04, 0x00000000 },
{ 0x001948, 1, 0x04, 0x00000000 },
{ 0x001970, 1, 0x04, 0x00000001 },
{ 0x00161c, 1, 0x04, 0x000009f0 },
{ 0x000dcc, 1, 0x04, 0x00000010 },
{ 0x0015e4, 1, 0x04, 0x00000000 },
{ 0x001160, 32, 0x04, 0x25e00040 },
{ 0x001880, 32, 0x04, 0x00000000 },
{ 0x000f84, 2, 0x04, 0x00000000 },
{ 0x0017c8, 2, 0x04, 0x00000000 },
{ 0x0017d0, 1, 0x04, 0x000000ff },
{ 0x0017d4, 1, 0x04, 0xffffffff },
{ 0x0017d8, 1, 0x04, 0x00000002 },
{ 0x0017dc, 1, 0x04, 0x00000000 },
{ 0x0015f4, 2, 0x04, 0x00000000 },
{ 0x001434, 2, 0x04, 0x00000000 },
{ 0x000d74, 1, 0x04, 0x00000000 },
{ 0x0013a4, 1, 0x04, 0x00000000 },
{ 0x001318, 1, 0x04, 0x00000001 },
{ 0x001080, 2, 0x04, 0x00000000 },
{ 0x001088, 2, 0x04, 0x00000001 },
{ 0x001090, 1, 0x04, 0x00000000 },
{ 0x001094, 1, 0x04, 0x00000001 },
{ 0x001098, 1, 0x04, 0x00000000 },
{ 0x00109c, 1, 0x04, 0x00000001 },
{ 0x0010a0, 2, 0x04, 0x00000000 },
{ 0x001644, 1, 0x04, 0x00000000 },
{ 0x000748, 1, 0x04, 0x00000000 },
{ 0x000de8, 1, 0x04, 0x00000000 },
{ 0x001648, 1, 0x04, 0x00000000 },
{ 0x0012a4, 1, 0x04, 0x00000000 },
{ 0x001120, 4, 0x04, 0x00000000 },
{ 0x001118, 1, 0x04, 0x00000000 },
{ 0x00164c, 1, 0x04, 0x00000000 },
{ 0x001658, 1, 0x04, 0x00000000 },
{ 0x001910, 1, 0x04, 0x00000290 },
{ 0x001518, 1, 0x04, 0x00000000 },
{ 0x00165c, 1, 0x04, 0x00000001 },
{ 0x001520, 1, 0x04, 0x00000000 },
{ 0x001604, 1, 0x04, 0x00000000 },
{ 0x001570, 1, 0x04, 0x00000000 },
{ 0x0013b0, 2, 0x04, 0x3f800000 },
{ 0x00020c, 1, 0x04, 0x00000000 },
{ 0x001670, 1, 0x04, 0x30201000 },
{ 0x001674, 1, 0x04, 0x70605040 },
{ 0x001678, 1, 0x04, 0xb8a89888 },
{ 0x00167c, 1, 0x04, 0xf8e8d8c8 },
{ 0x00166c, 1, 0x04, 0x00000000 },
{ 0x001680, 1, 0x04, 0x00ffff00 },
{ 0x0012d0, 1, 0x04, 0x00000003 },
{ 0x0012d4, 1, 0x04, 0x00000002 },
{ 0x001684, 2, 0x04, 0x00000000 },
{ 0x000dac, 2, 0x04, 0x00001b02 },
{ 0x000db4, 1, 0x04, 0x00000000 },
{ 0x00168c, 1, 0x04, 0x00000000 },
{ 0x0015bc, 1, 0x04, 0x00000000 },
{ 0x00156c, 1, 0x04, 0x00000000 },
{ 0x00187c, 1, 0x04, 0x00000000 },
{ 0x001110, 1, 0x04, 0x00000001 },
{ 0x000dc0, 3, 0x04, 0x00000000 },
{ 0x000f40, 5, 0x04, 0x00000000 },
{ 0x001234, 1, 0x04, 0x00000000 },
{ 0x001690, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x001000, 1, 0x04, 0x00000010 },
{ 0x0010fc, 1, 0x04, 0x00000000 },
{ 0x001290, 1, 0x04, 0x00000000 },
{ 0x000218, 1, 0x04, 0x00000010 },
{ 0x0012d8, 1, 0x04, 0x00000000 },
{ 0x0012dc, 1, 0x04, 0x00000010 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x00155c, 2, 0x04, 0x00000000 },
{ 0x001564, 1, 0x04, 0x00000fff },
{ 0x001574, 2, 0x04, 0x00000000 },
{ 0x00157c, 1, 0x04, 0x000fffff },
{ 0x001354, 1, 0x04, 0x00000000 },
{ 0x001610, 1, 0x04, 0x00000012 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x00260c, 1, 0x04, 0x00000000 },
{ 0x0007ac, 1, 0x04, 0x00000000 },
{ 0x00162c, 1, 0x04, 0x00000003 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000324, 6, 0x04, 0x3f800000 },
{ 0x000750, 1, 0x04, 0x00000000 },
{ 0x000760, 1, 0x04, 0x39291909 },
{ 0x000764, 1, 0x04, 0x79695949 },
{ 0x000768, 1, 0x04, 0xb9a99989 },
{ 0x00076c, 1, 0x04, 0xf9e9d9c9 },
{ 0x000770, 1, 0x04, 0x30201000 },
{ 0x000774, 1, 0x04, 0x70605040 },
{ 0x000778, 1, 0x04, 0x00009080 },
{ 0x000780, 1, 0x04, 0x39291909 },
{ 0x000784, 1, 0x04, 0x79695949 },
{ 0x000788, 1, 0x04, 0xb9a99989 },
{ 0x00078c, 1, 0x04, 0xf9e9d9c9 },
{ 0x0007d0, 1, 0x04, 0x30201000 },
{ 0x0007d4, 1, 0x04, 0x70605040 },
{ 0x0007d8, 1, 0x04, 0x00009080 },
{ 0x00037c, 1, 0x04, 0x00000001 },
{ 0x000740, 2, 0x04, 0x00000000 },
{ 0x002600, 1, 0x04, 0x00000000 },
{ 0x001918, 1, 0x04, 0x00000000 },
{ 0x00191c, 1, 0x04, 0x00000900 },
{ 0x001920, 1, 0x04, 0x00000405 },
{ 0x001308, 1, 0x04, 0x00000001 },
{ 0x001924, 1, 0x04, 0x00000000 },
{ 0x0013ac, 1, 0x04, 0x00000000 },
{ 0x00192c, 1, 0x04, 0x00000001 },
{ 0x00193c, 1, 0x04, 0x00002c1c },
{ 0x000d7c, 1, 0x04, 0x00000000 },
{ 0x000f8c, 1, 0x04, 0x00000000 },
{ 0x0002c0, 1, 0x04, 0x00000001 },
{ 0x001510, 1, 0x04, 0x00000000 },
{ 0x001940, 1, 0x04, 0x00000000 },
{ 0x000ff4, 2, 0x04, 0x00000000 },
{ 0x00194c, 2, 0x04, 0x00000000 },
{ 0x001968, 1, 0x04, 0x00000000 },
{ 0x001590, 1, 0x04, 0x0000003f },
{ 0x0007e8, 4, 0x04, 0x00000000 },
{ 0x00196c, 1, 0x04, 0x00000011 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x00197c, 1, 0x04, 0x00000000 },
{ 0x000fcc, 2, 0x04, 0x00000000 },
{ 0x0002d8, 1, 0x04, 0x00000040 },
{ 0x001980, 1, 0x04, 0x00000080 },
{ 0x001504, 1, 0x04, 0x00000080 },
{ 0x001984, 1, 0x04, 0x00000000 },
{ 0x000f60, 1, 0x04, 0x00000000 },
{ 0x000f64, 1, 0x04, 0x00400040 },
{ 0x000f68, 1, 0x04, 0x00002212 },
{ 0x000f6c, 1, 0x04, 0x08080203 },
{ 0x001108, 1, 0x04, 0x00000008 },
{ 0x000f70, 1, 0x04, 0x00080001 },
{ 0x000ffc, 1, 0x04, 0x00000000 },
{ 0x000300, 1, 0x04, 0x00000001 },
{ 0x0013a8, 1, 0x04, 0x00000000 },
{ 0x0012ec, 1, 0x04, 0x00000000 },
{ 0x001310, 1, 0x04, 0x00000000 },
{ 0x001314, 1, 0x04, 0x00000001 },
{ 0x001380, 1, 0x04, 0x00000000 },
{ 0x001384, 4, 0x04, 0x00000001 },
{ 0x001394, 1, 0x04, 0x00000000 },
{ 0x00139c, 1, 0x04, 0x00000000 },
{ 0x001398, 1, 0x04, 0x00000000 },
{ 0x001594, 1, 0x04, 0x00000000 },
{ 0x001598, 4, 0x04, 0x00000001 },
{ 0x000f54, 3, 0x04, 0x00000000 },
{ 0x0019bc, 1, 0x04, 0x00000000 },
{ 0x000f9c, 2, 0x04, 0x00000000 },
{ 0x0012cc, 1, 0x04, 0x00000000 },
{ 0x0012e8, 1, 0x04, 0x00000000 },
{ 0x00130c, 1, 0x04, 0x00000001 },
{ 0x001360, 8, 0x04, 0x00000000 },
{ 0x00133c, 2, 0x04, 0x00000001 },
{ 0x001344, 1, 0x04, 0x00000002 },
{ 0x001348, 2, 0x04, 0x00000001 },
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x000dd0, 1, 0x04, 0x00000000 },
{ 0x000dd4, 1, 0x04, 0x00000001 },
{ 0x0002f4, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
{ 0x0019c8, 1, 0x04, 0x00001500 },
{ 0x00135c, 1, 0x04, 0x00000000 },
{ 0x000f90, 1, 0x04, 0x00000000 },
{ 0x0019e0, 8, 0x04, 0x00000001 },
{ 0x0019cc, 1, 0x04, 0x00000001 },
{ 0x0015b8, 1, 0x04, 0x00000000 },
{ 0x001a00, 1, 0x04, 0x00001111 },
{ 0x001a04, 7, 0x04, 0x00000000 },
{ 0x000d6c, 2, 0x04, 0xffff0000 },
{ 0x0010f8, 1, 0x04, 0x00001010 },
{ 0x000d80, 5, 0x04, 0x00000000 },
{ 0x000da0, 1, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x001508, 1, 0x04, 0x80000000 },
{ 0x00150c, 1, 0x04, 0x40000000 },
{ 0x001668, 1, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000008 },
{ 0x000d9c, 1, 0x04, 0x00000001 },
{ 0x000f14, 1, 0x04, 0x00000000 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x0000000c },
{ 0x0007dc, 1, 0x04, 0x00000000 },
{ 0x00074c, 1, 0x04, 0x00000055 },
{ 0x001420, 1, 0x04, 0x00000003 },
{ 0x001008, 1, 0x04, 0x00000008 },
{ 0x00100c, 1, 0x04, 0x00000040 },
{ 0x001010, 1, 0x04, 0x0000012c },
{ 0x000d60, 1, 0x04, 0x00000040 },
{ 0x001018, 1, 0x04, 0x00000020 },
{ 0x00101c, 1, 0x04, 0x00000001 },
{ 0x001020, 1, 0x04, 0x00000020 },
{ 0x001024, 1, 0x04, 0x00000001 },
{ 0x001444, 3, 0x04, 0x00000000 },
{ 0x000360, 1, 0x04, 0x20164010 },
{ 0x000364, 1, 0x04, 0x00000020 },
{ 0x000368, 1, 0x04, 0x00000000 },
{ 0x000da8, 1, 0x04, 0x00000030 },
{ 0x000de4, 1, 0x04, 0x00000000 },
{ 0x000204, 1, 0x04, 0x00000006 },
{ 0x0002d0, 1, 0x04, 0x003fffff },
{ 0x001220, 1, 0x04, 0x00000005 },
{ 0x000fdc, 1, 0x04, 0x00000000 },
{ 0x000f98, 1, 0x04, 0x00400008 },
{ 0x001284, 1, 0x04, 0x08000080 },
{ 0x001450, 1, 0x04, 0x00400008 },
{ 0x001454, 1, 0x04, 0x08000080 },
{ 0x000214, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_mthd[] = {
{ gm107_grctx_init_b097_0, 0xb097 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
{ 0x4040a8, 8, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf800008f },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404100, 10, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000045 },
{ 0x40417c, 2, 0x04, 0x00000000 },
{ 0x404194, 1, 0x04, 0x01000700 },
{ 0x4041a0, 4, 0x04, 0x00000000 },
{ 0x404200, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8001bf },
{ 0x405830, 1, 0x04, 0x0aa01000 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{ 0x405a1c, 1, 0x04, 0x000000ff },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x07410001 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b0, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x80400280 },
{ 0x4064c4, 1, 0x04, 0x0400ffff },
{ 0x4064c8, 1, 0x04, 0x018001ff },
{ 0x4064cc, 9, 0x04, 0x00000000 },
{ 0x4064fc, 1, 0x04, 0x0000022a },
{ 0x406500, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
{ 0x408840, 1, 0x04, 0x0000000b },
{ 0x408900, 1, 0x04, 0xb080b801 },
{ 0x408904, 1, 0x04, 0x63038001 },
{ 0x408908, 1, 0x04, 0x02c8102f },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gm107_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gm107_grctx_init_ds_0 },
{ gk110_grctx_init_cwd_0 },
{ gm107_grctx_init_pd_0 },
{ gk208_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gm107_grctx_init_be_0 },
{}
};
const struct gf100_gr_init
gm107_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000056 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 1, 0x04, 0x40000000 },
{ 0x41870c, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418810, 1, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100058 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x90000000 },
{ 0x418e24, 1, 0x04, 0x00000000 },
{ 0x418e28, 1, 0x04, 0x00000030 },
{ 0x418e30, 1, 0x04, 0x00000000 },
{ 0x418e34, 1, 0x04, 0x00010000 },
{ 0x418e38, 1, 0x04, 0x00000000 },
{ 0x418e40, 22, 0x04, 0x00000000 },
{ 0x418ea0, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_gpc_0[] = {
{ gm107_grctx_init_gpc_unk_0 },
{ gk208_grctx_init_prop_0 },
{ gm107_grctx_init_gpc_unk_1 },
{ gm107_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_gpc_1[] = {
{ gk208_grctx_init_crstr_0 },
{ gk104_grctx_init_gpm_0 },
{ gm107_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000300f0 },
{ 0x419a04, 1, 0x04, 0x00000005 },
{ 0x419a08, 1, 0x04, 0x00000421 },
{ 0x419a0c, 1, 0x04, 0x00120000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00002200 },
{ 0x419a1c, 1, 0x04, 0x0000c000 },
{ 0x419a20, 1, 0x04, 0x20008a00 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419a3c, 1, 0x04, 0x00000002 },
{ 0x419ac4, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{ 0x419c2c, 1, 0x04, 0x00000000 },
{ 0x419c34, 1, 0x04, 0x01ff1ff3 },
{ 0x419c3c, 1, 0x04, 0x00001919 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_l1c_0[] = {
{ 0x419c84, 1, 0x04, 0x00000020 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
{ 0x419e44, 1, 0x04, 0x00d3eff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000007f },
{ 0x419e50, 1, 0x04, 0x00000000 },
{ 0x419e60, 4, 0x04, 0x00000000 },
{ 0x419e74, 10, 0x04, 0x00000000 },
{ 0x419eac, 1, 0x04, 0x0001cf8b },
{ 0x419eb0, 1, 0x04, 0x00030300 },
{ 0x419eb8, 1, 0x04, 0x00000000 },
{ 0x419ef0, 24, 0x04, 0x00000000 },
{ 0x419f68, 2, 0x04, 0x00000000 },
{ 0x419f70, 1, 0x04, 0x00000020 },
{ 0x419f78, 1, 0x04, 0x000003eb },
{ 0x419f7c, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gm107_grctx_init_tex_0 },
{ gm107_grctx_init_mpc_0 },
{ gm107_grctx_init_l1c_0 },
{ gm107_grctx_init_sm_0 },
{}
};
static const struct gf100_gr_init
gm107_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x00000000 },
{ 0x41bec4, 1, 0x04, 0x01050000 },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{ 0x41bef0, 1, 0x04, 0x000003ff },
{ 0x41bef4, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gm107_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
{ 0x41bf0c, 1, 0x04, 0x0e629062 },
{ 0x41bf10, 1, 0x04, 0x0a418820 },
{ 0x41bf14, 1, 0x04, 0x000000e6 },
{ 0x41bfd0, 1, 0x04, 0x00900103 },
{ 0x41bfe0, 1, 0x04, 0x80000000 },
{ 0x41bfe4, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gm107_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gm107_grctx_init_cbm_0 },
{ gm107_grctx_init_wwdx_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
static void
gm107_grctx_generate_r419e00(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080);
nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000);
nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000);
nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000);
}
void
gm107_grctx_generate_bundle(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
const struct gf100_grctx_func *grctx = chan->gr->func->grctx;
const u32 state_limit = min(grctx->bundle_min_gpm_fifo_depth, size / 0x20);
const u32 token_limit = grctx->bundle_token_limit;
gf100_grctx_patch_wr32(chan, 0x408004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408008, 0x80000000 | (size >> 8));
gf100_grctx_patch_wr32(chan, 0x418e24, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x418e28, 0x80000000 | (size >> 8));
gf100_grctx_patch_wr32(chan, 0x4064c8, (state_limit << 16) | token_limit);
}
void
gm107_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
gk104_grctx_generate_pagepool(chan, addr);
gf100_grctx_patch_wr32(chan, 0x418e30, 0x80000000);
}
void
gm107_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr;
const int max_batches = 0xffff;
u32 bo = 0;
u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
int gpc, ppc, n = 0;
gf100_grctx_patch_wr32(chan, 0x405830, (attrib << 16) | alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
gf100_grctx_patch_wr32(chan, o + 0xc0, bs);
gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, o + 0xe4, as);
gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, u, ((bs / 3) << 16) | bs);
}
}
}
void
gm107_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gf100_grctx_generate_attrib_cb(chan, addr, size);
gf100_grctx_patch_wr32(chan, 0x419c2c, 0x10000000 | addr >> 12);
}
static void
gm107_grctx_generate_r406500(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000001);
}
void
gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}
const struct gf100_grctx_func
gm107_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gm107_grctx_pack_hub,
.gpc_0 = gm107_grctx_pack_gpc_0,
.gpc_1 = gm107_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gm107_grctx_pack_tpc,
.ppc = gm107_grctx_pack_ppc,
.icmd = gm107_grctx_pack_icmd,
.mthd = gm107_grctx_pack_mthd,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x2c0,
.pagepool = gm107_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gm107_grctx_generate_attrib_cb,
.attrib = gm107_grctx_generate_attrib,
.attrib_nr_max = 0xff0,
.attrib_nr = 0xaa0,
.alpha_nr_max = 0x1800,
.alpha_nr = 0x1000,
.sm_id = gm107_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.r406500 = gm107_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.r419e00 = gm107_grctx_generate_r419e00,
.r419f78 = gk110_grctx_generate_r419f78,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c |
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
static void
gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80)));
u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80)));
const struct nvkm_enum *warp;
char glob[128];
nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: "
"global %08x [%s] warp %04x [%s]\n",
gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : "");
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr);
}
void
gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
gv100_gr_trap_sm(gr, gpc, tpc, 0);
gv100_gr_trap_sm(gr, gpc, tpc, 1);
}
void
gv100_gr_init_4188a4(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000);
}
void
gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int sm;
for (sm = 0; sm < 0x100; sm += 0x80) {
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004);
}
}
void
gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000);
}
void
gv100_gr_init_419bd8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000);
}
u32
gv100_gr_nonpes_aware_tpc(struct gf100_gr *gr, u32 gpc, u32 tpc)
{
u32 pes, temp, tpc_new = 0;
for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
if (gr->ppc_tpc_mask[gpc][pes] & BIT(tpc))
break;
tpc_new += gr->ppc_tpc_nr[gpc][pes];
}
temp = (BIT(tpc) - 1) & gr->ppc_tpc_mask[gpc][pes];
temp = hweight32(temp);
return tpc_new + temp;
}
static int
gv100_gr_scg_estimate_perf(struct gf100_gr *gr, unsigned long *gpc_tpc_mask,
u32 disable_gpc, u32 disable_tpc, int *perf)
{
const u32 scale_factor = 512UL; /* Use fx23.9 */
const u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */
const u32 world_scale = 1024UL; /* World performance in [19:10] */
const u32 tpc_scale = 1; /* TPC balancing in [9:0] */
u32 scg_num_pes = 0;
u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */
u32 average_tpcs = 0; /* Average of # of TPCs per GPC */
u32 deviation; /* absolute diff between TPC# and average_tpcs, averaged across GPCs */
u32 norm_tpc_deviation; /* deviation/max_tpc_per_gpc */
u32 tpc_balance;
u32 scg_gpc_pix_perf;
u32 scg_world_perf;
u32 gpc;
u32 pes;
int diff;
bool tpc_removed_gpc = false;
bool tpc_removed_pes = false;
u32 max_tpc_gpc = 0;
u32 num_tpc_mask;
u32 *num_tpc_gpc;
int ret = -EINVAL;
if (!(num_tpc_gpc = kcalloc(gr->gpc_nr, sizeof(*num_tpc_gpc), GFP_KERNEL)))
return -ENOMEM;
/* Calculate pix-perf-reduction-rate per GPC and find bottleneck TPC */
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
num_tpc_mask = gpc_tpc_mask[gpc];
if ((gpc == disable_gpc) && num_tpc_mask & BIT(disable_tpc)) {
/* Safety check if a TPC is removed twice */
if (WARN_ON(tpc_removed_gpc))
goto done;
/* Remove logical TPC from set */
num_tpc_mask &= ~BIT(disable_tpc);
tpc_removed_gpc = true;
}
/* track balancing of tpcs across gpcs */
num_tpc_gpc[gpc] = hweight32(num_tpc_mask);
average_tpcs += num_tpc_gpc[gpc];
/* save the maximum numer of gpcs */
max_tpc_gpc = num_tpc_gpc[gpc] > max_tpc_gpc ? num_tpc_gpc[gpc] : max_tpc_gpc;
/*
* Calculate ratio between TPC count and post-FS and post-SCG
*
* ratio represents relative throughput of the GPC
*/
scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc] / gr->tpc_nr[gpc];
if (min_scg_gpc_pix_perf > scg_gpc_pix_perf)
min_scg_gpc_pix_perf = scg_gpc_pix_perf;
/* Calculate # of surviving PES */
for (pes = 0; pes < gr->ppc_nr[gpc]; pes++) {
/* Count the number of TPC on the set */
num_tpc_mask = gr->ppc_tpc_mask[gpc][pes] & gpc_tpc_mask[gpc];
if ((gpc == disable_gpc) && (num_tpc_mask & BIT(disable_tpc))) {
if (WARN_ON(tpc_removed_pes))
goto done;
num_tpc_mask &= ~BIT(disable_tpc);
tpc_removed_pes = true;
}
if (hweight32(num_tpc_mask))
scg_num_pes++;
}
}
if (WARN_ON(!tpc_removed_gpc || !tpc_removed_pes))
goto done;
if (max_tpc_gpc == 0) {
*perf = 0;
goto done_ok;
}
/* Now calculate perf */
scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_total;
deviation = 0;
average_tpcs = scale_factor * average_tpcs / gr->gpc_nr;
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
diff = average_tpcs - scale_factor * num_tpc_gpc[gpc];
if (diff < 0)
diff = -diff;
deviation += diff;
}
deviation /= gr->gpc_nr;
norm_tpc_deviation = deviation / max_tpc_gpc;
tpc_balance = scale_factor - norm_tpc_deviation;
if ((tpc_balance > scale_factor) ||
(scg_world_perf > scale_factor) ||
(min_scg_gpc_pix_perf > scale_factor) ||
(norm_tpc_deviation > scale_factor)) {
WARN_ON(1);
goto done;
}
*perf = (pix_scale * min_scg_gpc_pix_perf) +
(world_scale * scg_world_perf) +
(tpc_scale * tpc_balance);
done_ok:
ret = 0;
done:
kfree(num_tpc_gpc);
return ret;
}
int
gv100_gr_oneinit_sm_id(struct gf100_gr *gr)
{
unsigned long *gpc_tpc_mask;
u32 *tpc_table, *gpc_table;
u32 gpc, tpc, pes, gtpc;
int perf, maxperf, ret = 0;
gpc_tpc_mask = kcalloc(gr->gpc_nr, sizeof(*gpc_tpc_mask), GFP_KERNEL);
gpc_table = kcalloc(gr->tpc_total, sizeof(*gpc_table), GFP_KERNEL);
tpc_table = kcalloc(gr->tpc_total, sizeof(*tpc_table), GFP_KERNEL);
if (!gpc_table || !tpc_table || !gpc_tpc_mask) {
ret = -ENOMEM;
goto done;
}
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (pes = 0; pes < gr->ppc_nr[gpc]; pes++)
gpc_tpc_mask[gpc] |= gr->ppc_tpc_mask[gpc][pes];
}
for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
for (maxperf = -1, gpc = 0; gpc < gr->gpc_nr; gpc++) {
for_each_set_bit(tpc, &gpc_tpc_mask[gpc], gr->tpc_nr[gpc]) {
ret = gv100_gr_scg_estimate_perf(gr, gpc_tpc_mask, gpc, tpc, &perf);
if (ret)
goto done;
/* nvgpu does ">=" here, but this gets us RM's numbers. */
if (perf > maxperf) {
maxperf = perf;
gpc_table[gtpc] = gpc;
tpc_table[gtpc] = tpc;
}
}
}
gpc_tpc_mask[gpc_table[gtpc]] &= ~BIT(tpc_table[gtpc]);
}
/*TODO: build table for sm_per_tpc != 1, don't use yet, but might need later? */
for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) {
gr->sm[gtpc].gpc = gpc_table[gtpc];
gr->sm[gtpc].tpc = tpc_table[gtpc];
gr->sm_nr++;
}
done:
kfree(gpc_table);
kfree(tpc_table);
kfree(gpc_tpc_mask);
return ret;
}
static const struct gf100_gr_func
gv100_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gv100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_419bd8 = gv100_gr_init_419bd8,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_504430 = gv100_gr_init_504430,
.init_shader_exceptions = gv100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_4188a4 = gv100_gr_init_4188a4,
.trap_mp = gv100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 7,
.ppc_nr = 3,
.grctx = &gv100_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, VOLTA_A, &gf100_fermi },
{ -1, -1, VOLTA_COMPUTE_A },
{}
}
};
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gv100_gr_fwif[] = {
{ 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000b2, 40, 0x01, 0x00000000 },
{ 0x000210, 8, 0x01, 0x00000040 },
{ 0x000218, 8, 0x01, 0x0000c080 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00001fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x003fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x0005e0, 5, 0x01, 0x00000022 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x00097d, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x00000c48 },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00300008 },
{ 0x000841, 1, 0x01, 0x04000080 },
{ 0x000842, 1, 0x01, 0x00300008 },
{ 0x000843, 1, 0x01, 0x04000080 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x000944, 1, 0x01, 0x00000022 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gf110_grctx_pack_icmd[] = {
{ gf110_grctx_init_icmd_0 },
{}
};
const struct gf100_gr_init
gf110_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
const struct gf100_gr_init
gf110_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x00000020 },
{}
};
static const struct gf100_gr_pack
gf110_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf110_grctx_init_9197_0, 0x9197 },
{ gf110_grctx_init_9297_0, 0x9297 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct gf100_gr_init
gf110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x00000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100000 },
{}
};
static const struct gf100_gr_pack
gf110_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf100_grctx_init_prop_0 },
{ gf100_grctx_init_gpc_unk_1 },
{ gf110_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gf110_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gf100_grctx_generate_unkn,
.hub = gf100_grctx_pack_hub,
.gpc_0 = gf110_grctx_pack_gpc_0,
.gpc_1 = gf100_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf100_grctx_pack_tpc,
.icmd = gf110_grctx_pack_icmd,
.mthd = gf110_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf100_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk104_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000383, 1, 0x01, 0x00000011 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x00097d, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x003fffff },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00400008 },
{ 0x000841, 1, 0x01, 0x08000080 },
{ 0x000842, 1, 0x01, 0x00400008 },
{ 0x000843, 1, 0x01, 0x08000080 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000008 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
const struct gf100_gr_pack
gk104_grctx_pack_icmd[] = {
{ gk104_grctx_init_icmd_0 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_a097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
{ 0x00080c, 8, 0x40, 0x00000300 },
{ 0x000810, 1, 0x04, 0x000000cf },
{ 0x000850, 7, 0x40, 0x00000000 },
{ 0x000814, 8, 0x40, 0x00000040 },
{ 0x000818, 8, 0x40, 0x00000001 },
{ 0x00081c, 8, 0x40, 0x00000000 },
{ 0x000820, 8, 0x40, 0x00000000 },
{ 0x001c00, 16, 0x10, 0x00000000 },
{ 0x001c04, 16, 0x10, 0x00000000 },
{ 0x001c08, 16, 0x10, 0x00000000 },
{ 0x001c0c, 16, 0x10, 0x00000000 },
{ 0x001d00, 16, 0x10, 0x00000000 },
{ 0x001d04, 16, 0x10, 0x00000000 },
{ 0x001d08, 16, 0x10, 0x00000000 },
{ 0x001d0c, 16, 0x10, 0x00000000 },
{ 0x001f00, 16, 0x08, 0x00000000 },
{ 0x001f04, 16, 0x08, 0x00000000 },
{ 0x001f80, 16, 0x08, 0x00000000 },
{ 0x001f84, 16, 0x08, 0x00000000 },
{ 0x002000, 1, 0x04, 0x00000000 },
{ 0x002040, 1, 0x04, 0x00000011 },
{ 0x002080, 1, 0x04, 0x00000020 },
{ 0x0020c0, 1, 0x04, 0x00000030 },
{ 0x002100, 1, 0x04, 0x00000040 },
{ 0x002140, 1, 0x04, 0x00000051 },
{ 0x00200c, 6, 0x40, 0x00000001 },
{ 0x002010, 1, 0x04, 0x00000000 },
{ 0x002050, 1, 0x04, 0x00000000 },
{ 0x002090, 1, 0x04, 0x00000001 },
{ 0x0020d0, 1, 0x04, 0x00000002 },
{ 0x002110, 1, 0x04, 0x00000003 },
{ 0x002150, 1, 0x04, 0x00000004 },
{ 0x000380, 4, 0x20, 0x00000000 },
{ 0x000384, 4, 0x20, 0x00000000 },
{ 0x000388, 4, 0x20, 0x00000000 },
{ 0x00038c, 4, 0x20, 0x00000000 },
{ 0x000700, 4, 0x10, 0x00000000 },
{ 0x000704, 4, 0x10, 0x00000000 },
{ 0x000708, 4, 0x10, 0x00000000 },
{ 0x002800, 128, 0x04, 0x00000000 },
{ 0x000a00, 16, 0x20, 0x00000000 },
{ 0x000a04, 16, 0x20, 0x00000000 },
{ 0x000a08, 16, 0x20, 0x00000000 },
{ 0x000a0c, 16, 0x20, 0x00000000 },
{ 0x000a10, 16, 0x20, 0x00000000 },
{ 0x000a14, 16, 0x20, 0x00000000 },
{ 0x000c00, 16, 0x10, 0x00000000 },
{ 0x000c04, 16, 0x10, 0x00000000 },
{ 0x000c08, 16, 0x10, 0x00000000 },
{ 0x000c0c, 16, 0x10, 0x3f800000 },
{ 0x000d00, 8, 0x08, 0xffff0000 },
{ 0x000d04, 8, 0x08, 0xffff0000 },
{ 0x000e00, 16, 0x10, 0x00000000 },
{ 0x000e04, 16, 0x10, 0xffff0000 },
{ 0x000e08, 16, 0x10, 0xffff0000 },
{ 0x000d40, 4, 0x08, 0x00000000 },
{ 0x000d44, 4, 0x08, 0x00000000 },
{ 0x001e00, 8, 0x20, 0x00000001 },
{ 0x001e04, 8, 0x20, 0x00000001 },
{ 0x001e08, 8, 0x20, 0x00000002 },
{ 0x001e0c, 8, 0x20, 0x00000001 },
{ 0x001e10, 8, 0x20, 0x00000001 },
{ 0x001e14, 8, 0x20, 0x00000002 },
{ 0x001e18, 8, 0x20, 0x00000001 },
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x001514, 1, 0x04, 0x00000000 },
{ 0x000d68, 1, 0x04, 0x0000ffff },
{ 0x00121c, 1, 0x04, 0x0fac6881 },
{ 0x000fac, 1, 0x04, 0x00000001 },
{ 0x001538, 1, 0x04, 0x00000001 },
{ 0x000fe0, 2, 0x04, 0x00000000 },
{ 0x000fe8, 1, 0x04, 0x00000014 },
{ 0x000fec, 1, 0x04, 0x00000040 },
{ 0x000ff0, 1, 0x04, 0x00000000 },
{ 0x00179c, 1, 0x04, 0x00000000 },
{ 0x001228, 1, 0x04, 0x00000400 },
{ 0x00122c, 1, 0x04, 0x00000300 },
{ 0x001230, 1, 0x04, 0x00010001 },
{ 0x0007f8, 1, 0x04, 0x00000000 },
{ 0x0015b4, 1, 0x04, 0x00000001 },
{ 0x0015cc, 1, 0x04, 0x00000000 },
{ 0x001534, 1, 0x04, 0x00000000 },
{ 0x000fb0, 1, 0x04, 0x00000000 },
{ 0x0015d0, 1, 0x04, 0x00000000 },
{ 0x00153c, 1, 0x04, 0x00000000 },
{ 0x0016b4, 1, 0x04, 0x00000003 },
{ 0x000fbc, 4, 0x04, 0x0000ffff },
{ 0x000df8, 2, 0x04, 0x00000000 },
{ 0x001948, 1, 0x04, 0x00000000 },
{ 0x001970, 1, 0x04, 0x00000001 },
{ 0x00161c, 1, 0x04, 0x000009f0 },
{ 0x000dcc, 1, 0x04, 0x00000010 },
{ 0x00163c, 1, 0x04, 0x00000000 },
{ 0x0015e4, 1, 0x04, 0x00000000 },
{ 0x001160, 32, 0x04, 0x25e00040 },
{ 0x001880, 32, 0x04, 0x00000000 },
{ 0x000f84, 2, 0x04, 0x00000000 },
{ 0x0017c8, 2, 0x04, 0x00000000 },
{ 0x0017d0, 1, 0x04, 0x000000ff },
{ 0x0017d4, 1, 0x04, 0xffffffff },
{ 0x0017d8, 1, 0x04, 0x00000002 },
{ 0x0017dc, 1, 0x04, 0x00000000 },
{ 0x0015f4, 2, 0x04, 0x00000000 },
{ 0x001434, 2, 0x04, 0x00000000 },
{ 0x000d74, 1, 0x04, 0x00000000 },
{ 0x000dec, 1, 0x04, 0x00000001 },
{ 0x0013a4, 1, 0x04, 0x00000000 },
{ 0x001318, 1, 0x04, 0x00000001 },
{ 0x001644, 1, 0x04, 0x00000000 },
{ 0x000748, 1, 0x04, 0x00000000 },
{ 0x000de8, 1, 0x04, 0x00000000 },
{ 0x001648, 1, 0x04, 0x00000000 },
{ 0x0012a4, 1, 0x04, 0x00000000 },
{ 0x001120, 4, 0x04, 0x00000000 },
{ 0x001118, 1, 0x04, 0x00000000 },
{ 0x00164c, 1, 0x04, 0x00000000 },
{ 0x001658, 1, 0x04, 0x00000000 },
{ 0x001910, 1, 0x04, 0x00000290 },
{ 0x001518, 1, 0x04, 0x00000000 },
{ 0x00165c, 1, 0x04, 0x00000001 },
{ 0x001520, 1, 0x04, 0x00000000 },
{ 0x001604, 1, 0x04, 0x00000000 },
{ 0x001570, 1, 0x04, 0x00000000 },
{ 0x0013b0, 2, 0x04, 0x3f800000 },
{ 0x00020c, 1, 0x04, 0x00000000 },
{ 0x001670, 1, 0x04, 0x30201000 },
{ 0x001674, 1, 0x04, 0x70605040 },
{ 0x001678, 1, 0x04, 0xb8a89888 },
{ 0x00167c, 1, 0x04, 0xf8e8d8c8 },
{ 0x00166c, 1, 0x04, 0x00000000 },
{ 0x001680, 1, 0x04, 0x00ffff00 },
{ 0x0012d0, 1, 0x04, 0x00000003 },
{ 0x0012d4, 1, 0x04, 0x00000002 },
{ 0x001684, 2, 0x04, 0x00000000 },
{ 0x000dac, 2, 0x04, 0x00001b02 },
{ 0x000db4, 1, 0x04, 0x00000000 },
{ 0x00168c, 1, 0x04, 0x00000000 },
{ 0x0015bc, 1, 0x04, 0x00000000 },
{ 0x00156c, 1, 0x04, 0x00000000 },
{ 0x00187c, 1, 0x04, 0x00000000 },
{ 0x001110, 1, 0x04, 0x00000001 },
{ 0x000dc0, 3, 0x04, 0x00000000 },
{ 0x001234, 1, 0x04, 0x00000000 },
{ 0x001690, 1, 0x04, 0x00000000 },
{ 0x0012ac, 1, 0x04, 0x00000001 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x001000, 1, 0x04, 0x00000010 },
{ 0x0010fc, 1, 0x04, 0x00000000 },
{ 0x001290, 1, 0x04, 0x00000000 },
{ 0x000218, 1, 0x04, 0x00000010 },
{ 0x0012d8, 1, 0x04, 0x00000000 },
{ 0x0012dc, 1, 0x04, 0x00000010 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x00155c, 2, 0x04, 0x00000000 },
{ 0x001564, 1, 0x04, 0x00000fff },
{ 0x001574, 2, 0x04, 0x00000000 },
{ 0x00157c, 1, 0x04, 0x000fffff },
{ 0x001354, 1, 0x04, 0x00000000 },
{ 0x001610, 1, 0x04, 0x00000012 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x00260c, 1, 0x04, 0x00000000 },
{ 0x0007ac, 1, 0x04, 0x00000000 },
{ 0x00162c, 1, 0x04, 0x00000003 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000324, 6, 0x04, 0x3f800000 },
{ 0x000750, 1, 0x04, 0x00000000 },
{ 0x000760, 1, 0x04, 0x39291909 },
{ 0x000764, 1, 0x04, 0x79695949 },
{ 0x000768, 1, 0x04, 0xb9a99989 },
{ 0x00076c, 1, 0x04, 0xf9e9d9c9 },
{ 0x000770, 1, 0x04, 0x30201000 },
{ 0x000774, 1, 0x04, 0x70605040 },
{ 0x000778, 1, 0x04, 0x00009080 },
{ 0x000780, 1, 0x04, 0x39291909 },
{ 0x000784, 1, 0x04, 0x79695949 },
{ 0x000788, 1, 0x04, 0xb9a99989 },
{ 0x00078c, 1, 0x04, 0xf9e9d9c9 },
{ 0x0007d0, 1, 0x04, 0x30201000 },
{ 0x0007d4, 1, 0x04, 0x70605040 },
{ 0x0007d8, 1, 0x04, 0x00009080 },
{ 0x00037c, 1, 0x04, 0x00000001 },
{ 0x000740, 2, 0x04, 0x00000000 },
{ 0x002600, 1, 0x04, 0x00000000 },
{ 0x001918, 1, 0x04, 0x00000000 },
{ 0x00191c, 1, 0x04, 0x00000900 },
{ 0x001920, 1, 0x04, 0x00000405 },
{ 0x001308, 1, 0x04, 0x00000001 },
{ 0x001924, 1, 0x04, 0x00000000 },
{ 0x0013ac, 1, 0x04, 0x00000000 },
{ 0x00192c, 1, 0x04, 0x00000001 },
{ 0x00193c, 1, 0x04, 0x00002c1c },
{ 0x000d7c, 1, 0x04, 0x00000000 },
{ 0x000f8c, 1, 0x04, 0x00000000 },
{ 0x0002c0, 1, 0x04, 0x00000001 },
{ 0x001510, 1, 0x04, 0x00000000 },
{ 0x001940, 1, 0x04, 0x00000000 },
{ 0x000ff4, 2, 0x04, 0x00000000 },
{ 0x00194c, 2, 0x04, 0x00000000 },
{ 0x001968, 1, 0x04, 0x00000000 },
{ 0x001590, 1, 0x04, 0x0000003f },
{ 0x0007e8, 4, 0x04, 0x00000000 },
{ 0x00196c, 1, 0x04, 0x00000011 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x00197c, 1, 0x04, 0x00000000 },
{ 0x000fcc, 2, 0x04, 0x00000000 },
{ 0x0002d8, 1, 0x04, 0x00000040 },
{ 0x001980, 1, 0x04, 0x00000080 },
{ 0x001504, 1, 0x04, 0x00000080 },
{ 0x001984, 1, 0x04, 0x00000000 },
{ 0x000300, 1, 0x04, 0x00000001 },
{ 0x0013a8, 1, 0x04, 0x00000000 },
{ 0x0012ec, 1, 0x04, 0x00000000 },
{ 0x001310, 1, 0x04, 0x00000000 },
{ 0x001314, 1, 0x04, 0x00000001 },
{ 0x001380, 1, 0x04, 0x00000000 },
{ 0x001384, 4, 0x04, 0x00000001 },
{ 0x001394, 1, 0x04, 0x00000000 },
{ 0x00139c, 1, 0x04, 0x00000000 },
{ 0x001398, 1, 0x04, 0x00000000 },
{ 0x001594, 1, 0x04, 0x00000000 },
{ 0x001598, 4, 0x04, 0x00000001 },
{ 0x000f54, 3, 0x04, 0x00000000 },
{ 0x0019bc, 1, 0x04, 0x00000000 },
{ 0x000f9c, 2, 0x04, 0x00000000 },
{ 0x0012cc, 1, 0x04, 0x00000000 },
{ 0x0012e8, 1, 0x04, 0x00000000 },
{ 0x00130c, 1, 0x04, 0x00000001 },
{ 0x001360, 8, 0x04, 0x00000000 },
{ 0x00133c, 2, 0x04, 0x00000001 },
{ 0x001344, 1, 0x04, 0x00000002 },
{ 0x001348, 2, 0x04, 0x00000001 },
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
{ 0x0019c8, 1, 0x04, 0x00001500 },
{ 0x00135c, 1, 0x04, 0x00000000 },
{ 0x000f90, 1, 0x04, 0x00000000 },
{ 0x0019e0, 8, 0x04, 0x00000001 },
{ 0x0019cc, 1, 0x04, 0x00000001 },
{ 0x0015b8, 1, 0x04, 0x00000000 },
{ 0x001a00, 1, 0x04, 0x00001111 },
{ 0x001a04, 7, 0x04, 0x00000000 },
{ 0x000d6c, 2, 0x04, 0xffff0000 },
{ 0x0010f8, 1, 0x04, 0x00001010 },
{ 0x000d80, 5, 0x04, 0x00000000 },
{ 0x000da0, 1, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x001508, 1, 0x04, 0x80000000 },
{ 0x00150c, 1, 0x04, 0x40000000 },
{ 0x001668, 1, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000008 },
{ 0x000d9c, 1, 0x04, 0x00000001 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x00000020 },
{ 0x0007dc, 1, 0x04, 0x00000000 },
{ 0x00074c, 1, 0x04, 0x00000055 },
{ 0x001420, 1, 0x04, 0x00000003 },
{ 0x0017bc, 2, 0x04, 0x00000000 },
{ 0x0017c4, 1, 0x04, 0x00000001 },
{ 0x001008, 1, 0x04, 0x00000008 },
{ 0x00100c, 1, 0x04, 0x00000040 },
{ 0x001010, 1, 0x04, 0x0000012c },
{ 0x000d60, 1, 0x04, 0x00000040 },
{ 0x00075c, 1, 0x04, 0x00000003 },
{ 0x001018, 1, 0x04, 0x00000020 },
{ 0x00101c, 1, 0x04, 0x00000001 },
{ 0x001020, 1, 0x04, 0x00000020 },
{ 0x001024, 1, 0x04, 0x00000001 },
{ 0x001444, 3, 0x04, 0x00000000 },
{ 0x000360, 1, 0x04, 0x20164010 },
{ 0x000364, 1, 0x04, 0x00000020 },
{ 0x000368, 1, 0x04, 0x00000000 },
{ 0x000de4, 1, 0x04, 0x00000000 },
{ 0x000204, 1, 0x04, 0x00000006 },
{ 0x000208, 1, 0x04, 0x00000000 },
{ 0x0002cc, 2, 0x04, 0x003fffff },
{ 0x001220, 1, 0x04, 0x00000005 },
{ 0x000fdc, 1, 0x04, 0x00000000 },
{ 0x000f98, 1, 0x04, 0x00400008 },
{ 0x001284, 1, 0x04, 0x08000080 },
{ 0x001450, 1, 0x04, 0x00400008 },
{ 0x001454, 1, 0x04, 0x08000080 },
{ 0x000214, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gk104_grctx_pack_mthd[] = {
{ gk104_grctx_init_a097_0, 0xa097 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_fe_0[] = {
{ 0x404010, 5, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 1, 0x04, 0x00000000 },
{ 0x4040a8, 8, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf800008f },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x4041a0, 4, 0x04, 0x00000000 },
{ 0x404200, 4, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000014 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00003fff },
{ 0x404610, 1, 0x04, 0x00000100 },
{ 0x404618, 4, 0x04, 0x00000000 },
{ 0x40462c, 2, 0x04, 0x00000000 },
{ 0x404640, 1, 0x04, 0x00000000 },
{ 0x404654, 1, 0x04, 0x00000000 },
{ 0x404660, 1, 0x04, 0x00000000 },
{ 0x404678, 1, 0x04, 0x00000000 },
{ 0x40467c, 1, 0x04, 0x00000002 },
{ 0x404680, 8, 0x04, 0x00000000 },
{ 0x4046a0, 1, 0x04, 0x007f0080 },
{ 0x4046a4, 8, 0x04, 0x00000000 },
{ 0x4046c8, 3, 0x04, 0x00000000 },
{ 0x404700, 3, 0x04, 0x00000000 },
{ 0x404718, 7, 0x04, 0x00000000 },
{ 0x404734, 1, 0x04, 0x00000100 },
{ 0x404738, 2, 0x04, 0x00000000 },
{ 0x404744, 2, 0x04, 0x00000000 },
{ 0x404754, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x004103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 2, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x801a00f0 },
{ 0x4064c4, 1, 0x04, 0x0192ffff },
{ 0x4064c8, 1, 0x04, 0x01800600 },
{ 0x4064cc, 9, 0x04, 0x00000000 },
{ 0x4064fc, 1, 0x04, 0x0000022a },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_sked_0[] = {
{ 0x407040, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000030 },
{ 0x40800c, 2, 0x04, 0x00000000 },
{ 0x408014, 1, 0x04, 0x00000069 },
{ 0x408018, 1, 0x04, 0xe100e100 },
{ 0x408064, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
{ 0x408840, 1, 0x04, 0x0000000b },
{ 0x408900, 1, 0x04, 0x3080b801 },
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c8102f },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
const struct gf100_gr_pack
gk104_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gk104_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gk104_grctx_init_ds_0 },
{ gk104_grctx_init_cwd_0 },
{ gk104_grctx_init_pd_0 },
{ gk104_grctx_init_sked_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gk104_grctx_init_be_0 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100018 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
{ 0x418c6c, 1, 0x04, 0x00000001 },
{ 0x418c80, 1, 0x04, 0x20200004 },
{ 0x418c8c, 1, 0x04, 0x00000001 },
{}
};
static const struct gf100_gr_pack
gk104_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gk104_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
static const struct gf100_gr_pack
gk104_grctx_pack_gpc_1[] = {
{ gf119_grctx_init_crstr_0 },
{ gk104_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x0000c000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00003203 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000402 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000007f },
{ 0x419e50, 19, 0x04, 0x00000000 },
{ 0x419eac, 1, 0x04, 0x00001f8f },
{ 0x419eb0, 1, 0x04, 0x00000d3f },
{ 0x419ec8, 1, 0x04, 0x0001304f },
{ 0x419f30, 8, 0x04, 0x00000000 },
{ 0x419f58, 1, 0x04, 0x00000000 },
{ 0x419f70, 1, 0x04, 0x00000000 },
{ 0x419f78, 1, 0x04, 0x0000000b },
{ 0x419f7c, 1, 0x04, 0x0000027c },
{}
};
const struct gf100_gr_pack
gk104_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk104_grctx_init_tex_0 },
{ gk104_grctx_init_mpc_0 },
{ gk104_grctx_init_l1c_0 },
{ gk104_grctx_init_sm_0 },
{}
};
const struct gf100_gr_init
gk104_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000006 },
{}
};
static const struct gf100_gr_init
gk104_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x06480430 },
{}
};
const struct gf100_gr_pack
gk104_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gk104_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gk104_grctx_generate_r418800(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
/*XXX: Not real sure where to apply these, there doesn't seem
* to be any pattern to which chipsets it's done on.
*
* Perhaps a VBIOS tweak?
*/
if (0) {
nvkm_mask(device, 0x418800, 0x00200000, 0x00200000);
nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000);
}
}
void
gk104_grctx_generate_patch_ltc(struct gf100_gr_chan *chan)
{
struct nvkm_device *device = chan->gr->base.engine.subdev.device;
u32 data0 = nvkm_rd32(device, 0x17e91c);
u32 data1 = nvkm_rd32(device, 0x17e920);
/*XXX: Figure out how to modify this correctly! */
gf100_grctx_patch_wr32(chan, 0x17e91c, data0);
gf100_grctx_patch_wr32(chan, 0x17e920, data1);
}
void
gk104_grctx_generate_bundle(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
const struct gf100_grctx_func *grctx = chan->gr->func->grctx;
const u32 state_limit = min(grctx->bundle_min_gpm_fifo_depth, size / 0x20);
const u32 token_limit = grctx->bundle_token_limit;
gf100_grctx_generate_bundle(chan, addr, size);
gf100_grctx_patch_wr32(chan, 0x4064c8, (state_limit << 16) | token_limit);
}
void
gk104_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
gf100_grctx_generate_pagepool(chan, addr);
gf100_grctx_patch_wr32(chan, 0x4064cc, 0x80000000);
}
void
gk104_grctx_generate_unkn(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001);
nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
}
static void
gk104_grctx_generate_r419f78(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
/* bit 3 set disables loads in fp helper invocations, we need it enabled */
nvkm_mask(device, 0x419f78, 0x00000009, 0x00000000);
}
void
gk104_grctx_generate_gpc_tpc_nr(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
}
void
gk104_grctx_generate_alpha_beta_tables(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int i, j, gpc, ppc;
for (i = 0; i < 32; i++) {
u32 atarget = max_t(u32, gr->tpc_total * i / 32, 1);
u32 btarget = gr->tpc_total - atarget;
bool alpha = atarget < btarget;
u64 amask = 0, bmask = 0;
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {
u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc];
u32 abits, bbits, pmask;
if (alpha) {
abits = atarget ? ppc_tpcs : 0;
bbits = ppc_tpcs - abits;
} else {
bbits = btarget ? ppc_tpcs : 0;
abits = ppc_tpcs - bbits;
}
pmask = gr->ppc_tpc_mask[gpc][ppc];
while (ppc_tpcs-- > abits)
pmask &= pmask - 1;
amask |= (u64)pmask << (gpc * 8);
pmask ^= gr->ppc_tpc_mask[gpc][ppc];
bmask |= (u64)pmask << (gpc * 8);
atarget -= min(abits, atarget);
btarget -= min(bbits, btarget);
if ((abits > 0) || (bbits > 0))
alpha = !alpha;
}
}
for (j = 0; j < gr->gpc_nr; j += 4, amask >>= 32, bmask >>= 32) {
nvkm_wr32(device, 0x406800 + (i * 0x20) + j, amask);
nvkm_wr32(device, 0x406c00 + (i * 0x20) + j, bmask);
}
}
}
const struct gf100_grctx_func
gk104_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk104_grctx_pack_hub,
.gpc_0 = gk104_grctx_pack_gpc_0,
.gpc_1 = gk104_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk104_grctx_pack_tpc,
.ppc = gk104_grctx_pack_ppc,
.icmd = gk104_grctx_pack_icmd,
.mthd = gk104_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
.alpha_nr = 0x648,
.patch_ltc = gk104_grctx_generate_patch_ltc,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.r419f78 = gk104_grctx_generate_r419f78,
.r418800 = gk104_grctx_generate_r418800,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <subdev/timer.h>
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gk208_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
{ 0x400090, 1, 0x04, 0x00000030 },
{ 0x40013c, 1, 0x04, 0x003901f7 },
{ 0x400140, 1, 0x04, 0x00000100 },
{ 0x400144, 1, 0x04, 0x00000000 },
{ 0x400148, 1, 0x04, 0x00000110 },
{ 0x400138, 1, 0x04, 0x00000000 },
{ 0x400130, 2, 0x04, 0x00000000 },
{ 0x400124, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_init
gk208_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gk208_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
{ 0x418384, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk208_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000201 },
{}
};
static const struct gf100_gr_init
gk208_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{ 0x419ab4, 1, 0x04, 0x00000000 },
{ 0x419aa8, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk208_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00b08bea },
{ 0x419c84, 1, 0x04, 0x00010384 },
{ 0x419cbc, 1, 0x04, 0x281b3646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00000230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gk208_gr_pack_mmio[] = {
{ gk208_gr_init_main_0 },
{ gk110_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gk208_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gk110_gr_init_sked_0 },
{ gk110_gr_init_cwd_0 },
{ gf119_gr_init_prop_0 },
{ gk208_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gk208_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gk110_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gk104_gr_init_gpc_unk_2 },
{ gk104_gr_init_tpccs_0 },
{ gk208_gr_init_tex_0 },
{ gk104_gr_init_pe_0 },
{ gk208_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gk110_gr_init_sm_0 },
{ gf117_gr_init_pes_0 },
{ gf117_gr_init_wwdx_0 },
{ gf117_gr_init_cbm_0 },
{ gk104_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
#include "fuc/hubgk208.fuc5.h"
static struct gf100_gr_ucode
gk208_gr_fecs_ucode = {
.code.data = gk208_grhub_code,
.code.size = sizeof(gk208_grhub_code),
.data.data = gk208_grhub_data,
.data.size = sizeof(gk208_grhub_data),
};
#include "fuc/gpcgk208.fuc5.h"
static struct gf100_gr_ucode
gk208_gr_gpccs_ucode = {
.code.data = gk208_grgpc_code,
.code.size = sizeof(gk208_grgpc_code),
.data.data = gk208_grgpc_data,
.data.size = sizeof(gk208_grgpc_data),
};
static const struct gf100_gr_func
gk208_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gk208_gr_pack_mmio,
.fecs.ucode = &gk208_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gk208_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 1,
.grctx = &gk208_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, KEPLER_B, &gf100_fermi },
{ -1, -1, KEPLER_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gk208_gr_fwif[] = {
{ -1, gf100_gr_load, &gk208_gr },
{ -1, gf100_gr_nofw, &gk208_gr },
{}
};
int
gk208_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk208_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c |
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf100_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000b2, 40, 0x01, 0x00000000 },
{ 0x000210, 8, 0x01, 0x00000040 },
{ 0x000218, 8, 0x01, 0x0000c080 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00001fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x003fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x0005e0, 5, 0x01, 0x00000022 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x00000c48 },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00300008 },
{ 0x000841, 1, 0x01, 0x04000080 },
{ 0x000842, 1, 0x01, 0x00300008 },
{ 0x000843, 1, 0x01, 0x04000080 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x000944, 1, 0x01, 0x00000022 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_icmd[] = {
{ gf100_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
{ 0x00080c, 8, 0x40, 0x00000300 },
{ 0x000810, 1, 0x04, 0x000000cf },
{ 0x000850, 7, 0x40, 0x00000000 },
{ 0x000814, 8, 0x40, 0x00000040 },
{ 0x000818, 8, 0x40, 0x00000001 },
{ 0x00081c, 8, 0x40, 0x00000000 },
{ 0x000820, 8, 0x40, 0x00000000 },
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x002710, 8, 0x20, 0x00014000 },
{ 0x002714, 8, 0x20, 0x00000040 },
{ 0x001c00, 16, 0x10, 0x00000000 },
{ 0x001c04, 16, 0x10, 0x00000000 },
{ 0x001c08, 16, 0x10, 0x00000000 },
{ 0x001c0c, 16, 0x10, 0x00000000 },
{ 0x001d00, 16, 0x10, 0x00000000 },
{ 0x001d04, 16, 0x10, 0x00000000 },
{ 0x001d08, 16, 0x10, 0x00000000 },
{ 0x001d0c, 16, 0x10, 0x00000000 },
{ 0x001f00, 16, 0x08, 0x00000000 },
{ 0x001f04, 16, 0x08, 0x00000000 },
{ 0x001f80, 16, 0x08, 0x00000000 },
{ 0x001f84, 16, 0x08, 0x00000000 },
{ 0x002200, 5, 0x10, 0x00000022 },
{ 0x002000, 1, 0x04, 0x00000000 },
{ 0x002040, 1, 0x04, 0x00000011 },
{ 0x002080, 1, 0x04, 0x00000020 },
{ 0x0020c0, 1, 0x04, 0x00000030 },
{ 0x002100, 1, 0x04, 0x00000040 },
{ 0x002140, 1, 0x04, 0x00000051 },
{ 0x00200c, 6, 0x40, 0x00000001 },
{ 0x002010, 1, 0x04, 0x00000000 },
{ 0x002050, 1, 0x04, 0x00000000 },
{ 0x002090, 1, 0x04, 0x00000001 },
{ 0x0020d0, 1, 0x04, 0x00000002 },
{ 0x002110, 1, 0x04, 0x00000003 },
{ 0x002150, 1, 0x04, 0x00000004 },
{ 0x000380, 4, 0x20, 0x00000000 },
{ 0x000384, 4, 0x20, 0x00000000 },
{ 0x000388, 4, 0x20, 0x00000000 },
{ 0x00038c, 4, 0x20, 0x00000000 },
{ 0x000700, 4, 0x10, 0x00000000 },
{ 0x000704, 4, 0x10, 0x00000000 },
{ 0x000708, 4, 0x10, 0x00000000 },
{ 0x002800, 128, 0x04, 0x00000000 },
{ 0x000a00, 16, 0x20, 0x00000000 },
{ 0x000a04, 16, 0x20, 0x00000000 },
{ 0x000a08, 16, 0x20, 0x00000000 },
{ 0x000a0c, 16, 0x20, 0x00000000 },
{ 0x000a10, 16, 0x20, 0x00000000 },
{ 0x000a14, 16, 0x20, 0x00000000 },
{ 0x000c00, 16, 0x10, 0x00000000 },
{ 0x000c04, 16, 0x10, 0x00000000 },
{ 0x000c08, 16, 0x10, 0x00000000 },
{ 0x000c0c, 16, 0x10, 0x3f800000 },
{ 0x000d00, 8, 0x08, 0xffff0000 },
{ 0x000d04, 8, 0x08, 0xffff0000 },
{ 0x000e00, 16, 0x10, 0x00000000 },
{ 0x000e04, 16, 0x10, 0xffff0000 },
{ 0x000e08, 16, 0x10, 0xffff0000 },
{ 0x000d40, 4, 0x08, 0x00000000 },
{ 0x000d44, 4, 0x08, 0x00000000 },
{ 0x001e00, 8, 0x20, 0x00000001 },
{ 0x001e04, 8, 0x20, 0x00000001 },
{ 0x001e08, 8, 0x20, 0x00000002 },
{ 0x001e0c, 8, 0x20, 0x00000001 },
{ 0x001e10, 8, 0x20, 0x00000001 },
{ 0x001e14, 8, 0x20, 0x00000002 },
{ 0x001e18, 8, 0x20, 0x00000001 },
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x001514, 1, 0x04, 0x00000000 },
{ 0x000d68, 1, 0x04, 0x0000ffff },
{ 0x00121c, 1, 0x04, 0x0fac6881 },
{ 0x000fac, 1, 0x04, 0x00000001 },
{ 0x001538, 1, 0x04, 0x00000001 },
{ 0x000fe0, 2, 0x04, 0x00000000 },
{ 0x000fe8, 1, 0x04, 0x00000014 },
{ 0x000fec, 1, 0x04, 0x00000040 },
{ 0x000ff0, 1, 0x04, 0x00000000 },
{ 0x00179c, 1, 0x04, 0x00000000 },
{ 0x001228, 1, 0x04, 0x00000400 },
{ 0x00122c, 1, 0x04, 0x00000300 },
{ 0x001230, 1, 0x04, 0x00010001 },
{ 0x0007f8, 1, 0x04, 0x00000000 },
{ 0x0015b4, 1, 0x04, 0x00000001 },
{ 0x0015cc, 1, 0x04, 0x00000000 },
{ 0x001534, 1, 0x04, 0x00000000 },
{ 0x000fb0, 1, 0x04, 0x00000000 },
{ 0x0015d0, 1, 0x04, 0x00000000 },
{ 0x00153c, 1, 0x04, 0x00000000 },
{ 0x0016b4, 1, 0x04, 0x00000003 },
{ 0x000fbc, 4, 0x04, 0x0000ffff },
{ 0x000df8, 2, 0x04, 0x00000000 },
{ 0x001948, 1, 0x04, 0x00000000 },
{ 0x001970, 1, 0x04, 0x00000001 },
{ 0x00161c, 1, 0x04, 0x000009f0 },
{ 0x000dcc, 1, 0x04, 0x00000010 },
{ 0x00163c, 1, 0x04, 0x00000000 },
{ 0x0015e4, 1, 0x04, 0x00000000 },
{ 0x001160, 32, 0x04, 0x25e00040 },
{ 0x001880, 32, 0x04, 0x00000000 },
{ 0x000f84, 2, 0x04, 0x00000000 },
{ 0x0017c8, 2, 0x04, 0x00000000 },
{ 0x0017d0, 1, 0x04, 0x000000ff },
{ 0x0017d4, 1, 0x04, 0xffffffff },
{ 0x0017d8, 1, 0x04, 0x00000002 },
{ 0x0017dc, 1, 0x04, 0x00000000 },
{ 0x0015f4, 2, 0x04, 0x00000000 },
{ 0x001434, 2, 0x04, 0x00000000 },
{ 0x000d74, 1, 0x04, 0x00000000 },
{ 0x000dec, 1, 0x04, 0x00000001 },
{ 0x0013a4, 1, 0x04, 0x00000000 },
{ 0x001318, 1, 0x04, 0x00000001 },
{ 0x001644, 1, 0x04, 0x00000000 },
{ 0x000748, 1, 0x04, 0x00000000 },
{ 0x000de8, 1, 0x04, 0x00000000 },
{ 0x001648, 1, 0x04, 0x00000000 },
{ 0x0012a4, 1, 0x04, 0x00000000 },
{ 0x001120, 4, 0x04, 0x00000000 },
{ 0x001118, 1, 0x04, 0x00000000 },
{ 0x00164c, 1, 0x04, 0x00000000 },
{ 0x001658, 1, 0x04, 0x00000000 },
{ 0x001910, 1, 0x04, 0x00000290 },
{ 0x001518, 1, 0x04, 0x00000000 },
{ 0x00165c, 1, 0x04, 0x00000001 },
{ 0x001520, 1, 0x04, 0x00000000 },
{ 0x001604, 1, 0x04, 0x00000000 },
{ 0x001570, 1, 0x04, 0x00000000 },
{ 0x0013b0, 2, 0x04, 0x3f800000 },
{ 0x00020c, 1, 0x04, 0x00000000 },
{ 0x001670, 1, 0x04, 0x30201000 },
{ 0x001674, 1, 0x04, 0x70605040 },
{ 0x001678, 1, 0x04, 0xb8a89888 },
{ 0x00167c, 1, 0x04, 0xf8e8d8c8 },
{ 0x00166c, 1, 0x04, 0x00000000 },
{ 0x001680, 1, 0x04, 0x00ffff00 },
{ 0x0012d0, 1, 0x04, 0x00000003 },
{ 0x0012d4, 1, 0x04, 0x00000002 },
{ 0x001684, 2, 0x04, 0x00000000 },
{ 0x000dac, 2, 0x04, 0x00001b02 },
{ 0x000db4, 1, 0x04, 0x00000000 },
{ 0x00168c, 1, 0x04, 0x00000000 },
{ 0x0015bc, 1, 0x04, 0x00000000 },
{ 0x00156c, 1, 0x04, 0x00000000 },
{ 0x00187c, 1, 0x04, 0x00000000 },
{ 0x001110, 1, 0x04, 0x00000001 },
{ 0x000dc0, 3, 0x04, 0x00000000 },
{ 0x001234, 1, 0x04, 0x00000000 },
{ 0x001690, 1, 0x04, 0x00000000 },
{ 0x0012ac, 1, 0x04, 0x00000001 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x001000, 1, 0x04, 0x00000010 },
{ 0x0010fc, 1, 0x04, 0x00000000 },
{ 0x001290, 1, 0x04, 0x00000000 },
{ 0x000218, 1, 0x04, 0x00000010 },
{ 0x0012d8, 1, 0x04, 0x00000000 },
{ 0x0012dc, 1, 0x04, 0x00000010 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x00155c, 2, 0x04, 0x00000000 },
{ 0x001564, 1, 0x04, 0x00001fff },
{ 0x001574, 2, 0x04, 0x00000000 },
{ 0x00157c, 1, 0x04, 0x003fffff },
{ 0x001354, 1, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{ 0x001610, 1, 0x04, 0x00000012 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x00162c, 1, 0x04, 0x00000003 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000324, 6, 0x04, 0x3f800000 },
{ 0x000750, 1, 0x04, 0x00000000 },
{ 0x000760, 1, 0x04, 0x39291909 },
{ 0x000764, 1, 0x04, 0x79695949 },
{ 0x000768, 1, 0x04, 0xb9a99989 },
{ 0x00076c, 1, 0x04, 0xf9e9d9c9 },
{ 0x000770, 1, 0x04, 0x30201000 },
{ 0x000774, 1, 0x04, 0x70605040 },
{ 0x000778, 1, 0x04, 0x00009080 },
{ 0x000780, 1, 0x04, 0x39291909 },
{ 0x000784, 1, 0x04, 0x79695949 },
{ 0x000788, 1, 0x04, 0xb9a99989 },
{ 0x00078c, 1, 0x04, 0xf9e9d9c9 },
{ 0x0007d0, 1, 0x04, 0x30201000 },
{ 0x0007d4, 1, 0x04, 0x70605040 },
{ 0x0007d8, 1, 0x04, 0x00009080 },
{ 0x00037c, 1, 0x04, 0x00000001 },
{ 0x000740, 2, 0x04, 0x00000000 },
{ 0x002600, 1, 0x04, 0x00000000 },
{ 0x001918, 1, 0x04, 0x00000000 },
{ 0x00191c, 1, 0x04, 0x00000900 },
{ 0x001920, 1, 0x04, 0x00000405 },
{ 0x001308, 1, 0x04, 0x00000001 },
{ 0x001924, 1, 0x04, 0x00000000 },
{ 0x0013ac, 1, 0x04, 0x00000000 },
{ 0x00192c, 1, 0x04, 0x00000001 },
{ 0x00193c, 1, 0x04, 0x00002c1c },
{ 0x000d7c, 1, 0x04, 0x00000000 },
{ 0x000f8c, 1, 0x04, 0x00000000 },
{ 0x0002c0, 1, 0x04, 0x00000001 },
{ 0x001510, 1, 0x04, 0x00000000 },
{ 0x001940, 1, 0x04, 0x00000000 },
{ 0x000ff4, 2, 0x04, 0x00000000 },
{ 0x00194c, 2, 0x04, 0x00000000 },
{ 0x001968, 1, 0x04, 0x00000000 },
{ 0x001590, 1, 0x04, 0x0000003f },
{ 0x0007e8, 4, 0x04, 0x00000000 },
{ 0x00196c, 1, 0x04, 0x00000011 },
{ 0x00197c, 1, 0x04, 0x00000000 },
{ 0x000fcc, 2, 0x04, 0x00000000 },
{ 0x0002d8, 1, 0x04, 0x00000040 },
{ 0x001980, 1, 0x04, 0x00000080 },
{ 0x001504, 1, 0x04, 0x00000080 },
{ 0x001984, 1, 0x04, 0x00000000 },
{ 0x000300, 1, 0x04, 0x00000001 },
{ 0x0013a8, 1, 0x04, 0x00000000 },
{ 0x0012ec, 1, 0x04, 0x00000000 },
{ 0x001310, 1, 0x04, 0x00000000 },
{ 0x001314, 1, 0x04, 0x00000001 },
{ 0x001380, 1, 0x04, 0x00000000 },
{ 0x001384, 4, 0x04, 0x00000001 },
{ 0x001394, 1, 0x04, 0x00000000 },
{ 0x00139c, 1, 0x04, 0x00000000 },
{ 0x001398, 1, 0x04, 0x00000000 },
{ 0x001594, 1, 0x04, 0x00000000 },
{ 0x001598, 4, 0x04, 0x00000001 },
{ 0x000f54, 3, 0x04, 0x00000000 },
{ 0x0019bc, 1, 0x04, 0x00000000 },
{ 0x000f9c, 2, 0x04, 0x00000000 },
{ 0x0012cc, 1, 0x04, 0x00000000 },
{ 0x0012e8, 1, 0x04, 0x00000000 },
{ 0x00130c, 1, 0x04, 0x00000001 },
{ 0x001360, 8, 0x04, 0x00000000 },
{ 0x00133c, 2, 0x04, 0x00000001 },
{ 0x001344, 1, 0x04, 0x00000002 },
{ 0x001348, 2, 0x04, 0x00000001 },
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
{ 0x0019c8, 1, 0x04, 0x00001500 },
{ 0x00135c, 1, 0x04, 0x00000000 },
{ 0x000f90, 1, 0x04, 0x00000000 },
{ 0x0019e0, 8, 0x04, 0x00000001 },
{ 0x0019cc, 1, 0x04, 0x00000001 },
{ 0x0015b8, 1, 0x04, 0x00000000 },
{ 0x001a00, 1, 0x04, 0x00001111 },
{ 0x001a04, 7, 0x04, 0x00000000 },
{ 0x000d6c, 2, 0x04, 0xffff0000 },
{ 0x0010f8, 1, 0x04, 0x00001010 },
{ 0x000d80, 5, 0x04, 0x00000000 },
{ 0x000da0, 1, 0x04, 0x00000000 },
{ 0x001508, 1, 0x04, 0x80000000 },
{ 0x00150c, 1, 0x04, 0x40000000 },
{ 0x001668, 1, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000008 },
{ 0x000d9c, 1, 0x04, 0x00000001 },
{ 0x0007dc, 1, 0x04, 0x00000000 },
{ 0x00074c, 1, 0x04, 0x00000055 },
{ 0x001420, 1, 0x04, 0x00000003 },
{ 0x0017bc, 2, 0x04, 0x00000000 },
{ 0x0017c4, 1, 0x04, 0x00000001 },
{ 0x001008, 1, 0x04, 0x00000008 },
{ 0x00100c, 1, 0x04, 0x00000040 },
{ 0x001010, 1, 0x04, 0x0000012c },
{ 0x000d60, 1, 0x04, 0x00000040 },
{ 0x00075c, 1, 0x04, 0x00000003 },
{ 0x001018, 1, 0x04, 0x00000020 },
{ 0x00101c, 1, 0x04, 0x00000001 },
{ 0x001020, 1, 0x04, 0x00000020 },
{ 0x001024, 1, 0x04, 0x00000001 },
{ 0x001444, 3, 0x04, 0x00000000 },
{ 0x000360, 1, 0x04, 0x20164010 },
{ 0x000364, 1, 0x04, 0x00000020 },
{ 0x000368, 1, 0x04, 0x00000000 },
{ 0x000de4, 1, 0x04, 0x00000000 },
{ 0x000204, 1, 0x04, 0x00000006 },
{ 0x000208, 1, 0x04, 0x00000000 },
{ 0x0002cc, 1, 0x04, 0x003fffff },
{ 0x0002d0, 1, 0x04, 0x00000c48 },
{ 0x001220, 1, 0x04, 0x00000005 },
{ 0x000fdc, 1, 0x04, 0x00000000 },
{ 0x000f98, 1, 0x04, 0x00300008 },
{ 0x001284, 1, 0x04, 0x04000080 },
{ 0x001450, 1, 0x04, 0x00300008 },
{ 0x001454, 1, 0x04, 0x04000080 },
{ 0x000214, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_902d_0[] = {
{ 0x000200, 1, 0x04, 0x000000cf },
{ 0x000204, 1, 0x04, 0x00000001 },
{ 0x000208, 1, 0x04, 0x00000020 },
{ 0x00020c, 1, 0x04, 0x00000001 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000214, 1, 0x04, 0x00000080 },
{ 0x000218, 2, 0x04, 0x00000100 },
{ 0x000220, 2, 0x04, 0x00000000 },
{ 0x000230, 1, 0x04, 0x000000cf },
{ 0x000234, 1, 0x04, 0x00000001 },
{ 0x000238, 1, 0x04, 0x00000020 },
{ 0x00023c, 1, 0x04, 0x00000001 },
{ 0x000244, 1, 0x04, 0x00000080 },
{ 0x000248, 2, 0x04, 0x00000100 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_9039_0[] = {
{ 0x00030c, 3, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000238, 2, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_90c0_0[] = {
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x000758, 1, 0x04, 0x00000100 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x000204, 3, 0x04, 0x00000000 },
{ 0x000214, 1, 0x04, 0x00000000 },
{ 0x00024c, 1, 0x04, 0x00000000 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_mthd[] = {
{ gf100_grctx_init_9097_0, 0x9097 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_main_0[] = {
{ 0x400204, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_fe_0[] = {
{ 0x404004, 11, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf0000087 },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x404168, 1, 0x04, 0x00000000 },
{ 0x404174, 3, 0x04, 0x00000000 },
{ 0x404200, 8, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_pri_0[] = {
{ 0x404404, 14, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
{ 0x404468, 1, 0x04, 0x00ffffff },
{ 0x40446c, 1, 0x04, 0x00000000 },
{ 0x404480, 1, 0x04, 0x00000001 },
{ 0x404498, 1, 0x04, 0x00000001 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000015 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00002e00 },
{ 0x404610, 1, 0x04, 0x00000100 },
{ 0x404618, 8, 0x04, 0x00000000 },
{ 0x404638, 1, 0x04, 0x00000004 },
{ 0x40463c, 8, 0x04, 0x00000000 },
{ 0x40465c, 1, 0x04, 0x007f0100 },
{ 0x404660, 7, 0x04, 0x00000000 },
{ 0x40467c, 1, 0x04, 0x00000002 },
{ 0x404680, 8, 0x04, 0x00000000 },
{ 0x4046a0, 1, 0x04, 0x007f0080 },
{ 0x4046a4, 18, 0x04, 0x00000000 },
{ 0x4046f0, 2, 0x04, 0x00000000 },
{ 0x404700, 13, 0x04, 0x00000000 },
{ 0x404734, 1, 0x04, 0x00000100 },
{ 0x404738, 8, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x078000bf },
{ 0x405830, 1, 0x04, 0x02180000 },
{ 0x405834, 2, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000023 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
{ 0x407814, 1, 0x04, 0x020398a4 },
{ 0x407818, 1, 0x04, 0x0e629062 },
{ 0x40781c, 1, 0x04, 0x0a418820 },
{ 0x407820, 1, 0x04, 0x000000e6 },
{ 0x4078bc, 1, 0x04, 0x00000103 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000018 },
{ 0x40800c, 2, 0x04, 0x00000000 },
{ 0x408014, 1, 0x04, 0x00000069 },
{ 0x408018, 1, 0x04, 0xe100e100 },
{ 0x408064, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x0003e00d },
{ 0x408900, 1, 0x04, 0x3080b801 },
{ 0x408904, 1, 0x04, 0x02000001 },
{ 0x408908, 1, 0x04, 0x00c80929 },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf100_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf100_grctx_init_ds_0 },
{ gf100_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf100_grctx_init_be_0 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x41840c, 1, 0x04, 0x00001008 },
{ 0x418410, 1, 0x04, 0x0fff0fff },
{ 0x418414, 1, 0x04, 0x00200fff },
{ 0x418450, 6, 0x04, 0x00000000 },
{ 0x418468, 1, 0x04, 0x00000001 },
{ 0x41846c, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 1, 0x04, 0x00000000 },
{ 0x41870c, 1, 0x04, 0x07c80000 },
{ 0x418710, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x00000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x00100000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_zcull_0[] = {
{ 0x41891c, 1, 0x04, 0x00ff00ff },
{ 0x418924, 1, 0x04, 0x00000000 },
{ 0x418928, 1, 0x04, 0x00ffff00 },
{ 0x41892c, 1, 0x04, 0x0000ff00 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000000 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
{ 0x418b10, 1, 0x04, 0x020398a4 },
{ 0x418b14, 1, 0x04, 0x0e629062 },
{ 0x418b18, 1, 0x04, 0x0a418820 },
{ 0x418b1c, 1, 0x04, 0x000000e6 },
{ 0x418bb8, 1, 0x04, 0x00000103 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c80, 1, 0x04, 0x20200004 },
{ 0x418c8c, 1, 0x04, 0x00000001 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_gcc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf100_grctx_init_prop_0 },
{ gf100_grctx_init_gpc_unk_1 },
{ gf100_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_gpc_1[] = {
{ gf100_grctx_init_crstr_0 },
{ gf100_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_zcullr_0[] = {
{ 0x418a00, 3, 0x04, 0x00000000 },
{ 0x418a0c, 1, 0x04, 0x00010000 },
{ 0x418a10, 3, 0x04, 0x00000000 },
{ 0x418a20, 3, 0x04, 0x00000000 },
{ 0x418a2c, 1, 0x04, 0x00010000 },
{ 0x418a30, 3, 0x04, 0x00000000 },
{ 0x418a40, 3, 0x04, 0x00000000 },
{ 0x418a4c, 1, 0x04, 0x00010000 },
{ 0x418a50, 3, 0x04, 0x00000000 },
{ 0x418a60, 3, 0x04, 0x00000000 },
{ 0x418a6c, 1, 0x04, 0x00010000 },
{ 0x418a70, 3, 0x04, 0x00000000 },
{ 0x418a80, 3, 0x04, 0x00000000 },
{ 0x418a8c, 1, 0x04, 0x00010000 },
{ 0x418a90, 3, 0x04, 0x00000000 },
{ 0x418aa0, 3, 0x04, 0x00000000 },
{ 0x418aac, 1, 0x04, 0x00010000 },
{ 0x418ab0, 3, 0x04, 0x00000000 },
{ 0x418ac0, 3, 0x04, 0x00000000 },
{ 0x418acc, 1, 0x04, 0x00010000 },
{ 0x418ad0, 3, 0x04, 0x00000000 },
{ 0x418ae0, 3, 0x04, 0x00000000 },
{ 0x418aec, 1, 0x04, 0x00010000 },
{ 0x418af0, 3, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_zcull[] = {
{ gf100_grctx_init_zcullr_0 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x0000012a },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
{ 0x419b0c, 1, 0x04, 0x0e629062 },
{ 0x419b10, 1, 0x04, 0x0a418820 },
{ 0x419b14, 1, 0x04, 0x000000e6 },
{ 0x419bd0, 1, 0x04, 0x00900103 },
{ 0x419be0, 1, 0x04, 0x00000001 },
{ 0x419be4, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00060048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
const struct gf100_gr_init
gf100_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
static const struct gf100_gr_init
gf100_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419f50, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gf100_grctx_pack_tpc[] = {
{ gf100_grctx_init_pe_0 },
{ gf100_grctx_init_tex_0 },
{ gf100_grctx_init_wwdx_0 },
{ gf100_grctx_init_mpc_0 },
{ gf100_grctx_init_l1c_0 },
{ gf100_grctx_init_tpccs_0 },
{ gf100_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gf100_grctx_patch_wr32(struct gf100_gr_chan *chan, u32 addr, u32 data)
{
if (unlikely(!chan->mmio)) {
nvkm_wr32(chan->gr->base.engine.subdev.device, addr, data);
return;
}
nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
}
void
gf100_grctx_generate_r419cb8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419cb8, 0x00007c00, 0x00000000);
}
void
gf100_grctx_generate_bundle(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gf100_grctx_patch_wr32(chan, 0x408004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408008, 0x80000000 | (size >> 8));
gf100_grctx_patch_wr32(chan, 0x418808, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x41880c, 0x80000000 | (size >> 8));
}
void
gf100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408010, 0x80000000);
gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
}
void
gf100_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 attrib = grctx->attrib_nr;
int gpc, tpc;
u32 bo = 0;
gf100_grctx_patch_wr32(chan, 0x405830, (attrib << 16));
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
gf100_grctx_patch_wr32(chan, o, (attrib << 16) | bo);
bo += grctx->attrib_nr_max;
}
}
}
void
gf100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gf100_grctx_patch_wr32(chan, 0x418810, 0x80000000 | addr >> 12);
gf100_grctx_patch_wr32(chan, 0x419848, 0x10000000 | addr >> 12);
}
u32
gf100_grctx_generate_attrib_cb_size(struct gf100_gr *gr)
{
const struct gf100_grctx_func *grctx = gr->func->grctx;
return 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max) * gr->tpc_total;
}
void
gf100_grctx_generate_unkn(struct gf100_gr *gr)
{
}
void
gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u8 gpcmax = nvkm_rd32(device, 0x022430);
const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax;
int i, j, sm = 0;
u32 data;
for (i = 0; i < DIV_ROUND_UP(tpcmax, 4); i++) {
for (data = 0, j = 0; j < 4; j++) {
if (sm < gr->sm_nr)
data |= gr->sm[sm++].gpc << (j * 8);
else
data |= 0x1f << (j * 8);
}
nvkm_wr32(device, 0x4060a8 + (i * 4), data);
}
}
void
gf100_grctx_generate_rop_mapping(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data[6] = {}, data2[2] = {};
u8 shift, ntpcv;
int i;
/* Pack tile map into register format. */
for (i = 0; i < 32; i++)
data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
/* Magic. */
shift = 0;
ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
}
data2[0] = (ntpcv << 16);
data2[0] |= (shift << 21);
data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
for (i = 1; i < 7; i++)
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) |
gr->screen_tile_row_offset | data2[0]);
nvkm_wr32(device, 0x419be4, data2[1]);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x419b00 + (i * 4), data[i]);
/* UNK78xx */
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
}
void
gf100_grctx_generate_max_ways_evict(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 fbps = nvkm_rd32(device, 0x121c74);
if (fbps == 1)
nvkm_mask(device, 0x17e91c, 0x001f0000, 0x00090000);
}
static const u32
gf100_grctx_alpha_beta_map[17][32] = {
[1] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
},
[2] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
},
//XXX: 3
[4] = {
1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3, 3, 3,
},
//XXX: 5
//XXX: 6
[7] = {
1, 1, 1, 1,
2, 2, 2, 2, 2, 2,
3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4,
5, 5, 5, 5, 5, 5,
6, 6, 6, 6,
},
[8] = {
1, 1, 1,
2, 2, 2, 2, 2,
3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4,
5, 5, 5, 5, 5,
6, 6, 6, 6, 6,
7, 7, 7,
},
//XXX: 9
//XXX: 10
[11] = {
1, 1,
2, 2, 2, 2,
3, 3, 3,
4, 4, 4, 4,
5, 5, 5,
6, 6, 6,
7, 7, 7, 7,
8, 8, 8,
9, 9, 9, 9,
10, 10,
},
//XXX: 12
//XXX: 13
[14] = {
1, 1,
2, 2,
3, 3, 3,
4, 4, 4,
5, 5,
6, 6, 6,
7, 7,
8, 8, 8,
9, 9,
10, 10, 10,
11, 11, 11,
12, 12,
13, 13,
},
[15] = {
1, 1,
2, 2,
3, 3,
4, 4, 4,
5, 5,
6, 6, 6,
7, 7,
8, 8,
9, 9, 9,
10, 10,
11, 11, 11,
12, 12,
13, 13,
14, 14,
},
[16] = {
1, 1,
2, 2,
3, 3,
4, 4,
5, 5,
6, 6, 6,
7, 7,
8, 8,
9, 9,
10, 10, 10,
11, 11,
12, 12,
13, 13,
14, 14,
15, 15,
},
};
void
gf100_grctx_generate_alpha_beta_tables(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
int i, gpc;
for (i = 0; i < 32; i++) {
u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i];
u32 abits[GPC_MAX] = {}, amask = 0, bmask = 0;
if (!atarget) {
nvkm_warn(subdev, "missing alpha/beta mapping table\n");
atarget = max_t(u32, gr->tpc_total * i / 32, 1);
}
while (atarget) {
for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) {
if (abits[gpc] < gr->tpc_nr[gpc]) {
abits[gpc]++;
atarget--;
}
}
}
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
u32 bbits = gr->tpc_nr[gpc] - abits[gpc];
amask |= ((1 << abits[gpc]) - 1) << (gpc * 8);
bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8);
}
nvkm_wr32(device, 0x406800 + (i * 0x20), amask);
nvkm_wr32(device, 0x406c00 + (i * 0x20), bmask);
}
}
void
gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]);
}
void
gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), sm);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}
void
gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
{
const struct gf100_grctx_func *func = gr->func->grctx;
int sm;
for (sm = 0; sm < gr->sm_nr; sm++) {
func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm);
if (func->tpc_nr)
func->tpc_nr(gr, gr->sm[sm].gpc);
}
gf100_gr_init_num_tpc_per_gpc(gr, false, true);
if (!func->skip_pd_num_tpc_per_gpc)
gf100_gr_init_num_tpc_per_gpc(gr, true, false);
if (func->r4060a8)
func->r4060a8(gr);
func->rop_mapping(gr);
if (func->alpha_beta_tables)
func->alpha_beta_tables(gr);
if (func->max_ways_evict)
func->max_ways_evict(gr);
if (func->dist_skip_table)
func->dist_skip_table(gr);
if (func->r406500)
func->r406500(gr);
if (func->gpc_tpc_nr)
func->gpc_tpc_nr(gr);
if (func->r419f78)
func->r419f78(gr);
if (func->tpc_mask)
func->tpc_mask(gr);
if (func->smid_config)
func->smid_config(gr);
}
void
gf100_grctx_generate_main(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
nvkm_mc_unk260(device, 0);
if (!gr->sw_ctx) {
gf100_gr_mmio(gr, grctx->hub);
gf100_gr_mmio(gr, grctx->gpc_0);
gf100_gr_mmio(gr, grctx->zcull);
gf100_gr_mmio(gr, grctx->gpc_1);
gf100_gr_mmio(gr, grctx->tpc);
gf100_gr_mmio(gr, grctx->ppc);
} else {
gf100_gr_mmio(gr, gr->sw_ctx);
}
if (gr->func->init_419bd8)
gr->func->init_419bd8(gr);
if (grctx->r419ea8)
grctx->r419ea8(gr);
gf100_gr_wait_idle(gr);
idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(chan, chan->bundle_cb->addr, grctx->bundle_size);
grctx->attrib_cb(chan, chan->attrib_cb->addr, grctx->attrib_cb_size(gr));
grctx->attrib(chan);
if (grctx->patch_ltc)
grctx->patch_ltc(chan);
if (grctx->unknown_size)
grctx->unknown(chan, chan->unknown->addr, grctx->unknown_size);
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
gf100_gr_wait_idle(gr);
if (grctx->r400088) grctx->r400088(gr, false);
if (gr->bundle)
gf100_gr_icmd(gr, gr->bundle);
else
gf100_gr_icmd(gr, grctx->icmd);
if (gr->bundle_veid)
gf100_gr_icmd(gr, gr->bundle_veid);
else
gf100_gr_icmd(gr, grctx->sw_veid_bundle_init);
if (gr->bundle64)
gf100_gr_icmd(gr, gr->bundle64);
else
if (grctx->sw_bundle64_init)
gf100_gr_icmd(gr, grctx->sw_bundle64_init);
if (grctx->r400088) grctx->r400088(gr, true);
nvkm_wr32(device, 0x404154, idle_timeout);
if (gr->method)
gf100_gr_mthd(gr, gr->method);
else
gf100_gr_mthd(gr, grctx->mthd);
nvkm_mc_unk260(device, 1);
if (grctx->r419cb8)
grctx->r419cb8(gr);
if (grctx->r418800)
grctx->r418800(gr);
if (grctx->r419eb0)
grctx->r419eb0(gr);
if (grctx->r419e00)
grctx->r419e00(gr);
if (grctx->r418e94)
grctx->r418e94(gr);
if (grctx->r419a3c)
grctx->r419a3c(gr);
if (grctx->r408840)
grctx->r408840(gr);
if (grctx->r419c0c)
grctx->r419c0c(gr);
gf100_gr_wait_idle(gr);
}
#define CB_RESERVED 0x80000
int
gf100_grctx_generate(struct gf100_gr *gr, struct gf100_gr_chan *chan, struct nvkm_gpuobj *inst)
{
const struct gf100_grctx_func *grctx = gr->func->grctx;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_memory *data = NULL;
struct nvkm_vma *ctx = NULL;
int ret, i;
u64 addr;
/* NV_PGRAPH_FE_PWR_MODE_FORCE_ON. */
nvkm_wr32(device, 0x404170, 0x00000012);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x404170) & 0x00000010))
break;
);
if (grctx->unkn88c)
grctx->unkn88c(gr, true);
/* Reset FECS. */
gr->func->fecs.reset(gr);
if (grctx->unkn88c)
grctx->unkn88c(gr, false);
/* NV_PGRAPH_FE_PWR_MODE_AUTO. */
nvkm_wr32(device, 0x404170, 0x00000010);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x404170) & 0x00000010))
break;
);
/* Init SCC RAM. */
nvkm_wr32(device, 0x40802c, 0x00000001);
/* Allocate memory to store context, and dummy global context buffers. */
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
CB_RESERVED + gr->size, 0, true, &data);
if (ret)
goto done;
ret = nvkm_vmm_get(chan->vmm, 0, nvkm_memory_size(data), &ctx);
if (ret)
goto done;
ret = nvkm_memory_map(data, 0, chan->vmm, ctx, NULL, 0);
if (ret)
goto done;
/* Setup context pointer. */
nvkm_kmap(inst);
nvkm_wo32(inst, 0x0210, lower_32_bits(ctx->addr + CB_RESERVED) | 4);
nvkm_wo32(inst, 0x0214, upper_32_bits(ctx->addr + CB_RESERVED));
nvkm_done(inst);
/* Make channel current. */
addr = inst->addr >> 12;
if (gr->firmware) {
ret = gf100_gr_fecs_bind_pointer(gr, 0x80000000 | addr);
if (ret)
goto done_inst;
nvkm_kmap(data);
nvkm_wo32(data, 0x1c, 1);
nvkm_wo32(data, 0x20, 0);
nvkm_wo32(data, 0x28, 0);
nvkm_wo32(data, 0x2c, 0);
nvkm_done(data);
} else {
nvkm_wr32(device, 0x409840, 0x80000000);
nvkm_wr32(device, 0x409500, 0x80000000 | addr);
nvkm_wr32(device, 0x409504, 0x00000001);
nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) & 0x80000000)
break;
);
}
grctx->main(chan);
if (!gr->firmware) {
/* Trigger a context unload by unsetting the "next channel valid" bit
* and faking a context switch interrupt.
*/
nvkm_mask(device, 0x409b04, 0x80000000, 0x00000000);
nvkm_wr32(device, 0x409000, 0x00000100);
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x409b00) & 0x80000000))
break;
) < 0) {
ret = -EBUSY;
goto done_inst;
}
} else {
ret = gf100_gr_fecs_wfi_golden_save(gr, 0x80000000 | addr);
if (ret)
goto done_inst;
nvkm_mask(device, 0x409b00, 0x80000000, 0x00000000);
}
gr->data = kmalloc(gr->size, GFP_KERNEL);
if (gr->data) {
nvkm_kmap(data);
for (i = 0; i < gr->size; i += 4)
gr->data[i / 4] = nvkm_ro32(data, CB_RESERVED + i);
nvkm_done(data);
ret = 0;
} else {
ret = -ENOMEM;
}
done_inst:
nvkm_kmap(inst);
nvkm_wo32(inst, 0x0210, 0);
nvkm_wo32(inst, 0x0214, 0);
nvkm_done(inst);
done:
nvkm_vmm_put(chan->vmm, &ctx);
nvkm_memory_unref(&data);
return ret;
}
const struct gf100_grctx_func
gf100_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gf100_grctx_generate_unkn,
.hub = gf100_grctx_pack_hub,
.gpc_0 = gf100_grctx_pack_gpc_0,
.gpc_1 = gf100_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf100_grctx_pack_tpc,
.icmd = gf100_grctx_pack_icmd,
.mthd = gf100_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf100_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <subdev/timer.h>
#include <nvif/class.h>
static const struct nvkm_bitfield nv50_gr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
{ 0x00000008, "UNK3" },
{ 0x00000010, "UNK4" },
{ 0x00000020, "UNK5" },
{ 0x00000040, "M2MF" },
{ 0x00000080, "UNK7" },
{ 0x00000100, "CTXPROG" },
{ 0x00000200, "VFETCH" },
{ 0x00000400, "CCACHE_PREGEOM" },
{ 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
{ 0x00001000, "VCLIP" },
{ 0x00002000, "RATTR_APLANE" },
{ 0x00004000, "TRAST" },
{ 0x00008000, "CLIPID" },
{ 0x00010000, "ZCULL" },
{ 0x00020000, "ENG2D" },
{ 0x00040000, "RMASK" },
{ 0x00080000, "TPC_RAST" },
{ 0x00100000, "TPC_PROP" },
{ 0x00200000, "TPC_TEX" },
{ 0x00400000, "TPC_GEOM" },
{ 0x00800000, "TPC_MP" },
{ 0x01000000, "ROP" },
{}
};
static const struct nvkm_bitfield
nv50_gr_vstatus_0[] = {
{ 0x01, "VFETCH" },
{ 0x02, "CCACHE" },
{ 0x04, "PREGEOM" },
{ 0x08, "POSTGEOM" },
{ 0x10, "VATTR" },
{ 0x20, "STRMOUT" },
{ 0x40, "VCLIP" },
{}
};
static const struct nvkm_bitfield
nv50_gr_vstatus_1[] = {
{ 0x01, "TPC_RAST" },
{ 0x02, "TPC_PROP" },
{ 0x04, "TPC_TEX" },
{ 0x08, "TPC_GEOM" },
{ 0x10, "TPC_MP" },
{}
};
static const struct nvkm_bitfield
nv50_gr_vstatus_2[] = {
{ 0x01, "RATTR" },
{ 0x02, "APLANE" },
{ 0x04, "TRAST" },
{ 0x08, "CLIPID" },
{ 0x10, "ZCULL" },
{ 0x20, "ENG2D" },
{ 0x40, "RMASK" },
{ 0x80, "ROP" },
{}
};
static void
nvkm_gr_vstatus_print(struct nv50_gr *gr, int r,
const struct nvkm_bitfield *units, u32 status)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
u32 stat = status;
u8 mask = 0x00;
char msg[64];
int i;
for (i = 0; units[i].name && status; i++) {
if ((status & 7) == 1)
mask |= (1 << i);
status >>= 3;
}
nvkm_snprintbf(msg, sizeof(msg), units, mask);
nvkm_error(subdev, "PGRAPH_VSTATUS%d: %08x [%s]\n", r, stat, msg);
}
int
g84_gr_tlb_flush(struct nvkm_gr *base)
{
struct nv50_gr *gr = nv50_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_timer *tmr = device->timer;
bool idle, timeout = false;
unsigned long flags;
char status[128];
u64 start;
u32 tmp;
spin_lock_irqsave(&gr->lock, flags);
nvkm_mask(device, 0x400500, 0x00000001, 0x00000000);
start = nvkm_timer_read(tmr);
do {
idle = true;
for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
} while (!idle &&
!(timeout = nvkm_timer_read(tmr) - start > 2000000000));
if (timeout) {
nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n");
tmp = nvkm_rd32(device, 0x400700);
nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp);
nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status);
nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0,
nvkm_rd32(device, 0x400380));
nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1,
nvkm_rd32(device, 0x400384));
nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2,
nvkm_rd32(device, 0x400388));
}
nvkm_wr32(device, 0x100c80, 0x00000001);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x100c80) & 0x00000001))
break;
);
nvkm_mask(device, 0x400500, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&gr->lock, flags);
return timeout ? -EBUSY : 0;
}
static const struct nvkm_gr_func
g84_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{ -1, -1, G82_TESLA, &nv50_gr_object },
{}
}
};
int
g84_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&g84_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
const struct gf100_gr_init
gf108_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
{ 0x418384, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf108_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{}
};
static const struct gf100_gr_init
gf108_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf108_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
{ 0x419850, 4, 0x04, 0x00000000 },
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_pack
gf108_gr_pack_mmio[] = {
{ gf100_gr_init_main_0 },
{ gf100_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gf104_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gf100_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf100_gr_init_gpm_0 },
{ gf108_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gf100_gr_init_tpccs_0 },
{ gf104_gr_init_tex_0 },
{ gf108_gr_init_pe_0 },
{ gf100_gr_init_l1c_0 },
{ gf100_gr_init_wwdx_0 },
{ gf100_gr_init_tpccs_1 },
{ gf100_gr_init_mpc_0 },
{ gf104_gr_init_sm_0 },
{ gf100_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static void
gf108_gr_init_r405a14(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x405a14, 0x80000000);
}
static const struct gf100_gr_func
gf108_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_r405a14 = gf108_gr_init_r405a14,
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_40601c = gf100_gr_init_40601c,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gf100_gr_init_419eb4,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gf108_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gf100_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.grctx = &gf108_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
{ -1, -1, FERMI_A, &gf100_fermi },
{ -1, -1, FERMI_B, &gf100_fermi },
{ -1, -1, FERMI_COMPUTE_A },
{}
}
};
static const struct gf100_gr_fwif
gf108_gr_fwif[] = {
{ -1, gf100_gr_load, &gf108_gr },
{ -1, gf100_gr_nofw, &gf108_gr },
{}
};
int
gf108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf108_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "ctxgf100.h"
static void
tu102_grctx_generate_r419c0c(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000);
nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000);
nvkm_mask(device, 0x400080, 0x00000000, 0x00000000);
}
static void
tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
}
static const struct gf100_gr_init
tu102_grctx_init_unknown_bundle_init_0[] = {
{ 0x00001000, 1, 0x00000001, 0x00000004 },
{ 0x00002020, 64, 0x00000001, 0x00000000 },
{ 0x0001e100, 1, 0x00000001, 0x00000001 },
{}
};
static const struct gf100_gr_pack
tu102_grctx_pack_sw_bundle64_init[] = {
{ tu102_grctx_init_unknown_bundle_init_0, .type = 64 },
{}
};
void
tu102_grctx_generate_unknown(struct gf100_gr_chan *chan, u64 addr, u32 size)
{
gf100_grctx_patch_wr32(chan, 0x408070, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408074, size >> 8); /*XXX: guess */
gf100_grctx_patch_wr32(chan, 0x419034, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408078, 0x00000000);
}
const struct gf100_grctx_func
tu102_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gv100_grctx_generate_unkn,
.sw_bundle64_init = tu102_grctx_pack_sw_bundle64_init,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0xa80,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gv100_grctx_generate_attrib_cb,
.attrib = gv100_grctx_generate_attrib,
.attrib_nr_max = 0x800,
.attrib_nr = 0x700,
.unknown_size = 0x80000,
.unknown = tu102_grctx_generate_unknown,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xfa8,
.sm_id = tu102_grctx_generate_sm_id,
.skip_pd_num_tpc_per_gpc = true,
.rop_mapping = gv100_grctx_generate_rop_mapping,
.r406500 = gm200_grctx_generate_r406500,
.r400088 = gv100_grctx_generate_r400088,
.r419c0c = tu102_grctx_generate_r419c0c,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <nvif/class.h>
static const struct nvkm_gr_func
gt215_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.tlb_flush = g84_gr_tlb_flush,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{ -1, -1, GT214_TESLA, &nv50_gr_object },
{ -1, -1, GT214_COMPUTE, &nv50_gr_object },
{}
}
};
int
gt215_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(>215_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
const struct gf100_gr_init
gf104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x00000000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0007f440 },
{}
};
const struct gf100_gr_init
gf104_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
const struct gf100_gr_init
gf104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00011110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf104_grctx_pack_tpc[] = {
{ gf100_grctx_init_pe_0 },
{ gf104_grctx_init_tex_0 },
{ gf100_grctx_init_wwdx_0 },
{ gf100_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf100_grctx_init_tpccs_0 },
{ gf104_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gf104_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gf100_grctx_generate_unkn,
.hub = gf100_grctx_pack_hub,
.gpc_0 = gf100_grctx_pack_gpc_0,
.gpc_1 = gf100_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf104_grctx_pack_tpc,
.icmd = gf100_grctx_pack_icmd,
.mthd = gf100_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf100_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gk110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x0002f2, 2, 0x01, 0x00000001 },
{ 0x0002f5, 1, 0x01, 0x00000001 },
{ 0x0002f7, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000383, 1, 0x01, 0x00000011 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000662, 1, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x00080b, 1, 0x01, 0x00000002 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x000a0d, 1, 0x01, 0x00000006 },
{ 0x00097d, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x003fffff },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00400008 },
{ 0x000841, 1, 0x01, 0x08000080 },
{ 0x000842, 1, 0x01, 0x00400008 },
{ 0x000843, 1, 0x01, 0x08000080 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000008 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00000fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x000fffff },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x000a04, 1, 0x01, 0x000000ff },
{ 0x000a0b, 1, 0x01, 0x00000040 },
{ 0x00097f, 1, 0x01, 0x00000100 },
{ 0x000a02, 1, 0x01, 0x00000001 },
{ 0x000809, 1, 0x01, 0x00000007 },
{ 0x00c221, 1, 0x01, 0x00000040 },
{ 0x00c401, 1, 0x01, 0x00000001 },
{ 0x00c402, 1, 0x01, 0x00010001 },
{ 0x00c403, 2, 0x01, 0x00000001 },
{ 0x00c40e, 1, 0x01, 0x00000020 },
{ 0x00c500, 1, 0x01, 0x00000003 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x000b07, 1, 0x01, 0x00000002 },
{ 0x000b08, 2, 0x01, 0x00000100 },
{ 0x000b0a, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_icmd[] = {
{ gk110_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_a197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
{ 0x00080c, 8, 0x40, 0x00000300 },
{ 0x000810, 1, 0x04, 0x000000cf },
{ 0x000850, 7, 0x40, 0x00000000 },
{ 0x000814, 8, 0x40, 0x00000040 },
{ 0x000818, 8, 0x40, 0x00000001 },
{ 0x00081c, 8, 0x40, 0x00000000 },
{ 0x000820, 8, 0x40, 0x00000000 },
{ 0x001c00, 16, 0x10, 0x00000000 },
{ 0x001c04, 16, 0x10, 0x00000000 },
{ 0x001c08, 16, 0x10, 0x00000000 },
{ 0x001c0c, 16, 0x10, 0x00000000 },
{ 0x001d00, 16, 0x10, 0x00000000 },
{ 0x001d04, 16, 0x10, 0x00000000 },
{ 0x001d08, 16, 0x10, 0x00000000 },
{ 0x001d0c, 16, 0x10, 0x00000000 },
{ 0x001f00, 16, 0x08, 0x00000000 },
{ 0x001f04, 16, 0x08, 0x00000000 },
{ 0x001f80, 16, 0x08, 0x00000000 },
{ 0x001f84, 16, 0x08, 0x00000000 },
{ 0x002000, 1, 0x04, 0x00000000 },
{ 0x002040, 1, 0x04, 0x00000011 },
{ 0x002080, 1, 0x04, 0x00000020 },
{ 0x0020c0, 1, 0x04, 0x00000030 },
{ 0x002100, 1, 0x04, 0x00000040 },
{ 0x002140, 1, 0x04, 0x00000051 },
{ 0x00200c, 6, 0x40, 0x00000001 },
{ 0x002010, 1, 0x04, 0x00000000 },
{ 0x002050, 1, 0x04, 0x00000000 },
{ 0x002090, 1, 0x04, 0x00000001 },
{ 0x0020d0, 1, 0x04, 0x00000002 },
{ 0x002110, 1, 0x04, 0x00000003 },
{ 0x002150, 1, 0x04, 0x00000004 },
{ 0x000380, 4, 0x20, 0x00000000 },
{ 0x000384, 4, 0x20, 0x00000000 },
{ 0x000388, 4, 0x20, 0x00000000 },
{ 0x00038c, 4, 0x20, 0x00000000 },
{ 0x000700, 4, 0x10, 0x00000000 },
{ 0x000704, 4, 0x10, 0x00000000 },
{ 0x000708, 4, 0x10, 0x00000000 },
{ 0x002800, 128, 0x04, 0x00000000 },
{ 0x000a00, 16, 0x20, 0x00000000 },
{ 0x000a04, 16, 0x20, 0x00000000 },
{ 0x000a08, 16, 0x20, 0x00000000 },
{ 0x000a0c, 16, 0x20, 0x00000000 },
{ 0x000a10, 16, 0x20, 0x00000000 },
{ 0x000a14, 16, 0x20, 0x00000000 },
{ 0x000c00, 16, 0x10, 0x00000000 },
{ 0x000c04, 16, 0x10, 0x00000000 },
{ 0x000c08, 16, 0x10, 0x00000000 },
{ 0x000c0c, 16, 0x10, 0x3f800000 },
{ 0x000d00, 8, 0x08, 0xffff0000 },
{ 0x000d04, 8, 0x08, 0xffff0000 },
{ 0x000e00, 16, 0x10, 0x00000000 },
{ 0x000e04, 16, 0x10, 0xffff0000 },
{ 0x000e08, 16, 0x10, 0xffff0000 },
{ 0x000d40, 4, 0x08, 0x00000000 },
{ 0x000d44, 4, 0x08, 0x00000000 },
{ 0x001e00, 8, 0x20, 0x00000001 },
{ 0x001e04, 8, 0x20, 0x00000001 },
{ 0x001e08, 8, 0x20, 0x00000002 },
{ 0x001e0c, 8, 0x20, 0x00000001 },
{ 0x001e10, 8, 0x20, 0x00000001 },
{ 0x001e14, 8, 0x20, 0x00000002 },
{ 0x001e18, 8, 0x20, 0x00000001 },
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x001514, 1, 0x04, 0x00000000 },
{ 0x000d68, 1, 0x04, 0x0000ffff },
{ 0x00121c, 1, 0x04, 0x0fac6881 },
{ 0x000fac, 1, 0x04, 0x00000001 },
{ 0x001538, 1, 0x04, 0x00000001 },
{ 0x000fe0, 2, 0x04, 0x00000000 },
{ 0x000fe8, 1, 0x04, 0x00000014 },
{ 0x000fec, 1, 0x04, 0x00000040 },
{ 0x000ff0, 1, 0x04, 0x00000000 },
{ 0x00179c, 1, 0x04, 0x00000000 },
{ 0x001228, 1, 0x04, 0x00000400 },
{ 0x00122c, 1, 0x04, 0x00000300 },
{ 0x001230, 1, 0x04, 0x00010001 },
{ 0x0007f8, 1, 0x04, 0x00000000 },
{ 0x0015b4, 1, 0x04, 0x00000001 },
{ 0x0015cc, 1, 0x04, 0x00000000 },
{ 0x001534, 1, 0x04, 0x00000000 },
{ 0x000fb0, 1, 0x04, 0x00000000 },
{ 0x0015d0, 1, 0x04, 0x00000000 },
{ 0x00153c, 1, 0x04, 0x00000000 },
{ 0x0016b4, 1, 0x04, 0x00000003 },
{ 0x000fbc, 4, 0x04, 0x0000ffff },
{ 0x000df8, 2, 0x04, 0x00000000 },
{ 0x001948, 1, 0x04, 0x00000000 },
{ 0x001970, 1, 0x04, 0x00000001 },
{ 0x00161c, 1, 0x04, 0x000009f0 },
{ 0x000dcc, 1, 0x04, 0x00000010 },
{ 0x00163c, 1, 0x04, 0x00000000 },
{ 0x0015e4, 1, 0x04, 0x00000000 },
{ 0x001160, 32, 0x04, 0x25e00040 },
{ 0x001880, 32, 0x04, 0x00000000 },
{ 0x000f84, 2, 0x04, 0x00000000 },
{ 0x0017c8, 2, 0x04, 0x00000000 },
{ 0x0017d0, 1, 0x04, 0x000000ff },
{ 0x0017d4, 1, 0x04, 0xffffffff },
{ 0x0017d8, 1, 0x04, 0x00000002 },
{ 0x0017dc, 1, 0x04, 0x00000000 },
{ 0x0015f4, 2, 0x04, 0x00000000 },
{ 0x001434, 2, 0x04, 0x00000000 },
{ 0x000d74, 1, 0x04, 0x00000000 },
{ 0x000dec, 1, 0x04, 0x00000001 },
{ 0x0013a4, 1, 0x04, 0x00000000 },
{ 0x001318, 1, 0x04, 0x00000001 },
{ 0x001644, 1, 0x04, 0x00000000 },
{ 0x000748, 1, 0x04, 0x00000000 },
{ 0x000de8, 1, 0x04, 0x00000000 },
{ 0x001648, 1, 0x04, 0x00000000 },
{ 0x0012a4, 1, 0x04, 0x00000000 },
{ 0x001120, 4, 0x04, 0x00000000 },
{ 0x001118, 1, 0x04, 0x00000000 },
{ 0x00164c, 1, 0x04, 0x00000000 },
{ 0x001658, 1, 0x04, 0x00000000 },
{ 0x001910, 1, 0x04, 0x00000290 },
{ 0x001518, 1, 0x04, 0x00000000 },
{ 0x00165c, 1, 0x04, 0x00000001 },
{ 0x001520, 1, 0x04, 0x00000000 },
{ 0x001604, 1, 0x04, 0x00000000 },
{ 0x001570, 1, 0x04, 0x00000000 },
{ 0x0013b0, 2, 0x04, 0x3f800000 },
{ 0x00020c, 1, 0x04, 0x00000000 },
{ 0x001670, 1, 0x04, 0x30201000 },
{ 0x001674, 1, 0x04, 0x70605040 },
{ 0x001678, 1, 0x04, 0xb8a89888 },
{ 0x00167c, 1, 0x04, 0xf8e8d8c8 },
{ 0x00166c, 1, 0x04, 0x00000000 },
{ 0x001680, 1, 0x04, 0x00ffff00 },
{ 0x0012d0, 1, 0x04, 0x00000003 },
{ 0x0012d4, 1, 0x04, 0x00000002 },
{ 0x001684, 2, 0x04, 0x00000000 },
{ 0x000dac, 2, 0x04, 0x00001b02 },
{ 0x000db4, 1, 0x04, 0x00000000 },
{ 0x00168c, 1, 0x04, 0x00000000 },
{ 0x0015bc, 1, 0x04, 0x00000000 },
{ 0x00156c, 1, 0x04, 0x00000000 },
{ 0x00187c, 1, 0x04, 0x00000000 },
{ 0x001110, 1, 0x04, 0x00000001 },
{ 0x000dc0, 3, 0x04, 0x00000000 },
{ 0x001234, 1, 0x04, 0x00000000 },
{ 0x001690, 1, 0x04, 0x00000000 },
{ 0x0012ac, 1, 0x04, 0x00000001 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x001000, 1, 0x04, 0x00000010 },
{ 0x0010fc, 1, 0x04, 0x00000000 },
{ 0x001290, 1, 0x04, 0x00000000 },
{ 0x000218, 1, 0x04, 0x00000010 },
{ 0x0012d8, 1, 0x04, 0x00000000 },
{ 0x0012dc, 1, 0x04, 0x00000010 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x00155c, 2, 0x04, 0x00000000 },
{ 0x001564, 1, 0x04, 0x00000fff },
{ 0x001574, 2, 0x04, 0x00000000 },
{ 0x00157c, 1, 0x04, 0x000fffff },
{ 0x001354, 1, 0x04, 0x00000000 },
{ 0x001610, 1, 0x04, 0x00000012 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x00260c, 1, 0x04, 0x00000000 },
{ 0x0007ac, 1, 0x04, 0x00000000 },
{ 0x00162c, 1, 0x04, 0x00000003 },
{ 0x000210, 1, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000324, 6, 0x04, 0x3f800000 },
{ 0x000750, 1, 0x04, 0x00000000 },
{ 0x000760, 1, 0x04, 0x39291909 },
{ 0x000764, 1, 0x04, 0x79695949 },
{ 0x000768, 1, 0x04, 0xb9a99989 },
{ 0x00076c, 1, 0x04, 0xf9e9d9c9 },
{ 0x000770, 1, 0x04, 0x30201000 },
{ 0x000774, 1, 0x04, 0x70605040 },
{ 0x000778, 1, 0x04, 0x00009080 },
{ 0x000780, 1, 0x04, 0x39291909 },
{ 0x000784, 1, 0x04, 0x79695949 },
{ 0x000788, 1, 0x04, 0xb9a99989 },
{ 0x00078c, 1, 0x04, 0xf9e9d9c9 },
{ 0x0007d0, 1, 0x04, 0x30201000 },
{ 0x0007d4, 1, 0x04, 0x70605040 },
{ 0x0007d8, 1, 0x04, 0x00009080 },
{ 0x00037c, 1, 0x04, 0x00000001 },
{ 0x000740, 2, 0x04, 0x00000000 },
{ 0x002600, 1, 0x04, 0x00000000 },
{ 0x001918, 1, 0x04, 0x00000000 },
{ 0x00191c, 1, 0x04, 0x00000900 },
{ 0x001920, 1, 0x04, 0x00000405 },
{ 0x001308, 1, 0x04, 0x00000001 },
{ 0x001924, 1, 0x04, 0x00000000 },
{ 0x0013ac, 1, 0x04, 0x00000000 },
{ 0x00192c, 1, 0x04, 0x00000001 },
{ 0x00193c, 1, 0x04, 0x00002c1c },
{ 0x000d7c, 1, 0x04, 0x00000000 },
{ 0x000f8c, 1, 0x04, 0x00000000 },
{ 0x0002c0, 1, 0x04, 0x00000001 },
{ 0x001510, 1, 0x04, 0x00000000 },
{ 0x001940, 1, 0x04, 0x00000000 },
{ 0x000ff4, 2, 0x04, 0x00000000 },
{ 0x00194c, 2, 0x04, 0x00000000 },
{ 0x001968, 1, 0x04, 0x00000000 },
{ 0x001590, 1, 0x04, 0x0000003f },
{ 0x0007e8, 4, 0x04, 0x00000000 },
{ 0x00196c, 1, 0x04, 0x00000011 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x00197c, 1, 0x04, 0x00000000 },
{ 0x000fcc, 2, 0x04, 0x00000000 },
{ 0x0002d8, 1, 0x04, 0x00000040 },
{ 0x001980, 1, 0x04, 0x00000080 },
{ 0x001504, 1, 0x04, 0x00000080 },
{ 0x001984, 1, 0x04, 0x00000000 },
{ 0x000300, 1, 0x04, 0x00000001 },
{ 0x0013a8, 1, 0x04, 0x00000000 },
{ 0x0012ec, 1, 0x04, 0x00000000 },
{ 0x001310, 1, 0x04, 0x00000000 },
{ 0x001314, 1, 0x04, 0x00000001 },
{ 0x001380, 1, 0x04, 0x00000000 },
{ 0x001384, 4, 0x04, 0x00000001 },
{ 0x001394, 1, 0x04, 0x00000000 },
{ 0x00139c, 1, 0x04, 0x00000000 },
{ 0x001398, 1, 0x04, 0x00000000 },
{ 0x001594, 1, 0x04, 0x00000000 },
{ 0x001598, 4, 0x04, 0x00000001 },
{ 0x000f54, 3, 0x04, 0x00000000 },
{ 0x0019bc, 1, 0x04, 0x00000000 },
{ 0x000f9c, 2, 0x04, 0x00000000 },
{ 0x0012cc, 1, 0x04, 0x00000000 },
{ 0x0012e8, 1, 0x04, 0x00000000 },
{ 0x00130c, 1, 0x04, 0x00000001 },
{ 0x001360, 8, 0x04, 0x00000000 },
{ 0x00133c, 2, 0x04, 0x00000001 },
{ 0x001344, 1, 0x04, 0x00000002 },
{ 0x001348, 2, 0x04, 0x00000001 },
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
{ 0x0019c8, 1, 0x04, 0x00001500 },
{ 0x00135c, 1, 0x04, 0x00000000 },
{ 0x000f90, 1, 0x04, 0x00000000 },
{ 0x0019e0, 8, 0x04, 0x00000001 },
{ 0x0019cc, 1, 0x04, 0x00000001 },
{ 0x0015b8, 1, 0x04, 0x00000000 },
{ 0x001a00, 1, 0x04, 0x00001111 },
{ 0x001a04, 7, 0x04, 0x00000000 },
{ 0x000d6c, 2, 0x04, 0xffff0000 },
{ 0x0010f8, 1, 0x04, 0x00001010 },
{ 0x000d80, 5, 0x04, 0x00000000 },
{ 0x000da0, 1, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x001508, 1, 0x04, 0x80000000 },
{ 0x00150c, 1, 0x04, 0x40000000 },
{ 0x001668, 1, 0x04, 0x00000000 },
{ 0x000318, 2, 0x04, 0x00000008 },
{ 0x000d9c, 1, 0x04, 0x00000001 },
{ 0x000ddc, 1, 0x04, 0x00000002 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x00000020 },
{ 0x0007dc, 1, 0x04, 0x00000000 },
{ 0x00074c, 1, 0x04, 0x00000055 },
{ 0x001420, 1, 0x04, 0x00000003 },
{ 0x0017bc, 2, 0x04, 0x00000000 },
{ 0x0017c4, 1, 0x04, 0x00000001 },
{ 0x001008, 1, 0x04, 0x00000008 },
{ 0x00100c, 1, 0x04, 0x00000040 },
{ 0x001010, 1, 0x04, 0x0000012c },
{ 0x000d60, 1, 0x04, 0x00000040 },
{ 0x00075c, 1, 0x04, 0x00000003 },
{ 0x001018, 1, 0x04, 0x00000020 },
{ 0x00101c, 1, 0x04, 0x00000001 },
{ 0x001020, 1, 0x04, 0x00000020 },
{ 0x001024, 1, 0x04, 0x00000001 },
{ 0x001444, 3, 0x04, 0x00000000 },
{ 0x000360, 1, 0x04, 0x20164010 },
{ 0x000364, 1, 0x04, 0x00000020 },
{ 0x000368, 1, 0x04, 0x00000000 },
{ 0x000de4, 1, 0x04, 0x00000000 },
{ 0x000204, 1, 0x04, 0x00000006 },
{ 0x000208, 1, 0x04, 0x00000000 },
{ 0x0002cc, 2, 0x04, 0x003fffff },
{ 0x001220, 1, 0x04, 0x00000005 },
{ 0x000fdc, 1, 0x04, 0x00000000 },
{ 0x000f98, 1, 0x04, 0x00400008 },
{ 0x001284, 1, 0x04, 0x08000080 },
{ 0x001450, 1, 0x04, 0x00400008 },
{ 0x001454, 1, 0x04, 0x08000080 },
{ 0x000214, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_mthd[] = {
{ gk110_grctx_init_a197_0, 0xa197 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
{ 0x4040a8, 8, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf800008f },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404100, 10, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x40417c, 2, 0x04, 0x00000000 },
{ 0x4041a0, 4, 0x04, 0x00000000 },
{ 0x404200, 1, 0x04, 0x0000a197 },
{ 0x404204, 1, 0x04, 0x0000a1c0 },
{ 0x404208, 1, 0x04, 0x0000a140 },
{ 0x40420c, 1, 0x04, 0x0000902d },
{}
};
const struct gf100_gr_init
gk110_grctx_init_pri_0[] = {
{ 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
{ 0x404468, 1, 0x04, 0x00ffffff },
{ 0x40446c, 1, 0x04, 0x00000000 },
{ 0x404480, 1, 0x04, 0x00000001 },
{ 0x404498, 1, 0x04, 0x00000001 },
{}
};
const struct gf100_gr_init
gk110_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{ 0x405b20, 1, 0x04, 0x04000000 },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b0, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x802000f0 },
{ 0x4064c4, 1, 0x04, 0x0192ffff },
{ 0x4064c8, 1, 0x04, 0x018007c0 },
{ 0x4064cc, 9, 0x04, 0x00000000 },
{ 0x4064fc, 1, 0x04, 0x0000022a },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x12802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
{ 0x408840, 1, 0x04, 0x0000000b },
{ 0x408900, 1, 0x04, 0x3080b801 },
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c8102f },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gk110_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gk104_grctx_init_ds_0 },
{ gk110_grctx_init_cwd_0 },
{ gk110_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gk110_grctx_init_be_0 },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
{ 0x418810, 1, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100018 },
{}
};
const struct gf100_gr_init
gk110_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gk110_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_gpc_1[] = {
{ gf119_grctx_init_crstr_0 },
{ gk104_grctx_init_gpm_0 },
{ gk110_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct gf100_gr_init
gk110_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x0000c000 },
{ 0x419a20, 1, 0x04, 0x00020800 },
{ 0x419a30, 1, 0x04, 0x00000001 },
{ 0x419ac4, 1, 0x04, 0x0037f440 },
{}
};
const struct gf100_gr_init
gk110_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{}
};
const struct gf100_gr_init
gk110_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000007f },
{ 0x419e50, 2, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000001 },
{ 0x419e5c, 3, 0x04, 0x00000000 },
{ 0x419e68, 1, 0x04, 0x00000002 },
{ 0x419e6c, 12, 0x04, 0x00000000 },
{ 0x419eac, 1, 0x04, 0x00001f8f },
{ 0x419eb0, 1, 0x04, 0x0db00d2f },
{ 0x419eb8, 1, 0x04, 0x00000000 },
{ 0x419ec8, 1, 0x04, 0x0001304f },
{ 0x419f30, 4, 0x04, 0x00000000 },
{ 0x419f40, 1, 0x04, 0x00000018 },
{ 0x419f44, 3, 0x04, 0x00000000 },
{ 0x419f58, 1, 0x04, 0x00000000 },
{ 0x419f70, 1, 0x04, 0x00007300 },
{ 0x419f78, 1, 0x04, 0x000000eb },
{ 0x419f7c, 1, 0x04, 0x00000404 },
{}
};
static const struct gf100_gr_pack
gk110_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gk110_grctx_init_tex_0 },
{ gk110_grctx_init_mpc_0 },
{ gk110_grctx_init_l1c_0 },
{ gk110_grctx_init_sm_0 },
{}
};
static const struct gf100_gr_init
gk110_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gk110_grctx_pack_ppc[] = {
{ gk104_grctx_init_pes_0 },
{ gk110_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gk110_grctx_generate_r419eb0(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419eb0, 0x00001000, 0x00001000);
}
void
gk110_grctx_generate_r419f78(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
/* bit 3 set disables loads in fp helper invocations, we need it enabled */
nvkm_mask(device, 0x419f78, 0x00000008, 0x00000000);
}
const struct gf100_grctx_func
gk110_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gk110_grctx_pack_hub,
.gpc_0 = gk110_grctx_pack_gpc_0,
.gpc_1 = gk110_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gk110_grctx_pack_tpc,
.ppc = gk110_grctx_pack_ppc,
.icmd = gk110_grctx_pack_icmd,
.mthd = gk110_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
.pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
.alpha_nr = 0x648,
.patch_ltc = gk104_grctx_generate_patch_ltc,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.r418800 = gk104_grctx_generate_r418800,
.r419eb0 = gk110_grctx_generate_r419eb0,
.r419f78 = gk110_grctx_generate_r419f78,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <core/firmware.h>
#include <subdev/acr.h>
#include <subdev/timer.h>
#include <subdev/vfn.h>
#include <nvfw/flcn.h>
#include <nvif/class.h>
static void
ga102_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 invalid[] = { 0, 0, 0, 0 }, *color;
if (gr->zbc_color[zbc].format)
color = gr->zbc_color[zbc].l2;
else
color = invalid;
nvkm_mask(device, 0x41bcb4, 0x0000001f, zbc);
nvkm_wr32(device, 0x41bcec, color[0]);
nvkm_wr32(device, 0x41bcf0, color[1]);
nvkm_wr32(device, 0x41bcf4, color[2]);
nvkm_wr32(device, 0x41bcf8, color[3]);
}
static const struct gf100_gr_func_zbc
ga102_gr_zbc = {
.clear_color = ga102_gr_zbc_clear_color,
.clear_depth = gp100_gr_zbc_clear_depth,
.stencil_get = gp102_gr_zbc_stencil_get,
.clear_stencil = gp102_gr_zbc_clear_stencil,
};
static void
ga102_gr_gpccs_reset(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x41a610, 0x00000000);
nvkm_msec(device, 1, NVKM_DELAY);
nvkm_wr32(device, 0x41a610, 0x00000001);
}
static const struct nvkm_acr_lsf_func
ga102_gr_gpccs_acr = {
.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
.bl_entry = 0x3400,
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp108_gr_acr_bld_write,
.bld_patch = gp108_gr_acr_bld_patch,
};
static void
ga102_gr_fecs_reset(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409614, 0x00000010);
nvkm_wr32(device, 0x41a614, 0x00000020);
nvkm_usec(device, 10, NVKM_DELAY);
nvkm_wr32(device, 0x409614, 0x00000110);
nvkm_wr32(device, 0x41a614, 0x00000a20);
nvkm_usec(device, 10, NVKM_DELAY);
nvkm_rd32(device, 0x409614);
nvkm_rd32(device, 0x41a614);
}
static const struct nvkm_acr_lsf_func
ga102_gr_fecs_acr = {
.bl_entry = 0x7e00,
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp108_gr_acr_bld_write,
.bld_patch = gp108_gr_acr_bld_patch,
};
static void
ga102_gr_init_rop_exceptions(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x41bcbc, 0x40000000);
nvkm_wr32(device, 0x41bc38, 0x40000000);
nvkm_wr32(device, 0x41ac94, nvkm_rd32(device, 0x502c94));
}
static void
ga102_gr_init_40a790(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x40a790, 0xc0000000);
}
static void
ga102_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
nvkm_wr32(device, 0x418894, 0x00000000);
nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
}
static struct nvkm_intr *
ga102_gr_oneinit_intr(struct gf100_gr *gr, enum nvkm_intr_type *pvector)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
*pvector = nvkm_rd32(device, 0x400154) & 0x00000fff;
return &device->vfn->intr;
}
static int
ga102_gr_nonstall(struct gf100_gr *gr)
{
return nvkm_rd32(gr->base.engine.subdev.device, 0x400160) & 0x00000fff;
}
static const struct gf100_gr_func
ga102_gr = {
.nonstall = ga102_gr_nonstall,
.oneinit_intr = ga102_gr_oneinit_intr,
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gv100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_419bd8 = gv100_gr_init_419bd8,
.init_gpc_mmu = ga102_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = tu102_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fs = tu102_gr_init_fs,
.init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
.init_40a790 = ga102_gr_init_40a790,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_504430 = gv100_gr_init_504430,
.init_shader_exceptions = gv100_gr_init_shader_exceptions,
.init_rop_exceptions = ga102_gr_init_rop_exceptions,
.init_4188a4 = gv100_gr_init_4188a4,
.trap_mp = gv100_gr_trap_mp,
.fecs.reset = ga102_gr_fecs_reset,
.gpccs.reset = ga102_gr_gpccs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 7,
.tpc_nr = 6,
.ppc_nr = 3,
.grctx = &ga102_grctx,
.zbc = &ga102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, AMPERE_B, &gf100_fermi },
{ -1, -1, AMPERE_COMPUTE_B },
{}
}
};
MODULE_FIRMWARE("nvidia/ga102/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/ga102/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/ga102/gr/NET_img.bin");
MODULE_FIRMWARE("nvidia/ga103/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/ga103/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/ga103/gr/NET_img.bin");
MODULE_FIRMWARE("nvidia/ga104/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/ga104/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/ga104/gr/NET_img.bin");
MODULE_FIRMWARE("nvidia/ga106/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/ga106/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/ga106/gr/NET_img.bin");
MODULE_FIRMWARE("nvidia/ga107/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/ga107/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/ga107/gr/NET_img.bin");
struct netlist_region {
u32 region_id;
u32 data_size;
u32 data_offset;
};
struct netlist_image_header {
u32 version;
u32 regions;
};
struct netlist_image {
struct netlist_image_header header;
struct netlist_region regions[];
};
struct netlist_av64 {
u32 addr;
u32 data_hi;
u32 data_lo;
};
static int
ga102_gr_av64_to_init(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
{
struct gf100_gr_init *init;
struct gf100_gr_pack *pack;
int nent;
int i;
nent = (blob->size / sizeof(struct netlist_av64));
pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
if (!pack)
return -ENOMEM;
init = (void *)(pack + 2);
pack[0].init = init;
pack[0].type = 64;
for (i = 0; i < nent; i++) {
struct gf100_gr_init *ent = &init[i];
struct netlist_av64 *av = &((struct netlist_av64 *)blob->data)[i];
ent->addr = av->addr;
ent->data = ((u64)av->data_hi << 32) | av->data_lo;
ent->count = 1;
ent->pitch = 1;
}
*ppack = pack;
return 0;
}
static int
ga102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
const struct firmware *fw;
const struct netlist_image *net;
const struct netlist_region *fecs_inst = NULL;
const struct netlist_region *fecs_data = NULL;
const struct netlist_region *gpccs_inst = NULL;
const struct netlist_region *gpccs_data = NULL;
int ret, i;
ret = nvkm_firmware_get(subdev, "gr/NET_img", 0, &fw);
if (ret)
return ret;
net = (const void *)fw->data;
nvkm_debug(subdev, "netlist version %d, %d regions\n",
net->header.version, net->header.regions);
for (i = 0; i < net->header.regions; i++) {
const struct netlist_region *reg = &net->regions[i];
struct nvkm_blob blob = {
.data = (void *)fw->data + reg->data_offset,
.size = reg->data_size,
};
nvkm_debug(subdev, "\t%2d: %08x %08x\n",
reg->region_id, reg->data_offset, reg->data_size);
switch (reg->region_id) {
case 0: fecs_data = reg; break;
case 1: fecs_inst = reg; break;
case 2: gpccs_data = reg; break;
case 3: gpccs_inst = reg; break;
case 4: gk20a_gr_av_to_init(&blob, &gr->bundle); break;
case 5: gk20a_gr_aiv_to_init(&blob, &gr->sw_ctx); break;
case 7: gk20a_gr_av_to_method(&blob, &gr->method); break;
case 28: tu102_gr_av_to_init_veid(&blob, &gr->bundle_veid); break;
case 34: ga102_gr_av64_to_init(&blob, &gr->bundle64); break;
case 48: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx1); break;
case 49: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx2); break;
case 50: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx3); break;
case 51: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx4); break;
default:
break;
}
}
ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->fecs.falcon, NVKM_ACR_LSF_FECS,
"gr/fecs_", ver, fwif->fecs,
fw->data + fecs_inst->data_offset,
fecs_inst->data_size,
fw->data + fecs_data->data_offset,
fecs_data->data_size);
if (ret)
return ret;
ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->gpccs.falcon, NVKM_ACR_LSF_GPCCS,
"gr/gpccs_", ver, fwif->gpccs,
fw->data + gpccs_inst->data_offset,
gpccs_inst->data_size,
fw->data + gpccs_data->data_offset,
gpccs_data->data_size);
if (ret)
return ret;
gr->firmware = true;
nvkm_firmware_put(fw);
return 0;
}
static const struct gf100_gr_fwif
ga102_gr_fwif[] = {
{ 0, ga102_gr_load, &ga102_gr, &ga102_gr_fecs_acr, &ga102_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
ga102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(ga102_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c |
/*
* Copyright 2018 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
static const struct gf100_gr_func
gp104_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gp100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 5,
.ppc_nr = 3,
.grctx = &gp104_grctx,
.zbc = &gp102_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, PASCAL_B, &gf100_fermi },
{ -1, -1, PASCAL_COMPUTE_B },
{}
}
};
MODULE_FIRMWARE("nvidia/gp104/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp104/gr/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gp104_gr_fwif[] = {
{ 0, gm200_gr_load, &gp104_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf117_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x801a0078 },
{ 0x4064c4, 1, 0x04, 0x00c9ffff },
{ 0x4064d0, 8, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf117_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf119_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf117_grctx_init_ds_0 },
{ gf117_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf119_grctx_init_be_0 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100018 },
{}
};
static const struct gf100_gr_pack
gf117_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gf117_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
const struct gf100_gr_pack
gf117_grctx_pack_gpc_1[] = {
{ gf119_grctx_init_crstr_0 },
{ gf108_grctx_init_gpm_0 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct gf100_gr_init
gf117_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x00008000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0017f440 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3efbefbe },
{}
};
static const struct gf100_gr_pack
gf117_grctx_pack_tpc[] = {
{ gf117_grctx_init_pe_0 },
{ gf117_grctx_init_tex_0 },
{ gf117_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf119_grctx_init_sm_0 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{}
};
static const struct gf100_gr_init
gf117_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
{ 0x41bee4, 1, 0x04, 0x03240218 },
{}
};
const struct gf100_gr_init
gf117_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
{ 0x41bf0c, 1, 0x04, 0x0e629062 },
{ 0x41bf10, 1, 0x04, 0x0a418820 },
{ 0x41bf14, 1, 0x04, 0x000000e6 },
{ 0x41bfd0, 1, 0x04, 0x00900103 },
{ 0x41bfe0, 1, 0x04, 0x00400001 },
{ 0x41bfe4, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf117_grctx_pack_ppc[] = {
{ gf117_grctx_init_pes_0 },
{ gf117_grctx_init_cbm_0 },
{ gf117_grctx_init_wwdx_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int i;
for (i = 0; i < 8; i++)
nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
}
void
gf117_grctx_generate_rop_mapping(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data[6] = {}, data2[2] = {};
u8 shift, ntpcv;
int i;
/* Pack tile map into register format. */
for (i = 0; i < 32; i++)
data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5);
/* Magic. */
shift = 0;
ntpcv = gr->tpc_total;
while (!(ntpcv & (1 << 4))) {
ntpcv <<= 1;
shift++;
}
data2[0] = (ntpcv << 16);
data2[0] |= (shift << 21);
data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
for (i = 1; i < 7; i++)
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
/* GPC_BROADCAST */
nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x418b08 + (i * 4), data[i]);
/* GPC_BROADCAST.TP_BROADCAST */
nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
gr->screen_tile_row_offset | data2[0]);
nvkm_wr32(device, 0x41bfe4, data2[1]);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]);
/* UNK78xx */
nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
gr->screen_tile_row_offset);
for (i = 0; i < 6; i++)
nvkm_wr32(device, 0x40780c + (i * 4), data[i]);
}
void
gf117_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 beta = grctx->attrib_nr;
const int timeslice_mode = 1;
const int max_batches = 0xffff;
u32 bo = 0;
u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total;
int gpc, ppc;
gf100_grctx_patch_wr32(chan, 0x405830, (beta << 16) | alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {
const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
const u32 t = timeslice_mode;
const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
gf100_grctx_patch_wr32(chan, o + 0xc0, (t << 28) | (b << 16) | bo);
bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, o + 0xe4, (a << 16) | ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
}
}
}
const struct gf100_grctx_func
gf117_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gf117_grctx_pack_hub,
.gpc_0 = gf117_grctx_pack_gpc_0,
.gpc_1 = gf117_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf117_grctx_pack_tpc,
.ppc = gf117_grctx_pack_ppc,
.icmd = gf119_grctx_pack_icmd,
.mthd = gf119_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
.alpha_nr = 0x324,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.dist_skip_table = gf117_grctx_generate_dist_skip_table,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
int
nv20_gr_chan_init(struct nvkm_object *object)
{
struct nv20_gr_chan *chan = nv20_gr_chan(object);
struct nv20_gr *gr = chan->gr;
u32 inst = nvkm_memory_addr(chan->inst);
nvkm_kmap(gr->ctxtab);
nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
nvkm_done(gr->ctxtab);
return 0;
}
int
nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
{
struct nv20_gr_chan *chan = nv20_gr_chan(object);
struct nv20_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 inst = nvkm_memory_addr(chan->inst);
int chid = -1;
nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
if (nvkm_rd32(device, 0x400144) & 0x00010000)
chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
if (chan->chid == chid) {
nvkm_wr32(device, 0x400784, inst >> 4);
nvkm_wr32(device, 0x400788, 0x00000002);
nvkm_msec(device, 2000,
if (!nvkm_rd32(device, 0x400700))
break;
);
nvkm_wr32(device, 0x400144, 0x10000000);
nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
}
nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
nvkm_kmap(gr->ctxtab);
nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
nvkm_done(gr->ctxtab);
return 0;
}
void *
nv20_gr_chan_dtor(struct nvkm_object *object)
{
struct nv20_gr_chan *chan = nv20_gr_chan(object);
nvkm_memory_unref(&chan->inst);
return chan;
}
static const struct nvkm_object_func
nv20_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
nvkm_wo32(chan->inst, 0x047c, 0x00000101);
nvkm_wo32(chan->inst, 0x0490, 0x00000111);
nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
for (i = 0x04d4; i <= 0x04e0; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x04f4; i <= 0x0500; i += 4)
nvkm_wo32(chan->inst, i, 0x00080000);
for (i = 0x050c; i <= 0x0518; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x051c; i <= 0x0528; i += 4)
nvkm_wo32(chan->inst, i, 0x000105b8);
for (i = 0x052c; i <= 0x0538; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
for (i = 0x055c; i <= 0x0598; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
nvkm_wo32(chan->inst, 0x0604, 0x00004000);
nvkm_wo32(chan->inst, 0x0610, 0x00000001);
nvkm_wo32(chan->inst, 0x0618, 0x00040000);
nvkm_wo32(chan->inst, 0x061c, 0x00010000);
for (i = 0x1c1c; i <= 0x248c; i += 16) {
nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
}
nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
nvkm_wo32(chan->inst, 0x285c, 0x40000000);
nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
nvkm_wo32(chan->inst, 0x286c, 0x40000000);
nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
for (i = 0x355c; i <= 0x3578; i += 4)
nvkm_wo32(chan->inst, i, 0x001c527c);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
void
nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
{
struct nv20_gr *gr = nv20_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_fifo *fifo = device->fifo;
unsigned long flags;
nvkm_fifo_pause(fifo, &flags);
nv04_gr_idle(&gr->base);
nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
if (device->chipset != 0x34) {
nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
}
nvkm_fifo_start(fifo, &flags);
}
void
nv20_gr_intr(struct nvkm_gr *base)
{
struct nv20_gr *gr = nv20_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_chan *chan;
u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
u32 chid = (addr & 0x01f00000) >> 20;
u32 subc = (addr & 0x00070000) >> 16;
u32 mthd = (addr & 0x00001ffc);
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
chan = nvkm_chan_get_chid(&gr->base.engine, chid, &flags);
nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
chan ? chan->name : "unknown",
subc, class, mthd, data);
}
nvkm_chan_put(&chan, flags);
}
int
nv20_gr_oneinit(struct nvkm_gr *base)
{
struct nv20_gr *gr = nv20_gr(base);
return nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 32 * 4, 16,
true, &gr->ctxtab);
}
int
nv20_gr_init(struct nvkm_gr *base)
{
struct nv20_gr *gr = nv20_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 tmp, vramsz;
int i;
nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
nvkm_memory_addr(gr->ctxtab) >> 4);
if (device->chipset == 0x20) {
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
for (i = 0; i < 15; i++)
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
nvkm_msec(device, 2000,
if (!nvkm_rd32(device, 0x400700))
break;
);
} else {
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
for (i = 0; i < 32; i++)
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
nvkm_msec(device, 2000,
if (!nvkm_rd32(device, 0x400700))
break;
);
}
nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
nvkm_wr32(device, 0x40009C , 0x00000040);
if (device->chipset >= 0x25) {
nvkm_wr32(device, 0x400890, 0x00a8cfff);
nvkm_wr32(device, 0x400610, 0x304B1FB6);
nvkm_wr32(device, 0x400B80, 0x1cbd3883);
nvkm_wr32(device, 0x400B84, 0x44000000);
nvkm_wr32(device, 0x400098, 0x40000080);
nvkm_wr32(device, 0x400B88, 0x000000ff);
} else {
nvkm_wr32(device, 0x400880, 0x0008c7df);
nvkm_wr32(device, 0x400094, 0x00000005);
nvkm_wr32(device, 0x400B80, 0x45eae20e);
nvkm_wr32(device, 0x400B84, 0x24000000);
nvkm_wr32(device, 0x400098, 0x00000040);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
}
nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
/* begin RAM config */
vramsz = device->func->resource_size(device, 1) - 1;
nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
nvkm_wr32(device, 0x400820, 0);
nvkm_wr32(device, 0x400824, 0);
nvkm_wr32(device, 0x400864, vramsz - 1);
nvkm_wr32(device, 0x400868, vramsz - 1);
/* interesting.. the below overwrites some of the tile setup above.. */
nvkm_wr32(device, 0x400B20, 0x00000000);
nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
return 0;
}
void *
nv20_gr_dtor(struct nvkm_gr *base)
{
struct nv20_gr *gr = nv20_gr(base);
nvkm_memory_unref(&gr->ctxtab);
return gr;
}
int
nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv20_gr *gr;
if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
return -ENOMEM;
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
nv20_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv20_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv20_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{}
}
};
int
nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv20_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
gm200_grctx_generate_r419a3c(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419a3c, 0x00000014, 0x00000000);
}
static void
gm200_grctx_generate_r418e94(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000);
nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000);
}
void
gm200_grctx_generate_smid_config(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
u32 dist[TPC_MAX / 4] = {};
u32 gpcs[GPC_MAX] = {};
u8 sm, i;
for (sm = 0; sm < gr->sm_nr; sm++) {
const u8 gpc = gr->sm[sm].gpc;
const u8 tpc = gr->sm[sm].tpc;
dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
gpcs[gpc] |= sm << (tpc * 8);
}
for (i = 0; i < dist_nr; i++)
nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
for (i = 0; i < gr->gpc_nr; i++)
nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
}
void
gm200_grctx_generate_tpc_mask(struct gf100_gr *gr)
{
u32 tmp, i;
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * gr->func->tpc_nr);
nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp);
}
void
gm200_grctx_generate_r406500(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000);
}
void
gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 data[8] = {};
int gpc, ppc, i;
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) {
u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc];
u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc];
while (ppc_tpcs-- > gr->ppc_tpc_min)
ppc_tpcm &= ppc_tpcm - 1;
ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc];
((u8 *)data)[gpc] |= ppc_tpcm;
}
}
for (i = 0; i < ARRAY_SIZE(data); i++)
nvkm_wr32(device, 0x4064d0 + (i * 0x04), data[i]);
}
const struct gf100_grctx_func
gm200_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x780,
.pagepool = gm107_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gm107_grctx_generate_attrib_cb,
.attrib = gm107_grctx_generate_attrib,
.attrib_nr_max = 0x600,
.attrib_nr = 0x400,
.alpha_nr_max = 0x1800,
.alpha_nr = 0x1000,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.tpc_mask = gm200_grctx_generate_tpc_mask,
.smid_config = gm200_grctx_generate_smid_config,
.r418e94 = gm200_grctx_generate_r418e94,
.r419a3c = gm200_grctx_generate_r419a3c,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c |
/*
* Copyright 2016 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
static void
gp102_grctx_generate_r408840(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x408840, 0x00000003, 0x00000000);
}
void
gp102_grctx_generate_attrib(struct gf100_gr_chan *chan)
{
struct gf100_gr *gr = chan->gr;
const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr;
const u32 gfxp = grctx->gfxp_nr;
const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0;
u32 bo = ao + size;
int gpc, ppc, n = 0;
gf100_grctx_patch_wr32(chan, 0x405830, attrib);
gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_max;
const u32 gs = gfxp * gr->ppc_tpc_max;
const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0);
const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4));
if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue;
gf100_grctx_patch_wr32(chan, o + 0xc0, gs);
gf100_grctx_patch_wr32(chan, p, bs);
gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
bo += gs;
gf100_grctx_patch_wr32(chan, o + 0xe4, as);
gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
gf100_grctx_patch_wr32(chan, u, bs);
}
}
gf100_grctx_patch_wr32(chan, 0x4181e4, 0x00000100);
gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000100);
}
u32
gp102_grctx_generate_attrib_cb_size(struct gf100_gr *gr)
{
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
int gpc;
for (gpc = 0; gpc < gr->gpc_nr; gpc++)
size += grctx->gfxp_nr * gr->func->ppc_nr * gr->ppc_tpc_max;
return ((size * 0x20) + 127) & ~127;
}
const struct gf100_grctx_func
gp102_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x900,
.pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
.attrib_cb = gp100_grctx_generate_attrib_cb,
.attrib = gp102_grctx_generate_attrib,
.attrib_nr_max = 0x4b0,
.attrib_nr = 0x320,
.alpha_nr_max = 0xc00,
.alpha_nr = 0x800,
.gfxp_nr = 0xba8,
.sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table,
.r406500 = gm200_grctx_generate_r406500,
.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
.tpc_mask = gm200_grctx_generate_tpc_mask,
.smid_config = gp100_grctx_generate_smid_config,
.r419a3c = gm200_grctx_generate_r419a3c,
.r408840 = gp102_grctx_generate_r408840,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct gf100_gr_init
gf119_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
{ 0x00003d, 1, 0x01, 0x00000001 },
{ 0x0000e8, 8, 0x01, 0x00000400 },
{ 0x000078, 8, 0x01, 0x00000300 },
{ 0x000050, 1, 0x01, 0x00000011 },
{ 0x000058, 8, 0x01, 0x00000008 },
{ 0x000208, 8, 0x01, 0x00000001 },
{ 0x000081, 1, 0x01, 0x00000001 },
{ 0x000085, 1, 0x01, 0x00000004 },
{ 0x000088, 1, 0x01, 0x00000400 },
{ 0x000090, 1, 0x01, 0x00000300 },
{ 0x000098, 1, 0x01, 0x00001001 },
{ 0x0000e3, 1, 0x01, 0x00000001 },
{ 0x0000da, 1, 0x01, 0x00000001 },
{ 0x0000f8, 1, 0x01, 0x00000003 },
{ 0x0000fa, 1, 0x01, 0x00000001 },
{ 0x00009f, 4, 0x01, 0x0000ffff },
{ 0x0000b1, 1, 0x01, 0x00000001 },
{ 0x0000b2, 40, 0x01, 0x00000000 },
{ 0x000210, 8, 0x01, 0x00000040 },
{ 0x000400, 24, 0x01, 0x00000040 },
{ 0x000218, 8, 0x01, 0x0000c080 },
{ 0x000440, 24, 0x01, 0x0000c080 },
{ 0x0000ad, 1, 0x01, 0x0000013e },
{ 0x0000e1, 1, 0x01, 0x00000010 },
{ 0x000290, 16, 0x01, 0x00000000 },
{ 0x0003b0, 16, 0x01, 0x00000000 },
{ 0x0002a0, 16, 0x01, 0x00000000 },
{ 0x000420, 16, 0x01, 0x00000000 },
{ 0x0002b0, 16, 0x01, 0x00000000 },
{ 0x000430, 16, 0x01, 0x00000000 },
{ 0x0002c0, 16, 0x01, 0x00000000 },
{ 0x0004d0, 16, 0x01, 0x00000000 },
{ 0x000720, 16, 0x01, 0x00000000 },
{ 0x0008c0, 16, 0x01, 0x00000000 },
{ 0x000890, 16, 0x01, 0x00000000 },
{ 0x0008e0, 16, 0x01, 0x00000000 },
{ 0x0008a0, 16, 0x01, 0x00000000 },
{ 0x0008f0, 16, 0x01, 0x00000000 },
{ 0x00094c, 1, 0x01, 0x000000ff },
{ 0x00094d, 1, 0x01, 0xffffffff },
{ 0x00094e, 1, 0x01, 0x00000002 },
{ 0x0002ec, 1, 0x01, 0x00000001 },
{ 0x000303, 1, 0x01, 0x00000001 },
{ 0x0002e6, 1, 0x01, 0x00000001 },
{ 0x000466, 1, 0x01, 0x00000052 },
{ 0x000301, 1, 0x01, 0x3f800000 },
{ 0x000304, 1, 0x01, 0x30201000 },
{ 0x000305, 1, 0x01, 0x70605040 },
{ 0x000306, 1, 0x01, 0xb8a89888 },
{ 0x000307, 1, 0x01, 0xf8e8d8c8 },
{ 0x00030a, 1, 0x01, 0x00ffff00 },
{ 0x00030b, 1, 0x01, 0x0000001a },
{ 0x00030c, 1, 0x01, 0x00000001 },
{ 0x000318, 1, 0x01, 0x00000001 },
{ 0x000340, 1, 0x01, 0x00000000 },
{ 0x000375, 1, 0x01, 0x00000001 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x00037d, 1, 0x01, 0x00000006 },
{ 0x0003a0, 1, 0x01, 0x00000002 },
{ 0x0003aa, 1, 0x01, 0x00000001 },
{ 0x0003a9, 1, 0x01, 0x00000001 },
{ 0x000380, 1, 0x01, 0x00000001 },
{ 0x000360, 1, 0x01, 0x00000040 },
{ 0x000366, 2, 0x01, 0x00000000 },
{ 0x000368, 1, 0x01, 0x00001fff },
{ 0x000370, 2, 0x01, 0x00000000 },
{ 0x000372, 1, 0x01, 0x003fffff },
{ 0x00037a, 1, 0x01, 0x00000012 },
{ 0x0005e0, 5, 0x01, 0x00000022 },
{ 0x000619, 1, 0x01, 0x00000003 },
{ 0x000811, 1, 0x01, 0x00000003 },
{ 0x000812, 1, 0x01, 0x00000004 },
{ 0x000813, 1, 0x01, 0x00000006 },
{ 0x000814, 1, 0x01, 0x00000008 },
{ 0x000815, 1, 0x01, 0x0000000b },
{ 0x000800, 6, 0x01, 0x00000001 },
{ 0x000632, 1, 0x01, 0x00000001 },
{ 0x000633, 1, 0x01, 0x00000002 },
{ 0x000634, 1, 0x01, 0x00000003 },
{ 0x000635, 1, 0x01, 0x00000004 },
{ 0x000654, 1, 0x01, 0x3f800000 },
{ 0x000657, 1, 0x01, 0x3f800000 },
{ 0x000655, 2, 0x01, 0x3f800000 },
{ 0x0006cd, 1, 0x01, 0x3f800000 },
{ 0x0007f5, 1, 0x01, 0x3f800000 },
{ 0x0007dc, 1, 0x01, 0x39291909 },
{ 0x0007dd, 1, 0x01, 0x79695949 },
{ 0x0007de, 1, 0x01, 0xb9a99989 },
{ 0x0007df, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007e8, 1, 0x01, 0x00003210 },
{ 0x0007e9, 1, 0x01, 0x00007654 },
{ 0x0007ea, 1, 0x01, 0x00000098 },
{ 0x0007ec, 1, 0x01, 0x39291909 },
{ 0x0007ed, 1, 0x01, 0x79695949 },
{ 0x0007ee, 1, 0x01, 0xb9a99989 },
{ 0x0007ef, 1, 0x01, 0xf9e9d9c9 },
{ 0x0007f0, 1, 0x01, 0x00003210 },
{ 0x0007f1, 1, 0x01, 0x00007654 },
{ 0x0007f2, 1, 0x01, 0x00000098 },
{ 0x0005a5, 1, 0x01, 0x00000001 },
{ 0x000980, 128, 0x01, 0x00000000 },
{ 0x000468, 1, 0x01, 0x00000004 },
{ 0x00046c, 1, 0x01, 0x00000001 },
{ 0x000470, 96, 0x01, 0x00000000 },
{ 0x000510, 16, 0x01, 0x3f800000 },
{ 0x000520, 1, 0x01, 0x000002b6 },
{ 0x000529, 1, 0x01, 0x00000001 },
{ 0x000530, 16, 0x01, 0xffff0000 },
{ 0x000585, 1, 0x01, 0x0000003f },
{ 0x000576, 1, 0x01, 0x00000003 },
{ 0x00057b, 1, 0x01, 0x00000059 },
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
{ 0x00063e, 1, 0x01, 0x00000001 },
{ 0x0008b8, 8, 0x01, 0x00000001 },
{ 0x000900, 8, 0x01, 0x00000001 },
{ 0x000908, 8, 0x01, 0x00000002 },
{ 0x000910, 16, 0x01, 0x00000001 },
{ 0x000920, 8, 0x01, 0x00000002 },
{ 0x000928, 8, 0x01, 0x00000001 },
{ 0x000648, 9, 0x01, 0x00000001 },
{ 0x000658, 1, 0x01, 0x0000000f },
{ 0x0007ff, 1, 0x01, 0x0000000a },
{ 0x00066a, 1, 0x01, 0x40000000 },
{ 0x00066b, 1, 0x01, 0x10000000 },
{ 0x00066c, 2, 0x01, 0xffff0000 },
{ 0x0007af, 2, 0x01, 0x00000008 },
{ 0x0007f6, 1, 0x01, 0x00000001 },
{ 0x0006b2, 1, 0x01, 0x00000055 },
{ 0x0007ad, 1, 0x01, 0x00000003 },
{ 0x000937, 1, 0x01, 0x00000001 },
{ 0x000971, 1, 0x01, 0x00000008 },
{ 0x000972, 1, 0x01, 0x00000040 },
{ 0x000973, 1, 0x01, 0x0000012c },
{ 0x00097c, 1, 0x01, 0x00000040 },
{ 0x000979, 1, 0x01, 0x00000003 },
{ 0x000975, 1, 0x01, 0x00000020 },
{ 0x000976, 1, 0x01, 0x00000001 },
{ 0x000977, 1, 0x01, 0x00000020 },
{ 0x000978, 1, 0x01, 0x00000001 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095e, 1, 0x01, 0x20164010 },
{ 0x00095f, 1, 0x01, 0x00000020 },
{ 0x00097d, 1, 0x01, 0x00000020 },
{ 0x000683, 1, 0x01, 0x00000006 },
{ 0x000685, 1, 0x01, 0x003fffff },
{ 0x000687, 1, 0x01, 0x00000c48 },
{ 0x0006a0, 1, 0x01, 0x00000005 },
{ 0x000840, 1, 0x01, 0x00300008 },
{ 0x000841, 1, 0x01, 0x04000080 },
{ 0x000842, 1, 0x01, 0x00300008 },
{ 0x000843, 1, 0x01, 0x04000080 },
{ 0x000818, 8, 0x01, 0x00000000 },
{ 0x000848, 16, 0x01, 0x00000000 },
{ 0x000738, 1, 0x01, 0x00000000 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ab, 1, 0x01, 0x00000002 },
{ 0x0006ac, 1, 0x01, 0x00000080 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x0006bb, 1, 0x01, 0x000000cf },
{ 0x0006ce, 1, 0x01, 0x2a712488 },
{ 0x000739, 1, 0x01, 0x4085c000 },
{ 0x00073a, 1, 0x01, 0x00000080 },
{ 0x000786, 1, 0x01, 0x80000100 },
{ 0x00073c, 1, 0x01, 0x00010100 },
{ 0x00073d, 1, 0x01, 0x02800000 },
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x000944, 1, 0x01, 0x00000022 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x00c1b0, 8, 0x01, 0x0000000f },
{ 0x00c1b8, 1, 0x01, 0x0fac6881 },
{ 0x00c1b9, 1, 0x01, 0x00fac688 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
{ 0x000351, 1, 0x01, 0x00000100 },
{ 0x000957, 1, 0x01, 0x00000003 },
{ 0x00095d, 1, 0x01, 0x00000001 },
{ 0x00082b, 1, 0x01, 0x00000004 },
{ 0x000942, 1, 0x01, 0x00010001 },
{ 0x000943, 1, 0x01, 0x00000001 },
{ 0x0007c5, 1, 0x01, 0x00010001 },
{ 0x000834, 1, 0x01, 0x00000001 },
{ 0x0007c7, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000001 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
{ 0x00080f, 1, 0x01, 0x00000001 },
{ 0x000823, 1, 0x01, 0x00000002 },
{ 0x000824, 2, 0x01, 0x00000100 },
{ 0x000826, 1, 0x01, 0x00000001 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{}
};
const struct gf100_gr_pack
gf119_grctx_pack_icmd[] = {
{ gf119_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x002710, 8, 0x20, 0x00014000 },
{ 0x002714, 8, 0x20, 0x00000040 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x000758, 1, 0x04, 0x00000100 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x000204, 3, 0x04, 0x00000000 },
{ 0x000214, 1, 0x04, 0x00000000 },
{ 0x00024c, 1, 0x04, 0x00000000 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_pack
gf119_grctx_pack_mthd[] = {
{ gf108_grctx_init_9097_0, 0x9097 },
{ gf110_grctx_init_9197_0, 0x9197 },
{ gf110_grctx_init_9297_0, 0x9297 },
{ gf100_grctx_init_902d_0, 0x902d },
{ gf100_grctx_init_9039_0, 0x9039 },
{ gf119_grctx_init_90c0_0, 0x90c0 },
{}
};
const struct gf100_gr_init
gf119_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf0000087 },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x404168, 1, 0x04, 0x00000000 },
{ 0x404178, 2, 0x04, 0x00000000 },
{ 0x404200, 8, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 1, 0x04, 0x08000000 },
{ 0x405838, 1, 0x04, 0x00000000 },
{ 0x405854, 1, 0x04, 0x00000000 },
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 3, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x80140078 },
{ 0x4064c4, 1, 0x04, 0x0086ffff },
{}
};
const struct gf100_gr_init
gf119_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
{ 0x408900, 1, 0x04, 0x3080b801 },
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c8102f },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static const struct gf100_gr_pack
gf119_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gf119_grctx_init_fe_0 },
{ gf100_grctx_init_pri_0 },
{ gf100_grctx_init_memfmt_0 },
{ gf119_grctx_init_ds_0 },
{ gf119_grctx_init_pd_0 },
{ gf100_grctx_init_rstr2d_0 },
{ gf100_grctx_init_scc_0 },
{ gf119_grctx_init_be_0 },
{}
};
const struct gf100_gr_init
gf119_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
{ 0x418410, 1, 0x04, 0x0fff0fff },
{ 0x418414, 1, 0x04, 0x02200fff },
{ 0x418450, 6, 0x04, 0x00000000 },
{ 0x418468, 1, 0x04, 0x00000001 },
{ 0x41846c, 2, 0x04, 0x00000000 },
{}
};
const struct gf100_gr_init
gf119_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 3, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
{ 0x418830, 1, 0x04, 0x10000001 },
{ 0x4188d8, 1, 0x04, 0x00000008 },
{ 0x4188e0, 1, 0x04, 0x01000000 },
{ 0x4188e8, 5, 0x04, 0x00000000 },
{ 0x4188fc, 1, 0x04, 0x20100008 },
{}
};
const struct gf100_gr_init
gf119_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
{ 0x418b10, 1, 0x04, 0x020398a4 },
{ 0x418b14, 1, 0x04, 0x0e629062 },
{ 0x418b18, 1, 0x04, 0x0a418820 },
{ 0x418b1c, 1, 0x04, 0x000000e6 },
{ 0x418bb8, 1, 0x04, 0x00000103 },
{}
};
static const struct gf100_gr_pack
gf119_grctx_pack_gpc_0[] = {
{ gf100_grctx_init_gpc_unk_0 },
{ gf119_grctx_init_prop_0 },
{ gf119_grctx_init_gpc_unk_1 },
{ gf119_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
{ 0x419a0c, 1, 0x04, 0x00020000 },
{ 0x419a10, 1, 0x04, 0x00000000 },
{ 0x419a14, 1, 0x04, 0x00000200 },
{ 0x419a1c, 1, 0x04, 0x00000000 },
{ 0x419a20, 1, 0x04, 0x00000800 },
{ 0x419ac4, 1, 0x04, 0x0017f440 },
{}
};
static const struct gf100_gr_init
gf119_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
{ 0x419c20, 1, 0x04, 0x00000000 },
{ 0x419c24, 1, 0x04, 0x00084210 },
{ 0x419c28, 1, 0x04, 0x3cf3cf3c },
{}
};
const struct gf100_gr_init
gf119_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
{ 0x419e48, 1, 0x04, 0x00000000 },
{ 0x419e4c, 1, 0x04, 0x0000000f },
{ 0x419e50, 17, 0x04, 0x00000000 },
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00010110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gf119_grctx_pack_tpc[] = {
{ gf108_grctx_init_pe_0 },
{ gf119_grctx_init_tex_0 },
{ gf108_grctx_init_wwdx_0 },
{ gf119_grctx_init_mpc_0 },
{ gf104_grctx_init_l1c_0 },
{ gf108_grctx_init_tpccs_0 },
{ gf119_grctx_init_sm_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
const struct gf100_grctx_func
gf119_grctx = {
.main = gf100_grctx_generate_main,
.unkn = gf108_grctx_generate_unkn,
.hub = gf119_grctx_pack_hub,
.gpc_0 = gf119_grctx_pack_gpc_0,
.gpc_1 = gf117_grctx_pack_gpc_1,
.zcull = gf100_grctx_pack_zcull,
.tpc = gf119_grctx_pack_tpc,
.icmd = gf119_grctx_pack_icmd,
.mthd = gf119_grctx_pack_mthd,
.bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
.pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
.attrib_cb_size = gf100_grctx_generate_attrib_cb_size,
.attrib_cb = gf100_grctx_generate_attrib_cb,
.attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
.r4060a8 = gf100_grctx_generate_r4060a8,
.rop_mapping = gf100_grctx_generate_rop_mapping,
.alpha_beta_tables = gf100_grctx_generate_alpha_beta_tables,
.max_ways_evict = gf100_grctx_generate_max_ways_evict,
.r419cb8 = gf100_grctx_generate_r419cb8,
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c |
/*
* Copyright 2016 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
void
gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const int znum = zbc - 1;
const u32 zoff = znum * 4;
if (gr->zbc_color[zbc].format) {
nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);
nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);
nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);
nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);
}
nvkm_mask(device, 0x418100 + ((znum / 4) * 4),
0x0000007f << ((znum % 4) * 7),
gr->zbc_color[zbc].format << ((znum % 4) * 7));
}
void
gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const int znum = zbc - 1;
const u32 zoff = znum * 4;
if (gr->zbc_depth[zbc].format)
nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);
nvkm_mask(device, 0x41814c + ((znum / 4) * 4),
0x0000007f << ((znum % 4) * 7),
gr->zbc_depth[zbc].format << ((znum % 4) * 7));
}
const struct gf100_gr_func_zbc
gp100_gr_zbc = {
.clear_color = gp100_gr_zbc_clear_color,
.clear_depth = gp100_gr_zbc_clear_depth,
};
void
gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
}
static void
gp100_gr_init_419c9c(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
}
void
gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000e0002);
}
void
gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
/*XXX: otherwise identical to gm200 aside from mask.. do everywhere? */
const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;
nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
}
static const struct gf100_gr_func
gp100_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gm200_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419c9c = gp100_gr_init_419c9c,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.init_shader_exceptions = gp100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.trap_mp = gf100_gr_trap_mp,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.gpc_nr = 6,
.tpc_nr = 5,
.ppc_nr = 2,
.grctx = &gp100_grctx,
.zbc = &gp100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, PASCAL_A, &gf100_fermi },
{ -1, -1, PASCAL_COMPUTE_A },
{}
}
};
MODULE_FIRMWARE("nvidia/gp100/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_bl.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/gpccs_sig.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin");
static const struct gf100_gr_fwif
gp100_gr_fwif[] = {
{ 0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gp100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp100_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c |
/*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <core/firmware.h>
#include <subdev/timer.h>
#include <nvif/class.h>
struct gk20a_fw_av
{
u32 addr;
u32 data;
};
int
gk20a_gr_av_to_init_(struct nvkm_blob *blob, u8 count, u32 pitch, struct gf100_gr_pack **ppack)
{
struct gf100_gr_init *init;
struct gf100_gr_pack *pack;
int nent;
int i;
nent = (blob->size / sizeof(struct gk20a_fw_av));
pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
if (!pack)
return -ENOMEM;
init = (void *)(pack + 2);
pack[0].init = init;
for (i = 0; i < nent; i++) {
struct gf100_gr_init *ent = &init[i];
struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob->data)[i];
ent->addr = av->addr;
ent->data = av->data;
ent->count = ((ent->addr & 0xffff) != 0xe100) ? count : 1;
ent->pitch = pitch;
}
*ppack = pack;
return 0;
}
int
gk20a_gr_av_to_init(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
{
return gk20a_gr_av_to_init_(blob, 1, 1, ppack);
}
struct gk20a_fw_aiv
{
u32 addr;
u32 index;
u32 data;
};
int
gk20a_gr_aiv_to_init(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
{
struct gf100_gr_init *init;
struct gf100_gr_pack *pack;
int nent;
int i;
nent = (blob->size / sizeof(struct gk20a_fw_aiv));
pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
if (!pack)
return -ENOMEM;
init = (void *)(pack + 2);
pack[0].init = init;
for (i = 0; i < nent; i++) {
struct gf100_gr_init *ent = &init[i];
struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)blob->data)[i];
ent->addr = av->addr;
ent->data = av->data;
ent->count = 1;
ent->pitch = 1;
}
*ppack = pack;
return 0;
}
int
gk20a_gr_av_to_method(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
{
struct gf100_gr_init *init;
struct gf100_gr_pack *pack;
/* We don't suppose we will initialize more than 16 classes here... */
static const unsigned int max_classes = 16;
u32 classidx = 0, prevclass = 0;
int nent;
int i;
nent = (blob->size / sizeof(struct gk20a_fw_av));
pack = vzalloc((sizeof(*pack) * (max_classes + 1)) +
(sizeof(*init) * (nent + max_classes + 1)));
if (!pack)
return -ENOMEM;
init = (void *)(pack + max_classes + 1);
for (i = 0; i < nent; i++, init++) {
struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob->data)[i];
u32 class = av->addr & 0xffff;
u32 addr = (av->addr & 0xffff0000) >> 14;
if (prevclass != class) {
if (prevclass) /* Add terminator to the method list. */
init++;
pack[classidx].init = init;
pack[classidx].type = class;
prevclass = class;
if (++classidx >= max_classes) {
vfree(pack);
return -ENOSPC;
}
}
init->addr = addr;
init->data = av->data;
init->count = 1;
init->pitch = 1;
}
*ppack = pack;
return 0;
}
static int
gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
break;
) < 0) {
nvkm_error(subdev, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
break;
) < 0) {
nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
return 0;
}
static void
gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x419e44, 0x1ffffe);
nvkm_wr32(device, 0x419e4c, 0x7f);
}
int
gk20a_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int ret;
/* Clear SCC RAM */
nvkm_wr32(device, 0x40802c, 0x1);
gf100_gr_mmio(gr, gr->sw_nonctx);
ret = gk20a_gr_wait_mem_scrubbing(gr);
if (ret)
return ret;
ret = gf100_gr_wait_idle(gr);
if (ret)
return ret;
/* MMU debug buffer */
if (gr->func->init_gpc_mmu)
gr->func->init_gpc_mmu(gr);
/* Set the PE as stream master */
nvkm_mask(device, 0x503018, 0x1, 0x1);
/* Zcull init */
gr->func->init_zcull(gr);
gr->func->init_rop_active_fbps(gr);
/* Enable FIFO access */
nvkm_wr32(device, 0x400500, 0x00010001);
/* Enable interrupts */
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
/* Enable FECS error interrupts */
nvkm_wr32(device, 0x409c24, 0x000f0000);
/* Enable hardware warning exceptions */
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
if (gr->func->set_hww_esr_report_mask)
gr->func->set_hww_esr_report_mask(gr);
/* Enable TPC exceptions per GPC */
nvkm_wr32(device, 0x419d0c, 0x2);
nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
/* Reset and enable all exceptions */
nvkm_wr32(device, 0x400108, 0xffffffff);
nvkm_wr32(device, 0x400138, 0xffffffff);
nvkm_wr32(device, 0x400118, 0xffffffff);
nvkm_wr32(device, 0x400130, 0xffffffff);
nvkm_wr32(device, 0x40011c, 0xffffffff);
nvkm_wr32(device, 0x400134, 0xffffffff);
gf100_gr_zbc_init(gr);
return gf100_gr_init_ctxctl(gr);
}
static const struct gf100_gr_func
gk20a_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gk20a_gr_init,
.init_zcull = gf117_gr_init_zcull,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.trap_mp = gf100_gr_trap_mp,
.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gf100_gr_rops,
.ppc_nr = 1,
.grctx = &gk20a_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },
{ -1, -1, KEPLER_C, &gf100_fermi },
{ -1, -1, KEPLER_COMPUTE_A },
{}
}
};
int
gk20a_gr_load_net(struct gf100_gr *gr, const char *path, const char *name, int ver,
int (*load)(struct nvkm_blob *, struct gf100_gr_pack **),
struct gf100_gr_pack **ppack)
{
struct nvkm_blob blob;
int ret;
ret = nvkm_firmware_load_blob(&gr->base.engine.subdev, path, name, ver, &blob);
if (ret)
return ret;
ret = load(&blob, ppack);
nvkm_blob_dtor(&blob);
return 0;
}
int
gk20a_gr_load_sw(struct gf100_gr *gr, const char *path, int ver)
{
if (gk20a_gr_load_net(gr, path, "sw_nonctx", ver, gk20a_gr_av_to_init, &gr->sw_nonctx) ||
gk20a_gr_load_net(gr, path, "sw_ctx", ver, gk20a_gr_aiv_to_init, &gr->sw_ctx) ||
gk20a_gr_load_net(gr, path, "sw_bundle_init", ver, gk20a_gr_av_to_init, &gr->bundle) ||
gk20a_gr_load_net(gr, path, "sw_method_init", ver, gk20a_gr_av_to_method, &gr->method))
return -ENOENT;
return 0;
}
#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC)
MODULE_FIRMWARE("nvidia/gk20a/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gk20a/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gk20a/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gk20a/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gk20a/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gk20a/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gk20a/sw_method_init.bin");
MODULE_FIRMWARE("nvidia/gk20a/sw_nonctx.bin");
#endif
static int
gk20a_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
if (nvkm_firmware_load_blob(subdev, "", "fecs_inst", ver,
&gr->fecs.inst) ||
nvkm_firmware_load_blob(subdev, "", "fecs_data", ver,
&gr->fecs.data) ||
nvkm_firmware_load_blob(subdev, "", "gpccs_inst", ver,
&gr->gpccs.inst) ||
nvkm_firmware_load_blob(subdev, "", "gpccs_data", ver,
&gr->gpccs.data))
return -ENOENT;
gr->firmware = true;
return gk20a_gr_load_sw(gr, "", ver);
}
static const struct gf100_gr_fwif
gk20a_gr_fwif[] = {
{ 0, gk20a_gr_load, &gk20a_gr },
{}
};
int
gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv50.h"
#include <nvif/class.h>
static const struct nvkm_gr_func
mcp79_gr = {
.init = nv50_gr_init,
.intr = nv50_gr_intr,
.chan_new = nv50_gr_chan_new,
.units = nv50_gr_units,
.sclass = {
{ -1, -1, NV_NULL_CLASS, &nv50_gr_object },
{ -1, -1, NV50_TWOD, &nv50_gr_object },
{ -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object },
{ -1, -1, NV50_COMPUTE, &nv50_gr_object },
{ -1, -1, GT200_TESLA, &nv50_gr_object },
{}
}
};
int
mcp79_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&mcp79_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct nvkm_object_func
nv34_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x46dc, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x040c, 0x01000101);
nvkm_wo32(chan->inst, 0x0420, 0x00000111);
nvkm_wo32(chan->inst, 0x0424, 0x00000060);
nvkm_wo32(chan->inst, 0x0440, 0x00000080);
nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
nvkm_wo32(chan->inst, 0x0448, 0x00000001);
nvkm_wo32(chan->inst, 0x045c, 0x44400000);
nvkm_wo32(chan->inst, 0x0480, 0xffff0000);
for (i = 0x04d4; i < 0x04dc; i += 4)
nvkm_wo32(chan->inst, i, 0x0fff0000);
nvkm_wo32(chan->inst, 0x04e0, 0x00011100);
for (i = 0x04fc; i < 0x053c; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x0544, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x057c, 0x00000080);
nvkm_wo32(chan->inst, 0x0580, 0x30201000);
nvkm_wo32(chan->inst, 0x0584, 0x70605040);
nvkm_wo32(chan->inst, 0x0588, 0xb8a89888);
nvkm_wo32(chan->inst, 0x058c, 0xf8e8d8c8);
nvkm_wo32(chan->inst, 0x05a0, 0xb0000000);
for (i = 0x05f0; i < 0x0630; i += 4)
nvkm_wo32(chan->inst, i, 0x00010588);
for (i = 0x0630; i < 0x0670; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x06b0; i < 0x06f0; i += 4)
nvkm_wo32(chan->inst, i, 0x0008aae4);
for (i = 0x06f0; i < 0x0730; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x0730; i < 0x0770; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
nvkm_wo32(chan->inst, 0x0850, 0x00040000);
nvkm_wo32(chan->inst, 0x0854, 0x00010000);
for (i = 0x0858; i < 0x0868; i += 4)
nvkm_wo32(chan->inst, i, 0x00040004);
for (i = 0x15ac; i <= 0x271c ; i += 16) {
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
}
for (i = 0x274c; i < 0x275c; i += 4)
nvkm_wo32(chan->inst, i, 0x0000ffff);
nvkm_wo32(chan->inst, 0x2ae0, 0x3f800000);
nvkm_wo32(chan->inst, 0x2e9c, 0x3f800000);
nvkm_wo32(chan->inst, 0x2eb0, 0x3f800000);
nvkm_wo32(chan->inst, 0x2edc, 0x40000000);
nvkm_wo32(chan->inst, 0x2ee0, 0x3f800000);
nvkm_wo32(chan->inst, 0x2ee4, 0x3f000000);
nvkm_wo32(chan->inst, 0x2eec, 0x40000000);
nvkm_wo32(chan->inst, 0x2ef0, 0x3f800000);
nvkm_wo32(chan->inst, 0x2ef8, 0xbf800000);
nvkm_wo32(chan->inst, 0x2f00, 0xbf800000);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct nvkm_gr_func
nv34_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv30_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv34_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
{ -1, -1, 0x0697, &nv04_gr_object }, /* rankine */
{}
}
};
int
nv34_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv34_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c |
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <nvif/class.h>
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
static const struct gf100_gr_init
gk110b_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x09000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
{ 0x419cb8, 1, 0x04, 0x00b08bea },
{ 0x419c84, 1, 0x04, 0x00010384 },
{ 0x419cbc, 1, 0x04, 0x281b3646 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x00020230 },
{ 0x419ccc, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gk110b_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
{ 0x419ea8, 1, 0x04, 0x00000000 },
{ 0x419eb4, 1, 0x04, 0x00000000 },
{ 0x419ebc, 2, 0x04, 0x00000000 },
{ 0x419edc, 1, 0x04, 0x00000000 },
{ 0x419f00, 1, 0x04, 0x00000000 },
{ 0x419ed0, 1, 0x04, 0x00002616 },
{ 0x419f74, 1, 0x04, 0x00015555 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_pack
gk110b_gr_pack_mmio[] = {
{ gk104_gr_init_main_0 },
{ gk110_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf119_gr_init_pd_0 },
{ gk110_gr_init_ds_0 },
{ gf100_gr_init_scc_0 },
{ gk110_gr_init_sked_0 },
{ gk110_gr_init_cwd_0 },
{ gf119_gr_init_prop_0 },
{ gf108_gr_init_gpc_unk_0 },
{ gf100_gr_init_setup_0 },
{ gf100_gr_init_crstr_0 },
{ gf108_gr_init_setup_1 },
{ gf100_gr_init_zcull_0 },
{ gf119_gr_init_gpm_0 },
{ gk110_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gk104_gr_init_gpc_unk_2 },
{ gk104_gr_init_tpccs_0 },
{ gk110_gr_init_tex_0 },
{ gk104_gr_init_pe_0 },
{ gk110b_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gk110b_gr_init_sm_0 },
{ gf117_gr_init_pes_0 },
{ gf117_gr_init_wwdx_0 },
{ gf117_gr_init_cbm_0 },
{ gk104_gr_init_be_0 },
{ gf100_gr_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static const struct gf100_gr_func
gk110b_gr = {
.oneinit_tiles = gf100_gr_oneinit_tiles,
.oneinit_sm_id = gf100_gr_oneinit_sm_id,
.init = gf100_gr_init,
.init_gpc_mmu = gf100_gr_init_gpc_mmu,
.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
.init_419cc0 = gf100_gr_init_419cc0,
.init_419eb4 = gk110_gr_init_419eb4,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_shader_exceptions = gf100_gr_init_shader_exceptions,
.init_rop_exceptions = gf100_gr_init_rop_exceptions,
.init_exception2 = gf100_gr_init_exception2,
.init_400054 = gf100_gr_init_400054,
.trap_mp = gf100_gr_trap_mp,
.mmio = gk110b_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,
.fecs.reset = gf100_gr_fecs_reset,
.gpccs.ucode = &gk110_gr_gpccs_ucode,
.rops = gf100_gr_rops,
.ppc_nr = 2,
.grctx = &gk110b_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, KEPLER_B, &gf100_fermi },
{ -1, -1, KEPLER_COMPUTE_B },
{}
}
};
static const struct gf100_gr_fwif
gk110b_gr_fwif[] = {
{ -1, gf100_gr_load, &gk110b_gr },
{ -1, gf100_gr_nofw, &gk110b_gr },
{}
};
int
gk110b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk110b_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c |
// SPDX-License-Identifier: MIT
#include "nv20.h"
#include "regs.h"
#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static const struct nvkm_object_func
nv30_gr_chan = {
.dtor = nv20_gr_chan_dtor,
.init = nv20_gr_chan_init,
.fini = nv20_gr_chan_fini,
};
static int
nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_chan *fifoch,
const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
{
struct nv20_gr *gr = nv20_gr(base);
struct nv20_gr_chan *chan;
int ret, i;
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
return -ENOMEM;
nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object);
chan->gr = gr;
chan->chid = fifoch->id;
*pobject = &chan->object;
ret = nvkm_memory_new(gr->base.engine.subdev.device,
NVKM_MEM_TARGET_INST, 0x5f48, 16, true,
&chan->inst);
if (ret)
return ret;
nvkm_kmap(chan->inst);
nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
nvkm_wo32(chan->inst, 0x0410, 0x00000101);
nvkm_wo32(chan->inst, 0x0424, 0x00000111);
nvkm_wo32(chan->inst, 0x0428, 0x00000060);
nvkm_wo32(chan->inst, 0x0444, 0x00000080);
nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
nvkm_wo32(chan->inst, 0x044c, 0x00000001);
nvkm_wo32(chan->inst, 0x0460, 0x44400000);
nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
for (i = 0x04e0; i < 0x04e8; i += 4)
nvkm_wo32(chan->inst, i, 0x0fff0000);
nvkm_wo32(chan->inst, 0x04ec, 0x00011100);
for (i = 0x0508; i < 0x0548; i += 4)
nvkm_wo32(chan->inst, i, 0x07ff0000);
nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff);
nvkm_wo32(chan->inst, 0x058c, 0x00000080);
nvkm_wo32(chan->inst, 0x0590, 0x30201000);
nvkm_wo32(chan->inst, 0x0594, 0x70605040);
nvkm_wo32(chan->inst, 0x0598, 0xb8a89888);
nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8);
nvkm_wo32(chan->inst, 0x05b0, 0xb0000000);
for (i = 0x0600; i < 0x0640; i += 4)
nvkm_wo32(chan->inst, i, 0x00010588);
for (i = 0x0640; i < 0x0680; i += 4)
nvkm_wo32(chan->inst, i, 0x00030303);
for (i = 0x06c0; i < 0x0700; i += 4)
nvkm_wo32(chan->inst, i, 0x0008aae4);
for (i = 0x0700; i < 0x0740; i += 4)
nvkm_wo32(chan->inst, i, 0x01012000);
for (i = 0x0740; i < 0x0780; i += 4)
nvkm_wo32(chan->inst, i, 0x00080008);
nvkm_wo32(chan->inst, 0x085c, 0x00040000);
nvkm_wo32(chan->inst, 0x0860, 0x00010000);
for (i = 0x0864; i < 0x0874; i += 4)
nvkm_wo32(chan->inst, i, 0x00040004);
for (i = 0x1f18; i <= 0x3088 ; i += 16) {
nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
nvkm_wo32(chan->inst, i + 4, 0x0436086c);
nvkm_wo32(chan->inst, i + 8, 0x000c001b);
}
for (i = 0x30b8; i < 0x30c8; i += 4)
nvkm_wo32(chan->inst, i, 0x0000ffff);
nvkm_wo32(chan->inst, 0x344c, 0x3f800000);
nvkm_wo32(chan->inst, 0x3808, 0x3f800000);
nvkm_wo32(chan->inst, 0x381c, 0x3f800000);
nvkm_wo32(chan->inst, 0x3848, 0x40000000);
nvkm_wo32(chan->inst, 0x384c, 0x3f800000);
nvkm_wo32(chan->inst, 0x3850, 0x3f000000);
nvkm_wo32(chan->inst, 0x3858, 0x40000000);
nvkm_wo32(chan->inst, 0x385c, 0x3f800000);
nvkm_wo32(chan->inst, 0x3864, 0xbf800000);
nvkm_wo32(chan->inst, 0x386c, 0xbf800000);
nvkm_done(chan->inst);
return 0;
}
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
int
nv30_gr_init(struct nvkm_gr *base)
{
struct nv20_gr *gr = nv20_gr(base);
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
nvkm_memory_addr(gr->ctxtab) >> 4);
nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
nvkm_wr32(device, 0x400890, 0x01b463ff);
nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
nvkm_wr32(device, 0x400B80, 0x1003d888);
nvkm_wr32(device, 0x400B84, 0x0c000000);
nvkm_wr32(device, 0x400098, 0x00000000);
nvkm_wr32(device, 0x40009C, 0x0005ad00);
nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
nvkm_wr32(device, 0x4000a0, 0x00000000);
nvkm_wr32(device, 0x4000a4, 0x00000008);
nvkm_wr32(device, 0x4008a8, 0xb784a400);
nvkm_wr32(device, 0x400ba0, 0x002f8685);
nvkm_wr32(device, 0x400ba4, 0x00231f3f);
nvkm_wr32(device, 0x4008a4, 0x40000020);
if (device->chipset == 0x34) {
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032);
nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002);
}
nvkm_wr32(device, 0x4000c0, 0x00000016);
nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
nvkm_wr32(device, 0x0040075c , 0x00000001);
/* begin RAM config */
/* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */
nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
if (device->chipset != 0x34) {
nvkm_wr32(device, 0x400750, 0x00EA0000);
nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200));
nvkm_wr32(device, 0x400750, 0x00EA0004);
nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204));
}
return 0;
}
static const struct nvkm_gr_func
nv30_gr = {
.dtor = nv20_gr_dtor,
.oneinit = nv20_gr_oneinit,
.init = nv30_gr_init,
.intr = nv20_gr_intr,
.tile = nv20_gr_tile,
.chan_new = nv30_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
{ -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */
{ -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */
{ -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */
{ -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */
{ -1, -1, 0x0397, &nv04_gr_object }, /* rankine */
{ -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */
{}
}
};
int
nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv30_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c |
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gf100.h"
#include "ctxgf100.h"
#include <core/firmware.h>
#include <subdev/acr.h>
#include <subdev/timer.h>
#include <nvfw/flcn.h>
#include <nvif/class.h>
void
gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct flcn_bl_dmem_desc hdr;
u64 addr;
nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8);
hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8);
hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8);
addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8);
hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8);
hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8);
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
flcn_bl_dmem_desc_dump(&acr->subdev, &hdr);
}
void
gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
const u64 base = lsfw->offset.img + lsfw->app_start_offset;
const u64 code = (base + lsfw->app_resident_code_offset) >> 8;
const u64 data = (base + lsfw->app_resident_data_offset) >> 8;
const struct flcn_bl_dmem_desc hdr = {
.ctx_dma = FALCON_DMAIDX_UCODE,
.code_dma_base = lower_32_bits(code),
.non_sec_code_off = lsfw->app_resident_code_offset,
.non_sec_code_size = lsfw->app_resident_code_size,
.code_entry_point = lsfw->app_imem_entry,
.data_dma_base = lower_32_bits(data),
.data_size = lsfw->app_resident_data_size,
.code_dma_base1 = upper_32_bits(code),
.data_dma_base1 = upper_32_bits(data),
};
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
}
const struct nvkm_acr_lsf_func
gm20b_gr_fecs_acr = {
.bld_size = sizeof(struct flcn_bl_dmem_desc),
.bld_write = gm20b_gr_acr_bld_write,
.bld_patch = gm20b_gr_acr_bld_patch,
};
static void
gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
u32 val;
/* Bypass MMU check for non-secure boot */
if (!device->acr) {
nvkm_wr32(device, 0x100ce4, 0xffffffff);
if (nvkm_rd32(device, 0x100ce4) != 0xffffffff)
nvdev_warn(device,
"cannot bypass secure boot - expect failure soon!\n");
}
val = nvkm_rd32(device, 0x100c80);
val &= 0xf000187f;
nvkm_wr32(device, 0x418880, val);
nvkm_wr32(device, 0x418890, 0);
nvkm_wr32(device, 0x418894, 0);
nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800));
}
static void
gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x419e44, 0xdffffe);
nvkm_wr32(device, 0x419e4c, 0x5);
}
static const struct gf100_gr_func
gm20b_gr = {
.oneinit_tiles = gm200_gr_oneinit_tiles,
.oneinit_sm_id = gm200_gr_oneinit_sm_id,
.init = gk20a_gr_init,
.init_zcull = gf117_gr_init_zcull,
.init_gpc_mmu = gm20b_gr_init_gpc_mmu,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.trap_mp = gf100_gr_trap_mp,
.set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,
.fecs.reset = gf100_gr_fecs_reset,
.rops = gm200_gr_rops,
.ppc_nr = 1,
.grctx = &gm20b_grctx,
.zbc = &gf100_gr_zbc,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
{ -1, -1, MAXWELL_B, &gf100_fermi },
{ -1, -1, MAXWELL_COMPUTE_B },
{}
}
};
static int
gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int ret;
ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,
NVKM_ACR_LSF_FECS,
"gr/fecs_", ver, fwif->fecs);
if (ret)
return ret;
if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver,
&gr->gpccs.inst) ||
nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver,
&gr->gpccs.data))
return -ENOENT;
gr->firmware = true;
return gk20a_gr_load_sw(gr, "gr/", ver);
}
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
#endif
static const struct gf100_gr_fwif
gm20b_gr_fwif[] = {
{ 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr },
{ -1, gm200_gr_nofw },
{}
};
int
gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c |
/*
* Copyright 2007 Matthieu CASTET <[email protected]>
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragr) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nv10.h"
static const struct nvkm_gr_func
nv15_gr = {
.init = nv10_gr_init,
.intr = nv10_gr_intr,
.tile = nv10_gr_tile,
.chan_new = nv10_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
{ -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
{ -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
{ -1, -1, 0x005f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
{ -1, -1, 0x009f, &nv04_gr_object }, /* blit */
{ -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */
{ -1, -1, 0x0094, &nv04_gr_object }, /* ttri */
{ -1, -1, 0x0095, &nv04_gr_object }, /* mtri */
{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
{}
}
};
int
nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv15_gr, device, type, inst, pgr);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <engine/sec.h>
#include <engine/fifo.h>
#include "fuc/g98.fuc0s.h"
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <nvif/class.h>
static const struct nvkm_enum g98_sec_isr_error_name[] = {
{ 0x0000, "ILLEGAL_MTHD" },
{ 0x0001, "INVALID_BITFIELD" },
{ 0x0002, "INVALID_ENUM" },
{ 0x0003, "QUERY" },
{}
};
static void
g98_sec_intr(struct nvkm_falcon *sec, struct nvkm_chan *chan)
{
struct nvkm_subdev *subdev = &sec->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff;
u32 addr = nvkm_rd32(device, 0x087040) >> 16;
u32 mthd = (addr & 0x07ff) << 2;
u32 subc = (addr & 0x3800) >> 11;
u32 data = nvkm_rd32(device, 0x087044);
const struct nvkm_enum *en =
nvkm_enum_find(g98_sec_isr_error_name, ssta);
nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] "
"subc %d mthd %04x data %08x\n", ssta,
en ? en->name : "UNKNOWN", chan ? chan->id : -1,
chan ? chan->inst->addr : 0,
chan ? chan->name : "unknown",
subc, mthd, data);
}
static const struct nvkm_falcon_func
g98_sec = {
.code.data = g98_sec_code,
.code.size = sizeof(g98_sec_code),
.data.data = g98_sec_data,
.data.size = sizeof(g98_sec_data),
.intr = g98_sec_intr,
.sclass = {
{ -1, -1, G98_SEC },
{}
}
};
int
g98_sec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(&g98_sec, device, type, inst, true, 0x087000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_msppp_init(struct nvkm_falcon *msppp)
{
struct nvkm_device *device = msppp->engine.subdev.device;
nvkm_wr32(device, 0x086010, 0x0000ffd2);
nvkm_wr32(device, 0x08601c, 0x0000fff2);
}
static const struct nvkm_falcon_func
g98_msppp = {
.init = g98_msppp_init,
.sclass = {
{ -1, -1, G98_MSPPP },
{}
}
};
int
g98_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(&g98_msppp, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c |
/*
* Copyright 2012 Maarten Lankhorst
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
static void
gf100_msppp_init(struct nvkm_falcon *msppp)
{
struct nvkm_device *device = msppp->engine.subdev.device;
nvkm_wr32(device, 0x086010, 0x0000fff2);
nvkm_wr32(device, 0x08601c, 0x0000fff2);
}
static const struct nvkm_falcon_func
gf100_msppp = {
.init = gf100_msppp_init,
.sclass = {
{ -1, -1, GF100_MSPPP },
{}
}
};
int
gf100_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(&gf100_msppp, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "priv.h"
int
nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, type, inst, true, 0x086000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gt215_msppp = {
.init = g98_msppp_init,
.sclass = {
{ -1, -1, GT212_MSPPP },
{}
}
};
int
gt215_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(>215_msppp, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <engine/cipher.h>
#include <engine/fifo.h>
#include <core/client.h>
#include <core/enum.h>
#include <core/gpuobj.h>
#include <nvif/class.h>
static int
g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
align, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm_done(*pgpuobj);
}
return ret;
}
static const struct nvkm_object_func
g84_cipher_oclass_func = {
.bind = g84_cipher_oclass_bind,
};
static int
g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
int align, struct nvkm_gpuobj **pgpuobj)
{
return nvkm_gpuobj_new(object->engine->subdev.device, 256,
align, true, parent, pgpuobj);
}
static const struct nvkm_object_func
g84_cipher_cclass = {
.bind = g84_cipher_cclass_bind,
};
static const struct nvkm_bitfield
g84_cipher_intr_mask[] = {
{ 0x00000001, "INVALID_STATE" },
{ 0x00000002, "ILLEGAL_MTHD" },
{ 0x00000004, "ILLEGAL_CLASS" },
{ 0x00000080, "QUERY" },
{ 0x00000100, "FAULT" },
{}
};
static void
g84_cipher_intr(struct nvkm_engine *cipher)
{
struct nvkm_subdev *subdev = &cipher->subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_chan *chan;
u32 stat = nvkm_rd32(device, 0x102130);
u32 mthd = nvkm_rd32(device, 0x102190);
u32 data = nvkm_rd32(device, 0x102194);
u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
unsigned long flags;
char msg[128];
chan = nvkm_chan_get_inst(cipher, (u64)inst << 12, &flags);
if (stat) {
nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat);
nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] "
"mthd %04x data %08x\n", stat, msg,
chan ? chan->id : -1, (u64)inst << 12,
chan ? chan->name : "unknown",
mthd, data);
}
nvkm_chan_put(&chan, flags);
nvkm_wr32(device, 0x102130, stat);
nvkm_wr32(device, 0x10200c, 0x10);
}
static int
g84_cipher_init(struct nvkm_engine *cipher)
{
struct nvkm_device *device = cipher->subdev.device;
nvkm_wr32(device, 0x102130, 0xffffffff);
nvkm_wr32(device, 0x102140, 0xffffffbf);
nvkm_wr32(device, 0x10200c, 0x00000010);
return 0;
}
static const struct nvkm_engine_func
g84_cipher = {
.init = g84_cipher_init,
.intr = g84_cipher_intr,
.cclass = &g84_cipher_cclass,
.sclass = {
{ -1, -1, NV74_CIPHER, &g84_cipher_oclass_func },
{}
}
};
int
g84_cipher_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_engine_new_(&g84_cipher, device, type, inst, true, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_mspdec_init(struct nvkm_falcon *mspdec)
{
struct nvkm_device *device = mspdec->engine.subdev.device;
nvkm_wr32(device, 0x085010, 0x0000ffd2);
nvkm_wr32(device, 0x08501c, 0x0000fff2);
}
static const struct nvkm_falcon_func
g98_mspdec = {
.init = g98_mspdec_init,
.sclass = {
{ -1, -1, G98_MSPDEC },
{}
}
};
int
g98_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&g98_mspdec, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gk104_mspdec = {
.init = gf100_mspdec_init,
.sclass = {
{ -1, -1, GK104_MSPDEC },
{}
}
};
int
gk104_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&gk104_mspdec, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c |
/*
* Copyright 2012 Maarten Lankhorst
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
void
gf100_mspdec_init(struct nvkm_falcon *mspdec)
{
struct nvkm_device *device = mspdec->engine.subdev.device;
nvkm_wr32(device, 0x085010, 0x0000fff2);
nvkm_wr32(device, 0x08501c, 0x0000fff2);
}
static const struct nvkm_falcon_func
gf100_mspdec = {
.init = gf100_mspdec_init,
.sclass = {
{ -1, -1, GF100_MSPDEC },
{}
}
};
int
gf100_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&gf100_mspdec, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "priv.h"
int
nvkm_mspdec_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, type, inst, true, 0x085000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gt215_mspdec = {
.init = g98_mspdec_init,
.sclass = {
{ -1, -1, GT212_MSPDEC },
{}
}
};
int
gt215_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(>215_mspdec, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
#include <engine/bsp.h>
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_bsp = {
.fifo_val = 0x1111,
.unkd28 = 0x90044,
.sclass = {
{ -1, -1, NV74_BSP },
{}
}
};
int
g84_bsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_xtensa_new_(&g84_bsp, device, type, inst,
device->chipset != 0x92, 0x103000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Ilia Mirkin
*/
#include <engine/vp.h>
#include <nvif/class.h>
static const struct nvkm_xtensa_func
g84_vp = {
.fifo_val = 0x111,
.unkd28 = 0x9c544,
.sclass = {
{ -1, -1, NV74_VP2 },
{}
}
};
int
g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c |
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
static const struct nvkm_falcon_func
gm107_nvdec_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.reset_pmc = true,
.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
.debug = 0xd00,
.imem_pio = &gm200_flcn_imem_pio,
.dmem_pio = &gm200_flcn_dmem_pio,
};
static const struct nvkm_nvdec_func
gm107_nvdec = {
.flcn = &gm107_nvdec_flcn,
};
static int
gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
const struct nvkm_nvdec_fwif *fwif)
{
return 0;
}
static const struct nvkm_nvdec_fwif
gm107_nvdec_fwif[] = {
{ -1, gm107_nvdec_nofw, &gm107_nvdec },
{}
};
int
gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_nvdec **pnvdec)
{
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, 0, pnvdec);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c |
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <core/firmware.h>
static void *
nvkm_nvdec_dtor(struct nvkm_engine *engine)
{
struct nvkm_nvdec *nvdec = nvkm_nvdec(engine);
nvkm_falcon_dtor(&nvdec->falcon);
return nvdec;
}
static const struct nvkm_engine_func
nvkm_nvdec = {
.dtor = nvkm_nvdec_dtor,
};
int
nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_nvdec **pnvdec)
{
struct nvkm_nvdec *nvdec;
int ret;
if (!(nvdec = *pnvdec = kzalloc(sizeof(*nvdec), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_engine_ctor(&nvkm_nvdec, device, type, inst, true,
&nvdec->engine);
if (ret)
return ret;
fwif = nvkm_firmware_load(&nvdec->engine.subdev, fwif, "Nvdec", nvdec);
if (IS_ERR(fwif))
return -ENODEV;
nvdec->func = fwif->func;
return nvkm_falcon_ctor(nvdec->func->flcn, &nvdec->engine.subdev,
nvdec->engine.subdev.name, addr, &nvdec->falcon);
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c |
/*
* Copyright 2021 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/mc.h>
#include <subdev/timer.h>
static const struct nvkm_falcon_func
ga102_nvdec_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.addr2 = 0x1c00,
.reset_pmc = true,
.reset_prep = ga102_flcn_reset_prep,
.reset_wait_mem_scrubbing = ga102_flcn_reset_wait_mem_scrubbing,
.imem_dma = &ga102_flcn_dma,
.dmem_dma = &ga102_flcn_dma,
};
static const struct nvkm_nvdec_func
ga102_nvdec = {
.flcn = &ga102_nvdec_flcn,
};
static int
ga102_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver, const struct nvkm_nvdec_fwif *fwif)
{
return 0;
}
static const struct nvkm_nvdec_fwif
ga102_nvdec_fwif[] = {
{ -1, ga102_nvdec_nofw, &ga102_nvdec },
{}
};
int
ga102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_nvdec **pnvdec)
{
return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/acr.h>
#include <nvfw/sec2.h>
static const struct nvkm_falcon_func
tu102_sec2_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.reset_pmc = true,
.reset_eng = gp102_flcn_reset_eng,
.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
.debug = 0x408,
.bind_inst = gm200_flcn_bind_inst,
.bind_stat = gm200_flcn_bind_stat,
.bind_intr = true,
.imem_pio = &gm200_flcn_imem_pio,
.dmem_pio = &gm200_flcn_dmem_pio,
.emem_addr = 0x01000000,
.emem_pio = &gp102_flcn_emem_pio,
.start = nvkm_falcon_v1_start,
.cmdq = { 0xc00, 0xc04, 8 },
.msgq = { 0xc80, 0xc84, 8 },
};
static const struct nvkm_sec2_func
tu102_sec2 = {
.flcn = &tu102_sec2_flcn,
.unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
.unit_acr = NV_SEC2_UNIT_V2_ACR,
.intr = gp102_sec2_intr,
.initmsg = gp102_sec2_initmsg,
};
MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin");
MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
static const struct nvkm_sec2_fwif
tu102_sec2_fwif[] = {
{ 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
{ -1, gp102_sec2_nofw, &tu102_sec2 }
};
int
tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{
/* TOP info wasn't updated on Turing to reflect the PRI
* address change for some reason. We override it here.
*/
return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c |
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <core/memory.h>
#include <subdev/acr.h>
#include <subdev/timer.h>
#include <nvfw/flcn.h>
#include <nvfw/sec2.h>
int
gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n");
return 0;
}
static int
gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
{
struct nv_sec2_acr_bootstrap_falcon_msg *msg =
container_of(hdr, typeof(*msg), msg.hdr);
struct nvkm_subdev *subdev = priv;
const char *name = nvkm_acr_lsf_id(msg->falcon_id);
if (msg->error_code) {
nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for "
"falcon %d [%s]: %08x\n",
msg->falcon_id, name, msg->error_code);
return -EINVAL;
}
nvkm_debug(subdev, "%s booted\n", name);
return 0;
}
static int
gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
enum nvkm_acr_lsf_id id)
{
struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);
struct nv_sec2_acr_bootstrap_falcon_cmd cmd = {
.cmd.hdr.unit_id = sec2->func->unit_acr,
.cmd.hdr.size = sizeof(cmd),
.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
.falcon_id = id,
};
return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
gp102_sec2_acr_bootstrap_falcon_callback,
&sec2->engine.subdev,
msecs_to_jiffies(1000));
}
static void
gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct loader_config_v1 hdr;
nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
hdr.code_dma_base = hdr.code_dma_base + adjust;
hdr.data_dma_base = hdr.data_dma_base + adjust;
hdr.overlay_dma_base = hdr.overlay_dma_base + adjust;
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
loader_config_v1_dump(&acr->subdev, &hdr);
}
static void
gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
const struct loader_config_v1 hdr = {
.dma_idx = FALCON_SEC2_DMAIDX_UCODE,
.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
.code_size_total = lsfw->app_size,
.code_size_to_load = lsfw->app_resident_code_size,
.code_entry_point = lsfw->app_imem_entry,
.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
lsfw->app_resident_data_offset,
.data_size = lsfw->app_resident_data_size,
.overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset,
.argc = 1,
.argv = lsfw->falcon->func->emem_addr,
};
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
}
static const struct nvkm_acr_lsf_func
gp102_sec2_acr_0 = {
.bld_size = sizeof(struct loader_config_v1),
.bld_write = gp102_sec2_acr_bld_write,
.bld_patch = gp102_sec2_acr_bld_patch,
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
BIT_ULL(NVKM_ACR_LSF_SEC2),
.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
};
int
gp102_sec2_initmsg(struct nvkm_sec2 *sec2)
{
struct nv_sec2_init_msg msg;
int ret, i;
ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg));
if (ret)
return ret;
if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT ||
msg.msg_type != NV_SEC2_INIT_MSG_INIT)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) {
if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) {
nvkm_falcon_msgq_init(sec2->msgq,
msg.queue_info[i].index,
msg.queue_info[i].offset,
msg.queue_info[i].size);
} else {
nvkm_falcon_cmdq_init(sec2->cmdq,
msg.queue_info[i].index,
msg.queue_info[i].offset,
msg.queue_info[i].size);
}
}
return 0;
}
irqreturn_t
gp102_sec2_intr(struct nvkm_inth *inth)
{
struct nvkm_sec2 *sec2 = container_of(inth, typeof(*sec2), engine.subdev.inth);
struct nvkm_subdev *subdev = &sec2->engine.subdev;
struct nvkm_falcon *falcon = &sec2->falcon;
u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
if (intr & 0x00000040) {
if (unlikely(atomic_read(&sec2->initmsg) == 0)) {
int ret = sec2->func->initmsg(sec2);
if (ret)
nvkm_error(subdev, "error parsing init message: %d\n", ret);
atomic_set(&sec2->initmsg, ret ?: 1);
}
if (atomic_read(&sec2->initmsg) > 0) {
if (!nvkm_falcon_msgq_empty(sec2->msgq))
nvkm_falcon_msgq_recv(sec2->msgq);
}
nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
intr &= ~0x00000040;
}
if (intr & 0x00000010) {
if (atomic_read(&sec2->running)) {
FLCN_ERR(falcon, "halted");
gm200_flcn_tracepc(falcon);
}
nvkm_falcon_wr32(falcon, 0x004, 0x00000010);
intr &= ~0x00000010;
}
if (intr) {
nvkm_error(subdev, "unhandled intr %08x\n", intr);
nvkm_falcon_wr32(falcon, 0x004, intr);
}
return IRQ_HANDLED;
}
static const struct nvkm_falcon_func
gp102_sec2_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.reset_pmc = true,
.reset_eng = gp102_flcn_reset_eng,
.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
.debug = 0x408,
.bind_inst = gm200_flcn_bind_inst,
.bind_stat = gm200_flcn_bind_stat,
.bind_intr = true,
.imem_pio = &gm200_flcn_imem_pio,
.dmem_pio = &gm200_flcn_dmem_pio,
.emem_addr = 0x01000000,
.emem_pio = &gp102_flcn_emem_pio,
.start = nvkm_falcon_v1_start,
.cmdq = { 0xa00, 0xa04, 8 },
.msgq = { 0xa30, 0xa34, 8 },
};
const struct nvkm_sec2_func
gp102_sec2 = {
.flcn = &gp102_sec2_flcn,
.unit_unload = NV_SEC2_UNIT_UNLOAD,
.unit_acr = NV_SEC2_UNIT_ACR,
.intr = gp102_sec2_intr,
.initmsg = gp102_sec2_initmsg,
};
MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");
void
gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust)
{
struct flcn_bl_dmem_desc_v2 hdr;
nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
hdr.code_dma_base = hdr.code_dma_base + adjust;
hdr.data_dma_base = hdr.data_dma_base + adjust;
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
}
void
gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld,
struct nvkm_acr_lsfw *lsfw)
{
const struct flcn_bl_dmem_desc_v2 hdr = {
.ctx_dma = FALCON_SEC2_DMAIDX_UCODE,
.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
.non_sec_code_off = lsfw->app_resident_code_offset,
.non_sec_code_size = lsfw->app_resident_code_size,
.code_entry_point = lsfw->app_imem_entry,
.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
lsfw->app_resident_data_offset,
.data_size = lsfw->app_resident_data_size,
.argc = 1,
.argv = lsfw->falcon->func->emem_addr,
};
nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
}
const struct nvkm_acr_lsf_func
gp102_sec2_acr_1 = {
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp102_sec2_acr_bld_write_1,
.bld_patch = gp102_sec2_acr_bld_patch_1,
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
BIT_ULL(NVKM_ACR_LSF_SEC2),
.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
};
int
gp102_sec2_load(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
return nvkm_acr_lsfw_load_sig_image_desc_v1(&sec2->engine.subdev,
&sec2->falcon,
NVKM_ACR_LSF_SEC2, "sec2/",
ver, fwif->acr);
}
MODULE_FIRMWARE("nvidia/gp102/sec2/desc-1.bin");
MODULE_FIRMWARE("nvidia/gp102/sec2/image-1.bin");
MODULE_FIRMWARE("nvidia/gp102/sec2/sig-1.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/desc-1.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/image-1.bin");
MODULE_FIRMWARE("nvidia/gp104/sec2/sig-1.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/desc-1.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/image-1.bin");
MODULE_FIRMWARE("nvidia/gp106/sec2/sig-1.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/desc-1.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/image-1.bin");
MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
static const struct nvkm_sec2_fwif
gp102_sec2_fwif[] = {
{ 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
{ 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
{ -1, gp102_sec2_nofw, &gp102_sec2 },
{}
};
int
gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{
return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c |
/*
* Copyright 2019 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/acr.h>
MODULE_FIRMWARE("nvidia/gp108/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gp108/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gp108/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/image.bin");
MODULE_FIRMWARE("nvidia/gv100/sec2/sig.bin");
static const struct nvkm_sec2_fwif
gp108_sec2_fwif[] = {
{ 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
{}
};
int
gp108_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{
return nvkm_sec2_new_(gp108_sec2_fwif, device, type, inst, 0, psec2);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c |
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <core/firmware.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <nvfw/sec2.h>
static int
nvkm_sec2_finimsg(void *priv, struct nvfw_falcon_msg *hdr)
{
struct nvkm_sec2 *sec2 = priv;
atomic_set(&sec2->running, 0);
return 0;
}
static int
nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
struct nvkm_subdev *subdev = &sec2->engine.subdev;
struct nvkm_falcon *falcon = &sec2->falcon;
struct nvkm_falcon_cmdq *cmdq = sec2->cmdq;
struct nvfw_falcon_cmd cmd = {
.unit_id = sec2->func->unit_unload,
.size = sizeof(cmd),
};
int ret;
if (!subdev->use.enabled)
return 0;
if (atomic_read(&sec2->initmsg) == 1) {
ret = nvkm_falcon_cmdq_send(cmdq, &cmd, nvkm_sec2_finimsg, sec2,
msecs_to_jiffies(1000));
WARN_ON(ret);
nvkm_msec(subdev->device, 2000,
if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)
break;
);
}
nvkm_inth_block(&subdev->inth);
nvkm_falcon_cmdq_fini(cmdq);
falcon->func->disable(falcon);
nvkm_falcon_put(falcon, subdev);
return 0;
}
static int
nvkm_sec2_init(struct nvkm_engine *engine)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
struct nvkm_subdev *subdev = &sec2->engine.subdev;
struct nvkm_falcon *falcon = &sec2->falcon;
int ret;
ret = nvkm_falcon_get(falcon, subdev);
if (ret)
return ret;
nvkm_falcon_wr32(falcon, 0x014, 0xffffffff);
atomic_set(&sec2->initmsg, 0);
atomic_set(&sec2->running, 1);
nvkm_inth_allow(&subdev->inth);
nvkm_falcon_start(falcon);
return 0;
}
static int
nvkm_sec2_oneinit(struct nvkm_engine *engine)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
struct nvkm_subdev *subdev = &sec2->engine.subdev;
struct nvkm_intr *intr = &sec2->engine.subdev.device->mc->intr;
enum nvkm_intr_type type = NVKM_INTR_SUBDEV;
if (sec2->func->intr_vector) {
intr = sec2->func->intr_vector(sec2, &type);
if (IS_ERR(intr))
return PTR_ERR(intr);
}
return nvkm_inth_add(intr, type, NVKM_INTR_PRIO_NORMAL, subdev, sec2->func->intr,
&subdev->inth);
}
static void *
nvkm_sec2_dtor(struct nvkm_engine *engine)
{
struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
nvkm_falcon_msgq_del(&sec2->msgq);
nvkm_falcon_cmdq_del(&sec2->cmdq);
nvkm_falcon_qmgr_del(&sec2->qmgr);
nvkm_falcon_dtor(&sec2->falcon);
return sec2;
}
static const struct nvkm_engine_func
nvkm_sec2 = {
.dtor = nvkm_sec2_dtor,
.oneinit = nvkm_sec2_oneinit,
.init = nvkm_sec2_init,
.fini = nvkm_sec2_fini,
};
int
nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2)
{
struct nvkm_sec2 *sec2;
int ret;
if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_engine_ctor(&nvkm_sec2, device, type, inst, true, &sec2->engine);
if (ret)
return ret;
fwif = nvkm_firmware_load(&sec2->engine.subdev, fwif, "Sec2", sec2);
if (IS_ERR(fwif))
return PTR_ERR(fwif);
sec2->func = fwif->func;
ret = nvkm_falcon_ctor(sec2->func->flcn, &sec2->engine.subdev,
sec2->engine.subdev.name, addr, &sec2->falcon);
if (ret)
return ret;
if ((ret = nvkm_falcon_qmgr_new(&sec2->falcon, &sec2->qmgr)) ||
(ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) ||
(ret = nvkm_falcon_msgq_new(sec2->qmgr, "msgq", &sec2->msgq)))
return ret;
return 0;
};
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c |
/*
* Copyright 2021 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/acr.h>
#include <subdev/vfn.h>
#include <nvfw/flcn.h>
#include <nvfw/sec2.h>
static int
ga102_sec2_initmsg(struct nvkm_sec2 *sec2)
{
struct nv_sec2_init_msg_v1 msg;
int ret, i;
ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg));
if (ret)
return ret;
if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT ||
msg.msg_type != NV_SEC2_INIT_MSG_INIT)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) {
if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) {
nvkm_falcon_msgq_init(sec2->msgq, msg.queue_info[i].index,
msg.queue_info[i].offset,
msg.queue_info[i].size);
} else {
nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index,
msg.queue_info[i].offset,
msg.queue_info[i].size);
}
}
return 0;
}
static struct nvkm_intr *
ga102_sec2_intr_vector(struct nvkm_sec2 *sec2, enum nvkm_intr_type *pvector)
{
struct nvkm_device *device = sec2->engine.subdev.device;
struct nvkm_falcon *falcon = &sec2->falcon;
int ret;
ret = ga102_flcn_select(falcon);
if (ret)
return ERR_PTR(ret);
*pvector = nvkm_rd32(device, 0x8403e0) & 0x000000ff;
return &device->vfn->intr;
}
static int
ga102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
{
struct nv_sec2_acr_bootstrap_falcon_msg_v1 *msg =
container_of(hdr, typeof(*msg), msg.hdr);
struct nvkm_subdev *subdev = priv;
const char *name = nvkm_acr_lsf_id(msg->falcon_id);
if (msg->error_code) {
nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for falcon %d [%s]: %08x %08x\n",
msg->falcon_id, name, msg->error_code, msg->unkn08);
return -EINVAL;
}
nvkm_debug(subdev, "%s booted\n", name);
return 0;
}
static int
ga102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon, enum nvkm_acr_lsf_id id)
{
struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);
struct nv_sec2_acr_bootstrap_falcon_cmd_v1 cmd = {
.cmd.hdr.unit_id = sec2->func->unit_acr,
.cmd.hdr.size = sizeof(cmd),
.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
.falcon_id = id,
};
return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
ga102_sec2_acr_bootstrap_falcon_callback,
&sec2->engine.subdev,
msecs_to_jiffies(1000));
}
static const struct nvkm_acr_lsf_func
ga102_sec2_acr_0 = {
.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
.bld_write = gp102_sec2_acr_bld_write_1,
.bld_patch = gp102_sec2_acr_bld_patch_1,
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
BIT_ULL(NVKM_ACR_LSF_GPCCS) |
BIT_ULL(NVKM_ACR_LSF_SEC2),
.bootstrap_falcon = ga102_sec2_acr_bootstrap_falcon,
};
static const struct nvkm_falcon_func
ga102_sec2_flcn = {
.disable = gm200_flcn_disable,
.enable = gm200_flcn_enable,
.select = ga102_flcn_select,
.addr2 = 0x1000,
.reset_pmc = true,
.reset_eng = gp102_flcn_reset_eng,
.reset_prep = ga102_flcn_reset_prep,
.reset_wait_mem_scrubbing = ga102_flcn_reset_wait_mem_scrubbing,
.imem_dma = &ga102_flcn_dma,
.dmem_pio = &gm200_flcn_dmem_pio,
.dmem_dma = &ga102_flcn_dma,
.emem_addr = 0x01000000,
.emem_pio = &gp102_flcn_emem_pio,
.start = nvkm_falcon_v1_start,
.cmdq = { 0xc00, 0xc04, 8 },
.msgq = { 0xc80, 0xc84, 8 },
};
static const struct nvkm_sec2_func
ga102_sec2 = {
.flcn = &ga102_sec2_flcn,
.intr_vector = ga102_sec2_intr_vector,
.intr = gp102_sec2_intr,
.initmsg = ga102_sec2_initmsg,
.unit_acr = NV_SEC2_UNIT_V2_ACR,
.unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
};
MODULE_FIRMWARE("nvidia/ga102/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/ga102/sec2/image.bin");
MODULE_FIRMWARE("nvidia/ga102/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/ga102/sec2/hs_bl_sig.bin");
MODULE_FIRMWARE("nvidia/ga103/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/ga103/sec2/image.bin");
MODULE_FIRMWARE("nvidia/ga103/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/ga103/sec2/hs_bl_sig.bin");
MODULE_FIRMWARE("nvidia/ga104/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/ga104/sec2/image.bin");
MODULE_FIRMWARE("nvidia/ga104/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/ga104/sec2/hs_bl_sig.bin");
MODULE_FIRMWARE("nvidia/ga106/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/ga106/sec2/image.bin");
MODULE_FIRMWARE("nvidia/ga106/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/ga106/sec2/hs_bl_sig.bin");
MODULE_FIRMWARE("nvidia/ga107/sec2/desc.bin");
MODULE_FIRMWARE("nvidia/ga107/sec2/image.bin");
MODULE_FIRMWARE("nvidia/ga107/sec2/sig.bin");
MODULE_FIRMWARE("nvidia/ga107/sec2/hs_bl_sig.bin");
static int
ga102_sec2_load(struct nvkm_sec2 *sec2, int ver,
const struct nvkm_sec2_fwif *fwif)
{
return nvkm_acr_lsfw_load_sig_image_desc_v2(&sec2->engine.subdev, &sec2->falcon,
NVKM_ACR_LSF_SEC2, "sec2/", ver, fwif->acr);
}
static const struct nvkm_sec2_fwif
ga102_sec2_fwif[] = {
{ 0, ga102_sec2_load, &ga102_sec2, &ga102_sec2_acr_0 },
{ -1, gp102_sec2_nofw, &ga102_sec2 }
};
int
ga102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{
/* TOP info wasn't updated on Turing to reflect the PRI
* address change for some reason. We override it here.
*/
return nvkm_sec2_new_(ga102_sec2_fwif, device, type, inst, 0x840000, psec2);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include "priv.h"
#include <nvif/class.h>
void
g98_msvld_init(struct nvkm_falcon *msvld)
{
struct nvkm_device *device = msvld->engine.subdev.device;
nvkm_wr32(device, 0x084010, 0x0000ffd2);
nvkm_wr32(device, 0x08401c, 0x0000fff2);
}
static const struct nvkm_falcon_func
g98_msvld = {
.init = g98_msvld_init,
.sclass = {
{ -1, -1, G98_MSVLD },
{}
}
};
int
g98_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&g98_msvld, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c |
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#include <nvif/class.h>
static const struct nvkm_falcon_func
gk104_msvld = {
.init = gf100_msvld_init,
.sclass = {
{ -1, -1, GK104_MSVLD },
{}
}
};
int
gk104_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&gk104_msvld, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c |
/*
* Copyright 2012 Maarten Lankhorst
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Maarten Lankhorst
*/
#include "priv.h"
#include <nvif/class.h>
void
gf100_msvld_init(struct nvkm_falcon *msvld)
{
struct nvkm_device *device = msvld->engine.subdev.device;
nvkm_wr32(device, 0x084010, 0x0000fff2);
nvkm_wr32(device, 0x08401c, 0x0000fff2);
}
static const struct nvkm_falcon_func
gf100_msvld = {
.init = gf100_msvld_init,
.sclass = {
{ -1, -1, GF100_MSVLD },
{}
}
};
int
gf100_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&gf100_msvld, device, type, inst, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c |
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <[email protected]>
*/
#include "priv.h"
int
nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, type, inst, true, 0x084000, pengine);
}
| linux-master | drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c |
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