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// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/dreamcast/setup.c
*
* Hardware support for the Sega Dreamcast.
*
* Copyright (c) 2001, 2002 M. R. Brown <[email protected]>
* Copyright (c) 2002, 2003, 2004 Paul Mundt <[email protected]>
*
* This file is part of the LinuxDC project (www.linuxdc.org)
*
* This file originally bore the message (with enclosed-$):
* Id: setup_dc.c,v 1.5 2001/05/24 05:09:16 mrbrown Exp
* SEGA Dreamcast support
*/
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/rtc.h>
#include <asm/machvec.h>
#include <mach/sysasic.h>
static void __init dreamcast_setup(char **cmdline_p)
{
}
static struct sh_machine_vector mv_dreamcast __initmv = {
.mv_name = "Sega Dreamcast",
.mv_setup = dreamcast_setup,
.mv_irq_demux = systemasic_irq_demux,
.mv_init_irq = systemasic_irq_init,
};
| linux-master | arch/sh/boards/mach-dreamcast/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Technology Europe RSK+ 7203 Support.
*
* Copyright (C) 2008 - 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/smsc911x.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <cpu/sh7203.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_32BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x24000000,
.end = 0x240000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 64,
.end = 64,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct gpio_led rsk7203_gpio_leds[] = {
{
.name = "green",
.gpio = GPIO_PE10,
.active_low = 1,
}, {
.name = "orange",
.default_trigger = "nand-disk",
.gpio = GPIO_PE12,
.active_low = 1,
}, {
.name = "red:timer",
.default_trigger = "timer",
.gpio = GPIO_PC14,
.active_low = 1,
}, {
.name = "red:heartbeat",
.default_trigger = "heartbeat",
.gpio = GPIO_PE11,
.active_low = 1,
},
};
static struct gpio_led_platform_data rsk7203_gpio_leds_info = {
.leds = rsk7203_gpio_leds,
.num_leds = ARRAY_SIZE(rsk7203_gpio_leds),
};
static struct platform_device led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &rsk7203_gpio_leds_info,
},
};
static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
{
.code = BTN_0,
.gpio = GPIO_PB0,
.active_low = 1,
.desc = "SW1",
}, {
.code = BTN_1,
.gpio = GPIO_PB1,
.active_low = 1,
.desc = "SW2",
}, {
.code = BTN_2,
.gpio = GPIO_PB2,
.active_low = 1,
.desc = "SW3",
},
};
static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
.buttons = rsk7203_gpio_keys_table,
.nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table),
.poll_interval = 50, /* default to 50ms */
};
static struct platform_device keys_device = {
.name = "gpio-keys-polled",
.dev = {
.platform_data = &rsk7203_gpio_keys_info,
},
};
static struct platform_device *rsk7203_devices[] __initdata = {
&smsc911x_device,
&led_device,
&keys_device,
};
static int __init rsk7203_devices_setup(void)
{
/* Select pins for SCIF0 */
gpio_request(GPIO_FN_TXD0, NULL);
gpio_request(GPIO_FN_RXD0, NULL);
/* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
__raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
gpio_request(GPIO_FN_IRQ0_PB, NULL);
return platform_add_devices(rsk7203_devices,
ARRAY_SIZE(rsk7203_devices));
}
device_initcall(rsk7203_devices_setup);
| linux-master | arch/sh/boards/mach-rsk/devices-rsk7203.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Technology Europe RSK+ Support.
*
* Copyright (C) 2008 Paul Mundt
* Copyright (C) 2008 Peter Griffin <[email protected]>
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/map.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <asm/machvec.h>
#include <asm/io.h>
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};
static struct mtd_partition rsk_partitions[] = {
{
.name = "Bootloader",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x001c0000,
}, {
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.parts = rsk_partitions,
.nr_parts = ARRAY_SIZE(rsk_partitions),
.width = 2,
};
static struct resource flash_resource = {
.start = 0x20000000,
.end = 0x20400000,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device *rsk_devices[] __initdata = {
&flash_device,
};
static int __init rsk_devices_setup(void)
{
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
return platform_add_devices(rsk_devices,
ARRAY_SIZE(rsk_devices));
}
device_initcall(rsk_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_rsk __initmv = {
.mv_name = "RSK+",
};
| linux-master | arch/sh/boards/mach-rsk/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RSK+SH7264 Support.
*
* Copyright (C) 2012 Renesas Electronics Europe
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <asm/machvec.h>
#include <asm/io.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x28000000,
.end = 0x280000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct platform_device *rsk7264_devices[] __initdata = {
&smsc911x_device,
};
static int __init rsk7264_devices_setup(void)
{
return platform_add_devices(rsk7264_devices,
ARRAY_SIZE(rsk7264_devices));
}
device_initcall(rsk7264_devices_setup);
| linux-master | arch/sh/boards/mach-rsk/devices-rsk7264.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RSK+SH7269 Support
*
* Copyright (C) 2012 Renesas Electronics Europe Ltd
* Copyright (C) 2012 Phil Edworthy
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <asm/machvec.h>
#include <asm/io.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x24000000,
.end = 0x240000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 85,
.end = 85,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct platform_device *rsk7269_devices[] __initdata = {
&smsc911x_device,
};
static int __init rsk7269_devices_setup(void)
{
return platform_add_devices(rsk7269_devices,
ARRAY_SIZE(rsk7269_devices));
}
device_initcall(rsk7269_devices_setup);
| linux-master | arch/sh/boards/mach-rsk/devices-rsk7269.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Solutions Highlander R7780MP Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/highlander.h>
enum {
UNUSED = 0,
/* board specific interrupt sources */
CF, /* Compact Flash */
TP, /* Touch panel */
SCIF1, /* FPGA SCIF1 */
SCIF0, /* FPGA SCIF0 */
SMBUS, /* SMBUS */
RTC, /* RTC Alarm */
AX88796, /* Ethernet controller */
PSW, /* Push Switch */
/* external bus connector */
EXT1, EXT2, EXT4, EXT5, EXT6,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(CF, IRQ_CF),
INTC_IRQ(TP, IRQ_TP),
INTC_IRQ(SCIF1, IRQ_SCIF1),
INTC_IRQ(SCIF0, IRQ_SCIF0),
INTC_IRQ(SMBUS, IRQ_SMBUS),
INTC_IRQ(RTC, IRQ_RTC),
INTC_IRQ(AX88796, IRQ_AX88796),
INTC_IRQ(PSW, IRQ_PSW),
INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2),
INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
INTC_IRQ(EXT6, IRQ_EXT6),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,
0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
0, IRQ_CF, IRQ_TP, IRQ_SCIF1,
IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6,
IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1,
0, IRQ_AX88796, IRQ_PSW,
};
static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
NULL, mask_registers, NULL, NULL);
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) {
printk(KERN_INFO "Using r7780mp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;
}
return NULL;
}
| linux-master | arch/sh/boards/mach-highlander/irq-r7780mp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/renesas/r7780rp/psw.c
*
* push switch support for RDBRP-1/RDBREVRP-1 debug boards.
*
* Copyright (C) 2006 Paul Mundt
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <mach/highlander.h>
#include <asm/push-switch.h>
static irqreturn_t psw_irq_handler(int irq, void *arg)
{
struct platform_device *pdev = arg;
struct push_switch *psw = platform_get_drvdata(pdev);
struct push_switch_platform_info *psw_info = pdev->dev.platform_data;
unsigned int l, mask;
int ret = 0;
l = __raw_readw(PA_DBSW);
/* Nothing to do if there's no state change */
if (psw->state) {
ret = 1;
goto out;
}
mask = l & 0x70;
/* Figure out who raised it */
if (mask & (1 << psw_info->bit)) {
psw->state = !!(mask & (1 << psw_info->bit));
if (psw->state) /* debounce */
mod_timer(&psw->debounce, jiffies + 50);
ret = 1;
}
out:
/* Clear the switch IRQs */
l |= (0x7 << 12);
__raw_writew(l, PA_DBSW);
return IRQ_RETVAL(ret);
}
static struct resource psw_resources[] = {
[0] = {
.start = IRQ_PSW,
.flags = IORESOURCE_IRQ,
},
};
static struct push_switch_platform_info s2_platform_data = {
.name = "s2",
.bit = 6,
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct platform_device s2_switch_device = {
.name = "push-switch",
.id = 0,
.num_resources = ARRAY_SIZE(psw_resources),
.resource = psw_resources,
.dev = {
.platform_data = &s2_platform_data,
},
};
static struct push_switch_platform_info s3_platform_data = {
.name = "s3",
.bit = 5,
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct platform_device s3_switch_device = {
.name = "push-switch",
.id = 1,
.num_resources = ARRAY_SIZE(psw_resources),
.resource = psw_resources,
.dev = {
.platform_data = &s3_platform_data,
},
};
static struct push_switch_platform_info s4_platform_data = {
.name = "s4",
.bit = 4,
.irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct platform_device s4_switch_device = {
.name = "push-switch",
.id = 2,
.num_resources = ARRAY_SIZE(psw_resources),
.resource = psw_resources,
.dev = {
.platform_data = &s4_platform_data,
},
};
static struct platform_device *psw_devices[] = {
&s2_switch_device, &s3_switch_device, &s4_switch_device,
};
static int __init psw_init(void)
{
return platform_add_devices(psw_devices, ARRAY_SIZE(psw_devices));
}
module_init(psw_init);
| linux-master | arch/sh/boards/mach-highlander/psw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Solutions Highlander R7785RP Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 - 2008 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/highlander.h>
enum {
UNUSED = 0,
/* FPGA specific interrupt sources */
CF, /* Compact Flash */
SMBUS, /* SMBUS */
TP, /* Touch panel */
RTC, /* RTC Alarm */
TH_ALERT, /* Temperature sensor */
AX88796, /* Ethernet controller */
/* external bus connector */
EXT0, EXT1, EXT2, EXT3, EXT4, EXT5, EXT6, EXT7,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(CF, IRQ_CF),
INTC_IRQ(SMBUS, IRQ_SMBUS),
INTC_IRQ(TP, IRQ_TP),
INTC_IRQ(RTC, IRQ_RTC),
INTC_IRQ(TH_ALERT, IRQ_TH_ALERT),
INTC_IRQ(EXT0, IRQ_EXT0), INTC_IRQ(EXT1, IRQ_EXT1),
INTC_IRQ(EXT2, IRQ_EXT2), INTC_IRQ(EXT3, IRQ_EXT3),
INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
INTC_IRQ(EXT6, IRQ_EXT6), INTC_IRQ(EXT7, IRQ_EXT7),
INTC_IRQ(AX88796, IRQ_AX88796),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4000010, 0, 16, /* IRLMCR1 */
{ 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
{ 0xa4000012, 0, 16, /* IRLMCR2 */
{ 0, 0, 0, 0, 0, 0, 0, 0,
EXT7, EXT6, EXT5, EXT4, EXT3, EXT2, EXT1, EXT0 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
IRQ_EXT6, IRQ_EXT7, IRQ_SMBUS, IRQ_TP,
IRQ_RTC, IRQ_TH_ALERT, IRQ_AX88796, IRQ_EXT0,
IRQ_EXT1, IRQ_EXT2, IRQ_EXT3,
};
static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
NULL, mask_registers, NULL, NULL);
unsigned char * __init highlander_plat_irq_setup(void)
{
if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
return NULL;
printk(KERN_INFO "Using r7785rp interrupt controller.\n");
__raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
/* Setup the FPGA IRL */
__raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
__raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
__raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
__raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
__raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
__raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
register_intc_controller(&intc_desc);
return irl2irq;
}
| linux-master | arch/sh/boards/mach-highlander/irq-r7785rp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/renesas/r7780rp/setup.c
*
* Renesas Solutions Highlander Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2005 - 2008 Paul Mundt
*
* This contains support for the R7780RP-1, R7780MP, and R7785RP
* Highlander modules.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/types.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/m66592.h>
#include <linux/clkdev.h>
#include <net/ax88796.h>
#include <asm/machvec.h>
#include <mach/highlander.h>
#include <asm/clock.h>
#include <asm/heartbeat.h>
#include <asm/io.h>
#include <asm/io_trapped.h>
static struct r8a66597_platdata r8a66597_data = {
.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
.vif = 1,
};
static struct resource r8a66597_usb_host_resources[] = {
[0] = {
.start = 0xA4200000,
.end = 0xA42000FF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_EXT1, /* irq number */
.end = IRQ_EXT1,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device r8a66597_usb_host_device = {
.name = "r8a66597_hcd",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &r8a66597_data,
},
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
.resource = r8a66597_usb_host_resources,
};
static struct m66592_platdata usbf_platdata = {
.xtal = M66592_PLATDATA_XTAL_24MHZ,
.vif = 1,
};
static struct resource m66592_usb_peripheral_resources[] = {
[0] = {
.name = "m66592_udc",
.start = 0xb0000000,
.end = 0xb00000FF,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "m66592_udc",
.start = IRQ_EXT4, /* irq number */
.end = IRQ_EXT4,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device m66592_usb_peripheral_device = {
.name = "m66592_udc",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usbf_platdata,
},
.num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources),
.resource = m66592_usb_peripheral_resources,
};
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_AREA5_IO + 0x1000,
.end = PA_AREA5_IO + 0x1000 + 0x08 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PA_AREA5_IO + 0x80c,
.end = PA_AREA5_IO + 0x80c + 0x16 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_CF,
.flags = IORESOURCE_IRQ,
},
};
static struct pata_platform_info pata_info = {
.ioport_shift = 1,
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
.dev = {
.platform_data = &pata_info,
},
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_OBLED,
.end = PA_OBLED,
.flags = IORESOURCE_MEM,
},
};
#ifndef CONFIG_SH_R7785RP
static unsigned char heartbeat_bit_pos[] = { 2, 1, 0, 3, 6, 5, 4, 7 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
#endif
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
/* R7785RP has a slightly more sensible FPGA.. */
#ifndef CONFIG_SH_R7785RP
.dev = {
.platform_data = &heartbeat_data,
},
#endif
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct ax_plat_data ax88796_platdata = {
.flags = AXFLG_HAS_93CX6,
.wordlength = 2,
.dcr_val = 0x1,
.rcr_val = 0x40,
};
static struct resource ax88796_resources[] = {
{
#ifdef CONFIG_SH_R7780RP
.start = 0xa5800400,
.end = 0xa5800400 + (0x20 * 0x2) - 1,
#else
.start = 0xa4100400,
.end = 0xa4100400 + (0x20 * 0x2) - 1,
#endif
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_AX88796,
.end = IRQ_AX88796,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ax88796_device = {
.name = "ax88796",
.id = 0,
.dev = {
.platform_data = &ax88796_platdata,
},
.num_resources = ARRAY_SIZE(ax88796_resources),
.resource = ax88796_resources,
};
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "loader",
.offset = 0x00000000,
.size = 512 * 1024,
},
{
.name = "bootenv",
.offset = MTDPART_OFS_APPEND,
.size = 512 * 1024,
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 4 * 1024 * 1024,
},
{
.name = "data",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 4,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
/* This config is flash board for mass production. */
static struct resource nor_flash_resources[] = {
[0] = {
.start = PA_NORFLASH_ADDR,
.end = PA_NORFLASH_ADDR + PA_NORFLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.dev = {
.platform_data = &nor_flash_data,
},
.num_resources = ARRAY_SIZE(nor_flash_resources),
.resource = nor_flash_resources,
};
static struct resource smbus_resources[] = {
[0] = {
.start = PA_SMCR,
.end = PA_SMCR + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SMBUS,
.end = IRQ_SMBUS,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smbus_device = {
.name = "i2c-highlander",
.id = 0,
.num_resources = ARRAY_SIZE(smbus_resources),
.resource = smbus_resources,
};
static struct i2c_board_info __initdata highlander_i2c_devices[] = {
{
I2C_BOARD_INFO("r2025sd", 0x32),
},
};
static struct platform_device *r7780rp_devices[] __initdata = {
&r8a66597_usb_host_device,
&m66592_usb_peripheral_device,
&heartbeat_device,
&smbus_device,
&nor_flash_device,
#ifndef CONFIG_SH_R7780RP
&ax88796_device,
#endif
};
/*
* The CF is connected using a 16-bit bus where 8-bit operations are
* unsupported. The linux ata driver is however using 8-bit operations, so
* insert a trapped io filter to convert 8-bit operations into 16-bit.
*/
static struct trapped_io cf_trapped_io = {
.resource = cf_ide_resources,
.num_resources = 2,
.minimum_bus_width = 16,
};
static int __init r7780rp_devices_setup(void)
{
int ret = 0;
#ifndef CONFIG_SH_R7780RP
if (register_trapped_io(&cf_trapped_io) == 0)
ret |= platform_device_register(&cf_ide_device);
#endif
ret |= platform_add_devices(r7780rp_devices,
ARRAY_SIZE(r7780rp_devices));
ret |= i2c_register_board_info(0, highlander_i2c_devices,
ARRAY_SIZE(highlander_i2c_devices));
return ret;
}
device_initcall(r7780rp_devices_setup);
/*
* Platform specific clocks
*/
static int ivdr_clk_enable(struct clk *clk)
{
__raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
return 0;
}
static void ivdr_clk_disable(struct clk *clk)
{
__raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
}
static struct sh_clk_ops ivdr_clk_ops = {
.enable = ivdr_clk_enable,
.disable = ivdr_clk_disable,
};
static struct clk ivdr_clk = {
.ops = &ivdr_clk_ops,
};
static struct clk *r7780rp_clocks[] = {
&ivdr_clk,
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("ivdr_clk", &ivdr_clk),
};
static void r7780rp_power_off(void)
{
if (mach_is_r7780mp() || mach_is_r7785rp())
__raw_writew(0x0001, PA_POFF);
}
/*
* Initialize the board
*/
static void __init highlander_setup(char **cmdline_p)
{
u16 ver = __raw_readw(PA_VERREG);
int i;
printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
mach_is_r7780rp() ? "R7780RP-1" :
mach_is_r7780mp() ? "R7780MP" :
"R7785RP");
printk(KERN_INFO "Board version: %d (revision %d), "
"FPGA version: %d (revision %d)\n",
(ver >> 12) & 0xf, (ver >> 8) & 0xf,
(ver >> 4) & 0xf, ver & 0xf);
highlander_plat_pinmux_setup();
/*
* Enable the important clocks right away..
*/
for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) {
struct clk *clk = r7780rp_clocks[i];
clk_register(clk);
clk_enable(clk);
}
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
__raw_writew(0x0000, PA_OBLED); /* Clear LED. */
if (mach_is_r7780rp())
__raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
__raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
pm_power_off = r7780rp_power_off;
}
static unsigned char irl2irq[HL_NR_IRL];
static int highlander_irq_demux(int irq)
{
if (irq >= HL_NR_IRL + 16 || irq < 16 || !irl2irq[irq - 16])
return irq;
return irl2irq[irq - 16];
}
static void __init highlander_init_irq(void)
{
unsigned char *ucp = highlander_plat_irq_setup();
if (ucp) {
plat_irq_setup_pins(IRQ_MODE_IRL3210);
memcpy(irl2irq, ucp, HL_NR_IRL);
}
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_highlander __initmv = {
.mv_name = "Highlander",
.mv_setup = highlander_setup,
.mv_init_irq = highlander_init_irq,
.mv_irq_demux = highlander_irq_demux,
};
| linux-master | arch/sh/boards/mach-highlander/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2008 Paul Mundt
*/
#include <linux/init.h>
#include <linux/gpio.h>
#include <cpu/sh7785.h>
void __init highlander_plat_pinmux_setup(void)
{
/* SCIF0 */
gpio_request(GPIO_FN_SCIF0_CTS, NULL);
gpio_request(GPIO_FN_SCIF0_RTS, NULL);
gpio_request(GPIO_FN_SCIF0_SCK, NULL);
gpio_request(GPIO_FN_SCIF0_RXD, NULL);
gpio_request(GPIO_FN_SCIF0_TXD, NULL);
}
| linux-master | arch/sh/boards/mach-highlander/pinmux-r7785rp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Solutions Highlander R7780RP-1 Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2008 Magnus Damm
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/highlander.h>
enum {
UNUSED = 0,
/* board specific interrupt sources */
AX88796, /* Ethernet controller */
PSW, /* Push Switch */
CF, /* Compact Flash */
PCI_A,
PCI_B,
PCI_C,
PCI_D,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(PCI_A, 65), /* dirty: overwrite cpu vectors for pci */
INTC_IRQ(PCI_B, 66),
INTC_IRQ(PCI_C, 67),
INTC_IRQ(PCI_D, 68),
INTC_IRQ(CF, IRQ_CF),
INTC_IRQ(PSW, IRQ_PSW),
INTC_IRQ(AX88796, IRQ_AX88796),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa5000000, 0, 16, /* IRLMSK */
{ PCI_A, PCI_B, PCI_C, PCI_D, CF, 0, 0, 0,
0, 0, 0, 0, 0, 0, PSW, AX88796 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
65, 66, 67, 68,
IRQ_CF, 0, 0, 0,
0, 0, 0, 0,
IRQ_AX88796, IRQ_PSW
};
static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
NULL, mask_registers, NULL, NULL);
unsigned char * __init highlander_plat_irq_setup(void)
{
if (__raw_readw(0xa5000600)) {
printk(KERN_INFO "Using r7780rp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;
}
return NULL;
}
| linux-master | arch/sh/boards/mach-highlander/irq-r7780rp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/sh03/rtc.c -- CTP/PCI-SH03 on-chip RTC support
*
* Copyright (C) 2004 Saito.K & Jeanne([email protected])
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/bcd.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#define RTC_BASE 0xb0000000
#define RTC_SEC1 (RTC_BASE + 0)
#define RTC_SEC10 (RTC_BASE + 1)
#define RTC_MIN1 (RTC_BASE + 2)
#define RTC_MIN10 (RTC_BASE + 3)
#define RTC_HOU1 (RTC_BASE + 4)
#define RTC_HOU10 (RTC_BASE + 5)
#define RTC_WEE1 (RTC_BASE + 6)
#define RTC_DAY1 (RTC_BASE + 7)
#define RTC_DAY10 (RTC_BASE + 8)
#define RTC_MON1 (RTC_BASE + 9)
#define RTC_MON10 (RTC_BASE + 10)
#define RTC_YEA1 (RTC_BASE + 11)
#define RTC_YEA10 (RTC_BASE + 12)
#define RTC_YEA100 (RTC_BASE + 13)
#define RTC_YEA1000 (RTC_BASE + 14)
#define RTC_CTL (RTC_BASE + 15)
#define RTC_BUSY 1
#define RTC_STOP 2
static DEFINE_SPINLOCK(sh03_rtc_lock);
static int sh03_rtc_gettimeofday(struct device *dev, struct rtc_time *tm)
{
unsigned int year, mon, day, hour, min, sec;
spin_lock(&sh03_rtc_lock);
again:
do {
sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10;
min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10;
day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10;
mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10;
year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10
+ (__raw_readb(RTC_YEA100 ) & 0xf) * 100
+ (__raw_readb(RTC_YEA1000) & 0xf) * 1000;
} while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10);
if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
hour > 23 || min > 59 || sec > 59) {
printk(KERN_ERR
"SH-03 RTC: invalid value, resetting to 1 Jan 2000\n");
printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n",
year, mon, day, hour, min, sec);
__raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10);
__raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10);
__raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10);
__raw_writeb(6, RTC_WEE1);
__raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10);
__raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10);
__raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10);
__raw_writeb(0, RTC_YEA100);
__raw_writeb(2, RTC_YEA1000);
__raw_writeb(0, RTC_CTL);
goto again;
}
spin_unlock(&sh03_rtc_lock);
tm->tm_sec = sec;
tm->tm_min = min;
tm->tm_hour = hour;
tm->tm_mday = day;
tm->tm_mon = mon;
tm->tm_year = year - 1900;
return 0;
}
static int set_rtc_mmss(struct rtc_time *tm)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
int i;
/* gets recalled with irq locally disabled */
spin_lock(&sh03_rtc_lock);
for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
if (!(__raw_readb(RTC_CTL) & RTC_BUSY))
break;
cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
real_seconds = tm->tm_sec;
real_minutes = tm->tm_min;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
__raw_writeb(real_seconds % 10, RTC_SEC1);
__raw_writeb(real_seconds / 10, RTC_SEC10);
__raw_writeb(real_minutes % 10, RTC_MIN1);
__raw_writeb(real_minutes / 10, RTC_MIN10);
} else {
printk_once(KERN_NOTICE
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -EINVAL;
}
spin_unlock(&sh03_rtc_lock);
return retval;
}
int sh03_rtc_settimeofday(struct device *dev, struct rtc_time *tm)
{
return set_rtc_mmss(tm);
}
static const struct rtc_class_ops rtc_generic_ops = {
.read_time = sh03_rtc_gettimeofday,
.set_time = sh03_rtc_settimeofday,
};
static int __init sh03_time_init(void)
{
struct platform_device *pdev;
pdev = platform_device_register_data(NULL, "rtc-generic", -1,
&rtc_generic_ops,
sizeof(rtc_generic_ops));
return PTR_ERR_OR_ZERO(pdev);
}
arch_initcall(sh03_time_init);
| linux-master | arch/sh/boards/mach-sh03/rtc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/sh03/setup.c
*
* Copyright (C) 2004 Interface Co.,Ltd. Saito.K
*
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <mach-sh03/mach/io.h>
#include <mach-sh03/mach/sh03.h>
#include <asm/addrspace.h>
static void __init init_sh03_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static struct resource cf_ide_resources[] = {
[0] = {
.start = 0x1f0,
.end = 0x1f0 + 8,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 0x1f0 + 0x206,
.end = 0x1f0 +8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
.start = IRL2_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xa0800000,
.end = 0xa0800000,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct platform_device *sh03_devices[] __initdata = {
&heartbeat_device,
&cf_ide_device,
};
static int __init sh03_devices_setup(void)
{
pgprot_t prot;
unsigned long paddrbase;
void *cf_ide_base;
/* open I/O area window */
paddrbase = virt_to_phys((void *)PA_AREA5_IO);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
if (!cf_ide_base) {
printk("allocate_cf_area : can't open CF I/O window!\n");
return -ENOMEM;
}
/* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */
cf_ide_resources[0].start += (unsigned long)cf_ide_base;
cf_ide_resources[0].end += (unsigned long)cf_ide_base;
cf_ide_resources[1].start += (unsigned long)cf_ide_base;
cf_ide_resources[1].end += (unsigned long)cf_ide_base;
return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices));
}
device_initcall(sh03_devices_setup);
static struct sh_machine_vector mv_sh03 __initmv = {
.mv_name = "Interface (CTP/PCI-SH03)",
.mv_init_irq = init_sh03_IRQ,
};
| linux-master | arch/sh/boards/mach-sh03/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* KFR2R09 board support code
*
* Copyright (C) 2009 Magnus Damm
*/
#include <asm/clock.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/suspend.h>
#include <cpu/sh7724.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_data/lv5207lp.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_intc.h>
#include <linux/usb/r8a66597.h>
#include <linux/videodev2.h>
#include <linux/dma-map-ops.h>
#include <mach/kfr2r09.h>
#include <media/drv-intf/renesas-ceu.h>
#include <media/i2c/rj54n1cb0c.h>
#include <video/sh_mobile_lcdc.h>
#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
static phys_addr_t ceu_dma_membase;
/* set VIO_CKO clock to 25MHz */
#define CEU_MCLK_FREQ 25000000
#define DRVCRB 0xA405018C
static struct mtd_partition kfr2r09_nor_flash_partitions[] =
{
{
.name = "boot",
.offset = 0,
.size = (4 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "other",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data kfr2r09_nor_flash_data = {
.width = 2,
.parts = kfr2r09_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(kfr2r09_nor_flash_partitions),
};
static struct resource kfr2r09_nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x03ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device kfr2r09_nor_flash_device = {
.name = "physmap-flash",
.resource = kfr2r09_nor_flash_resources,
.num_resources = ARRAY_SIZE(kfr2r09_nor_flash_resources),
.dev = {
.platform_data = &kfr2r09_nor_flash_data,
},
};
static struct resource kfr2r09_nand_flash_resources[] = {
[0] = {
.name = "NAND Flash",
.start = 0x10000000,
.end = 0x1001ffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device kfr2r09_nand_flash_device = {
.name = "onenand-flash",
.resource = kfr2r09_nand_flash_resources,
.num_resources = ARRAY_SIZE(kfr2r09_nand_flash_resources),
};
static struct sh_keysc_info kfr2r09_sh_keysc_info = {
.mode = SH_KEYSC_MODE_1, /* KEYOUT0->4, KEYIN0->4 */
.scan_timing = 3,
.delay = 10,
.keycodes = {
KEY_PHONE, KEY_CLEAR, KEY_MAIL, KEY_WWW, KEY_ENTER,
KEY_1, KEY_2, KEY_3, 0, KEY_UP,
KEY_4, KEY_5, KEY_6, 0, KEY_LEFT,
KEY_7, KEY_8, KEY_9, KEY_PROG1, KEY_RIGHT,
KEY_S, KEY_0, KEY_P, KEY_PROG2, KEY_DOWN,
0, 0, 0, 0, 0
},
};
static struct resource kfr2r09_sh_keysc_resources[] = {
[0] = {
.name = "KEYSC",
.start = 0x044b0000,
.end = 0x044b000f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kfr2r09_sh_keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(kfr2r09_sh_keysc_resources),
.resource = kfr2r09_sh_keysc_resources,
.dev = {
.platform_data = &kfr2r09_sh_keysc_info,
},
};
static const struct fb_videomode kfr2r09_lcdc_modes[] = {
{
.name = "TX07D34VM0AAA",
.xres = 240,
.yres = 400,
.left_margin = 0,
.right_margin = 16,
.hsync_len = 8,
.upper_margin = 0,
.lower_margin = 1,
.vsync_len = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
},
};
static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = SYS18,
.clock_divider = 6,
.flags = LCDC_FLAGS_DWPOL,
.lcd_modes = kfr2r09_lcdc_modes,
.num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes),
.panel_cfg = {
.width = 35,
.height = 58,
.setup_sys = kfr2r09_lcd_setup,
.start_transfer = kfr2r09_lcd_start,
},
.sys_bus_cfg = {
.ldmt2r = 0x07010904,
.ldmt3r = 0x14012914,
/* set 1s delay to encourage fsync() */
.deferred_io_msec = 1000,
},
}
};
static struct resource kfr2r09_sh_lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000, /* P4-only space */
.end = 0xfe942fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kfr2r09_sh_lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(kfr2r09_sh_lcdc_resources),
.resource = kfr2r09_sh_lcdc_resources,
.dev = {
.platform_data = &kfr2r09_sh_lcdc_info,
},
};
static struct lv5207lp_platform_data kfr2r09_backlight_data = {
.dev = &kfr2r09_sh_lcdc_device.dev,
.def_value = 13,
.max_value = 13,
};
static struct i2c_board_info kfr2r09_backlight_board_info = {
I2C_BOARD_INFO("lv5207lp", 0x75),
.platform_data = &kfr2r09_backlight_data,
};
static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
.on_chip = 1,
};
static struct resource kfr2r09_usb0_gadget_resources[] = {
[0] = {
.start = 0x04d80000,
.end = 0x04d80123,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa20),
.end = evt2irq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device kfr2r09_usb0_gadget_device = {
.name = "r8a66597_udc",
.id = 0,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &kfr2r09_usb0_gadget_data,
},
.num_resources = ARRAY_SIZE(kfr2r09_usb0_gadget_resources),
.resource = kfr2r09_usb0_gadget_resources,
};
static struct ceu_platform_data ceu_pdata = {
.num_subdevs = 1,
.subdevs = {
{ /* [0] = rj54n1cb0c */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 1,
.i2c_address = 0x50,
},
},
};
static struct resource kfr2r09_ceu_resources[] = {
[0] = {
.name = "CEU",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x880),
.end = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kfr2r09_ceu_device = {
.name = "renesas-ceu",
.id = 0, /* "ceu0" clock */
.num_resources = ARRAY_SIZE(kfr2r09_ceu_resources),
.resource = kfr2r09_ceu_resources,
.dev = {
.platform_data = &ceu_pdata,
},
};
static struct rj54n1_pdata rj54n1_priv = {
.mclk_freq = CEU_MCLK_FREQ,
.ioctl_high = false,
};
static struct i2c_board_info kfr2r09_i2c_camera = {
I2C_BOARD_INFO("rj54n1cb0c", 0x50),
.platform_data = &rj54n1_priv,
};
static struct gpiod_lookup_table rj54n1_gpios = {
.dev_id = "1-0050",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTB4, "poweron",
GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sh7724_pfc", GPIO_PTB7, "enable",
GPIO_ACTIVE_HIGH),
},
};
/* Fixed 3.3V regulator to be used by SDHI0 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};
static struct resource kfr2r09_sh_sdhi0_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0x04ce0000,
.end = 0x04ce00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sh7724_sdhi0_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
};
static struct platform_device kfr2r09_sh_sdhi0_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(kfr2r09_sh_sdhi0_resources),
.resource = kfr2r09_sh_sdhi0_resources,
.dev = {
.platform_data = &sh7724_sdhi0_data,
},
};
static struct platform_device *kfr2r09_devices[] __initdata = {
&kfr2r09_nor_flash_device,
&kfr2r09_nand_flash_device,
&kfr2r09_sh_keysc_device,
&kfr2r09_sh_lcdc_device,
&kfr2r09_sh_sdhi0_device,
};
#define BSC_CS0BCR 0xfec10004
#define BSC_CS0WCR 0xfec10024
#define BSC_CS4BCR 0xfec10010
#define BSC_CS4WCR 0xfec10030
#define PORT_MSELCRB 0xa4050182
#ifdef CONFIG_I2C
static int kfr2r09_usb0_gadget_i2c_setup(void)
{
struct i2c_adapter *a;
struct i2c_msg msg;
unsigned char buf[2];
int ret;
a = i2c_get_adapter(0);
if (!a)
return -ENODEV;
/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[0] = 0;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = I2C_M_RD;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[1] = buf[0] | (1 << 1);
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 2;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
return 0;
}
static int kfr2r09_serial_i2c_setup(void)
{
struct i2c_adapter *a;
struct i2c_msg msg;
unsigned char buf[2];
int ret;
a = i2c_get_adapter(0);
if (!a)
return -ENODEV;
/* set bit 6 (the 7th bit) of chip at 0x09, register 0x13 */
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[0] = 0;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = I2C_M_RD;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[1] = buf[0] | (1 << 6);
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 2;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
return 0;
}
#else
static int kfr2r09_usb0_gadget_i2c_setup(void)
{
return -ENODEV;
}
static int kfr2r09_serial_i2c_setup(void)
{
return -ENODEV;
}
#endif
static int kfr2r09_usb0_gadget_setup(void)
{
int plugged_in;
gpio_request(GPIO_PTN4, NULL); /* USB_DET */
gpio_direction_input(GPIO_PTN4);
plugged_in = gpio_get_value(GPIO_PTN4);
if (!plugged_in)
return -ENODEV; /* no cable plugged in */
if (kfr2r09_usb0_gadget_i2c_setup() != 0)
return -ENODEV; /* unable to configure using i2c */
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
msleep(20); /* wait 20ms to let the clock settle */
clk_enable(clk_get(NULL, "usb0"));
__raw_writew(0x0600, 0xa40501d4);
return 0;
}
extern char kfr2r09_sdram_enter_start;
extern char kfr2r09_sdram_enter_end;
extern char kfr2r09_sdram_leave_start;
extern char kfr2r09_sdram_leave_end;
static int __init kfr2r09_devices_setup(void)
{
struct clk *camera_clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&kfr2r09_sdram_enter_start,
&kfr2r09_sdram_enter_end,
&kfr2r09_sdram_leave_start,
&kfr2r09_sdram_leave_end);
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* enable SCIF1 serial port for YC401 console support */
gpio_request(GPIO_FN_SCIF1_RXD, NULL);
gpio_request(GPIO_FN_SCIF1_TXD, NULL);
kfr2r09_serial_i2c_setup(); /* ECONTMSK(bit6=L10ONEN) set 1 */
gpio_request(GPIO_PTG3, NULL); /* HPON_ON */
gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
/* setup NOR flash at CS0 */
__raw_writel(0x36db0400, BSC_CS0BCR);
__raw_writel(0x00000500, BSC_CS0WCR);
/* setup NAND flash at CS4 */
__raw_writel(0x36db0400, BSC_CS4BCR);
__raw_writel(0x00000500, BSC_CS4WCR);
/* setup KEYSC pins */
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYIN0, NULL);
gpio_request(GPIO_FN_KEYIN1, NULL);
gpio_request(GPIO_FN_KEYIN2, NULL);
gpio_request(GPIO_FN_KEYIN3, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
/* setup LCDC pins for SYS panel */
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDRS, NULL); /* LCD_RS */
gpio_request(GPIO_FN_LCDCS, NULL); /* LCD_CS/ */
gpio_request(GPIO_FN_LCDRD, NULL); /* LCD_RD/ */
gpio_request(GPIO_FN_LCDWR, NULL); /* LCD_WR/ */
gpio_request(GPIO_FN_LCDVSYN, NULL); /* LCD_VSYNC */
gpio_request(GPIO_PTE4, NULL); /* LCD_RST/ */
gpio_direction_output(GPIO_PTE4, 1);
gpio_request(GPIO_PTF4, NULL); /* PROTECT/ */
gpio_direction_output(GPIO_PTF4, 1);
gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */
gpio_direction_output(GPIO_PTU0, 1);
/* setup USB function */
if (kfr2r09_usb0_gadget_setup() == 0)
platform_device_register(&kfr2r09_usb0_gadget_device);
/* CEU */
gpio_request(GPIO_FN_VIO_CKO, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
/* SDHI0 connected to yc304 */
gpio_request(GPIO_FN_SDHI0CD, NULL);
gpio_request(GPIO_FN_SDHI0D3, NULL);
gpio_request(GPIO_FN_SDHI0D2, NULL);
gpio_request(GPIO_FN_SDHI0D1, NULL);
gpio_request(GPIO_FN_SDHI0D0, NULL);
gpio_request(GPIO_FN_SDHI0CMD, NULL);
gpio_request(GPIO_FN_SDHI0CLK, NULL);
i2c_register_board_info(0, &kfr2r09_backlight_board_info, 1);
/* Set camera clock frequency and register and alias for rj54n1. */
camera_clk = clk_get(NULL, "video_clk");
if (!IS_ERR(camera_clk)) {
clk_set_rate(camera_clk,
clk_round_rate(camera_clk, CEU_MCLK_FREQ));
clk_put(camera_clk);
}
clk_add_alias(NULL, "1-0050", "video_clk", NULL);
/* set DRVCRB
*
* use 1.8 V for VccQ_VIO
* use 2.85V for VccQ_SR
*/
__raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
gpiod_add_lookup_table(&rj54n1_gpios);
i2c_register_board_info(1, &kfr2r09_i2c_camera, 1);
/* Initialize CEU platform device separately to map memory first */
device_initialize(&kfr2r09_ceu_device.dev);
dma_declare_coherent_memory(&kfr2r09_ceu_device.dev,
ceu_dma_membase, ceu_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(&kfr2r09_ceu_device);
return platform_add_devices(kfr2r09_devices,
ARRAY_SIZE(kfr2r09_devices));
}
device_initcall(kfr2r09_devices_setup);
/* Return the board specific boot mode pin configuration */
static int kfr2r09_mode_pins(void)
{
/* MD0=1, MD1=1, MD2=0: Clock Mode 3
* MD3=0: 16-bit Area0 Bus Width
* MD5=1: Little Endian
* MD8=1: Test Mode Disabled
*/
return MODE_PIN0 | MODE_PIN1 | MODE_PIN5 | MODE_PIN8;
}
/* Reserve a portion of memory for CEU buffers */
static void __init kfr2r09_mv_mem_reserve(void)
{
phys_addr_t phys;
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu_dma_membase = phys;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_kfr2r09 __initmv = {
.mv_name = "kfr2r09",
.mv_mode_pins = kfr2r09_mode_pins,
.mv_mem_reserve = kfr2r09_mv_mem_reserve,
};
| linux-master | arch/sh/boards/mach-kfr2r09/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* KFR2R09 LCD panel support
*
* Copyright (C) 2009 Magnus Damm
*
* Register settings based on the out-of-tree t33fb.c driver
* Copyright (C) 2008 Lineo Solutions, Inc.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <video/sh_mobile_lcdc.h>
#include <mach/kfr2r09.h>
#include <cpu/sh7724.h>
/* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made
* up of a 240x400 LCD hooked up to a R61517 driver IC. The driver IC is
* communicating with the main port of the LCDC using an 18-bit SYS interface.
*
* The device code for this LCD module is 0x01221517.
*/
static const unsigned char data_frame_if[] = {
0x02, /* WEMODE: 1=cont, 0=one-shot */
0x00, 0x00,
0x00, /* EPF, DFM */
0x02, /* RIM[1] : 1 (18bpp) */
};
static const unsigned char data_panel[] = {
0x0b,
0x63, /* 400 lines */
0x04, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00,
};
static const unsigned char data_timing[] = {
0x00, 0x00, 0x13, 0x08, 0x08,
};
static const unsigned char data_timing_src[] = {
0x11, 0x01, 0x00, 0x01,
};
static const unsigned char data_gamma[] = {
0x01, 0x02, 0x08, 0x23, 0x03, 0x0c, 0x00, 0x06, 0x00, 0x00,
0x01, 0x00, 0x0c, 0x23, 0x03, 0x08, 0x02, 0x06, 0x00, 0x00,
};
static const unsigned char data_power[] = {
0x07, 0xc5, 0xdc, 0x02, 0x33, 0x0a,
};
static unsigned long read_reg(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
{
return so->read_data(sohandle);
}
static void write_reg(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so,
int i, unsigned long v)
{
if (i)
so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */
else
so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */
}
static void write_data(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so,
unsigned char const *data, int no_data)
{
int i;
for (i = 0; i < no_data; i++)
write_reg(sohandle, so, 1, data[i]);
}
static unsigned long read_device_code(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
{
unsigned long device_code;
/* access protect OFF */
write_reg(sohandle, so, 0, 0xb0);
write_reg(sohandle, so, 1, 0x00);
/* deep standby OFF */
write_reg(sohandle, so, 0, 0xb1);
write_reg(sohandle, so, 1, 0x00);
/* device code command */
write_reg(sohandle, so, 0, 0xbf);
mdelay(50);
/* dummy read */
read_reg(sohandle, so);
/* read device code */
device_code = ((read_reg(sohandle, so) & 0xff) << 24);
device_code |= ((read_reg(sohandle, so) & 0xff) << 16);
device_code |= ((read_reg(sohandle, so) & 0xff) << 8);
device_code |= (read_reg(sohandle, so) & 0xff);
return device_code;
}
static void write_memory_start(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
{
write_reg(sohandle, so, 0, 0x2c);
}
static void clear_memory(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
{
int i;
/* write start */
write_memory_start(sohandle, so);
/* paint it black */
for (i = 0; i < (240 * 400); i++)
write_reg(sohandle, so, 1, 0x00);
}
static void display_on(void *sohandle,
struct sh_mobile_lcdc_sys_bus_ops *so)
{
/* access protect off */
write_reg(sohandle, so, 0, 0xb0);
write_reg(sohandle, so, 1, 0x00);
/* exit deep standby mode */
write_reg(sohandle, so, 0, 0xb1);
write_reg(sohandle, so, 1, 0x00);
/* frame memory I/F */
write_reg(sohandle, so, 0, 0xb3);
write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if));
/* display mode and frame memory write mode */
write_reg(sohandle, so, 0, 0xb4);
write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */
/* panel */
write_reg(sohandle, so, 0, 0xc0);
write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel));
/* timing (normal) */
write_reg(sohandle, so, 0, 0xc1);
write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
/* timing (partial) */
write_reg(sohandle, so, 0, 0xc2);
write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
/* timing (idle) */
write_reg(sohandle, so, 0, 0xc3);
write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
/* timing (source/VCOM/gate driving) */
write_reg(sohandle, so, 0, 0xc4);
write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src));
/* gamma (red) */
write_reg(sohandle, so, 0, 0xc8);
write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
/* gamma (green) */
write_reg(sohandle, so, 0, 0xc9);
write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
/* gamma (blue) */
write_reg(sohandle, so, 0, 0xca);
write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
/* power (common) */
write_reg(sohandle, so, 0, 0xd0);
write_data(sohandle, so, data_power, ARRAY_SIZE(data_power));
/* VCOM */
write_reg(sohandle, so, 0, 0xd1);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x0f);
write_reg(sohandle, so, 1, 0x02);
/* power (normal) */
write_reg(sohandle, so, 0, 0xd2);
write_reg(sohandle, so, 1, 0x63);
write_reg(sohandle, so, 1, 0x24);
/* power (partial) */
write_reg(sohandle, so, 0, 0xd3);
write_reg(sohandle, so, 1, 0x63);
write_reg(sohandle, so, 1, 0x24);
/* power (idle) */
write_reg(sohandle, so, 0, 0xd4);
write_reg(sohandle, so, 1, 0x63);
write_reg(sohandle, so, 1, 0x24);
write_reg(sohandle, so, 0, 0xd8);
write_reg(sohandle, so, 1, 0x77);
write_reg(sohandle, so, 1, 0x77);
/* TE signal */
write_reg(sohandle, so, 0, 0x35);
write_reg(sohandle, so, 1, 0x00);
/* TE signal line */
write_reg(sohandle, so, 0, 0x44);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x00);
/* column address */
write_reg(sohandle, so, 0, 0x2a);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0xef);
/* page address */
write_reg(sohandle, so, 0, 0x2b);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x00);
write_reg(sohandle, so, 1, 0x01);
write_reg(sohandle, so, 1, 0x8f);
/* exit sleep mode */
write_reg(sohandle, so, 0, 0x11);
mdelay(120);
/* clear vram */
clear_memory(sohandle, so);
/* display ON */
write_reg(sohandle, so, 0, 0x29);
mdelay(1);
write_memory_start(sohandle, so);
}
int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
/* power on */
gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */
gpio_set_value(GPIO_PTE4, 0); /* LCD_RST/ -> L */
gpio_set_value(GPIO_PTF4, 1); /* PROTECT/ -> H */
udelay(1100);
gpio_set_value(GPIO_PTE4, 1); /* LCD_RST/ -> H */
udelay(10);
gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */
mdelay(20);
if (read_device_code(sohandle, so) != 0x01221517)
return -ENODEV;
pr_info("KFR2R09 WQVGA LCD Module detected.\n");
display_on(sohandle, so);
return 0;
}
void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
write_memory_start(sohandle, so);
}
| linux-master | arch/sh/boards/mach-kfr2r09/lcd_wqvga.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Support for SuperH MigoR Quarter VGA LCD Panel
*
* Copyright (C) 2008 Magnus Damm
*
* Based on lcd_powertip.c from Kenati Technologies Pvt Ltd.
* Copyright (c) 2007 Ujjwal Pande <[email protected]>,
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <video/sh_mobile_lcdc.h>
#include <cpu/sh7722.h>
#include <mach/migor.h>
/* LCD Module is a PH240320T according to board schematics. This module
* is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
* Driver IC. This IC is connected to the SH7722 built-in LCDC using a
* SYS-80 interface configured in 16 bit mode.
*
* Index 0: "Device Code Read" returns 0x1505.
*/
static void reset_lcd_module(void)
{
gpio_set_value(GPIO_PTH2, 0);
mdelay(2);
gpio_set_value(GPIO_PTH2, 1);
mdelay(1);
}
/* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
static unsigned long adjust_reg18(unsigned short data)
{
unsigned long tmp1, tmp2;
tmp1 = (data<<1 | 0x00000001) & 0x000001FF;
tmp2 = (data<<2 | 0x00000200) & 0x0003FE00;
return tmp1 | tmp2;
}
static void write_reg(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
unsigned short reg, unsigned short data)
{
sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data));
}
static void write_reg16(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
unsigned short reg, unsigned short data)
{
sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
sys_ops->write_data(sys_ops_handle, adjust_reg18(data));
}
static unsigned long read_reg16(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
unsigned short reg)
{
unsigned long data;
sys_ops->write_index(sys_ops_handle, adjust_reg18(reg));
data = sys_ops->read_data(sys_ops_handle);
return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00);
}
static void migor_lcd_qvga_seq(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops,
unsigned short const *data, int no_data)
{
int i;
for (i = 0; i < no_data; i += 2)
write_reg16(sys_ops_handle, sys_ops, data[i], data[i + 1]);
}
static const unsigned short sync_data[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};
static const unsigned short magic0_data[] = {
0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001,
0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116,
0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8,
};
static const unsigned short magic1_data[] = {
0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202,
0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303,
0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102,
0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300,
0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000,
0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000,
0x0015, 0x8000,
};
static const unsigned short magic2_data[] = {
0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021,
};
static const unsigned short magic3_data[] = {
0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061,
};
int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
{
unsigned long xres = 320;
unsigned long yres = 240;
int k;
reset_lcd_module();
migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
if (read_reg16(sohandle, so, 0) != 0x1505)
return -ENODEV;
pr_info("Migo-R QVGA LCD Module detected.\n");
migor_lcd_qvga_seq(sohandle, so, sync_data, ARRAY_SIZE(sync_data));
write_reg16(sohandle, so, 0x00A4, 0x0001);
mdelay(10);
migor_lcd_qvga_seq(sohandle, so, magic0_data, ARRAY_SIZE(magic0_data));
mdelay(100);
migor_lcd_qvga_seq(sohandle, so, magic1_data, ARRAY_SIZE(magic1_data));
write_reg16(sohandle, so, 0x0050, 0xef - (yres - 1));
write_reg16(sohandle, so, 0x0051, 0x00ef);
write_reg16(sohandle, so, 0x0052, 0x0000);
write_reg16(sohandle, so, 0x0053, xres - 1);
migor_lcd_qvga_seq(sohandle, so, magic2_data, ARRAY_SIZE(magic2_data));
mdelay(10);
migor_lcd_qvga_seq(sohandle, so, magic3_data, ARRAY_SIZE(magic3_data));
mdelay(40);
/* clear GRAM to avoid displaying garbage */
write_reg16(sohandle, so, 0x0020, 0x0000); /* horiz addr */
write_reg16(sohandle, so, 0x0021, 0x0000); /* vert addr */
for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */
write_reg16(sohandle, so, 0x0022, 0x0000);
write_reg16(sohandle, so, 0x0020, 0x0000); /* reset horiz addr */
write_reg16(sohandle, so, 0x0021, 0x0000); /* reset vert addr */
write_reg16(sohandle, so, 0x0007, 0x0173);
mdelay(40);
/* enable display */
write_reg(sohandle, so, 0x00, 0x22);
mdelay(100);
return 0;
}
| linux-master | arch/sh/boards/mach-migor/lcd_qvga.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas System Solutions Asia Pte. Ltd - Migo-R
*
* Copyright (C) 2008 Magnus Damm
*/
#include <linux/clkdev.h>
#include <linux/dma-map-ops.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/memblock.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/platnand.h>
#include <linux/i2c.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <video/sh_mobile_lcdc.h>
#include <media/drv-intf/renesas-ceu.h>
#include <media/i2c/ov772x.h>
#include <media/i2c/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>
/* Address IRQ Size Bus Description
* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
*/
#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
static phys_addr_t ceu_dma_membase;
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "SMC91C111" ,
.start = 0x10000300,
.end = 0x1000030f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x600), /* IRQ0 */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
.dev = {
.platform_data = &smc91x_info,
},
};
static struct sh_keysc_info sh_keysc_info = {
.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
.scan_timing = 3,
.delay = 5,
.keycodes = {
0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
},
};
static struct resource sh_keysc_resources[] = {
[0] = {
.start = 0x044b0000,
.end = 0x044b000f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh_keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(sh_keysc_resources),
.resource = sh_keysc_resources,
.dev = {
.platform_data = &sh_keysc_info,
},
};
static struct mtd_partition migor_nor_flash_partitions[] =
{
{
.name = "uboot",
.offset = 0,
.size = (1 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = (15 * 1024 * 1024),
},
{
.name = "other",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data migor_nor_flash_data = {
.width = 2,
.parts = migor_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
};
static struct resource migor_nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x03ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device migor_nor_flash_device = {
.name = "physmap-flash",
.resource = migor_nor_flash_resources,
.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
.dev = {
.platform_data = &migor_nor_flash_data,
},
};
static struct mtd_partition migor_nand_flash_partitions[] = {
{
.name = "nanddata1",
.offset = 0x0,
.size = 512 * 1024 * 1024,
},
{
.name = "nanddata2",
.offset = MTDPART_OFS_APPEND,
.size = 512 * 1024 * 1024,
},
};
static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
unsigned int ctrl)
{
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
else if (ctrl & NAND_ALE)
writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
else
writeb(cmd, chip->legacy.IO_ADDR_W);
}
static int migor_nand_flash_ready(struct nand_chip *chip)
{
return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}
static struct platform_nand_data migor_nand_flash_data = {
.chip = {
.nr_chips = 1,
.partitions = migor_nand_flash_partitions,
.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
.chip_delay = 20,
},
.ctrl = {
.dev_ready = migor_nand_flash_ready,
.cmd_ctrl = migor_nand_flash_cmd_ctl,
},
};
static struct resource migor_nand_flash_resources[] = {
[0] = {
.name = "NAND Flash",
.start = 0x18000000,
.end = 0x18ffffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device migor_nand_flash_device = {
.name = "gen_nand",
.resource = migor_nand_flash_resources,
.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
.dev = {
.platform_data = &migor_nand_flash_data,
}
};
static const struct fb_videomode migor_lcd_modes[] = {
{
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
.name = "LB070WV1",
.xres = 800,
.yres = 480,
.left_margin = 64,
.right_margin = 16,
.hsync_len = 120,
.sync = 0,
#elif defined(CONFIG_SH_MIGOR_QVGA)
.name = "PH240320T",
.xres = 320,
.yres = 240,
.left_margin = 0,
.right_margin = 16,
.hsync_len = 8,
.sync = FB_SYNC_HOR_HIGH_ACT,
#endif
.upper_margin = 1,
.lower_margin = 17,
.vsync_len = 2,
},
};
static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB16,
.clock_divider = 2,
.lcd_modes = migor_lcd_modes,
.num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
}
#elif defined(CONFIG_SH_MIGOR_QVGA)
.clock_source = LCDC_CLK_PERIPHERAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = SYS16A,
.clock_divider = 10,
.lcd_modes = migor_lcd_modes,
.num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = {
.width = 49, /* 2.4 inch */
.height = 37,
.setup_sys = migor_lcd_qvga_setup,
},
.sys_bus_cfg = {
.ldmt2r = 0x06000a09,
.ldmt3r = 0x180e3418,
/* set 1s delay to encourage fsync() */
.deferred_io_msec = 1000,
},
}
#endif
};
static struct resource migor_lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000, /* P4-only space */
.end = 0xfe942fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device migor_lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(migor_lcdc_resources),
.resource = migor_lcdc_resources,
.dev = {
.platform_data = &sh_mobile_lcdc_info,
},
};
static struct ceu_platform_data ceu_pdata = {
.num_subdevs = 2,
.subdevs = {
{ /* [0] = ov772x */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 0,
.i2c_address = 0x21,
},
{ /* [1] = tw9910 */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 0,
.i2c_address = 0x45,
},
},
};
static struct resource migor_ceu_resources[] = {
[0] = {
.name = "CEU",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device migor_ceu_device = {
.name = "renesas-ceu",
.id = 0, /* ceu.0 */
.num_resources = ARRAY_SIZE(migor_ceu_resources),
.resource = migor_ceu_resources,
.dev = {
.platform_data = &ceu_pdata,
},
};
/* Powerdown/reset gpios for CEU image sensors */
static struct gpiod_lookup_table ov7725_gpios = {
.dev_id = "0-0021",
.table = {
GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
},
};
static struct gpiod_lookup_table tw9910_gpios = {
.dev_id = "0-0045",
.table = {
GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
},
};
/* Fixed 3.3V regulator to be used by SDHI0 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};
static struct resource sdhi_cn9_resources[] = {
[0] = {
.name = "SDHI",
.start = 0x04ce0000,
.end = 0x04ce00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sh7724_sdhi_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi_cn9_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
.resource = sdhi_cn9_resources,
.dev = {
.platform_data = &sh7724_sdhi_data,
},
};
static struct ov772x_camera_info ov7725_info = {
.flags = 0,
};
static struct tw9910_video_info tw9910_info = {
.buswidth = 8,
.mpout = TW9910_MPO_FIELD,
};
static struct i2c_board_info migor_i2c_devices[] = {
{
I2C_BOARD_INFO("rs5c372b", 0x32),
},
{
I2C_BOARD_INFO("migor_ts", 0x51),
.irq = evt2irq(0x6c0), /* IRQ6 */
},
{
I2C_BOARD_INFO("wm8978", 0x1a),
},
{
I2C_BOARD_INFO("ov772x", 0x21),
.platform_data = &ov7725_info,
},
{
I2C_BOARD_INFO("tw9910", 0x45),
.platform_data = &tw9910_info,
},
};
static struct platform_device *migor_devices[] __initdata = {
&smc91x_eth_device,
&sh_keysc_device,
&migor_lcdc_device,
&migor_nor_flash_device,
&migor_nand_flash_device,
&sdhi_cn9_device,
};
extern char migor_sdram_enter_start;
extern char migor_sdram_enter_end;
extern char migor_sdram_leave_start;
extern char migor_sdram_leave_end;
static int __init migor_devices_setup(void)
{
struct clk *video_clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
&migor_sdram_enter_start,
&migor_sdram_enter_end,
&migor_sdram_leave_start,
&migor_sdram_leave_end);
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* Let D11 LED show STATUS0 */
gpio_request(GPIO_FN_STATUS0, NULL);
/* Lit D12 LED show PDSTATUS */
gpio_request(GPIO_FN_PDSTATUS, NULL);
/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
gpio_request(GPIO_FN_IRQ0, NULL);
__raw_writel(0x00003400, BSC_CS4BCR);
__raw_writel(0x00110080, BSC_CS4WCR);
/* KEYSC */
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYIN1, NULL);
gpio_request(GPIO_FN_KEYIN2, NULL);
gpio_request(GPIO_FN_KEYIN3, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
/* NAND Flash */
gpio_request(GPIO_FN_CS6A_CE2B, NULL);
__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
gpio_request(GPIO_PTA1, NULL);
gpio_direction_input(GPIO_PTA1);
/* SDHI */
gpio_request(GPIO_FN_SDHICD, NULL);
gpio_request(GPIO_FN_SDHIWP, NULL);
gpio_request(GPIO_FN_SDHID3, NULL);
gpio_request(GPIO_FN_SDHID2, NULL);
gpio_request(GPIO_FN_SDHID1, NULL);
gpio_request(GPIO_FN_SDHID0, NULL);
gpio_request(GPIO_FN_SDHICMD, NULL);
gpio_request(GPIO_FN_SDHICLK, NULL);
/* Touch Panel */
gpio_request(GPIO_FN_IRQ6, NULL);
/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDRS, NULL);
gpio_request(GPIO_FN_LCDCS, NULL);
gpio_request(GPIO_FN_LCDRD, NULL);
gpio_request(GPIO_FN_LCDWR, NULL);
gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVEPWC, NULL);
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
#endif
/* CEU */
gpio_request(GPIO_FN_VIO_CLK2, NULL);
gpio_request(GPIO_FN_VIO_VD2, NULL);
gpio_request(GPIO_FN_VIO_HD2, NULL);
gpio_request(GPIO_FN_VIO_FLD, NULL);
gpio_request(GPIO_FN_VIO_CKO, NULL);
gpio_request(GPIO_FN_VIO_D15, NULL);
gpio_request(GPIO_FN_VIO_D14, NULL);
gpio_request(GPIO_FN_VIO_D13, NULL);
gpio_request(GPIO_FN_VIO_D12, NULL);
gpio_request(GPIO_FN_VIO_D11, NULL);
gpio_request(GPIO_FN_VIO_D10, NULL);
gpio_request(GPIO_FN_VIO_D9, NULL);
gpio_request(GPIO_FN_VIO_D8, NULL);
__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
/* SIU: Port B */
gpio_request(GPIO_FN_SIUBOLR, NULL);
gpio_request(GPIO_FN_SIUBOBT, NULL);
gpio_request(GPIO_FN_SIUBISLD, NULL);
gpio_request(GPIO_FN_SIUBOSLD, NULL);
gpio_request(GPIO_FN_SIUMCKB, NULL);
/*
* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
* output. Need only SIUB, set to output for master mode (table 34.2)
*/
__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
/*
* Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
* issues on Panel Board V2.1.
*/
video_clk = clk_get(NULL, "video_clk");
if (!IS_ERR(video_clk)) {
clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
clk_put(video_clk);
}
/* Add a clock alias for ov7725 xclk source. */
clk_add_alias(NULL, "0-0021", "video_clk", NULL);
/* Register GPIOs for video sources. */
gpiod_add_lookup_table(&ov7725_gpios);
gpiod_add_lookup_table(&tw9910_gpios);
i2c_register_board_info(0, migor_i2c_devices,
ARRAY_SIZE(migor_i2c_devices));
/* Initialize CEU platform device separately to map memory first */
device_initialize(&migor_ceu_device.dev);
dma_declare_coherent_memory(&migor_ceu_device.dev,
ceu_dma_membase, ceu_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(&migor_ceu_device);
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
arch_initcall(migor_devices_setup);
/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
/* MD0=1, MD1=1, MD2=0: Clock Mode 3
* MD3=0: 16-bit Area0 Bus Width
* MD5=1: Little Endian
* TSTMD=1, MD8=0: Test Mode Disabled
*/
return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}
/* Reserve a portion of memory for CEU buffers */
static void __init migor_mv_mem_reserve(void)
{
phys_addr_t phys;
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu_dma_membase = phys;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_migor __initmv = {
.mv_name = "Migo-R",
.mv_mode_pins = migor_mode_pins,
.mv_mem_reserve = migor_mv_mem_reserve,
};
| linux-master | arch/sh/boards/mach-migor/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/mach-landisk/irq.c
*
* I-O DATA Device, Inc. LANDISK Support
*
* Copyright (C) 2005-2007 kogiidena
* Copyright (C) 2011 Nobuhiro Iwamatsu
*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach-landisk/mach/iodata_landisk.h>
enum {
UNUSED = 0,
PCI_INTA, /* PCI int A */
PCI_INTB, /* PCI int B */
PCI_INTC, /* PCI int C */
PCI_INTD, /* PCI int D */
ATA, /* ATA */
FATA, /* CF */
POWER, /* Power switch */
BUTTON, /* Button switch */
};
/* Vectors for LANDISK */
static struct intc_vect vectors_landisk[] __initdata = {
INTC_IRQ(PCI_INTA, IRQ_PCIINTA),
INTC_IRQ(PCI_INTB, IRQ_PCIINTB),
INTC_IRQ(PCI_INTC, IRQ_PCIINTC),
INTC_IRQ(PCI_INTD, IRQ_PCIINTD),
INTC_IRQ(ATA, IRQ_ATA),
INTC_IRQ(FATA, IRQ_FATA),
INTC_IRQ(POWER, IRQ_POWER),
INTC_IRQ(BUTTON, IRQ_BUTTON),
};
/* IRLMSK mask register layout for LANDISK */
static struct intc_mask_reg mask_registers_landisk[] __initdata = {
{ PA_IMASK, 0, 8, /* IRLMSK */
{ BUTTON, POWER, FATA, ATA,
PCI_INTD, PCI_INTC, PCI_INTB, PCI_INTA,
}
},
};
static DECLARE_INTC_DESC(intc_desc_landisk, "landisk", vectors_landisk, NULL,
mask_registers_landisk, NULL, NULL);
/*
* Initialize IRQ setting
*/
void __init init_landisk_IRQ(void)
{
register_intc_controller(&intc_desc_landisk);
__raw_writeb(0x00, PA_PWRINT_CLR);
}
| linux-master | arch/sh/boards/mach-landisk/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/landisk/psw.c
*
* push switch support for LANDISK and USL-5P
*
* Copyright (C) 2006-2007 Paul Mundt
* Copyright (C) 2007 kogiidena
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <mach-landisk/mach/iodata_landisk.h>
#include <asm/push-switch.h>
static irqreturn_t psw_irq_handler(int irq, void *arg)
{
struct platform_device *pdev = arg;
struct push_switch *psw = platform_get_drvdata(pdev);
struct push_switch_platform_info *psw_info = pdev->dev.platform_data;
unsigned int sw_value;
int ret = 0;
sw_value = (0x0ff & (~__raw_readb(PA_STATUS)));
/* Nothing to do if there's no state change */
if (psw->state) {
ret = 1;
goto out;
}
/* Figure out who raised it */
if (sw_value & (1 << psw_info->bit)) {
psw->state = 1;
mod_timer(&psw->debounce, jiffies + 50);
ret = 1;
}
out:
/* Clear the switch IRQs */
__raw_writeb(0x00, PA_PWRINT_CLR);
return IRQ_RETVAL(ret);
}
static struct resource psw_power_resources[] = {
[0] = {
.start = IRQ_POWER,
.flags = IORESOURCE_IRQ,
},
};
static struct resource psw_usl5p_resources[] = {
[0] = {
.start = IRQ_BUTTON,
.flags = IORESOURCE_IRQ,
},
};
static struct push_switch_platform_info psw_power_platform_data = {
.name = "psw_power",
.bit = 4,
.irq_flags = IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct push_switch_platform_info psw1_platform_data = {
.name = "psw1",
.bit = 0,
.irq_flags = IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct push_switch_platform_info psw2_platform_data = {
.name = "psw2",
.bit = 2,
.irq_flags = IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct push_switch_platform_info psw3_platform_data = {
.name = "psw3",
.bit = 1,
.irq_flags = IRQF_SHARED,
.irq_handler = psw_irq_handler,
};
static struct platform_device psw_power_switch_device = {
.name = "push-switch",
.id = 0,
.num_resources = ARRAY_SIZE(psw_power_resources),
.resource = psw_power_resources,
.dev = {
.platform_data = &psw_power_platform_data,
},
};
static struct platform_device psw1_switch_device = {
.name = "push-switch",
.id = 1,
.num_resources = ARRAY_SIZE(psw_usl5p_resources),
.resource = psw_usl5p_resources,
.dev = {
.platform_data = &psw1_platform_data,
},
};
static struct platform_device psw2_switch_device = {
.name = "push-switch",
.id = 2,
.num_resources = ARRAY_SIZE(psw_usl5p_resources),
.resource = psw_usl5p_resources,
.dev = {
.platform_data = &psw2_platform_data,
},
};
static struct platform_device psw3_switch_device = {
.name = "push-switch",
.id = 3,
.num_resources = ARRAY_SIZE(psw_usl5p_resources),
.resource = psw_usl5p_resources,
.dev = {
.platform_data = &psw3_platform_data,
},
};
static struct platform_device *psw_devices[] = {
&psw_power_switch_device,
&psw1_switch_device,
&psw2_switch_device,
&psw3_switch_device,
};
static int __init psw_init(void)
{
return platform_add_devices(psw_devices, ARRAY_SIZE(psw_devices));
}
device_initcall(psw_init);
| linux-master | arch/sh/boards/mach-landisk/psw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/landisk/setup.c
*
* I-O DATA Device, Inc. LANDISK Support.
*
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2002 Paul Mundt
* Copylight (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2005-2007 kogiidena
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/pm.h>
#include <linux/mm.h>
#include <asm/machvec.h>
#include <mach-landisk/mach/iodata_landisk.h>
#include <asm/io.h>
static void landisk_power_off(void)
{
__raw_writeb(0x01, PA_SHUTDOWN);
}
static struct resource cf_ide_resources[3];
static struct pata_platform_info pata_info = {
.ioport_shift = 1,
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
.dev = {
.platform_data = &pata_info,
},
};
static struct platform_device rtc_device = {
.name = "rs5c313",
.id = -1,
};
static struct platform_device *landisk_devices[] __initdata = {
&cf_ide_device,
&rtc_device,
};
static int __init landisk_devices_setup(void)
{
pgprot_t prot;
unsigned long paddrbase;
void *cf_ide_base;
/* open I/O area window */
paddrbase = virt_to_phys((void *)PA_AREA5_IO);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
if (!cf_ide_base) {
printk("allocate_cf_area : can't open CF I/O window!\n");
return -ENOMEM;
}
/* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */
cf_ide_resources[0].start = (unsigned long)cf_ide_base + 0x40;
cf_ide_resources[0].end = (unsigned long)cf_ide_base + 0x40 + 0x0f;
cf_ide_resources[0].flags = IORESOURCE_IO;
cf_ide_resources[1].start = (unsigned long)cf_ide_base + 0x2c;
cf_ide_resources[1].end = (unsigned long)cf_ide_base + 0x2c + 0x03;
cf_ide_resources[1].flags = IORESOURCE_IO;
cf_ide_resources[2].start = IRQ_FATA;
cf_ide_resources[2].flags = IORESOURCE_IRQ;
return platform_add_devices(landisk_devices,
ARRAY_SIZE(landisk_devices));
}
device_initcall(landisk_devices_setup);
static void __init landisk_setup(char **cmdline_p)
{
/* I/O port identity mapping */
__set_io_port_base(0);
/* LED ON */
__raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
pm_power_off = landisk_power_off;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_landisk __initmv = {
.mv_name = "LANDISK",
.mv_setup = landisk_setup,
.mv_init_irq = init_landisk_IRQ,
};
| linux-master | arch/sh/boards/mach-landisk/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/landisk/gio.c - driver for landisk
*
* This driver will also support the I-O DATA Device, Inc. LANDISK Board.
* LANDISK and USL-5P Button, LED and GIO driver drive function.
*
* Copylight (C) 2006 kogiidena
* Copylight (C) 2002 Atom Create Engineering Co., Ltd. *
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kdev_t.h>
#include <linux/cdev.h>
#include <linux/fs.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <mach-landisk/mach/gio.h>
#include <mach-landisk/mach/iodata_landisk.h>
#define DEVCOUNT 4
#define GIO_MINOR 2 /* GIO minor no. */
static dev_t dev;
static struct cdev *cdev_p;
static int openCnt;
static int gio_open(struct inode *inode, struct file *filp)
{
int minor = iminor(inode);
int ret = -ENOENT;
preempt_disable();
if (minor < DEVCOUNT) {
if (openCnt > 0) {
ret = -EALREADY;
} else {
openCnt++;
ret = 0;
}
}
preempt_enable();
return ret;
}
static int gio_close(struct inode *inode, struct file *filp)
{
int minor = iminor(inode);
if (minor < DEVCOUNT) {
openCnt--;
}
return 0;
}
static long gio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
unsigned int data;
static unsigned int addr = 0;
if (cmd & 0x01) { /* write */
if (copy_from_user(&data, (int *)arg, sizeof(int))) {
return -EFAULT;
}
}
switch (cmd) {
case GIODRV_IOCSGIOSETADDR: /* address set */
addr = data;
break;
case GIODRV_IOCSGIODATA1: /* write byte */
__raw_writeb((unsigned char)(0x0ff & data), addr);
break;
case GIODRV_IOCSGIODATA2: /* write word */
if (addr & 0x01) {
return -EFAULT;
}
__raw_writew((unsigned short int)(0x0ffff & data), addr);
break;
case GIODRV_IOCSGIODATA4: /* write long */
if (addr & 0x03) {
return -EFAULT;
}
__raw_writel(data, addr);
break;
case GIODRV_IOCGGIODATA1: /* read byte */
data = __raw_readb(addr);
break;
case GIODRV_IOCGGIODATA2: /* read word */
if (addr & 0x01) {
return -EFAULT;
}
data = __raw_readw(addr);
break;
case GIODRV_IOCGGIODATA4: /* read long */
if (addr & 0x03) {
return -EFAULT;
}
data = __raw_readl(addr);
break;
default:
return -EFAULT;
break;
}
if ((cmd & 0x01) == 0) { /* read */
if (copy_to_user((int *)arg, &data, sizeof(int))) {
return -EFAULT;
}
}
return 0;
}
static const struct file_operations gio_fops = {
.owner = THIS_MODULE,
.open = gio_open, /* open */
.release = gio_close, /* release */
.unlocked_ioctl = gio_ioctl,
.llseek = noop_llseek,
};
static int __init gio_init(void)
{
int error;
printk(KERN_INFO "gio: driver initialized\n");
openCnt = 0;
if ((error = alloc_chrdev_region(&dev, 0, DEVCOUNT, "gio")) < 0) {
printk(KERN_ERR
"gio: Couldn't alloc_chrdev_region, error=%d\n",
error);
return 1;
}
cdev_p = cdev_alloc();
cdev_p->ops = &gio_fops;
error = cdev_add(cdev_p, dev, DEVCOUNT);
if (error) {
printk(KERN_ERR
"gio: Couldn't cdev_add, error=%d\n", error);
return 1;
}
return 0;
}
static void __exit gio_exit(void)
{
cdev_del(cdev_p);
unregister_chrdev_region(dev, DEVCOUNT);
}
module_init(gio_init);
module_exit(gio_exit);
MODULE_LICENSE("GPL");
| linux-master | arch/sh/boards/mach-landisk/gio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/superh/microdev/irq.c
*
* Copyright (C) 2003 Sean McGoogan ([email protected])
*
* SuperH SH4-202 MicroDev board support.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <mach/microdev.h>
#define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */
static const struct {
unsigned char fpgaIrq;
unsigned char mapped;
const char *name;
} fpgaIrqTable[NUM_EXTERNAL_IRQS] = {
{ 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */
{ MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */
{ MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */
{ MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */
{ MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */
{ 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */
{ 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */
{ MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */
{ MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */
{ MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */
{ MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */
{ MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */
{ MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */
{ MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */
{ MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */
{ 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */
};
#if (MICRODEV_LINUX_IRQ_KEYBOARD != 1)
# error Inconsistancy in defining the IRQ# for Keyboard!
#endif
#if (MICRODEV_LINUX_IRQ_ETHERNET != 3)
# error Inconsistancy in defining the IRQ# for Ethernet!
#endif
#if (MICRODEV_LINUX_IRQ_USB_HC != 7)
# error Inconsistancy in defining the IRQ# for USB!
#endif
#if (MICRODEV_LINUX_IRQ_MOUSE != 12)
# error Inconsistancy in defining the IRQ# for PS/2 Mouse!
#endif
#if (MICRODEV_LINUX_IRQ_IDE2 != 13)
# error Inconsistancy in defining the IRQ# for secondary IDE!
#endif
#if (MICRODEV_LINUX_IRQ_IDE1 != 14)
# error Inconsistancy in defining the IRQ# for primary IDE!
#endif
static void disable_microdev_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned int fpgaIrq;
if (irq >= NUM_EXTERNAL_IRQS)
return;
if (!fpgaIrqTable[irq].mapped)
return;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
/* disable interrupts on the FPGA INTC register */
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
}
static void enable_microdev_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned long priorityReg, priorities, pri;
unsigned int fpgaIrq;
if (unlikely(irq >= NUM_EXTERNAL_IRQS))
return;
if (unlikely(!fpgaIrqTable[irq].mapped))
return;
pri = 15 - irq;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
/* set priority for the interrupt */
priorities = __raw_readl(priorityReg);
priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
__raw_writel(priorities, priorityReg);
/* enable interrupts on the FPGA INTC register */
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
}
static struct irq_chip microdev_irq_type = {
.name = "MicroDev-IRQ",
.irq_unmask = enable_microdev_irq,
.irq_mask = disable_microdev_irq,
};
/* This function sets the desired irq handler to be a MicroDev type */
static void __init make_microdev_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq);
disable_microdev_irq(irq_get_irq_data(irq));
}
extern void __init init_microdev_irq(void)
{
int i;
/* disable interrupts on the FPGA INTC register */
__raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
make_microdev_irq(i);
}
extern void microdev_print_fpga_intc_status(void)
{
volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG;
volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG;
volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0);
volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8);
volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16);
volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24);
volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG;
volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG;
printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n");
printk("FPGA_INTENB = 0x%08x\n", *intenb);
printk("FPGA_INTDSB = 0x%08x\n", *intdsb);
printk("FPGA_INTSRC = 0x%08x\n", *intsrc);
printk("FPGA_INTREQ = 0x%08x\n", *intreq);
printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
printk("-------------------------------------------------------------------------------\n");
}
| linux-master | arch/sh/boards/mach-microdev/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/superh/microdev/io.c
*
* Copyright (C) 2003 Sean McGoogan ([email protected])
* Copyright (C) 2003, 2004 SuperH, Inc.
* Copyright (C) 2004 Paul Mundt
*
* SuperH SH4-202 MicroDev board support.
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/wait.h>
#include <asm/io.h>
#include <mach/microdev.h>
/*
* we need to have a 'safe' address to re-direct all I/O requests
* that we do not explicitly wish to handle. This safe address
* must have the following properies:
*
* * writes are ignored (no exception)
* * reads are benign (no side-effects)
* * accesses of width 1, 2 and 4-bytes are all valid.
*
* The Processor Version Register (PVR) has these properties.
*/
#define PVR 0xff000030 /* Processor Version Register */
#define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */
#define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */
#define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */
#define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */
#define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */
#define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */
#define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */
#define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */
#define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */
#define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */
#define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */
#define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */
#define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */
#define IO_SERIAL_EXTENT 0x10ul
#define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */
#define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */
#define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */
/*
* map I/O ports to memory-mapped addresses
*/
void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len)
{
unsigned long result;
if ((offset >= IO_LAN91C111_BASE) &&
(offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
/*
* SMSC LAN91C111 Ethernet chip
*/
result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE;
} else if ((offset >= IO_SUPERIO_BASE) &&
(offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* Configuration Registers
*/
result = IO_SUPERIO_PHYS + (offset << 1);
} else if (((offset >= IO_IDE1_BASE) &&
(offset < IO_IDE1_BASE + IO_IDE_EXTENT)) ||
(offset == IO_IDE1_MISC)) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* IDE #1
*/
result = IO_SUPERIO_PHYS + (offset << 1);
} else if (((offset >= IO_IDE2_BASE) &&
(offset < IO_IDE2_BASE + IO_IDE_EXTENT)) ||
(offset == IO_IDE2_MISC)) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* IDE #2
*/
result = IO_SUPERIO_PHYS + (offset << 1);
} else if ((offset >= IO_SERIAL1_BASE) &&
(offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* Serial #1
*/
result = IO_SUPERIO_PHYS + (offset << 1);
} else if ((offset >= IO_SERIAL2_BASE) &&
(offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* Serial #2
*/
result = IO_SUPERIO_PHYS + (offset << 1);
} else if ((offset >= IO_ISP1161_BASE) &&
(offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) {
/*
* Philips USB ISP1161x chip
*/
result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE;
} else {
/*
* safe default.
*/
printk("Warning: unexpected port in %s( offset = 0x%lx )\n",
__func__, offset);
result = PVR;
}
return (void __iomem *)result;
}
| linux-master | arch/sh/boards/mach-microdev/io.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Setup for the SMSC FDC37C93xAPM
*
* Copyright (C) 2003 Sean McGoogan ([email protected])
* Copyright (C) 2003, 2004 SuperH, Inc.
* Copyright (C) 2004, 2005 Paul Mundt
*
* SuperH SH4-202 MicroDev board support.
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach/microdev.h>
#define SMSC_CONFIG_PORT_ADDR (0x3F0)
#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
#define SMSC_ENTER_CONFIG_KEY 0x55
#define SMSC_EXIT_CONFIG_KEY 0xaa
#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
#define SMSC_READ_INDEXED(index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
inb(SMSC_DATA_PORT_ADDR); })
#define SMSC_WRITE_INDEXED(val, index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
outb((val), SMSC_DATA_PORT_ADDR); })
#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
#define SERIAL1_PRIMARY_BASE 0x03f8
#define SERIAL2_PRIMARY_BASE 0x02f8
#define MSB(x) ( (x) >> 8 )
#define LSB(x) ( (x) & 0xff )
/* General-Purpose base address on CPU-board FPGA */
#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
static int __init smsc_superio_setup(void)
{
unsigned char devid, devrev;
/* Initially the chip is in run state */
/* Put it into configuration state */
outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
/* Read device ID info */
devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
if ((devid == 0x30) && (devrev == 0x01))
printk("SMSC FDC37C93xAPM SuperIO device detected\n");
else
return -ENODEV;
/* Select the keyboard device */
SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
/* Select the Serial #1 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
/* Select the Serial #2 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#1 device */
SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#2 device */
SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
/* Select the configuration registers */
SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
/* enable the appropriate GPIO pins for IDE functionality:
* bit[0] In/Out 1==input; 0==output
* bit[1] Polarity 1==invert; 0==no invert
* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
* bit[3:4] Function Select 00==original; 01==Alternate Function #1
*/
SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
/* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;
}
device_initcall(smsc_superio_setup);
| linux-master | arch/sh/boards/mach-microdev/fdc37c93xapm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/superh/microdev/setup.c
*
* Copyright (C) 2003 Sean McGoogan ([email protected])
* Copyright (C) 2003, 2004 SuperH, Inc.
* Copyright (C) 2004, 2005 Paul Mundt
*
* SuperH SH4-202 MicroDev board support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <video/s1d13xxxfb.h>
#include <mach/microdev.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <linux/sizes.h>
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x300,
.end = 0x300 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MICRODEV_LINUX_IRQ_ETHERNET,
.end = MICRODEV_LINUX_IRQ_ETHERNET,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct s1d13xxxfb_regval s1d13806_initregs[] = {
{ S1DREG_MISC, 0x00 },
{ S1DREG_COM_DISP_MODE, 0x00 },
{ S1DREG_GPIO_CNF0, 0x00 },
{ S1DREG_GPIO_CNF1, 0x00 },
{ S1DREG_GPIO_CTL0, 0x00 },
{ S1DREG_GPIO_CTL1, 0x00 },
{ S1DREG_CLK_CNF, 0x02 },
{ S1DREG_LCD_CLK_CNF, 0x01 },
{ S1DREG_CRT_CLK_CNF, 0x03 },
{ S1DREG_MPLUG_CLK_CNF, 0x03 },
{ S1DREG_CPU2MEM_WST_SEL, 0x02 },
{ S1DREG_SDRAM_REF_RATE, 0x03 },
{ S1DREG_SDRAM_TC0, 0x00 },
{ S1DREG_SDRAM_TC1, 0x01 },
{ S1DREG_MEM_CNF, 0x80 },
{ S1DREG_PANEL_TYPE, 0x25 },
{ S1DREG_MOD_RATE, 0x00 },
{ S1DREG_LCD_DISP_HWIDTH, 0x63 },
{ S1DREG_LCD_NDISP_HPER, 0x1e },
{ S1DREG_TFT_FPLINE_START, 0x06 },
{ S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
{ S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
{ S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
{ S1DREG_LCD_NDISP_VPER, 0x00 },
{ S1DREG_TFT_FPFRAME_START, 0x0a },
{ S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
{ S1DREG_LCD_DISP_MODE, 0x03 },
{ S1DREG_LCD_MISC, 0x00 },
{ S1DREG_LCD_DISP_START0, 0x00 },
{ S1DREG_LCD_DISP_START1, 0x00 },
{ S1DREG_LCD_DISP_START2, 0x00 },
{ S1DREG_LCD_MEM_OFF0, 0x90 },
{ S1DREG_LCD_MEM_OFF1, 0x01 },
{ S1DREG_LCD_PIX_PAN, 0x00 },
{ S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
{ S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
{ S1DREG_CRT_DISP_HWIDTH, 0x63 },
{ S1DREG_CRT_NDISP_HPER, 0x1f },
{ S1DREG_CRT_HRTC_START, 0x04 },
{ S1DREG_CRT_HRTC_PWIDTH, 0x8f },
{ S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
{ S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
{ S1DREG_CRT_NDISP_VPER, 0x1b },
{ S1DREG_CRT_VRTC_START, 0x00 },
{ S1DREG_CRT_VRTC_PWIDTH, 0x83 },
{ S1DREG_TV_OUT_CTL, 0x10 },
{ S1DREG_CRT_DISP_MODE, 0x05 },
{ S1DREG_CRT_DISP_START0, 0x00 },
{ S1DREG_CRT_DISP_START1, 0x00 },
{ S1DREG_CRT_DISP_START2, 0x00 },
{ S1DREG_CRT_MEM_OFF0, 0x20 },
{ S1DREG_CRT_MEM_OFF1, 0x03 },
{ S1DREG_CRT_PIX_PAN, 0x00 },
{ S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
{ S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
{ S1DREG_LCD_CUR_CTL, 0x00 },
{ S1DREG_LCD_CUR_START, 0x01 },
{ S1DREG_LCD_CUR_XPOS0, 0x00 },
{ S1DREG_LCD_CUR_XPOS1, 0x00 },
{ S1DREG_LCD_CUR_YPOS0, 0x00 },
{ S1DREG_LCD_CUR_YPOS1, 0x00 },
{ S1DREG_LCD_CUR_BCTL0, 0x00 },
{ S1DREG_LCD_CUR_GCTL0, 0x00 },
{ S1DREG_LCD_CUR_RCTL0, 0x00 },
{ S1DREG_LCD_CUR_BCTL1, 0x1f },
{ S1DREG_LCD_CUR_GCTL1, 0x3f },
{ S1DREG_LCD_CUR_RCTL1, 0x1f },
{ S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
{ S1DREG_CRT_CUR_CTL, 0x00 },
{ S1DREG_CRT_CUR_START, 0x01 },
{ S1DREG_CRT_CUR_XPOS0, 0x00 },
{ S1DREG_CRT_CUR_XPOS1, 0x00 },
{ S1DREG_CRT_CUR_YPOS0, 0x00 },
{ S1DREG_CRT_CUR_YPOS1, 0x00 },
{ S1DREG_CRT_CUR_BCTL0, 0x00 },
{ S1DREG_CRT_CUR_GCTL0, 0x00 },
{ S1DREG_CRT_CUR_RCTL0, 0x00 },
{ S1DREG_CRT_CUR_BCTL1, 0x1f },
{ S1DREG_CRT_CUR_GCTL1, 0x3f },
{ S1DREG_CRT_CUR_RCTL1, 0x1f },
{ S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
{ S1DREG_BBLT_CTL0, 0x00 },
{ S1DREG_BBLT_CTL1, 0x00 },
{ S1DREG_BBLT_CC_EXP, 0x00 },
{ S1DREG_BBLT_OP, 0x00 },
{ S1DREG_BBLT_SRC_START0, 0x00 },
{ S1DREG_BBLT_SRC_START1, 0x00 },
{ S1DREG_BBLT_SRC_START2, 0x00 },
{ S1DREG_BBLT_DST_START0, 0x00 },
{ S1DREG_BBLT_DST_START1, 0x00 },
{ S1DREG_BBLT_DST_START2, 0x00 },
{ S1DREG_BBLT_MEM_OFF0, 0x00 },
{ S1DREG_BBLT_MEM_OFF1, 0x00 },
{ S1DREG_BBLT_WIDTH0, 0x00 },
{ S1DREG_BBLT_WIDTH1, 0x00 },
{ S1DREG_BBLT_HEIGHT0, 0x00 },
{ S1DREG_BBLT_HEIGHT1, 0x00 },
{ S1DREG_BBLT_BGC0, 0x00 },
{ S1DREG_BBLT_BGC1, 0x00 },
{ S1DREG_BBLT_FGC0, 0x00 },
{ S1DREG_BBLT_FGC1, 0x00 },
{ S1DREG_LKUP_MODE, 0x00 },
{ S1DREG_LKUP_ADDR, 0x00 },
{ S1DREG_PS_CNF, 0x10 },
{ S1DREG_PS_STATUS, 0x00 },
{ S1DREG_CPU2MEM_WDOGT, 0x00 },
{ S1DREG_COM_DISP_MODE, 0x02 },
};
static struct s1d13xxxfb_pdata s1d13806_platform_data = {
.initregs = s1d13806_initregs,
.initregssize = ARRAY_SIZE(s1d13806_initregs),
};
static struct resource s1d13806_resources[] = {
[0] = {
.start = 0x07200000,
.end = 0x07200000 + SZ_2M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x07000000,
.end = 0x07000000 + SZ_2M - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device s1d13806_device = {
.name = "s1d13806fb",
.id = -1,
.num_resources = ARRAY_SIZE(s1d13806_resources),
.resource = s1d13806_resources,
.dev = {
.platform_data = &s1d13806_platform_data,
},
};
static struct platform_device *microdev_devices[] __initdata = {
&smc91x_device,
&s1d13806_device,
};
static int __init microdev_devices_setup(void)
{
return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
}
device_initcall(microdev_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_sh4202_microdev __initmv = {
.mv_name = "SH4-202 MicroDev",
.mv_ioport_map = microdev_ioport_map,
.mv_init_irq = init_microdev_irq,
};
| linux-master | arch/sh/boards/mach-microdev/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <[email protected]>
*/
#include <asm/clock.h>
#include <asm/heartbeat.h>
#include <asm/suspend.h>
#include <cpu/sh7724.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/sh_mmcif.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/platform_data/gpio_backlight.h>
#include <linux/platform_data/tsc2007.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/spi/mmc_spi.h>
#include <linux/spi/sh_msiof.h>
#include <linux/spi/spi.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/renesas_usbhs.h>
#include <linux/videodev2.h>
#include <linux/dma-map-ops.h>
#include <media/drv-intf/renesas-ceu.h>
#include <media/i2c/mt9t112.h>
#include <media/i2c/tw9910.h>
#include <sound/sh_fsi.h>
#include <sound/simple_card.h>
#include <video/sh_mobile_lcdc.h>
/*
* Address Interface BusWidth
*-----------------------------------------
* 0x0000_0000 uboot 16bit
* 0x0004_0000 Linux romImage 16bit
* 0x0014_0000 MTD for Linux 16bit
* 0x0400_0000 Internal I/O 16/32bit
* 0x0800_0000 DRAM 32bit
* 0x1800_0000 MFI 16bit
*/
/* SWITCH
*------------------------------
* DS2[1] = FlashROM write protect ON : write protect
* OFF : No write protect
* DS2[2] = RMII / TS, SCIF ON : RMII
* OFF : TS, SCIF3
* DS2[3] = Camera / Video ON : Camera
* OFF : NTSC/PAL (IN)
* DS2[5] = NTSC_OUT Clock ON : On board OSC
* OFF : SH7724 DV_CLK
* DS2[6-7] = MMC / SD ON-OFF : SD
* OFF-ON : MMC
*/
/*
* FSI - DA7210
*
* it needs amixer settings for playing
*
* amixer set 'HeadPhone' 80
* amixer set 'Out Mixer Left DAC Left' on
* amixer set 'Out Mixer Right DAC Right' on
*/
#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
static phys_addr_t ceu0_dma_membase;
static phys_addr_t ceu1_dma_membase;
/* Heartbeat */
static unsigned char led_pos[] = { 0, 1, 2, 3 };
static struct heartbeat_data heartbeat_data = {
.nr_bits = 4,
.bit_pos = led_pos,
};
static struct resource heartbeat_resource = {
.start = 0xA405012C, /* PTG */
.end = 0xA405012E - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* MTD */
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "boot loader",
.offset = 0,
.size = (5 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* force read-only */
}, {
.name = "free-area",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x03ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.resource = nor_flash_resources,
.num_resources = ARRAY_SIZE(nor_flash_resources),
.dev = {
.platform_data = &nor_flash_data,
},
};
/* SH Eth */
#define SH_ETH_ADDR (0xA4600000)
static struct resource sh_eth_resources[] = {
[0] = {
.start = SH_ETH_ADDR,
.end = SH_ETH_ADDR + 0x1FC,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xd60),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct sh_eth_plat_data sh_eth_plat = {
.phy = 0x1f, /* SMSC LAN8700 */
.phy_interface = PHY_INTERFACE_MODE_MII,
.ether_link_active_low = 1
};
static struct platform_device sh_eth_device = {
.name = "sh7724-ether",
.id = 0,
.dev = {
.platform_data = &sh_eth_plat,
},
.num_resources = ARRAY_SIZE(sh_eth_resources),
.resource = sh_eth_resources,
};
/* USB0 host */
static void usb0_port_power(int port, int power)
{
gpio_set_value(GPIO_PTB4, power);
}
static struct r8a66597_platdata usb0_host_data = {
.on_chip = 1,
.port_power = usb0_port_power,
};
static struct resource usb0_host_resources[] = {
[0] = {
.start = 0xa4d80000,
.end = 0xa4d80124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa20),
.end = evt2irq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device usb0_host_device = {
.name = "r8a66597_hcd",
.id = 0,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usb0_host_data,
},
.num_resources = ARRAY_SIZE(usb0_host_resources),
.resource = usb0_host_resources,
};
/* USB1 host/function */
static void usb1_port_power(int port, int power)
{
gpio_set_value(GPIO_PTB5, power);
}
static struct r8a66597_platdata usb1_common_data = {
.on_chip = 1,
.port_power = usb1_port_power,
};
static struct resource usb1_common_resources[] = {
[0] = {
.start = 0xa4d90000,
.end = 0xa4d90124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device usb1_common_device = {
/* .name will be added in arch_setup */
.id = 1,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usb1_common_data,
},
.num_resources = ARRAY_SIZE(usb1_common_resources),
.resource = usb1_common_resources,
};
/*
* USBHS
*/
static int usbhs_get_id(struct platform_device *pdev)
{
return gpio_get_value(GPIO_PTB3);
}
static int usbhs_phy_reset(struct platform_device *pdev)
{
/* enable vbus if HOST */
if (!gpio_get_value(GPIO_PTB3))
gpio_set_value(GPIO_PTB5, 1);
return 0;
}
static struct renesas_usbhs_platform_info usbhs_info = {
.platform_callback = {
.get_id = usbhs_get_id,
.phy_reset = usbhs_phy_reset,
},
.driver_param = {
.buswait_bwait = 4,
.detection_delay = 5,
.d0_tx_id = SHDMA_SLAVE_USB1D0_TX,
.d0_rx_id = SHDMA_SLAVE_USB1D0_RX,
.d1_tx_id = SHDMA_SLAVE_USB1D1_TX,
.d1_rx_id = SHDMA_SLAVE_USB1D1_RX,
},
};
static struct resource usbhs_resources[] = {
[0] = {
.start = 0xa4d90000,
.end = 0xa4d90124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usbhs_device = {
.name = "renesas_usbhs",
.id = 1,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usbhs_info,
},
.num_resources = ARRAY_SIZE(usbhs_resources),
.resource = usbhs_resources,
};
/* LCDC and backlight */
static const struct fb_videomode ecovec_lcd_modes[] = {
{
.name = "Panel",
.xres = 800,
.yres = 480,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 70,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.sync = 0, /* hsync and vsync are active low */
},
};
static const struct fb_videomode ecovec_dvi_modes[] = {
{
.name = "DVI",
.xres = 1280,
.yres = 720,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 40,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.sync = 0, /* hsync and vsync are active low */
},
};
static struct sh_mobile_lcdc_info lcdc_info = {
.ch[0] = {
.interface_type = RGB18,
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000,
.end = 0xfe942fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
},
};
static struct gpiod_lookup_table gpio_backlight_lookup = {
.dev_id = "gpio-backlight.0",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTR1, NULL, GPIO_ACTIVE_HIGH),
{ }
},
};
static struct property_entry gpio_backlight_props[] = {
PROPERTY_ENTRY_BOOL("default-on"),
{ }
};
static struct gpio_backlight_platform_data gpio_backlight_data = {
.dev = &lcdc_device.dev,
};
static const struct platform_device_info gpio_backlight_device_info = {
.name = "gpio-backlight",
.data = &gpio_backlight_data,
.size_data = sizeof(gpio_backlight_data),
.properties = gpio_backlight_props,
};
static struct platform_device *gpio_backlight_device;
/* CEU0 */
static struct ceu_platform_data ceu0_pdata = {
.num_subdevs = 2,
.subdevs = {
{ /* [0] = mt9t112 */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 0,
.i2c_address = 0x3c,
},
{ /* [1] = tw9910 */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 0,
.i2c_address = 0x45,
},
},
};
static struct resource ceu0_resources[] = {
[0] = {
.name = "CEU0",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ceu0_device = {
.name = "renesas-ceu",
.id = 0, /* ceu.0 */
.num_resources = ARRAY_SIZE(ceu0_resources),
.resource = ceu0_resources,
.dev = {
.platform_data = &ceu0_pdata,
},
};
/* CEU1 */
static struct ceu_platform_data ceu1_pdata = {
.num_subdevs = 1,
.subdevs = {
{ /* [0] = mt9t112 */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 1,
.i2c_address = 0x3c,
},
},
};
static struct resource ceu1_resources[] = {
[0] = {
.name = "CEU1",
.start = 0xfe914000,
.end = 0xfe91409f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ceu1_device = {
.name = "renesas-ceu",
.id = 1, /* ceu.1 */
.num_resources = ARRAY_SIZE(ceu1_resources),
.resource = ceu1_resources,
.dev = {
.platform_data = &ceu1_pdata,
},
};
/* Power up/down GPIOs for camera devices and video decoder */
static struct gpiod_lookup_table tw9910_gpios = {
.dev_id = "0-0045",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTU2, "pdn", GPIO_ACTIVE_HIGH),
},
};
static struct gpiod_lookup_table mt9t112_0_gpios = {
.dev_id = "0-003c",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTA3, "standby",
GPIO_ACTIVE_HIGH),
},
};
static struct gpiod_lookup_table mt9t112_1_gpios = {
.dev_id = "1-003c",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTA4, "standby",
GPIO_ACTIVE_HIGH),
},
};
/* I2C device */
static struct tw9910_video_info tw9910_info = {
.buswidth = 8,
.mpout = TW9910_MPO_FIELD,
};
static struct mt9t112_platform_data mt9t112_0_pdata = {
.flags = MT9T112_FLAG_PCLK_RISING_EDGE,
.divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
};
static struct mt9t112_platform_data mt9t112_1_pdata = {
.flags = MT9T112_FLAG_PCLK_RISING_EDGE,
.divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
};
static struct i2c_board_info i2c0_devices[] = {
{
I2C_BOARD_INFO("da7210", 0x1a),
},
{
I2C_BOARD_INFO("tw9910", 0x45),
.platform_data = &tw9910_info,
},
{
/* 1st camera */
I2C_BOARD_INFO("mt9t112", 0x3c),
.platform_data = &mt9t112_0_pdata,
},
};
static struct i2c_board_info i2c1_devices[] = {
{
I2C_BOARD_INFO("r2025sd", 0x32),
},
{
I2C_BOARD_INFO("lis3lv02d", 0x1c),
.irq = evt2irq(0x620),
},
{
/* 2nd camera */
I2C_BOARD_INFO("mt9t112", 0x3c),
.platform_data = &mt9t112_1_pdata,
},
};
/* KEYSC */
static struct sh_keysc_info keysc_info = {
.mode = SH_KEYSC_MODE_1,
.scan_timing = 3,
.delay = 50,
.kycr2_delay = 100,
.keycodes = { KEY_1, 0, 0, 0, 0,
KEY_2, 0, 0, 0, 0,
KEY_3, 0, 0, 0, 0,
KEY_4, 0, 0, 0, 0,
KEY_5, 0, 0, 0, 0,
KEY_6, 0, 0, 0, 0, },
};
static struct resource keysc_resources[] = {
[0] = {
.name = "KEYSC",
.start = 0x044b0000,
.end = 0x044b000f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device keysc_device = {
.name = "sh_keysc",
.id = 0, /* keysc0 clock */
.num_resources = ARRAY_SIZE(keysc_resources),
.resource = keysc_resources,
.dev = {
.platform_data = &keysc_info,
},
};
/* TouchScreen */
#define IRQ0 evt2irq(0x600)
static int ts_get_pendown_state(struct device *dev)
{
int val = 0;
gpio_free(GPIO_FN_INTC_IRQ0);
gpio_request(GPIO_PTZ0, NULL);
gpio_direction_input(GPIO_PTZ0);
val = gpio_get_value(GPIO_PTZ0);
gpio_free(GPIO_PTZ0);
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
return val ? 0 : 1;
}
static int ts_init(void)
{
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
return 0;
}
static struct tsc2007_platform_data tsc2007_info = {
.model = 2007,
.x_plate_ohms = 180,
.get_pendown_state = ts_get_pendown_state,
.init_platform_hw = ts_init,
};
static struct i2c_board_info ts_i2c_clients = {
I2C_BOARD_INFO("tsc2007", 0x48),
.type = "tsc2007",
.platform_data = &tsc2007_info,
.irq = IRQ0,
};
static struct regulator_consumer_supply cn12_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
};
static struct regulator_init_data cn12_power_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(cn12_power_consumers),
.consumer_supplies = cn12_power_consumers,
};
static struct fixed_voltage_config cn12_power_info = {
.supply_name = "CN12 SD/MMC Vdd",
.microvolts = 3300000,
.init_data = &cn12_power_init_data,
};
static struct platform_device cn12_power = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &cn12_power_info,
},
};
static struct gpiod_lookup_table cn12_power_gpiod_table = {
.dev_id = "reg-fixed-voltage.0",
.table = {
/* Offset 7 on port B */
GPIO_LOOKUP("sh7724_pfc", GPIO_PTB7,
NULL, GPIO_ACTIVE_HIGH),
{ },
},
};
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* SDHI0 */
static struct regulator_consumer_supply sdhi0_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};
static struct regulator_init_data sdhi0_power_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdhi0_power_consumers),
.consumer_supplies = sdhi0_power_consumers,
};
static struct fixed_voltage_config sdhi0_power_info = {
.supply_name = "CN11 SD/MMC Vdd",
.microvolts = 3300000,
.init_data = &sdhi0_power_init_data,
};
static struct platform_device sdhi0_power = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &sdhi0_power_info,
},
};
static struct gpiod_lookup_table sdhi0_power_gpiod_table = {
.dev_id = "reg-fixed-voltage.1",
.table = {
/* Offset 6 on port B */
GPIO_LOOKUP("sh7724_pfc", GPIO_PTB6,
NULL, GPIO_ACTIVE_HIGH),
{ },
},
};
static struct gpiod_lookup_table sdhi0_gpio_table = {
.dev_id = "sh_mobile_sdhi.0",
.table = {
/* Card detect */
GPIO_LOOKUP("sh7724_pfc", GPIO_PTY7, "cd", GPIO_ACTIVE_LOW),
{ },
},
};
static struct tmio_mmc_data sdhi0_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
MMC_CAP_NEEDS_POLL,
};
static struct resource sdhi0_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0x04ce0000,
.end = 0x04ce00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi0_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi0_resources),
.resource = sdhi0_resources,
.id = 0,
.dev = {
.platform_data = &sdhi0_info,
},
};
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SDHI1 */
static struct tmio_mmc_data sdhi1_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
.capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
MMC_CAP_NEEDS_POLL,
};
static struct gpiod_lookup_table sdhi1_gpio_table = {
.dev_id = "sh_mobile_sdhi.1",
.table = {
/* Card detect */
GPIO_LOOKUP("sh7724_pfc", GPIO_PTW7, "cd", GPIO_ACTIVE_LOW),
{ },
},
};
static struct resource sdhi1_resources[] = {
[0] = {
.name = "SDHI1",
.start = 0x04cf0000,
.end = 0x04cf00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi1_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi1_resources),
.resource = sdhi1_resources,
.id = 1,
.dev = {
.platform_data = &sdhi1_info,
},
};
#endif /* CONFIG_MMC_SH_MMCIF */
#else
/* MMC SPI */
static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
{
gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
}
static struct mmc_spi_platform_data mmc_spi_info = {
.caps = MMC_CAP_NEEDS_POLL,
.caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
.setpower = mmc_spi_setpower,
};
static struct gpiod_lookup_table mmc_spi_gpio_table = {
.dev_id = "mmc_spi.0", /* device "mmc_spi" @ CS0 */
.table = {
/* Card detect */
GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY7, NULL, 0,
GPIO_ACTIVE_LOW),
/* Write protect */
GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY6, NULL, 1,
GPIO_ACTIVE_HIGH),
{ },
},
};
static struct spi_board_info spi_bus[] = {
{
.modalias = "mmc_spi",
.platform_data = &mmc_spi_info,
.max_speed_hz = 5000000,
.mode = SPI_MODE_0,
},
};
/* MSIOF0 */
static struct sh_msiof_spi_info msiof0_data = {
.num_chipselect = 1,
};
static struct resource msiof0_resources[] = {
[0] = {
.name = "MSIOF0",
.start = 0xa4c40000,
.end = 0xa4c40063,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xc80),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device msiof0_device = {
.name = "spi_sh_msiof",
.id = 0, /* MSIOF0 */
.dev = {
.platform_data = &msiof0_data,
},
.num_resources = ARRAY_SIZE(msiof0_resources),
.resource = msiof0_resources,
};
static struct gpiod_lookup_table msiof_gpio_table = {
.dev_id = "spi_sh_msiof.0",
.table = {
GPIO_LOOKUP("sh7724_pfc", GPIO_PTM4, "cs", GPIO_ACTIVE_HIGH),
{ },
},
};
#endif
/* FSI */
static struct resource fsi_resources[] = {
[0] = {
.name = "FSI",
.start = 0xFE3C0000,
.end = 0xFE3C021d,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xf80),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device fsi_device = {
.name = "sh_fsi",
.id = 0,
.num_resources = ARRAY_SIZE(fsi_resources),
.resource = fsi_resources,
};
static struct asoc_simple_card_info fsi_da7210_info = {
.name = "DA7210",
.card = "FSIB-DA7210",
.codec = "da7210.0-001a",
.platform = "sh_fsi.0",
.daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBP_CFP,
.cpu_dai = {
.name = "fsib-dai",
},
.codec_dai = {
.name = "da7210-hifi",
},
};
static struct platform_device fsi_da7210_device = {
.name = "asoc-simple-card",
.dev = {
.platform_data = &fsi_da7210_info,
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &fsi_da7210_device.dev.coherent_dma_mask,
},
};
/* IrDA */
static struct resource irda_resources[] = {
[0] = {
.name = "IrDA",
.start = 0xA45D0000,
.end = 0xA45D0049,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x480),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device irda_device = {
.name = "sh_sir",
.num_resources = ARRAY_SIZE(irda_resources),
.resource = irda_resources,
};
#include <media/i2c/ak881x.h>
#include <media/drv-intf/sh_vou.h>
static struct ak881x_pdata ak881x_pdata = {
.flags = AK881X_IF_MODE_SLAVE,
};
static struct i2c_board_info ak8813 = {
I2C_BOARD_INFO("ak8813", 0x20),
.platform_data = &ak881x_pdata,
};
static struct sh_vou_pdata sh_vou_pdata = {
.bus_fmt = SH_VOU_BUS_8BIT,
.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
.board_info = &ak8813,
.i2c_adap = 0,
};
static struct resource sh_vou_resources[] = {
[0] = {
.start = 0xfe960000,
.end = 0xfe962043,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x8e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device vou_device = {
.name = "sh-vou",
.id = -1,
.num_resources = ARRAY_SIZE(sh_vou_resources),
.resource = sh_vou_resources,
.dev = {
.platform_data = &sh_vou_pdata,
},
};
#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SH_MMCIF */
static struct resource sh_mmcif_resources[] = {
[0] = {
.name = "SH_MMCIF",
.start = 0xA4CA0000,
.end = 0xA4CA00FF,
.flags = IORESOURCE_MEM,
},
[1] = {
/* MMC2I */
.start = evt2irq(0x5a0),
.flags = IORESOURCE_IRQ,
},
[2] = {
/* MMC3I */
.start = evt2irq(0x5c0),
.flags = IORESOURCE_IRQ,
},
};
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0, /* SH7724: Max Pclk/2 */
.caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_8_BIT_DATA |
MMC_CAP_NEEDS_POLL,
.ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
};
static struct platform_device sh_mmcif_device = {
.name = "sh_mmcif",
.id = 0,
.dev = {
.platform_data = &sh_mmcif_plat,
},
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
.resource = sh_mmcif_resources,
};
#endif
static struct platform_device *ecovec_ceu_devices[] __initdata = {
&ceu0_device,
&ceu1_device,
};
static struct platform_device *ecovec_devices[] __initdata = {
&heartbeat_device,
&nor_flash_device,
&sh_eth_device,
&usb0_host_device,
&usb1_common_device,
&usbhs_device,
&lcdc_device,
&keysc_device,
&cn12_power,
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
&sdhi0_power,
&sdhi0_device,
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
&sdhi1_device,
#endif
#else
&msiof0_device,
#endif
&fsi_device,
&fsi_da7210_device,
&irda_device,
&vou_device,
#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
&sh_mmcif_device,
#endif
};
#ifdef CONFIG_I2C
#define EEPROM_ADDR 0x50
static u8 mac_read(struct i2c_adapter *a, u8 command)
{
struct i2c_msg msg[2];
u8 buf;
int ret;
msg[0].addr = EEPROM_ADDR;
msg[0].flags = 0;
msg[0].len = 1;
msg[0].buf = &command;
msg[1].addr = EEPROM_ADDR;
msg[1].flags = I2C_M_RD;
msg[1].len = 1;
msg[1].buf = &buf;
ret = i2c_transfer(a, msg, 2);
if (ret < 0) {
printk(KERN_ERR "error %d\n", ret);
buf = 0xff;
}
return buf;
}
static void __init sh_eth_init(struct sh_eth_plat_data *pd)
{
struct i2c_adapter *a = i2c_get_adapter(1);
int i;
if (!a) {
pr_err("can not get I2C 1\n");
return;
}
/* read MAC address from EEPROM */
for (i = 0; i < sizeof(pd->mac_addr); i++) {
pd->mac_addr[i] = mac_read(a, 0x10 + i);
msleep(10);
}
i2c_put_adapter(a);
}
#else
static void __init sh_eth_init(struct sh_eth_plat_data *pd)
{
pr_err("unable to read sh_eth MAC address\n");
}
#endif
#define PORT_HIZA 0xA4050158
#define IODRIVEA 0xA405018A
extern char ecovec24_sdram_enter_start;
extern char ecovec24_sdram_enter_end;
extern char ecovec24_sdram_leave_start;
extern char ecovec24_sdram_leave_end;
static int __init arch_setup(void)
{
struct clk *clk;
bool cn12_enabled = false;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&ecovec24_sdram_enter_start,
&ecovec24_sdram_enter_end,
&ecovec24_sdram_leave_start,
&ecovec24_sdram_leave_end);
/* enable STATUS0, STATUS2 and PDSTATUS */
gpio_request(GPIO_FN_STATUS0, NULL);
gpio_request(GPIO_FN_STATUS2, NULL);
gpio_request(GPIO_FN_PDSTATUS, NULL);
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIF0_TXD, NULL);
gpio_request(GPIO_FN_SCIF0_RXD, NULL);
/* enable debug LED */
gpio_request(GPIO_PTG0, NULL);
gpio_request(GPIO_PTG1, NULL);
gpio_request(GPIO_PTG2, NULL);
gpio_request(GPIO_PTG3, NULL);
gpio_direction_output(GPIO_PTG0, 0);
gpio_direction_output(GPIO_PTG1, 0);
gpio_direction_output(GPIO_PTG2, 0);
gpio_direction_output(GPIO_PTG3, 0);
__raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
/* enable SH-Eth */
gpio_request(GPIO_PTA1, NULL);
gpio_direction_output(GPIO_PTA1, 1);
mdelay(20);
gpio_request(GPIO_FN_RMII_RXD0, NULL);
gpio_request(GPIO_FN_RMII_RXD1, NULL);
gpio_request(GPIO_FN_RMII_TXD0, NULL);
gpio_request(GPIO_FN_RMII_TXD1, NULL);
gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
gpio_request(GPIO_FN_RMII_TX_EN, NULL);
gpio_request(GPIO_FN_RMII_RX_ER, NULL);
gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
gpio_request(GPIO_FN_MDIO, NULL);
gpio_request(GPIO_FN_MDC, NULL);
gpio_request(GPIO_FN_LNKSTA, NULL);
/* enable USB */
__raw_writew(0x0000, 0xA4D80000);
__raw_writew(0x0000, 0xA4D90000);
gpio_request(GPIO_PTB3, NULL);
gpio_request(GPIO_PTB4, NULL);
gpio_request(GPIO_PTB5, NULL);
gpio_direction_input(GPIO_PTB3);
gpio_direction_output(GPIO_PTB4, 0);
gpio_direction_output(GPIO_PTB5, 0);
__raw_writew(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa4050192);
if (gpio_get_value(GPIO_PTB3)) {
printk(KERN_INFO "USB1 function is selected\n");
usb1_common_device.name = "r8a66597_udc";
} else {
printk(KERN_INFO "USB1 host is selected\n");
usb1_common_device.name = "r8a66597_hcd";
}
/* enable LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
gpio_request(GPIO_PTE6, NULL);
gpio_request(GPIO_PTU1, NULL);
gpio_request(GPIO_PTA2, NULL);
gpio_direction_input(GPIO_PTE6);
gpio_direction_output(GPIO_PTU1, 0);
gpio_direction_output(GPIO_PTA2, 0);
/* I/O buffer drive ability is high */
__raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
lcdc_info.ch[0].clock_divider = 1;
lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
/* No backlight */
gpio_backlight_data.fbdev = NULL;
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
} else {
/* Panel */
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
lcdc_info.ch[0].clock_divider = 2;
lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
/* FIXME
*
* LCDDON control is needed for Panel,
* but current sh_mobile_lcdc driver doesn't control it.
* It is temporary correspondence
*/
gpio_request(GPIO_PTF4, NULL);
gpio_direction_output(GPIO_PTF4, 1);
/* enable TouchScreen */
i2c_register_board_info(0, &ts_i2c_clients, 1);
irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
}
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
gpio_request(GPIO_FN_VIO0_D14, NULL);
gpio_request(GPIO_FN_VIO0_D13, NULL);
gpio_request(GPIO_FN_VIO0_D12, NULL);
gpio_request(GPIO_FN_VIO0_D11, NULL);
gpio_request(GPIO_FN_VIO0_D10, NULL);
gpio_request(GPIO_FN_VIO0_D9, NULL);
gpio_request(GPIO_FN_VIO0_D8, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
/* enable CEU1 */
gpio_request(GPIO_FN_VIO1_D7, NULL);
gpio_request(GPIO_FN_VIO1_D6, NULL);
gpio_request(GPIO_FN_VIO1_D5, NULL);
gpio_request(GPIO_FN_VIO1_D4, NULL);
gpio_request(GPIO_FN_VIO1_D3, NULL);
gpio_request(GPIO_FN_VIO1_D2, NULL);
gpio_request(GPIO_FN_VIO1_D1, NULL);
gpio_request(GPIO_FN_VIO1_D0, NULL);
gpio_request(GPIO_FN_VIO1_FLD, NULL);
gpio_request(GPIO_FN_VIO1_HD, NULL);
gpio_request(GPIO_FN_VIO1_VD, NULL);
gpio_request(GPIO_FN_VIO1_CLK, NULL);
/* enable KEYSC */
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYIN0, NULL);
/* enable user debug switch */
gpio_request(GPIO_PTR0, NULL);
gpio_request(GPIO_PTR4, NULL);
gpio_request(GPIO_PTR5, NULL);
gpio_request(GPIO_PTR6, NULL);
gpio_direction_input(GPIO_PTR0);
gpio_direction_input(GPIO_PTR4);
gpio_direction_input(GPIO_PTR5);
gpio_direction_input(GPIO_PTR6);
/* SD-card slot CN11 */
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
gpio_request(GPIO_FN_SDHI0WP, NULL);
gpio_request(GPIO_FN_SDHI0CMD, NULL);
gpio_request(GPIO_FN_SDHI0CLK, NULL);
gpio_request(GPIO_FN_SDHI0D3, NULL);
gpio_request(GPIO_FN_SDHI0D2, NULL);
gpio_request(GPIO_FN_SDHI0D1, NULL);
gpio_request(GPIO_FN_SDHI0D0, NULL);
#else
/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
gpiod_add_lookup_table(&mmc_spi_gpio_table);
gpiod_add_lookup_table(&msiof_gpio_table);
spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
#endif
/* MMC/SD-card slot CN12 */
#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
gpio_request(GPIO_FN_MMC_D7, NULL);
gpio_request(GPIO_FN_MMC_D6, NULL);
gpio_request(GPIO_FN_MMC_D5, NULL);
gpio_request(GPIO_FN_MMC_D4, NULL);
gpio_request(GPIO_FN_MMC_D3, NULL);
gpio_request(GPIO_FN_MMC_D2, NULL);
gpio_request(GPIO_FN_MMC_D1, NULL);
gpio_request(GPIO_FN_MMC_D0, NULL);
gpio_request(GPIO_FN_MMC_CLK, NULL);
gpio_request(GPIO_FN_MMC_CMD, NULL);
cn12_enabled = true;
#elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
gpio_request(GPIO_FN_SDHI1WP, NULL);
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
gpio_request(GPIO_FN_SDHI1D3, NULL);
gpio_request(GPIO_FN_SDHI1D2, NULL);
gpio_request(GPIO_FN_SDHI1D1, NULL);
gpio_request(GPIO_FN_SDHI1D0, NULL);
cn12_enabled = true;
#endif
if (cn12_enabled)
/* I/O buffer drive ability is high for CN12 */
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
IODRIVEA);
/* enable FSI */
gpio_request(GPIO_FN_FSIMCKB, NULL);
gpio_request(GPIO_FN_FSIIBSD, NULL);
gpio_request(GPIO_FN_FSIOBSD, NULL);
gpio_request(GPIO_FN_FSIIBBCK, NULL);
gpio_request(GPIO_FN_FSIIBLRCK, NULL);
gpio_request(GPIO_FN_FSIOBBCK, NULL);
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
if (!IS_ERR(clk)) {
/* 48kHz dummy clock was used to make sure 1/1 divide */
clk_set_rate(&sh7724_fsimckb_clk, 48000);
clk_set_parent(clk, &sh7724_fsimckb_clk);
clk_set_rate(clk, 48000);
clk_put(clk);
}
gpio_request(GPIO_PTU0, NULL);
gpio_direction_output(GPIO_PTU0, 0);
mdelay(20);
/* enable motion sensor */
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_direction_input(GPIO_FN_INTC_IRQ1);
/* set VPU clock to 166 MHz */
clk = clk_get(NULL, "vpu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 166000000));
clk_put(clk);
}
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
gpio_request(GPIO_PTU5, NULL);
gpio_direction_output(GPIO_PTU5, 0);
/* Register gpio lookup tables for cameras and video decoder */
gpiod_add_lookup_table(&tw9910_gpios);
gpiod_add_lookup_table(&mt9t112_0_gpios);
gpiod_add_lookup_table(&mt9t112_1_gpios);
/* enable I2C device */
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));
i2c_register_board_info(1, i2c1_devices,
ARRAY_SIZE(i2c1_devices));
#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
/* VOU */
gpio_request(GPIO_FN_DV_D15, NULL);
gpio_request(GPIO_FN_DV_D14, NULL);
gpio_request(GPIO_FN_DV_D13, NULL);
gpio_request(GPIO_FN_DV_D12, NULL);
gpio_request(GPIO_FN_DV_D11, NULL);
gpio_request(GPIO_FN_DV_D10, NULL);
gpio_request(GPIO_FN_DV_D9, NULL);
gpio_request(GPIO_FN_DV_D8, NULL);
gpio_request(GPIO_FN_DV_CLKI, NULL);
gpio_request(GPIO_FN_DV_CLK, NULL);
gpio_request(GPIO_FN_DV_VSYNC, NULL);
gpio_request(GPIO_FN_DV_HSYNC, NULL);
/* AK8813 power / reset sequence */
gpio_request(GPIO_PTG4, NULL);
gpio_request(GPIO_PTU3, NULL);
/* Reset */
gpio_direction_output(GPIO_PTG4, 0);
/* Power down */
gpio_direction_output(GPIO_PTU3, 1);
udelay(10);
/* Power up, reset */
gpio_set_value(GPIO_PTU3, 0);
udelay(10);
/* Remove reset */
gpio_set_value(GPIO_PTG4, 1);
#endif
/* Initialize CEU platform devices separately to map memory first */
device_initialize(&ecovec_ceu_devices[0]->dev);
dma_declare_coherent_memory(&ecovec_ceu_devices[0]->dev,
ceu0_dma_membase, ceu0_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(ecovec_ceu_devices[0]);
device_initialize(&ecovec_ceu_devices[1]->dev);
dma_declare_coherent_memory(&ecovec_ceu_devices[1]->dev,
ceu1_dma_membase, ceu1_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(ecovec_ceu_devices[1]);
gpiod_add_lookup_table(&cn12_power_gpiod_table);
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
gpiod_add_lookup_table(&sdhi0_power_gpiod_table);
gpiod_add_lookup_table(&sdhi0_gpio_table);
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
gpiod_add_lookup_table(&sdhi1_gpio_table);
#endif
#endif
gpiod_add_lookup_table(&gpio_backlight_lookup);
gpio_backlight_device = platform_device_register_full(
&gpio_backlight_device_info);
if (IS_ERR(gpio_backlight_device))
return PTR_ERR(gpio_backlight_device);
return platform_add_devices(ecovec_devices,
ARRAY_SIZE(ecovec_devices));
}
arch_initcall(arch_setup);
static int __init devices_setup(void)
{
sh_eth_init(&sh_eth_plat);
return 0;
}
device_initcall(devices_setup);
/* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
static void __init ecovec_mv_mem_reserve(void)
{
phys_addr_t phys;
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU0 memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu0_dma_membase = phys;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU1 memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu1_dma_membase = phys;
}
static struct sh_machine_vector mv_ecovec __initmv = {
.mv_name = "R0P7724 (EcoVec)",
.mv_mem_reserve = ecovec_mv_mem_reserve,
};
| linux-master | arch/sh/boards/mach-ecovec24/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/hp6xx/setup.c
*
* Copyright (C) 2002 Andriy Skulysh
* Copyright (C) 2007 Kristoffer Ericson <[email protected]>
*
* Setup code for HP620/HP660/HP680/HP690 (internal peripherials only)
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/sh_intc.h>
#include <sound/sh_dac_audio.h>
#include <asm/hd64461.h>
#include <asm/io.h>
#include <mach/hp6xx.h>
#include <cpu/dac.h>
#define SCPCR 0xa4000116
#define SCPDR 0xa4000136
/* CF Slot */
static struct resource cf_ide_resources[] = {
[0] = {
.start = 0x15000000 + 0x1f0,
.end = 0x15000000 + 0x1f0 + 0x08 - 0x01,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x15000000 + 0x1fe,
.end = 0x15000000 + 0x1fe + 0x01,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = evt2irq(0xba0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct platform_device jornadakbd_device = {
.name = "jornada680_kbd",
.id = -1,
};
static void dac_audio_start(struct dac_audio_pdata *pdata)
{
u16 v;
u8 v8;
/* HP Jornada 680/690 speaker on */
v = inw(HD64461_GPADR);
v &= ~HD64461_GPADR_SPEAKER;
outw(v, HD64461_GPADR);
/* HP Palmtop 620lx/660lx speaker on */
v8 = inb(PKDR);
v8 &= ~PKDR_SPEAKER;
outb(v8, PKDR);
sh_dac_enable(pdata->channel);
}
static void dac_audio_stop(struct dac_audio_pdata *pdata)
{
u16 v;
u8 v8;
/* HP Jornada 680/690 speaker off */
v = inw(HD64461_GPADR);
v |= HD64461_GPADR_SPEAKER;
outw(v, HD64461_GPADR);
/* HP Palmtop 620lx/660lx speaker off */
v8 = inb(PKDR);
v8 |= PKDR_SPEAKER;
outb(v8, PKDR);
sh_dac_output(0, pdata->channel);
sh_dac_disable(pdata->channel);
}
static struct dac_audio_pdata dac_audio_platform_data = {
.buffer_size = 64000,
.channel = 1,
.start = dac_audio_start,
.stop = dac_audio_stop,
};
static struct platform_device dac_audio_device = {
.name = "dac_audio",
.id = -1,
.dev = {
.platform_data = &dac_audio_platform_data,
}
};
static struct platform_device *hp6xx_devices[] __initdata = {
&cf_ide_device,
&jornadakbd_device,
&dac_audio_device,
};
static void __init hp6xx_init_irq(void)
{
/* Gets touchscreen and powerbutton IRQ working */
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static int __init hp6xx_devices_setup(void)
{
return platform_add_devices(hp6xx_devices, ARRAY_SIZE(hp6xx_devices));
}
static void __init hp6xx_setup(char **cmdline_p)
{
u8 v8;
u16 v;
v = inw(HD64461_STBCR);
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST |
HD64461_STBCR_SAFEST | HD64461_STBCR_SPC0ST |
HD64461_STBCR_SMIAST | HD64461_STBCR_SAFECKE_OST|
HD64461_STBCR_SAFECKE_IST;
#ifndef CONFIG_HD64461_ENABLER
v |= HD64461_STBCR_SPC1ST;
#endif
outw(v, HD64461_STBCR);
v = inw(HD64461_GPADR);
v |= HD64461_GPADR_SPEAKER | HD64461_GPADR_PCMCIA0;
outw(v, HD64461_GPADR);
outw(HD64461_PCCGCR_VCC0 | HD64461_PCCSCR_VCC1, HD64461_PCC0GCR);
#ifndef CONFIG_HD64461_ENABLER
outw(HD64461_PCCGCR_VCC0 | HD64461_PCCSCR_VCC1, HD64461_PCC1GCR);
#endif
sh_dac_output(0, DAC_SPEAKER_VOLUME);
sh_dac_disable(DAC_SPEAKER_VOLUME);
v8 = __raw_readb(DACR);
v8 &= ~DACR_DAE;
__raw_writeb(v8,DACR);
v8 = __raw_readb(SCPDR);
v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
v8 &= ~SCPDR_TS_SCAN_ENABLE;
__raw_writeb(v8, SCPDR);
v = __raw_readw(SCPCR);
v &= ~SCPCR_TS_MASK;
v |= SCPCR_TS_ENABLE;
__raw_writew(v, SCPCR);
}
device_initcall(hp6xx_devices_setup);
static struct sh_machine_vector mv_hp6xx __initmv = {
.mv_name = "hp6xx",
.mv_setup = hp6xx_setup,
/* Enable IRQ0 -> IRQ3 in IRQ_MODE */
.mv_init_irq = hp6xx_init_irq,
};
| linux-master | arch/sh/boards/mach-hp6xx/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* hp6x0 Power Management Routines
*
* Copyright (c) 2006 Andriy Skulysh <[email protected]>
*/
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <asm/io.h>
#include <asm/hd64461.h>
#include <asm/bl_bit.h>
#include <mach/hp6xx.h>
#include <cpu/dac.h>
#include <asm/freq.h>
#include <asm/watchdog.h>
#define INTR_OFFSET 0x600
#define STBCR 0xffffff82
#define STBCR2 0xffffff88
#define STBCR_STBY 0x80
#define STBCR_MSTP2 0x04
#define MCR 0xffffff68
#define RTCNT 0xffffff70
#define MCR_RMODE 2
#define MCR_RFSH 4
extern u8 wakeup_start;
extern u8 wakeup_end;
static void pm_enter(void)
{
u8 stbcr, csr;
u16 frqcr, mcr;
u32 vbr_new, vbr_old;
set_bl_bit();
/* set wdt */
csr = sh_wdt_read_csr();
csr &= ~WTCSR_TME;
csr |= WTCSR_CKS_4096;
sh_wdt_write_csr(csr);
csr = sh_wdt_read_csr();
sh_wdt_write_cnt(0);
/* disable PLL1 */
frqcr = __raw_readw(FRQCR);
frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
__raw_writew(frqcr, FRQCR);
/* enable standby */
stbcr = __raw_readb(STBCR);
__raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
/* set self-refresh */
mcr = __raw_readw(MCR);
__raw_writew(mcr & ~MCR_RFSH, MCR);
/* set interrupt handler */
asm volatile("stc vbr, %0" : "=r" (vbr_old));
vbr_new = get_zeroed_page(GFP_ATOMIC);
udelay(50);
memcpy((void*)(vbr_new + INTR_OFFSET),
&wakeup_start, &wakeup_end - &wakeup_start);
asm volatile("ldc %0, vbr" : : "r" (vbr_new));
__raw_writew(0, RTCNT);
__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
cpu_sleep();
asm volatile("ldc %0, vbr" : : "r" (vbr_old));
free_page(vbr_new);
/* enable PLL1 */
frqcr = __raw_readw(FRQCR);
frqcr |= FRQCR_PSTBY;
__raw_writew(frqcr, FRQCR);
udelay(50);
frqcr |= FRQCR_PLLEN;
__raw_writew(frqcr, FRQCR);
__raw_writeb(stbcr, STBCR);
clear_bl_bit();
}
static int hp6x0_pm_enter(suspend_state_t state)
{
u8 stbcr, stbcr2;
#ifdef CONFIG_HD64461_ENABLER
u8 scr;
u16 hd64461_stbcr;
#endif
#ifdef CONFIG_HD64461_ENABLER
outb(0, HD64461_PCC1CSCIER);
scr = inb(HD64461_PCC1SCR);
scr |= HD64461_PCCSCR_VCC1;
outb(scr, HD64461_PCC1SCR);
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr |= HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
#endif
__raw_writeb(0x1f, DACR);
stbcr = __raw_readb(STBCR);
__raw_writeb(0x01, STBCR);
stbcr2 = __raw_readb(STBCR2);
__raw_writeb(0x7f , STBCR2);
outw(0xf07f, HD64461_SCPUCR);
pm_enter();
outw(0, HD64461_SCPUCR);
__raw_writeb(stbcr, STBCR);
__raw_writeb(stbcr2, STBCR2);
#ifdef CONFIG_HD64461_ENABLER
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
outb(0x4c, HD64461_PCC1CSCIER);
outb(0x00, HD64461_PCC1CSCR);
#endif
return 0;
}
static const struct platform_suspend_ops hp6x0_pm_ops = {
.enter = hp6x0_pm_enter,
.valid = suspend_valid_only_mem,
};
static int __init hp6x0_pm_init(void)
{
suspend_set_ops(&hp6x0_pm_ops);
return 0;
}
late_initcall(hp6x0_pm_init);
| linux-master | arch/sh/boards/mach-hp6xx/pm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* bios-less APM driver for hp680
*
* Copyright 2005 (c) Andriy Skulysh <[email protected]>
* Copyright 2008 (c) Kristoffer Ericson <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/apm-emulation.h>
#include <linux/io.h>
#include <asm/adc.h>
#include <mach/hp6xx.h>
/* percentage values */
#define APM_CRITICAL 10
#define APM_LOW 30
/* resonably sane values */
#define HP680_BATTERY_MAX 898
#define HP680_BATTERY_MIN 486
#define HP680_BATTERY_AC_ON 1023
#define MODNAME "hp6x0_apm"
#define PGDR 0xa400012c
static void hp6x0_apm_get_power_status(struct apm_power_info *info)
{
int battery, backup, charging, percentage;
u8 pgdr;
battery = adc_single(ADC_CHANNEL_BATTERY);
backup = adc_single(ADC_CHANNEL_BACKUP);
charging = adc_single(ADC_CHANNEL_CHARGE);
percentage = 100 * (battery - HP680_BATTERY_MIN) /
(HP680_BATTERY_MAX - HP680_BATTERY_MIN);
/* % of full battery */
info->battery_life = percentage;
/* We want our estimates in minutes */
info->units = 0;
/* Extremely(!!) rough estimate, we will replace this with a datalist later on */
info->time = (2 * battery);
info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
APM_AC_ONLINE : APM_AC_OFFLINE;
pgdr = __raw_readb(PGDR);
if (pgdr & PGDR_MAIN_BATTERY_OUT) {
info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
info->battery_flag = 0x80;
} else if (charging < 8) {
info->battery_status = APM_BATTERY_STATUS_CHARGING;
info->battery_flag = 0x08;
info->ac_line_status = 0x01;
} else if (percentage <= APM_CRITICAL) {
info->battery_status = APM_BATTERY_STATUS_CRITICAL;
info->battery_flag = 0x04;
} else if (percentage <= APM_LOW) {
info->battery_status = APM_BATTERY_STATUS_LOW;
info->battery_flag = 0x02;
} else {
info->battery_status = APM_BATTERY_STATUS_HIGH;
info->battery_flag = 0x01;
}
}
static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev)
{
if (!APM_DISABLED)
apm_queue_event(APM_USER_SUSPEND);
return IRQ_HANDLED;
}
static int __init hp6x0_apm_init(void)
{
int ret;
ret = request_irq(HP680_BTN_IRQ, hp6x0_apm_interrupt,
0, MODNAME, NULL);
if (unlikely(ret < 0)) {
printk(KERN_ERR MODNAME ": IRQ %d request failed\n",
HP680_BTN_IRQ);
return ret;
}
apm_get_power_status = hp6x0_apm_get_power_status;
return ret;
}
static void __exit hp6x0_apm_exit(void)
{
free_irq(HP680_BTN_IRQ, 0);
}
module_init(hp6x0_apm_init);
module_exit(hp6x0_apm_exit);
MODULE_AUTHOR("Adriy Skulysh");
MODULE_DESCRIPTION("hp6xx Advanced Power Management");
MODULE_LICENSE("GPL");
| linux-master | arch/sh/boards/mach-hp6xx/hp6xx_apm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas - AP-325RXA
* (Compatible with Algo System ., LTD. - AP-320A)
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Author : Yusuke Goda <[email protected]>
*/
#include <asm/clock.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <cpu/sh7723.h>
#include <linux/dma-map-ops.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_intc.h>
#include <linux/smsc911x.h>
#include <linux/videodev2.h>
#include <media/drv-intf/renesas-ceu.h>
#include <media/i2c/ov772x.h>
#include <video/sh_mobile_lcdc.h>
#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
static phys_addr_t ceu_dma_membase;
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_32BIT,
};
static struct resource smsc9118_resources[] = {
[0] = {
.start = 0xb6080000,
.end = 0xb60fffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x660),
.end = evt2irq(0x660),
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device smsc9118_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc9118_resources),
.resource = smsc9118_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
/*
* AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
* If this area erased, this board can not boot.
*/
static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
{
.name = "uboot",
.offset = 0,
.size = (1 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* Read-only */
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = (2 * 1024 * 1024),
}, {
.name = "free-area0",
.offset = MTDPART_OFS_APPEND,
.size = ((7 * 1024 * 1024) + (512 * 1024)),
}, {
.name = "CPLD-Data",
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE, /* Read-only */
.size = (1024 * 128 * 2),
}, {
.name = "free-area1",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data ap325rxa_nor_flash_data = {
.width = 2,
.parts = ap325rxa_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
};
static struct resource ap325rxa_nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x00ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device ap325rxa_nor_flash_device = {
.name = "physmap-flash",
.resource = ap325rxa_nor_flash_resources,
.num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
.dev = {
.platform_data = &ap325rxa_nor_flash_data,
},
};
static struct mtd_partition nand_partition_info[] = {
{
.name = "nand_data",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
static struct resource nand_flash_resources[] = {
[0] = {
.start = 0xa4530000,
.end = 0xa45300ff,
.flags = IORESOURCE_MEM,
}
};
static struct sh_flctl_platform_data nand_flash_data = {
.parts = nand_partition_info,
.nr_parts = ARRAY_SIZE(nand_partition_info),
.flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
.has_hwecc = 1,
};
static struct platform_device nand_flash_device = {
.name = "sh_flctl",
.resource = nand_flash_resources,
.num_resources = ARRAY_SIZE(nand_flash_resources),
.dev = {
.platform_data = &nand_flash_data,
},
};
#define FPGA_LCDREG 0xB4100180
#define FPGA_BKLREG 0xB4100212
#define FPGA_LCDREG_VAL 0x0018
#define PORT_MSELCRB 0xA4050182
#define PORT_HIZCRC 0xA405015C
#define PORT_DRVCRA 0xA405018A
#define PORT_DRVCRB 0xA405018C
static int ap320_wvga_set_brightness(int brightness)
{
if (brightness) {
gpio_set_value(GPIO_PTS3, 0);
__raw_writew(0x100, FPGA_BKLREG);
} else {
__raw_writew(0, FPGA_BKLREG);
gpio_set_value(GPIO_PTS3, 1);
}
return 0;
}
static void ap320_wvga_power_on(void)
{
msleep(100);
/* ASD AP-320/325 LCD ON */
__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
}
static void ap320_wvga_power_off(void)
{
/* ASD AP-320/325 LCD OFF */
__raw_writew(0, FPGA_LCDREG);
}
static const struct fb_videomode ap325rxa_lcdc_modes[] = {
{
.name = "LB070WV1",
.xres = 800,
.yres = 480,
.left_margin = 32,
.right_margin = 160,
.hsync_len = 8,
.upper_margin = 63,
.lower_margin = 80,
.vsync_len = 1,
.sync = 0, /* hsync and vsync are active low */
},
};
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB18,
.clock_divider = 1,
.lcd_modes = ap325rxa_lcdc_modes,
.num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
.panel_cfg = {
.width = 152, /* 7.0 inch */
.height = 91,
.display_on = ap320_wvga_power_on,
.display_off = ap320_wvga_power_off,
},
.bl_info = {
.name = "sh_mobile_lcdc_bl",
.max_brightness = 1,
.set_brightness = ap320_wvga_set_brightness,
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000, /* P4-only space */
.end = 0xfe942fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
},
};
/* Powerdown/reset gpios for CEU image sensors */
static struct gpiod_lookup_table ov7725_gpios = {
.dev_id = "0-0021",
.table = {
GPIO_LOOKUP("sh7723_pfc", GPIO_PTZ5, "reset", GPIO_ACTIVE_LOW),
},
};
static struct ceu_platform_data ceu0_pdata = {
.num_subdevs = 1,
.subdevs = {
{ /* [0] = ov7725 */
.flags = 0,
.bus_width = 8,
.bus_shift = 0,
.i2c_adapter_id = 0,
.i2c_address = 0x21,
},
},
};
static struct resource ceu_resources[] = {
[0] = {
.name = "CEU",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ap325rxa_ceu_device = {
.name = "renesas-ceu",
.id = 0, /* "ceu.0" clock */
.num_resources = ARRAY_SIZE(ceu_resources),
.resource = ceu_resources,
.dev = {
.platform_data = &ceu0_pdata,
},
};
/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
};
static struct resource sdhi0_cn3_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0x04ce0000,
.end = 0x04ce00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sdhi0_cn3_data = {
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi0_cn3_device = {
.name = "sh_mobile_sdhi",
.id = 0, /* "sdhi0" clock */
.num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
.resource = sdhi0_cn3_resources,
.dev = {
.platform_data = &sdhi0_cn3_data,
},
};
static struct resource sdhi1_cn7_resources[] = {
[0] = {
.name = "SDHI1",
.start = 0x04cf0000,
.end = 0x04cf00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sdhi1_cn7_data = {
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi1_cn7_device = {
.name = "sh_mobile_sdhi",
.id = 1, /* "sdhi1" clock */
.num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
.resource = sdhi1_cn7_resources,
.dev = {
.platform_data = &sdhi1_cn7_data,
},
};
static struct ov772x_camera_info ov7725_info = {
.flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
};
static struct i2c_board_info ap325rxa_i2c_devices[] __initdata = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
{
I2C_BOARD_INFO("ov772x", 0x21),
.platform_data = &ov7725_info,
},
};
static struct platform_device *ap325rxa_devices[] __initdata = {
&smsc9118_device,
&ap325rxa_nor_flash_device,
&lcdc_device,
&nand_flash_device,
&sdhi0_cn3_device,
&sdhi1_cn7_device,
};
extern char ap325rxa_sdram_enter_start;
extern char ap325rxa_sdram_enter_end;
extern char ap325rxa_sdram_leave_start;
extern char ap325rxa_sdram_leave_end;
static int __init ap325rxa_devices_setup(void)
{
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
&ap325rxa_sdram_enter_start,
&ap325rxa_sdram_enter_end,
&ap325rxa_sdram_leave_start,
&ap325rxa_sdram_leave_end);
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
/* LD3 and LD4 LEDs */
gpio_request(GPIO_PTX5, NULL); /* RUN */
gpio_direction_output(GPIO_PTX5, 1);
gpiod_export(gpio_to_desc(GPIO_PTX5), 0);
gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
gpio_direction_output(GPIO_PTX4, 0);
gpiod_export(gpio_to_desc(GPIO_PTX4), 0);
/* SW1 input */
gpio_request(GPIO_PTF7, NULL); /* MODE */
gpio_direction_input(GPIO_PTF7);
gpiod_export(gpio_to_desc(GPIO_PTF7), 0);
/* LCDC */
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVEPWC, NULL);
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
/* LCD backlight */
gpio_request(GPIO_PTS3, NULL);
gpio_direction_output(GPIO_PTS3, 1);
/* CEU */
gpio_request(GPIO_FN_VIO_CLK2, NULL);
gpio_request(GPIO_FN_VIO_VD2, NULL);
gpio_request(GPIO_FN_VIO_HD2, NULL);
gpio_request(GPIO_FN_VIO_FLD, NULL);
gpio_request(GPIO_FN_VIO_CKO, NULL);
gpio_request(GPIO_FN_VIO_D15, NULL);
gpio_request(GPIO_FN_VIO_D14, NULL);
gpio_request(GPIO_FN_VIO_D13, NULL);
gpio_request(GPIO_FN_VIO_D12, NULL);
gpio_request(GPIO_FN_VIO_D11, NULL);
gpio_request(GPIO_FN_VIO_D10, NULL);
gpio_request(GPIO_FN_VIO_D9, NULL);
gpio_request(GPIO_FN_VIO_D8, NULL);
gpio_request(GPIO_PTZ7, NULL);
gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
gpio_request(GPIO_PTZ6, NULL);
gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
gpio_request(GPIO_PTZ5, NULL);
gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
gpio_request(GPIO_PTZ4, NULL);
gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
/* FLCTL */
gpio_request(GPIO_FN_FCE, NULL);
gpio_request(GPIO_FN_NAF7, NULL);
gpio_request(GPIO_FN_NAF6, NULL);
gpio_request(GPIO_FN_NAF5, NULL);
gpio_request(GPIO_FN_NAF4, NULL);
gpio_request(GPIO_FN_NAF3, NULL);
gpio_request(GPIO_FN_NAF2, NULL);
gpio_request(GPIO_FN_NAF1, NULL);
gpio_request(GPIO_FN_NAF0, NULL);
gpio_request(GPIO_FN_FCDE, NULL);
gpio_request(GPIO_FN_FOE, NULL);
gpio_request(GPIO_FN_FSC, NULL);
gpio_request(GPIO_FN_FWE, NULL);
gpio_request(GPIO_FN_FRB, NULL);
__raw_writew(0, PORT_HIZCRC);
__raw_writew(0xFFFF, PORT_DRVCRA);
__raw_writew(0xFFFF, PORT_DRVCRB);
/* SDHI0 - CN3 - SD CARD */
gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
/* SDHI1 - CN7 - MICRO SD CARD */
gpio_request(GPIO_FN_SDHI1CD, NULL);
gpio_request(GPIO_FN_SDHI1D3, NULL);
gpio_request(GPIO_FN_SDHI1D2, NULL);
gpio_request(GPIO_FN_SDHI1D1, NULL);
gpio_request(GPIO_FN_SDHI1D0, NULL);
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
/* Add a clock alias for ov7725 xclk source. */
clk_add_alias(NULL, "0-0021", "video_clk", NULL);
/* Register RSTB gpio for ov7725 camera sensor. */
gpiod_add_lookup_table(&ov7725_gpios);
i2c_register_board_info(0, ap325rxa_i2c_devices,
ARRAY_SIZE(ap325rxa_i2c_devices));
/* Initialize CEU platform device separately to map memory first */
device_initialize(&ap325rxa_ceu_device.dev);
dma_declare_coherent_memory(&ap325rxa_ceu_device.dev,
ceu_dma_membase, ceu_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(&ap325rxa_ceu_device);
return platform_add_devices(ap325rxa_devices,
ARRAY_SIZE(ap325rxa_devices));
}
arch_initcall(ap325rxa_devices_setup);
/* Return the board specific boot mode pin configuration */
static int ap325rxa_mode_pins(void)
{
/* MD0=0, MD1=0, MD2=0: Clock Mode 0
* MD3=0: 16-bit Area0 Bus Width
* MD5=1: Little Endian
* TSTMD=1, MD8=1: Test Mode Disabled
*/
return MODE_PIN5 | MODE_PIN8;
}
/* Reserve a portion of memory for CEU buffers */
static void __init ap325rxa_mv_mem_reserve(void)
{
phys_addr_t phys;
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu_dma_membase = phys;
}
static struct sh_machine_vector mv_ap325rxa __initmv = {
.mv_name = "AP-325RXA",
.mv_mode_pins = ap325rxa_mode_pins,
.mv_mem_reserve = ap325rxa_mv_mem_reserve,
};
| linux-master | arch/sh/boards/mach-ap325rxa/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/se/7619/setup.c
*
* Copyright (C) 2006 Yoshinori Sato
*
* Hitachi SH7619 SolutionEngine Support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/machvec.h>
static int se7619_mode_pins(void)
{
return MODE_PIN2 | MODE_PIN0;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_mode_pins = se7619_mode_pins,
};
| linux-master | arch/sh/boards/mach-se/board-se7619.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7724/irq.c
*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <[email protected]>
*
* Based on linux/arch/sh/boards/se/7722/irq.c
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7724 Support.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/export.h>
#include <linux/topology.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach-se/mach/se7724.h>
struct fpga_irq {
unsigned long sraddr;
unsigned long mraddr;
unsigned short mask;
unsigned int base;
};
static unsigned int fpga2irq(unsigned int irq)
{
if (irq >= IRQ0_BASE &&
irq <= IRQ0_END)
return IRQ0_IRQ;
else if (irq >= IRQ1_BASE &&
irq <= IRQ1_END)
return IRQ1_IRQ;
else
return IRQ2_IRQ;
}
static struct fpga_irq get_fpga_irq(unsigned int irq)
{
struct fpga_irq set;
switch (irq) {
case IRQ0_IRQ:
set.sraddr = IRQ0_SR;
set.mraddr = IRQ0_MR;
set.mask = IRQ0_MASK;
set.base = IRQ0_BASE;
break;
case IRQ1_IRQ:
set.sraddr = IRQ1_SR;
set.mraddr = IRQ1_MR;
set.mask = IRQ1_MASK;
set.base = IRQ1_BASE;
break;
default:
set.sraddr = IRQ2_SR;
set.mraddr = IRQ2_MR;
set.mask = IRQ2_MASK;
set.base = IRQ2_BASE;
break;
}
return set;
}
static void disable_se7724_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
__raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
}
static void enable_se7724_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
unsigned int bit = irq - set.base;
__raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
}
static struct irq_chip se7724_irq_chip __read_mostly = {
.name = "SE7724-FPGA",
.irq_mask = disable_se7724_irq,
.irq_unmask = enable_se7724_irq,
};
static void se7724_irq_demux(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct fpga_irq set = get_fpga_irq(irq);
unsigned short intv = __raw_readw(set.sraddr);
unsigned int ext_irq = set.base;
intv &= set.mask;
for (; intv; intv >>= 1, ext_irq++) {
if (!(intv & 1))
continue;
generic_handle_irq(ext_irq);
}
}
/*
* Initialize IRQ setting
*/
void __init init_se7724_IRQ(void)
{
int irq_base, i;
__raw_writew(0xffff, IRQ0_MR); /* mask all */
__raw_writew(0xffff, IRQ1_MR); /* mask all */
__raw_writew(0xffff, IRQ2_MR); /* mask all */
__raw_writew(0x0000, IRQ0_SR); /* clear irq */
__raw_writew(0x0000, IRQ1_SR); /* clear irq */
__raw_writew(0x0000, IRQ2_SR); /* clear irq */
__raw_writew(0x002a, IRQ_MODE); /* set irq type */
irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
SE7724_FPGA_IRQ_NR, numa_node_id());
if (IS_ERR_VALUE(irq_base)) {
pr_err("%s: failed hooking irqs for FPGA\n", __func__);
return;
}
for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip,
handle_level_irq, "level");
irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux);
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux);
irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
}
| linux-master | arch/sh/boards/mach-se/7724/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7724/setup.c
*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <[email protected]>
*/
#include <asm/clock.h>
#include <asm/heartbeat.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <cpu/sh7724.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/smc91x.h>
#include <linux/usb/r8a66597.h>
#include <linux/videodev2.h>
#include <linux/dma-map-ops.h>
#include <mach-se/mach/se7724.h>
#include <media/drv-intf/renesas-ceu.h>
#include <sound/sh_fsi.h>
#include <sound/simple_card.h>
#include <video/sh_mobile_lcdc.h>
#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
static phys_addr_t ceu0_dma_membase;
static phys_addr_t ceu1_dma_membase;
/*
* SWx 1234 5678
* ------------------------------------
* SW31 : 1001 1100 : default
* SW32 : 0111 1111 : use on board flash
*
* SW41 : abxx xxxx -> a = 0 : Analog monitor
* 1 : Digital monitor
* b = 0 : VGA
* 1 : 720p
*/
/*
* about 720p
*
* When you use 1280 x 720 lcdc output,
* you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
* and change SW41 to use 720p
*/
/*
* about sound
*
* This setup.c supports FSI slave mode.
* Please change J20, J21, J22 pin to 1-2 connection.
*/
/* Heartbeat */
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* LAN91C111 */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "SMC91C111" ,
.start = 0x1a300300,
.end = 0x1a30030f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ0_SMC,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
.dev = {
.platform_data = &smc91x_info,
},
};
/* MTD */
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "uboot",
.offset = 0,
.size = (1 * 1024 * 1024),
.mask_flags = MTD_WRITEABLE, /* Read-only */
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = (2 * 1024 * 1024),
}, {
.name = "free-area",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x01ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.resource = nor_flash_resources,
.num_resources = ARRAY_SIZE(nor_flash_resources),
.dev = {
.platform_data = &nor_flash_data,
},
};
/* LCDC */
static const struct fb_videomode lcdc_720p_modes[] = {
{
.name = "LB070WV1",
.sync = 0, /* hsync and vsync are active low */
.xres = 1280,
.yres = 720,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 40,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
},
};
static const struct fb_videomode lcdc_vga_modes[] = {
{
.name = "LB070WV1",
.sync = 0, /* hsync and vsync are active low */
.xres = 640,
.yres = 480,
.left_margin = 105,
.right_margin = 50,
.hsync_len = 96,
.upper_margin = 33,
.lower_margin = 10,
.vsync_len = 2,
},
};
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.clock_divider = 1,
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000,
.end = 0xfe942fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xf40),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
},
};
/* CEU0 */
static struct ceu_platform_data ceu0_pdata = {
.num_subdevs = 0,
};
static struct resource ceu0_resources[] = {
[0] = {
.name = "CEU0",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ceu0_device = {
.name = "renesas-ceu",
.id = 0, /* "ceu.0" clock */
.num_resources = ARRAY_SIZE(ceu0_resources),
.resource = ceu0_resources,
.dev = {
.platform_data = &ceu0_pdata,
},
};
/* CEU1 */
static struct ceu_platform_data ceu1_pdata = {
.num_subdevs = 0,
};
static struct resource ceu1_resources[] = {
[0] = {
.name = "CEU1",
.start = 0xfe914000,
.end = 0xfe91409f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x9e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device ceu1_device = {
.name = "renesas-ceu",
.id = 1, /* "ceu.1" clock */
.num_resources = ARRAY_SIZE(ceu1_resources),
.resource = ceu1_resources,
.dev = {
.platform_data = &ceu1_pdata,
},
};
/* FSI */
/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
static struct resource fsi_resources[] = {
[0] = {
.name = "FSI",
.start = 0xFE3C0000,
.end = 0xFE3C021d,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xf80),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device fsi_device = {
.name = "sh_fsi",
.id = 0,
.num_resources = ARRAY_SIZE(fsi_resources),
.resource = fsi_resources,
};
static struct asoc_simple_card_info fsi_ak4642_info = {
.name = "AK4642",
.card = "FSIA-AK4642",
.codec = "ak4642-codec.0-0012",
.platform = "sh_fsi.0",
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBP_CFP,
.cpu_dai = {
.name = "fsia-dai",
},
.codec_dai = {
.name = "ak4642-hifi",
.sysclk = 11289600,
},
};
static struct platform_device fsi_ak4642_device = {
.name = "asoc-simple-card",
.dev = {
.platform_data = &fsi_ak4642_info,
},
};
/* KEYSC in SoC (Needs SW33-2 set to ON) */
static struct sh_keysc_info keysc_info = {
.mode = SH_KEYSC_MODE_1,
.scan_timing = 3,
.delay = 50,
.keycodes = {
KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
},
};
static struct resource keysc_resources[] = {
[0] = {
.name = "KEYSC",
.start = 0x044b0000,
.end = 0x044b000f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(keysc_resources),
.resource = keysc_resources,
.dev = {
.platform_data = &keysc_info,
},
};
/* SH Eth */
static struct resource sh_eth_resources[] = {
[0] = {
.start = SH_ETH_ADDR,
.end = SH_ETH_ADDR + 0x1FC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xd60),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct sh_eth_plat_data sh_eth_plat = {
.phy = 0x1f, /* SMSC LAN8187 */
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct platform_device sh_eth_device = {
.name = "sh7724-ether",
.id = 0,
.dev = {
.platform_data = &sh_eth_plat,
},
.num_resources = ARRAY_SIZE(sh_eth_resources),
.resource = sh_eth_resources,
};
static struct r8a66597_platdata sh7724_usb0_host_data = {
.on_chip = 1,
};
static struct resource sh7724_usb0_host_resources[] = {
[0] = {
.start = 0xa4d80000,
.end = 0xa4d80124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa20),
.end = evt2irq(0xa20),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device sh7724_usb0_host_device = {
.name = "r8a66597_hcd",
.id = 0,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &sh7724_usb0_host_data,
},
.num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
.resource = sh7724_usb0_host_resources,
};
static struct r8a66597_platdata sh7724_usb1_gadget_data = {
.on_chip = 1,
};
static struct resource sh7724_usb1_gadget_resources[] = {
[0] = {
.start = 0xa4d90000,
.end = 0xa4d90123,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xa40),
.end = evt2irq(0xa40),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device sh7724_usb1_gadget_device = {
.name = "r8a66597_udc",
.id = 1, /* USB1 */
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &sh7724_usb1_gadget_data,
},
.num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
.resource = sh7724_usb1_gadget_resources,
};
/* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
};
static struct resource sdhi0_cn7_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0x04ce0000,
.end = 0x04ce00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xe80),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sh7724_sdhi0_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi0_cn7_device = {
.name = "sh_mobile_sdhi",
.id = 0,
.num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
.resource = sdhi0_cn7_resources,
.dev = {
.platform_data = &sh7724_sdhi0_data,
},
};
static struct resource sdhi1_cn8_resources[] = {
[0] = {
.name = "SDHI1",
.start = 0x04cf0000,
.end = 0x04cf00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x4e0),
.flags = IORESOURCE_IRQ,
},
};
static struct tmio_mmc_data sh7724_sdhi1_data = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
.capabilities = MMC_CAP_SDIO_IRQ,
};
static struct platform_device sdhi1_cn8_device = {
.name = "sh_mobile_sdhi",
.id = 1,
.num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
.resource = sdhi1_cn8_resources,
.dev = {
.platform_data = &sh7724_sdhi1_data,
},
};
/* IrDA */
static struct resource irda_resources[] = {
[0] = {
.name = "IrDA",
.start = 0xA45D0000,
.end = 0xA45D0049,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x480),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device irda_device = {
.name = "sh_sir",
.num_resources = ARRAY_SIZE(irda_resources),
.resource = irda_resources,
};
#include <media/i2c/ak881x.h>
#include <media/drv-intf/sh_vou.h>
static struct ak881x_pdata ak881x_pdata = {
.flags = AK881X_IF_MODE_SLAVE,
};
static struct i2c_board_info ak8813 = {
/* With open J18 jumper address is 0x21 */
I2C_BOARD_INFO("ak8813", 0x20),
.platform_data = &ak881x_pdata,
};
static struct sh_vou_pdata sh_vou_pdata = {
.bus_fmt = SH_VOU_BUS_8BIT,
.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
.board_info = &ak8813,
.i2c_adap = 0,
};
static struct resource sh_vou_resources[] = {
[0] = {
.start = 0xfe960000,
.end = 0xfe962043,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x8e0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device vou_device = {
.name = "sh-vou",
.id = -1,
.num_resources = ARRAY_SIZE(sh_vou_resources),
.resource = sh_vou_resources,
.dev = {
.platform_data = &sh_vou_pdata,
},
};
static struct platform_device *ms7724se_ceu_devices[] __initdata = {
&ceu0_device,
&ceu1_device,
};
static struct platform_device *ms7724se_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&lcdc_device,
&nor_flash_device,
&keysc_device,
&sh_eth_device,
&sh7724_usb0_host_device,
&sh7724_usb1_gadget_device,
&fsi_device,
&fsi_ak4642_device,
&sdhi0_cn7_device,
&sdhi1_cn8_device,
&irda_device,
&vou_device,
};
/* I2C device */
static struct i2c_board_info i2c0_devices[] = {
{
I2C_BOARD_INFO("ak4642", 0x12),
},
};
#define EEPROM_OP 0xBA206000
#define EEPROM_ADR 0xBA206004
#define EEPROM_DATA 0xBA20600C
#define EEPROM_STAT 0xBA206010
#define EEPROM_STRT 0xBA206014
static int __init sh_eth_is_eeprom_ready(void)
{
int t = 10000;
while (t--) {
if (!__raw_readw(EEPROM_STAT))
return 1;
udelay(1);
}
printk(KERN_ERR "ms7724se can not access to eeprom\n");
return 0;
}
static void __init sh_eth_init(void)
{
int i;
u16 mac;
/* check EEPROM status */
if (!sh_eth_is_eeprom_ready())
return;
/* read MAC addr from EEPROM */
for (i = 0 ; i < 3 ; i++) {
__raw_writew(0x0, EEPROM_OP); /* read */
__raw_writew(i*2, EEPROM_ADR);
__raw_writew(0x1, EEPROM_STRT);
if (!sh_eth_is_eeprom_ready())
return;
mac = __raw_readw(EEPROM_DATA);
sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
}
}
#define SW4140 0xBA201000
#define FPGA_OUT 0xBA200400
#define PORT_HIZA 0xA4050158
#define PORT_MSELCRB 0xA4050182
#define SW41_A 0x0100
#define SW41_B 0x0200
#define SW41_C 0x0400
#define SW41_D 0x0800
#define SW41_E 0x1000
#define SW41_F 0x2000
#define SW41_G 0x4000
#define SW41_H 0x8000
extern char ms7724se_sdram_enter_start;
extern char ms7724se_sdram_enter_end;
extern char ms7724se_sdram_leave_start;
extern char ms7724se_sdram_leave_end;
static int __init arch_setup(void)
{
/* enable I2C device */
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));
return 0;
}
arch_initcall(arch_setup);
static int __init devices_setup(void)
{
u16 sw = __raw_readw(SW4140); /* select camera, monitor */
struct clk *clk;
u16 fpga_out;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&ms7724se_sdram_enter_start,
&ms7724se_sdram_enter_end,
&ms7724se_sdram_leave_start,
&ms7724se_sdram_leave_end);
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* Reset Release */
fpga_out = __raw_readw(FPGA_OUT);
/* bit4: NTSC_PDN, bit5: NTSC_RESET */
fpga_out &= ~((1 << 1) | /* LAN */
(1 << 4) | /* AK8813 PDN */
(1 << 5) | /* AK8813 RESET */
(1 << 6) | /* VIDEO DAC */
(1 << 7) | /* AK4643 */
(1 << 8) | /* IrDA */
(1 << 12) | /* USB0 */
(1 << 14)); /* RMII */
__raw_writew(fpga_out | (1 << 4), FPGA_OUT);
udelay(10);
/* AK8813 RESET */
__raw_writew(fpga_out | (1 << 5), FPGA_OUT);
udelay(10);
__raw_writew(fpga_out, FPGA_OUT);
/* turn on USB clocks, use external clock */
__raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
/* Let LED9 show STATUS2 */
gpio_request(GPIO_FN_STATUS2, NULL);
/* Lit LED10 show STATUS0 */
gpio_request(GPIO_FN_STATUS0, NULL);
/* Lit LED11 show PDSTATUS */
gpio_request(GPIO_FN_PDSTATUS, NULL);
/* enable USB0 port */
__raw_writew(0x0600, 0xa40501d4);
/* enable USB1 port */
__raw_writew(0x0600, 0xa4050192);
/* enable IRQ 0,1,2 */
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_request(GPIO_FN_INTC_IRQ2, NULL);
/* enable SCIFA3 */
gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
/* enable LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDVEPWC, NULL);
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDRD, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
gpio_request(GPIO_FN_VIO0_D14, NULL);
gpio_request(GPIO_FN_VIO0_D13, NULL);
gpio_request(GPIO_FN_VIO0_D12, NULL);
gpio_request(GPIO_FN_VIO0_D11, NULL);
gpio_request(GPIO_FN_VIO0_D10, NULL);
gpio_request(GPIO_FN_VIO0_D9, NULL);
gpio_request(GPIO_FN_VIO0_D8, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
/* enable CEU1 */
gpio_request(GPIO_FN_VIO1_D7, NULL);
gpio_request(GPIO_FN_VIO1_D6, NULL);
gpio_request(GPIO_FN_VIO1_D5, NULL);
gpio_request(GPIO_FN_VIO1_D4, NULL);
gpio_request(GPIO_FN_VIO1_D3, NULL);
gpio_request(GPIO_FN_VIO1_D2, NULL);
gpio_request(GPIO_FN_VIO1_D1, NULL);
gpio_request(GPIO_FN_VIO1_D0, NULL);
gpio_request(GPIO_FN_VIO1_FLD, NULL);
gpio_request(GPIO_FN_VIO1_HD, NULL);
gpio_request(GPIO_FN_VIO1_VD, NULL);
gpio_request(GPIO_FN_VIO1_CLK, NULL);
/* KEYSC */
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
gpio_request(GPIO_FN_KEYIN3, NULL);
gpio_request(GPIO_FN_KEYIN2, NULL);
gpio_request(GPIO_FN_KEYIN1, NULL);
gpio_request(GPIO_FN_KEYIN0, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
/* enable FSI */
gpio_request(GPIO_FN_FSIMCKA, NULL);
gpio_request(GPIO_FN_FSIIASD, NULL);
gpio_request(GPIO_FN_FSIOASD, NULL);
gpio_request(GPIO_FN_FSIIABCK, NULL);
gpio_request(GPIO_FN_FSIIALRCK, NULL);
gpio_request(GPIO_FN_FSIOABCK, NULL);
gpio_request(GPIO_FN_FSIOALRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI A */
clk = clk_get(NULL, "fsia_clk");
if (!IS_ERR(clk)) {
/* 48kHz dummy clock was used to make sure 1/1 divide */
clk_set_rate(&sh7724_fsimcka_clk, 48000);
clk_set_parent(clk, &sh7724_fsimcka_clk);
clk_set_rate(clk, 48000);
clk_put(clk);
}
/* SDHI0 connected to cn7 */
gpio_request(GPIO_FN_SDHI0CD, NULL);
gpio_request(GPIO_FN_SDHI0WP, NULL);
gpio_request(GPIO_FN_SDHI0D3, NULL);
gpio_request(GPIO_FN_SDHI0D2, NULL);
gpio_request(GPIO_FN_SDHI0D1, NULL);
gpio_request(GPIO_FN_SDHI0D0, NULL);
gpio_request(GPIO_FN_SDHI0CMD, NULL);
gpio_request(GPIO_FN_SDHI0CLK, NULL);
/* SDHI1 connected to cn8 */
gpio_request(GPIO_FN_SDHI1CD, NULL);
gpio_request(GPIO_FN_SDHI1WP, NULL);
gpio_request(GPIO_FN_SDHI1D3, NULL);
gpio_request(GPIO_FN_SDHI1D2, NULL);
gpio_request(GPIO_FN_SDHI1D1, NULL);
gpio_request(GPIO_FN_SDHI1D0, NULL);
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
/*
* enable SH-Eth
*
* please remove J33 pin from your board !!
*
* ms7724 board should not use GPIO_FN_LNKSTA pin
* So, This time PTX5 is set to input pin
*/
gpio_request(GPIO_FN_RMII_RXD0, NULL);
gpio_request(GPIO_FN_RMII_RXD1, NULL);
gpio_request(GPIO_FN_RMII_TXD0, NULL);
gpio_request(GPIO_FN_RMII_TXD1, NULL);
gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
gpio_request(GPIO_FN_RMII_TX_EN, NULL);
gpio_request(GPIO_FN_RMII_RX_ER, NULL);
gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
gpio_request(GPIO_FN_MDIO, NULL);
gpio_request(GPIO_FN_MDC, NULL);
gpio_request(GPIO_PTX5, NULL);
gpio_direction_input(GPIO_PTX5);
sh_eth_init();
if (sw & SW41_B) {
/* 720p */
lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
} else {
/* VGA */
lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
}
if (sw & SW41_A) {
/* Digital monitor */
lcdc_info.ch[0].interface_type = RGB18;
lcdc_info.ch[0].flags = 0;
} else {
/* Analog monitor */
lcdc_info.ch[0].interface_type = RGB24;
lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
}
/* VOU */
gpio_request(GPIO_FN_DV_D15, NULL);
gpio_request(GPIO_FN_DV_D14, NULL);
gpio_request(GPIO_FN_DV_D13, NULL);
gpio_request(GPIO_FN_DV_D12, NULL);
gpio_request(GPIO_FN_DV_D11, NULL);
gpio_request(GPIO_FN_DV_D10, NULL);
gpio_request(GPIO_FN_DV_D9, NULL);
gpio_request(GPIO_FN_DV_D8, NULL);
gpio_request(GPIO_FN_DV_CLKI, NULL);
gpio_request(GPIO_FN_DV_CLK, NULL);
gpio_request(GPIO_FN_DV_VSYNC, NULL);
gpio_request(GPIO_FN_DV_HSYNC, NULL);
/* Initialize CEU platform devices separately to map memory first */
device_initialize(&ms7724se_ceu_devices[0]->dev);
dma_declare_coherent_memory(&ms7724se_ceu_devices[0]->dev,
ceu0_dma_membase, ceu0_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(ms7724se_ceu_devices[0]);
device_initialize(&ms7724se_ceu_devices[1]->dev);
dma_declare_coherent_memory(&ms7724se_ceu_devices[1]->dev,
ceu1_dma_membase, ceu1_dma_membase,
CEU_BUFFER_MEMORY_SIZE);
platform_device_add(ms7724se_ceu_devices[1]);
return platform_add_devices(ms7724se_devices,
ARRAY_SIZE(ms7724se_devices));
}
device_initcall(devices_setup);
/* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
static void __init ms7724se_mv_mem_reserve(void)
{
phys_addr_t phys;
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU0 memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu0_dma_membase = phys;
phys = memblock_phys_alloc(size, PAGE_SIZE);
if (!phys)
panic("Failed to allocate CEU1 memory\n");
memblock_phys_free(phys, size);
memblock_remove(phys, size);
ceu1_dma_membase = phys;
}
static struct sh_machine_vector mv_ms7724se __initmv = {
.mv_name = "ms7724se",
.mv_init_irq = init_se7724_IRQ,
.mv_mem_reserve = ms7724se_mv_mem_reserve,
};
| linux-master | arch/sh/boards/mach-se/7724/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2012 Paul Mundt
*/
#define DRV_NAME "SE7722-FPGA"
#define pr_fmt(fmt) DRV_NAME ": " fmt
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/sizes.h>
#include <mach-se/mach/se7722.h>
#define IRQ01_BASE_ADDR 0x11800000
#define IRQ01_MODE_REG 0
#define IRQ01_STS_REG 4
#define IRQ01_MASK_REG 8
static void __iomem *se7722_irq_regs;
struct irq_domain *se7722_irq_domain;
static void se7722_irq_demux(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
unsigned long mask;
int bit;
chip->irq_mask_ack(data);
mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
generic_handle_domain_irq(se7722_irq_domain, bit);
chip->irq_unmask(data);
}
static void __init se7722_domain_init(void)
{
int i;
se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
&irq_domain_simple_ops, NULL);
if (unlikely(!se7722_irq_domain)) {
printk("Failed to get IRQ domain\n");
return;
}
for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
int irq = irq_create_mapping(se7722_irq_domain, i);
if (unlikely(irq == 0)) {
printk("Failed to allocate IRQ %d\n", i);
return;
}
}
}
static void __init se7722_gc_init(void)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
unsigned int irq_base;
irq_base = irq_linear_revmap(se7722_irq_domain, 0);
gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
handle_level_irq);
if (unlikely(!gc))
return;
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->regs.mask = IRQ01_MASK_REG;
irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
}
/*
* Initialize FPGA IRQs
*/
void __init init_se7722_IRQ(void)
{
se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
if (unlikely(!se7722_irq_regs)) {
printk("Failed to remap IRQ01 regs\n");
return;
}
/*
* All FPGA IRQs disabled by default
*/
iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
se7722_domain_init();
se7722_gc_init();
}
| linux-master | arch/sh/boards/mach-se/7722/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7722/setup.c
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2012 Paul Mundt
*
* Hitachi UL SolutionEngine 7722 Support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/irqdomain.h>
#include <linux/smc91x.h>
#include <linux/sh_intc.h>
#include <mach-se/mach/se7722.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/clock.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <cpu/sh7722.h>
/* Heartbeat */
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT,
};
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = PA_LAN + 0x300,
.end = PA_LAN + 0x300 + 0x10 ,
.flags = IORESOURCE_MEM,
},
[1] = {
/* Filled in later */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_MRSHPC_IO + 0x1f0,
.end = PA_MRSHPC_IO + 0x1f0 + 8 ,
.flags = IORESOURCE_IO,
},
[1] = {
.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
.end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
/* Filled in later */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct sh_keysc_info sh_keysc_info = {
.mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
.scan_timing = 3,
.delay = 5,
.keycodes = { /* SW1 -> SW30 */
KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
KEY_Z,
KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
},
};
static struct resource sh_keysc_resources[] = {
[0] = {
.start = 0x044b0000,
.end = 0x044b000f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0xbe0),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh_keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(sh_keysc_resources),
.resource = sh_keysc_resources,
.dev = {
.platform_data = &sh_keysc_info,
},
};
static struct platform_device *se7722_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&cf_ide_device,
&sh_keysc_device,
};
static int __init se7722_devices_setup(void)
{
mrshpc_setup_windows();
/* Wire-up dynamic vectors */
cf_ide_resources[2].start = cf_ide_resources[2].end =
irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
}
device_initcall(se7722_devices_setup);
static void __init se7722_setup(char **cmdline_p)
{
__raw_writew(0x010D, FPGA_OUT); /* FPGA */
__raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
__raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
/* LCDC I/O */
__raw_writew(0x0020, PORT_PSELD);
/* SIOF1*/
__raw_writew(0x0003, PORT_PSELB);
__raw_writew(0xe000, PORT_PSELC);
__raw_writew(0x0000, PORT_PKCR);
/* LCDC */
__raw_writew(0x4020, PORT_PHCR);
__raw_writew(0x0000, PORT_PLCR);
__raw_writew(0x0000, PORT_PMCR);
__raw_writew(0x0002, PORT_PRCR);
__raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
/* KEYSC */
__raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
__raw_writew(0x0000, PORT_PYCR);
__raw_writew(0x0000, PORT_PZCR);
__raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
__raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se7722 __initmv = {
.mv_name = "Solution Engine 7722" ,
.mv_setup = se7722_setup ,
.mv_init_irq = init_se7722_IRQ,
};
| linux-master | arch/sh/boards/mach-se/7722/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/770x/irq.c
*
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2006 Nobuhiro Iwamatsu
*
* Hitachi SolutionEngine Support.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <mach-se/mach/se.h>
static struct ipr_data ipr_irq_table[] = {
/*
* Super I/O (Just mimic PC):
* 1: keyboard
* 3: serial 0
* 4: serial 1
* 5: printer
* 6: floppy
* 8: rtc
* 12: mouse
* 14: ide0
*/
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
/* This is default value */
{ 13, 0, 8, 0x0f-13, },
{ 5 , 0, 4, 0x0f- 5, },
{ 10, 1, 0, 0x0f-10, },
{ 7 , 2, 4, 0x0f- 7, },
{ 3 , 2, 0, 0x0f- 3, },
{ 1 , 3, 12, 0x0f- 1, },
{ 12, 3, 4, 0x0f-12, }, /* LAN */
{ 2 , 4, 8, 0x0f- 2, }, /* PCIRQ2 */
{ 6 , 4, 4, 0x0f- 6, }, /* PCIRQ1 */
{ 14, 4, 0, 0x0f-14, }, /* PCIRQ0 */
{ 0 , 5, 12, 0x0f , },
{ 4 , 5, 4, 0x0f- 4, },
{ 8 , 6, 12, 0x0f- 8, },
{ 9 , 6, 8, 0x0f- 9, },
{ 11, 6, 4, 0x0f-11, },
#else
{ 14, 0, 8, 0x0f-14, },
{ 12, 0, 4, 0x0f-12, },
{ 8, 1, 4, 0x0f- 8, },
{ 6, 2, 12, 0x0f- 6, },
{ 5, 2, 8, 0x0f- 5, },
{ 4, 2, 4, 0x0f- 4, },
{ 3, 2, 0, 0x0f- 3, },
{ 1, 3, 12, 0x0f- 1, },
#if defined(CONFIG_STNIC)
/* ST NIC */
{ 10, 3, 4, 0x0f-10, }, /* LAN */
#endif
/* MRSHPC IRQs setting */
{ 0, 4, 12, 0x0f- 0, }, /* PCIRQ3 */
{ 11, 4, 8, 0x0f-11, }, /* PCIRQ2 */
{ 9, 4, 4, 0x0f- 9, }, /* PCIRQ1 */
{ 7, 4, 0, 0x0f- 7, }, /* PCIRQ0 */
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
/* NOTE: #2 and #13 are not used on PC */
{ 13, 6, 4, 0x0f-13, }, /* SLOTIRQ2 */
{ 2, 6, 0, 0x0f- 2, }, /* SLOTIRQ1 */
#endif
};
static unsigned long ipr_offsets[] = {
BCR_ILCRA,
BCR_ILCRB,
BCR_ILCRC,
BCR_ILCRD,
BCR_ILCRE,
BCR_ILCRF,
BCR_ILCRG,
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-se770x",
},
};
/*
* Initialize IRQ setting
*/
void __init init_se_IRQ(void)
{
/* Disable all interrupts */
__raw_writew(0, BCR_ILCRA);
__raw_writew(0, BCR_ILCRB);
__raw_writew(0, BCR_ILCRC);
__raw_writew(0, BCR_ILCRD);
__raw_writew(0, BCR_ILCRE);
__raw_writew(0, BCR_ILCRF);
__raw_writew(0, BCR_ILCRG);
register_ipr_controller(&ipr_irq_desc);
}
| linux-master | arch/sh/boards/mach-se/770x/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/770x/setup.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SolutionEngine Support.
*
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sh_eth.h>
#include <mach-se/mach/se.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/smc37c93x.h>
#include <asm/heartbeat.h>
/*
* Configure the Super I/O chip
*/
static void __init smsc_config(int index, int data)
{
outb_p(index, INDEX_PORT);
outb_p(data, DATA_PORT);
}
/* XXX: Another candidate for a more generic cchip machine vector */
static void __init smsc_setup(char **cmdline_p)
{
outb_p(CONFIG_ENTER, CONFIG_PORT);
outb_p(CONFIG_ENTER, CONFIG_PORT);
/* FDC */
smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
smsc_config(ACTIVATE_INDEX, 0x01);
smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
/* AUXIO (GPIO): to use IDE1 */
smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
/* COM1 */
smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
smsc_config(ACTIVATE_INDEX, 0x01);
smsc_config(IO_BASE_HI_INDEX, 0x03);
smsc_config(IO_BASE_LO_INDEX, 0xf8);
smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
/* COM2 */
smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
smsc_config(ACTIVATE_INDEX, 0x01);
smsc_config(IO_BASE_HI_INDEX, 0x02);
smsc_config(IO_BASE_LO_INDEX, 0xf8);
smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
/* RTC */
smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
smsc_config(ACTIVATE_INDEX, 0x01);
smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
/* XXX: PARPORT, KBD, and MOUSE will come here... */
outb_p(CONFIG_EXIT, CONFIG_PORT);
}
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_MRSHPC_IO + 0x1f0,
.end = PA_MRSHPC_IO + 0x1f0 + 8,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
.end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_CFCARD,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = 1,
.resource = &heartbeat_resource,
};
#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
defined(CONFIG_CPU_SUBTYPE_SH7712)
/* SH771X Ethernet driver */
static struct sh_eth_plat_data sh_eth_plat = {
.phy = PHY_ID,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct resource sh_eth0_resources[] = {
[0] = {
.start = SH_ETH0_BASE,
.end = SH_ETH0_BASE + 0x1B8 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SH_TSU_BASE,
.end = SH_TSU_BASE + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = SH_ETH0_IRQ,
.end = SH_ETH0_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh_eth0_device = {
.name = "sh771x-ether",
.id = 0,
.dev = {
.platform_data = &sh_eth_plat,
},
.num_resources = ARRAY_SIZE(sh_eth0_resources),
.resource = sh_eth0_resources,
};
static struct resource sh_eth1_resources[] = {
[0] = {
.start = SH_ETH1_BASE,
.end = SH_ETH1_BASE + 0x1B8 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SH_TSU_BASE,
.end = SH_TSU_BASE + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = SH_ETH1_IRQ,
.end = SH_ETH1_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sh_eth1_device = {
.name = "sh771x-ether",
.id = 1,
.dev = {
.platform_data = &sh_eth_plat,
},
.num_resources = ARRAY_SIZE(sh_eth1_resources),
.resource = sh_eth1_resources,
};
#endif
static struct platform_device *se_devices[] __initdata = {
&heartbeat_device,
&cf_ide_device,
#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
defined(CONFIG_CPU_SUBTYPE_SH7712)
&sh_eth0_device,
&sh_eth1_device,
#endif
};
static int __init se_devices_setup(void)
{
mrshpc_setup_windows();
return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
}
device_initcall(se_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_setup = smsc_setup,
.mv_init_irq = init_se_IRQ,
};
| linux-master | arch/sh/boards/mach-se/770x/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7751/irq.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SolutionEngine Support.
*
* Modified for 7751 Solution Engine by
* Ian da Silva and Jeremy Siegel, 2001.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <mach-se/mach/se7751.h>
static struct ipr_data ipr_irq_table[] = {
{ 13, 3, 3, 2 },
/* Add additional entries here as drivers are added and tested. */
};
static unsigned long ipr_offsets[] = {
BCR_ILCRA,
BCR_ILCRB,
BCR_ILCRC,
BCR_ILCRD,
BCR_ILCRE,
BCR_ILCRF,
BCR_ILCRG,
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-se7751",
},
};
/*
* Initialize IRQ setting
*/
void __init init_7751se_IRQ(void)
{
register_ipr_controller(&ipr_irq_desc);
}
| linux-master | arch/sh/boards/mach-se/7751/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7751/setup.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SolutionEngine Support.
*
* Modified for 7751 Solution Engine by
* Ian da Silva and Jeremy Siegel, 2001.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <mach-se/mach/se7751.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct platform_device *se7751_devices[] __initdata = {
&heartbeat_device,
};
static int __init se7751_devices_setup(void)
{
return platform_add_devices(se7751_devices, ARRAY_SIZE(se7751_devices));
}
device_initcall(se7751_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_7751se __initmv = {
.mv_name = "7751 SolutionEngine",
.mv_init_irq = init_7751se_IRQ,
};
| linux-master | arch/sh/boards/mach-se/7751/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7206/irq.c
*
* Copyright (C) 2005,2006 Yoshinori Sato
*
* Hitachi SolutionEngine Support.
*
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <mach-se/mach/se7206.h>
#define INTSTS0 0x31800000
#define INTSTS1 0x31800002
#define INTMSK0 0x31800004
#define INTMSK1 0x31800006
#define INTSEL 0x31800008
#define IRQ0_IRQ 64
#define IRQ1_IRQ 65
#define IRQ3_IRQ 67
#define INTC_IPR01 0xfffe0818
#define INTC_ICR1 0xfffe0802
static void disable_se7206_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned short val;
unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
unsigned short msk0,msk1;
/* Set the priority in IPR to 0 */
val = __raw_readw(INTC_IPR01);
val &= mask;
__raw_writew(val, INTC_IPR01);
/* FPGA mask set */
msk0 = __raw_readw(INTMSK0);
msk1 = __raw_readw(INTMSK1);
switch (irq) {
case IRQ0_IRQ:
msk0 |= 0x0010;
break;
case IRQ1_IRQ:
msk0 |= 0x000f;
break;
case IRQ3_IRQ:
msk0 |= 0x0f00;
msk1 |= 0x00ff;
break;
}
__raw_writew(msk0, INTMSK0);
__raw_writew(msk1, INTMSK1);
}
static void enable_se7206_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned short val;
unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
unsigned short msk0,msk1;
/* Set priority in IPR back to original value */
val = __raw_readw(INTC_IPR01);
val |= value;
__raw_writew(val, INTC_IPR01);
/* FPGA mask reset */
msk0 = __raw_readw(INTMSK0);
msk1 = __raw_readw(INTMSK1);
switch (irq) {
case IRQ0_IRQ:
msk0 &= ~0x0010;
break;
case IRQ1_IRQ:
msk0 &= ~0x000f;
break;
case IRQ3_IRQ:
msk0 &= ~0x0f00;
msk1 &= ~0x00ff;
break;
}
__raw_writew(msk0, INTMSK0);
__raw_writew(msk1, INTMSK1);
}
static void eoi_se7206_irq(struct irq_data *data)
{
unsigned short sts0,sts1;
unsigned int irq = data->irq;
if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
enable_se7206_irq(data);
/* FPGA isr clear */
sts0 = __raw_readw(INTSTS0);
sts1 = __raw_readw(INTSTS1);
switch (irq) {
case IRQ0_IRQ:
sts0 &= ~0x0010;
break;
case IRQ1_IRQ:
sts0 &= ~0x000f;
break;
case IRQ3_IRQ:
sts0 &= ~0x0f00;
sts1 &= ~0x00ff;
break;
}
__raw_writew(sts0, INTSTS0);
__raw_writew(sts1, INTSTS1);
}
static struct irq_chip se7206_irq_chip __read_mostly = {
.name = "SE7206-FPGA",
.irq_mask = disable_se7206_irq,
.irq_unmask = enable_se7206_irq,
.irq_eoi = eoi_se7206_irq,
};
static void make_se7206_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
handle_level_irq, "level");
disable_se7206_irq(irq_get_irq_data(irq));
}
/*
* Initialize IRQ setting
*/
void __init init_se7206_IRQ(void)
{
make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
make_se7206_irq(IRQ1_IRQ); /* ATA */
make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
/* FPGA System register setup*/
__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
__raw_writew(0x0001,INTSEL);
}
| linux-master | arch/sh/boards/mach-se/7206/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
*
* linux/arch/sh/boards/se/7206/setup.c
*
* Copyright (C) 2006 Yoshinori Sato
* Copyright (C) 2007 - 2008 Paul Mundt
*
* Hitachi 7206 SolutionEngine Support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <mach-se/mach/se7206.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/heartbeat.h>
static struct resource smc91x_resources[] = {
[0] = {
.name = "smc91x-regs",
.start = PA_SMSC + 0x300,
.end = PA_SMSC + 0x300 + 0x020 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 64,
.end = 64,
.flags = IORESOURCE_IRQ,
},
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.dma_mask = NULL,
.coherent_dma_mask = 0xffffffff,
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct platform_device *se7206_devices[] __initdata = {
&smc91x_device,
&heartbeat_device,
};
static int __init se7206_devices_setup(void)
{
return platform_add_devices(se7206_devices, ARRAY_SIZE(se7206_devices));
}
device_initcall(se7206_devices_setup);
static int se7206_mode_pins(void)
{
return MODE_PIN1 | MODE_PIN2;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_init_irq = init_se7206_IRQ,
.mv_mode_pins = se7206_mode_pins,
};
| linux-master | arch/sh/boards/mach-se/7206/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
*
* Copyright (C) 2008 Yoshihiro Shimoda
* Copyright (C) 2012 Paul Mundt
*
* Based on linux/arch/sh/boards/se/7343/irq.c
* Copyright (C) 2007 Nobuhiro Iwamatsu
*/
#define DRV_NAME "SE7343-FPGA"
#define pr_fmt(fmt) DRV_NAME ": " fmt
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <mach-se/mach/se7343.h>
#define PA_CPLD_BASE_ADDR 0x11400000
#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
static void __iomem *se7343_irq_regs;
struct irq_domain *se7343_irq_domain;
static void se7343_irq_demux(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
unsigned long mask;
int bit;
chip->irq_mask_ack(data);
mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
generic_handle_domain_irq(se7343_irq_domain, bit);
chip->irq_unmask(data);
}
static void __init se7343_domain_init(void)
{
int i;
se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
&irq_domain_simple_ops, NULL);
if (unlikely(!se7343_irq_domain)) {
printk("Failed to get IRQ domain\n");
return;
}
for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
int irq = irq_create_mapping(se7343_irq_domain, i);
if (unlikely(irq == 0)) {
printk("Failed to allocate IRQ %d\n", i);
return;
}
}
}
static void __init se7343_gc_init(void)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
unsigned int irq_base;
irq_base = irq_linear_revmap(se7343_irq_domain, 0);
gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
handle_level_irq);
if (unlikely(!gc))
return;
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->regs.mask = PA_CPLD_IMSK_REG;
irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
}
/*
* Initialize IRQ setting
*/
void __init init_7343se_IRQ(void)
{
se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
if (unlikely(!se7343_irq_regs)) {
pr_err("Failed to remap CPLD\n");
return;
}
/*
* All FPGA IRQs disabled by default
*/
iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
se7343_domain_init();
se7343_gc_init();
}
| linux-master | arch/sh/boards/mach-se/7343/irq.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/usb/isp116x.h>
#include <linux/delay.h>
#include <linux/irqdomain.h>
#include <asm/machvec.h>
#include <mach-se/mach/se7343.h>
#include <asm/heartbeat.h>
#include <asm/irq.h>
#include <asm/io.h>
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "loader",
.offset = 0x00000000,
.size = 128 * 1024,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = 31 * 1024 * 1024,
},
{
.name = "data",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.start = 0x00000000,
.end = 0x01ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.dev = {
.platform_data = &nor_flash_data,
},
.num_resources = ARRAY_SIZE(nor_flash_resources),
.resource = nor_flash_resources,
};
#define ST16C2550C_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP)
static struct plat_serial8250_port serial_platform_data[] = {
[0] = {
.iotype = UPIO_MEM,
.mapbase = 0x16000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.uartclk = 7372800,
},
[1] = {
.iotype = UPIO_MEM,
.mapbase = 0x17000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.uartclk = 7372800,
},
{ },
};
static struct platform_device uart_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
static void isp116x_delay(struct device *dev, int delay)
{
ndelay(delay);
}
static struct resource usb_resources[] = {
[0] = {
.start = 0x11800000,
.end = 0x11800001,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x11800002,
.end = 0x11800003,
.flags = IORESOURCE_MEM,
},
[2] = {
/* Filled in later */
.flags = IORESOURCE_IRQ,
},
};
static struct isp116x_platform_data usb_platform_data = {
.sel15Kres = 1,
.oc_enable = 1,
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_enable = 0,
.delay = isp116x_delay,
};
static struct platform_device usb_device = {
.name = "isp116x-hcd",
.id = -1,
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
.dev = {
.platform_data = &usb_platform_data,
},
};
static struct platform_device *sh7343se_platform_devices[] __initdata = {
&heartbeat_device,
&nor_flash_device,
&uart_device,
&usb_device,
};
static int __init sh7343se_devices_setup(void)
{
/* Wire-up dynamic vectors */
serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
SE7343_FPGA_IRQ_UARTA);
serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
SE7343_FPGA_IRQ_UARTB);
usb_resources[2].start = usb_resources[2].end =
irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
return platform_add_devices(sh7343se_platform_devices,
ARRAY_SIZE(sh7343se_platform_devices));
}
device_initcall(sh7343se_devices_setup);
/*
* Initialize the board
*/
static void __init sh7343se_setup(char **cmdline_p)
{
__raw_writew(0xf900, FPGA_OUT); /* FPGA */
__raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
__raw_writew(0x0020, PORT_PSELD);
printk(KERN_INFO "MS7343CP01 Setup...done\n");
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_7343se __initmv = {
.mv_name = "SolutionEngine 7343",
.mv_setup = sh7343se_setup,
.mv_init_irq = init_7343se_IRQ,
};
| linux-master | arch/sh/boards/mach-se/7343/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7780/irq.c
*
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7780 Support.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach-se/mach/se7780.h>
#define INTC_BASE 0xffd00000
#define INTC_ICR1 (INTC_BASE+0x1c)
/*
* Initialize IRQ setting
*/
void __init init_se7780_IRQ(void)
{
/* enable all interrupt at FPGA */
__raw_writew(0, FPGA_INTMSK1);
/* mask SM501 interrupt */
__raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
/* enable all interrupt at FPGA */
__raw_writew(0, FPGA_INTMSK2);
/* set FPGA INTSEL register */
/* FPGA + 0x06 */
__raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
/* FPGA + 0x08 */
__raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
/* FPGA + 0x0A */
__raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
/* ICR1: detect low level(for 2ndcut) */
__raw_writel(0xAAAA0000, INTC_ICR1);
/*
* FPGA PCISEL register initialize
*
* CPU || SLOT1 | SLOT2 | S-ATA | USB
* -------------------------------------
* INTA || INTA | INTD | -- | INTB
* -------------------------------------
* INTB || INTB | INTA | -- | INTC
* -------------------------------------
* INTC || INTC | INTB | INTA | --
* -------------------------------------
* INTD || INTD | INTC | -- | INTA
* -------------------------------------
*/
__raw_writew(0x0013, FPGA_PCI_INTSEL1);
__raw_writew(0xE402, FPGA_PCI_INTSEL2);
}
| linux-master | arch/sh/boards/mach-se/7780/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7780/setup.c
*
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7780 Support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <mach-se/mach/se7780.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
/* Heartbeat */
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = PA_LAN + 0x300,
.end = PA_LAN + 0x300 + 0x10 ,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SMC_IRQ,
.end = SMC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct platform_device *se7780_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
};
static int __init se7780_devices_setup(void)
{
return platform_add_devices(se7780_devices,
ARRAY_SIZE(se7780_devices));
}
device_initcall(se7780_devices_setup);
#define GPIO_PHCR 0xFFEA000E
#define GPIO_PMSELR 0xFFEA0080
#define GPIO_PECR 0xFFEA0008
static void __init se7780_setup(char **cmdline_p)
{
/* "SH-Linux" on LED Display */
__raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
__raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
__raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
__raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
__raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
__raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
__raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
__raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
/*
* PCI REQ/GNT setting
* REQ0/GNT0 -> USB
* REQ1/GNT1 -> PC Card
* REQ2/GNT2 -> Serial ATA
* REQ3/GNT3 -> PCI slot
*/
__raw_writew(0x0213, FPGA_REQSEL);
/* GPIO setting */
__raw_writew(0x0000, GPIO_PECR);
__raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
__raw_writew(0x0c00, GPIO_PMSELR);
/* iVDR Power ON */
__raw_writew(0x0001, FPGA_IVDRPW);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se7780 __initmv = {
.mv_name = "Solution Engine 7780" ,
.mv_setup = se7780_setup ,
.mv_init_irq = init_se7780_IRQ,
};
| linux-master | arch/sh/boards/mach-se/7780/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7721/irq.c
*
* Copyright (C) 2008 Renesas Solutions Corp.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach-se/mach/se7721.h>
enum {
UNUSED = 0,
/* board specific interrupt sources */
MRSHPC,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(MRSHPC, MRSHPC_IRQ0),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ FPGA_ILSR6, 0, 8, 4, /* IRLMSK */
{ 0, MRSHPC } },
};
static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
NULL, NULL, prio_registers, NULL);
/*
* Initialize IRQ setting
*/
void __init init_se7721_IRQ(void)
{
/* PPCR */
__raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118);
register_intc_controller(&intc_desc);
intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
}
| linux-master | arch/sh/boards/mach-se/7721/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/se/7721/setup.c
*
* Copyright (C) 2008 Renesas Solutions Corp.
*
* Hitachi UL SolutionEngine 7721 Support.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <mach-se/mach/se7721.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = 1,
.resource = &heartbeat_resource,
};
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_MRSHPC_IO + 0x1f0,
.end = PA_MRSHPC_IO + 0x1f0 + 8 ,
.flags = IORESOURCE_IO,
},
[1] = {
.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
.end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
.start = MRSHPC_IRQ0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct platform_device *se7721_devices[] __initdata = {
&cf_ide_device,
&heartbeat_device
};
static int __init se7721_devices_setup(void)
{
mrshpc_setup_windows();
return platform_add_devices(se7721_devices, ARRAY_SIZE(se7721_devices));
}
device_initcall(se7721_devices_setup);
static void __init se7721_setup(char **cmdline_p)
{
/* for USB */
__raw_writew(0x0000, 0xA405010C); /* PGCR */
__raw_writew(0x0000, 0xA405010E); /* PHCR */
__raw_writew(0x00AA, 0xA4050118); /* PPCR */
__raw_writew(0x0000, 0xA4050124); /* PSELA */
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_se7721 __initmv = {
.mv_name = "Solution Engine 7721",
.mv_setup = se7721_setup,
.mv_init_irq = init_se7721_IRQ,
};
| linux-master | arch/sh/boards/mach-se/7721/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/lboxre2/irq.c
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* NTT COMWARE L-BOX RE2 Support.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <mach/lboxre2.h>
/*
* Initialize IRQ setting
*/
void __init init_lboxre2_IRQ(void)
{
make_imask_irq(IRQ_CF1);
make_imask_irq(IRQ_CF0);
make_imask_irq(IRQ_INTD);
make_imask_irq(IRQ_ETH1);
make_imask_irq(IRQ_ETH0);
make_imask_irq(IRQ_INTA);
}
| linux-master | arch/sh/boards/mach-lboxre2/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/lbox/setup.c
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* NTT COMWARE L-BOX RE2 Support
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <asm/machvec.h>
#include <asm/addrspace.h>
#include <mach/lboxre2.h>
#include <asm/io.h>
static struct resource cf_ide_resources[] = {
[0] = {
.start = 0x1f0,
.end = 0x1f0 + 8 ,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 0x1f0 + 0x206,
.end = 0x1f0 +8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
.start = IRQ_CF0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct platform_device *lboxre2_devices[] __initdata = {
&cf_ide_device,
};
static int __init lboxre2_devices_setup(void)
{
u32 cf0_io_base; /* Boot CF base address */
pgprot_t prot;
unsigned long paddrbase, psize;
/* open I/O area window */
paddrbase = virt_to_phys((void*)PA_AREA5_IO);
psize = PAGE_SIZE;
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf0_io_base = (u32)ioremap_prot(paddrbase, psize, pgprot_val(prot));
if (!cf0_io_base) {
printk(KERN_ERR "%s : can't open CF I/O window!\n" , __func__ );
return -ENOMEM;
}
cf_ide_resources[0].start += cf0_io_base ;
cf_ide_resources[0].end += cf0_io_base ;
cf_ide_resources[1].start += cf0_io_base ;
cf_ide_resources[1].end += cf0_io_base ;
return platform_add_devices(lboxre2_devices,
ARRAY_SIZE(lboxre2_devices));
}
device_initcall(lboxre2_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_lboxre2 __initmv = {
.mv_name = "L-BOX RE2",
.mv_init_irq = init_lboxre2_IRQ,
};
| linux-master | arch/sh/boards/mach-lboxre2/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/renesas/sdk7780/irq.c
*
* Renesas Technology Europe SDK7780 Support.
*
* Copyright (C) 2008 Nicholas Beck <[email protected]>
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/sdk7780.h>
enum {
UNUSED = 0,
/* board specific interrupt sources */
SMC91C111, /* Ethernet controller */
};
static struct intc_vect fpga_vectors[] __initdata = {
INTC_IRQ(SMC91C111, IRQ_ETHERNET),
};
static struct intc_mask_reg fpga_mask_registers[] __initdata = {
{ 0, FPGA_IRQ0MR, 16,
{ 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, SMC91C111, 0, 0, 0, 0 } },
};
static DECLARE_INTC_DESC(fpga_intc_desc, "sdk7780-irq", fpga_vectors,
NULL, fpga_mask_registers, NULL, NULL);
void __init init_sdk7780_IRQ(void)
{
printk(KERN_INFO "Using SDK7780 interrupt controller.\n");
__raw_writew(0xFFFF, FPGA_IRQ0MR);
/* Setup IRL 0-3 */
__raw_writew(0x0003, FPGA_IMSR);
plat_irq_setup_pins(IRQ_MODE_IRL3210);
register_intc_controller(&fpga_intc_desc);
}
| linux-master | arch/sh/boards/mach-sdk7780/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/renesas/sdk7780/setup.c
*
* Renesas Solutions SH7780 SDK Support
* Copyright (C) 2008 Nicholas Beck <[email protected]>
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <asm/machvec.h>
#include <mach/sdk7780.h>
#include <asm/heartbeat.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#define GPIO_PECR 0xFFEA0008
/* Heartbeat */
static struct resource heartbeat_resource = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* SMC91x */
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = PA_LAN + 0x300,
.end = PA_LAN + 0x300 + 0x10 ,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_ETHERNET,
.end = IRQ_ETHERNET,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct platform_device *sdk7780_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
};
static int __init sdk7780_devices_setup(void)
{
return platform_add_devices(sdk7780_devices,
ARRAY_SIZE(sdk7780_devices));
}
device_initcall(sdk7780_devices_setup);
static void __init sdk7780_setup(char **cmdline_p)
{
u16 ver = __raw_readw(FPGA_FPVERR);
u16 dateStamp = __raw_readw(FPGA_FPDATER);
printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n");
printk(KERN_INFO "Board version: %d (revision %d), "
"FPGA version: %d (revision %d), datestamp : %d\n",
(ver >> 12) & 0xf, (ver >> 8) & 0xf,
(ver >> 4) & 0xf, ver & 0xf,
dateStamp);
/* Setup pin mux'ing for PCIC */
__raw_writew(0x0000, GPIO_PECR);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_se7780 __initmv = {
.mv_name = "Renesas SDK7780-R3" ,
.mv_setup = sdk7780_setup,
.mv_init_irq = init_sdk7780_IRQ,
};
| linux-master | arch/sh/boards/mach-sdk7780/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/mach-x3proto/gpio.c
*
* Renesas SH-X3 Prototype Baseboard GPIO Support.
*
* Copyright (C) 2010 - 2012 Paul Mundt
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <mach/ilsel.h>
#include <mach/hardware.h>
#define KEYCTLR 0xb81c0000
#define KEYOUTR 0xb81c0002
#define KEYDETR 0xb81c0004
static DEFINE_SPINLOCK(x3proto_gpio_lock);
static struct irq_domain *x3proto_irq_domain;
static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
unsigned long flags;
unsigned int data;
spin_lock_irqsave(&x3proto_gpio_lock, flags);
data = __raw_readw(KEYCTLR);
data |= (1 << gpio);
__raw_writew(data, KEYCTLR);
spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
return 0;
}
static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
return !!(__raw_readw(KEYDETR) & (1 << gpio));
}
static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
int virq;
if (gpio < chip->ngpio)
virq = irq_create_mapping(x3proto_irq_domain, gpio);
else
virq = -ENXIO;
return virq;
}
static void x3proto_gpio_irq_handler(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
unsigned long mask;
int pin;
chip->irq_mask_ack(data);
mask = __raw_readw(KEYDETR);
for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
generic_handle_domain_irq(x3proto_irq_domain, pin);
chip->irq_unmask(data);
}
struct gpio_chip x3proto_gpio_chip = {
.label = "x3proto-gpio",
.direction_input = x3proto_gpio_direction_input,
.get = x3proto_gpio_get,
.to_irq = x3proto_gpio_to_irq,
.base = -1,
.ngpio = NR_BASEBOARD_GPIOS,
};
static int x3proto_gpio_irq_map(struct irq_domain *domain, unsigned int virq,
irq_hw_number_t hwirq)
{
irq_set_chip_and_handler_name(virq, &dummy_irq_chip, handle_simple_irq,
"gpio");
return 0;
}
static struct irq_domain_ops x3proto_gpio_irq_ops = {
.map = x3proto_gpio_irq_map,
.xlate = irq_domain_xlate_twocell,
};
int __init x3proto_gpio_setup(void)
{
int ilsel, ret;
ilsel = ilsel_enable(ILSEL_KEY);
if (unlikely(ilsel < 0))
return ilsel;
ret = gpiochip_add_data(&x3proto_gpio_chip, NULL);
if (unlikely(ret))
goto err_gpio;
x3proto_irq_domain = irq_domain_add_linear(NULL, NR_BASEBOARD_GPIOS,
&x3proto_gpio_irq_ops, NULL);
if (unlikely(!x3proto_irq_domain))
goto err_irq;
pr_info("registering '%s' support, handling GPIOs %u -> %u, "
"bound to IRQ %u\n",
x3proto_gpio_chip.label, x3proto_gpio_chip.base,
x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio,
ilsel);
irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler);
irq_set_irq_wake(ilsel, 1);
return 0;
err_irq:
gpiochip_remove(&x3proto_gpio_chip);
ret = 0;
err_gpio:
synchronize_irq(ilsel);
ilsel_disable(ILSEL_KEY);
return ret;
}
| linux-master | arch/sh/boards/mach-x3proto/gpio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/mach-x3proto/setup.c
*
* Renesas SH-X3 Prototype Board Support.
*
* Copyright (C) 2007 - 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/smc91x.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/m66592.h>
#include <linux/gpio/driver.h>
#include <linux/gpio_keys.h>
#include <mach/ilsel.h>
#include <mach/hardware.h>
#include <asm/smp-ops.h>
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xb8140020,
.end = 0xb8140020,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x18000300,
.end = 0x18000300 + 0x10 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.resource = smc91x_resources,
.num_resources = ARRAY_SIZE(smc91x_resources),
.dev = {
.platform_data = &smc91x_info,
},
};
static struct r8a66597_platdata r8a66597_data = {
.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
.vif = 1,
};
static struct resource r8a66597_usb_host_resources[] = {
[0] = {
.start = 0x18040000,
.end = 0x18080000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device r8a66597_usb_host_device = {
.name = "r8a66597_hcd",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &r8a66597_data,
},
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
.resource = r8a66597_usb_host_resources,
};
static struct m66592_platdata usbf_platdata = {
.xtal = M66592_PLATDATA_XTAL_24MHZ,
.vif = 1,
};
static struct resource m66592_usb_peripheral_resources[] = {
[0] = {
.name = "m66592_udc",
.start = 0x18080000,
.end = 0x180c0000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "m66592_udc",
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device m66592_usb_peripheral_device = {
.name = "m66592_udc",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usbf_platdata,
},
.num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources),
.resource = m66592_usb_peripheral_resources,
};
static struct gpio_keys_button baseboard_buttons[NR_BASEBOARD_GPIOS] = {
{
.desc = "key44",
.code = KEY_POWER,
.active_low = 1,
.wakeup = 1,
}, {
.desc = "key43",
.code = KEY_SUSPEND,
.active_low = 1,
.wakeup = 1,
}, {
.desc = "key42",
.code = KEY_KATAKANAHIRAGANA,
.active_low = 1,
}, {
.desc = "key41",
.code = KEY_SWITCHVIDEOMODE,
.active_low = 1,
}, {
.desc = "key34",
.code = KEY_F12,
.active_low = 1,
}, {
.desc = "key33",
.code = KEY_F11,
.active_low = 1,
}, {
.desc = "key32",
.code = KEY_F10,
.active_low = 1,
}, {
.desc = "key31",
.code = KEY_F9,
.active_low = 1,
}, {
.desc = "key24",
.code = KEY_F8,
.active_low = 1,
}, {
.desc = "key23",
.code = KEY_F7,
.active_low = 1,
}, {
.desc = "key22",
.code = KEY_F6,
.active_low = 1,
}, {
.desc = "key21",
.code = KEY_F5,
.active_low = 1,
}, {
.desc = "key14",
.code = KEY_F4,
.active_low = 1,
}, {
.desc = "key13",
.code = KEY_F3,
.active_low = 1,
}, {
.desc = "key12",
.code = KEY_F2,
.active_low = 1,
}, {
.desc = "key11",
.code = KEY_F1,
.active_low = 1,
},
};
static struct gpio_keys_platform_data baseboard_buttons_data = {
.buttons = baseboard_buttons,
.nbuttons = ARRAY_SIZE(baseboard_buttons),
};
static struct platform_device baseboard_buttons_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &baseboard_buttons_data,
},
};
static struct platform_device *x3proto_devices[] __initdata = {
&heartbeat_device,
&smc91x_device,
&r8a66597_usb_host_device,
&m66592_usb_peripheral_device,
&baseboard_buttons_device,
};
static void __init x3proto_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRL3210);
/* Set ICR0.LVLMODE */
__raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
}
static int __init x3proto_devices_setup(void)
{
int ret, i;
/*
* IRLs are only needed for ILSEL mappings, so flip over the INTC
* pins at a later point to enable the GPIOs to settle.
*/
x3proto_init_irq();
/*
* Now that ILSELs are available, set up the baseboard GPIOs.
*/
ret = x3proto_gpio_setup();
if (unlikely(ret))
return ret;
/*
* Propagate dynamic GPIOs for the baseboard button device.
*/
for (i = 0; i < ARRAY_SIZE(baseboard_buttons); i++)
baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i;
r8a66597_usb_host_resources[1].start =
r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I);
m66592_usb_peripheral_resources[1].start =
m66592_usb_peripheral_resources[1].end = ilsel_enable(ILSEL_USBP_I);
smc91x_resources[1].start =
smc91x_resources[1].end = ilsel_enable(ILSEL_LAN);
return platform_add_devices(x3proto_devices,
ARRAY_SIZE(x3proto_devices));
}
device_initcall(x3proto_devices_setup);
static void __init x3proto_setup(char **cmdline_p)
{
register_smp_ops(&shx3_smp_ops);
}
static struct sh_machine_vector mv_x3proto __initmv = {
.mv_name = "x3proto",
.mv_setup = x3proto_setup,
};
| linux-master | arch/sh/boards/mach-x3proto/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/boards/mach-x3proto/ilsel.c
*
* Helper routines for SH-X3 proto board ILSEL.
*
* Copyright (C) 2007 - 2010 Paul Mundt
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/bitmap.h>
#include <linux/io.h>
#include <mach/ilsel.h>
/*
* ILSEL is split across:
*
* ILSEL0 - 0xb8100004 [ Levels 1 - 4 ]
* ILSEL1 - 0xb8100006 [ Levels 5 - 8 ]
* ILSEL2 - 0xb8100008 [ Levels 9 - 12 ]
* ILSEL3 - 0xb810000a [ Levels 13 - 15 ]
*
* With each level being relative to an ilsel_source_t.
*/
#define ILSEL_BASE 0xb8100004
#define ILSEL_LEVELS 15
/*
* ILSEL level map, in descending order from the highest level down.
*
* Supported levels are 1 - 15 spread across ILSEL0 - ILSEL4, mapping
* directly to IRLs. As the IRQs are numbered in reverse order relative
* to the interrupt level, the level map is carefully managed to ensure a
* 1:1 mapping between the bit position and the IRQ number.
*
* This careful constructions allows ilsel_enable*() to be referenced
* directly for hooking up an ILSEL set and getting back an IRQ which can
* subsequently be used for internal accounting in the (optional) disable
* path.
*/
static unsigned long ilsel_level_map;
static inline unsigned int ilsel_offset(unsigned int bit)
{
return ILSEL_LEVELS - bit - 1;
}
static inline unsigned long mk_ilsel_addr(unsigned int bit)
{
return ILSEL_BASE + ((ilsel_offset(bit) >> 1) & ~0x1);
}
static inline unsigned int mk_ilsel_shift(unsigned int bit)
{
return (ilsel_offset(bit) & 0x3) << 2;
}
static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
{
unsigned int tmp, shift;
unsigned long addr;
pr_notice("enabling ILSEL set %d\n", set);
addr = mk_ilsel_addr(bit);
shift = mk_ilsel_shift(bit);
pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n",
__func__, bit, addr, shift, set);
tmp = __raw_readw(addr);
tmp &= ~(0xf << shift);
tmp |= set << shift;
__raw_writew(tmp, addr);
}
/**
* ilsel_enable - Enable an ILSEL set.
* @set: ILSEL source (see ilsel_source_t enum in include/asm-sh/ilsel.h).
*
* Enables a given non-aliased ILSEL source (<= ILSEL_KEY) at the highest
* available interrupt level. Callers should take care to order callsites
* noting descending interrupt levels. Aliasing FPGA and external board
* IRQs need to use ilsel_enable_fixed().
*
* The return value is an IRQ number that can later be taken down with
* ilsel_disable().
*/
int ilsel_enable(ilsel_source_t set)
{
unsigned int bit;
if (unlikely(set > ILSEL_KEY)) {
pr_err("Aliased sources must use ilsel_enable_fixed()\n");
return -EINVAL;
}
do {
bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS);
} while (test_and_set_bit(bit, &ilsel_level_map));
__ilsel_enable(set, bit);
return bit;
}
EXPORT_SYMBOL_GPL(ilsel_enable);
/**
* ilsel_enable_fixed - Enable an ILSEL set at a fixed interrupt level
* @set: ILSEL source (see ilsel_source_t enum in include/asm-sh/ilsel.h).
* @level: Interrupt level (1 - 15)
*
* Enables a given ILSEL source at a fixed interrupt level. Necessary
* both for level reservation as well as for aliased sources that only
* exist on special ILSEL#s.
*
* Returns an IRQ number (as ilsel_enable()).
*/
int ilsel_enable_fixed(ilsel_source_t set, unsigned int level)
{
unsigned int bit = ilsel_offset(level - 1);
if (test_and_set_bit(bit, &ilsel_level_map))
return -EBUSY;
__ilsel_enable(set, bit);
return bit;
}
EXPORT_SYMBOL_GPL(ilsel_enable_fixed);
/**
* ilsel_disable - Disable an ILSEL set
* @irq: Bit position for ILSEL set value (retval from enable routines)
*
* Disable a previously enabled ILSEL set.
*/
void ilsel_disable(unsigned int irq)
{
unsigned long addr;
unsigned int tmp;
pr_notice("disabling ILSEL set %d\n", irq);
addr = mk_ilsel_addr(irq);
tmp = __raw_readw(addr);
tmp &= ~(0xf << mk_ilsel_shift(irq));
__raw_writew(tmp, addr);
clear_bit(irq, &ilsel_level_map);
}
EXPORT_SYMBOL_GPL(ilsel_disable);
| linux-master | arch/sh/boards/mach-x3proto/ilsel.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SDK7786 FPGA SRAM Support.
*
* Copyright (C) 2010 Paul Mundt
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/string.h>
#include <mach/fpga.h>
#include <asm/sram.h>
#include <linux/sizes.h>
static int __init fpga_sram_init(void)
{
unsigned long phys;
unsigned int area;
void __iomem *vaddr;
int ret;
u16 data;
/* Enable FPGA SRAM */
data = fpga_read_reg(LCLASR);
data |= LCLASR_FRAMEN;
fpga_write_reg(data, LCLASR);
/*
* FPGA_SEL determines the area mapping
*/
area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
if (unlikely(area == LCLASR_AREA_MASK)) {
pr_err("FPGA memory unmapped.\n");
return -ENXIO;
}
/*
* The memory itself occupies a 2KiB range at the top of the area
* immediately below the system registers.
*/
phys = (area << 26) + SZ_64M - SZ_4K;
/*
* The FPGA SRAM resides in translatable physical space, so set
* up a mapping prior to inserting it in to the pool.
*/
vaddr = ioremap(phys, SZ_2K);
if (unlikely(!vaddr)) {
pr_err("Failed remapping FPGA memory.\n");
return -ENXIO;
}
pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
"(area %d) to pool.\n",
SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
if (unlikely(ret < 0)) {
pr_err("Failed adding memory\n");
iounmap(vaddr);
return ret;
}
return 0;
}
postcore_initcall(fpga_sram_init);
| linux-master | arch/sh/boards/mach-sdk7786/sram.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SDK7786 FPGA IRQ Controller Support.
*
* Copyright (C) 2010 Matt Fleming
* Copyright (C) 2010 Paul Mundt
*/
#include <linux/irq.h>
#include <mach/fpga.h>
#include <mach/irq.h>
enum {
ATA_IRQ_BIT = 1,
SPI_BUSY_BIT = 2,
LIRQ5_BIT = 3,
LIRQ6_BIT = 4,
LIRQ7_BIT = 5,
LIRQ8_BIT = 6,
KEY_IRQ_BIT = 7,
PEN_IRQ_BIT = 8,
ETH_IRQ_BIT = 9,
RTC_ALARM_BIT = 10,
CRYSTAL_FAIL_BIT = 12,
ETH_PME_BIT = 14,
};
void __init sdk7786_init_irq(void)
{
unsigned int tmp;
/* Enable priority encoding for all IRLs */
fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
/* Clear FPGA interrupt status registers */
fpga_write_reg(0x0000, INTASR);
fpga_write_reg(0x0000, INTBSR);
/* Unmask FPGA interrupts */
tmp = fpga_read_reg(INTAMR);
tmp &= ~(1 << ETH_IRQ_BIT);
fpga_write_reg(tmp, INTAMR);
plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
}
| linux-master | arch/sh/boards/mach-sdk7786/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SDK7786 FPGA USRGPIR Support.
*
* Copyright (C) 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <mach/fpga.h>
#define NR_FPGA_GPIOS 8
static const char *usrgpir_gpio_names[NR_FPGA_GPIOS] = {
"in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7",
};
static int usrgpir_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
/* always in */
return 0;
}
static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
return !!(fpga_read_reg(USRGPIR) & (1 << gpio));
}
static struct gpio_chip usrgpir_gpio_chip = {
.label = "sdk7786-fpga",
.names = usrgpir_gpio_names,
.direction_input = usrgpir_gpio_direction_input,
.get = usrgpir_gpio_get,
.base = -1, /* don't care */
.ngpio = NR_FPGA_GPIOS,
};
static int __init usrgpir_gpio_setup(void)
{
return gpiochip_add_data(&usrgpir_gpio_chip, NULL);
}
device_initcall(usrgpir_gpio_setup);
| linux-master | arch/sh/boards/mach-sdk7786/gpio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SDK7786 FPGA Support.
*
* Copyright (C) 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bcd.h>
#include <mach/fpga.h>
#include <linux/sizes.h>
#define FPGA_REGS_OFFSET 0x03fff800
#define FPGA_REGS_SIZE 0x490
/*
* The FPGA can be mapped in any of the generally available areas,
* so we attempt to scan for it using the fixed SRSTR read magic.
*
* Once the FPGA is located, the rest of the mapping data for the other
* components can be determined dynamically from its section mapping
* registers.
*/
static void __iomem *sdk7786_fpga_probe(void)
{
unsigned long area;
void __iomem *base;
/*
* Iterate over all of the areas where the FPGA could be mapped.
* The possible range is anywhere from area 0 through 6, area 7
* is reserved.
*/
for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
base = ioremap(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
if (!base) {
/* Failed to remap this area, move along. */
continue;
}
if (ioread16(base + SRSTR) == SRSTR_MAGIC)
return base; /* Found it! */
iounmap(base);
}
return NULL;
}
void __iomem *sdk7786_fpga_base;
void __init sdk7786_fpga_init(void)
{
u16 version, date;
sdk7786_fpga_base = sdk7786_fpga_probe();
if (unlikely(!sdk7786_fpga_base)) {
panic("FPGA detection failed.\n");
return;
}
version = fpga_read_reg(FPGAVR);
date = fpga_read_reg(FPGADR);
pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
((date >> 12) & 0xf) + 2000,
(date >> 8) & 0xf, bcd2bin(date & 0xff));
}
| linux-master | arch/sh/boards/mach-sdk7786/fpga.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Technology Europe SDK7786 Support.
*
* Copyright (C) 2010 Matt Fleming
* Copyright (C) 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <mach/fpga.h>
#include <mach/irq.h>
#include <asm/machvec.h>
#include <asm/heartbeat.h>
#include <linux/sizes.h>
#include <asm/clock.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
static struct resource heartbeat_resource = {
.start = 0x07fff8b0,
.end = 0x07fff8b0 + sizeof(u16) - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};
static struct resource smsc911x_resources[] = {
[0] = {
.name = "smsc911x-memory",
.start = 0x07ffff00,
.end = 0x07ffff00 + SZ_256 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "smsc911x-irq",
.start = evt2irq(0x2c0),
.end = evt2irq(0x2c0),
.flags = IORESOURCE_IRQ,
},
};
static struct smsc911x_platform_config smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_32BIT,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct resource smbus_fpga_resource = {
.start = 0x07fff9e0,
.end = 0x07fff9e0 + SZ_32 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device smbus_fpga_device = {
.name = "i2c-sdk7786",
.id = 0,
.num_resources = 1,
.resource = &smbus_fpga_resource,
};
static struct resource smbus_pcie_resource = {
.start = 0x07fffc30,
.end = 0x07fffc30 + SZ_32 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device smbus_pcie_device = {
.name = "i2c-sdk7786",
.id = 1,
.num_resources = 1,
.resource = &smbus_pcie_resource,
};
static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
{
I2C_BOARD_INFO("max6900", 0x68),
},
};
static struct platform_device *sh7786_devices[] __initdata = {
&heartbeat_device,
&smsc911x_device,
&smbus_fpga_device,
&smbus_pcie_device,
};
static int sdk7786_i2c_setup(void)
{
unsigned int tmp;
/*
* Hand over I2C control to the FPGA.
*/
tmp = fpga_read_reg(SBCR);
tmp &= ~SCBR_I2CCEN;
tmp |= SCBR_I2CMEN;
fpga_write_reg(tmp, SBCR);
return i2c_register_board_info(0, sdk7786_i2c_devices,
ARRAY_SIZE(sdk7786_i2c_devices));
}
static int __init sdk7786_devices_setup(void)
{
int ret;
ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
if (unlikely(ret != 0))
return ret;
return sdk7786_i2c_setup();
}
device_initcall(sdk7786_devices_setup);
static int sdk7786_mode_pins(void)
{
return fpga_read_reg(MODSWR);
}
/*
* FPGA-driven PCIe clocks
*
* Historically these include the oscillator, clock B (slots 2/3/4) and
* clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
* everything under a single PCIe clocks enable bit that happens to map
* to the same bit position as the oscillator bit for earlier FPGA
* versions.
*
* Given that the legacy clocks have the side-effect of shutting the CPU
* off through the FPGA along with the PCI slots, we simply leave them in
* their initial state and don't bother registering them with the clock
* framework.
*/
static int sdk7786_pcie_clk_enable(struct clk *clk)
{
fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
return 0;
}
static void sdk7786_pcie_clk_disable(struct clk *clk)
{
fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
}
static struct sh_clk_ops sdk7786_pcie_clk_ops = {
.enable = sdk7786_pcie_clk_enable,
.disable = sdk7786_pcie_clk_disable,
};
static struct clk sdk7786_pcie_clk = {
.ops = &sdk7786_pcie_clk_ops,
};
static struct clk_lookup sdk7786_pcie_cl = {
.con_id = "pcie_plat_clk",
.clk = &sdk7786_pcie_clk,
};
static int sdk7786_clk_init(void)
{
struct clk *clk;
int ret;
/*
* Only handle the EXTAL case, anyone interfacing a crystal
* resonator will need to provide their own input clock.
*/
if (test_mode_pin(MODE_PIN9))
return -EINVAL;
clk = clk_get(NULL, "extal");
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
/*
* Setup the FPGA clocks.
*/
ret = clk_register(&sdk7786_pcie_clk);
if (unlikely(ret)) {
pr_err("FPGA clock registration failed\n");
return ret;
}
clkdev_add(&sdk7786_pcie_cl);
return 0;
}
static void sdk7786_restart(char *cmd)
{
fpga_write_reg(0xa5a5, SRSTR);
}
static void sdk7786_power_off(void)
{
fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
/*
* It can take up to 20us for the R8C to do its job, back off and
* wait a bit until we've been shut off. Even though newer FPGA
* versions don't set the ACK bit, the latency issue remains.
*/
while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
cpu_sleep();
}
/* Initialize the board */
static void __init sdk7786_setup(char **cmdline_p)
{
pr_info("Renesas Technology Europe SDK7786 support:\n");
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
sdk7786_fpga_init();
sdk7786_nmi_init();
pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
machine_ops.restart = sdk7786_restart;
pm_power_off = sdk7786_power_off;
register_smp_ops(&shx3_smp_ops);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_sdk7786 __initmv = {
.mv_name = "SDK7786",
.mv_setup = sdk7786_setup,
.mv_mode_pins = sdk7786_mode_pins,
.mv_clk_init = sdk7786_clk_init,
.mv_init_irq = sdk7786_init_irq,
};
| linux-master | arch/sh/boards/mach-sdk7786/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SDK7786 FPGA NMI Support.
*
* Copyright (C) 2010 Paul Mundt
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <mach/fpga.h>
enum {
NMI_MODE_MANUAL,
NMI_MODE_AUX,
NMI_MODE_MASKED,
NMI_MODE_ANY,
NMI_MODE_UNKNOWN,
};
/*
* Default to the manual NMI switch.
*/
static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
static int __init nmi_mode_setup(char *str)
{
if (!str)
return 0;
if (strcmp(str, "manual") == 0)
nmi_mode = NMI_MODE_MANUAL;
else if (strcmp(str, "aux") == 0)
nmi_mode = NMI_MODE_AUX;
else if (strcmp(str, "masked") == 0)
nmi_mode = NMI_MODE_MASKED;
else if (strcmp(str, "any") == 0)
nmi_mode = NMI_MODE_ANY;
else {
nmi_mode = NMI_MODE_UNKNOWN;
pr_warn("Unknown NMI mode %s\n", str);
}
printk("Set NMI mode to %d\n", nmi_mode);
return 0;
}
early_param("nmi_mode", nmi_mode_setup);
void __init sdk7786_nmi_init(void)
{
unsigned int source, mask, tmp;
switch (nmi_mode) {
case NMI_MODE_MANUAL:
source = NMISR_MAN_NMI;
mask = NMIMR_MAN_NMIM;
break;
case NMI_MODE_AUX:
source = NMISR_AUX_NMI;
mask = NMIMR_AUX_NMIM;
break;
case NMI_MODE_ANY:
source = NMISR_MAN_NMI | NMISR_AUX_NMI;
mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
break;
case NMI_MODE_MASKED:
case NMI_MODE_UNKNOWN:
default:
source = mask = 0;
break;
}
/* Set the NMI source */
tmp = fpga_read_reg(NMISR);
tmp &= ~NMISR_MASK;
tmp |= source;
fpga_write_reg(tmp, NMISR);
/* And the IRQ masking */
fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
}
| linux-master | arch/sh/boards/mach-sdk7786/nmi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/boards/renesas/rts7751r2d/irq.c
*
* Copyright (C) 2007 Magnus Damm
* Copyright (C) 2000 Kazumoto Kojima
*
* Renesas Technology Sales RTS7751R2D Support, R2D-PLUS and R2D-1.
*
* Modified for RTS7751R2D by
* Atom Create Engineering Co., Ltd. 2002.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/r2d.h>
#define R2D_NR_IRL 13
enum {
UNUSED = 0,
/* board specific interrupt sources (R2D-1 and R2D-PLUS) */
EXT, /* EXT_INT0-3 */
RTC_T, RTC_A, /* Real Time Clock */
AX88796, /* Ethernet controller (R2D-1 board) */
KEY, /* Key input (R2D-PLUS board) */
SDCARD, /* SD Card */
CF_CD, CF_IDE, /* CF Card Detect + CF IDE */
SM501, /* SM501 aka Voyager */
PCI_INTD_RTL8139, /* Ethernet controller */
PCI_INTC_PCI1520, /* Cardbus/PCMCIA bridge */
PCI_INTB_RTL8139, /* Ethernet controller with HUB (R2D-PLUS board) */
PCI_INTB_SLOT, /* PCI Slot 3.3v (R2D-1 board) */
PCI_INTA_SLOT, /* PCI Slot 3.3v */
TP, /* Touch Panel */
};
#ifdef CONFIG_RTS7751R2D_1
/* Vectors for R2D-1 */
static struct intc_vect vectors_r2d_1[] __initdata = {
INTC_IRQ(EXT, IRQ_EXT),
INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
INTC_IRQ(AX88796, IRQ_AX88796), INTC_IRQ(SDCARD, IRQ_SDCARD),
INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE), /* ng */
INTC_IRQ(SM501, IRQ_VOYAGER),
INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
INTC_IRQ(PCI_INTB_SLOT, IRQ_PCI_INTB),
INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
INTC_IRQ(TP, IRQ_TP),
};
/* IRLMSK mask register layout for R2D-1 */
static struct intc_mask_reg mask_registers_r2d_1[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ TP, PCI_INTA_SLOT, PCI_INTB_SLOT,
PCI_INTC_PCI1520, PCI_INTD_RTL8139,
SM501, CF_IDE, CF_CD, SDCARD, AX88796,
RTC_A, RTC_T, 0, 0, 0, EXT } },
};
/* IRLn to IRQ table for R2D-1 */
static unsigned char irl2irq_r2d_1[R2D_NR_IRL] __initdata = {
IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
IRQ_VOYAGER, IRQ_AX88796, IRQ_RTC_A, IRQ_RTC_T,
IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
IRQ_TP,
};
static DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1", vectors_r2d_1,
NULL, mask_registers_r2d_1, NULL, NULL);
#endif /* CONFIG_RTS7751R2D_1 */
#ifdef CONFIG_RTS7751R2D_PLUS
/* Vectors for R2D-PLUS */
static struct intc_vect vectors_r2d_plus[] __initdata = {
INTC_IRQ(EXT, IRQ_EXT),
INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
INTC_IRQ(KEY, IRQ_KEY), INTC_IRQ(SDCARD, IRQ_SDCARD),
INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE),
INTC_IRQ(SM501, IRQ_VOYAGER),
INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
INTC_IRQ(PCI_INTB_RTL8139, IRQ_PCI_INTB),
INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
INTC_IRQ(TP, IRQ_TP),
};
/* IRLMSK mask register layout for R2D-PLUS */
static struct intc_mask_reg mask_registers_r2d_plus[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ TP, PCI_INTA_SLOT, PCI_INTB_RTL8139,
PCI_INTC_PCI1520, PCI_INTD_RTL8139,
SM501, CF_IDE, CF_CD, SDCARD, KEY,
RTC_A, RTC_T, 0, 0, 0, EXT } },
};
/* IRLn to IRQ table for R2D-PLUS */
static unsigned char irl2irq_r2d_plus[R2D_NR_IRL] __initdata = {
IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
IRQ_VOYAGER, IRQ_KEY, IRQ_RTC_A, IRQ_RTC_T,
IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
IRQ_TP,
};
static DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus", vectors_r2d_plus,
NULL, mask_registers_r2d_plus, NULL, NULL);
#endif /* CONFIG_RTS7751R2D_PLUS */
static unsigned char irl2irq[R2D_NR_IRL];
int rts7751r2d_irq_demux(int irq)
{
if (irq >= R2D_NR_IRL + 16 || irq < 16 || !irl2irq[irq - 16])
return irq;
return irl2irq[irq - 16];
}
/*
* Initialize IRQ setting
*/
void __init init_rts7751r2d_IRQ(void)
{
struct intc_desc *d;
switch (__raw_readw(PA_VERREG) & 0xf0) {
#ifdef CONFIG_RTS7751R2D_PLUS
case 0x10:
printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
d = &intc_desc_r2d_plus;
memcpy(irl2irq, irl2irq_r2d_plus, R2D_NR_IRL);
break;
#endif
#ifdef CONFIG_RTS7751R2D_1
case 0x00: /* according to manual */
case 0x30: /* in reality */
printk(KERN_INFO "Using R2D-1 interrupt controller.\n");
d = &intc_desc_r2d_1;
memcpy(irl2irq, irl2irq_r2d_1, R2D_NR_IRL);
break;
#endif
default:
printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n",
__raw_readw(PA_VERREG));
return;
}
register_intc_controller(d);
}
| linux-master | arch/sh/boards/mach-r2d/irq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Technology Sales RTS7751R2D Support.
*
* Copyright (C) 2002 - 2006 Atom Create Engineering Co., Ltd.
* Copyright (C) 2004 - 2007 Paul Mundt
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/ata_platform.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>
#include <linux/pm.h>
#include <linux/fb.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <asm/machvec.h>
#include <mach/r2d.h>
#include <asm/io.h>
#include <asm/io_trapped.h>
#include <asm/spi.h>
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_AREA5_IO + 0x1000,
.end = PA_AREA5_IO + 0x1000 + 0x10 - 0x2,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PA_AREA5_IO + 0x80c,
.end = PA_AREA5_IO + 0x80c,
.flags = IORESOURCE_MEM,
},
#ifndef CONFIG_RTS7751R2D_1 /* For R2D-1 polling is preferred */
[2] = {
.start = IRQ_CF_IDE,
.flags = IORESOURCE_IRQ,
},
#endif
};
static struct pata_platform_info pata_info = {
.ioport_shift = 1,
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
.dev = {
.platform_data = &pata_info,
},
};
static struct spi_board_info spi_bus[] = {
{
.modalias = "rtc-r9701",
.max_speed_hz = 1000000,
.mode = SPI_MODE_3,
},
};
static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state)
{
BUG_ON(cs != 0); /* Single Epson RTC-9701JE attached on CS0 */
__raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
}
static struct sh_spi_info spi_info = {
.num_chipselect = 1,
.chip_select = r2d_chip_select,
};
static struct resource spi_sh_sci_resources[] = {
{
.start = 0xffe00000,
.end = 0xffe0001f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device spi_sh_sci_device = {
.name = "spi_sh_sci",
.id = -1,
.num_resources = ARRAY_SIZE(spi_sh_sci_resources),
.resource = spi_sh_sci_resources,
.dev = {
.platform_data = &spi_info,
},
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_OUTPORT,
.end = PA_OUTPORT,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct resource sm501_resources[] = {
[0] = {
.start = 0x10000000,
.end = 0x13e00000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x13e00000,
.end = 0x13ffffff,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_VOYAGER,
.flags = IORESOURCE_IRQ,
},
};
static struct fb_videomode sm501_default_mode = {
.pixclock = 35714,
.xres = 640,
.yres = 480,
.left_margin = 105,
.right_margin = 50,
.upper_margin = 35,
.lower_margin = 0,
.hsync_len = 96,
.vsync_len = 2,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};
static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
.def_bpp = 16,
.def_mode = &sm501_default_mode,
.flags = SM501FB_FLAG_USE_INIT_MODE |
SM501FB_FLAG_USE_HWCURSOR |
SM501FB_FLAG_USE_HWACCEL |
SM501FB_FLAG_DISABLE_AT_EXIT,
};
static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
.flags = (SM501FB_FLAG_USE_INIT_MODE |
SM501FB_FLAG_USE_HWCURSOR |
SM501FB_FLAG_USE_HWACCEL |
SM501FB_FLAG_DISABLE_AT_EXIT),
};
static struct sm501_platdata_fb sm501_fb_pdata = {
.fb_route = SM501_FB_OWN,
.fb_crt = &sm501_pdata_fbsub_crt,
.fb_pnl = &sm501_pdata_fbsub_pnl,
.flags = SM501_FBPD_SWAP_FB_ENDIAN,
};
static struct sm501_initdata sm501_initdata = {
.devices = SM501_USE_USB_HOST | SM501_USE_UART0,
};
static struct sm501_platdata sm501_platform_data = {
.init = &sm501_initdata,
.fb = &sm501_fb_pdata,
};
static struct platform_device sm501_device = {
.name = "sm501",
.id = -1,
.dev = {
.platform_data = &sm501_platform_data,
},
.num_resources = ARRAY_SIZE(sm501_resources),
.resource = sm501_resources,
};
static struct mtd_partition r2d_partitions[] = {
{
.name = "U-Boot",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Environment",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x001c0000,
}, {
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(r2d_partitions),
.parts = r2d_partitions,
};
static struct resource flash_resource = {
.start = 0x00000000,
.end = 0x02000000,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device *rts7751r2d_devices[] __initdata = {
&sm501_device,
&heartbeat_device,
&spi_sh_sci_device,
};
/*
* The CF is connected with a 16-bit bus where 8-bit operations are
* unsupported. The linux ata driver is however using 8-bit operations, so
* insert a trapped io filter to convert 8-bit operations into 16-bit.
*/
static struct trapped_io cf_trapped_io = {
.resource = cf_ide_resources,
.num_resources = 2,
.minimum_bus_width = 16,
};
static int __init rts7751r2d_devices_setup(void)
{
if (register_trapped_io(&cf_trapped_io) == 0)
platform_device_register(&cf_ide_device);
if (mach_is_r2d_plus())
platform_device_register(&flash_device);
spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
return platform_add_devices(rts7751r2d_devices,
ARRAY_SIZE(rts7751r2d_devices));
}
device_initcall(rts7751r2d_devices_setup);
static void rts7751r2d_power_off(void)
{
__raw_writew(0x0001, PA_POWOFF);
}
/*
* Initialize the board
*/
static void __init rts7751r2d_setup(char **cmdline_p)
{
void __iomem *sm501_reg;
u16 ver = __raw_readw(PA_VERREG);
printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
printk(KERN_INFO "FPGA version:%d (revision:%d)\n",
(ver >> 4) & 0xf, ver & 0xf);
__raw_writew(0x0000, PA_OUTPORT);
pm_power_off = rts7751r2d_power_off;
/* sm501 dram configuration:
* ColSizeX = 11 - External Memory Column Size: 256 words.
* APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks.
* RstX = 1 - External Memory Reset: Normal.
* Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks.
* BwC = 1 - Local Memory Block Write Cycle Time: 2 clocks.
* BwP = 1 - Local Memory Block Write to Pre-Charge Delay: 1 clock.
* AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks.
* Rst = 1 - Internal Memory Reset: Normal.
* RA = 1 - Internal Memory Remain in Active State: Do not remain.
*/
sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
writel(readl(sm501_reg) | 0x00f107c0, sm501_reg);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_rts7751r2d __initmv = {
.mv_name = "RTS7751R2D",
.mv_setup = rts7751r2d_setup,
.mv_init_irq = init_rts7751r2d_IRQ,
.mv_irq_demux = rts7751r2d_irq_demux,
};
| linux-master | arch/sh/boards/mach-r2d/setup.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/lib/io.c - SH32 optimized I/O routines
*
* Copyright (C) 2000 Stuart Menefy
* Copyright (C) 2005 Paul Mundt
*
* Provide real functions which expand to whatever the header file defined.
* Also definitions of machine independent IO functions.
*/
#include <linux/module.h>
#include <linux/io.h>
void __raw_readsl(const void __iomem *addr, void *datap, int len)
{
u32 *data;
for (data = datap; (len != 0) && (((u32)data & 0x1f) != 0); len--)
*data++ = __raw_readl(addr);
if (likely(len >= (0x20 >> 2))) {
int tmp2, tmp3, tmp4, tmp5, tmp6;
__asm__ __volatile__(
"1: \n\t"
"mov.l @%7, r0 \n\t"
"mov.l @%7, %2 \n\t"
#ifdef CONFIG_CPU_SH4
"movca.l r0, @%0 \n\t"
#else
"mov.l r0, @%0 \n\t"
#endif
"mov.l @%7, %3 \n\t"
"mov.l @%7, %4 \n\t"
"mov.l @%7, %5 \n\t"
"mov.l @%7, %6 \n\t"
"mov.l @%7, r7 \n\t"
"mov.l @%7, r0 \n\t"
"mov.l %2, @(0x04,%0) \n\t"
"mov #0x20>>2, %2 \n\t"
"mov.l %3, @(0x08,%0) \n\t"
"sub %2, %1 \n\t"
"mov.l %4, @(0x0c,%0) \n\t"
"cmp/hi %1, %2 ! T if 32 > len \n\t"
"mov.l %5, @(0x10,%0) \n\t"
"mov.l %6, @(0x14,%0) \n\t"
"mov.l r7, @(0x18,%0) \n\t"
"mov.l r0, @(0x1c,%0) \n\t"
"bf.s 1b \n\t"
" add #0x20, %0 \n\t"
: "=&r" (data), "=&r" (len),
"=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4),
"=&r" (tmp5), "=&r" (tmp6)
: "r"(addr), "0" (data), "1" (len)
: "r0", "r7", "t", "memory");
}
for (; len != 0; len--)
*data++ = __raw_readl(addr);
}
EXPORT_SYMBOL(__raw_readsl);
void __raw_writesl(void __iomem *addr, const void *data, int len)
{
if (likely(len != 0)) {
int tmp1;
__asm__ __volatile__ (
"1: \n\t"
"mov.l @%0+, %1 \n\t"
"dt %3 \n\t"
"bf.s 1b \n\t"
" mov.l %1, @%4 \n\t"
: "=&r" (data), "=&r" (tmp1)
: "0" (data), "r" (len), "r"(addr)
: "t", "memory");
}
}
EXPORT_SYMBOL(__raw_writesl);
| linux-master | arch/sh/lib/io.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Precise Delay Loops for SuperH
*
* Copyright (C) 1999 Niibe Yutaka & Kaz Kojima
*/
#include <linux/sched.h>
#include <linux/delay.h>
void __delay(unsigned long loops)
{
__asm__ __volatile__(
/*
* ST40-300 appears to have an issue with this code,
* normally taking two cycles each loop, as with all
* other SH variants. If however the branch and the
* delay slot straddle an 8 byte boundary, this increases
* to 3 cycles.
* This align directive ensures this doesn't occur.
*/
".balign 8\n\t"
"tst %0, %0\n\t"
"1:\t"
"bf/s 1b\n\t"
" dt %0"
: "=r" (loops)
: "0" (loops)
: "t");
}
inline void __const_udelay(unsigned long xloops)
{
xloops *= 4;
__asm__("dmulu.l %0, %2\n\t"
"sts mach, %0"
: "=r" (xloops)
: "0" (xloops),
"r" (cpu_data[raw_smp_processor_id()].loops_per_jiffy * (HZ/4))
: "macl", "mach");
__delay(++xloops);
}
void __udelay(unsigned long usecs)
{
__const_udelay(usecs * 0x000010c6); /* 2**32 / 1000000 */
}
void __ndelay(unsigned long nsecs)
{
__const_udelay(nsecs * 0x00000005);
}
| linux-master | arch/sh/lib/delay.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Generic __div64_32 wrapper for __xdiv64_32.
*/
#include <linux/types.h>
#include <asm/div64.h>
extern uint64_t __xdiv64_32(u64 n, u32 d);
uint32_t __div64_32(u64 *xp, u32 y)
{
uint32_t rem;
uint64_t q = __xdiv64_32(*xp, y);
rem = *xp - q * y;
*xp = q;
return rem;
}
| linux-master | arch/sh/lib/div64-generic.c |
/*
* SRAM pool for tiny memories not otherwise managed.
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <asm/sram.h>
/*
* This provides a standard SRAM pool for tiny memories that can be
* added either by the CPU or the platform code. Typical SRAM sizes
* to be inserted in to the pool will generally be less than the page
* size, with anything more reasonably sized handled as a NUMA memory
* node.
*/
struct gen_pool *sram_pool;
static int __init sram_pool_init(void)
{
/*
* This is a global pool, we don't care about node locality.
*/
sram_pool = gen_pool_create(1, -1);
if (unlikely(!sram_pool))
return -ENOMEM;
return 0;
}
core_initcall(sram_pool_init);
| linux-master | arch/sh/mm/sram.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/kmap.c
*
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
* Copyright (C) 2002 - 2009 Paul Mundt
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
static pte_t *kmap_coherent_pte;
void __init kmap_coherent_init(void)
{
unsigned long vaddr;
/* cache the first coherent kmap pte */
vaddr = __fix_to_virt(FIX_CMAP_BEGIN);
kmap_coherent_pte = virt_to_kpte(vaddr);
}
void *kmap_coherent(struct page *page, unsigned long addr)
{
struct folio *folio = page_folio(page);
enum fixed_addresses idx;
unsigned long vaddr;
BUG_ON(!test_bit(PG_dcache_clean, &folio->flags));
preempt_disable();
pagefault_disable();
idx = FIX_CMAP_END -
(((addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1)) +
(FIX_N_COLOURS * smp_processor_id()));
vaddr = __fix_to_virt(idx);
BUG_ON(!pte_none(*(kmap_coherent_pte - idx)));
set_pte(kmap_coherent_pte - idx, mk_pte(page, PAGE_KERNEL));
return (void *)vaddr;
}
void kunmap_coherent(void *kvaddr)
{
if (kvaddr >= (void *)FIXADDR_START) {
unsigned long vaddr = (unsigned long)kvaddr & PAGE_MASK;
enum fixed_addresses idx = __virt_to_fix(vaddr);
/* XXX.. Kill this later, here for sanity at the moment.. */
__flush_purge_region((void *)vaddr, PAGE_SIZE);
pte_clear(&init_mm, vaddr, kmap_coherent_pte - idx);
local_flush_tlb_one(get_asid(), vaddr);
}
pagefault_enable();
preempt_enable();
}
| linux-master | arch/sh/mm/kmap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* arch/sh/mm/hugetlbpage.c
*
* SuperH HugeTLB page support.
*
* Cloned from sparc64 by Paul Mundt.
*
* Copyright (C) 2002, 2003 David S. Miller ([email protected])
*/
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/pagemap.h>
#include <linux/sysctl.h>
#include <asm/mman.h>
#include <asm/tlb.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte = NULL;
pgd = pgd_offset(mm, addr);
if (pgd) {
p4d = p4d_alloc(mm, pgd, addr);
if (p4d) {
pud = pud_alloc(mm, p4d, addr);
if (pud) {
pmd = pmd_alloc(mm, pud, addr);
if (pmd)
pte = pte_alloc_huge(mm, pmd, addr);
}
}
}
return pte;
}
pte_t *huge_pte_offset(struct mm_struct *mm,
unsigned long addr, unsigned long sz)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte = NULL;
pgd = pgd_offset(mm, addr);
if (pgd) {
p4d = p4d_offset(pgd, addr);
if (p4d) {
pud = pud_offset(p4d, addr);
if (pud) {
pmd = pmd_offset(pud, addr);
if (pmd)
pte = pte_offset_huge(pmd, addr);
}
}
}
return pte;
}
int pmd_huge(pmd_t pmd)
{
return 0;
}
int pud_huge(pud_t pud)
{
return 0;
}
| linux-master | arch/sh/mm/hugetlbpage.c |
/*
* arch/sh/mm/cache-shx3.c - SH-X3 optimized cache ops
*
* Copyright (C) 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/cache.h>
#define CCR_CACHE_SNM 0x40000 /* Hardware-assisted synonym avoidance */
#define CCR_CACHE_IBE 0x1000000 /* ICBI broadcast */
void __init shx3_cache_init(void)
{
unsigned int ccr;
ccr = __raw_readl(SH_CCR);
/*
* If we've got cache aliases, resolve them in hardware.
*/
if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) {
ccr |= CCR_CACHE_SNM;
boot_cpu_data.icache.n_aliases = 0;
boot_cpu_data.dcache.n_aliases = 0;
pr_info("Enabling hardware synonym avoidance\n");
}
#ifdef CONFIG_SMP
/*
* Broadcast I-cache block invalidations by default.
*/
ccr |= CCR_CACHE_IBE;
#endif
writel_uncached(ccr, SH_CCR);
}
| linux-master | arch/sh/mm/cache-shx3.c |
/*
* arch/sh/mm/cache-sh7705.c
*
* Copyright (C) 1999, 2000 Niibe Yutaka
* Copyright (C) 2004 Alex Song
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/init.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/pagemap.h>
#include <linux/threads.h>
#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
/*
* The 32KB cache on the SH7705 suffers from the same synonym problem
* as SH4 CPUs
*/
static inline void cache_wback_all(void)
{
unsigned long ways, waysize, addrstart;
ways = current_cpu_data.dcache.ways;
waysize = current_cpu_data.dcache.sets;
waysize <<= current_cpu_data.dcache.entry_shift;
addrstart = CACHE_OC_ADDRESS_ARRAY;
do {
unsigned long addr;
for (addr = addrstart;
addr < addrstart + waysize;
addr += current_cpu_data.dcache.linesz) {
unsigned long data;
int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
data = __raw_readl(addr);
if ((data & v) == v)
__raw_writel(data & ~v, addr);
}
addrstart += current_cpu_data.dcache.way_incr;
} while (--ways);
}
/*
* Write back the range of D-cache, and purge the I-cache.
*
* Called from kernel/module.c:sys_init_module and routine for a.out format.
*/
static void sh7705_flush_icache_range(void *args)
{
struct flusher_data *data = args;
unsigned long start, end;
start = data->addr1;
end = data->addr2;
__flush_wback_region((void *)start, end - start);
}
/*
* Writeback&Invalidate the D-cache of the page
*/
static void __flush_dcache_page(unsigned long phys)
{
unsigned long ways, waysize, addrstart;
unsigned long flags;
phys |= SH_CACHE_VALID;
/*
* Here, phys is the physical address of the page. We check all the
* tags in the cache for those with the same page number as this page
* (by masking off the lowest 2 bits of the 19-bit tag; these bits are
* derived from the offset within in the 4k page). Matching valid
* entries are invalidated.
*
* Since 2 bits of the cache index are derived from the virtual page
* number, knowing this would reduce the number of cache entries to be
* searched by a factor of 4. However this function exists to deal with
* potential cache aliasing, therefore the optimisation is probably not
* possible.
*/
local_irq_save(flags);
jump_to_uncached();
ways = current_cpu_data.dcache.ways;
waysize = current_cpu_data.dcache.sets;
waysize <<= current_cpu_data.dcache.entry_shift;
addrstart = CACHE_OC_ADDRESS_ARRAY;
do {
unsigned long addr;
for (addr = addrstart;
addr < addrstart + waysize;
addr += current_cpu_data.dcache.linesz) {
unsigned long data;
data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
if (data == phys) {
data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
__raw_writel(data, addr);
}
}
addrstart += current_cpu_data.dcache.way_incr;
} while (--ways);
back_to_cached();
local_irq_restore(flags);
}
/*
* Write back & invalidate the D-cache of the page.
* (To avoid "alias" issues)
*/
static void sh7705_flush_dcache_folio(void *arg)
{
struct folio *folio = arg;
struct address_space *mapping = folio_flush_mapping(folio);
if (mapping && !mapping_mapped(mapping))
clear_bit(PG_dcache_clean, &folio->flags);
else {
unsigned long pfn = folio_pfn(folio);
unsigned int i, nr = folio_nr_pages(folio);
for (i = 0; i < nr; i++)
__flush_dcache_page((pfn + i) * PAGE_SIZE);
}
}
static void sh7705_flush_cache_all(void *args)
{
unsigned long flags;
local_irq_save(flags);
jump_to_uncached();
cache_wback_all();
back_to_cached();
local_irq_restore(flags);
}
/*
* Write back and invalidate I/D-caches for the page.
*
* ADDRESS: Virtual Address (U0 address)
*/
static void sh7705_flush_cache_page(void *args)
{
struct flusher_data *data = args;
unsigned long pfn = data->addr2;
__flush_dcache_page(pfn << PAGE_SHIFT);
}
/*
* This is called when a page-cache page is about to be mapped into a
* user process' address space. It offers an opportunity for a
* port to ensure d-cache/i-cache coherency if necessary.
*
* Not entirely sure why this is necessary on SH3 with 32K cache but
* without it we get occasional "Memory fault" when loading a program.
*/
static void sh7705_flush_icache_folio(void *arg)
{
struct folio *folio = arg;
__flush_purge_region(folio_address(folio), folio_size(folio));
}
void __init sh7705_cache_init(void)
{
local_flush_icache_range = sh7705_flush_icache_range;
local_flush_dcache_folio = sh7705_flush_dcache_folio;
local_flush_cache_all = sh7705_flush_cache_all;
local_flush_cache_mm = sh7705_flush_cache_all;
local_flush_cache_dup_mm = sh7705_flush_cache_all;
local_flush_cache_range = sh7705_flush_cache_all;
local_flush_cache_page = sh7705_flush_cache_page;
local_flush_icache_folio = sh7705_flush_icache_folio;
}
| linux-master | arch/sh/mm/cache-sh7705.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/cache-sh2.c
*
* Copyright (C) 2002 Paul Mundt
* Copyright (C) 2008 Yoshinori Sato
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
static void sh2__flush_wback_region(void *start, int size)
{
unsigned long v;
unsigned long begin, end;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
int way;
for (way = 0; way < 4; way++) {
unsigned long data = __raw_readl(addr | (way << 12));
if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
data &= ~SH_CACHE_UPDATED;
__raw_writel(data, addr | (way << 12));
}
}
}
}
static void sh2__flush_purge_region(void *start, int size)
{
unsigned long v;
unsigned long begin, end;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
for (v = begin; v < end; v+=L1_CACHE_BYTES)
__raw_writel((v & CACHE_PHYSADDR_MASK),
CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
}
static void sh2__flush_invalidate_region(void *start, int size)
{
#ifdef CONFIG_CACHE_WRITEBACK
/*
* SH-2 does not support individual line invalidation, only a
* global invalidate.
*/
unsigned long ccr;
unsigned long flags;
local_irq_save(flags);
jump_to_uncached();
ccr = __raw_readl(SH_CCR);
ccr |= CCR_CACHE_INVALIDATE;
__raw_writel(ccr, SH_CCR);
back_to_cached();
local_irq_restore(flags);
#else
unsigned long v;
unsigned long begin, end;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
for (v = begin; v < end; v+=L1_CACHE_BYTES)
__raw_writel((v & CACHE_PHYSADDR_MASK),
CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
#endif
}
void __init sh2_cache_init(void)
{
__flush_wback_region = sh2__flush_wback_region;
__flush_purge_region = sh2__flush_purge_region;
__flush_invalidate_region = sh2__flush_invalidate_region;
}
| linux-master | arch/sh/mm/cache-sh2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/tlb-sh4.c
*
* SH-4 specific TLB operations
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 - 2007 Paul Mundt
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
unsigned long flags, pteval, vpn;
/*
* Handle debugger faulting in for debugee.
*/
if (vma && current->active_mm != vma->vm_mm)
return;
local_irq_save(flags);
/* Set PTEH register */
vpn = (address & MMU_VPN_MASK) | get_asid();
__raw_writel(vpn, MMU_PTEH);
pteval = pte.pte_low;
/* Set PTEA register */
#ifdef CONFIG_X2TLB
/*
* For the extended mode TLB this is trivial, only the ESZ and
* EPR bits need to be written out to PTEA, with the remainder of
* the protection bits (with the exception of the compat-mode SZ
* and PR bits, which are cleared) being written out in PTEL.
*/
__raw_writel(pte.pte_high, MMU_PTEA);
#else
if (cpu_data->flags & CPU_HAS_PTEA) {
/* The last 3 bits and the first one of pteval contains
* the PTEA timing control and space attribute bits
*/
__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
}
#endif
/* Set PTEL register */
pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_CACHE_WRITETHROUGH
pteval |= _PAGE_WT;
#endif
/* conveniently, we want all the software flags to be 0 anyway */
__raw_writel(pteval, MMU_PTEL);
/* Load the TLB */
asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
local_irq_restore(flags);
}
void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
unsigned long addr, data;
/*
* NOTE: PTEH.ASID should be set to this MM
* _AND_ we need to write ASID to the array.
*
* It would be simple if we didn't need to set PTEH.ASID...
*/
addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
data = page | asid; /* VALID bit is off */
jump_to_uncached();
__raw_writel(data, addr);
back_to_cached();
}
void local_flush_tlb_all(void)
{
unsigned long flags, status;
int i;
/*
* Flush all the TLB.
*/
local_irq_save(flags);
jump_to_uncached();
status = __raw_readl(MMUCR);
status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
if (status == 0)
status = MMUCR_URB_NENTRIES;
for (i = 0; i < status; i++)
__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
for (i = 0; i < 4; i++)
__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
back_to_cached();
ctrl_barrier();
local_irq_restore(flags);
}
| linux-master | arch/sh/mm/tlb-sh4.c |
/*
* debugfs ops for process ASIDs
*
* Copyright (C) 2000, 2001 Paolo Alberelli
* Copyright (C) 2003 - 2008 Paul Mundt
* Copyright (C) 2003, 2004 Richard Curnow
*
* Provides a debugfs file that lists out the ASIDs currently associated
* with the processes.
*
* In the SH-5 case, if the DM.PC register is examined through the debug
* link, this shows ASID + PC. To make use of this, the PID->ASID
* relationship needs to be known. This is primarily for debugging.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/sched/signal.h>
#include <linux/sched/task.h>
#include <asm/processor.h>
#include <asm/mmu_context.h>
static int asids_debugfs_show(struct seq_file *file, void *iter)
{
struct task_struct *p;
read_lock(&tasklist_lock);
for_each_process(p) {
int pid = p->pid;
if (unlikely(!pid))
continue;
if (p->mm)
seq_printf(file, "%5d : %04lx\n", pid,
cpu_asid(smp_processor_id(), p->mm));
}
read_unlock(&tasklist_lock);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(asids_debugfs);
static int __init asids_debugfs_init(void)
{
debugfs_create_file("asids", S_IRUSR, arch_debugfs_dir, NULL,
&asids_debugfs_fops);
return 0;
}
device_initcall(asids_debugfs_init);
| linux-master | arch/sh/mm/asids-debugfs.c |
/*
* arch/sh/mm/mmap.c
*
* Copyright (C) 2008 - 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/sched/mm.h>
#include <linux/mman.h>
#include <linux/module.h>
#include <asm/page.h>
#include <asm/processor.h>
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
EXPORT_SYMBOL(shm_align_mask);
#ifdef CONFIG_MMU
static const pgprot_t protection_map[16] = {
[VM_NONE] = PAGE_NONE,
[VM_READ] = PAGE_READONLY,
[VM_WRITE] = PAGE_COPY,
[VM_WRITE | VM_READ] = PAGE_COPY,
[VM_EXEC] = PAGE_EXECREAD,
[VM_EXEC | VM_READ] = PAGE_EXECREAD,
[VM_EXEC | VM_WRITE] = PAGE_COPY,
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY,
[VM_SHARED] = PAGE_NONE,
[VM_SHARED | VM_READ] = PAGE_READONLY,
[VM_SHARED | VM_WRITE] = PAGE_WRITEONLY,
[VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED,
[VM_SHARED | VM_EXEC] = PAGE_EXECREAD,
[VM_SHARED | VM_EXEC | VM_READ] = PAGE_EXECREAD,
[VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_RWX,
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_RWX
};
DECLARE_VM_GET_PAGE_PROT
/*
* To avoid cache aliases, we map the shared page with same color.
*/
static inline unsigned long COLOUR_ALIGN(unsigned long addr,
unsigned long pgoff)
{
unsigned long base = (addr + shm_align_mask) & ~shm_align_mask;
unsigned long off = (pgoff << PAGE_SHIFT) & shm_align_mask;
return base + off;
}
unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
unsigned long len, unsigned long pgoff, unsigned long flags)
{
struct mm_struct *mm = current->mm;
struct vm_area_struct *vma;
int do_colour_align;
struct vm_unmapped_area_info info;
if (flags & MAP_FIXED) {
/* We do not accept a shared mapping if it would violate
* cache aliasing constraints.
*/
if ((flags & MAP_SHARED) &&
((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
return -EINVAL;
return addr;
}
if (unlikely(len > TASK_SIZE))
return -ENOMEM;
do_colour_align = 0;
if (filp || (flags & MAP_SHARED))
do_colour_align = 1;
if (addr) {
if (do_colour_align)
addr = COLOUR_ALIGN(addr, pgoff);
else
addr = PAGE_ALIGN(addr);
vma = find_vma(mm, addr);
if (TASK_SIZE - len >= addr &&
(!vma || addr + len <= vm_start_gap(vma)))
return addr;
}
info.flags = 0;
info.length = len;
info.low_limit = TASK_UNMAPPED_BASE;
info.high_limit = TASK_SIZE;
info.align_mask = do_colour_align ? (PAGE_MASK & shm_align_mask) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
return vm_unmapped_area(&info);
}
unsigned long
arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
const unsigned long len, const unsigned long pgoff,
const unsigned long flags)
{
struct vm_area_struct *vma;
struct mm_struct *mm = current->mm;
unsigned long addr = addr0;
int do_colour_align;
struct vm_unmapped_area_info info;
if (flags & MAP_FIXED) {
/* We do not accept a shared mapping if it would violate
* cache aliasing constraints.
*/
if ((flags & MAP_SHARED) &&
((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
return -EINVAL;
return addr;
}
if (unlikely(len > TASK_SIZE))
return -ENOMEM;
do_colour_align = 0;
if (filp || (flags & MAP_SHARED))
do_colour_align = 1;
/* requesting a specific address */
if (addr) {
if (do_colour_align)
addr = COLOUR_ALIGN(addr, pgoff);
else
addr = PAGE_ALIGN(addr);
vma = find_vma(mm, addr);
if (TASK_SIZE - len >= addr &&
(!vma || addr + len <= vm_start_gap(vma)))
return addr;
}
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
info.low_limit = PAGE_SIZE;
info.high_limit = mm->mmap_base;
info.align_mask = do_colour_align ? (PAGE_MASK & shm_align_mask) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
addr = vm_unmapped_area(&info);
/*
* A failed mmap() very likely causes application failure,
* so fall back to the bottom-up function here. This scenario
* can happen with large stack limits and large mmap()
* allocations.
*/
if (addr & ~PAGE_MASK) {
VM_BUG_ON(addr != -ENOMEM);
info.flags = 0;
info.low_limit = TASK_UNMAPPED_BASE;
info.high_limit = TASK_SIZE;
addr = vm_unmapped_area(&info);
}
return addr;
}
#endif /* CONFIG_MMU */
/*
* You really shouldn't be using read() or write() on /dev/mem. This
* might go away in the future.
*/
int valid_phys_addr_range(phys_addr_t addr, size_t count)
{
if (addr < __MEMORY_START)
return 0;
if (addr + count > __pa(high_memory))
return 0;
return 1;
}
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
{
return 1;
}
| linux-master | arch/sh/mm/mmap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/sh/mm/init.c
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 - 2011 Paul Mundt
*
* Based on linux/arch/i386/mm/init.c:
* Copyright (C) 1995 Linus Torvalds
*/
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/memblock.h>
#include <linux/proc_fs.h>
#include <linux/pagemap.h>
#include <linux/percpu.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <asm/mmu_context.h>
#include <asm/mmzone.h>
#include <asm/kexec.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/cache.h>
#include <asm/pgalloc.h>
#include <linux/sizes.h>
#include "ioremap.h"
pgd_t swapper_pg_dir[PTRS_PER_PGD];
void __init generic_mem_init(void)
{
memblock_add(__MEMORY_START, __MEMORY_SIZE);
}
void __init __weak plat_mem_setup(void)
{
/* Nothing to see here, move along. */
}
#ifdef CONFIG_MMU
static pte_t *__get_pte_phys(unsigned long addr)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pgd = pgd_offset_k(addr);
if (pgd_none(*pgd)) {
pgd_ERROR(*pgd);
return NULL;
}
p4d = p4d_alloc(NULL, pgd, addr);
if (unlikely(!p4d)) {
p4d_ERROR(*p4d);
return NULL;
}
pud = pud_alloc(NULL, p4d, addr);
if (unlikely(!pud)) {
pud_ERROR(*pud);
return NULL;
}
pmd = pmd_alloc(NULL, pud, addr);
if (unlikely(!pmd)) {
pmd_ERROR(*pmd);
return NULL;
}
return pte_offset_kernel(pmd, addr);
}
static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
{
pte_t *pte;
pte = __get_pte_phys(addr);
if (!pte_none(*pte)) {
pte_ERROR(*pte);
return;
}
set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot));
local_flush_tlb_one(get_asid(), addr);
if (pgprot_val(prot) & _PAGE_WIRED)
tlb_wire_entry(NULL, addr, *pte);
}
static void clear_pte_phys(unsigned long addr, pgprot_t prot)
{
pte_t *pte;
pte = __get_pte_phys(addr);
if (pgprot_val(prot) & _PAGE_WIRED)
tlb_unwire_entry();
set_pte(pte, pfn_pte(0, __pgprot(0)));
local_flush_tlb_one(get_asid(), addr);
}
void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
{
unsigned long address = __fix_to_virt(idx);
if (idx >= __end_of_fixed_addresses) {
BUG();
return;
}
set_pte_phys(address, phys, prot);
}
void __clear_fixmap(enum fixed_addresses idx, pgprot_t prot)
{
unsigned long address = __fix_to_virt(idx);
if (idx >= __end_of_fixed_addresses) {
BUG();
return;
}
clear_pte_phys(address, prot);
}
static pmd_t * __init one_md_table_init(pud_t *pud)
{
if (pud_none(*pud)) {
pmd_t *pmd;
pmd = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!pmd)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
pud_populate(&init_mm, pud, pmd);
BUG_ON(pmd != pmd_offset(pud, 0));
}
return pmd_offset(pud, 0);
}
static pte_t * __init one_page_table_init(pmd_t *pmd)
{
if (pmd_none(*pmd)) {
pte_t *pte;
pte = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!pte)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
pmd_populate_kernel(&init_mm, pmd, pte);
BUG_ON(pte != pte_offset_kernel(pmd, 0));
}
return pte_offset_kernel(pmd, 0);
}
static pte_t * __init page_table_kmap_check(pte_t *pte, pmd_t *pmd,
unsigned long vaddr, pte_t *lastpte)
{
return pte;
}
void __init page_table_range_init(unsigned long start, unsigned long end,
pgd_t *pgd_base)
{
pgd_t *pgd;
pud_t *pud;
pmd_t *pmd;
pte_t *pte = NULL;
int i, j, k;
unsigned long vaddr;
vaddr = start;
i = pgd_index(vaddr);
j = pud_index(vaddr);
k = pmd_index(vaddr);
pgd = pgd_base + i;
for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
pud = (pud_t *)pgd;
for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
pmd = one_md_table_init(pud);
#ifndef __PAGETABLE_PMD_FOLDED
pmd += k;
#endif
for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
pte = page_table_kmap_check(one_page_table_init(pmd),
pmd, vaddr, pte);
vaddr += PMD_SIZE;
}
k = 0;
}
j = 0;
}
}
#endif /* CONFIG_MMU */
void __init allocate_pgdat(unsigned int nid)
{
unsigned long start_pfn, end_pfn;
get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
#ifdef CONFIG_NUMA
NODE_DATA(nid) = memblock_alloc_try_nid(
sizeof(struct pglist_data),
SMP_CACHE_BYTES, MEMBLOCK_LOW_LIMIT,
MEMBLOCK_ALLOC_ACCESSIBLE, nid);
if (!NODE_DATA(nid))
panic("Can't allocate pgdat for node %d\n", nid);
#endif
NODE_DATA(nid)->node_start_pfn = start_pfn;
NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
}
static void __init do_init_bootmem(void)
{
unsigned long start_pfn, end_pfn;
int i;
/* Add active regions with valid PFNs. */
for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL)
__add_active_range(0, start_pfn, end_pfn);
/* All of system RAM sits in node 0 for the non-NUMA case */
allocate_pgdat(0);
node_set_online(0);
plat_mem_setup();
sparse_init();
}
static void __init early_reserve_mem(void)
{
unsigned long start_pfn;
u32 zero_base = (u32)__MEMORY_START + (u32)PHYSICAL_OFFSET;
u32 start = zero_base + (u32)CONFIG_ZERO_PAGE_OFFSET;
/*
* Partially used pages are not usable - thus
* we are rounding upwards:
*/
start_pfn = PFN_UP(__pa(_end));
/*
* Reserve the kernel text and Reserve the bootmem bitmap. We do
* this in two steps (first step was init_bootmem()), because
* this catches the (definitely buggy) case of us accidentally
* initializing the bootmem allocator with an invalid RAM area.
*/
memblock_reserve(start, (PFN_PHYS(start_pfn) + PAGE_SIZE - 1) - start);
/*
* Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET.
*/
if (CONFIG_ZERO_PAGE_OFFSET != 0)
memblock_reserve(zero_base, CONFIG_ZERO_PAGE_OFFSET);
/*
* Handle additional early reservations
*/
check_for_initrd();
reserve_crashkernel();
}
void __init paging_init(void)
{
unsigned long max_zone_pfns[MAX_NR_ZONES];
unsigned long vaddr, end;
sh_mv.mv_mem_init();
early_reserve_mem();
/*
* Once the early reservations are out of the way, give the
* platforms a chance to kick out some memory.
*/
if (sh_mv.mv_mem_reserve)
sh_mv.mv_mem_reserve();
memblock_enforce_memory_limit(memory_limit);
memblock_allow_resize();
memblock_dump_all();
/*
* Determine low and high memory ranges:
*/
max_low_pfn = max_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
min_low_pfn = __MEMORY_START >> PAGE_SHIFT;
set_max_mapnr(max_low_pfn - min_low_pfn);
nodes_clear(node_online_map);
memory_start = (unsigned long)__va(__MEMORY_START);
memory_end = memory_start + (memory_limit ?: memblock_phys_mem_size());
uncached_init();
pmb_init();
do_init_bootmem();
ioremap_fixed_init();
/* We don't need to map the kernel through the TLB, as
* it is permanatly mapped using P1. So clear the
* entire pgd. */
memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
/* Set an initial value for the MMU.TTB so we don't have to
* check for a null value. */
set_TTB(swapper_pg_dir);
/*
* Populate the relevant portions of swapper_pg_dir so that
* we can use the fixmap entries without calling kmalloc.
* pte's will be filled in by __set_fixmap().
*/
vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
page_table_range_init(vaddr, end, swapper_pg_dir);
kmap_coherent_init();
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
free_area_init(max_zone_pfns);
}
unsigned int mem_init_done = 0;
void __init mem_init(void)
{
pg_data_t *pgdat;
high_memory = NULL;
for_each_online_pgdat(pgdat)
high_memory = max_t(void *, high_memory,
__va(pgdat_end_pfn(pgdat) << PAGE_SHIFT));
memblock_free_all();
/* Set this up early, so we can take care of the zero page */
cpu_cache_init();
/* clear the zero-page */
memset(empty_zero_page, 0, PAGE_SIZE);
__flush_wback_region(empty_zero_page, PAGE_SIZE);
vsyscall_init();
pr_info("virtual kernel memory layout:\n"
" fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
" vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n"
" lowmem : 0x%08lx - 0x%08lx (%4ld MB) (cached)\n"
#ifdef CONFIG_UNCACHED_MAPPING
" : 0x%08lx - 0x%08lx (%4ld MB) (uncached)\n"
#endif
" .init : 0x%08lx - 0x%08lx (%4ld kB)\n"
" .data : 0x%08lx - 0x%08lx (%4ld kB)\n"
" .text : 0x%08lx - 0x%08lx (%4ld kB)\n",
FIXADDR_START, FIXADDR_TOP,
(FIXADDR_TOP - FIXADDR_START) >> 10,
(unsigned long)VMALLOC_START, VMALLOC_END,
(VMALLOC_END - VMALLOC_START) >> 20,
(unsigned long)memory_start, (unsigned long)high_memory,
((unsigned long)high_memory - (unsigned long)memory_start) >> 20,
#ifdef CONFIG_UNCACHED_MAPPING
uncached_start, uncached_end, uncached_size >> 20,
#endif
(unsigned long)&__init_begin, (unsigned long)&__init_end,
((unsigned long)&__init_end -
(unsigned long)&__init_begin) >> 10,
(unsigned long)&_etext, (unsigned long)&_edata,
((unsigned long)&_edata - (unsigned long)&_etext) >> 10,
(unsigned long)&_text, (unsigned long)&_etext,
((unsigned long)&_etext - (unsigned long)&_text) >> 10);
mem_init_done = 1;
}
#ifdef CONFIG_MEMORY_HOTPLUG
int arch_add_memory(int nid, u64 start, u64 size,
struct mhp_params *params)
{
unsigned long start_pfn = PFN_DOWN(start);
unsigned long nr_pages = size >> PAGE_SHIFT;
int ret;
if (WARN_ON_ONCE(params->pgprot.pgprot != PAGE_KERNEL.pgprot))
return -EINVAL;
/* We only have ZONE_NORMAL, so this is easy.. */
ret = __add_pages(nid, start_pfn, nr_pages, params);
if (unlikely(ret))
printk("%s: Failed, __add_pages() == %d\n", __func__, ret);
return ret;
}
void arch_remove_memory(u64 start, u64 size, struct vmem_altmap *altmap)
{
unsigned long start_pfn = PFN_DOWN(start);
unsigned long nr_pages = size >> PAGE_SHIFT;
__remove_pages(start_pfn, nr_pages, altmap);
}
#endif /* CONFIG_MEMORY_HOTPLUG */
| linux-master | arch/sh/mm/init.c |
/*
* arch/sh/mm/tlb-pteaex.c
*
* TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
*
* Copyright (C) 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
unsigned long flags, pteval, vpn;
/*
* Handle debugger faulting in for debugee.
*/
if (vma && current->active_mm != vma->vm_mm)
return;
local_irq_save(flags);
/* Set PTEH register */
vpn = address & MMU_VPN_MASK;
__raw_writel(vpn, MMU_PTEH);
/* Set PTEAEX */
__raw_writel(get_asid(), MMU_PTEAEX);
pteval = pte.pte_low;
/* Set PTEA register */
#ifdef CONFIG_X2TLB
/*
* For the extended mode TLB this is trivial, only the ESZ and
* EPR bits need to be written out to PTEA, with the remainder of
* the protection bits (with the exception of the compat-mode SZ
* and PR bits, which are cleared) being written out in PTEL.
*/
__raw_writel(pte.pte_high, MMU_PTEA);
#endif
/* Set PTEL register */
pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_CACHE_WRITETHROUGH
pteval |= _PAGE_WT;
#endif
/* conveniently, we want all the software flags to be 0 anyway */
__raw_writel(pteval, MMU_PTEL);
/* Load the TLB */
asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
local_irq_restore(flags);
}
/*
* While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
* data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
* address arrays. In compat mode the second array is inaccessible, while
* in extended mode, the legacy 8-bit ASID field in address array 1 has
* undefined behaviour.
*/
void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
jump_to_uncached();
__raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
__raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
back_to_cached();
}
void local_flush_tlb_all(void)
{
unsigned long flags, status;
int i;
/*
* Flush all the TLB.
*/
local_irq_save(flags);
jump_to_uncached();
status = __raw_readl(MMUCR);
status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
if (status == 0)
status = MMUCR_URB_NENTRIES;
for (i = 0; i < status; i++)
__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
for (i = 0; i < 4; i++)
__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
back_to_cached();
ctrl_barrier();
local_irq_restore(flags);
}
| linux-master | arch/sh/mm/tlb-pteaex.c |
/*
* Copyright (C) 2004 - 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
static int __init memchunk_setup(char *str)
{
return 1; /* accept anything that begins with "memchunk." */
}
__setup("memchunk.", memchunk_setup);
static void __init memchunk_cmdline_override(char *name, unsigned long *sizep)
{
char *p = boot_command_line;
int k = strlen(name);
while ((p = strstr(p, "memchunk."))) {
p += 9; /* strlen("memchunk.") */
if (!strncmp(name, p, k) && p[k] == '=') {
p += k + 1;
*sizep = memparse(p, NULL);
pr_info("%s: forcing memory chunk size to 0x%08lx\n",
name, *sizep);
break;
}
}
}
int __init platform_resource_setup_memory(struct platform_device *pdev,
char *name, unsigned long memsize)
{
struct resource *r;
dma_addr_t dma_handle;
void *buf;
r = pdev->resource + pdev->num_resources - 1;
if (r->flags) {
pr_warn("%s: unable to find empty space for resource\n", name);
return -EINVAL;
}
memchunk_cmdline_override(name, &memsize);
if (!memsize)
return 0;
buf = dma_alloc_coherent(&pdev->dev, memsize, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_warn("%s: unable to allocate memory\n", name);
return -ENOMEM;
}
r->flags = IORESOURCE_MEM;
r->start = dma_handle;
r->end = r->start + memsize - 1;
r->name = name;
return 0;
}
| linux-master | arch/sh/mm/consistent.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Re-map IO memory to kernel address space so that we can access it.
*
* These functions should only be used when it is necessary to map a
* physical address space into the kernel address space before ioremap()
* can be used, e.g. early in boot before paging_init().
*
* Copyright (C) 2009 Matt Fleming
*/
#include <linux/vmalloc.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/proc_fs.h>
#include <asm/fixmap.h>
#include <asm/page.h>
#include <asm/addrspace.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include "ioremap.h"
struct ioremap_map {
void __iomem *addr;
unsigned long size;
unsigned long fixmap_addr;
};
static struct ioremap_map ioremap_maps[FIX_N_IOREMAPS];
void __init ioremap_fixed_init(void)
{
struct ioremap_map *map;
int i;
for (i = 0; i < FIX_N_IOREMAPS; i++) {
map = &ioremap_maps[i];
map->fixmap_addr = __fix_to_virt(FIX_IOREMAP_BEGIN + i);
}
}
void __init __iomem *
ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
{
enum fixed_addresses idx0, idx;
struct ioremap_map *map;
unsigned int nrpages;
unsigned long offset;
int i, slot;
/*
* Mappings have to be page-aligned
*/
offset = phys_addr & ~PAGE_MASK;
phys_addr &= PAGE_MASK;
size = PAGE_ALIGN(phys_addr + size) - phys_addr;
slot = -1;
for (i = 0; i < FIX_N_IOREMAPS; i++) {
map = &ioremap_maps[i];
if (!map->addr) {
map->size = size;
slot = i;
break;
}
}
if (slot < 0)
return NULL;
/*
* Mappings have to fit in the FIX_IOREMAP area.
*/
nrpages = size >> PAGE_SHIFT;
if (nrpages > FIX_N_IOREMAPS)
return NULL;
/*
* Ok, go for it..
*/
idx0 = FIX_IOREMAP_BEGIN + slot;
idx = idx0;
while (nrpages > 0) {
pgprot_val(prot) |= _PAGE_WIRED;
__set_fixmap(idx, phys_addr, prot);
phys_addr += PAGE_SIZE;
idx++;
--nrpages;
}
map->addr = (void __iomem *)(offset + map->fixmap_addr);
return map->addr;
}
int iounmap_fixed(void __iomem *addr)
{
enum fixed_addresses idx;
struct ioremap_map *map;
unsigned int nrpages;
int i, slot;
slot = -1;
for (i = 0; i < FIX_N_IOREMAPS; i++) {
map = &ioremap_maps[i];
if (map->addr == addr) {
slot = i;
break;
}
}
/*
* If we don't match, it's not for us.
*/
if (slot < 0)
return -EINVAL;
nrpages = map->size >> PAGE_SHIFT;
idx = FIX_IOREMAP_BEGIN + slot + nrpages - 1;
while (nrpages > 0) {
__clear_fixmap(idx, __pgprot(_PAGE_WIRED));
--idx;
--nrpages;
}
map->size = 0;
map->addr = NULL;
return 0;
}
| linux-master | arch/sh/mm/ioremap_fixed.c |
/*
* TLB miss handler for SH with an MMU.
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 - 2012 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/kprobes.h>
#include <linux/kdebug.h>
#include <asm/mmu_context.h>
#include <asm/thread_info.h>
/*
* Called with interrupts disabled.
*/
asmlinkage int __kprobes
handle_tlbmiss(struct pt_regs *regs, unsigned long error_code,
unsigned long address)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
pte_t entry;
/*
* We don't take page faults for P1, P2, and parts of P4, these
* are always mapped, whether it be due to legacy behaviour in
* 29-bit mode, or due to PMB configuration in 32-bit mode.
*/
if (address >= P3SEG && address < P3_ADDR_MAX) {
pgd = pgd_offset_k(address);
} else {
if (unlikely(address >= TASK_SIZE || !current->mm))
return 1;
pgd = pgd_offset(current->mm, address);
}
p4d = p4d_offset(pgd, address);
if (p4d_none_or_clear_bad(p4d))
return 1;
pud = pud_offset(p4d, address);
if (pud_none_or_clear_bad(pud))
return 1;
pmd = pmd_offset(pud, address);
if (pmd_none_or_clear_bad(pmd))
return 1;
pte = pte_offset_kernel(pmd, address);
entry = *pte;
if (unlikely(pte_none(entry) || pte_not_present(entry)))
return 1;
if (unlikely(error_code && !pte_write(entry)))
return 1;
if (error_code)
entry = pte_mkdirty(entry);
entry = pte_mkyoung(entry);
set_pte(pte, entry);
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP)
/*
* SH-4 does not set MMUCR.RC to the corresponding TLB entry in
* the case of an initial page write exception, so we need to
* flush it in order to avoid potential TLB entry duplication.
*/
if (error_code == FAULT_CODE_INITIAL)
local_flush_tlb_one(get_asid(), address & PAGE_MASK);
#endif
set_thread_fault_code(error_code);
update_mmu_cache(NULL, address, pte);
return 0;
}
| linux-master | arch/sh/mm/tlbex_32.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/tlb-sh3.c
*
* SH-3 specific TLB operations
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 Paul Mundt
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
unsigned long flags, pteval, vpn;
/*
* Handle debugger faulting in for debugee.
*/
if (vma && current->active_mm != vma->vm_mm)
return;
local_irq_save(flags);
/* Set PTEH register */
vpn = (address & MMU_VPN_MASK) | get_asid();
__raw_writel(vpn, MMU_PTEH);
pteval = pte_val(pte);
/* Set PTEL register */
pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
/* conveniently, we want all the software flags to be 0 anyway */
__raw_writel(pteval, MMU_PTEL);
/* Load the TLB */
asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
local_irq_restore(flags);
}
void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
unsigned long addr, data;
int i, ways = MMU_NTLB_WAYS;
/*
* NOTE: PTEH.ASID should be set to this MM
* _AND_ we need to write ASID to the array.
*
* It would be simple if we didn't need to set PTEH.ASID...
*/
addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
data = (page & 0xfffe0000) | asid; /* VALID bit is off */
if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
addr |= MMU_PAGE_ASSOC_BIT;
ways = 1; /* we already know the way .. */
}
for (i = 0; i < ways; i++)
__raw_writel(data, addr + (i << 8));
}
void local_flush_tlb_all(void)
{
unsigned long flags, status;
/*
* Flush all the TLB.
*
* Write to the MMU control register's bit:
* TF-bit for SH-3, TI-bit for SH-4.
* It's same position, bit #2.
*/
local_irq_save(flags);
status = __raw_readl(MMUCR);
status |= 0x04;
__raw_writel(status, MMUCR);
ctrl_barrier();
local_irq_restore(flags);
}
| linux-master | arch/sh/mm/tlb-sh3.c |
/*
* arch/sh/mm/tlb-urb.c
*
* TLB entry wiring helpers for URB-equipped parts.
*
* Copyright (C) 2010 Matt Fleming
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/tlb.h>
#include <asm/mmu_context.h>
/*
* Load the entry for 'addr' into the TLB and wire the entry.
*/
void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
{
unsigned long status, flags;
int urb;
local_irq_save(flags);
status = __raw_readl(MMUCR);
urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
status &= ~MMUCR_URC;
/*
* Make sure we're not trying to wire the last TLB entry slot.
*/
BUG_ON(!--urb);
urb = urb % MMUCR_URB_NENTRIES;
/*
* Insert this entry into the highest non-wired TLB slot (via
* the URC field).
*/
status |= (urb << MMUCR_URC_SHIFT);
__raw_writel(status, MMUCR);
ctrl_barrier();
/* Load the entry into the TLB */
__update_tlb(vma, addr, pte);
/* ... and wire it up. */
status = __raw_readl(MMUCR);
status &= ~MMUCR_URB;
status |= (urb << MMUCR_URB_SHIFT);
__raw_writel(status, MMUCR);
ctrl_barrier();
local_irq_restore(flags);
}
/*
* Unwire the last wired TLB entry.
*
* It should also be noted that it is not possible to wire and unwire
* TLB entries in an arbitrary order. If you wire TLB entry N, followed
* by entry N+1, you must unwire entry N+1 first, then entry N. In this
* respect, it works like a stack or LIFO queue.
*/
void tlb_unwire_entry(void)
{
unsigned long status, flags;
int urb;
local_irq_save(flags);
status = __raw_readl(MMUCR);
urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
status &= ~MMUCR_URB;
/*
* Make sure we're not trying to unwire a TLB entry when none
* have been wired.
*/
BUG_ON(urb++ == MMUCR_URB_NENTRIES);
urb = urb % MMUCR_URB_NENTRIES;
status |= (urb << MMUCR_URB_SHIFT);
__raw_writel(status, MMUCR);
ctrl_barrier();
local_irq_restore(flags);
}
| linux-master | arch/sh/mm/tlb-urb.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/mm.h>
#include <asm/mmu_context.h>
#include <asm/cache_insns.h>
#include <asm/cacheflush.h>
#include <asm/traps.h>
/*
* Write back the dirty D-caches, but not invalidate them.
*
* START: Virtual Address (U0, P1, or P3)
* SIZE: Size of the region.
*/
static void sh4__flush_wback_region(void *start, int size)
{
reg_size_t aligned_start, v, cnt, end;
aligned_start = register_align(start);
v = aligned_start & ~(L1_CACHE_BYTES-1);
end = (aligned_start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
cnt = (end - v) / L1_CACHE_BYTES;
while (cnt >= 8) {
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
__ocbwb(v); v += L1_CACHE_BYTES;
cnt -= 8;
}
while (cnt) {
__ocbwb(v); v += L1_CACHE_BYTES;
cnt--;
}
}
/*
* Write back the dirty D-caches and invalidate them.
*
* START: Virtual Address (U0, P1, or P3)
* SIZE: Size of the region.
*/
static void sh4__flush_purge_region(void *start, int size)
{
reg_size_t aligned_start, v, cnt, end;
aligned_start = register_align(start);
v = aligned_start & ~(L1_CACHE_BYTES-1);
end = (aligned_start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
cnt = (end - v) / L1_CACHE_BYTES;
while (cnt >= 8) {
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
__ocbp(v); v += L1_CACHE_BYTES;
cnt -= 8;
}
while (cnt) {
__ocbp(v); v += L1_CACHE_BYTES;
cnt--;
}
}
/*
* No write back please
*/
static void sh4__flush_invalidate_region(void *start, int size)
{
reg_size_t aligned_start, v, cnt, end;
aligned_start = register_align(start);
v = aligned_start & ~(L1_CACHE_BYTES-1);
end = (aligned_start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
cnt = (end - v) / L1_CACHE_BYTES;
while (cnt >= 8) {
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
__ocbi(v); v += L1_CACHE_BYTES;
cnt -= 8;
}
while (cnt) {
__ocbi(v); v += L1_CACHE_BYTES;
cnt--;
}
}
void __init sh4__flush_region_init(void)
{
__flush_wback_region = sh4__flush_wback_region;
__flush_invalidate_region = sh4__flush_invalidate_region;
__flush_purge_region = sh4__flush_purge_region;
}
| linux-master | arch/sh/mm/flush-sh4.c |
/*
* arch/sh/mm/ioremap.c
*
* (C) Copyright 1995 1996 Linus Torvalds
* (C) Copyright 2005 - 2010 Paul Mundt
*
* Re-map IO memory to kernel address space so that we can access it.
* This is needed for high PCI addresses that aren't mapped in the
* 640k-1MB IO memory area on PC's
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*/
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <asm/io_trapped.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/addrspace.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/mmu.h>
#include "ioremap.h"
/*
* On 32-bit SH, we traditionally have the whole physical address space mapped
* at all times (as MIPS does), so "ioremap()" and "iounmap()" do not need to do
* anything but place the address in the proper segment. This is true for P1
* and P2 addresses, as well as some P3 ones. However, most of the P3 addresses
* and newer cores using extended addressing need to map through page tables, so
* the ioremap() implementation becomes a bit more complicated.
*/
#ifdef CONFIG_29BIT
static void __iomem *
__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
{
phys_addr_t last_addr = offset + size - 1;
/*
* For P1 and P2 space this is trivial, as everything is already
* mapped. Uncached access for P1 addresses are done through P2.
* In the P3 case or for addresses outside of the 29-bit space,
* mapping must be done by the PMB or by using page tables.
*/
if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
u64 flags = pgprot_val(prot);
/*
* Anything using the legacy PTEA space attributes needs
* to be kicked down to page table mappings.
*/
if (unlikely(flags & _PAGE_PCC_MASK))
return NULL;
if (unlikely(flags & _PAGE_CACHABLE))
return (void __iomem *)P1SEGADDR(offset);
return (void __iomem *)P2SEGADDR(offset);
}
/* P4 above the store queues are always mapped. */
if (unlikely(offset >= P3_ADDR_MAX))
return (void __iomem *)P4SEGADDR(offset);
return NULL;
}
#else
#define __ioremap_29bit(offset, size, prot) NULL
#endif /* CONFIG_29BIT */
void __iomem __ref *ioremap_prot(phys_addr_t phys_addr, size_t size,
unsigned long prot)
{
void __iomem *mapped;
pgprot_t pgprot = __pgprot(prot);
mapped = __ioremap_trapped(phys_addr, size);
if (mapped)
return mapped;
mapped = __ioremap_29bit(phys_addr, size, pgprot);
if (mapped)
return mapped;
/*
* If we can't yet use the regular approach, go the fixmap route.
*/
if (!mem_init_done)
return ioremap_fixed(phys_addr, size, pgprot);
/*
* First try to remap through the PMB.
* PMB entries are all pre-faulted.
*/
mapped = pmb_remap_caller(phys_addr, size, pgprot,
__builtin_return_address(0));
if (mapped && !IS_ERR(mapped))
return mapped;
return generic_ioremap_prot(phys_addr, size, pgprot);
}
EXPORT_SYMBOL(ioremap_prot);
/*
* Simple checks for non-translatable mappings.
*/
static inline int iomapping_nontranslatable(unsigned long offset)
{
#ifdef CONFIG_29BIT
/*
* In 29-bit mode this includes the fixed P1/P2 areas, as well as
* parts of P3.
*/
if (PXSEG(offset) < P3SEG || offset >= P3_ADDR_MAX)
return 1;
#endif
return 0;
}
void iounmap(volatile void __iomem *addr)
{
unsigned long vaddr = (unsigned long __force)addr;
/*
* Nothing to do if there is no translatable mapping.
*/
if (iomapping_nontranslatable(vaddr))
return;
/*
* There's no VMA if it's from an early fixed mapping.
*/
if (iounmap_fixed((void __iomem *)addr) == 0)
return;
/*
* If the PMB handled it, there's nothing else to do.
*/
if (pmb_unmap((void __iomem *)addr) == 0)
return;
generic_iounmap(addr);
}
EXPORT_SYMBOL(iounmap);
| linux-master | arch/sh/mm/ioremap.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/mm.h>
#include <linux/slab.h>
static struct kmem_cache *pgd_cachep;
#if PAGETABLE_LEVELS > 2
static struct kmem_cache *pmd_cachep;
#endif
void pgd_ctor(void *x)
{
pgd_t *pgd = x;
memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
memcpy(pgd + USER_PTRS_PER_PGD,
swapper_pg_dir + USER_PTRS_PER_PGD,
(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
}
void pgtable_cache_init(void)
{
pgd_cachep = kmem_cache_create("pgd_cache",
PTRS_PER_PGD * (1<<PTE_MAGNITUDE),
PAGE_SIZE, SLAB_PANIC, pgd_ctor);
#if PAGETABLE_LEVELS > 2
pmd_cachep = kmem_cache_create("pmd_cache",
PTRS_PER_PMD * (1<<PTE_MAGNITUDE),
PAGE_SIZE, SLAB_PANIC, NULL);
#endif
}
pgd_t *pgd_alloc(struct mm_struct *mm)
{
return kmem_cache_alloc(pgd_cachep, GFP_KERNEL);
}
void pgd_free(struct mm_struct *mm, pgd_t *pgd)
{
kmem_cache_free(pgd_cachep, pgd);
}
#if PAGETABLE_LEVELS > 2
void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
{
set_pud(pud, __pud((unsigned long)pmd));
}
pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
{
return kmem_cache_alloc(pmd_cachep, GFP_KERNEL | __GFP_ZERO);
}
void pmd_free(struct mm_struct *mm, pmd_t *pmd)
{
kmem_cache_free(pmd_cachep, pmd);
}
#endif /* PAGETABLE_LEVELS > 2 */
| linux-master | arch/sh/mm/pgtable.c |
/*
* Alignment access counters and corresponding user-space interfaces.
*
* Copyright (C) 2009 ST Microelectronics
* Copyright (C) 2009 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/seq_file.h>
#include <linux/proc_fs.h>
#include <linux/uaccess.h>
#include <linux/ratelimit.h>
#include <asm/alignment.h>
#include <asm/processor.h>
static unsigned long se_user;
static unsigned long se_sys;
static unsigned long se_half;
static unsigned long se_word;
static unsigned long se_dword;
static unsigned long se_multi;
/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
valid! */
static int se_usermode = UM_WARN | UM_FIXUP;
/* 0: no warning 1: print a warning message, disabled by default */
static int se_kernmode_warn;
core_param(alignment, se_usermode, int, 0600);
void inc_unaligned_byte_access(void)
{
se_half++;
}
void inc_unaligned_word_access(void)
{
se_word++;
}
void inc_unaligned_dword_access(void)
{
se_dword++;
}
void inc_unaligned_multi_access(void)
{
se_multi++;
}
void inc_unaligned_user_access(void)
{
se_user++;
}
void inc_unaligned_kernel_access(void)
{
se_sys++;
}
/*
* This defaults to the global policy which can be set from the command
* line, while processes can overload their preferences via prctl().
*/
unsigned int unaligned_user_action(void)
{
unsigned int action = se_usermode;
if (current->thread.flags & SH_THREAD_UAC_SIGBUS) {
action &= ~UM_FIXUP;
action |= UM_SIGNAL;
}
if (current->thread.flags & SH_THREAD_UAC_NOPRINT)
action &= ~UM_WARN;
return action;
}
int get_unalign_ctl(struct task_struct *tsk, unsigned long addr)
{
return put_user(tsk->thread.flags & SH_THREAD_UAC_MASK,
(unsigned int __user *)addr);
}
int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
{
tsk->thread.flags = (tsk->thread.flags & ~SH_THREAD_UAC_MASK) |
(val & SH_THREAD_UAC_MASK);
return 0;
}
void unaligned_fixups_notify(struct task_struct *tsk, insn_size_t insn,
struct pt_regs *regs)
{
if (user_mode(regs) && (se_usermode & UM_WARN))
pr_notice_ratelimited("Fixing up unaligned userspace access "
"in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
tsk->comm, task_pid_nr(tsk),
(void *)instruction_pointer(regs), insn);
else if (se_kernmode_warn)
pr_notice_ratelimited("Fixing up unaligned kernel access "
"in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
tsk->comm, task_pid_nr(tsk),
(void *)instruction_pointer(regs), insn);
}
static const char *se_usermode_action[] = {
"ignored",
"warn",
"fixup",
"fixup+warn",
"signal",
"signal+warn"
};
static int alignment_proc_show(struct seq_file *m, void *v)
{
seq_printf(m, "User:\t\t%lu\n", se_user);
seq_printf(m, "System:\t\t%lu\n", se_sys);
seq_printf(m, "Half:\t\t%lu\n", se_half);
seq_printf(m, "Word:\t\t%lu\n", se_word);
seq_printf(m, "DWord:\t\t%lu\n", se_dword);
seq_printf(m, "Multi:\t\t%lu\n", se_multi);
seq_printf(m, "User faults:\t%i (%s)\n", se_usermode,
se_usermode_action[se_usermode]);
seq_printf(m, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
se_kernmode_warn ? "+warn" : "");
return 0;
}
static int alignment_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, alignment_proc_show, NULL);
}
static ssize_t alignment_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
int *data = pde_data(file_inode(file));
char mode;
if (count > 0) {
if (get_user(mode, buffer))
return -EFAULT;
if (mode >= '0' && mode <= '5')
*data = mode - '0';
}
return count;
}
static const struct proc_ops alignment_proc_ops = {
.proc_open = alignment_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = alignment_proc_write,
};
/*
* This needs to be done after sysctl_init_bases(), otherwise sys/ will be
* overwritten. Actually, this shouldn't be in sys/ at all since
* it isn't a sysctl, and it doesn't contain sysctl information.
* We now locate it in /proc/cpu/alignment instead.
*/
static int __init alignment_init(void)
{
struct proc_dir_entry *dir, *res;
dir = proc_mkdir("cpu", NULL);
if (!dir)
return -ENOMEM;
res = proc_create_data("alignment", S_IWUSR | S_IRUGO, dir,
&alignment_proc_ops, &se_usermode);
if (!res)
return -ENOMEM;
res = proc_create_data("kernel_alignment", S_IWUSR | S_IRUGO, dir,
&alignment_proc_ops, &se_kernmode_warn);
if (!res)
return -ENOMEM;
return 0;
}
fs_initcall(alignment_init);
| linux-master | arch/sh/mm/alignment.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/cache-j2.c
*
* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/cpumask.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
#define ICACHE_ENABLE 0x1
#define DCACHE_ENABLE 0x2
#define CACHE_ENABLE (ICACHE_ENABLE | DCACHE_ENABLE)
#define ICACHE_FLUSH 0x100
#define DCACHE_FLUSH 0x200
#define CACHE_FLUSH (ICACHE_FLUSH | DCACHE_FLUSH)
u32 __iomem *j2_ccr_base;
static void j2_flush_icache(void *args)
{
unsigned cpu;
for_each_possible_cpu(cpu)
__raw_writel(CACHE_ENABLE | ICACHE_FLUSH, j2_ccr_base + cpu);
}
static void j2_flush_dcache(void *args)
{
unsigned cpu;
for_each_possible_cpu(cpu)
__raw_writel(CACHE_ENABLE | DCACHE_FLUSH, j2_ccr_base + cpu);
}
static void j2_flush_both(void *args)
{
unsigned cpu;
for_each_possible_cpu(cpu)
__raw_writel(CACHE_ENABLE | CACHE_FLUSH, j2_ccr_base + cpu);
}
void __init j2_cache_init(void)
{
if (!j2_ccr_base)
return;
local_flush_cache_all = j2_flush_both;
local_flush_cache_mm = j2_flush_both;
local_flush_cache_dup_mm = j2_flush_both;
local_flush_cache_page = j2_flush_both;
local_flush_cache_range = j2_flush_both;
local_flush_dcache_folio = j2_flush_dcache;
local_flush_icache_range = j2_flush_icache;
local_flush_icache_folio = j2_flush_icache;
local_flush_cache_sigtramp = j2_flush_icache;
pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base));
}
| linux-master | arch/sh/mm/cache-j2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/cache-sh2a.c
*
* Copyright (C) 2008 Yoshinori Sato
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
/*
* The maximum number of pages we support up to when doing ranged dcache
* flushing. Anything exceeding this will simply flush the dcache in its
* entirety.
*/
#define MAX_OCACHE_PAGES 32
#define MAX_ICACHE_PAGES 32
#ifdef CONFIG_CACHE_WRITEBACK
static void sh2a_flush_oc_line(unsigned long v, int way)
{
unsigned long addr = (v & 0x000007f0) | (way << 11);
unsigned long data;
data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
data &= ~SH_CACHE_UPDATED;
__raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
}
}
#endif
static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
{
/* Set associative bit to hit all ways */
unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
__raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
}
/*
* Write back the dirty D-caches, but not invalidate them.
*/
static void sh2a__flush_wback_region(void *start, int size)
{
#ifdef CONFIG_CACHE_WRITEBACK
unsigned long v;
unsigned long begin, end;
unsigned long flags;
int nr_ways;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
nr_ways = current_cpu_data.dcache.ways;
local_irq_save(flags);
jump_to_uncached();
/* If there are too many pages then flush the entire cache */
if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
begin = CACHE_OC_ADDRESS_ARRAY;
end = begin + (nr_ways * current_cpu_data.dcache.way_size);
for (v = begin; v < end; v += L1_CACHE_BYTES) {
unsigned long data = __raw_readl(v);
if (data & SH_CACHE_UPDATED)
__raw_writel(data & ~SH_CACHE_UPDATED, v);
}
} else {
int way;
for (way = 0; way < nr_ways; way++) {
for (v = begin; v < end; v += L1_CACHE_BYTES)
sh2a_flush_oc_line(v, way);
}
}
back_to_cached();
local_irq_restore(flags);
#endif
}
/*
* Write back the dirty D-caches and invalidate them.
*/
static void sh2a__flush_purge_region(void *start, int size)
{
unsigned long v;
unsigned long begin, end;
unsigned long flags;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
local_irq_save(flags);
jump_to_uncached();
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
#ifdef CONFIG_CACHE_WRITEBACK
int way;
int nr_ways = current_cpu_data.dcache.ways;
for (way = 0; way < nr_ways; way++)
sh2a_flush_oc_line(v, way);
#endif
sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
}
back_to_cached();
local_irq_restore(flags);
}
/*
* Invalidate the D-caches, but no write back please
*/
static void sh2a__flush_invalidate_region(void *start, int size)
{
unsigned long v;
unsigned long begin, end;
unsigned long flags;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
local_irq_save(flags);
jump_to_uncached();
/* If there are too many pages then just blow the cache */
if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
SH_CCR);
} else {
for (v = begin; v < end; v += L1_CACHE_BYTES)
sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
}
back_to_cached();
local_irq_restore(flags);
}
/*
* Write back the range of D-cache, and purge the I-cache.
*/
static void sh2a_flush_icache_range(void *args)
{
struct flusher_data *data = args;
unsigned long start, end;
unsigned long v;
unsigned long flags;
start = data->addr1 & ~(L1_CACHE_BYTES-1);
end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
#ifdef CONFIG_CACHE_WRITEBACK
sh2a__flush_wback_region((void *)start, end-start);
#endif
local_irq_save(flags);
jump_to_uncached();
/* I-Cache invalidate */
/* If there are too many pages then just blow the cache */
if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
SH_CCR);
} else {
for (v = start; v < end; v += L1_CACHE_BYTES)
sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
}
back_to_cached();
local_irq_restore(flags);
}
void __init sh2a_cache_init(void)
{
local_flush_icache_range = sh2a_flush_icache_range;
__flush_wback_region = sh2a__flush_wback_region;
__flush_purge_region = sh2a__flush_purge_region;
__flush_invalidate_region = sh2a__flush_invalidate_region;
}
| linux-master | arch/sh/mm/cache-sh2a.c |
/*
* arch/sh/mm/numa.c - Multiple node support for SH machines
*
* Copyright (C) 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/memblock.h>
#include <linux/mm.h>
#include <linux/numa.h>
#include <linux/pfn.h>
#include <asm/sections.h>
struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
EXPORT_SYMBOL_GPL(node_data);
/*
* On SH machines the conventional approach is to stash system RAM
* in node 0, and other memory blocks in to node 1 and up, ordered by
* latency. Each node's pgdat is node-local at the beginning of the node,
* immediately followed by the node mem map.
*/
void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
{
unsigned long start_pfn, end_pfn;
/* Don't allow bogus node assignment */
BUG_ON(nid >= MAX_NUMNODES || nid <= 0);
start_pfn = PFN_DOWN(start);
end_pfn = PFN_DOWN(end);
pmb_bolt_mapping((unsigned long)__va(start), start, end - start,
PAGE_KERNEL);
memblock_add(start, end - start);
__add_active_range(nid, start_pfn, end_pfn);
/* Node-local pgdat */
NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
SMP_CACHE_BYTES, nid);
if (!NODE_DATA(nid))
panic("%s: Failed to allocate %zu bytes align=0x%x nid=%d\n",
__func__, sizeof(struct pglist_data), SMP_CACHE_BYTES,
nid);
NODE_DATA(nid)->node_start_pfn = start_pfn;
NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
/* It's up */
node_set_online(nid);
}
| linux-master | arch/sh/mm/numa.c |
/*
* arch/sh/mm/cache-sh4.c
*
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
* Copyright (C) 2001 - 2009 Paul Mundt
* Copyright (C) 2003 Richard Curnow
* Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/highmem.h>
#include <linux/pagemap.h>
#include <asm/mmu_context.h>
#include <asm/cache_insns.h>
#include <asm/cacheflush.h>
/*
* The maximum number of pages we support up to when doing ranged dcache
* flushing. Anything exceeding this will simply flush the dcache in its
* entirety.
*/
#define MAX_ICACHE_PAGES 32
static void __flush_cache_one(unsigned long addr, unsigned long phys,
unsigned long exec_offset);
/*
* Write back the range of D-cache, and purge the I-cache.
*
* Called from kernel/module.c:sys_init_module and routine for a.out format,
* signal handler code and kprobes code
*/
static void sh4_flush_icache_range(void *args)
{
struct flusher_data *data = args;
unsigned long start, end;
unsigned long flags, v;
int i;
start = data->addr1;
end = data->addr2;
/* If there are too many pages then just blow away the caches */
if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
local_flush_cache_all(NULL);
return;
}
/*
* Selectively flush d-cache then invalidate the i-cache.
* This is inefficient, so only use this for small ranges.
*/
start &= ~(L1_CACHE_BYTES-1);
end += L1_CACHE_BYTES-1;
end &= ~(L1_CACHE_BYTES-1);
local_irq_save(flags);
jump_to_uncached();
for (v = start; v < end; v += L1_CACHE_BYTES) {
unsigned long icacheaddr;
int j, n;
__ocbwb(v);
icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v &
cpu_data->icache.entry_mask);
/* Clear i-cache line valid-bit */
n = boot_cpu_data.icache.n_aliases;
for (i = 0; i < cpu_data->icache.ways; i++) {
for (j = 0; j < n; j++)
__raw_writel(0, icacheaddr + (j * PAGE_SIZE));
icacheaddr += cpu_data->icache.way_incr;
}
}
back_to_cached();
local_irq_restore(flags);
}
static inline void flush_cache_one(unsigned long start, unsigned long phys)
{
unsigned long flags, exec_offset = 0;
/*
* All types of SH-4 require PC to be uncached to operate on the I-cache.
* Some types of SH-4 require PC to be uncached to operate on the D-cache.
*/
if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
(start < CACHE_OC_ADDRESS_ARRAY))
exec_offset = cached_to_uncached;
local_irq_save(flags);
__flush_cache_one(start, phys, exec_offset);
local_irq_restore(flags);
}
/*
* Write back & invalidate the D-cache of the page.
* (To avoid "alias" issues)
*/
static void sh4_flush_dcache_folio(void *arg)
{
struct folio *folio = arg;
#ifndef CONFIG_SMP
struct address_space *mapping = folio_flush_mapping(folio);
if (mapping && !mapping_mapped(mapping))
clear_bit(PG_dcache_clean, &folio->flags);
else
#endif
{
unsigned long pfn = folio_pfn(folio);
unsigned long addr = (unsigned long)folio_address(folio);
unsigned int i, nr = folio_nr_pages(folio);
for (i = 0; i < nr; i++) {
flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
(addr & shm_align_mask),
pfn * PAGE_SIZE);
addr += PAGE_SIZE;
pfn++;
}
}
wmb();
}
/* TODO: Selective icache invalidation through IC address array.. */
static void flush_icache_all(void)
{
unsigned long flags, ccr;
local_irq_save(flags);
jump_to_uncached();
/* Flush I-cache */
ccr = __raw_readl(SH_CCR);
ccr |= CCR_CACHE_ICI;
__raw_writel(ccr, SH_CCR);
/*
* back_to_cached() will take care of the barrier for us, don't add
* another one!
*/
back_to_cached();
local_irq_restore(flags);
}
static void flush_dcache_all(void)
{
unsigned long addr, end_addr, entry_offset;
end_addr = CACHE_OC_ADDRESS_ARRAY +
(current_cpu_data.dcache.sets <<
current_cpu_data.dcache.entry_shift) *
current_cpu_data.dcache.ways;
entry_offset = 1 << current_cpu_data.dcache.entry_shift;
for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) {
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
__raw_writel(0, addr); addr += entry_offset;
}
}
static void sh4_flush_cache_all(void *unused)
{
flush_dcache_all();
flush_icache_all();
}
/*
* Note : (RPC) since the caches are physically tagged, the only point
* of flush_cache_mm for SH-4 is to get rid of aliases from the
* D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
* lines can stay resident so long as the virtual address they were
* accessed with (hence cache set) is in accord with the physical
* address (i.e. tag). It's no different here.
*
* Caller takes mm->mmap_lock.
*/
static void sh4_flush_cache_mm(void *arg)
{
struct mm_struct *mm = arg;
if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)
return;
flush_dcache_all();
}
/*
* Write back and invalidate I/D-caches for the page.
*
* ADDR: Virtual Address (U0 address)
* PFN: Physical page number
*/
static void sh4_flush_cache_page(void *args)
{
struct flusher_data *data = args;
struct vm_area_struct *vma;
struct page *page;
unsigned long address, pfn, phys;
int map_coherent = 0;
pmd_t *pmd;
pte_t *pte;
void *vaddr;
vma = data->vma;
address = data->addr1 & PAGE_MASK;
pfn = data->addr2;
phys = pfn << PAGE_SHIFT;
page = pfn_to_page(pfn);
if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
return;
pmd = pmd_off(vma->vm_mm, address);
pte = pte_offset_kernel(pmd, address);
/* If the page isn't present, there is nothing to do here. */
if (!(pte_val(*pte) & _PAGE_PRESENT))
return;
if ((vma->vm_mm == current->active_mm))
vaddr = NULL;
else {
/*
* Use kmap_coherent or kmap_atomic to do flushes for
* another ASID than the current one.
*/
map_coherent = (current_cpu_data.dcache.n_aliases &&
test_bit(PG_dcache_clean, &page->flags) &&
page_mapcount(page));
if (map_coherent)
vaddr = kmap_coherent(page, address);
else
vaddr = kmap_atomic(page);
address = (unsigned long)vaddr;
}
flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
(address & shm_align_mask), phys);
if (vma->vm_flags & VM_EXEC)
flush_icache_all();
if (vaddr) {
if (map_coherent)
kunmap_coherent(vaddr);
else
kunmap_atomic(vaddr);
}
}
/*
* Write back and invalidate D-caches.
*
* START, END: Virtual Address (U0 address)
*
* NOTE: We need to flush the _physical_ page entry.
* Flushing the cache lines for U0 only isn't enough.
* We need to flush for P1 too, which may contain aliases.
*/
static void sh4_flush_cache_range(void *args)
{
struct flusher_data *data = args;
struct vm_area_struct *vma;
unsigned long start, end;
vma = data->vma;
start = data->addr1;
end = data->addr2;
if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
return;
/*
* If cache is only 4k-per-way, there are never any 'aliases'. Since
* the cache is physically tagged, the data can just be left in there.
*/
if (boot_cpu_data.dcache.n_aliases == 0)
return;
flush_dcache_all();
if (vma->vm_flags & VM_EXEC)
flush_icache_all();
}
/**
* __flush_cache_one
*
* @addr: address in memory mapped cache array
* @phys: P1 address to flush (has to match tags if addr has 'A' bit
* set i.e. associative write)
* @exec_offset: set to 0x20000000 if flush has to be executed from P2
* region else 0x0
*
* The offset into the cache array implied by 'addr' selects the
* 'colour' of the virtual address range that will be flushed. The
* operation (purge/write-back) is selected by the lower 2 bits of
* 'phys'.
*/
static void __flush_cache_one(unsigned long addr, unsigned long phys,
unsigned long exec_offset)
{
int way_count;
unsigned long base_addr = addr;
struct cache_info *dcache;
unsigned long way_incr;
unsigned long a, ea, p;
unsigned long temp_pc;
dcache = &boot_cpu_data.dcache;
/* Write this way for better assembly. */
way_count = dcache->ways;
way_incr = dcache->way_incr;
/*
* Apply exec_offset (i.e. branch to P2 if required.).
*
* FIXME:
*
* If I write "=r" for the (temp_pc), it puts this in r6 hence
* trashing exec_offset before it's been added on - why? Hence
* "=&r" as a 'workaround'
*/
asm volatile("mov.l 1f, %0\n\t"
"add %1, %0\n\t"
"jmp @%0\n\t"
"nop\n\t"
".balign 4\n\t"
"1: .long 2f\n\t"
"2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
/*
* We know there will be >=1 iteration, so write as do-while to avoid
* pointless nead-of-loop check for 0 iterations.
*/
do {
ea = base_addr + PAGE_SIZE;
a = base_addr;
p = phys;
do {
*(volatile unsigned long *)a = p;
/*
* Next line: intentionally not p+32, saves an add, p
* will do since only the cache tag bits need to
* match.
*/
*(volatile unsigned long *)(a+32) = p;
a += 64;
p += 64;
} while (a < ea);
base_addr += way_incr;
} while (--way_count != 0);
}
extern void __weak sh4__flush_region_init(void);
/*
* SH-4 has virtually indexed and physically tagged cache.
*/
void __init sh4_cache_init(void)
{
printk("PVR=%08x CVR=%08x PRR=%08x\n",
__raw_readl(CCN_PVR),
__raw_readl(CCN_CVR),
__raw_readl(CCN_PRR));
local_flush_icache_range = sh4_flush_icache_range;
local_flush_dcache_folio = sh4_flush_dcache_folio;
local_flush_cache_all = sh4_flush_cache_all;
local_flush_cache_mm = sh4_flush_cache_mm;
local_flush_cache_dup_mm = sh4_flush_cache_mm;
local_flush_cache_page = sh4_flush_cache_page;
local_flush_cache_range = sh4_flush_cache_range;
sh4__flush_region_init();
}
| linux-master | arch/sh/mm/cache-sh4.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/module.h>
#include <linux/sizes.h>
#include <asm/page.h>
#include <asm/addrspace.h>
/*
* This is the offset of the uncached section from its cached alias.
*
* Legacy platforms handle trivial transitions between cached and
* uncached segments by making use of the 1:1 mapping relationship in
* 512MB lowmem, others via a special uncached mapping.
*
* Default value only valid in 29 bit mode, in 32bit mode this will be
* updated by the early PMB initialization code.
*/
unsigned long cached_to_uncached = SZ_512M;
unsigned long uncached_size = SZ_512M;
unsigned long uncached_start, uncached_end;
EXPORT_SYMBOL(uncached_start);
EXPORT_SYMBOL(uncached_end);
int virt_addr_uncached(unsigned long kaddr)
{
return (kaddr >= uncached_start) && (kaddr < uncached_end);
}
EXPORT_SYMBOL(virt_addr_uncached);
void __init uncached_init(void)
{
#if defined(CONFIG_29BIT) || !defined(CONFIG_MMU)
uncached_start = P2SEG;
#else
uncached_start = memory_end;
#endif
uncached_end = uncached_start + uncached_size;
}
void __init uncached_resize(unsigned long size)
{
uncached_size = size;
uncached_end = uncached_start + uncached_size;
}
| linux-master | arch/sh/mm/uncached.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/cache.c
*
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
* Copyright (C) 2002 - 2010 Paul Mundt
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/smp.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
void (*local_flush_cache_all)(void *args) = cache_noop;
void (*local_flush_cache_mm)(void *args) = cache_noop;
void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
void (*local_flush_cache_page)(void *args) = cache_noop;
void (*local_flush_cache_range)(void *args) = cache_noop;
void (*local_flush_dcache_folio)(void *args) = cache_noop;
void (*local_flush_icache_range)(void *args) = cache_noop;
void (*local_flush_icache_folio)(void *args) = cache_noop;
void (*local_flush_cache_sigtramp)(void *args) = cache_noop;
void (*__flush_wback_region)(void *start, int size);
EXPORT_SYMBOL(__flush_wback_region);
void (*__flush_purge_region)(void *start, int size);
EXPORT_SYMBOL(__flush_purge_region);
void (*__flush_invalidate_region)(void *start, int size);
EXPORT_SYMBOL(__flush_invalidate_region);
static inline void noop__flush_region(void *start, int size)
{
}
static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
int wait)
{
preempt_disable();
/* Needing IPI for cross-core flush is SHX3-specific. */
#ifdef CONFIG_CPU_SHX3
/*
* It's possible that this gets called early on when IRQs are
* still disabled due to ioremapping by the boot CPU, so don't
* even attempt IPIs unless there are other CPUs online.
*/
if (num_online_cpus() > 1)
smp_call_function(func, info, wait);
#endif
func(info);
preempt_enable();
}
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
struct folio *folio = page_folio(page);
if (boot_cpu_data.dcache.n_aliases && folio_mapped(folio) &&
test_bit(PG_dcache_clean, &folio->flags)) {
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(vto, src, len);
kunmap_coherent(vto);
} else {
memcpy(dst, src, len);
if (boot_cpu_data.dcache.n_aliases)
clear_bit(PG_dcache_clean, &folio->flags);
}
if (vma->vm_flags & VM_EXEC)
flush_cache_page(vma, vaddr, page_to_pfn(page));
}
void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
struct folio *folio = page_folio(page);
if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
test_bit(PG_dcache_clean, &folio->flags)) {
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(dst, vfrom, len);
kunmap_coherent(vfrom);
} else {
memcpy(dst, src, len);
if (boot_cpu_data.dcache.n_aliases)
clear_bit(PG_dcache_clean, &folio->flags);
}
}
void copy_user_highpage(struct page *to, struct page *from,
unsigned long vaddr, struct vm_area_struct *vma)
{
struct folio *src = page_folio(from);
void *vfrom, *vto;
vto = kmap_atomic(to);
if (boot_cpu_data.dcache.n_aliases && folio_mapped(src) &&
test_bit(PG_dcache_clean, &src->flags)) {
vfrom = kmap_coherent(from, vaddr);
copy_page(vto, vfrom);
kunmap_coherent(vfrom);
} else {
vfrom = kmap_atomic(from);
copy_page(vto, vfrom);
kunmap_atomic(vfrom);
}
if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
(vma->vm_flags & VM_EXEC))
__flush_purge_region(vto, PAGE_SIZE);
kunmap_atomic(vto);
/* Make sure this page is cleared on other CPU's too before using it */
smp_wmb();
}
EXPORT_SYMBOL(copy_user_highpage);
void clear_user_highpage(struct page *page, unsigned long vaddr)
{
void *kaddr = kmap_atomic(page);
clear_page(kaddr);
if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
__flush_purge_region(kaddr, PAGE_SIZE);
kunmap_atomic(kaddr);
}
EXPORT_SYMBOL(clear_user_highpage);
void __update_cache(struct vm_area_struct *vma,
unsigned long address, pte_t pte)
{
unsigned long pfn = pte_pfn(pte);
if (!boot_cpu_data.dcache.n_aliases)
return;
if (pfn_valid(pfn)) {
struct folio *folio = page_folio(pfn_to_page(pfn));
int dirty = !test_and_set_bit(PG_dcache_clean, &folio->flags);
if (dirty)
__flush_purge_region(folio_address(folio),
folio_size(folio));
}
}
void __flush_anon_page(struct page *page, unsigned long vmaddr)
{
struct folio *folio = page_folio(page);
unsigned long addr = (unsigned long) page_address(page);
if (pages_do_alias(addr, vmaddr)) {
if (boot_cpu_data.dcache.n_aliases && folio_mapped(folio) &&
test_bit(PG_dcache_clean, &folio->flags)) {
void *kaddr;
kaddr = kmap_coherent(page, vmaddr);
/* XXX.. For now kunmap_coherent() does a purge */
/* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
kunmap_coherent(kaddr);
} else
__flush_purge_region(folio_address(folio),
folio_size(folio));
}
}
void flush_cache_all(void)
{
cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
}
EXPORT_SYMBOL(flush_cache_all);
void flush_cache_mm(struct mm_struct *mm)
{
if (boot_cpu_data.dcache.n_aliases == 0)
return;
cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
}
void flush_cache_dup_mm(struct mm_struct *mm)
{
if (boot_cpu_data.dcache.n_aliases == 0)
return;
cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
}
void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
unsigned long pfn)
{
struct flusher_data data;
data.vma = vma;
data.addr1 = addr;
data.addr2 = pfn;
cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
}
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
struct flusher_data data;
data.vma = vma;
data.addr1 = start;
data.addr2 = end;
cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_cache_range);
void flush_dcache_folio(struct folio *folio)
{
cacheop_on_each_cpu(local_flush_dcache_folio, folio, 1);
}
EXPORT_SYMBOL(flush_dcache_folio);
void flush_icache_range(unsigned long start, unsigned long end)
{
struct flusher_data data;
data.vma = NULL;
data.addr1 = start;
data.addr2 = end;
cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
}
EXPORT_SYMBOL(flush_icache_range);
void flush_icache_pages(struct vm_area_struct *vma, struct page *page,
unsigned int nr)
{
/* Nothing uses the VMA, so just pass the folio along */
cacheop_on_each_cpu(local_flush_icache_folio, page_folio(page), 1);
}
void flush_cache_sigtramp(unsigned long address)
{
cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
}
static void compute_alias(struct cache_info *c)
{
#ifdef CONFIG_MMU
c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
#else
c->alias_mask = 0;
#endif
c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}
static void __init emit_cache_params(void)
{
printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
boot_cpu_data.icache.ways,
boot_cpu_data.icache.sets,
boot_cpu_data.icache.way_incr);
printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
boot_cpu_data.icache.entry_mask,
boot_cpu_data.icache.alias_mask,
boot_cpu_data.icache.n_aliases);
printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
boot_cpu_data.dcache.ways,
boot_cpu_data.dcache.sets,
boot_cpu_data.dcache.way_incr);
printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
boot_cpu_data.dcache.entry_mask,
boot_cpu_data.dcache.alias_mask,
boot_cpu_data.dcache.n_aliases);
/*
* Emit Secondary Cache parameters if the CPU has a probed L2.
*/
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
boot_cpu_data.scache.ways,
boot_cpu_data.scache.sets,
boot_cpu_data.scache.way_incr);
printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
boot_cpu_data.scache.entry_mask,
boot_cpu_data.scache.alias_mask,
boot_cpu_data.scache.n_aliases);
}
}
void __init cpu_cache_init(void)
{
unsigned int cache_disabled = 0;
#ifdef SH_CCR
cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
#endif
compute_alias(&boot_cpu_data.icache);
compute_alias(&boot_cpu_data.dcache);
compute_alias(&boot_cpu_data.scache);
__flush_wback_region = noop__flush_region;
__flush_purge_region = noop__flush_region;
__flush_invalidate_region = noop__flush_region;
/*
* No flushing is necessary in the disabled cache case so we can
* just keep the noop functions in local_flush_..() and __flush_..()
*/
if (unlikely(cache_disabled))
goto skip;
if (boot_cpu_data.type == CPU_J2) {
extern void __weak j2_cache_init(void);
j2_cache_init();
} else if (boot_cpu_data.family == CPU_FAMILY_SH2) {
extern void __weak sh2_cache_init(void);
sh2_cache_init();
}
if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
extern void __weak sh2a_cache_init(void);
sh2a_cache_init();
}
if (boot_cpu_data.family == CPU_FAMILY_SH3) {
extern void __weak sh3_cache_init(void);
sh3_cache_init();
if ((boot_cpu_data.type == CPU_SH7705) &&
(boot_cpu_data.dcache.sets == 512)) {
extern void __weak sh7705_cache_init(void);
sh7705_cache_init();
}
}
if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
(boot_cpu_data.family == CPU_FAMILY_SH4A) ||
(boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
extern void __weak sh4_cache_init(void);
sh4_cache_init();
if ((boot_cpu_data.type == CPU_SH7786) ||
(boot_cpu_data.type == CPU_SHX3)) {
extern void __weak shx3_cache_init(void);
shx3_cache_init();
}
}
skip:
emit_cache_params();
}
| linux-master | arch/sh/mm/cache.c |
/*
* arch/sh/mm/pmb.c
*
* Privileged Space Mapping Buffer (PMB) Support.
*
* Copyright (C) 2005 - 2011 Paul Mundt
* Copyright (C) 2010 Matt Fleming
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/syscore_ops.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/vmalloc.h>
#include <linux/pgtable.h>
#include <asm/cacheflush.h>
#include <linux/sizes.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
struct pmb_entry;
struct pmb_entry {
unsigned long vpn;
unsigned long ppn;
unsigned long flags;
unsigned long size;
raw_spinlock_t lock;
/*
* 0 .. NR_PMB_ENTRIES for specific entry selection, or
* PMB_NO_ENTRY to search for a free one
*/
int entry;
/* Adjacent entry link for contiguous multi-entry mappings */
struct pmb_entry *link;
};
static struct {
unsigned long size;
int flag;
} pmb_sizes[] = {
{ .size = SZ_512M, .flag = PMB_SZ_512M, },
{ .size = SZ_128M, .flag = PMB_SZ_128M, },
{ .size = SZ_64M, .flag = PMB_SZ_64M, },
{ .size = SZ_16M, .flag = PMB_SZ_16M, },
};
static void pmb_unmap_entry(struct pmb_entry *, int depth);
static DEFINE_RWLOCK(pmb_rwlock);
static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
static unsigned int pmb_iomapping_enabled;
static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
{
return (entry & PMB_E_MASK) << PMB_E_SHIFT;
}
static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
{
return mk_pmb_entry(entry) | PMB_ADDR;
}
static __always_inline unsigned long mk_pmb_data(unsigned int entry)
{
return mk_pmb_entry(entry) | PMB_DATA;
}
static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
{
return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
}
/*
* Ensure that the PMB entries match our cache configuration.
*
* When we are in 32-bit address extended mode, CCR.CB becomes
* invalid, so care must be taken to manually adjust cacheable
* translations.
*/
static __always_inline unsigned long pmb_cache_flags(void)
{
unsigned long flags = 0;
#if defined(CONFIG_CACHE_OFF)
flags |= PMB_WT | PMB_UB;
#elif defined(CONFIG_CACHE_WRITETHROUGH)
flags |= PMB_C | PMB_WT | PMB_UB;
#elif defined(CONFIG_CACHE_WRITEBACK)
flags |= PMB_C;
#endif
return flags;
}
/*
* Convert typical pgprot value to the PMB equivalent
*/
static inline unsigned long pgprot_to_pmb_flags(pgprot_t prot)
{
unsigned long pmb_flags = 0;
u64 flags = pgprot_val(prot);
if (flags & _PAGE_CACHABLE)
pmb_flags |= PMB_C;
if (flags & _PAGE_WT)
pmb_flags |= PMB_WT | PMB_UB;
return pmb_flags;
}
static inline bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
{
return (b->vpn == (a->vpn + a->size)) &&
(b->ppn == (a->ppn + a->size)) &&
(b->flags == a->flags);
}
static bool pmb_mapping_exists(unsigned long vaddr, phys_addr_t phys,
unsigned long size)
{
int i;
read_lock(&pmb_rwlock);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
struct pmb_entry *pmbe, *iter;
unsigned long span;
if (!test_bit(i, pmb_map))
continue;
pmbe = &pmb_entry_list[i];
/*
* See if VPN and PPN are bounded by an existing mapping.
*/
if ((vaddr < pmbe->vpn) || (vaddr >= (pmbe->vpn + pmbe->size)))
continue;
if ((phys < pmbe->ppn) || (phys >= (pmbe->ppn + pmbe->size)))
continue;
/*
* Now see if we're in range of a simple mapping.
*/
if (size <= pmbe->size) {
read_unlock(&pmb_rwlock);
return true;
}
span = pmbe->size;
/*
* Finally for sizes that involve compound mappings, walk
* the chain.
*/
for (iter = pmbe->link; iter; iter = iter->link)
span += iter->size;
/*
* Nothing else to do if the range requirements are met.
*/
if (size <= span) {
read_unlock(&pmb_rwlock);
return true;
}
}
read_unlock(&pmb_rwlock);
return false;
}
static bool pmb_size_valid(unsigned long size)
{
int i;
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
if (pmb_sizes[i].size == size)
return true;
return false;
}
static inline bool pmb_addr_valid(unsigned long addr, unsigned long size)
{
return (addr >= P1SEG && (addr + size - 1) < P3SEG);
}
static inline bool pmb_prot_valid(pgprot_t prot)
{
return (pgprot_val(prot) & _PAGE_USER) == 0;
}
static int pmb_size_to_flags(unsigned long size)
{
int i;
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
if (pmb_sizes[i].size == size)
return pmb_sizes[i].flag;
return 0;
}
static int pmb_alloc_entry(void)
{
int pos;
pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
if (pos >= 0 && pos < NR_PMB_ENTRIES)
__set_bit(pos, pmb_map);
else
pos = -ENOSPC;
return pos;
}
static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
unsigned long flags, int entry)
{
struct pmb_entry *pmbe;
unsigned long irqflags;
void *ret = NULL;
int pos;
write_lock_irqsave(&pmb_rwlock, irqflags);
if (entry == PMB_NO_ENTRY) {
pos = pmb_alloc_entry();
if (unlikely(pos < 0)) {
ret = ERR_PTR(pos);
goto out;
}
} else {
if (__test_and_set_bit(entry, pmb_map)) {
ret = ERR_PTR(-ENOSPC);
goto out;
}
pos = entry;
}
write_unlock_irqrestore(&pmb_rwlock, irqflags);
pmbe = &pmb_entry_list[pos];
memset(pmbe, 0, sizeof(struct pmb_entry));
raw_spin_lock_init(&pmbe->lock);
pmbe->vpn = vpn;
pmbe->ppn = ppn;
pmbe->flags = flags;
pmbe->entry = pos;
return pmbe;
out:
write_unlock_irqrestore(&pmb_rwlock, irqflags);
return ret;
}
static void pmb_free(struct pmb_entry *pmbe)
{
__clear_bit(pmbe->entry, pmb_map);
pmbe->entry = PMB_NO_ENTRY;
pmbe->link = NULL;
}
/*
* Must be run uncached.
*/
static void __set_pmb_entry(struct pmb_entry *pmbe)
{
unsigned long addr, data;
addr = mk_pmb_addr(pmbe->entry);
data = mk_pmb_data(pmbe->entry);
jump_to_uncached();
/* Set V-bit */
__raw_writel(pmbe->vpn | PMB_V, addr);
__raw_writel(pmbe->ppn | pmbe->flags | PMB_V, data);
back_to_cached();
}
static void __clear_pmb_entry(struct pmb_entry *pmbe)
{
unsigned long addr, data;
unsigned long addr_val, data_val;
addr = mk_pmb_addr(pmbe->entry);
data = mk_pmb_data(pmbe->entry);
addr_val = __raw_readl(addr);
data_val = __raw_readl(data);
/* Clear V-bit */
writel_uncached(addr_val & ~PMB_V, addr);
writel_uncached(data_val & ~PMB_V, data);
}
#ifdef CONFIG_PM
static void set_pmb_entry(struct pmb_entry *pmbe)
{
unsigned long flags;
raw_spin_lock_irqsave(&pmbe->lock, flags);
__set_pmb_entry(pmbe);
raw_spin_unlock_irqrestore(&pmbe->lock, flags);
}
#endif /* CONFIG_PM */
int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
unsigned long size, pgprot_t prot)
{
struct pmb_entry *pmbp, *pmbe;
unsigned long orig_addr, orig_size;
unsigned long flags, pmb_flags;
int i, mapped;
if (size < SZ_16M)
return -EINVAL;
if (!pmb_addr_valid(vaddr, size))
return -EFAULT;
if (pmb_mapping_exists(vaddr, phys, size))
return 0;
orig_addr = vaddr;
orig_size = size;
flush_tlb_kernel_range(vaddr, vaddr + size);
pmb_flags = pgprot_to_pmb_flags(prot);
pmbp = NULL;
do {
for (i = mapped = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
if (size < pmb_sizes[i].size)
continue;
pmbe = pmb_alloc(vaddr, phys, pmb_flags |
pmb_sizes[i].flag, PMB_NO_ENTRY);
if (IS_ERR(pmbe)) {
pmb_unmap_entry(pmbp, mapped);
return PTR_ERR(pmbe);
}
raw_spin_lock_irqsave(&pmbe->lock, flags);
pmbe->size = pmb_sizes[i].size;
__set_pmb_entry(pmbe);
phys += pmbe->size;
vaddr += pmbe->size;
size -= pmbe->size;
/*
* Link adjacent entries that span multiple PMB
* entries for easier tear-down.
*/
if (likely(pmbp)) {
raw_spin_lock_nested(&pmbp->lock,
SINGLE_DEPTH_NESTING);
pmbp->link = pmbe;
raw_spin_unlock(&pmbp->lock);
}
pmbp = pmbe;
/*
* Instead of trying smaller sizes on every
* iteration (even if we succeed in allocating
* space), try using pmb_sizes[i].size again.
*/
i--;
mapped++;
raw_spin_unlock_irqrestore(&pmbe->lock, flags);
}
} while (size >= SZ_16M);
flush_cache_vmap(orig_addr, orig_addr + orig_size);
return 0;
}
void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
pgprot_t prot, void *caller)
{
unsigned long vaddr;
phys_addr_t offset, last_addr;
phys_addr_t align_mask;
unsigned long aligned;
struct vm_struct *area;
int i, ret;
if (!pmb_iomapping_enabled)
return NULL;
/*
* Small mappings need to go through the TLB.
*/
if (size < SZ_16M)
return ERR_PTR(-EINVAL);
if (!pmb_prot_valid(prot))
return ERR_PTR(-EINVAL);
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
if (size >= pmb_sizes[i].size)
break;
last_addr = phys + size;
align_mask = ~(pmb_sizes[i].size - 1);
offset = phys & ~align_mask;
phys &= align_mask;
aligned = ALIGN(last_addr, pmb_sizes[i].size) - phys;
/*
* XXX: This should really start from uncached_end, but this
* causes the MMU to reset, so for now we restrict it to the
* 0xb000...0xc000 range.
*/
area = __get_vm_area_caller(aligned, VM_IOREMAP, 0xb0000000,
P3SEG, caller);
if (!area)
return NULL;
area->phys_addr = phys;
vaddr = (unsigned long)area->addr;
ret = pmb_bolt_mapping(vaddr, phys, size, prot);
if (unlikely(ret != 0))
return ERR_PTR(ret);
return (void __iomem *)(offset + (char *)vaddr);
}
int pmb_unmap(void __iomem *addr)
{
struct pmb_entry *pmbe = NULL;
unsigned long vaddr = (unsigned long __force)addr;
int i, found = 0;
read_lock(&pmb_rwlock);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
if (test_bit(i, pmb_map)) {
pmbe = &pmb_entry_list[i];
if (pmbe->vpn == vaddr) {
found = 1;
break;
}
}
}
read_unlock(&pmb_rwlock);
if (found) {
pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
return 0;
}
return -EINVAL;
}
static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
{
do {
struct pmb_entry *pmblink = pmbe;
/*
* We may be called before this pmb_entry has been
* entered into the PMB table via set_pmb_entry(), but
* that's OK because we've allocated a unique slot for
* this entry in pmb_alloc() (even if we haven't filled
* it yet).
*
* Therefore, calling __clear_pmb_entry() is safe as no
* other mapping can be using that slot.
*/
__clear_pmb_entry(pmbe);
flush_cache_vunmap(pmbe->vpn, pmbe->vpn + pmbe->size);
pmbe = pmblink->link;
pmb_free(pmblink);
} while (pmbe && --depth);
}
static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
{
unsigned long flags;
if (unlikely(!pmbe))
return;
write_lock_irqsave(&pmb_rwlock, flags);
__pmb_unmap_entry(pmbe, depth);
write_unlock_irqrestore(&pmb_rwlock, flags);
}
static void __init pmb_notify(void)
{
int i;
pr_info("PMB: boot mappings:\n");
read_lock(&pmb_rwlock);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
struct pmb_entry *pmbe;
if (!test_bit(i, pmb_map))
continue;
pmbe = &pmb_entry_list[i];
pr_info(" 0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
}
read_unlock(&pmb_rwlock);
}
/*
* Sync our software copy of the PMB mappings with those in hardware. The
* mappings in the hardware PMB were either set up by the bootloader or
* very early on by the kernel.
*/
static void __init pmb_synchronize(void)
{
struct pmb_entry *pmbp = NULL;
int i, j;
/*
* Run through the initial boot mappings, log the established
* ones, and blow away anything that falls outside of the valid
* PPN range. Specifically, we only care about existing mappings
* that impact the cached/uncached sections.
*
* Note that touching these can be a bit of a minefield; the boot
* loader can establish multi-page mappings with the same caching
* attributes, so we need to ensure that we aren't modifying a
* mapping that we're presently executing from, or may execute
* from in the case of straddling page boundaries.
*
* In the future we will have to tidy up after the boot loader by
* jumping between the cached and uncached mappings and tearing
* down alternating mappings while executing from the other.
*/
for (i = 0; i < NR_PMB_ENTRIES; i++) {
unsigned long addr, data;
unsigned long addr_val, data_val;
unsigned long ppn, vpn, flags;
unsigned long irqflags;
unsigned int size;
struct pmb_entry *pmbe;
addr = mk_pmb_addr(i);
data = mk_pmb_data(i);
addr_val = __raw_readl(addr);
data_val = __raw_readl(data);
/*
* Skip over any bogus entries
*/
if (!(data_val & PMB_V) || !(addr_val & PMB_V))
continue;
ppn = data_val & PMB_PFN_MASK;
vpn = addr_val & PMB_PFN_MASK;
/*
* Only preserve in-range mappings.
*/
if (!pmb_ppn_in_range(ppn)) {
/*
* Invalidate anything out of bounds.
*/
writel_uncached(addr_val & ~PMB_V, addr);
writel_uncached(data_val & ~PMB_V, data);
continue;
}
/*
* Update the caching attributes if necessary
*/
if (data_val & PMB_C) {
data_val &= ~PMB_CACHE_MASK;
data_val |= pmb_cache_flags();
writel_uncached(data_val, data);
}
size = data_val & PMB_SZ_MASK;
flags = size | (data_val & PMB_CACHE_MASK);
pmbe = pmb_alloc(vpn, ppn, flags, i);
if (IS_ERR(pmbe)) {
WARN_ON_ONCE(1);
continue;
}
raw_spin_lock_irqsave(&pmbe->lock, irqflags);
for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
if (pmb_sizes[j].flag == size)
pmbe->size = pmb_sizes[j].size;
if (pmbp) {
raw_spin_lock_nested(&pmbp->lock, SINGLE_DEPTH_NESTING);
/*
* Compare the previous entry against the current one to
* see if the entries span a contiguous mapping. If so,
* setup the entry links accordingly. Compound mappings
* are later coalesced.
*/
if (pmb_can_merge(pmbp, pmbe))
pmbp->link = pmbe;
raw_spin_unlock(&pmbp->lock);
}
pmbp = pmbe;
raw_spin_unlock_irqrestore(&pmbe->lock, irqflags);
}
}
static void __init pmb_merge(struct pmb_entry *head)
{
unsigned long span, newsize;
struct pmb_entry *tail;
int i = 1, depth = 0;
span = newsize = head->size;
tail = head->link;
while (tail) {
span += tail->size;
if (pmb_size_valid(span)) {
newsize = span;
depth = i;
}
/* This is the end of the line.. */
if (!tail->link)
break;
tail = tail->link;
i++;
}
/*
* The merged page size must be valid.
*/
if (!depth || !pmb_size_valid(newsize))
return;
head->flags &= ~PMB_SZ_MASK;
head->flags |= pmb_size_to_flags(newsize);
head->size = newsize;
__pmb_unmap_entry(head->link, depth);
__set_pmb_entry(head);
}
static void __init pmb_coalesce(void)
{
unsigned long flags;
int i;
write_lock_irqsave(&pmb_rwlock, flags);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
struct pmb_entry *pmbe;
if (!test_bit(i, pmb_map))
continue;
pmbe = &pmb_entry_list[i];
/*
* We're only interested in compound mappings
*/
if (!pmbe->link)
continue;
/*
* Nothing to do if it already uses the largest possible
* page size.
*/
if (pmbe->size == SZ_512M)
continue;
pmb_merge(pmbe);
}
write_unlock_irqrestore(&pmb_rwlock, flags);
}
#ifdef CONFIG_UNCACHED_MAPPING
static void __init pmb_resize(void)
{
int i;
/*
* If the uncached mapping was constructed by the kernel, it will
* already be a reasonable size.
*/
if (uncached_size == SZ_16M)
return;
read_lock(&pmb_rwlock);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
struct pmb_entry *pmbe;
unsigned long flags;
if (!test_bit(i, pmb_map))
continue;
pmbe = &pmb_entry_list[i];
if (pmbe->vpn != uncached_start)
continue;
/*
* Found it, now resize it.
*/
raw_spin_lock_irqsave(&pmbe->lock, flags);
pmbe->size = SZ_16M;
pmbe->flags &= ~PMB_SZ_MASK;
pmbe->flags |= pmb_size_to_flags(pmbe->size);
uncached_resize(pmbe->size);
__set_pmb_entry(pmbe);
raw_spin_unlock_irqrestore(&pmbe->lock, flags);
}
read_unlock(&pmb_rwlock);
}
#endif
static int __init early_pmb(char *p)
{
if (!p)
return 0;
if (strstr(p, "iomap"))
pmb_iomapping_enabled = 1;
return 0;
}
early_param("pmb", early_pmb);
void __init pmb_init(void)
{
/* Synchronize software state */
pmb_synchronize();
/* Attempt to combine compound mappings */
pmb_coalesce();
#ifdef CONFIG_UNCACHED_MAPPING
/* Resize initial mappings, if necessary */
pmb_resize();
#endif
/* Log them */
pmb_notify();
writel_uncached(0, PMB_IRMCR);
/* Flush out the TLB */
local_flush_tlb_all();
ctrl_barrier();
}
bool __in_29bit_mode(void)
{
return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
}
static int pmb_debugfs_show(struct seq_file *file, void *iter)
{
int i;
seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n"
"CB: Copy-Back, B: Buffered, UB: Unbuffered\n");
seq_printf(file, "ety vpn ppn size flags\n");
for (i = 0; i < NR_PMB_ENTRIES; i++) {
unsigned long addr, data;
unsigned int size;
char *sz_str = NULL;
addr = __raw_readl(mk_pmb_addr(i));
data = __raw_readl(mk_pmb_data(i));
size = data & PMB_SZ_MASK;
sz_str = (size == PMB_SZ_16M) ? " 16MB":
(size == PMB_SZ_64M) ? " 64MB":
(size == PMB_SZ_128M) ? "128MB":
"512MB";
/* 02: V 0x88 0x08 128MB C CB B */
seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n",
i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ',
(addr >> 24) & 0xff, (data >> 24) & 0xff,
sz_str, (data & PMB_C) ? 'C' : ' ',
(data & PMB_WT) ? "WT" : "CB",
(data & PMB_UB) ? "UB" : " B");
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pmb_debugfs);
static int __init pmb_debugfs_init(void)
{
debugfs_create_file("pmb", S_IFREG | S_IRUGO, arch_debugfs_dir, NULL,
&pmb_debugfs_fops);
return 0;
}
subsys_initcall(pmb_debugfs_init);
#ifdef CONFIG_PM
static void pmb_syscore_resume(void)
{
struct pmb_entry *pmbe;
int i;
read_lock(&pmb_rwlock);
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
if (test_bit(i, pmb_map)) {
pmbe = &pmb_entry_list[i];
set_pmb_entry(pmbe);
}
}
read_unlock(&pmb_rwlock);
}
static struct syscore_ops pmb_syscore_ops = {
.resume = pmb_syscore_resume,
};
static int __init pmb_sysdev_init(void)
{
register_syscore_ops(&pmb_syscore_ops);
return 0;
}
subsys_initcall(pmb_sysdev_init);
#endif
| linux-master | arch/sh/mm/pmb.c |
/*
* Page fault handler for SH with an MMU.
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 - 2012 Paul Mundt
*
* Based on linux/arch/i386/mm/fault.c:
* Copyright (C) 1995 Linus Torvalds
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/sched/signal.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
#include <linux/perf_event.h>
#include <linux/kdebug.h>
#include <linux/uaccess.h>
#include <asm/io_trapped.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/traps.h>
static void
force_sig_info_fault(int si_signo, int si_code, unsigned long address)
{
force_sig_fault(si_signo, si_code, (void __user *)address);
}
/*
* This is useful to dump out the page tables associated with
* 'addr' in mm 'mm'.
*/
static void show_pte(struct mm_struct *mm, unsigned long addr)
{
pgd_t *pgd;
if (mm) {
pgd = mm->pgd;
} else {
pgd = get_TTB();
if (unlikely(!pgd))
pgd = swapper_pg_dir;
}
pr_alert("pgd = %p\n", pgd);
pgd += pgd_index(addr);
pr_alert("[%08lx] *pgd=%0*llx", addr, (u32)(sizeof(*pgd) * 2),
(u64)pgd_val(*pgd));
do {
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
if (pgd_none(*pgd))
break;
if (pgd_bad(*pgd)) {
pr_cont("(bad)");
break;
}
p4d = p4d_offset(pgd, addr);
if (PTRS_PER_P4D != 1)
pr_cont(", *p4d=%0*Lx", (u32)(sizeof(*p4d) * 2),
(u64)p4d_val(*p4d));
if (p4d_none(*p4d))
break;
if (p4d_bad(*p4d)) {
pr_cont("(bad)");
break;
}
pud = pud_offset(p4d, addr);
if (PTRS_PER_PUD != 1)
pr_cont(", *pud=%0*llx", (u32)(sizeof(*pud) * 2),
(u64)pud_val(*pud));
if (pud_none(*pud))
break;
if (pud_bad(*pud)) {
pr_cont("(bad)");
break;
}
pmd = pmd_offset(pud, addr);
if (PTRS_PER_PMD != 1)
pr_cont(", *pmd=%0*llx", (u32)(sizeof(*pmd) * 2),
(u64)pmd_val(*pmd));
if (pmd_none(*pmd))
break;
if (pmd_bad(*pmd)) {
pr_cont("(bad)");
break;
}
/* We must not map this if we have highmem enabled */
if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT)))
break;
pte = pte_offset_kernel(pmd, addr);
pr_cont(", *pte=%0*llx", (u32)(sizeof(*pte) * 2),
(u64)pte_val(*pte));
} while (0);
pr_cont("\n");
}
static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address)
{
unsigned index = pgd_index(address);
pgd_t *pgd_k;
p4d_t *p4d, *p4d_k;
pud_t *pud, *pud_k;
pmd_t *pmd, *pmd_k;
pgd += index;
pgd_k = init_mm.pgd + index;
if (!pgd_present(*pgd_k))
return NULL;
p4d = p4d_offset(pgd, address);
p4d_k = p4d_offset(pgd_k, address);
if (!p4d_present(*p4d_k))
return NULL;
pud = pud_offset(p4d, address);
pud_k = pud_offset(p4d_k, address);
if (!pud_present(*pud_k))
return NULL;
if (!pud_present(*pud))
set_pud(pud, *pud_k);
pmd = pmd_offset(pud, address);
pmd_k = pmd_offset(pud_k, address);
if (!pmd_present(*pmd_k))
return NULL;
if (!pmd_present(*pmd))
set_pmd(pmd, *pmd_k);
else {
/*
* The page tables are fully synchronised so there must
* be another reason for the fault. Return NULL here to
* signal that we have not taken care of the fault.
*/
BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k));
return NULL;
}
return pmd_k;
}
#ifdef CONFIG_SH_STORE_QUEUES
#define __FAULT_ADDR_LIMIT P3_ADDR_MAX
#else
#define __FAULT_ADDR_LIMIT VMALLOC_END
#endif
/*
* Handle a fault on the vmalloc or module mapping area
*/
static noinline int vmalloc_fault(unsigned long address)
{
pgd_t *pgd_k;
pmd_t *pmd_k;
pte_t *pte_k;
/* Make sure we are in vmalloc/module/P3 area: */
if (!(address >= VMALLOC_START && address < __FAULT_ADDR_LIMIT))
return -1;
/*
* Synchronize this task's top level page-table
* with the 'reference' page table.
*
* Do _not_ use "current" here. We might be inside
* an interrupt in the middle of a task switch..
*/
pgd_k = get_TTB();
pmd_k = vmalloc_sync_one(pgd_k, address);
if (!pmd_k)
return -1;
pte_k = pte_offset_kernel(pmd_k, address);
if (!pte_present(*pte_k))
return -1;
return 0;
}
static void
show_fault_oops(struct pt_regs *regs, unsigned long address)
{
if (!oops_may_print())
return;
pr_alert("BUG: unable to handle kernel %s at %08lx\n",
address < PAGE_SIZE ? "NULL pointer dereference"
: "paging request",
address);
pr_alert("PC:");
printk_address(regs->pc, 1);
show_pte(NULL, address);
}
static noinline void
no_context(struct pt_regs *regs, unsigned long error_code,
unsigned long address)
{
/* Are we prepared to handle this kernel fault? */
if (fixup_exception(regs))
return;
if (handle_trapped_io(regs, address))
return;
/*
* Oops. The kernel tried to access some bad page. We'll have to
* terminate things with extreme prejudice.
*/
bust_spinlocks(1);
show_fault_oops(regs, address);
die("Oops", regs, error_code);
}
static void
__bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
unsigned long address, int si_code)
{
/* User mode accesses just cause a SIGSEGV */
if (user_mode(regs)) {
/*
* It's possible to have interrupts off here:
*/
local_irq_enable();
force_sig_info_fault(SIGSEGV, si_code, address);
return;
}
no_context(regs, error_code, address);
}
static noinline void
bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
unsigned long address)
{
__bad_area_nosemaphore(regs, error_code, address, SEGV_MAPERR);
}
static void
__bad_area(struct pt_regs *regs, unsigned long error_code,
unsigned long address, int si_code)
{
struct mm_struct *mm = current->mm;
/*
* Something tried to access memory that isn't in our memory map..
* Fix it, but check if it's kernel or user first..
*/
mmap_read_unlock(mm);
__bad_area_nosemaphore(regs, error_code, address, si_code);
}
static noinline void
bad_area(struct pt_regs *regs, unsigned long error_code, unsigned long address)
{
__bad_area(regs, error_code, address, SEGV_MAPERR);
}
static noinline void
bad_area_access_error(struct pt_regs *regs, unsigned long error_code,
unsigned long address)
{
__bad_area(regs, error_code, address, SEGV_ACCERR);
}
static void
do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address)
{
struct task_struct *tsk = current;
struct mm_struct *mm = tsk->mm;
mmap_read_unlock(mm);
/* Kernel mode? Handle exceptions or die: */
if (!user_mode(regs))
no_context(regs, error_code, address);
force_sig_info_fault(SIGBUS, BUS_ADRERR, address);
}
static noinline int
mm_fault_error(struct pt_regs *regs, unsigned long error_code,
unsigned long address, vm_fault_t fault)
{
/*
* Pagefault was interrupted by SIGKILL. We have no reason to
* continue pagefault.
*/
if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
no_context(regs, error_code, address);
return 1;
}
/* Release mmap_lock first if necessary */
if (!(fault & VM_FAULT_RETRY))
mmap_read_unlock(current->mm);
if (!(fault & VM_FAULT_ERROR))
return 0;
if (fault & VM_FAULT_OOM) {
/* Kernel mode? Handle exceptions or die: */
if (!user_mode(regs)) {
no_context(regs, error_code, address);
return 1;
}
/*
* We ran out of memory, call the OOM killer, and return the
* userspace (which will retry the fault, or kill us if we got
* oom-killed):
*/
pagefault_out_of_memory();
} else {
if (fault & VM_FAULT_SIGBUS)
do_sigbus(regs, error_code, address);
else if (fault & VM_FAULT_SIGSEGV)
bad_area(regs, error_code, address);
else
BUG();
}
return 1;
}
static inline int access_error(int error_code, struct vm_area_struct *vma)
{
if (error_code & FAULT_CODE_WRITE) {
/* write, present and write, not present: */
if (unlikely(!(vma->vm_flags & VM_WRITE)))
return 1;
return 0;
}
/* ITLB miss on NX page */
if (unlikely((error_code & FAULT_CODE_ITLB) &&
!(vma->vm_flags & VM_EXEC)))
return 1;
/* read, not present: */
if (unlikely(!vma_is_accessible(vma)))
return 1;
return 0;
}
static int fault_in_kernel_space(unsigned long address)
{
return address >= TASK_SIZE;
}
/*
* This routine handles page faults. It determines the address,
* and the problem, and then passes it off to one of the appropriate
* routines.
*/
asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
unsigned long error_code,
unsigned long address)
{
unsigned long vec;
struct task_struct *tsk;
struct mm_struct *mm;
struct vm_area_struct * vma;
vm_fault_t fault;
unsigned int flags = FAULT_FLAG_DEFAULT;
tsk = current;
mm = tsk->mm;
vec = lookup_exception_vector();
/*
* We fault-in kernel-space virtual memory on-demand. The
* 'reference' page table is init_mm.pgd.
*
* NOTE! We MUST NOT take any locks for this case. We may
* be in an interrupt or a critical region, and should
* only copy the information from the master page table,
* nothing more.
*/
if (unlikely(fault_in_kernel_space(address))) {
if (vmalloc_fault(address) >= 0)
return;
if (kprobe_page_fault(regs, vec))
return;
bad_area_nosemaphore(regs, error_code, address);
return;
}
if (unlikely(kprobe_page_fault(regs, vec)))
return;
/* Only enable interrupts if they were on before the fault */
if ((regs->sr & SR_IMASK) != SR_IMASK)
local_irq_enable();
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
/*
* If we're in an interrupt, have no user context or are running
* with pagefaults disabled then we must not take the fault:
*/
if (unlikely(faulthandler_disabled() || !mm)) {
bad_area_nosemaphore(regs, error_code, address);
return;
}
retry:
vma = lock_mm_and_find_vma(mm, address, regs);
if (unlikely(!vma)) {
bad_area_nosemaphore(regs, error_code, address);
return;
}
/*
* Ok, we have a good vm_area for this memory access, so
* we can handle it..
*/
if (unlikely(access_error(error_code, vma))) {
bad_area_access_error(regs, error_code, address);
return;
}
set_thread_fault_code(error_code);
if (user_mode(regs))
flags |= FAULT_FLAG_USER;
if (error_code & FAULT_CODE_WRITE)
flags |= FAULT_FLAG_WRITE;
/*
* If for any reason at all we couldn't handle the fault,
* make sure we exit gracefully rather than endlessly redo
* the fault.
*/
fault = handle_mm_fault(vma, address, flags, regs);
if (unlikely(fault & (VM_FAULT_RETRY | VM_FAULT_ERROR)))
if (mm_fault_error(regs, error_code, address, fault))
return;
/* The fault is fully completed (including releasing mmap lock) */
if (fault & VM_FAULT_COMPLETED)
return;
if (fault & VM_FAULT_RETRY) {
flags |= FAULT_FLAG_TRIED;
/*
* No need to mmap_read_unlock(mm) as we would
* have already released it in __lock_page_or_retry
* in mm/filemap.c.
*/
goto retry;
}
mmap_read_unlock(mm);
}
| linux-master | arch/sh/mm/fault.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/nommu.c
*
* Various helper routines and stubs for MMUless SH.
*
* Copyright (C) 2002 - 2009 Paul Mundt
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <asm/tlbflush.h>
#include <asm/page.h>
#include <linux/uaccess.h>
/*
* Nothing too terribly exciting here ..
*/
void copy_page(void *to, void *from)
{
memcpy(to, from, PAGE_SIZE);
}
__kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n)
{
memcpy(to, from, n);
return 0;
}
__kernel_size_t __clear_user(void __user *to, __kernel_size_t n)
{
memset((__force void *)to, 0, n);
return 0;
}
void local_flush_tlb_all(void)
{
BUG();
}
void local_flush_tlb_mm(struct mm_struct *mm)
{
BUG();
}
void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
BUG();
}
void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
BUG();
}
void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
BUG();
}
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
BUG();
}
void __flush_tlb_global(void)
{
}
void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
}
void __init kmap_coherent_init(void)
{
}
void *kmap_coherent(struct page *page, unsigned long addr)
{
BUG();
return NULL;
}
void kunmap_coherent(void *kvaddr)
{
BUG();
}
void __init page_table_range_init(unsigned long start, unsigned long end,
pgd_t *pgd_base)
{
}
void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
{
}
| linux-master | arch/sh/mm/nommu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/sh/mm/cache-sh3.c
*
* Copyright (C) 1999, 2000 Niibe Yutaka
* Copyright (C) 2002 Paul Mundt
*/
#include <linux/init.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/threads.h>
#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
/*
* Write back the dirty D-caches, but not invalidate them.
*
* Is this really worth it, or should we just alias this routine
* to __flush_purge_region too?
*
* START: Virtual Address (U0, P1, or P3)
* SIZE: Size of the region.
*/
static void sh3__flush_wback_region(void *start, int size)
{
unsigned long v, j;
unsigned long begin, end;
unsigned long flags;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY;
for (j = 0; j < current_cpu_data.dcache.ways; j++) {
unsigned long data, addr, p;
p = __pa(v);
addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
local_irq_save(flags);
data = __raw_readl(addr);
if ((data & CACHE_PHYSADDR_MASK) ==
(p & CACHE_PHYSADDR_MASK)) {
data &= ~SH_CACHE_UPDATED;
__raw_writel(data, addr);
local_irq_restore(flags);
break;
}
local_irq_restore(flags);
addrstart += current_cpu_data.dcache.way_incr;
}
}
}
/*
* Write back the dirty D-caches and invalidate them.
*
* START: Virtual Address (U0, P1, or P3)
* SIZE: Size of the region.
*/
static void sh3__flush_purge_region(void *start, int size)
{
unsigned long v;
unsigned long begin, end;
begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
& ~(L1_CACHE_BYTES-1);
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
unsigned long data, addr;
data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
addr = CACHE_OC_ADDRESS_ARRAY |
(v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
__raw_writel(data, addr);
}
}
void __init sh3_cache_init(void)
{
__flush_wback_region = sh3__flush_wback_region;
__flush_purge_region = sh3__flush_purge_region;
/*
* No write back please
*
* Except I don't think there's any way to avoid the writeback.
* So we just alias it to sh3__flush_purge_region(). dwmw2.
*/
__flush_invalidate_region = sh3__flush_purge_region;
}
| linux-master | arch/sh/mm/cache-sh3.c |
/*
* TLB flushing operations for SH with an MMU.
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/mm.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
unsigned int cpu = smp_processor_id();
if (vma->vm_mm && cpu_context(cpu, vma->vm_mm) != NO_CONTEXT) {
unsigned long flags;
unsigned long asid;
unsigned long saved_asid = MMU_NO_ASID;
asid = cpu_asid(cpu, vma->vm_mm);
page &= PAGE_MASK;
local_irq_save(flags);
if (vma->vm_mm != current->mm) {
saved_asid = get_asid();
set_asid(asid);
}
local_flush_tlb_one(asid, page);
if (saved_asid != MMU_NO_ASID)
set_asid(saved_asid);
local_irq_restore(flags);
}
}
void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
unsigned int cpu = smp_processor_id();
if (cpu_context(cpu, mm) != NO_CONTEXT) {
unsigned long flags;
int size;
local_irq_save(flags);
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
cpu_context(cpu, mm) = NO_CONTEXT;
if (mm == current->mm)
activate_context(mm, cpu);
} else {
unsigned long asid;
unsigned long saved_asid = MMU_NO_ASID;
asid = cpu_asid(cpu, mm);
start &= PAGE_MASK;
end += (PAGE_SIZE - 1);
end &= PAGE_MASK;
if (mm != current->mm) {
saved_asid = get_asid();
set_asid(asid);
}
while (start < end) {
local_flush_tlb_one(asid, start);
start += PAGE_SIZE;
}
if (saved_asid != MMU_NO_ASID)
set_asid(saved_asid);
}
local_irq_restore(flags);
}
}
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
unsigned int cpu = smp_processor_id();
unsigned long flags;
int size;
local_irq_save(flags);
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
local_flush_tlb_all();
} else {
unsigned long asid;
unsigned long saved_asid = get_asid();
asid = cpu_asid(cpu, &init_mm);
start &= PAGE_MASK;
end += (PAGE_SIZE - 1);
end &= PAGE_MASK;
set_asid(asid);
while (start < end) {
local_flush_tlb_one(asid, start);
start += PAGE_SIZE;
}
set_asid(saved_asid);
}
local_irq_restore(flags);
}
void local_flush_tlb_mm(struct mm_struct *mm)
{
unsigned int cpu = smp_processor_id();
/* Invalidate all TLB of this process. */
/* Instead of invalidating each TLB, we get new MMU context. */
if (cpu_context(cpu, mm) != NO_CONTEXT) {
unsigned long flags;
local_irq_save(flags);
cpu_context(cpu, mm) = NO_CONTEXT;
if (mm == current->mm)
activate_context(mm, cpu);
local_irq_restore(flags);
}
}
void __flush_tlb_global(void)
{
unsigned long flags;
local_irq_save(flags);
/*
* This is the most destructive of the TLB flushing options,
* and will tear down all of the UTLB/ITLB mappings, including
* wired entries.
*/
__raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
local_irq_restore(flags);
}
| linux-master | arch/sh/mm/tlbflush_32.c |
/*
* debugfs ops for the L1 cache
*
* Copyright (C) 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <asm/processor.h>
#include <linux/uaccess.h>
#include <asm/cache.h>
#include <asm/io.h>
enum cache_type {
CACHE_TYPE_ICACHE,
CACHE_TYPE_DCACHE,
CACHE_TYPE_UNIFIED,
};
static int cache_debugfs_show(struct seq_file *file, void *iter)
{
unsigned int cache_type = (unsigned int)file->private;
struct cache_info *cache;
unsigned int waysize, way;
unsigned long ccr;
unsigned long addrstart = 0;
/*
* Go uncached immediately so we don't skew the results any
* more than we already are..
*/
jump_to_uncached();
ccr = __raw_readl(SH_CCR);
if ((ccr & CCR_CACHE_ENABLE) == 0) {
back_to_cached();
seq_printf(file, "disabled\n");
return 0;
}
if (cache_type == CACHE_TYPE_DCACHE) {
addrstart = CACHE_OC_ADDRESS_ARRAY;
cache = ¤t_cpu_data.dcache;
} else {
addrstart = CACHE_IC_ADDRESS_ARRAY;
cache = ¤t_cpu_data.icache;
}
waysize = cache->sets;
/*
* If the OC is already in RAM mode, we only have
* half of the entries to consider..
*/
if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
waysize >>= 1;
waysize <<= cache->entry_shift;
for (way = 0; way < cache->ways; way++) {
unsigned long addr;
unsigned int line;
seq_printf(file, "-----------------------------------------\n");
seq_printf(file, "Way %d\n", way);
seq_printf(file, "-----------------------------------------\n");
for (addr = addrstart, line = 0;
addr < addrstart + waysize;
addr += cache->linesz, line++) {
unsigned long data = __raw_readl(addr);
/* Check the V bit, ignore invalid cachelines */
if ((data & 1) == 0)
continue;
/* U: Dirty, cache tag is 10 bits up */
seq_printf(file, "%3d: %c 0x%lx\n",
line, data & 2 ? 'U' : ' ',
data & 0x1ffffc00);
}
addrstart += cache->way_incr;
}
back_to_cached();
return 0;
}
DEFINE_SHOW_ATTRIBUTE(cache_debugfs);
static int __init cache_debugfs_init(void)
{
debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
(void *)CACHE_TYPE_DCACHE, &cache_debugfs_fops);
debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
(void *)CACHE_TYPE_ICACHE, &cache_debugfs_fops);
return 0;
}
module_init(cache_debugfs_init);
MODULE_LICENSE("GPL v2");
| linux-master | arch/sh/mm/cache-debugfs.c |
/*
* arch/sh/mm/tlb-debugfs.c
*
* debugfs ops for SH-4 ITLB/UTLBs.
*
* Copyright (C) 2010 Matt Fleming
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <asm/processor.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
enum tlb_type {
TLB_TYPE_ITLB,
TLB_TYPE_UTLB,
};
static struct {
int bits;
const char *size;
} tlb_sizes[] = {
{ 0x0, " 1KB" },
{ 0x1, " 4KB" },
{ 0x2, " 8KB" },
{ 0x4, " 64KB" },
{ 0x5, "256KB" },
{ 0x7, " 1MB" },
{ 0x8, " 4MB" },
{ 0xc, " 64MB" },
};
static int tlb_seq_show(struct seq_file *file, void *iter)
{
unsigned int tlb_type = (unsigned int)file->private;
unsigned long addr1, addr2, data1, data2;
unsigned long flags;
unsigned long mmucr;
unsigned int nentries, entry;
unsigned int urb;
mmucr = __raw_readl(MMUCR);
if ((mmucr & 0x1) == 0) {
seq_printf(file, "address translation disabled\n");
return 0;
}
if (tlb_type == TLB_TYPE_ITLB) {
addr1 = MMU_ITLB_ADDRESS_ARRAY;
addr2 = MMU_ITLB_ADDRESS_ARRAY2;
data1 = MMU_ITLB_DATA_ARRAY;
data2 = MMU_ITLB_DATA_ARRAY2;
nentries = 4;
} else {
addr1 = MMU_UTLB_ADDRESS_ARRAY;
addr2 = MMU_UTLB_ADDRESS_ARRAY2;
data1 = MMU_UTLB_DATA_ARRAY;
data2 = MMU_UTLB_DATA_ARRAY2;
nentries = 64;
}
local_irq_save(flags);
jump_to_uncached();
urb = (mmucr & MMUCR_URB) >> MMUCR_URB_SHIFT;
/* Make the "entry >= urb" test fail. */
if (urb == 0)
urb = MMUCR_URB_NENTRIES + 1;
if (tlb_type == TLB_TYPE_ITLB) {
addr1 = MMU_ITLB_ADDRESS_ARRAY;
addr2 = MMU_ITLB_ADDRESS_ARRAY2;
data1 = MMU_ITLB_DATA_ARRAY;
data2 = MMU_ITLB_DATA_ARRAY2;
nentries = 4;
} else {
addr1 = MMU_UTLB_ADDRESS_ARRAY;
addr2 = MMU_UTLB_ADDRESS_ARRAY2;
data1 = MMU_UTLB_DATA_ARRAY;
data2 = MMU_UTLB_DATA_ARRAY2;
nentries = 64;
}
seq_printf(file, "entry: vpn ppn asid size valid wired\n");
for (entry = 0; entry < nentries; entry++) {
unsigned long vpn, ppn, asid, size;
unsigned long valid;
unsigned long val;
const char *sz = " ?";
int i;
val = __raw_readl(addr1 | (entry << MMU_TLB_ENTRY_SHIFT));
ctrl_barrier();
vpn = val & 0xfffffc00;
valid = val & 0x100;
val = __raw_readl(addr2 | (entry << MMU_TLB_ENTRY_SHIFT));
ctrl_barrier();
asid = val & MMU_CONTEXT_ASID_MASK;
val = __raw_readl(data1 | (entry << MMU_TLB_ENTRY_SHIFT));
ctrl_barrier();
ppn = (val & 0x0ffffc00) << 4;
val = __raw_readl(data2 | (entry << MMU_TLB_ENTRY_SHIFT));
ctrl_barrier();
size = (val & 0xf0) >> 4;
for (i = 0; i < ARRAY_SIZE(tlb_sizes); i++) {
if (tlb_sizes[i].bits == size)
break;
}
if (i != ARRAY_SIZE(tlb_sizes))
sz = tlb_sizes[i].size;
seq_printf(file, "%2d: 0x%08lx 0x%08lx %5lu %s %s %s\n",
entry, vpn, ppn, asid,
sz, valid ? "V" : "-",
(urb <= entry) ? "W" : "-");
}
back_to_cached();
local_irq_restore(flags);
return 0;
}
static int tlb_debugfs_open(struct inode *inode, struct file *file)
{
return single_open(file, tlb_seq_show, inode->i_private);
}
static const struct file_operations tlb_debugfs_fops = {
.owner = THIS_MODULE,
.open = tlb_debugfs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init tlb_debugfs_init(void)
{
debugfs_create_file("itlb", S_IRUSR, arch_debugfs_dir,
(void *)TLB_TYPE_ITLB, &tlb_debugfs_fops);
debugfs_create_file("utlb", S_IRUSR, arch_debugfs_dir,
(void *)TLB_TYPE_UTLB, &tlb_debugfs_fops);
return 0;
}
module_init(tlb_debugfs_init);
MODULE_LICENSE("GPL v2");
| linux-master | arch/sh/mm/tlb-debugfs.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/sh/mm/extable.c
* Taken from:
* linux/arch/i386/mm/extable.c
*/
#include <linux/extable.h>
#include <linux/uaccess.h>
#include <asm/ptrace.h>
int fixup_exception(struct pt_regs *regs)
{
const struct exception_table_entry *fixup;
fixup = search_exception_tables(regs->pc);
if (fixup) {
regs->pc = fixup->fixup;
return 1;
}
return 0;
}
| linux-master | arch/sh/mm/extable_32.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2008 Matt Fleming <[email protected]>
* Copyright (C) 2008 Paul Mundt <[email protected]>
*
* Code for replacing ftrace calls with jumps.
*
* Copyright (C) 2007-2008 Steven Rostedt <[email protected]>
*
* Thanks goes to Ingo Molnar, for suggesting the idea.
* Mathieu Desnoyers, for suggesting postponing the modifications.
* Arjan van de Ven, for keeping me straight, and explaining to me
* the dangers of modifying code on the run.
*/
#include <linux/uaccess.h>
#include <linux/ftrace.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <asm/ftrace.h>
#include <asm/cacheflush.h>
#include <asm/unistd.h>
#include <trace/syscall.h>
#ifdef CONFIG_DYNAMIC_FTRACE
static unsigned char ftrace_replaced_code[MCOUNT_INSN_SIZE];
static unsigned char ftrace_nop[4];
/*
* If we're trying to nop out a call to a function, we instead
* place a call to the address after the memory table.
*
* 8c011060 <a>:
* 8c011060: 02 d1 mov.l 8c01106c <a+0xc>,r1
* 8c011062: 22 4f sts.l pr,@-r15
* 8c011064: 02 c7 mova 8c011070 <a+0x10>,r0
* 8c011066: 2b 41 jmp @r1
* 8c011068: 2a 40 lds r0,pr
* 8c01106a: 09 00 nop
* 8c01106c: 68 24 .word 0x2468 <--- ip
* 8c01106e: 1d 8c .word 0x8c1d
* 8c011070: 26 4f lds.l @r15+,pr <--- ip + MCOUNT_INSN_SIZE
*
* We write 0x8c011070 to 0x8c01106c so that on entry to a() we branch
* past the _mcount call and continue executing code like normal.
*/
static unsigned char *ftrace_nop_replace(unsigned long ip)
{
__raw_writel(ip + MCOUNT_INSN_SIZE, ftrace_nop);
return ftrace_nop;
}
static unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
{
/* Place the address in the memory table. */
__raw_writel(addr, ftrace_replaced_code);
/*
* No locking needed, this must be called via kstop_machine
* which in essence is like running on a uniprocessor machine.
*/
return ftrace_replaced_code;
}
/*
* Modifying code must take extra care. On an SMP machine, if
* the code being modified is also being executed on another CPU
* that CPU will have undefined results and possibly take a GPF.
* We use kstop_machine to stop other CPUS from executing code.
* But this does not stop NMIs from happening. We still need
* to protect against that. We separate out the modification of
* the code to take care of this.
*
* Two buffers are added: An IP buffer and a "code" buffer.
*
* 1) Put the instruction pointer into the IP buffer
* and the new code into the "code" buffer.
* 2) Wait for any running NMIs to finish and set a flag that says
* we are modifying code, it is done in an atomic operation.
* 3) Write the code
* 4) clear the flag.
* 5) Wait for any running NMIs to finish.
*
* If an NMI is executed, the first thing it does is to call
* "ftrace_nmi_enter". This will check if the flag is set to write
* and if it is, it will write what is in the IP and "code" buffers.
*
* The trick is, it does not matter if everyone is writing the same
* content to the code location. Also, if a CPU is executing code
* it is OK to write to that code location if the contents being written
* are the same as what exists.
*/
#define MOD_CODE_WRITE_FLAG (1 << 31) /* set when NMI should do the write */
static atomic_t nmi_running = ATOMIC_INIT(0);
static int mod_code_status; /* holds return value of text write */
static void *mod_code_ip; /* holds the IP to write to */
static void *mod_code_newcode; /* holds the text to write to the IP */
static void clear_mod_flag(void)
{
int old = atomic_read(&nmi_running);
for (;;) {
int new = old & ~MOD_CODE_WRITE_FLAG;
if (old == new)
break;
old = atomic_cmpxchg(&nmi_running, old, new);
}
}
static void ftrace_mod_code(void)
{
/*
* Yes, more than one CPU process can be writing to mod_code_status.
* (and the code itself)
* But if one were to fail, then they all should, and if one were
* to succeed, then they all should.
*/
mod_code_status = copy_to_kernel_nofault(mod_code_ip, mod_code_newcode,
MCOUNT_INSN_SIZE);
/* if we fail, then kill any new writers */
if (mod_code_status)
clear_mod_flag();
}
void arch_ftrace_nmi_enter(void)
{
if (atomic_inc_return(&nmi_running) & MOD_CODE_WRITE_FLAG) {
smp_rmb();
ftrace_mod_code();
}
/* Must have previous changes seen before executions */
smp_mb();
}
void arch_ftrace_nmi_exit(void)
{
/* Finish all executions before clearing nmi_running */
smp_mb();
atomic_dec(&nmi_running);
}
static void wait_for_nmi_and_set_mod_flag(void)
{
if (!atomic_cmpxchg(&nmi_running, 0, MOD_CODE_WRITE_FLAG))
return;
do {
cpu_relax();
} while (atomic_cmpxchg(&nmi_running, 0, MOD_CODE_WRITE_FLAG));
}
static void wait_for_nmi(void)
{
if (!atomic_read(&nmi_running))
return;
do {
cpu_relax();
} while (atomic_read(&nmi_running));
}
static int
do_ftrace_mod_code(unsigned long ip, void *new_code)
{
mod_code_ip = (void *)ip;
mod_code_newcode = new_code;
/* The buffers need to be visible before we let NMIs write them */
smp_mb();
wait_for_nmi_and_set_mod_flag();
/* Make sure all running NMIs have finished before we write the code */
smp_mb();
ftrace_mod_code();
/* Make sure the write happens before clearing the bit */
smp_mb();
clear_mod_flag();
wait_for_nmi();
return mod_code_status;
}
static int ftrace_modify_code(unsigned long ip, unsigned char *old_code,
unsigned char *new_code)
{
unsigned char replaced[MCOUNT_INSN_SIZE];
/*
* Note:
* We are paranoid about modifying text, as if a bug was to happen, it
* could cause us to read or write to someplace that could cause harm.
* Carefully read and modify the code with probe_kernel_*(), and make
* sure what we read is what we expected it to be before modifying it.
*/
/* read the text we want to modify */
if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE))
return -EFAULT;
/* Make sure it is what we expect it to be */
if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0)
return -EINVAL;
/* replace the text with the new text */
if (do_ftrace_mod_code(ip, new_code))
return -EPERM;
flush_icache_range(ip, ip + MCOUNT_INSN_SIZE);
return 0;
}
int ftrace_update_ftrace_func(ftrace_func_t func)
{
unsigned long ip = (unsigned long)(&ftrace_call) + MCOUNT_INSN_OFFSET;
unsigned char old[MCOUNT_INSN_SIZE], *new;
memcpy(old, (unsigned char *)ip, MCOUNT_INSN_SIZE);
new = ftrace_call_replace(ip, (unsigned long)func);
return ftrace_modify_code(ip, old, new);
}
int ftrace_make_nop(struct module *mod,
struct dyn_ftrace *rec, unsigned long addr)
{
unsigned char *new, *old;
unsigned long ip = rec->ip;
old = ftrace_call_replace(ip, addr);
new = ftrace_nop_replace(ip);
return ftrace_modify_code(rec->ip, old, new);
}
int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
{
unsigned char *new, *old;
unsigned long ip = rec->ip;
old = ftrace_nop_replace(ip);
new = ftrace_call_replace(ip, addr);
return ftrace_modify_code(rec->ip, old, new);
}
#endif /* CONFIG_DYNAMIC_FTRACE */
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
#ifdef CONFIG_DYNAMIC_FTRACE
extern void ftrace_graph_call(void);
static int ftrace_mod(unsigned long ip, unsigned long old_addr,
unsigned long new_addr)
{
unsigned char code[MCOUNT_INSN_SIZE];
if (copy_from_kernel_nofault(code, (void *)ip, MCOUNT_INSN_SIZE))
return -EFAULT;
if (old_addr != __raw_readl((unsigned long *)code))
return -EINVAL;
__raw_writel(new_addr, ip);
return 0;
}
int ftrace_enable_ftrace_graph_caller(void)
{
unsigned long ip, old_addr, new_addr;
ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET;
old_addr = (unsigned long)(&skip_trace);
new_addr = (unsigned long)(&ftrace_graph_caller);
return ftrace_mod(ip, old_addr, new_addr);
}
int ftrace_disable_ftrace_graph_caller(void)
{
unsigned long ip, old_addr, new_addr;
ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET;
old_addr = (unsigned long)(&ftrace_graph_caller);
new_addr = (unsigned long)(&skip_trace);
return ftrace_mod(ip, old_addr, new_addr);
}
#endif /* CONFIG_DYNAMIC_FTRACE */
/*
* Hook the return address and push it in the stack of return addrs
* in the current thread info.
*
* This is the main routine for the function graph tracer. The function
* graph tracer essentially works like this:
*
* parent is the stack address containing self_addr's return address.
* We pull the real return address out of parent and store it in
* current's ret_stack. Then, we replace the return address on the stack
* with the address of return_to_handler. self_addr is the function that
* called mcount.
*
* When self_addr returns, it will jump to return_to_handler which calls
* ftrace_return_to_handler. ftrace_return_to_handler will pull the real
* return address off of current's ret_stack and jump to it.
*/
void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
{
unsigned long old;
int faulted;
unsigned long return_hooker = (unsigned long)&return_to_handler;
if (unlikely(ftrace_graph_is_dead()))
return;
if (unlikely(atomic_read(¤t->tracing_graph_pause)))
return;
/*
* Protect against fault, even if it shouldn't
* happen. This tool is too much intrusive to
* ignore such a protection.
*/
__asm__ __volatile__(
"1: \n\t"
"mov.l @%2, %0 \n\t"
"2: \n\t"
"mov.l %3, @%2 \n\t"
"mov #0, %1 \n\t"
"3: \n\t"
".section .fixup, \"ax\" \n\t"
"4: \n\t"
"mov.l 5f, %0 \n\t"
"jmp @%0 \n\t"
" mov #1, %1 \n\t"
".balign 4 \n\t"
"5: .long 3b \n\t"
".previous \n\t"
".section __ex_table,\"a\" \n\t"
".long 1b, 4b \n\t"
".long 2b, 4b \n\t"
".previous \n\t"
: "=&r" (old), "=r" (faulted)
: "r" (parent), "r" (return_hooker)
);
if (unlikely(faulted)) {
ftrace_graph_stop();
WARN_ON(1);
return;
}
if (function_graph_enter(old, self_addr, 0, NULL))
__raw_writel(old, parent);
}
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
| linux-master | arch/sh/kernel/ftrace.c |
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